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diff --git a/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h7b3xxq.h b/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h7b3xxq.h
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1/**
2 ******************************************************************************
3 * @file stm32h7b3xxq.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32H7B3xxQ Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.</center></h2>
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26/** @addtogroup CMSIS_Device
27 * @{
28 */
29
30/** @addtogroup stm32h7b3xxq
31 * @{
32 */
33
34#ifndef STM32H7B3xxQ_H
35#define STM32H7B3xxQ_H
36
37#ifdef __cplusplus
38 extern "C" {
39#endif /* __cplusplus */
40
41/** @addtogroup Peripheral_interrupt_number_definition
42 * @{
43 */
44
45/**
46 * @brief STM32H7XX Interrupt Number Definition, according to the selected device
47 * in @ref Library_configuration_section
48 */
49typedef enum
50{
51/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
52 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
53 HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
54 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
55 BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
56 UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
57 SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
58 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
59 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
60 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
61/****** STM32 specific Interrupt Numbers **********************************************************************/
62 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
63 PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */
64 RTC_TAMP_STAMP_CSS_LSE_IRQn = 2, /*!< Tamper, TimeStamp, CSS and LSE interrupts through the EXTI line */
65 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
66 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
67 RCC_IRQn = 5, /*!< RCC global Interrupt */
68 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
69 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
70 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
71 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
72 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
73 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
74 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
75 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
76 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
77 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
78 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
79 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
80 ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
81 FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
82 FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
83 FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
84 FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
85 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
86 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
87 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
88 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
89 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
90 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
91 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
92 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
93 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
94 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
95 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
96 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
97 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
98 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
99 USART1_IRQn = 37, /*!< USART1 global Interrupt */
100 USART2_IRQn = 38, /*!< USART2 global Interrupt */
101 USART3_IRQn = 39, /*!< USART3 global Interrupt */
102 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
103 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
104 DFSDM2_IRQn = 42, /*!< DFSDM2 global Interrupt */
105 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
106 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
107 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
108 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
109 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
110 FMC_IRQn = 48, /*!< FMC global Interrupt */
111 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
112 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
113 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
114 UART4_IRQn = 52, /*!< UART4 global Interrupt */
115 UART5_IRQn = 53, /*!< UART5 global Interrupt */
116 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
117 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
118 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
119 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
120 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
121 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
122 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
123 FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
124 DFSDM1_FLT4_IRQn = 64, /*!< DFSDM Filter4 Interrupt */
125 DFSDM1_FLT5_IRQn = 65, /*!< DFSDM Filter5 Interrupt */
126 DFSDM1_FLT6_IRQn = 66, /*!< DFSDM Filter6 Interrupt */
127 DFSDM1_FLT7_IRQn = 67, /*!< DFSDM Filter7 Interrupt */
128 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
129 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
130 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
131 USART6_IRQn = 71, /*!< USART6 global interrupt */
132 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
133 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
134 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
135 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
136 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
137 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
138 DCMI_PSSI_IRQn = 78, /*!< DCMI and PSSI global interrupt */
139 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
140 HASH_RNG_IRQn = 80, /*!< HASH and RNG global interrupt */
141 FPU_IRQn = 81, /*!< FPU global interrupt */
142 UART7_IRQn = 82, /*!< UART7 global interrupt */
143 UART8_IRQn = 83, /*!< UART8 global interrupt */
144 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
145 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
146 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
147 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
148 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
149 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
150 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
151 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
152 OCTOSPI1_IRQn = 92, /*!< OCTOSPI1 global interrupt */
153 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
154 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
155 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
156 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
157 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
158 DMAMUX1_OVR_IRQn = 102, /*!<DMAMUX1 Overrun interrupt */
159 DFSDM1_FLT0_IRQn = 110, /*!<DFSDM Filter1 Interrupt */
160 DFSDM1_FLT1_IRQn = 111, /*!<DFSDM Filter2 Interrupt */
161 DFSDM1_FLT2_IRQn = 112, /*!<DFSDM Filter3 Interrupt */
162 DFSDM1_FLT3_IRQn = 113, /*!<DFSDM Filter4 Interrupt */
163 SWPMI1_IRQn = 115, /*!< Serial Wire Interface 1 global interrupt */
164 TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
165 TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
166 TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
167 MDIOS_WKUP_IRQn = 119, /*!< MDIOS Wakeup Interrupt */
168 MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
169 JPEG_IRQn = 121, /*!< JPEG global Interrupt */
170 MDMA_IRQn = 122, /*!< MDMA global Interrupt */
171 SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
172 HSEM1_IRQn = 125, /*!< HSEM1 global Interrupt */
173 DAC2_IRQn = 127, /*!< DAC2 global Interrupt */
174 DMAMUX2_OVR_IRQn = 128, /*!<DMAMUX2 Overrun interrupt */
175 BDMA2_Channel0_IRQn = 129, /*!< BDMA2 Channel 0 global Interrupt */
176 BDMA2_Channel1_IRQn = 130, /*!< BDMA2 Channel 1 global Interrupt */
177 BDMA2_Channel2_IRQn = 131, /*!< BDMA2 Channel 2 global Interrupt */
178 BDMA2_Channel3_IRQn = 132, /*!< BDMA2 Channel 3 global Interrupt */
179 BDMA2_Channel4_IRQn = 133, /*!< BDMA2 Channel 4 global Interrupt */
180 BDMA2_Channel5_IRQn = 134, /*!< BDMA2 Channel 5 global Interrupt */
181 BDMA2_Channel6_IRQn = 135, /*!< BDMA2 Channel 6 global Interrupt */
182 BDMA2_Channel7_IRQn = 136, /*!< BDMA2 Channel 7 global Interrupt */
183 COMP_IRQn = 137 , /*!< COMP global Interrupt */
184 LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
185 LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
186 UART9_IRQn = 140, /*!< UART9 global interrupt */
187 USART10_IRQn = 141, /*!< USART10 global interrupt */
188 LPUART1_IRQn = 142, /*!< LP UART1 interrupt */
189 WWDG_RST_IRQn = 143, /*!<Window Watchdog Event interrupt */
190 CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */
191 ECC_IRQn = 145, /*!< ECC diagnostic Global Interrupt */
192 DTS_IRQn = 147, /*!< Digital Temperature Sensor Global Interrupt */
193 WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
194 OCTOSPI2_IRQn = 150, /*!< OctoSPI2 global interrupt */
195 OTFDEC1_IRQn = 151, /*!< OTFDEC1 global interrupt */
196 OTFDEC2_IRQn = 152, /*!< OTFDEC2 global interrupt */
197 GFXMMU_IRQn = 153, /*!< GFXMMU global interrupt */
198 BDMA1_IRQn = 154, /*!< BDMA1 for DFSM global interrupt */
199} IRQn_Type;
200
201/**
202 * @}
203 */
204
205/** @addtogroup Configuration_section_for_CMSIS
206 * @{
207 */
208
209#define SMPS /*!< Switched mode power supply feature */
210
211
212
213/**
214 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
215 */
216#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
217#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
218#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
219#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
220#define __FPU_PRESENT 1 /*!< FPU present */
221#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
222#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
223#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
224
225/**
226 * @}
227 */
228
229
230
231
232#include "system_stm32h7xx.h"
233#include <stdint.h>
234
235/** @addtogroup Peripheral_registers_structures
236 * @{
237 */
238
239/**
240 * @brief Analog to Digital Converter
241 */
242
243typedef struct
244{
245 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
246 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
247 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
248 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
249 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
250 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
251 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
252 __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
253 __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
254 __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
255 uint32_t RESERVED1; /*!< Reserved, 0x028 */
256 uint32_t RESERVED2; /*!< Reserved, 0x02C */
257 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
258 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
259 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
260 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
261 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
262 uint32_t RESERVED3; /*!< Reserved, 0x044 */
263 uint32_t RESERVED4; /*!< Reserved, 0x048 */
264 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
265 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
266 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
267 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
268 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
269 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
270 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
271 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
272 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
273 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
274 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
275 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
276 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
277 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
278 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
279 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
280 __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
281 __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
282 __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
283 __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
284 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
285 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
286 __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
287} ADC_TypeDef;
288
289
290typedef struct
291{
292__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
293uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
294__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
295__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
296__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
297
298} ADC_Common_TypeDef;
299
300
301/**
302 * @brief VREFBUF
303 */
304
305typedef struct
306{
307 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
308 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
309} VREFBUF_TypeDef;
310
311
312/**
313 * @brief FD Controller Area Network
314 */
315
316typedef struct
317{
318 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
319 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
320 __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
321 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
322 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
323 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
324 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
325 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
326 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
327 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
328 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
329 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
330 __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
331 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
332 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
333 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
334 __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
335 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
336 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
337 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
338 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
339 __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
340 __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
341 __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
342 __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
343 __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
344 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
345 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
346 __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
347 __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
348 __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
349 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
350 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
351 __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
352 __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
353 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
354 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
355 __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
356 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
357 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
358 __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
359 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
360 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
361 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
362 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
363 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
364 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
365 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
366 __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
367 __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
368 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
369 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
370 __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
371} FDCAN_GlobalTypeDef;
372
373/**
374 * @brief TTFD Controller Area Network
375 */
376
377typedef struct
378{
379 __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
380 __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
381 __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
382 __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
383 __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
384 __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
385 __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
386 __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
387 __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
388 __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
389 __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
390 __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
391 __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
392 __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
393 __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
394 __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
395 __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
396 __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
397 __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
398} TTCAN_TypeDef;
399
400/**
401 * @brief FD Controller Area Network
402 */
403
404typedef struct
405{
406 __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
407 __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
408 __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
409 __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
410 __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
411 __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
412} FDCAN_ClockCalibrationUnit_TypeDef;
413
414
415/**
416 * @brief Consumer Electronics Control
417 */
418
419typedef struct
420{
421 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
422 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
423 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
424 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
425 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
426 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
427}CEC_TypeDef;
428
429/**
430 * @brief CRC calculation unit
431 */
432
433typedef struct
434{
435 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
436 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
437 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
438 uint32_t RESERVED2; /*!< Reserved, 0x0C */
439 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
440 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
441} CRC_TypeDef;
442
443
444/**
445 * @brief Clock Recovery System
446 */
447typedef struct
448{
449__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
450__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
451__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
452__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
453} CRS_TypeDef;
454
455
456/**
457 * @brief Digital to Analog Converter
458 */
459
460typedef struct
461{
462 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
463 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
464 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
465 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
466 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
467 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
468 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
469 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
470 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
471 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
472 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
473 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
474 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
475 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
476 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
477 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
478 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
479 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
480 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
481 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
482} DAC_TypeDef;
483
484/**
485 * @brief DFSDM module registers
486 */
487typedef struct
488{
489 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
490 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
491 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
492 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
493 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
494 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
495 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
496 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
497 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
498 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
499 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
500 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
501 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
502 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
503 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
504} DFSDM_Filter_TypeDef;
505
506/**
507 * @brief DFSDM channel configuration registers
508 */
509typedef struct
510{
511 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
512 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
513 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
514 short circuit detector register, Address offset: 0x08 */
515 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
516 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
517 __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */
518} DFSDM_Channel_TypeDef;
519
520/**
521 * @brief Debug MCU
522 */
523typedef struct
524{
525 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
526 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
527 uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
528 __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
529 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */
530 __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
531 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */
532 __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
533 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */
534 __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
535 uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */
536 __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
537}DBGMCU_TypeDef;
538/**
539 * @brief DCMI
540 */
541
542typedef struct
543{
544 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
545 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
546 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
547 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
548 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
549 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
550 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
551 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
552 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
553 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
554 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
555} DCMI_TypeDef;
556
557/**
558 * @brief PSSI
559 */
560
561typedef struct
562{
563 __IO uint32_t CR; /*!< PSSI control register 1, Address offset: 0x000 */
564 __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */
565 __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */
566 __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */
567 __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */
568 __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */
569 __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */
570 __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */
571 __IO uint32_t RESERVED2[241]; /*!< Reserved, 0x02C - 0x3EC */
572 __IO uint32_t HWCFGR; /*!< PSSI IP HW configuration register, Address offset: 0x3F0 */
573 __IO uint32_t VERR; /*!< PSSI IP version register, Address offset: 0x3F4 */
574 __IO uint32_t IPIDR; /*!< PSSI IP ID register, Address offset: 0x3F8 */
575 __IO uint32_t SIDR; /*!< PSSI SIZE ID register, Address offset: 0x3FC */
576} PSSI_TypeDef;
577
578/**
579 * @brief DMA Controller
580 */
581
582typedef struct
583{
584 __IO uint32_t CR; /*!< DMA stream x configuration register */
585 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
586 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
587 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
588 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
589 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
590} DMA_Stream_TypeDef;
591
592typedef struct
593{
594 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
595 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
596 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
597 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
598} DMA_TypeDef;
599
600typedef struct
601{
602 __IO uint32_t CCR; /*!< DMA channel x configuration register */
603 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
604 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
605 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */
606 __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */
607} BDMA_Channel_TypeDef;
608
609typedef struct
610{
611 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
612 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
613} BDMA_TypeDef;
614
615typedef struct
616{
617 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
618}DMAMUX_Channel_TypeDef;
619
620typedef struct
621{
622 __IO uint32_t CSR; /*!< DMA Channel Status Register */
623 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
624}DMAMUX_ChannelStatus_TypeDef;
625
626typedef struct
627{
628 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
629}DMAMUX_RequestGen_TypeDef;
630
631typedef struct
632{
633 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
634 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
635}DMAMUX_RequestGenStatus_TypeDef;
636
637/**
638 * @brief MDMA Controller
639 */
640typedef struct
641{
642 __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
643}MDMA_TypeDef;
644
645typedef struct
646{
647 __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
648 __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
649 __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
650 __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
651 __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
652 __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
653 __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
654 __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
655 __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
656 __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
657 __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
658 uint32_t RESERVED0; /*!< Reserved, 0x68 */
659 __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
660 __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
661}MDMA_Channel_TypeDef;
662
663/**
664 * @brief DMA2D Controller
665 */
666
667typedef struct
668{
669 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
670 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
671 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
672 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
673 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
674 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
675 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
676 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
677 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
678 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
679 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
680 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
681 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
682 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
683 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
684 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
685 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
686 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
687 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
688 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
689 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
690 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
691 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
692} DMA2D_TypeDef;
693
694
695/**
696 * @brief External Interrupt/Event Controller
697 */
698
699typedef struct
700{
701__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
702__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
703__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
704__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
705__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */
706__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */
707uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */
708__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
709__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
710__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
711__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
712__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */
713__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
714uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */
715__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
716__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
717__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
718__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
719__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
720__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
721uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */
722__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */
723__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */
724__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */
725uint32_t RESERVED4; /*!< Reserved, 0x8C */
726__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */
727__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */
728__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */
729uint32_t RESERVED5; /*!< Reserved, 0x9C */
730__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */
731__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */
732__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
733}EXTI_TypeDef;
734
735typedef struct
736{
737__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
738__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
739__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
740uint32_t RESERVED1; /*!< Reserved, 0x0C */
741__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
742__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
743__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
744uint32_t RESERVED2; /*!< Reserved, 0x1C */
745__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
746__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
747__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
748}EXTI_Core_TypeDef;
749
750
751/**
752 * @brief FLASH Registers
753 */
754
755typedef struct
756{
757 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
758 __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
759 __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
760 __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
761 __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
762 __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
763 __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
764 __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
765 __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */
766 __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
767 __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
768 __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
769 __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
770 __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */
771 __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
772 __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
773 __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
774 __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
775 uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */
776 __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
777 __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
778 __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
779 __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
780 __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
781 uint32_t RESERVED; /*!< Reserved, 0x64 */
782 __IO uint32_t OTPBL_CUR; /*!< Flash Current OTP Block Lock Register, Address offset: 0x68 */
783 __IO uint32_t OTPBL_PRG; /*!< Flash OTP Block Lock to Program Register, Address offset: 0x6C */
784 uint32_t RESERVED1[37]; /*!< Reserved, 0x70 to 0x100 */
785 __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
786 uint32_t RESERVED2; /*!< Reserved, 0x108 */
787 __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
788 __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
789 __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
790 uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
791 __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
792 __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
793 __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
794 __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
795 __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
796 __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
797 uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
798 __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
799 __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
800 __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
801 __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
802 __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
803} FLASH_TypeDef;
804
805/**
806 * @brief Flexible Memory Controller
807 */
808
809typedef struct
810{
811 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
812} FMC_Bank1_TypeDef;
813
814/**
815 * @brief Flexible Memory Controller Bank1E
816 */
817
818typedef struct
819{
820 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
821} FMC_Bank1E_TypeDef;
822
823/**
824 * @brief Flexible Memory Controller Bank2
825 */
826
827typedef struct
828{
829 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
830 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
831 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
832 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
833 uint32_t RESERVED0; /*!< Reserved, 0x70 */
834 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
835} FMC_Bank2_TypeDef;
836
837/**
838 * @brief Flexible Memory Controller Bank3
839 */
840
841typedef struct
842{
843 __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
844 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
845 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
846 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
847 uint32_t RESERVED; /*!< Reserved, 0x90 */
848 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
849} FMC_Bank3_TypeDef;
850
851/**
852 * @brief Flexible Memory Controller Bank5 and 6
853 */
854
855
856typedef struct
857{
858 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
859 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
860 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
861 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
862 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
863} FMC_Bank5_6_TypeDef;
864
865/**
866 * @brief GFXMMU registers
867 */
868
869typedef struct
870{
871 __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */
872 __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */
873 __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */
874 __IO uint32_t CCR; /*!< GFXMMU Cache Control Register, Address offset: 0x0C */
875 __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */
876 uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */
877 __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */
878 __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
879 __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
880 __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
881 uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */
882 __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */
883 __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */
884 __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */
885 __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */
886 __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
887 For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
888} GFXMMU_TypeDef;
889/**
890 * @brief General Purpose I/O
891 */
892
893typedef struct
894{
895 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
896 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
897 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
898 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
899 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
900 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
901 __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */
902 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
903 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
904} GPIO_TypeDef;
905
906/**
907 * @brief Operational Amplifier (OPAMP)
908 */
909
910typedef struct
911{
912 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
913 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
914 __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
915} OPAMP_TypeDef;
916
917/**
918 * @brief System configuration controller
919 */
920
921typedef struct
922{
923 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
924 __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
925 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
926 __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */
927 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
928 __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
929 __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
930 __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
931
932} SYSCFG_TypeDef;
933
934/**
935 * @brief Inter-integrated Circuit Interface
936 */
937
938typedef struct
939{
940 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
941 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
942 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
943 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
944 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
945 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
946 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
947 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
948 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
949 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
950 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
951} I2C_TypeDef;
952
953/**
954 * @brief Independent WATCHDOG
955 */
956
957typedef struct
958{
959 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
960 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
961 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
962 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
963 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
964} IWDG_TypeDef;
965
966
967/**
968 * @brief JPEG Codec
969 */
970typedef struct
971{
972 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
973 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
974 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
975 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
976 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
977 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
978 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
979 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
980 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
981 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
982 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
983 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
984 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
985 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
986 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
987 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
988 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
989 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
990 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
991 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
992 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
993 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
994 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
995 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
996 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
997 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
998 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
999 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
1000 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
1001
1002} JPEG_TypeDef;
1003
1004/**
1005 * @brief LCD-TFT Display Controller
1006 */
1007
1008typedef struct
1009{
1010 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
1011 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
1012 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
1013 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
1014 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
1015 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
1016 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
1017 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
1018 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
1019 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
1020 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
1021 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
1022 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
1023 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
1024 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
1025 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
1026 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
1027} LTDC_TypeDef;
1028
1029/**
1030 * @brief LCD-TFT Display layer x Controller
1031 */
1032
1033typedef struct
1034{
1035 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
1036 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
1037 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
1038 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
1039 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
1040 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
1041 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
1042 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
1043 uint32_t RESERVED0[2]; /*!< Reserved */
1044 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
1045 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
1046 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
1047 uint32_t RESERVED1[3]; /*!< Reserved */
1048 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
1049
1050} LTDC_Layer_TypeDef;
1051
1052/**
1053 * @brief Power Control
1054 */
1055
1056typedef struct
1057{
1058 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
1059 __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
1060 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
1061 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
1062 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
1063 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
1064 __IO uint32_t SRDCR; /*!< PWR SRD domain control register, Address offset: 0x18 */
1065 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
1066 __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
1067 __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
1068 __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
1069} PWR_TypeDef;
1070
1071/**
1072 * @brief Reset and Clock Control
1073 */
1074
1075typedef struct
1076{
1077 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
1078 __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */
1079 __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
1080 __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */
1081 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
1082 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
1083 __IO uint32_t CDCFGR1; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
1084 __IO uint32_t CDCFGR2; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
1085 __IO uint32_t SRDCFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
1086 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
1087 __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
1088 __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
1089 __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
1090 __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
1091 __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
1092 __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
1093 __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
1094 __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
1095 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
1096 __IO uint32_t CDCCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
1097 __IO uint32_t CDCCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
1098 __IO uint32_t CDCCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
1099 __IO uint32_t SRDCCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
1100 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
1101 __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
1102 __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
1103 __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
1104 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
1105 __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
1106 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
1107 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
1108 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
1109 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
1110 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
1111 __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
1112 __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
1113 __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
1114 __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
1115 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
1116 __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
1117 uint32_t RESERVED7; /*!< Reserved, Address offset: 0xA0 */
1118 uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */
1119 __IO uint32_t SRDAMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
1120 uint32_t RESERVED9; /*!< Reserved, 0xAC-0xAF Address offset: 0xAC */
1121 __IO uint32_t CKGAENR; /*!< AXI Clocks Gating Enable Register, Address offset: 0xB0 */
1122 uint32_t RESERVED10[31]; /*!< Reserved, 0xAC-0xAF Address offset: 0xAC */
1123 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
1124 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
1125 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
1126 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
1127 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
1128 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
1129 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
1130 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
1131 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
1132 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
1133 uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */
1134 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
1135 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
1136 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
1137 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
1138 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
1139 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
1140 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
1141 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
1142 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
1143 uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
1144
1145} RCC_TypeDef;
1146
1147
1148/**
1149 * @brief Real-Time Clock
1150 */
1151typedef struct
1152{
1153 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
1154 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
1155 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
1156 __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
1157 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
1158 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
1159 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
1160 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */
1161 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */
1162 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
1163 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
1164 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
1165 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
1166 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
1167 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
1168 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */
1169 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
1170 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
1171 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
1172 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
1173 __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
1174 __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
1175 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */
1176 __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */
1177 __IO uint32_t CFGR; /*!< RTC configuration register, Address offset: 0x60 */
1178} RTC_TypeDef;
1179
1180/**
1181 * @brief Tamper and backup registers
1182 */
1183typedef struct
1184{
1185 __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
1186 __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
1187 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x08 */
1188 __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
1189 __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */
1190 __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */
1191 __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */
1192 uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x1C -- 0x28 */
1193 __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */
1194 __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */
1195 __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */
1196 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x38 */
1197 __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
1198 __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
1199 uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x44 -- 0x4C */
1200 __IO uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x50 */
1201 uint32_t RESERVED4[43]; /*!< Reserved, Address offset: 0x54 -- 0xFC */
1202 __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
1203 __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
1204 __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
1205 __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
1206 __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
1207 __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
1208 __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
1209 __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
1210 __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
1211 __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
1212 __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
1213 __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
1214 __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
1215 __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
1216 __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
1217 __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
1218 __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
1219 __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
1220 __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
1221 __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
1222 __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
1223 __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
1224 __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
1225 __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
1226 __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
1227 __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
1228 __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
1229 __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
1230 __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
1231 __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
1232 __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
1233 __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
1234} TAMP_TypeDef;
1235
1236/**
1237 * @brief Serial Audio Interface
1238 */
1239
1240typedef struct
1241{
1242 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
1243 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
1244 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
1245 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
1246} SAI_TypeDef;
1247
1248typedef struct
1249{
1250 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
1251 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
1252 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
1253 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
1254 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
1255 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
1256 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
1257 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
1258} SAI_Block_TypeDef;
1259
1260/**
1261 * @brief SPDIF-RX Interface
1262 */
1263
1264typedef struct
1265{
1266 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
1267 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
1268 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
1269 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
1270 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
1271 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
1272 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
1273 uint32_t RESERVED2; /*!< Reserved, 0x1A */
1274} SPDIFRX_TypeDef;
1275
1276
1277/**
1278 * @brief Secure digital input/output Interface
1279 */
1280
1281typedef struct
1282{
1283 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
1284 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
1285 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
1286 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
1287 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
1288 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
1289 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
1290 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
1291 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
1292 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
1293 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
1294 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
1295 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
1296 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
1297 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
1298 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
1299 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
1300 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
1301 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
1302 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
1303 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
1304 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
1305 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
1306 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
1307 uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
1308 __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
1309} SDMMC_TypeDef;
1310
1311
1312/**
1313 * @brief Delay Block DLYB
1314 */
1315
1316typedef struct
1317{
1318 __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
1319 __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
1320} DLYB_TypeDef;
1321
1322/**
1323 * @brief HW Semaphore HSEM
1324 */
1325
1326typedef struct
1327{
1328 __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
1329 __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
1330 __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */
1331 __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */
1332 __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */
1333 __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */
1334 uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */
1335 __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
1336 __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
1337
1338} HSEM_TypeDef;
1339
1340typedef struct
1341{
1342 __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
1343 __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
1344 __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
1345 __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
1346} HSEM_Common_TypeDef;
1347
1348/**
1349 * @brief Serial Peripheral Interface
1350 */
1351
1352typedef struct
1353{
1354 __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
1355 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
1356 __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
1357 __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
1358 __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */
1359 __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */
1360 __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
1361 uint32_t RESERVED0; /*!< Reserved, 0x1C */
1362 __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */
1363 uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
1364 __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */
1365 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
1366 __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
1367 __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
1368 __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
1369 __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
1370 __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */
1371
1372} SPI_TypeDef;
1373
1374/**
1375 * @brief DTS
1376 */
1377typedef struct
1378{
1379 __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */
1380 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */
1381 __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */
1382 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */
1383 __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */
1384 __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */
1385 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
1386 __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */
1387 __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */
1388 __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */
1389 __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */
1390 __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */
1391}
1392DTS_TypeDef;
1393
1394/**
1395 * @brief TIM
1396 */
1397
1398typedef struct
1399{
1400 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
1401 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
1402 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
1403 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
1404 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
1405 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
1406 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
1407 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
1408 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
1409 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
1410 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
1411 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1412 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
1413 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
1414 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
1415 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
1416 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
1417 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1418 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
1419 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
1420 uint32_t RESERVED1; /*!< Reserved, 0x50 */
1421 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
1422 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
1423 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
1424 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
1425 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
1426 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
1427} TIM_TypeDef;
1428
1429/**
1430 * @brief LPTIMIMER
1431 */
1432typedef struct
1433{
1434 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
1435 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
1436 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
1437 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
1438 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
1439 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
1440 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
1441 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
1442 uint32_t RESERVED1; /*!< Reserved, 0x20 */
1443 __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */
1444} LPTIM_TypeDef;
1445
1446/**
1447 * @brief Comparator
1448 */
1449typedef struct
1450{
1451 __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
1452 __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
1453 __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
1454} COMPOPT_TypeDef;
1455
1456typedef struct
1457{
1458 __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
1459} COMP_TypeDef;
1460
1461typedef struct
1462{
1463 __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
1464} COMP_Common_TypeDef;
1465/**
1466 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1467 */
1468
1469typedef struct
1470{
1471 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1472 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1473 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1474 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1475 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1476 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1477 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
1478 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1479 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1480 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1481 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1482 __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
1483} USART_TypeDef;
1484
1485/**
1486 * @brief Single Wire Protocol Master Interface SPWMI
1487 */
1488typedef struct
1489{
1490 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
1491 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
1492 uint32_t RESERVED1; /*!< Reserved, 0x08 */
1493 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
1494 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
1495 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
1496 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
1497 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
1498 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
1499 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
1500} SWPMI_TypeDef;
1501
1502/**
1503 * @brief Window WATCHDOG
1504 */
1505
1506typedef struct
1507{
1508 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1509 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1510 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1511} WWDG_TypeDef;
1512
1513
1514/**
1515 * @brief RAM_ECC_Specific_Registers
1516 */
1517typedef struct
1518{
1519 __IO uint32_t CR; /*!< RAMECC monitor configuration register */
1520 __IO uint32_t SR; /*!< RAMECC monitor status register */
1521 __IO uint32_t FAR; /*!< RAMECC monitor failing address register */
1522 __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */
1523 __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */
1524 __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */
1525} RAMECC_MonitorTypeDef;
1526
1527typedef struct
1528{
1529 __IO uint32_t IER; /*!< RAMECC interrupt enable register */
1530} RAMECC_TypeDef;
1531/**
1532 * @}
1533 */
1534
1535
1536/**
1537 * @brief Crypto Processor
1538 */
1539
1540typedef struct
1541{
1542 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
1543 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
1544 __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */
1545 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
1546 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
1547 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
1548 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
1549 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
1550 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
1551 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
1552 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
1553 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
1554 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
1555 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
1556 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
1557 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
1558 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
1559 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
1560 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
1561 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
1562 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
1563 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
1564 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
1565 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
1566 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
1567 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
1568 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
1569 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
1570 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
1571 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
1572 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
1573 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
1574 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
1575 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
1576 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
1577 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
1578} CRYP_TypeDef;
1579
1580/**
1581 * @brief HASH
1582 */
1583
1584typedef struct
1585{
1586 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
1587 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
1588 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
1589 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
1590 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
1591 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
1592 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
1593 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
1594} HASH_TypeDef;
1595
1596/**
1597 * @brief HASH_DIGEST
1598 */
1599
1600typedef struct
1601{
1602 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
1603} HASH_DIGEST_TypeDef;
1604
1605
1606/**
1607 * @brief RNG
1608 */
1609
1610typedef struct
1611{
1612 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1613 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1614 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1615 uint32_t RESERVED;
1616 __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
1617} RNG_TypeDef;
1618
1619/**
1620 * @brief MDIOS
1621 */
1622
1623typedef struct
1624{
1625 __IO uint32_t CR;
1626 __IO uint32_t WRFR;
1627 __IO uint32_t CWRFR;
1628 __IO uint32_t RDFR;
1629 __IO uint32_t CRDFR;
1630 __IO uint32_t SR;
1631 __IO uint32_t CLRFR;
1632 uint32_t RESERVED[57];
1633 __IO uint32_t DINR0;
1634 __IO uint32_t DINR1;
1635 __IO uint32_t DINR2;
1636 __IO uint32_t DINR3;
1637 __IO uint32_t DINR4;
1638 __IO uint32_t DINR5;
1639 __IO uint32_t DINR6;
1640 __IO uint32_t DINR7;
1641 __IO uint32_t DINR8;
1642 __IO uint32_t DINR9;
1643 __IO uint32_t DINR10;
1644 __IO uint32_t DINR11;
1645 __IO uint32_t DINR12;
1646 __IO uint32_t DINR13;
1647 __IO uint32_t DINR14;
1648 __IO uint32_t DINR15;
1649 __IO uint32_t DINR16;
1650 __IO uint32_t DINR17;
1651 __IO uint32_t DINR18;
1652 __IO uint32_t DINR19;
1653 __IO uint32_t DINR20;
1654 __IO uint32_t DINR21;
1655 __IO uint32_t DINR22;
1656 __IO uint32_t DINR23;
1657 __IO uint32_t DINR24;
1658 __IO uint32_t DINR25;
1659 __IO uint32_t DINR26;
1660 __IO uint32_t DINR27;
1661 __IO uint32_t DINR28;
1662 __IO uint32_t DINR29;
1663 __IO uint32_t DINR30;
1664 __IO uint32_t DINR31;
1665 __IO uint32_t DOUTR0;
1666 __IO uint32_t DOUTR1;
1667 __IO uint32_t DOUTR2;
1668 __IO uint32_t DOUTR3;
1669 __IO uint32_t DOUTR4;
1670 __IO uint32_t DOUTR5;
1671 __IO uint32_t DOUTR6;
1672 __IO uint32_t DOUTR7;
1673 __IO uint32_t DOUTR8;
1674 __IO uint32_t DOUTR9;
1675 __IO uint32_t DOUTR10;
1676 __IO uint32_t DOUTR11;
1677 __IO uint32_t DOUTR12;
1678 __IO uint32_t DOUTR13;
1679 __IO uint32_t DOUTR14;
1680 __IO uint32_t DOUTR15;
1681 __IO uint32_t DOUTR16;
1682 __IO uint32_t DOUTR17;
1683 __IO uint32_t DOUTR18;
1684 __IO uint32_t DOUTR19;
1685 __IO uint32_t DOUTR20;
1686 __IO uint32_t DOUTR21;
1687 __IO uint32_t DOUTR22;
1688 __IO uint32_t DOUTR23;
1689 __IO uint32_t DOUTR24;
1690 __IO uint32_t DOUTR25;
1691 __IO uint32_t DOUTR26;
1692 __IO uint32_t DOUTR27;
1693 __IO uint32_t DOUTR28;
1694 __IO uint32_t DOUTR29;
1695 __IO uint32_t DOUTR30;
1696 __IO uint32_t DOUTR31;
1697} MDIOS_TypeDef;
1698
1699
1700/**
1701 * @brief USB_OTG_Core_Registers
1702 */
1703typedef struct
1704{
1705 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
1706 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
1707 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
1708 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
1709 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
1710 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
1711 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
1712 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
1713 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
1714 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
1715 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
1716 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
1717 uint32_t Reserved30[2]; /*!< Reserved 030h */
1718 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
1719 __IO uint32_t CID; /*!< User ID Register 03Ch */
1720 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1721 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1722 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1723 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
1724 uint32_t Reserved6; /*!< Reserved 050h */
1725 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
1726 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
1727 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
1728 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
1729 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
1730 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
1731 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
1732} USB_OTG_GlobalTypeDef;
1733
1734
1735/**
1736 * @brief USB_OTG_device_Registers
1737 */
1738typedef struct
1739{
1740 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1741 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1742 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1743 uint32_t Reserved0C; /*!< Reserved 80Ch */
1744 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1745 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1746 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1747 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1748 uint32_t Reserved20; /*!< Reserved 820h */
1749 uint32_t Reserved9; /*!< Reserved 824h */
1750 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1751 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1752 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1753 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1754 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1755 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1756 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1757 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1758 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1759 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1760} USB_OTG_DeviceTypeDef;
1761
1762
1763/**
1764 * @brief USB_OTG_IN_Endpoint-Specific_Register
1765 */
1766typedef struct
1767{
1768 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1769 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1770 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1771 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1772 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1773 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1774 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1775 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1776} USB_OTG_INEndpointTypeDef;
1777
1778
1779/**
1780 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1781 */
1782typedef struct
1783{
1784 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1785 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1786 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1787 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1788 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1789 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1790 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1791} USB_OTG_OUTEndpointTypeDef;
1792
1793
1794/**
1795 * @brief USB_OTG_Host_Mode_Register_Structures
1796 */
1797typedef struct
1798{
1799 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1800 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1801 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1802 uint32_t Reserved40C; /*!< Reserved 40Ch */
1803 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1804 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1805 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1806} USB_OTG_HostTypeDef;
1807
1808/**
1809 * @brief USB_OTG_Host_Channel_Specific_Registers
1810 */
1811typedef struct
1812{
1813 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1814 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1815 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1816 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1817 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1818 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1819 uint32_t Reserved[2]; /*!< Reserved */
1820} USB_OTG_HostChannelTypeDef;
1821/**
1822 * @}
1823 */
1824
1825/**
1826 * @brief OCTO Serial Peripheral Interface
1827 */
1828
1829typedef struct
1830{
1831 __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */
1832 uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */
1833 __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */
1834 __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */
1835 __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */
1836 __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */
1837 uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
1838 __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */
1839 __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */
1840 uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
1841 __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */
1842 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */
1843 __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */
1844 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */
1845 __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */
1846 uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
1847 __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */
1848 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */
1849 __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */
1850 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */
1851 __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */
1852 uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
1853 __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */
1854 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */
1855 __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */
1856 uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */
1857 __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */
1858 uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
1859 __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */
1860 uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
1861 __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */
1862 uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
1863 __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */
1864 uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */
1865 __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */
1866 uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */
1867 __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */
1868 uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
1869 __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */
1870 uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
1871 __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */
1872 uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */
1873 __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */
1874 uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */
1875 __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */
1876 uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
1877 __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
1878 uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
1879 __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
1880 uint32_t RESERVED22[122]; /*!< Reserved, Address offset: 0x204-0x3EC */
1881 __IO uint32_t HWCFGR; /*!< OCTOSPI HW Configuration register, Address offset: 0x3F0 */
1882 __IO uint32_t VER; /*!< OCTOSPI Version register, Address offset: 0x3F4 */
1883 __IO uint32_t ID; /*!< OCTOSPI Identification register, Address offset: 0x3F8 */
1884 __IO uint32_t MID; /*!< OCTOPSI HW Magic ID register, Address offset: 0x3FC */
1885} OCTOSPI_TypeDef;
1886
1887/**
1888 * @}
1889 */
1890/**
1891 * @brief OCTO Serial Peripheral Interface IO Manager
1892 */
1893
1894typedef struct
1895{
1896 __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */
1897 __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
1898} OCTOSPIM_TypeDef;
1899
1900/**
1901 * @}
1902 */
1903
1904/**
1905 * @brief OTFD register
1906 */
1907typedef struct
1908{
1909 __IO uint32_t REG_CONFIGR;
1910 __IO uint32_t REG_START_ADDR;
1911 __IO uint32_t REG_END_ADDR;
1912 __IO uint32_t REG_NONCER0;
1913 __IO uint32_t REG_NONCER1;
1914 __IO uint32_t REG_KEYR0;
1915 __IO uint32_t REG_KEYR1;
1916 __IO uint32_t REG_KEYR2;
1917 __IO uint32_t REG_KEYR3;
1918} OTFDEC_Region_TypeDef;
1919
1920typedef struct
1921{
1922 __IO uint32_t CR;
1923 uint32_t RESERVED1[191];
1924 __IO uint32_t ISR;
1925 __IO uint32_t ICR;
1926 __IO uint32_t IER;
1927 uint32_t RESERVED2[56];
1928 __IO uint32_t HWCFGR2;
1929 __IO uint32_t HWCFGR1;
1930 __IO uint32_t VERR;
1931 __IO uint32_t IPIDR;
1932 __IO uint32_t SIDR;
1933} OTFDEC_TypeDef;
1934/**
1935 * @}
1936 */
1937
1938/** @addtogroup Peripheral_memory_map
1939 * @{
1940 */
1941#define CD_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
1942#define CD_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB (2x64KB) system data RAM accessible over DTCM */
1943#define CD_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
1944
1945#define CD_AXISRAM1_BASE (0x24000000UL) /*!< Base address of : (up to 256KB) system data RAM1 accessible over over AXI */
1946#define CD_AXISRAM2_BASE (0x24040000UL) /*!< Base address of : (up to 384KB) system data RAM2 accessible over over AXI */
1947#define CD_AXISRAM3_BASE (0x240A0000UL) /*!< Base address of : (up to 384KB) system data RAM3 accessible over over AXI */
1948#define CD_AHBSRAM1_BASE (0x30000000UL) /*!< Base address of : (up to 64KB) system data RAM1 accessible over over AXI->AHB Bridge */
1949#define CD_AHBSRAM2_BASE (0x30010000UL) /*!< Base address of : (up to 64KB) system data RAM2 accessible over over AXI->AHB Bridge */
1950
1951#define SRD_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
1952#define SRD_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(32 KB) over AXI->AHB Bridge */
1953
1954#define OCTOSPI1_BASE (0x90000000UL) /*!< Base address of : OCTOSPI1 memories accessible over AXI */
1955#define OCTOSPI2_BASE (0x70000000UL) /*!< Base address of : OCTOSPI2 memories accessible over AXI */
1956
1957#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */
1958#define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */
1959#define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */
1960
1961/* Legacy define */
1962#define FLASH_BASE FLASH_BANK1_BASE
1963#define D1_AXISRAM_BASE CD_AXISRAM1_BASE
1964
1965#define FLASH_OTP_BASE (0x08FFF000UL) /*!< Base address of : (up to 1KB) embedded FLASH Bank1 OTP Area */
1966#define FLASH_OTP_END (0x08FFF3FFUL) /*!< End address of : (up to 1KB) embedded FLASH Bank1 OTP Area */
1967
1968
1969/*!< Device electronic signature memory map */
1970#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */
1971#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< FLASH Size register base address */
1972#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package Data register base address */
1973
1974#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/ABP Peripherals */
1975/*!< Peripheral memory map */
1976#define CD_APB1PERIPH_BASE PERIPH_BASE /*!< D2_APB1PERIPH_BASE PERIPH_BASE */
1977#define CD_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) /*!< D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) */
1978#define CD_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) /*!< D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) */
1979#define CD_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) /*!< D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) */
1980
1981#define CD_APB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) /*!< D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) */
1982#define CD_AHB3PERIPH_BASE (PERIPH_BASE + 0x12000000UL) /*!< D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) */
1983
1984#define SRD_APB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) /*!< D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) */
1985#define SRD_AHB4PERIPH_BASE (PERIPH_BASE + 0x18020000UL) /*!< D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) */
1986
1987/*!< Legacy Peripheral memory map */
1988#define APB1PERIPH_BASE PERIPH_BASE
1989#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1990#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1991#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
1992
1993/*!< CD_AHB3PERIPH peripherals */
1994#define MDMA_BASE (CD_AHB3PERIPH_BASE + 0x0000UL)
1995#define DMA2D_BASE (CD_AHB3PERIPH_BASE + 0x1000UL)
1996#define FLASH_R_BASE (CD_AHB3PERIPH_BASE + 0x2000UL)
1997#define JPGDEC_BASE (CD_AHB3PERIPH_BASE + 0x3000UL)
1998#define FMC_R_BASE (CD_AHB3PERIPH_BASE + 0x4000UL)
1999#define OCTOSPI1_R_BASE (CD_AHB3PERIPH_BASE + 0x5000UL)
2000#define DLYB_OCTOSPI1_BASE (CD_AHB3PERIPH_BASE + 0x6000UL)
2001#define SDMMC1_BASE (CD_AHB3PERIPH_BASE + 0x7000UL)
2002#define DLYB_SDMMC1_BASE (CD_AHB3PERIPH_BASE + 0x8000UL)
2003#define RAMECC_BASE (CD_AHB3PERIPH_BASE + 0x9000UL)
2004#define OCTOSPI2_R_BASE (CD_AHB3PERIPH_BASE + 0xA000UL)
2005#define DLYB_OCTOSPI2_BASE (CD_AHB3PERIPH_BASE + 0xB000UL)
2006#define OCTOSPIM_BASE (CD_AHB3PERIPH_BASE + 0xB400UL)
2007
2008/*!< CD_AHB1PERIPH peripherals */
2009
2010#define DMA1_BASE (CD_AHB1PERIPH_BASE + 0x0000UL)
2011#define DMA2_BASE (CD_AHB1PERIPH_BASE + 0x0400UL)
2012#define DMAMUX1_BASE (CD_AHB1PERIPH_BASE + 0x0800UL)
2013#define ADC1_BASE (CD_AHB1PERIPH_BASE + 0x2000UL)
2014#define ADC2_BASE (CD_AHB1PERIPH_BASE + 0x2100UL)
2015#define ADC12_COMMON_BASE (CD_AHB1PERIPH_BASE + 0x2300UL)
2016#define CRC_BASE (CD_AHB1PERIPH_BASE + 0x3000UL)
2017
2018/*!< USB registers base address */
2019#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
2020#define USB_OTG_GLOBAL_BASE (0x000UL)
2021#define USB_OTG_DEVICE_BASE (0x800UL)
2022#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
2023#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
2024#define USB_OTG_EP_REG_SIZE (0x20UL)
2025#define USB_OTG_HOST_BASE (0x400UL)
2026#define USB_OTG_HOST_PORT_BASE (0x440UL)
2027#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
2028#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
2029#define USB_OTG_PCGCCTL_BASE (0xE00UL)
2030#define USB_OTG_FIFO_BASE (0x1000UL)
2031#define USB_OTG_FIFO_SIZE (0x1000UL)
2032
2033/*!< CD_AHB2PERIPH peripherals */
2034
2035#define DCMI_BASE (CD_AHB2PERIPH_BASE + 0x0000UL)
2036#define PSSI_BASE (CD_AHB2PERIPH_BASE + 0x0400UL)
2037#define HSEM_BASE (CD_AHB2PERIPH_BASE + 0x0800UL)
2038#define CRYP_BASE (CD_AHB2PERIPH_BASE + 0x1000UL)
2039#define HASH_BASE (CD_AHB2PERIPH_BASE + 0x1400UL)
2040#define HASH_DIGEST_BASE (CD_AHB2PERIPH_BASE + 0x1710UL)
2041#define RNG_BASE (CD_AHB2PERIPH_BASE + 0x1800UL)
2042#define SDMMC2_BASE (CD_AHB2PERIPH_BASE + 0x2400UL)
2043#define DLYB_SDMMC2_BASE (CD_AHB2PERIPH_BASE + 0x2800UL)
2044#define BDMA1_BASE (CD_AHB2PERIPH_BASE + 0x2C00UL)
2045
2046/*!< SRD_AHB4PERIPH peripherals */
2047#define GPIOA_BASE (SRD_AHB4PERIPH_BASE + 0x0000UL)
2048#define GPIOB_BASE (SRD_AHB4PERIPH_BASE + 0x0400UL)
2049#define GPIOC_BASE (SRD_AHB4PERIPH_BASE + 0x0800UL)
2050#define GPIOD_BASE (SRD_AHB4PERIPH_BASE + 0x0C00UL)
2051#define GPIOE_BASE (SRD_AHB4PERIPH_BASE + 0x1000UL)
2052#define GPIOF_BASE (SRD_AHB4PERIPH_BASE + 0x1400UL)
2053#define GPIOG_BASE (SRD_AHB4PERIPH_BASE + 0x1800UL)
2054#define GPIOH_BASE (SRD_AHB4PERIPH_BASE + 0x1C00UL)
2055#define GPIOI_BASE (SRD_AHB4PERIPH_BASE + 0x2000UL)
2056#define GPIOJ_BASE (SRD_AHB4PERIPH_BASE + 0x2400UL)
2057#define GPIOK_BASE (SRD_AHB4PERIPH_BASE + 0x2800UL)
2058#define RCC_BASE (SRD_AHB4PERIPH_BASE + 0x4400UL)
2059#define PWR_BASE (SRD_AHB4PERIPH_BASE + 0x4800UL)
2060#define BDMA2_BASE (SRD_AHB4PERIPH_BASE + 0x5400UL)
2061#define DMAMUX2_BASE (SRD_AHB4PERIPH_BASE + 0x5800UL)
2062
2063/*!< CD_APB3PERIPH peripherals */
2064#define LTDC_BASE (CD_APB3PERIPH_BASE + 0x1000UL)
2065#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
2066#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
2067#define WWDG1_BASE (CD_APB3PERIPH_BASE + 0x3000UL)
2068
2069/*!< CD_APB1PERIPH peripherals */
2070#define TIM2_BASE (CD_APB1PERIPH_BASE + 0x0000UL)
2071#define TIM3_BASE (CD_APB1PERIPH_BASE + 0x0400UL)
2072#define TIM4_BASE (CD_APB1PERIPH_BASE + 0x0800UL)
2073#define TIM5_BASE (CD_APB1PERIPH_BASE + 0x0C00UL)
2074#define TIM6_BASE (CD_APB1PERIPH_BASE + 0x1000UL)
2075#define TIM7_BASE (CD_APB1PERIPH_BASE + 0x1400UL)
2076#define TIM12_BASE (CD_APB1PERIPH_BASE + 0x1800UL)
2077#define TIM13_BASE (CD_APB1PERIPH_BASE + 0x1C00UL)
2078#define TIM14_BASE (CD_APB1PERIPH_BASE + 0x2000UL)
2079#define LPTIM1_BASE (CD_APB1PERIPH_BASE + 0x2400UL)
2080
2081#define SPI2_BASE (CD_APB1PERIPH_BASE + 0x3800UL)
2082#define SPI3_BASE (CD_APB1PERIPH_BASE + 0x3C00UL)
2083#define SPDIFRX_BASE (CD_APB1PERIPH_BASE + 0x4000UL)
2084#define USART2_BASE (CD_APB1PERIPH_BASE + 0x4400UL)
2085#define USART3_BASE (CD_APB1PERIPH_BASE + 0x4800UL)
2086#define UART4_BASE (CD_APB1PERIPH_BASE + 0x4C00UL)
2087#define UART5_BASE (CD_APB1PERIPH_BASE + 0x5000UL)
2088#define I2C1_BASE (CD_APB1PERIPH_BASE + 0x5400UL)
2089#define I2C2_BASE (CD_APB1PERIPH_BASE + 0x5800UL)
2090#define I2C3_BASE (CD_APB1PERIPH_BASE + 0x5C00UL)
2091#define CEC_BASE (CD_APB1PERIPH_BASE + 0x6C00UL)
2092#define DAC1_BASE (CD_APB1PERIPH_BASE + 0x7400UL)
2093#define UART7_BASE (CD_APB1PERIPH_BASE + 0x7800UL)
2094#define UART8_BASE (CD_APB1PERIPH_BASE + 0x7C00UL)
2095#define CRS_BASE (CD_APB1PERIPH_BASE + 0x8400UL)
2096#define SWPMI1_BASE (CD_APB1PERIPH_BASE + 0x8800UL)
2097#define OPAMP_BASE (CD_APB1PERIPH_BASE + 0x9000UL)
2098#define OPAMP1_BASE (CD_APB1PERIPH_BASE + 0x9000UL)
2099#define OPAMP2_BASE (CD_APB1PERIPH_BASE + 0x9010UL)
2100#define MDIOS_BASE (CD_APB1PERIPH_BASE + 0x9400UL)
2101#define FDCAN1_BASE (CD_APB1PERIPH_BASE + 0xA000UL)
2102#define FDCAN2_BASE (CD_APB1PERIPH_BASE + 0xA400UL)
2103#define FDCAN_CCU_BASE (CD_APB1PERIPH_BASE + 0xA800UL)
2104#define SRAMCAN_BASE (CD_APB1PERIPH_BASE + 0xAC00UL)
2105
2106/*!< CD_APB2PERIPH peripherals */
2107
2108#define TIM1_BASE (CD_APB2PERIPH_BASE + 0x0000UL)
2109#define TIM8_BASE (CD_APB2PERIPH_BASE + 0x0400UL)
2110#define USART1_BASE (CD_APB2PERIPH_BASE + 0x1000UL)
2111#define USART6_BASE (CD_APB2PERIPH_BASE + 0x1400UL)
2112#define UART9_BASE (CD_APB2PERIPH_BASE + 0x1800UL)
2113#define USART10_BASE (CD_APB2PERIPH_BASE + 0x1C00UL)
2114#define SPI1_BASE (CD_APB2PERIPH_BASE + 0x3000UL)
2115#define SPI4_BASE (CD_APB2PERIPH_BASE + 0x3400UL)
2116#define TIM15_BASE (CD_APB2PERIPH_BASE + 0x4000UL)
2117#define TIM16_BASE (CD_APB2PERIPH_BASE + 0x4400UL)
2118#define TIM17_BASE (CD_APB2PERIPH_BASE + 0x4800UL)
2119#define SPI5_BASE (CD_APB2PERIPH_BASE + 0x5000UL)
2120#define SAI1_BASE (CD_APB2PERIPH_BASE + 0x5800UL)
2121#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2122#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2123#define SAI2_BASE (CD_APB2PERIPH_BASE + 0x5C00UL)
2124#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
2125#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
2126#define DFSDM1_BASE (CD_APB2PERIPH_BASE + 0x7800UL)
2127#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2128#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2129#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2130#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2131#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2132#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2133#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2134#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2135#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2136#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2137#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2138#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2139#define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300UL)
2140#define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380UL)
2141#define DFSDM1_Filter6_BASE (DFSDM1_BASE + 0x400UL)
2142#define DFSDM1_Filter7_BASE (DFSDM1_BASE + 0x480UL)
2143/*!< SRD_APB4PERIPH peripherals */
2144#define EXTI_BASE (SRD_APB4PERIPH_BASE + 0x0000UL)
2145#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2146#define SYSCFG_BASE (SRD_APB4PERIPH_BASE + 0x0400UL)
2147#define LPUART1_BASE (SRD_APB4PERIPH_BASE + 0x0C00UL)
2148#define SPI6_BASE (SRD_APB4PERIPH_BASE + 0x1400UL)
2149#define I2C4_BASE (SRD_APB4PERIPH_BASE + 0x1C00UL)
2150#define LPTIM2_BASE (SRD_APB4PERIPH_BASE + 0x2400UL)
2151#define LPTIM3_BASE (SRD_APB4PERIPH_BASE + 0x2800UL)
2152#define DAC2_BASE (SRD_APB4PERIPH_BASE + 0x3400UL)
2153#define COMP12_BASE (SRD_APB4PERIPH_BASE + 0x3800UL)
2154#define COMP1_BASE (COMP12_BASE + 0x0CUL)
2155#define COMP2_BASE (COMP12_BASE + 0x10UL)
2156#define VREFBUF_BASE (SRD_APB4PERIPH_BASE + 0x3C00UL)
2157#define RTC_BASE (SRD_APB4PERIPH_BASE + 0x4000UL)
2158#define TAMP_BASE (SRD_APB4PERIPH_BASE + 0x4400UL)
2159#define IWDG1_BASE (SRD_APB4PERIPH_BASE + 0x4800UL)
2160
2161#define DTS_BASE (SRD_APB4PERIPH_BASE + 0x6800UL)
2162
2163#define DFSDM2_BASE (SRD_APB4PERIPH_BASE + 0x6C00UL)
2164#define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00UL)
2165#define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20UL)
2166#define DFSDM2_FLT0_BASE (DFSDM2_BASE + 0x100UL)
2167
2168/*!< CD_AHB3PERIPH peripherals */
2169
2170#define OTFDEC1_BASE (CD_AHB3PERIPH_BASE + 0xB800UL)
2171#define OTFDEC1_REGION1_BASE (OTFDEC1_BASE + 0x20UL)
2172#define OTFDEC1_REGION2_BASE (OTFDEC1_BASE + 0x50UL)
2173#define OTFDEC1_REGION3_BASE (OTFDEC1_BASE + 0x80UL)
2174#define OTFDEC1_REGION4_BASE (OTFDEC1_BASE + 0xB0UL)
2175#define OTFDEC2_BASE (CD_AHB3PERIPH_BASE + 0xBC00UL)
2176#define OTFDEC2_REGION1_BASE (OTFDEC2_BASE + 0x20UL)
2177#define OTFDEC2_REGION2_BASE (OTFDEC2_BASE + 0x50UL)
2178#define OTFDEC2_REGION3_BASE (OTFDEC2_BASE + 0x80UL)
2179#define OTFDEC2_REGION4_BASE (OTFDEC2_BASE + 0xB0UL)
2180#define GFXMMU_BASE (CD_AHB3PERIPH_BASE + 0xC000UL)
2181
2182#define BDMA1_Channel0_BASE (BDMA1_BASE + 0x0008UL)
2183#define BDMA1_Channel1_BASE (BDMA1_BASE + 0x001CUL)
2184#define BDMA1_Channel2_BASE (BDMA1_BASE + 0x0030UL)
2185#define BDMA1_Channel3_BASE (BDMA1_BASE + 0x0044UL)
2186#define BDMA1_Channel4_BASE (BDMA1_BASE + 0x0058UL)
2187#define BDMA1_Channel5_BASE (BDMA1_BASE + 0x006CUL)
2188#define BDMA1_Channel6_BASE (BDMA1_BASE + 0x0080UL)
2189#define BDMA1_Channel7_BASE (BDMA1_BASE + 0x0094UL)
2190
2191#define BDMA2_Channel0_BASE (BDMA2_BASE + 0x0008UL)
2192#define BDMA2_Channel1_BASE (BDMA2_BASE + 0x001CUL)
2193#define BDMA2_Channel2_BASE (BDMA2_BASE + 0x0030UL)
2194#define BDMA2_Channel3_BASE (BDMA2_BASE + 0x0044UL)
2195#define BDMA2_Channel4_BASE (BDMA2_BASE + 0x0058UL)
2196#define BDMA2_Channel5_BASE (BDMA2_BASE + 0x006CUL)
2197#define BDMA2_Channel6_BASE (BDMA2_BASE + 0x0080UL)
2198#define BDMA2_Channel7_BASE (BDMA2_BASE + 0x0094UL)
2199
2200
2201#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2202#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2203#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2204#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2205#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2206#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2207#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2208#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2209
2210#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2211#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2212#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2213#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2214#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2215#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2216#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2217#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2218
2219#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2220#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2221
2222#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2223#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2224#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2225#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2226#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2227#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2228#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2229#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2230
2231#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2232#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2233#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2234#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2235#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2236#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2237#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2238#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2239
2240
2241#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2242#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2243#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2244#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2245#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2246#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2247#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2248#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2249#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2250#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2251#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2252#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2253#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2254#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2255#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2256#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2257
2258#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2259#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2260#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2261#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2262#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2263#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2264#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2265#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2266
2267#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2268#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2269
2270/*!< FMC Banks registers base address */
2271#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2272#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2273#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2274#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2275#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2276
2277/* Debug MCU registers base address */
2278#define DBGMCU_BASE (0x5C001000UL)
2279
2280#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2281#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2282#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2283#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2284#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2285#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2286#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2287#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2288#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2289#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2290#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2291#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2292#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2293#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2294#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2295#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2296#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
2297
2298/* GFXMMU virtual buffers base address */
2299#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
2300#define GFXMMU_VIRTUAL_BUFFER0_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE)
2301#define GFXMMU_VIRTUAL_BUFFER1_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x400000UL)
2302#define GFXMMU_VIRTUAL_BUFFER2_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x800000UL)
2303#define GFXMMU_VIRTUAL_BUFFER3_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0xC00000UL)
2304
2305#define RAMECC_Monitor1_BASE (RAMECC_BASE + 0x20UL)
2306#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)
2307#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)
2308
2309/**
2310 * @}
2311 */
2312
2313/** @addtogroup Peripheral_declaration
2314 * @{
2315 */
2316#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2317#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2318#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2319#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2320#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2321#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2322#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2323#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2324#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2325#define RTC ((RTC_TypeDef *) RTC_BASE)
2326#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
2327#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2328
2329
2330#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2331#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2332#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2333#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2334#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2335#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2336#define USART2 ((USART_TypeDef *) USART2_BASE)
2337#define USART3 ((USART_TypeDef *) USART3_BASE)
2338#define USART6 ((USART_TypeDef *) USART6_BASE)
2339#define USART10 ((USART_TypeDef *) USART10_BASE)
2340#define UART7 ((USART_TypeDef *) UART7_BASE)
2341#define UART8 ((USART_TypeDef *) UART8_BASE)
2342#define UART9 ((USART_TypeDef *) UART9_BASE)
2343#define CRS ((CRS_TypeDef *) CRS_BASE)
2344#define UART4 ((USART_TypeDef *) UART4_BASE)
2345#define UART5 ((USART_TypeDef *) UART5_BASE)
2346#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2347#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2348#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2349#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2350#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2351#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2352#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2353#define CEC ((CEC_TypeDef *) CEC_BASE)
2354#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2355#define PWR ((PWR_TypeDef *) PWR_BASE)
2356#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2357#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2358#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2359#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2360#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2361#define DTS ((DTS_TypeDef *) DTS_BASE)
2362
2363#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2364#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2365#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2366#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2367#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2368#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2369#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2370#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2371
2372
2373#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2374#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2375#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2376#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2377#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2378#define USART1 ((USART_TypeDef *) USART1_BASE)
2379#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2380#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2381#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2382#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2383#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2384#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2385#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2386#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2387#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2388#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2389
2390#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2391#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2392#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2393#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2394#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2395#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2396#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2397#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2398#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2399#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2400#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2401#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2402#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2403#define DFSDM1_Filter4 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)
2404#define DFSDM1_Filter5 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)
2405#define DFSDM1_Filter6 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)
2406#define DFSDM1_Filter7 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)
2407#define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
2408#define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
2409#define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)
2410#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2411#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2412#define PSSI ((PSSI_TypeDef *) PSSI_BASE)
2413#define RCC ((RCC_TypeDef *) RCC_BASE)
2414#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2415#define CRC ((CRC_TypeDef *) CRC_BASE)
2416
2417#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2418#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2419#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2420#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2421#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2422#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2423#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2424#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2425#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2426#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2427#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2428
2429#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2430#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2431#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2432
2433#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
2434#define HASH ((HASH_TypeDef *) HASH_BASE)
2435#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
2436#define RNG ((RNG_TypeDef *) RNG_BASE)
2437#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2438#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2439
2440#define BDMA1 ((BDMA_TypeDef *) BDMA1_BASE)
2441#define BDMA1_Channel0 ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)
2442#define BDMA1_Channel1 ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)
2443#define BDMA1_Channel2 ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)
2444#define BDMA1_Channel3 ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)
2445#define BDMA1_Channel4 ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)
2446#define BDMA1_Channel5 ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)
2447#define BDMA1_Channel6 ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)
2448#define BDMA1_Channel7 ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)
2449
2450#define BDMA2 ((BDMA_TypeDef *) BDMA2_BASE)
2451#define BDMA2_Channel0 ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)
2452#define BDMA2_Channel1 ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)
2453#define BDMA2_Channel2 ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)
2454#define BDMA2_Channel3 ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)
2455#define BDMA2_Channel4 ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)
2456#define BDMA2_Channel5 ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)
2457#define BDMA2_Channel6 ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)
2458#define BDMA2_Channel7 ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)
2459
2460#define RAMECC ((RAMECC_TypeDef *)RAMECC_BASE)
2461#define RAMECC_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)
2462#define RAMECC_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)
2463#define RAMECC_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)
2464
2465#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2466#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2467#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2468#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2469#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2470#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2471#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2472#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2473#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2474
2475
2476#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2477#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2478#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2479#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2480#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2481#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2482#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2483#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2484
2485#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2486#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2487
2488#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2489#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2490#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2491#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2492#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2493#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2494#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2495#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2496#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2497
2498#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2499#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2500#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2501#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2502#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2503#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2504#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2505#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2506#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2507
2508
2509#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2510#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2511#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2512#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2513#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2514#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2515#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2516#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2517#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2518#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2519#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2520#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2521#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2522#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2523#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2524#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2525#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2526
2527#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2528#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2529#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2530#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2531#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2532#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2533#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2534#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2535
2536#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2537#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2538
2539
2540#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2541#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2542#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2543#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2544#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2545
2546#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
2547#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)
2548#define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)
2549#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)
2550#define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)
2551#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)
2552
2553#define OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE)
2554#define OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)
2555#define OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)
2556#define OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)
2557#define OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)
2558
2559#define OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE)
2560#define OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)
2561#define OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)
2562#define OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)
2563#define OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)
2564#define GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE)
2565
2566#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2567#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2568
2569#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2570
2571#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
2572#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2573#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2574
2575#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2576#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2577#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2578
2579#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2580
2581#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2582#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2583#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2584#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2585#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2586#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2587#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2588#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2589#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2590#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2591#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2592#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2593#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2594#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2595#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2596#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2597#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2598
2599
2600#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2601
2602/* Legacy defines */
2603#define USB_OTG_HS USB1_OTG_HS
2604#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2605
2606/**
2607 * @}
2608 */
2609
2610/** @addtogroup Exported_constants
2611 * @{
2612 */
2613
2614 /** @addtogroup Peripheral_Registers_Bits_Definition
2615 * @{
2616 */
2617
2618/******************************************************************************/
2619/* Peripheral Registers_Bits_Definition */
2620/******************************************************************************/
2621
2622/******************************************************************************/
2623/* */
2624/* Analog to Digital Converter */
2625/* */
2626/******************************************************************************/
2627/******************************* ADC VERSION ********************************/
2628#define ADC_VER_V5_3
2629/******************** Bit definition for ADC_ISR register ********************/
2630#define ADC_ISR_ADRDY_Pos (0U)
2631#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
2632#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
2633#define ADC_ISR_EOSMP_Pos (1U)
2634#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
2635#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
2636#define ADC_ISR_EOC_Pos (2U)
2637#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
2638#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
2639#define ADC_ISR_EOS_Pos (3U)
2640#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
2641#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
2642#define ADC_ISR_OVR_Pos (4U)
2643#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
2644#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
2645#define ADC_ISR_JEOC_Pos (5U)
2646#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
2647#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
2648#define ADC_ISR_JEOS_Pos (6U)
2649#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
2650#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
2651#define ADC_ISR_AWD1_Pos (7U)
2652#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
2653#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
2654#define ADC_ISR_AWD2_Pos (8U)
2655#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
2656#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
2657#define ADC_ISR_AWD3_Pos (9U)
2658#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
2659#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
2660#define ADC_ISR_JQOVF_Pos (10U)
2661#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
2662#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2663
2664/******************** Bit definition for ADC_IER register ********************/
2665#define ADC_IER_ADRDYIE_Pos (0U)
2666#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
2667#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
2668#define ADC_IER_EOSMPIE_Pos (1U)
2669#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
2670#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
2671#define ADC_IER_EOCIE_Pos (2U)
2672#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
2673#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
2674#define ADC_IER_EOSIE_Pos (3U)
2675#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
2676#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
2677#define ADC_IER_OVRIE_Pos (4U)
2678#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
2679#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
2680#define ADC_IER_JEOCIE_Pos (5U)
2681#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
2682#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
2683#define ADC_IER_JEOSIE_Pos (6U)
2684#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
2685#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
2686#define ADC_IER_AWD1IE_Pos (7U)
2687#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
2688#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
2689#define ADC_IER_AWD2IE_Pos (8U)
2690#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
2691#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
2692#define ADC_IER_AWD3IE_Pos (9U)
2693#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
2694#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
2695#define ADC_IER_JQOVFIE_Pos (10U)
2696#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
2697#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
2698
2699/******************** Bit definition for ADC_CR register ********************/
2700#define ADC_CR_ADEN_Pos (0U)
2701#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
2702#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
2703#define ADC_CR_ADDIS_Pos (1U)
2704#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
2705#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
2706#define ADC_CR_ADSTART_Pos (2U)
2707#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
2708#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
2709#define ADC_CR_JADSTART_Pos (3U)
2710#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
2711#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
2712#define ADC_CR_ADSTP_Pos (4U)
2713#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
2714#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
2715#define ADC_CR_JADSTP_Pos (5U)
2716#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
2717#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
2718#define ADC_CR_BOOST_Pos (8U)
2719#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */
2720#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */
2721#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
2722#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */
2723#define ADC_CR_ADCALLIN_Pos (16U)
2724#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
2725#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
2726#define ADC_CR_LINCALRDYW1_Pos (22U)
2727#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
2728#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
2729#define ADC_CR_LINCALRDYW2_Pos (23U)
2730#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
2731#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
2732#define ADC_CR_LINCALRDYW3_Pos (24U)
2733#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
2734#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
2735#define ADC_CR_LINCALRDYW4_Pos (25U)
2736#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
2737#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
2738#define ADC_CR_LINCALRDYW5_Pos (26U)
2739#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
2740#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
2741#define ADC_CR_LINCALRDYW6_Pos (27U)
2742#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
2743#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
2744#define ADC_CR_ADVREGEN_Pos (28U)
2745#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
2746#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
2747#define ADC_CR_DEEPPWD_Pos (29U)
2748#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
2749#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
2750#define ADC_CR_ADCALDIF_Pos (30U)
2751#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
2752#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
2753#define ADC_CR_ADCAL_Pos (31U)
2754#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
2755#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
2756
2757/******************** Bit definition for ADC_CFGR register ********************/
2758#define ADC_CFGR_DMNGT_Pos (0U)
2759#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
2760#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
2761#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
2762#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
2763
2764#define ADC_CFGR_RES_Pos (2U)
2765#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
2766#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
2767#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
2768#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
2769#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
2770
2771#define ADC_CFGR_EXTSEL_Pos (5U)
2772#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
2773#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
2774#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
2775#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
2776#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
2777#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
2778#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
2779
2780#define ADC_CFGR_EXTEN_Pos (10U)
2781#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
2782#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
2783#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
2784#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
2785
2786#define ADC_CFGR_OVRMOD_Pos (12U)
2787#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
2788#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
2789#define ADC_CFGR_CONT_Pos (13U)
2790#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
2791#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
2792#define ADC_CFGR_AUTDLY_Pos (14U)
2793#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
2794#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
2795
2796#define ADC_CFGR_DISCEN_Pos (16U)
2797#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
2798#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
2799
2800#define ADC_CFGR_DISCNUM_Pos (17U)
2801#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
2802#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
2803#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
2804#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
2805#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
2806
2807#define ADC_CFGR_JDISCEN_Pos (20U)
2808#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
2809#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
2810#define ADC_CFGR_JQM_Pos (21U)
2811#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
2812#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
2813#define ADC_CFGR_AWD1SGL_Pos (22U)
2814#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
2815#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
2816#define ADC_CFGR_AWD1EN_Pos (23U)
2817#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
2818#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
2819#define ADC_CFGR_JAWD1EN_Pos (24U)
2820#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
2821#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
2822#define ADC_CFGR_JAUTO_Pos (25U)
2823#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
2824#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
2825
2826#define ADC_CFGR_AWD1CH_Pos (26U)
2827#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
2828#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
2829#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
2830#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
2831#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
2832#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
2833#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
2834
2835#define ADC_CFGR_JQDIS_Pos (31U)
2836#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
2837#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
2838
2839/******************** Bit definition for ADC_CFGR2 register ********************/
2840#define ADC_CFGR2_ROVSE_Pos (0U)
2841#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
2842#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
2843#define ADC_CFGR2_JOVSE_Pos (1U)
2844#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
2845#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
2846
2847#define ADC_CFGR2_OVSS_Pos (5U)
2848#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
2849#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
2850#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
2851#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
2852#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
2853#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
2854
2855#define ADC_CFGR2_TROVS_Pos (9U)
2856#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
2857#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
2858#define ADC_CFGR2_ROVSM_Pos (10U)
2859#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
2860#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
2861
2862#define ADC_CFGR2_RSHIFT1_Pos (11U)
2863#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
2864#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
2865#define ADC_CFGR2_RSHIFT2_Pos (12U)
2866#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
2867#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
2868#define ADC_CFGR2_RSHIFT3_Pos (13U)
2869#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
2870#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
2871#define ADC_CFGR2_RSHIFT4_Pos (14U)
2872#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
2873#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
2874
2875#define ADC_CFGR2_OVSR_Pos (16U)
2876#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
2877#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
2878#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
2879#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
2880#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
2881#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
2882#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
2883#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
2884#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
2885#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
2886#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
2887#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
2888
2889#define ADC_CFGR2_LSHIFT_Pos (28U)
2890#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
2891#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
2892#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
2893#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
2894#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
2895#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
2896
2897/******************** Bit definition for ADC_SMPR1 register ********************/
2898#define ADC_SMPR1_SMP0_Pos (0U)
2899#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
2900#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
2901#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
2902#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
2903#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
2904
2905#define ADC_SMPR1_SMP1_Pos (3U)
2906#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
2907#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
2908#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
2909#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
2910#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
2911
2912#define ADC_SMPR1_SMP2_Pos (6U)
2913#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
2914#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
2915#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
2916#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
2917#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
2918
2919#define ADC_SMPR1_SMP3_Pos (9U)
2920#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
2921#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
2922#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
2923#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
2924#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
2925
2926#define ADC_SMPR1_SMP4_Pos (12U)
2927#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
2928#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
2929#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
2930#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
2931#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
2932
2933#define ADC_SMPR1_SMP5_Pos (15U)
2934#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
2935#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
2936#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
2937#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
2938#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
2939
2940#define ADC_SMPR1_SMP6_Pos (18U)
2941#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
2942#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
2943#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
2944#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
2945#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
2946
2947#define ADC_SMPR1_SMP7_Pos (21U)
2948#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
2949#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
2950#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
2951#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
2952#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
2953
2954#define ADC_SMPR1_SMP8_Pos (24U)
2955#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
2956#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
2957#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
2958#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
2959#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
2960
2961#define ADC_SMPR1_SMP9_Pos (27U)
2962#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
2963#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
2964#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
2965#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
2966#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
2967
2968/******************** Bit definition for ADC_SMPR2 register ********************/
2969#define ADC_SMPR2_SMP10_Pos (0U)
2970#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
2971#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
2972#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
2973#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
2974#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
2975
2976#define ADC_SMPR2_SMP11_Pos (3U)
2977#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
2978#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
2979#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
2980#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
2981#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
2982
2983#define ADC_SMPR2_SMP12_Pos (6U)
2984#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
2985#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
2986#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
2987#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
2988#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
2989
2990#define ADC_SMPR2_SMP13_Pos (9U)
2991#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
2992#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
2993#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
2994#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
2995#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
2996
2997#define ADC_SMPR2_SMP14_Pos (12U)
2998#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
2999#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
3000#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
3001#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
3002#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
3003
3004#define ADC_SMPR2_SMP15_Pos (15U)
3005#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
3006#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
3007#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
3008#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
3009#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
3010
3011#define ADC_SMPR2_SMP16_Pos (18U)
3012#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
3013#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
3014#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
3015#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
3016#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
3017
3018#define ADC_SMPR2_SMP17_Pos (21U)
3019#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
3020#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
3021#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
3022#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
3023#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
3024
3025#define ADC_SMPR2_SMP18_Pos (24U)
3026#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
3027#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
3028#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
3029#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
3030#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
3031
3032#define ADC_SMPR2_SMP19_Pos (27U)
3033#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
3034#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
3035#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
3036#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
3037#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
3038
3039/******************** Bit definition for ADC_PCSEL register ********************/
3040#define ADC_PCSEL_PCSEL_Pos (0U)
3041#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
3042#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
3043#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
3044#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
3045#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
3046#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
3047#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
3048#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
3049#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
3050#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
3051#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
3052#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
3053#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
3054#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
3055#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
3056#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
3057#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
3058#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
3059#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
3060#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
3061#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
3062#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
3063
3064/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
3065#define ADC_LTR_LT_Pos (0U)
3066#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */
3067#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
3068
3069/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
3070#define ADC_HTR_HT_Pos (0U)
3071#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
3072#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
3073
3074
3075/******************** Bit definition for ADC_SQR1 register ********************/
3076#define ADC_SQR1_L_Pos (0U)
3077#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
3078#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
3079#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
3080#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
3081#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
3082#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
3083
3084#define ADC_SQR1_SQ1_Pos (6U)
3085#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
3086#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
3087#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
3088#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
3089#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
3090#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
3091#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
3092
3093#define ADC_SQR1_SQ2_Pos (12U)
3094#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
3095#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
3096#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
3097#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
3098#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
3099#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
3100#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
3101
3102#define ADC_SQR1_SQ3_Pos (18U)
3103#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
3104#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
3105#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
3106#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
3107#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
3108#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
3109#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
3110
3111#define ADC_SQR1_SQ4_Pos (24U)
3112#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
3113#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
3114#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
3115#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
3116#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
3117#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
3118#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
3119
3120/******************** Bit definition for ADC_SQR2 register ********************/
3121#define ADC_SQR2_SQ5_Pos (0U)
3122#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
3123#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
3124#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
3125#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
3126#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
3127#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
3128#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
3129
3130#define ADC_SQR2_SQ6_Pos (6U)
3131#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
3132#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
3133#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
3134#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
3135#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
3136#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
3137#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
3138
3139#define ADC_SQR2_SQ7_Pos (12U)
3140#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
3141#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
3142#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
3143#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
3144#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
3145#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
3146#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
3147
3148#define ADC_SQR2_SQ8_Pos (18U)
3149#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
3150#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
3151#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
3152#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
3153#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
3154#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
3155#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
3156
3157#define ADC_SQR2_SQ9_Pos (24U)
3158#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
3159#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
3160#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
3161#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
3162#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
3163#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
3164#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
3165
3166/******************** Bit definition for ADC_SQR3 register ********************/
3167#define ADC_SQR3_SQ10_Pos (0U)
3168#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
3169#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
3170#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
3171#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
3172#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
3173#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
3174#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
3175
3176#define ADC_SQR3_SQ11_Pos (6U)
3177#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
3178#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
3179#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
3180#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
3181#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
3182#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
3183#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
3184
3185#define ADC_SQR3_SQ12_Pos (12U)
3186#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
3187#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
3188#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
3189#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
3190#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
3191#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
3192#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
3193
3194#define ADC_SQR3_SQ13_Pos (18U)
3195#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
3196#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
3197#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
3198#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
3199#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
3200#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
3201#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
3202
3203#define ADC_SQR3_SQ14_Pos (24U)
3204#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
3205#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
3206#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
3207#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
3208#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
3209#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
3210#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
3211
3212/******************** Bit definition for ADC_SQR4 register ********************/
3213#define ADC_SQR4_SQ15_Pos (0U)
3214#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
3215#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
3216#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
3217#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
3218#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
3219#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
3220#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
3221
3222#define ADC_SQR4_SQ16_Pos (6U)
3223#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
3224#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
3225#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
3226#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
3227#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
3228#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
3229#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
3230/******************** Bit definition for ADC_DR register ********************/
3231#define ADC_DR_RDATA_Pos (0U)
3232#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
3233#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
3234
3235/******************** Bit definition for ADC_JSQR register ********************/
3236#define ADC_JSQR_JL_Pos (0U)
3237#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
3238#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
3239#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
3240#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
3241
3242#define ADC_JSQR_JEXTSEL_Pos (2U)
3243#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
3244#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
3245#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
3246#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
3247#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
3248#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
3249#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
3250
3251#define ADC_JSQR_JEXTEN_Pos (7U)
3252#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
3253#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
3254#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
3255#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
3256
3257#define ADC_JSQR_JSQ1_Pos (9U)
3258#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
3259#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
3260#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
3261#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
3262#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
3263#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
3264#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
3265
3266#define ADC_JSQR_JSQ2_Pos (15U)
3267#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
3268#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
3269#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
3270#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
3271#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
3272#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
3273#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
3274
3275#define ADC_JSQR_JSQ3_Pos (21U)
3276#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
3277#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
3278#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
3279#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
3280#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
3281#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
3282#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
3283
3284#define ADC_JSQR_JSQ4_Pos (27U)
3285#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
3286#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
3287#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
3288#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
3289#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
3290#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
3291#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
3292
3293/******************** Bit definition for ADC_OFR1 register ********************/
3294#define ADC_OFR1_OFFSET1_Pos (0U)
3295#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
3296#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
3297#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
3298#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
3299#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
3300#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
3301#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
3302#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
3303#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
3304#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
3305#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
3306#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
3307#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
3308#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
3309#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
3310#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
3311#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
3312#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
3313#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
3314#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
3315#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
3316#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
3317#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
3318#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
3319#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
3320#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
3321#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
3322#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
3323
3324#define ADC_OFR1_OFFSET1_CH_Pos (26U)
3325#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
3326#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
3327#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
3328#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
3329#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
3330#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
3331#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
3332
3333#define ADC_OFR1_SSATE_Pos (31U)
3334#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
3335#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
3336
3337
3338/******************** Bit definition for ADC_OFR2 register ********************/
3339#define ADC_OFR2_OFFSET2_Pos (0U)
3340#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
3341#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
3342#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
3343#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
3344#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
3345#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
3346#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
3347#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
3348#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
3349#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
3350#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
3351#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
3352#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
3353#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
3354#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
3355#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
3356#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
3357#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
3358#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
3359#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
3360#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
3361#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
3362#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
3363#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
3364#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
3365#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
3366#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
3367#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
3368
3369#define ADC_OFR2_OFFSET2_CH_Pos (26U)
3370#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
3371#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
3372#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
3373#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
3374#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
3375#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
3376#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
3377
3378#define ADC_OFR2_SSATE_Pos (31U)
3379#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
3380#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
3381
3382
3383/******************** Bit definition for ADC_OFR3 register ********************/
3384#define ADC_OFR3_OFFSET3_Pos (0U)
3385#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
3386#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
3387#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
3388#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
3389#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
3390#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
3391#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
3392#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
3393#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
3394#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
3395#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
3396#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
3397#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
3398#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
3399#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
3400#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
3401#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
3402#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
3403#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
3404#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
3405#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
3406#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
3407#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
3408#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
3409#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
3410#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
3411#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
3412#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
3413
3414#define ADC_OFR3_OFFSET3_CH_Pos (26U)
3415#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
3416#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
3417#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
3418#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
3419#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
3420#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
3421#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
3422
3423#define ADC_OFR3_SSATE_Pos (31U)
3424#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
3425#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
3426
3427
3428/******************** Bit definition for ADC_OFR4 register ********************/
3429#define ADC_OFR4_OFFSET4_Pos (0U)
3430#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
3431#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
3432#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
3433#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
3434#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
3435#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
3436#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
3437#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
3438#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
3439#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
3440#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
3441#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
3442#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
3443#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
3444#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
3445#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
3446#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
3447#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
3448#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
3449#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
3450#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
3451#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
3452#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
3453#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
3454#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
3455#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
3456#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
3457#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
3458
3459#define ADC_OFR4_OFFSET4_CH_Pos (26U)
3460#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
3461#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
3462#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
3463#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
3464#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
3465#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
3466#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
3467
3468#define ADC_OFR4_SSATE_Pos (31U)
3469#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
3470#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
3471
3472
3473/******************** Bit definition for ADC_JDR1 register ********************/
3474#define ADC_JDR1_JDATA_Pos (0U)
3475#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
3476#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
3477#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
3478#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
3479#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
3480#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
3481#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
3482#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
3483#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
3484#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
3485#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
3486#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
3487#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
3488#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
3489#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
3490#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
3491#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
3492#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
3493#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
3494#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
3495#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
3496#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
3497#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
3498#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
3499#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
3500#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
3501#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
3502#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
3503#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
3504#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
3505#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
3506#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
3507#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
3508#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
3509
3510/******************** Bit definition for ADC_JDR2 register ********************/
3511#define ADC_JDR2_JDATA_Pos (0U)
3512#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
3513#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
3514#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
3515#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
3516#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
3517#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
3518#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
3519#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
3520#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
3521#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
3522#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
3523#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
3524#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
3525#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
3526#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
3527#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
3528#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
3529#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
3530#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
3531#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
3532#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
3533#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
3534#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
3535#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
3536#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
3537#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
3538#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
3539#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
3540#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
3541#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
3542#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
3543#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
3544#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
3545#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
3546
3547/******************** Bit definition for ADC_JDR3 register ********************/
3548#define ADC_JDR3_JDATA_Pos (0U)
3549#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
3550#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
3551#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
3552#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
3553#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
3554#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
3555#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
3556#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
3557#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
3558#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
3559#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
3560#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
3561#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
3562#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
3563#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
3564#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
3565#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
3566#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
3567#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
3568#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
3569#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
3570#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
3571#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
3572#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
3573#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
3574#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
3575#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
3576#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
3577#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
3578#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
3579#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
3580#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
3581#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
3582#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
3583
3584/******************** Bit definition for ADC_JDR4 register ********************/
3585#define ADC_JDR4_JDATA_Pos (0U)
3586#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
3587#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
3588#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
3589#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
3590#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
3591#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
3592#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
3593#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
3594#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
3595#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
3596#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
3597#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
3598#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
3599#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
3600#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
3601#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
3602#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
3603#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
3604#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
3605#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
3606#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
3607#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
3608#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
3609#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
3610#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
3611#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
3612#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
3613#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
3614#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
3615#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
3616#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
3617#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
3618#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
3619#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
3620
3621/******************** Bit definition for ADC_AWD2CR register ********************/
3622#define ADC_AWD2CR_AWD2CH_Pos (0U)
3623#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
3624#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3625#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
3626#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
3627#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
3628#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
3629#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
3630#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
3631#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
3632#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
3633#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
3634#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
3635#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
3636#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
3637#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
3638#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
3639#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
3640#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
3641#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
3642#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
3643#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
3644#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
3645
3646/******************** Bit definition for ADC_AWD3CR register ********************/
3647#define ADC_AWD3CR_AWD3CH_Pos (0U)
3648#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
3649#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3650#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
3651#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
3652#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
3653#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
3654#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
3655#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
3656#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
3657#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
3658#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
3659#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
3660#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
3661#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
3662#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
3663#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
3664#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
3665#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
3666#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
3667#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
3668#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
3669#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
3670
3671/******************** Bit definition for ADC_DIFSEL register ********************/
3672#define ADC_DIFSEL_DIFSEL_Pos (0U)
3673#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
3674#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
3675#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
3676#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
3677#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
3678#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
3679#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
3680#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
3681#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
3682#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
3683#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
3684#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
3685#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
3686#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
3687#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
3688#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
3689#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
3690#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
3691#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
3692#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
3693#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
3694#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
3695
3696/******************** Bit definition for ADC_CALFACT register ********************/
3697#define ADC_CALFACT_CALFACT_S_Pos (0U)
3698#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
3699#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
3700#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
3701#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
3702#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
3703#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
3704#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
3705#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
3706#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
3707#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
3708#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
3709#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
3710#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
3711#define ADC_CALFACT_CALFACT_D_Pos (16U)
3712#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
3713#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
3714#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
3715#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
3716#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
3717#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
3718#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
3719#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
3720#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
3721#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
3722#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
3723#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
3724#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
3725
3726/******************** Bit definition for ADC_CALFACT2 register ********************/
3727#define ADC_CALFACT2_LINCALFACT_Pos (0U)
3728#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
3729#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
3730#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
3731#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
3732#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
3733#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
3734#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
3735#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
3736#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
3737#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
3738#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
3739#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
3740#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
3741#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
3742#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
3743#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
3744#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
3745#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
3746#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
3747#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
3748#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
3749#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
3750#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
3751#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
3752#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
3753#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
3754#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
3755#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
3756#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
3757#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
3758#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
3759#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
3760
3761/************************* ADC Common registers *****************************/
3762/******************** Bit definition for ADC_CSR register ********************/
3763#define ADC_CSR_ADRDY_MST_Pos (0U)
3764#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
3765#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
3766#define ADC_CSR_EOSMP_MST_Pos (1U)
3767#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
3768#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
3769#define ADC_CSR_EOC_MST_Pos (2U)
3770#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
3771#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
3772#define ADC_CSR_EOS_MST_Pos (3U)
3773#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
3774#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
3775#define ADC_CSR_OVR_MST_Pos (4U)
3776#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
3777#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
3778#define ADC_CSR_JEOC_MST_Pos (5U)
3779#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
3780#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
3781#define ADC_CSR_JEOS_MST_Pos (6U)
3782#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
3783#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
3784#define ADC_CSR_AWD1_MST_Pos (7U)
3785#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
3786#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
3787#define ADC_CSR_AWD2_MST_Pos (8U)
3788#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
3789#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
3790#define ADC_CSR_AWD3_MST_Pos (9U)
3791#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
3792#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
3793#define ADC_CSR_JQOVF_MST_Pos (10U)
3794#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
3795#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
3796#define ADC_CSR_ADRDY_SLV_Pos (16U)
3797#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
3798#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
3799#define ADC_CSR_EOSMP_SLV_Pos (17U)
3800#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
3801#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
3802#define ADC_CSR_EOC_SLV_Pos (18U)
3803#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
3804#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
3805#define ADC_CSR_EOS_SLV_Pos (19U)
3806#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
3807#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
3808#define ADC_CSR_OVR_SLV_Pos (20U)
3809#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
3810#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
3811#define ADC_CSR_JEOC_SLV_Pos (21U)
3812#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
3813#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
3814#define ADC_CSR_JEOS_SLV_Pos (22U)
3815#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
3816#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
3817#define ADC_CSR_AWD1_SLV_Pos (23U)
3818#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
3819#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
3820#define ADC_CSR_AWD2_SLV_Pos (24U)
3821#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
3822#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
3823#define ADC_CSR_AWD3_SLV_Pos (25U)
3824#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
3825#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
3826#define ADC_CSR_JQOVF_SLV_Pos (26U)
3827#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
3828#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
3829
3830/******************** Bit definition for ADC_CCR register ********************/
3831#define ADC_CCR_DUAL_Pos (0U)
3832#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
3833#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
3834#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
3835#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
3836#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
3837#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
3838#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
3839
3840#define ADC_CCR_DELAY_Pos (8U)
3841#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
3842#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
3843#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
3844#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
3845#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
3846#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
3847
3848
3849#define ADC_CCR_DAMDF_Pos (14U)
3850#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
3851#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
3852#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
3853#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
3854
3855#define ADC_CCR_CKMODE_Pos (16U)
3856#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
3857#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
3858#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
3859#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
3860
3861#define ADC_CCR_PRESC_Pos (18U)
3862#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
3863#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
3864#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
3865#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
3866#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
3867#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
3868
3869#define ADC_CCR_VREFEN_Pos (22U)
3870#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
3871#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
3872#define ADC_CCR_TSEN_Pos (23U)
3873#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
3874#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
3875#define ADC_CCR_VBATEN_Pos (24U)
3876#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
3877#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
3878
3879/******************** Bit definition for ADC_CDR register *******************/
3880#define ADC_CDR_RDATA_MST_Pos (0U)
3881#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
3882#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
3883
3884#define ADC_CDR_RDATA_SLV_Pos (16U)
3885#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
3886#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
3887
3888/******************** Bit definition for ADC_CDR2 register ******************/
3889#define ADC_CDR2_RDATA_ALT_Pos (0U)
3890#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
3891#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */
3892
3893
3894/******************************************************************************/
3895/* */
3896/* VREFBUF */
3897/* */
3898/******************************************************************************/
3899/******************* Bit definition for VREFBUF_CSR register ****************/
3900#define VREFBUF_CSR_ENVR_Pos (0U)
3901#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
3902#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
3903#define VREFBUF_CSR_HIZ_Pos (1U)
3904#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
3905#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
3906#define VREFBUF_CSR_VRR_Pos (3U)
3907#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
3908#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
3909#define VREFBUF_CSR_VRS_Pos (4U)
3910#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
3911#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
3912
3913#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
3914#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
3915#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
3916#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
3917#define VREFBUF_CSR_VRS_OUT3_Pos (5U)
3918#define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos) /*!< 0x00000020 */
3919#define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk /*!<Voltage reference VREF_OUT3 */
3920#define VREFBUF_CSR_VRS_OUT4_Pos (4U)
3921#define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos) /*!< 0x00000030 */
3922#define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk /*!<Voltage reference VREF_OUT4 */
3923
3924/******************* Bit definition for VREFBUF_CCR register ****************/
3925#define VREFBUF_CCR_TRIM_Pos (0U)
3926#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
3927#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
3928
3929/******************************************************************************/
3930/* */
3931/* Flexible Datarate Controller Area Network */
3932/* */
3933/******************************************************************************/
3934/*!<FDCAN control and status registers */
3935/***************** Bit definition for FDCAN_CREL register *******************/
3936#define FDCAN_CREL_DAY_Pos (0U)
3937#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
3938#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
3939#define FDCAN_CREL_MON_Pos (8U)
3940#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
3941#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
3942#define FDCAN_CREL_YEAR_Pos (16U)
3943#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
3944#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
3945#define FDCAN_CREL_SUBSTEP_Pos (20U)
3946#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
3947#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
3948#define FDCAN_CREL_STEP_Pos (24U)
3949#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
3950#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
3951#define FDCAN_CREL_REL_Pos (28U)
3952#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
3953#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
3954
3955/***************** Bit definition for FDCAN_ENDN register *******************/
3956#define FDCAN_ENDN_ETV_Pos (0U)
3957#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
3958#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
3959
3960/***************** Bit definition for FDCAN_DBTP register *******************/
3961#define FDCAN_DBTP_DSJW_Pos (0U)
3962#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
3963#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
3964#define FDCAN_DBTP_DTSEG2_Pos (4U)
3965#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
3966#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
3967#define FDCAN_DBTP_DTSEG1_Pos (8U)
3968#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
3969#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
3970#define FDCAN_DBTP_DBRP_Pos (16U)
3971#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
3972#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
3973#define FDCAN_DBTP_TDC_Pos (23U)
3974#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
3975#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
3976
3977/***************** Bit definition for FDCAN_TEST register *******************/
3978#define FDCAN_TEST_LBCK_Pos (4U)
3979#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
3980#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
3981#define FDCAN_TEST_TX_Pos (5U)
3982#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
3983#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
3984#define FDCAN_TEST_RX_Pos (7U)
3985#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
3986#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
3987
3988/***************** Bit definition for FDCAN_RWD register ********************/
3989#define FDCAN_RWD_WDC_Pos (0U)
3990#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
3991#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
3992#define FDCAN_RWD_WDV_Pos (8U)
3993#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
3994#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
3995
3996/***************** Bit definition for FDCAN_CCCR register ********************/
3997#define FDCAN_CCCR_INIT_Pos (0U)
3998#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
3999#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
4000#define FDCAN_CCCR_CCE_Pos (1U)
4001#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
4002#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
4003#define FDCAN_CCCR_ASM_Pos (2U)
4004#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
4005#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
4006#define FDCAN_CCCR_CSA_Pos (3U)
4007#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
4008#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
4009#define FDCAN_CCCR_CSR_Pos (4U)
4010#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
4011#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
4012#define FDCAN_CCCR_MON_Pos (5U)
4013#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
4014#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
4015#define FDCAN_CCCR_DAR_Pos (6U)
4016#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
4017#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
4018#define FDCAN_CCCR_TEST_Pos (7U)
4019#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
4020#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
4021#define FDCAN_CCCR_FDOE_Pos (8U)
4022#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
4023#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
4024#define FDCAN_CCCR_BRSE_Pos (9U)
4025#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
4026#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
4027#define FDCAN_CCCR_PXHD_Pos (12U)
4028#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
4029#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
4030#define FDCAN_CCCR_EFBI_Pos (13U)
4031#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
4032#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
4033#define FDCAN_CCCR_TXP_Pos (14U)
4034#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
4035#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
4036#define FDCAN_CCCR_NISO_Pos (15U)
4037#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
4038#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
4039
4040/***************** Bit definition for FDCAN_NBTP register ********************/
4041#define FDCAN_NBTP_NTSEG2_Pos (0U)
4042#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
4043#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
4044#define FDCAN_NBTP_NTSEG1_Pos (8U)
4045#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
4046#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
4047#define FDCAN_NBTP_NBRP_Pos (16U)
4048#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
4049#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
4050#define FDCAN_NBTP_NSJW_Pos (25U)
4051#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
4052#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
4053
4054/***************** Bit definition for FDCAN_TSCC register ********************/
4055#define FDCAN_TSCC_TSS_Pos (0U)
4056#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
4057#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
4058#define FDCAN_TSCC_TCP_Pos (16U)
4059#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
4060#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
4061
4062/***************** Bit definition for FDCAN_TSCV register ********************/
4063#define FDCAN_TSCV_TSC_Pos (0U)
4064#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
4065#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
4066
4067/***************** Bit definition for FDCAN_TOCC register ********************/
4068#define FDCAN_TOCC_ETOC_Pos (0U)
4069#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
4070#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
4071#define FDCAN_TOCC_TOS_Pos (1U)
4072#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
4073#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
4074#define FDCAN_TOCC_TOP_Pos (16U)
4075#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
4076#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
4077
4078/***************** Bit definition for FDCAN_TOCV register ********************/
4079#define FDCAN_TOCV_TOC_Pos (0U)
4080#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
4081#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
4082
4083/***************** Bit definition for FDCAN_ECR register *********************/
4084#define FDCAN_ECR_TEC_Pos (0U)
4085#define FDCAN_ECR_TEC_Msk (0xFUL << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */
4086#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
4087#define FDCAN_ECR_REC_Pos (8U)
4088#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
4089#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
4090#define FDCAN_ECR_RP_Pos (15U)
4091#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
4092#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
4093#define FDCAN_ECR_CEL_Pos (16U)
4094#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
4095#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
4096
4097/***************** Bit definition for FDCAN_PSR register *********************/
4098#define FDCAN_PSR_LEC_Pos (0U)
4099#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
4100#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
4101#define FDCAN_PSR_ACT_Pos (3U)
4102#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
4103#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
4104#define FDCAN_PSR_EP_Pos (5U)
4105#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
4106#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
4107#define FDCAN_PSR_EW_Pos (6U)
4108#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
4109#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
4110#define FDCAN_PSR_BO_Pos (7U)
4111#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
4112#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
4113#define FDCAN_PSR_DLEC_Pos (8U)
4114#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
4115#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
4116#define FDCAN_PSR_RESI_Pos (11U)
4117#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
4118#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
4119#define FDCAN_PSR_RBRS_Pos (12U)
4120#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
4121#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
4122#define FDCAN_PSR_REDL_Pos (13U)
4123#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
4124#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
4125#define FDCAN_PSR_PXE_Pos (14U)
4126#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
4127#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
4128#define FDCAN_PSR_TDCV_Pos (16U)
4129#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
4130#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
4131
4132/***************** Bit definition for FDCAN_TDCR register ********************/
4133#define FDCAN_TDCR_TDCF_Pos (0U)
4134#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
4135#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
4136#define FDCAN_TDCR_TDCO_Pos (8U)
4137#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
4138#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
4139
4140/***************** Bit definition for FDCAN_IR register **********************/
4141#define FDCAN_IR_RF0N_Pos (0U)
4142#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
4143#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
4144#define FDCAN_IR_RF0W_Pos (1U)
4145#define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */
4146#define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */
4147#define FDCAN_IR_RF0F_Pos (2U)
4148#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */
4149#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
4150#define FDCAN_IR_RF0L_Pos (3U)
4151#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */
4152#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4153#define FDCAN_IR_RF1N_Pos (4U)
4154#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */
4155#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
4156#define FDCAN_IR_RF1W_Pos (5U)
4157#define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */
4158#define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */
4159#define FDCAN_IR_RF1F_Pos (6U)
4160#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */
4161#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
4162#define FDCAN_IR_RF1L_Pos (7U)
4163#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */
4164#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4165#define FDCAN_IR_HPM_Pos (8U)
4166#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */
4167#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
4168#define FDCAN_IR_TC_Pos (9U)
4169#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000200 */
4170#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
4171#define FDCAN_IR_TCF_Pos (10U)
4172#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */
4173#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
4174#define FDCAN_IR_TFE_Pos (11U)
4175#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */
4176#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
4177#define FDCAN_IR_TEFN_Pos (12U)
4178#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */
4179#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
4180#define FDCAN_IR_TEFW_Pos (13U)
4181#define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */
4182#define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */
4183#define FDCAN_IR_TEFF_Pos (14U)
4184#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */
4185#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
4186#define FDCAN_IR_TEFL_Pos (15U)
4187#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */
4188#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4189#define FDCAN_IR_TSW_Pos (16U)
4190#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */
4191#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
4192#define FDCAN_IR_MRAF_Pos (17U)
4193#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */
4194#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
4195#define FDCAN_IR_TOO_Pos (18U)
4196#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */
4197#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
4198#define FDCAN_IR_DRX_Pos (19U)
4199#define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */
4200#define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */
4201#define FDCAN_IR_ELO_Pos (22U)
4202#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */
4203#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
4204#define FDCAN_IR_EP_Pos (23U)
4205#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00800000 */
4206#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
4207#define FDCAN_IR_EW_Pos (24U)
4208#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x01000000 */
4209#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
4210#define FDCAN_IR_BO_Pos (25U)
4211#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x02000000 */
4212#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
4213#define FDCAN_IR_WDI_Pos (26U)
4214#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */
4215#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
4216#define FDCAN_IR_PEA_Pos (27U)
4217#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */
4218#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
4219#define FDCAN_IR_PED_Pos (28U)
4220#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x10000000 */
4221#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
4222#define FDCAN_IR_ARA_Pos (29U)
4223#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */
4224#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
4225
4226/***************** Bit definition for FDCAN_IE register **********************/
4227#define FDCAN_IE_RF0NE_Pos (0U)
4228#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
4229#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
4230#define FDCAN_IE_RF0WE_Pos (1U)
4231#define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */
4232#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */
4233#define FDCAN_IE_RF0FE_Pos (2U)
4234#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */
4235#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
4236#define FDCAN_IE_RF0LE_Pos (3U)
4237#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */
4238#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
4239#define FDCAN_IE_RF1NE_Pos (4U)
4240#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */
4241#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
4242#define FDCAN_IE_RF1WE_Pos (5U)
4243#define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */
4244#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */
4245#define FDCAN_IE_RF1FE_Pos (6U)
4246#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */
4247#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
4248#define FDCAN_IE_RF1LE_Pos (7U)
4249#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */
4250#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
4251#define FDCAN_IE_HPME_Pos (8U)
4252#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */
4253#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
4254#define FDCAN_IE_TCE_Pos (9U)
4255#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */
4256#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
4257#define FDCAN_IE_TCFE_Pos (10U)
4258#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */
4259#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */
4260#define FDCAN_IE_TFEE_Pos (11U)
4261#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */
4262#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
4263#define FDCAN_IE_TEFNE_Pos (12U)
4264#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */
4265#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
4266#define FDCAN_IE_TEFWE_Pos (13U)
4267#define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */
4268#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */
4269#define FDCAN_IE_TEFFE_Pos (14U)
4270#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */
4271#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
4272#define FDCAN_IE_TEFLE_Pos (15U)
4273#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */
4274#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
4275#define FDCAN_IE_TSWE_Pos (16U)
4276#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */
4277#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
4278#define FDCAN_IE_MRAFE_Pos (17U)
4279#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */
4280#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
4281#define FDCAN_IE_TOOE_Pos (18U)
4282#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */
4283#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
4284#define FDCAN_IE_DRXE_Pos (19U)
4285#define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */
4286#define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */
4287#define FDCAN_IE_BECE_Pos (20U)
4288#define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos) /*!< 0x00100000 */
4289#define FDCAN_IE_BECE FDCAN_IE_BECE_Msk /*!<Bit Error Corrected Interrupt Enable */
4290#define FDCAN_IE_BEUE_Pos (21U)
4291#define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos) /*!< 0x00200000 */
4292#define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Enable */
4293#define FDCAN_IE_ELOE_Pos (22U)
4294#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */
4295#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
4296#define FDCAN_IE_EPE_Pos (23U)
4297#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */
4298#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
4299#define FDCAN_IE_EWE_Pos (24U)
4300#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */
4301#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
4302#define FDCAN_IE_BOE_Pos (25U)
4303#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */
4304#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
4305#define FDCAN_IE_WDIE_Pos (26U)
4306#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */
4307#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
4308#define FDCAN_IE_PEAE_Pos (27U)
4309#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */
4310#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */
4311#define FDCAN_IE_PEDE_Pos (28U)
4312#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */
4313#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
4314#define FDCAN_IE_ARAE_Pos (29U)
4315#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */
4316#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
4317
4318/***************** Bit definition for FDCAN_ILS register **********************/
4319#define FDCAN_ILS_RF0NL_Pos (0U)
4320#define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */
4321#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */
4322#define FDCAN_ILS_RF0WL_Pos (1U)
4323#define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */
4324#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */
4325#define FDCAN_ILS_RF0FL_Pos (2U)
4326#define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */
4327#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */
4328#define FDCAN_ILS_RF0LL_Pos (3U)
4329#define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */
4330#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */
4331#define FDCAN_ILS_RF1NL_Pos (4U)
4332#define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */
4333#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */
4334#define FDCAN_ILS_RF1WL_Pos (5U)
4335#define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */
4336#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */
4337#define FDCAN_ILS_RF1FL_Pos (6U)
4338#define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */
4339#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */
4340#define FDCAN_ILS_RF1LL_Pos (7U)
4341#define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */
4342#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */
4343#define FDCAN_ILS_HPML_Pos (8U)
4344#define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */
4345#define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */
4346#define FDCAN_ILS_TCL_Pos (9U)
4347#define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */
4348#define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */
4349#define FDCAN_ILS_TCFL_Pos (10U)
4350#define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */
4351#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */
4352#define FDCAN_ILS_TFEL_Pos (11U)
4353#define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */
4354#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */
4355#define FDCAN_ILS_TEFNL_Pos (12U)
4356#define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */
4357#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */
4358#define FDCAN_ILS_TEFWL_Pos (13U)
4359#define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */
4360#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */
4361#define FDCAN_ILS_TEFFL_Pos (14U)
4362#define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */
4363#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */
4364#define FDCAN_ILS_TEFLL_Pos (15U)
4365#define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */
4366#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */
4367#define FDCAN_ILS_TSWL_Pos (16U)
4368#define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */
4369#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */
4370#define FDCAN_ILS_MRAFE_Pos (17U)
4371#define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos) /*!< 0x00020000 */
4372#define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk /*!<Message RAM Access Failure Line */
4373#define FDCAN_ILS_TOOE_Pos (18U)
4374#define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos) /*!< 0x00040000 */
4375#define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk /*!<Timeout Occurred Line */
4376#define FDCAN_ILS_DRXE_Pos (19U)
4377#define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos) /*!< 0x00080000 */
4378#define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Line */
4379#define FDCAN_ILS_BECE_Pos (20U)
4380#define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos) /*!< 0x00100000 */
4381#define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk /*!<Bit Error Corrected Interrupt Line */
4382#define FDCAN_ILS_BEUE_Pos (21U)
4383#define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos) /*!< 0x00200000 */
4384#define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Line */
4385#define FDCAN_ILS_ELOE_Pos (22U)
4386#define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos) /*!< 0x00400000 */
4387#define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk /*!<Error Logging Overflow Line */
4388#define FDCAN_ILS_EPE_Pos (23U)
4389#define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos) /*!< 0x00800000 */
4390#define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk /*!<Error Passive Line */
4391#define FDCAN_ILS_EWE_Pos (24U)
4392#define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos) /*!< 0x01000000 */
4393#define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk /*!<Warning Status Line */
4394#define FDCAN_ILS_BOE_Pos (25U)
4395#define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos) /*!< 0x02000000 */
4396#define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk /*!<Bus_Off Status Line */
4397#define FDCAN_ILS_WDIE_Pos (26U)
4398#define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos) /*!< 0x04000000 */
4399#define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk /*!<Watchdog Interrupt Line */
4400#define FDCAN_ILS_PEAE_Pos (27U)
4401#define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos) /*!< 0x08000000 */
4402#define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk /*!<Protocol Error in Arbitration Phase Line */
4403#define FDCAN_ILS_PEDE_Pos (28U)
4404#define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos) /*!< 0x10000000 */
4405#define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk /*!<Protocol Error in Data Phase Line */
4406#define FDCAN_ILS_ARAE_Pos (29U)
4407#define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos) /*!< 0x20000000 */
4408#define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk /*!<Access to Reserved Address Line */
4409
4410/***************** Bit definition for FDCAN_ILE register **********************/
4411#define FDCAN_ILE_EINT0_Pos (0U)
4412#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
4413#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
4414#define FDCAN_ILE_EINT1_Pos (1U)
4415#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
4416#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
4417
4418/***************** Bit definition for FDCAN_GFC register **********************/
4419#define FDCAN_GFC_RRFE_Pos (0U)
4420#define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */
4421#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */
4422#define FDCAN_GFC_RRFS_Pos (1U)
4423#define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */
4424#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */
4425#define FDCAN_GFC_ANFE_Pos (2U)
4426#define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */
4427#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
4428#define FDCAN_GFC_ANFS_Pos (4U)
4429#define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */
4430#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
4431
4432/***************** Bit definition for FDCAN_SIDFC register ********************/
4433#define FDCAN_SIDFC_FLSSA_Pos (2U)
4434#define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */
4435#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */
4436#define FDCAN_SIDFC_LSS_Pos (16U)
4437#define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */
4438#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */
4439
4440/***************** Bit definition for FDCAN_XIDFC register ********************/
4441#define FDCAN_XIDFC_FLESA_Pos (2U)
4442#define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
4443#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */
4444#define FDCAN_XIDFC_LSE_Pos (16U)
4445#define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos) /*!< 0x007F0000 */
4446#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */
4447
4448/***************** Bit definition for FDCAN_XIDAM register ********************/
4449#define FDCAN_XIDAM_EIDM_Pos (0U)
4450#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
4451#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
4452
4453/***************** Bit definition for FDCAN_HPMS register *********************/
4454#define FDCAN_HPMS_BIDX_Pos (0U)
4455#define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */
4456#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
4457#define FDCAN_HPMS_MSI_Pos (6U)
4458#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
4459#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
4460#define FDCAN_HPMS_FIDX_Pos (8U)
4461#define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */
4462#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
4463#define FDCAN_HPMS_FLST_Pos (15U)
4464#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
4465#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
4466
4467/***************** Bit definition for FDCAN_NDAT1 register ********************/
4468#define FDCAN_NDAT1_ND0_Pos (0U)
4469#define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */
4470#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */
4471#define FDCAN_NDAT1_ND1_Pos (1U)
4472#define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */
4473#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */
4474#define FDCAN_NDAT1_ND2_Pos (2U)
4475#define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */
4476#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */
4477#define FDCAN_NDAT1_ND3_Pos (3U)
4478#define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */
4479#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */
4480#define FDCAN_NDAT1_ND4_Pos (4U)
4481#define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */
4482#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */
4483#define FDCAN_NDAT1_ND5_Pos (5U)
4484#define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */
4485#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */
4486#define FDCAN_NDAT1_ND6_Pos (6U)
4487#define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */
4488#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */
4489#define FDCAN_NDAT1_ND7_Pos (7U)
4490#define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */
4491#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */
4492#define FDCAN_NDAT1_ND8_Pos (8U)
4493#define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */
4494#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */
4495#define FDCAN_NDAT1_ND9_Pos (9U)
4496#define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */
4497#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */
4498#define FDCAN_NDAT1_ND10_Pos (10U)
4499#define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */
4500#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */
4501#define FDCAN_NDAT1_ND11_Pos (11U)
4502#define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */
4503#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */
4504#define FDCAN_NDAT1_ND12_Pos (12U)
4505#define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */
4506#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */
4507#define FDCAN_NDAT1_ND13_Pos (13U)
4508#define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */
4509#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */
4510#define FDCAN_NDAT1_ND14_Pos (14U)
4511#define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */
4512#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */
4513#define FDCAN_NDAT1_ND15_Pos (15U)
4514#define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */
4515#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */
4516#define FDCAN_NDAT1_ND16_Pos (16U)
4517#define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */
4518#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */
4519#define FDCAN_NDAT1_ND17_Pos (17U)
4520#define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */
4521#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */
4522#define FDCAN_NDAT1_ND18_Pos (18U)
4523#define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */
4524#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */
4525#define FDCAN_NDAT1_ND19_Pos (19U)
4526#define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */
4527#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */
4528#define FDCAN_NDAT1_ND20_Pos (20U)
4529#define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */
4530#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */
4531#define FDCAN_NDAT1_ND21_Pos (21U)
4532#define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */
4533#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */
4534#define FDCAN_NDAT1_ND22_Pos (22U)
4535#define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */
4536#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */
4537#define FDCAN_NDAT1_ND23_Pos (23U)
4538#define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */
4539#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */
4540#define FDCAN_NDAT1_ND24_Pos (24U)
4541#define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */
4542#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */
4543#define FDCAN_NDAT1_ND25_Pos (25U)
4544#define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */
4545#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */
4546#define FDCAN_NDAT1_ND26_Pos (26U)
4547#define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */
4548#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */
4549#define FDCAN_NDAT1_ND27_Pos (27U)
4550#define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */
4551#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */
4552#define FDCAN_NDAT1_ND28_Pos (28U)
4553#define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */
4554#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */
4555#define FDCAN_NDAT1_ND29_Pos (29U)
4556#define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */
4557#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */
4558#define FDCAN_NDAT1_ND30_Pos (30U)
4559#define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */
4560#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */
4561#define FDCAN_NDAT1_ND31_Pos (31U)
4562#define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */
4563#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */
4564
4565/***************** Bit definition for FDCAN_NDAT2 register ********************/
4566#define FDCAN_NDAT2_ND32_Pos (0U)
4567#define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */
4568#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */
4569#define FDCAN_NDAT2_ND33_Pos (1U)
4570#define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */
4571#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */
4572#define FDCAN_NDAT2_ND34_Pos (2U)
4573#define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */
4574#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */
4575#define FDCAN_NDAT2_ND35_Pos (3U)
4576#define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */
4577#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */
4578#define FDCAN_NDAT2_ND36_Pos (4U)
4579#define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */
4580#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */
4581#define FDCAN_NDAT2_ND37_Pos (5U)
4582#define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */
4583#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */
4584#define FDCAN_NDAT2_ND38_Pos (6U)
4585#define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */
4586#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */
4587#define FDCAN_NDAT2_ND39_Pos (7U)
4588#define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */
4589#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */
4590#define FDCAN_NDAT2_ND40_Pos (8U)
4591#define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */
4592#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */
4593#define FDCAN_NDAT2_ND41_Pos (9U)
4594#define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */
4595#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */
4596#define FDCAN_NDAT2_ND42_Pos (10U)
4597#define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */
4598#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */
4599#define FDCAN_NDAT2_ND43_Pos (11U)
4600#define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */
4601#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */
4602#define FDCAN_NDAT2_ND44_Pos (12U)
4603#define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */
4604#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */
4605#define FDCAN_NDAT2_ND45_Pos (13U)
4606#define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */
4607#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */
4608#define FDCAN_NDAT2_ND46_Pos (14U)
4609#define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */
4610#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */
4611#define FDCAN_NDAT2_ND47_Pos (15U)
4612#define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */
4613#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */
4614#define FDCAN_NDAT2_ND48_Pos (16U)
4615#define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */
4616#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */
4617#define FDCAN_NDAT2_ND49_Pos (17U)
4618#define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */
4619#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */
4620#define FDCAN_NDAT2_ND50_Pos (18U)
4621#define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */
4622#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */
4623#define FDCAN_NDAT2_ND51_Pos (19U)
4624#define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */
4625#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */
4626#define FDCAN_NDAT2_ND52_Pos (20U)
4627#define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */
4628#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */
4629#define FDCAN_NDAT2_ND53_Pos (21U)
4630#define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */
4631#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */
4632#define FDCAN_NDAT2_ND54_Pos (22U)
4633#define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */
4634#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */
4635#define FDCAN_NDAT2_ND55_Pos (23U)
4636#define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */
4637#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */
4638#define FDCAN_NDAT2_ND56_Pos (24U)
4639#define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */
4640#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */
4641#define FDCAN_NDAT2_ND57_Pos (25U)
4642#define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */
4643#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */
4644#define FDCAN_NDAT2_ND58_Pos (26U)
4645#define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */
4646#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */
4647#define FDCAN_NDAT2_ND59_Pos (27U)
4648#define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */
4649#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */
4650#define FDCAN_NDAT2_ND60_Pos (28U)
4651#define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */
4652#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */
4653#define FDCAN_NDAT2_ND61_Pos (29U)
4654#define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */
4655#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */
4656#define FDCAN_NDAT2_ND62_Pos (30U)
4657#define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */
4658#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */
4659#define FDCAN_NDAT2_ND63_Pos (31U)
4660#define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */
4661#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */
4662
4663/***************** Bit definition for FDCAN_RXF0C register ********************/
4664#define FDCAN_RXF0C_F0SA_Pos (2U)
4665#define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */
4666#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */
4667#define FDCAN_RXF0C_F0S_Pos (16U)
4668#define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */
4669#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */
4670#define FDCAN_RXF0C_F0WM_Pos (24U)
4671#define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */
4672#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */
4673#define FDCAN_RXF0C_F0OM_Pos (31U)
4674#define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */
4675#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */
4676
4677/***************** Bit definition for FDCAN_RXF0S register ********************/
4678#define FDCAN_RXF0S_F0FL_Pos (0U)
4679#define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */
4680#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
4681#define FDCAN_RXF0S_F0GI_Pos (8U)
4682#define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */
4683#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
4684#define FDCAN_RXF0S_F0PI_Pos (16U)
4685#define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */
4686#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
4687#define FDCAN_RXF0S_F0F_Pos (24U)
4688#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
4689#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
4690#define FDCAN_RXF0S_RF0L_Pos (25U)
4691#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
4692#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4693
4694/***************** Bit definition for FDCAN_RXF0A register ********************/
4695#define FDCAN_RXF0A_F0AI_Pos (0U)
4696#define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */
4697#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
4698
4699/***************** Bit definition for FDCAN_RXBC register ********************/
4700#define FDCAN_RXBC_RBSA_Pos (2U)
4701#define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos) /*!< 0x0000FFFC */
4702#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */
4703
4704/***************** Bit definition for FDCAN_RXF1C register ********************/
4705#define FDCAN_RXF1C_F1SA_Pos (2U)
4706#define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos) /*!< 0x0000FFFC */
4707#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */
4708#define FDCAN_RXF1C_F1S_Pos (16U)
4709#define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */
4710#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */
4711#define FDCAN_RXF1C_F1WM_Pos (24U)
4712#define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */
4713#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */
4714#define FDCAN_RXF1C_F1OM_Pos (31U)
4715#define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */
4716#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */
4717
4718/***************** Bit definition for FDCAN_RXF1S register ********************/
4719#define FDCAN_RXF1S_F1FL_Pos (0U)
4720#define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */
4721#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
4722#define FDCAN_RXF1S_F1GI_Pos (8U)
4723#define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */
4724#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
4725#define FDCAN_RXF1S_F1PI_Pos (16U)
4726#define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */
4727#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
4728#define FDCAN_RXF1S_F1F_Pos (24U)
4729#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
4730#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
4731#define FDCAN_RXF1S_RF1L_Pos (25U)
4732#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
4733#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4734
4735/***************** Bit definition for FDCAN_RXF1A register ********************/
4736#define FDCAN_RXF1A_F1AI_Pos (0U)
4737#define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */
4738#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
4739
4740/***************** Bit definition for FDCAN_RXESC register ********************/
4741#define FDCAN_RXESC_F0DS_Pos (0U)
4742#define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */
4743#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */
4744#define FDCAN_RXESC_F1DS_Pos (4U)
4745#define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */
4746#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */
4747#define FDCAN_RXESC_RBDS_Pos (8U)
4748#define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */
4749#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */
4750
4751/***************** Bit definition for FDCAN_TXBC register *********************/
4752#define FDCAN_TXBC_TBSA_Pos (2U)
4753#define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos) /*!< 0x0000FFFC */
4754#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */
4755#define FDCAN_TXBC_NDTB_Pos (16U)
4756#define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */
4757#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */
4758#define FDCAN_TXBC_TFQS_Pos (24U)
4759#define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */
4760#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */
4761#define FDCAN_TXBC_TFQM_Pos (30U)
4762#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */
4763#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
4764
4765/***************** Bit definition for FDCAN_TXFQS register *********************/
4766#define FDCAN_TXFQS_TFFL_Pos (0U)
4767#define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */
4768#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
4769#define FDCAN_TXFQS_TFGI_Pos (8U)
4770#define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */
4771#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
4772#define FDCAN_TXFQS_TFQPI_Pos (16U)
4773#define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */
4774#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
4775#define FDCAN_TXFQS_TFQF_Pos (21U)
4776#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
4777#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
4778
4779/***************** Bit definition for FDCAN_TXESC register *********************/
4780#define FDCAN_TXESC_TBDS_Pos (0U)
4781#define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */
4782#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */
4783
4784/***************** Bit definition for FDCAN_TXBRP register *********************/
4785#define FDCAN_TXBRP_TRP_Pos (0U)
4786#define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */
4787#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
4788
4789/***************** Bit definition for FDCAN_TXBAR register *********************/
4790#define FDCAN_TXBAR_AR_Pos (0U)
4791#define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */
4792#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
4793
4794/***************** Bit definition for FDCAN_TXBCR register *********************/
4795#define FDCAN_TXBCR_CR_Pos (0U)
4796#define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */
4797#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
4798
4799/***************** Bit definition for FDCAN_TXBTO register *********************/
4800#define FDCAN_TXBTO_TO_Pos (0U)
4801#define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */
4802#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
4803
4804/***************** Bit definition for FDCAN_TXBCF register *********************/
4805#define FDCAN_TXBCF_CF_Pos (0U)
4806#define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */
4807#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
4808
4809/***************** Bit definition for FDCAN_TXBTIE register ********************/
4810#define FDCAN_TXBTIE_TIE_Pos (0U)
4811#define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */
4812#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
4813
4814/***************** Bit definition for FDCAN_ TXBCIE register *******************/
4815#define FDCAN_TXBCIE_CFIE_Pos (0U)
4816#define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0xFFFFFFFF */
4817#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
4818
4819/***************** Bit definition for FDCAN_TXEFC register *********************/
4820#define FDCAN_TXEFC_EFSA_Pos (2U)
4821#define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos) /*!< 0x0000FFFC */
4822#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */
4823#define FDCAN_TXEFC_EFS_Pos (16U)
4824#define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos) /*!< 0x003F0000 */
4825#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */
4826#define FDCAN_TXEFC_EFWM_Pos (24U)
4827#define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */
4828#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */
4829
4830/***************** Bit definition for FDCAN_TXEFS register *********************/
4831#define FDCAN_TXEFS_EFFL_Pos (0U)
4832#define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */
4833#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
4834#define FDCAN_TXEFS_EFGI_Pos (8U)
4835#define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */
4836#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
4837#define FDCAN_TXEFS_EFPI_Pos (16U)
4838#define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */
4839#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
4840#define FDCAN_TXEFS_EFF_Pos (24U)
4841#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
4842#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
4843#define FDCAN_TXEFS_TEFL_Pos (25U)
4844#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
4845#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4846
4847/***************** Bit definition for FDCAN_TXEFA register *********************/
4848#define FDCAN_TXEFA_EFAI_Pos (0U)
4849#define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */
4850#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
4851
4852/***************** Bit definition for FDCAN_TTTMC register *********************/
4853#define FDCAN_TTTMC_TMSA_Pos (2U)
4854#define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */
4855#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */
4856#define FDCAN_TTTMC_TME_Pos (16U)
4857#define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */
4858#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */
4859
4860/***************** Bit definition for FDCAN_TTRMC register *********************/
4861#define FDCAN_TTRMC_RID_Pos (0U)
4862#define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */
4863#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */
4864#define FDCAN_TTRMC_XTD_Pos (30U)
4865#define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */
4866#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */
4867#define FDCAN_TTRMC_RMPS_Pos (31U)
4868#define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */
4869#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */
4870
4871/***************** Bit definition for FDCAN_TTOCF register *********************/
4872#define FDCAN_TTOCF_OM_Pos (0U)
4873#define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */
4874#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */
4875#define FDCAN_TTOCF_GEN_Pos (3U)
4876#define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */
4877#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */
4878#define FDCAN_TTOCF_TM_Pos (4U)
4879#define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */
4880#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */
4881#define FDCAN_TTOCF_LDSDL_Pos (5U)
4882#define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */
4883#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */
4884#define FDCAN_TTOCF_IRTO_Pos (8U)
4885#define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */
4886#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */
4887#define FDCAN_TTOCF_EECS_Pos (15U)
4888#define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */
4889#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */
4890#define FDCAN_TTOCF_AWL_Pos (16U)
4891#define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */
4892#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */
4893#define FDCAN_TTOCF_EGTF_Pos (24U)
4894#define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */
4895#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */
4896#define FDCAN_TTOCF_ECC_Pos (25U)
4897#define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */
4898#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */
4899#define FDCAN_TTOCF_EVTP_Pos (26U)
4900#define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */
4901#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */
4902
4903/***************** Bit definition for FDCAN_TTMLM register *********************/
4904#define FDCAN_TTMLM_CCM_Pos (0U)
4905#define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */
4906#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */
4907#define FDCAN_TTMLM_CSS_Pos (6U)
4908#define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */
4909#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */
4910#define FDCAN_TTMLM_TXEW_Pos (8U)
4911#define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */
4912#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */
4913#define FDCAN_TTMLM_ENTT_Pos (16U)
4914#define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */
4915#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */
4916
4917/***************** Bit definition for FDCAN_TURCF register *********************/
4918#define FDCAN_TURCF_NCL_Pos (0U)
4919#define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */
4920#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */
4921#define FDCAN_TURCF_DC_Pos (16U)
4922#define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */
4923#define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */
4924#define FDCAN_TURCF_ELT_Pos (31U)
4925#define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */
4926#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */
4927
4928/***************** Bit definition for FDCAN_TTOCN register ********************/
4929#define FDCAN_TTOCN_SGT_Pos (0U)
4930#define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */
4931#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */
4932#define FDCAN_TTOCN_ECS_Pos (1U)
4933#define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */
4934#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */
4935#define FDCAN_TTOCN_SWP_Pos (2U)
4936#define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */
4937#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */
4938#define FDCAN_TTOCN_SWS_Pos (3U)
4939#define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */
4940#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */
4941#define FDCAN_TTOCN_RTIE_Pos (5U)
4942#define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */
4943#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */
4944#define FDCAN_TTOCN_TMC_Pos (6U)
4945#define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */
4946#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */
4947#define FDCAN_TTOCN_TTIE_Pos (8U)
4948#define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */
4949#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */
4950#define FDCAN_TTOCN_GCS_Pos (9U)
4951#define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */
4952#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */
4953#define FDCAN_TTOCN_FGP_Pos (10U)
4954#define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */
4955#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */
4956#define FDCAN_TTOCN_TMG_Pos (11U)
4957#define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */
4958#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */
4959#define FDCAN_TTOCN_NIG_Pos (12U)
4960#define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */
4961#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */
4962#define FDCAN_TTOCN_ESCN_Pos (13U)
4963#define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */
4964#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */
4965#define FDCAN_TTOCN_LCKC_Pos (15U)
4966#define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */
4967#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */
4968
4969/***************** Bit definition for FDCAN_TTGTP register ********************/
4970#define FDCAN_TTGTP_TP_Pos (0U)
4971#define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos) /*!< 0x0000FFFF */
4972#define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk /*!<Time Preset */
4973#define FDCAN_TTGTP_CTP_Pos (16U)
4974#define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos) /*!< 0xFFFF0000 */
4975#define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk /*!<Cycle Time Target Phase */
4976
4977/***************** Bit definition for FDCAN_TTTMK register ********************/
4978#define FDCAN_TTTMK_TM_Pos (0U)
4979#define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos) /*!< 0x0000FFFF */
4980#define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk /*!<Time Mark */
4981#define FDCAN_TTTMK_TICC_Pos (16U)
4982#define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos) /*!< 0x007F0000 */
4983#define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk /*!<Time Mark Cycle Code */
4984#define FDCAN_TTTMK_LCKM_Pos (31U)
4985#define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos) /*!< 0x80000000 */
4986#define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk /*!<TT Time Mark Register Locked */
4987
4988/***************** Bit definition for FDCAN_TTIR register ********************/
4989#define FDCAN_TTIR_SBC_Pos (0U)
4990#define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos) /*!< 0x00000001 */
4991#define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk /*!<Start of Basic Cycle */
4992#define FDCAN_TTIR_SMC_Pos (1U)
4993#define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos) /*!< 0x00000002 */
4994#define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk /*!<Start of Matrix Cycle */
4995#define FDCAN_TTIR_CSM_Pos (2U)
4996#define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos) /*!< 0x00000004 */
4997#define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk /*!<Change of Synchronization Mode */
4998#define FDCAN_TTIR_SOG_Pos (3U)
4999#define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos) /*!< 0x00000008 */
5000#define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk /*!<Start of Gap */
5001#define FDCAN_TTIR_RTMI_Pos (4U)
5002#define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos) /*!< 0x00000010 */
5003#define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk /*!<Register Time Mark Interrupt */
5004#define FDCAN_TTIR_TTMI_Pos (5U)
5005#define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos) /*!< 0x00000020 */
5006#define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk /*!<Trigger Time Mark Event Internal */
5007#define FDCAN_TTIR_SWE_Pos (6U)
5008#define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos) /*!< 0x00000040 */
5009#define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk /*!<Stop Watch Event */
5010#define FDCAN_TTIR_GTW_Pos (7U)
5011#define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos) /*!< 0x00000080 */
5012#define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk /*!<Global Time Wrap */
5013#define FDCAN_TTIR_GTD_Pos (8U)
5014#define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos) /*!< 0x00000100 */
5015#define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk /*!<Global Time Discontinuity */
5016#define FDCAN_TTIR_GTE_Pos (9U)
5017#define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos) /*!< 0x00000200 */
5018#define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk /*!<Global Time Error */
5019#define FDCAN_TTIR_TXU_Pos (10U)
5020#define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos) /*!< 0x00000400 */
5021#define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk /*!<Tx Count Underflow */
5022#define FDCAN_TTIR_TXO_Pos (11U)
5023#define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos) /*!< 0x00000800 */
5024#define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk /*!<Tx Count Overflow */
5025#define FDCAN_TTIR_SE1_Pos (12U)
5026#define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos) /*!< 0x00001000 */
5027#define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk /*!<Scheduling Error 1 */
5028#define FDCAN_TTIR_SE2_Pos (13U)
5029#define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos) /*!< 0x00002000 */
5030#define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk /*!<Scheduling Error 2 */
5031#define FDCAN_TTIR_ELC_Pos (14U)
5032#define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos) /*!< 0x00004000 */
5033#define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk /*!<Error Level Changed */
5034#define FDCAN_TTIR_IWT_Pos (15U)
5035#define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos) /*!< 0x00008000 */
5036#define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk /*!<Initialization Watch Trigger */
5037#define FDCAN_TTIR_WT_Pos (16U)
5038#define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos) /*!< 0x00010000 */
5039#define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk /*!<Watch Trigger */
5040#define FDCAN_TTIR_AW_Pos (17U)
5041#define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos) /*!< 0x00020000 */
5042#define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk /*!<Application Watchdog */
5043#define FDCAN_TTIR_CER_Pos (18U)
5044#define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos) /*!< 0x00040000 */
5045#define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk /*!<Configuration Error */
5046
5047/***************** Bit definition for FDCAN_TTIE register ********************/
5048#define FDCAN_TTIE_SBCE_Pos (0U)
5049#define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos) /*!< 0x00000001 */
5050#define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk /*!<Start of Basic Cycle Interrupt Enable */
5051#define FDCAN_TTIE_SMCE_Pos (1U)
5052#define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos) /*!< 0x00000002 */
5053#define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk /*!<Start of Matrix Cycle Interrupt Enable */
5054#define FDCAN_TTIE_CSME_Pos (2U)
5055#define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos) /*!< 0x00000004 */
5056#define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk /*!<Change of Synchronization Mode Interrupt Enable */
5057#define FDCAN_TTIE_SOGE_Pos (3U)
5058#define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos) /*!< 0x00000008 */
5059#define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk /*!<Start of Gap Interrupt Enable */
5060#define FDCAN_TTIE_RTMIE_Pos (4U)
5061#define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos) /*!< 0x00000010 */
5062#define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk /*!<Register Time Mark Interrupt Interrupt Enable */
5063#define FDCAN_TTIE_TTMIE_Pos (5U)
5064#define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos) /*!< 0x00000020 */
5065#define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk /*!<Trigger Time Mark Event Internal Interrupt Enable */
5066#define FDCAN_TTIE_SWEE_Pos (6U)
5067#define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos) /*!< 0x00000040 */
5068#define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk /*!<Stop Watch Event Interrupt Enable */
5069#define FDCAN_TTIE_GTWE_Pos (7U)
5070#define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos) /*!< 0x00000080 */
5071#define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk /*!<Global Time Wrap Interrupt Enable */
5072#define FDCAN_TTIE_GTDE_Pos (8U)
5073#define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos) /*!< 0x00000100 */
5074#define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk /*!<Global Time Discontinuity Interrupt Enable */
5075#define FDCAN_TTIE_GTEE_Pos (9U)
5076#define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos) /*!< 0x00000200 */
5077#define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk /*!<Global Time Error Interrupt Enable */
5078#define FDCAN_TTIE_TXUE_Pos (10U)
5079#define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos) /*!< 0x00000400 */
5080#define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk /*!<Tx Count Underflow Interrupt Enable */
5081#define FDCAN_TTIE_TXOE_Pos (11U)
5082#define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos) /*!< 0x00000800 */
5083#define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk /*!<Tx Count Overflow Interrupt Enable */
5084#define FDCAN_TTIE_SE1E_Pos (12U)
5085#define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos) /*!< 0x00001000 */
5086#define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk /*!<Scheduling Error 1 Interrupt Enable */
5087#define FDCAN_TTIE_SE2E_Pos (13U)
5088#define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos) /*!< 0x00002000 */
5089#define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk /*!<Scheduling Error 2 Interrupt Enable */
5090#define FDCAN_TTIE_ELCE_Pos (14U)
5091#define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos) /*!< 0x00004000 */
5092#define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk /*!<Error Level Changed Interrupt Enable */
5093#define FDCAN_TTIE_IWTE_Pos (15U)
5094#define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos) /*!< 0x00008000 */
5095#define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk /*!<Initialization Watch Trigger Interrupt Enable */
5096#define FDCAN_TTIE_WTE_Pos (16U)
5097#define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos) /*!< 0x00010000 */
5098#define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk /*!<Watch Trigger Interrupt Enable */
5099#define FDCAN_TTIE_AWE_Pos (17U)
5100#define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos) /*!< 0x00020000 */
5101#define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk /*!<Application Watchdog Interrupt Enable */
5102#define FDCAN_TTIE_CERE_Pos (18U)
5103#define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos) /*!< 0x00040000 */
5104#define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk /*!<Configuration Error Interrupt Enable */
5105
5106/***************** Bit definition for FDCAN_TTILS register ********************/
5107#define FDCAN_TTILS_SBCS_Pos (0U)
5108#define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos) /*!< 0x00000001 */
5109#define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk /*!<Start of Basic Cycle Interrupt Line */
5110#define FDCAN_TTILS_SMCS_Pos (1U)
5111#define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos) /*!< 0x00000002 */
5112#define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk /*!<Start of Matrix Cycle Interrupt Line */
5113#define FDCAN_TTILS_CSMS_Pos (2U)
5114#define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos) /*!< 0x00000004 */
5115#define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk /*!<Change of Synchronization Mode Interrupt Line */
5116#define FDCAN_TTILS_SOGS_Pos (3U)
5117#define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos) /*!< 0x00000008 */
5118#define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk /*!<Start of Gap Interrupt Line */
5119#define FDCAN_TTILS_RTMIS_Pos (4U)
5120#define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos) /*!< 0x00000010 */
5121#define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk /*!<Register Time Mark Interrupt Interrupt Line */
5122#define FDCAN_TTILS_TTMIS_Pos (5U)
5123#define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos) /*!< 0x00000020 */
5124#define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk /*!<Trigger Time Mark Event Internal Interrupt Line */
5125#define FDCAN_TTILS_SWES_Pos (6U)
5126#define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos) /*!< 0x00000040 */
5127#define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk /*!<Stop Watch Event Interrupt Line */
5128#define FDCAN_TTILS_GTWS_Pos (7U)
5129#define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos) /*!< 0x00000080 */
5130#define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk /*!<Global Time Wrap Interrupt Line */
5131#define FDCAN_TTILS_GTDS_Pos (8U)
5132#define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos) /*!< 0x00000100 */
5133#define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk /*!<Global Time Discontinuity Interrupt Line */
5134#define FDCAN_TTILS_GTES_Pos (9U)
5135#define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos) /*!< 0x00000200 */
5136#define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk /*!<Global Time Error Interrupt Line */
5137#define FDCAN_TTILS_TXUS_Pos (10U)
5138#define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos) /*!< 0x00000400 */
5139#define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk /*!<Tx Count Underflow Interrupt Line */
5140#define FDCAN_TTILS_TXOS_Pos (11U)
5141#define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos) /*!< 0x00000800 */
5142#define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk /*!<Tx Count Overflow Interrupt Line */
5143#define FDCAN_TTILS_SE1S_Pos (12U)
5144#define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos) /*!< 0x00001000 */
5145#define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk /*!<Scheduling Error 1 Interrupt Line */
5146#define FDCAN_TTILS_SE2S_Pos (13U)
5147#define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos) /*!< 0x00002000 */
5148#define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk /*!<Scheduling Error 2 Interrupt Line */
5149#define FDCAN_TTILS_ELCS_Pos (14U)
5150#define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos) /*!< 0x00004000 */
5151#define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk /*!<Error Level Changed Interrupt Line */
5152#define FDCAN_TTILS_IWTS_Pos (15U)
5153#define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos) /*!< 0x00008000 */
5154#define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk /*!<Initialization Watch Trigger Interrupt Line */
5155#define FDCAN_TTILS_WTS_Pos (16U)
5156#define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos) /*!< 0x00010000 */
5157#define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk /*!<Watch Trigger Interrupt Line */
5158#define FDCAN_TTILS_AWS_Pos (17U)
5159#define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos) /*!< 0x00020000 */
5160#define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk /*!<Application Watchdog Interrupt Line */
5161#define FDCAN_TTILS_CERS_Pos (18U)
5162#define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos) /*!< 0x00040000 */
5163#define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk /*!<Configuration Error Interrupt Line */
5164
5165/***************** Bit definition for FDCAN_TTOST register ********************/
5166#define FDCAN_TTOST_EL_Pos (0U)
5167#define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos) /*!< 0x00000003 */
5168#define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk /*!<Error Level */
5169#define FDCAN_TTOST_MS_Pos (2U)
5170#define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos) /*!< 0x0000000C */
5171#define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk /*!<Master State */
5172#define FDCAN_TTOST_SYS_Pos (4U)
5173#define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos) /*!< 0x00000030 */
5174#define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk /*!<Synchronization State */
5175#define FDCAN_TTOST_QGTP_Pos (6U)
5176#define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos) /*!< 0x00000040 */
5177#define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk /*!<Quality of Global Time Phase */
5178#define FDCAN_TTOST_QCS_Pos (7U)
5179#define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos) /*!< 0x00000080 */
5180#define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk /*!<Quality of Clock Speed */
5181#define FDCAN_TTOST_RTO_Pos (8U)
5182#define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos) /*!< 0x0000FF00 */
5183#define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk /*!<Reference Trigger Offset */
5184#define FDCAN_TTOST_WGTD_Pos (22U)
5185#define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos) /*!< 0x00400000 */
5186#define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk /*!<Wait for Global Time Discontinuity */
5187#define FDCAN_TTOST_GFI_Pos (23U)
5188#define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos) /*!< 0x00800000 */
5189#define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk /*!<Gap Finished Indicator */
5190#define FDCAN_TTOST_TMP_Pos (24U)
5191#define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos) /*!< 0x07000000 */
5192#define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk /*!<Time Master Priority */
5193#define FDCAN_TTOST_GSI_Pos (27U)
5194#define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos) /*!< 0x08000000 */
5195#define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk /*!<Gap Started Indicator */
5196#define FDCAN_TTOST_WFE_Pos (28U)
5197#define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos) /*!< 0x10000000 */
5198#define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk /*!<Wait for Event */
5199#define FDCAN_TTOST_AWE_Pos (29U)
5200#define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos) /*!< 0x20000000 */
5201#define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk /*!<Application Watchdog Event */
5202#define FDCAN_TTOST_WECS_Pos (30U)
5203#define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos) /*!< 0x40000000 */
5204#define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk /*!<Wait for External Clock Synchronization */
5205#define FDCAN_TTOST_SPL_Pos (31U)
5206#define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos) /*!< 0x80000000 */
5207#define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk /*!<Schedule Phase Lock */
5208
5209/***************** Bit definition for FDCAN_TURNA register ********************/
5210#define FDCAN_TURNA_NAV_Pos (0U)
5211#define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos) /*!< 0x0003FFFF */
5212#define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk /*!<Numerator Actual Value */
5213
5214/***************** Bit definition for FDCAN_TTLGT register ********************/
5215#define FDCAN_TTLGT_LT_Pos (0U)
5216#define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos) /*!< 0x0000FFFF */
5217#define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk /*!<Local Time */
5218#define FDCAN_TTLGT_GT_Pos (16U)
5219#define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos) /*!< 0xFFFF0000 */
5220#define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk /*!<Global Time */
5221
5222/***************** Bit definition for FDCAN_TTCTC register ********************/
5223#define FDCAN_TTCTC_CT_Pos (0U)
5224#define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos) /*!< 0x0000FFFF */
5225#define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk /*!<Cycle Time */
5226#define FDCAN_TTCTC_CC_Pos (16U)
5227#define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos) /*!< 0x003F0000 */
5228#define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk /*!<Cycle Count */
5229
5230/***************** Bit definition for FDCAN_TTCPT register ********************/
5231#define FDCAN_TTCPT_CCV_Pos (0U)
5232#define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos) /*!< 0x0000003F */
5233#define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk /*!<Cycle Count Value */
5234#define FDCAN_TTCPT_SWV_Pos (16U)
5235#define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos) /*!< 0xFFFF0000 */
5236#define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk /*!<Stop Watch Value */
5237
5238/***************** Bit definition for FDCAN_TTCSM register ********************/
5239#define FDCAN_TTCSM_CSM_Pos (0U)
5240#define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos) /*!< 0x0000FFFF */
5241#define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk /*!<Cycle Sync Mark */
5242
5243/***************** Bit definition for FDCAN_TTTS register *********************/
5244#define FDCAN_TTTS_SWTSEL_Pos (0U)
5245#define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos) /*!< 0x00000003 */
5246#define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk /*!<Stop watch trigger input selection */
5247#define FDCAN_TTTS_EVTSEL_Pos (4U)
5248#define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos) /*!< 0x00000030 */
5249#define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk /*!<Event trigger input selection */
5250
5251/********************************************************************************/
5252/* */
5253/* FDCANCCU (Clock Calibration unit) */
5254/* */
5255/********************************************************************************/
5256
5257/***************** Bit definition for FDCANCCU_CREL register ******************/
5258#define FDCANCCU_CREL_DAY_Pos (0U)
5259#define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos) /*!< 0x000000FF */
5260#define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk /*!<Timestamp Day */
5261#define FDCANCCU_CREL_MON_Pos (8U)
5262#define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos) /*!< 0x0000FF00 */
5263#define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk /*!<Timestamp Month */
5264#define FDCANCCU_CREL_YEAR_Pos (16U)
5265#define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos) /*!< 0x000F0000 */
5266#define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk /*!<Timestamp Year */
5267#define FDCANCCU_CREL_SUBSTEP_Pos (20U)
5268#define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
5269#define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
5270#define FDCANCCU_CREL_STEP_Pos (24U)
5271#define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos) /*!< 0x0F000000 */
5272#define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk /*!<Step of Core release */
5273#define FDCANCCU_CREL_REL_Pos (28U)
5274#define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos) /*!< 0xF0000000 */
5275#define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk /*!<Core release */
5276
5277/***************** Bit definition for FDCANCCU_CCFG register ******************/
5278#define FDCANCCU_CCFG_TQBT_Pos (0U)
5279#define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos) /*!< 0x0000001F */
5280#define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk /*!<Time Quanta per Bit Time */
5281#define FDCANCCU_CCFG_BCC_Pos (6U)
5282#define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos) /*!< 0x00000040 */
5283#define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk /*!<Bypass Clock Calibration */
5284#define FDCANCCU_CCFG_CFL_Pos (7U)
5285#define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos) /*!< 0x00000080 */
5286#define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk /*!<Calibration Field Length */
5287#define FDCANCCU_CCFG_OCPM_Pos (8U)
5288#define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos) /*!< 0x0000FF00 */
5289#define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk /*!<Oscillator Clock Periods Minimum */
5290#define FDCANCCU_CCFG_CDIV_Pos (16U)
5291#define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos) /*!< 0x000F0000 */
5292#define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk /*!<Clock Divider */
5293#define FDCANCCU_CCFG_SWR_Pos (31U)
5294#define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos) /*!< 0x80000000 */
5295#define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk /*!<Software Reset */
5296
5297/***************** Bit definition for FDCANCCU_CSTAT register *****************/
5298#define FDCANCCU_CSTAT_OCPC_Pos (0U)
5299#define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos) /*!< 0x0003FFFF */
5300#define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk /*!<Oscillator Clock Period Counter */
5301#define FDCANCCU_CSTAT_TQC_Pos (18U)
5302#define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos) /*!< 0x1FFC0000 */
5303#define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk /*!<Time Quanta Counter */
5304#define FDCANCCU_CSTAT_CALS_Pos (30U)
5305#define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos) /*!< 0xC0000000 */
5306#define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk /*!<Calibration State */
5307
5308/****************** Bit definition for FDCANCCU_CWD register ******************/
5309#define FDCANCCU_CWD_WDC_Pos (0U)
5310#define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos) /*!< 0x0000FFFF */
5311#define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk /*!<Watchdog Configuration */
5312#define FDCANCCU_CWD_WDV_Pos (16U)
5313#define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos) /*!< 0xFFFF0000 */
5314#define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk /*!<Watchdog Value */
5315
5316/****************** Bit definition for FDCANCCU_IR register *******************/
5317#define FDCANCCU_IR_CWE_Pos (0U)
5318#define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos) /*!< 0x00000001 */
5319#define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk /*!<Calibration Watchdog Event */
5320#define FDCANCCU_IR_CSC_Pos (1U)
5321#define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos) /*!< 0x00000002 */
5322#define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk /*!<Calibration State Changed */
5323
5324/****************** Bit definition for FDCANCCU_IE register *******************/
5325#define FDCANCCU_IE_CWEE_Pos (0U)
5326#define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos) /*!< 0x00000001 */
5327#define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk /*!<Calibration Watchdog Event Enable */
5328#define FDCANCCU_IE_CSCE_Pos (1U)
5329#define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos) /*!< 0x00000002 */
5330#define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk /*!<Calibration State Changed Enable */
5331
5332/******************************************************************************/
5333/* */
5334/* HDMI-CEC (CEC) */
5335/* */
5336/******************************************************************************/
5337
5338/******************* Bit definition for CEC_CR register *********************/
5339#define CEC_CR_CECEN_Pos (0U)
5340#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
5341#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
5342#define CEC_CR_TXSOM_Pos (1U)
5343#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
5344#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
5345#define CEC_CR_TXEOM_Pos (2U)
5346#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
5347#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
5348
5349/******************* Bit definition for CEC_CFGR register *******************/
5350#define CEC_CFGR_SFT_Pos (0U)
5351#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
5352#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
5353#define CEC_CFGR_RXTOL_Pos (3U)
5354#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
5355#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
5356#define CEC_CFGR_BRESTP_Pos (4U)
5357#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
5358#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
5359#define CEC_CFGR_BREGEN_Pos (5U)
5360#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
5361#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
5362#define CEC_CFGR_LBPEGEN_Pos (6U)
5363#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
5364#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
5365#define CEC_CFGR_SFTOPT_Pos (8U)
5366#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
5367#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
5368#define CEC_CFGR_BRDNOGEN_Pos (7U)
5369#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
5370#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
5371#define CEC_CFGR_OAR_Pos (16U)
5372#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
5373#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
5374#define CEC_CFGR_LSTN_Pos (31U)
5375#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
5376#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
5377
5378/******************* Bit definition for CEC_TXDR register *******************/
5379#define CEC_TXDR_TXD_Pos (0U)
5380#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
5381#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
5382
5383/******************* Bit definition for CEC_RXDR register *******************/
5384#define CEC_RXDR_RXD_Pos (0U)
5385#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
5386#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
5387
5388/******************* Bit definition for CEC_ISR register ********************/
5389#define CEC_ISR_RXBR_Pos (0U)
5390#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
5391#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
5392#define CEC_ISR_RXEND_Pos (1U)
5393#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
5394#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
5395#define CEC_ISR_RXOVR_Pos (2U)
5396#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
5397#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
5398#define CEC_ISR_BRE_Pos (3U)
5399#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
5400#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
5401#define CEC_ISR_SBPE_Pos (4U)
5402#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
5403#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
5404#define CEC_ISR_LBPE_Pos (5U)
5405#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
5406#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
5407#define CEC_ISR_RXACKE_Pos (6U)
5408#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
5409#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
5410#define CEC_ISR_ARBLST_Pos (7U)
5411#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
5412#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
5413#define CEC_ISR_TXBR_Pos (8U)
5414#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
5415#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
5416#define CEC_ISR_TXEND_Pos (9U)
5417#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
5418#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
5419#define CEC_ISR_TXUDR_Pos (10U)
5420#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
5421#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
5422#define CEC_ISR_TXERR_Pos (11U)
5423#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
5424#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
5425#define CEC_ISR_TXACKE_Pos (12U)
5426#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
5427#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
5428
5429/******************* Bit definition for CEC_IER register ********************/
5430#define CEC_IER_RXBRIE_Pos (0U)
5431#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
5432#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
5433#define CEC_IER_RXENDIE_Pos (1U)
5434#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
5435#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
5436#define CEC_IER_RXOVRIE_Pos (2U)
5437#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
5438#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
5439#define CEC_IER_BREIE_Pos (3U)
5440#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
5441#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
5442#define CEC_IER_SBPEIE_Pos (4U)
5443#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
5444#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
5445#define CEC_IER_LBPEIE_Pos (5U)
5446#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
5447#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
5448#define CEC_IER_RXACKEIE_Pos (6U)
5449#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
5450#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
5451#define CEC_IER_ARBLSTIE_Pos (7U)
5452#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
5453#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
5454#define CEC_IER_TXBRIE_Pos (8U)
5455#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
5456#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
5457#define CEC_IER_TXENDIE_Pos (9U)
5458#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
5459#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
5460#define CEC_IER_TXUDRIE_Pos (10U)
5461#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
5462#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
5463#define CEC_IER_TXERRIE_Pos (11U)
5464#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
5465#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
5466#define CEC_IER_TXACKEIE_Pos (12U)
5467#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
5468#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
5469
5470/******************************************************************************/
5471/* */
5472/* CRC calculation unit */
5473/* */
5474/******************************************************************************/
5475/******************* Bit definition for CRC_DR register *********************/
5476#define CRC_DR_DR_Pos (0U)
5477#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5478#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5479
5480/******************* Bit definition for CRC_IDR register ********************/
5481#define CRC_IDR_IDR_Pos (0U)
5482#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
5483#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
5484
5485/******************** Bit definition for CRC_CR register ********************/
5486#define CRC_CR_RESET_Pos (0U)
5487#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5488#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
5489#define CRC_CR_POLYSIZE_Pos (3U)
5490#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
5491#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
5492#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
5493#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
5494#define CRC_CR_REV_IN_Pos (5U)
5495#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
5496#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
5497#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
5498#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
5499#define CRC_CR_REV_OUT_Pos (7U)
5500#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
5501#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
5502
5503/******************* Bit definition for CRC_INIT register *******************/
5504#define CRC_INIT_INIT_Pos (0U)
5505#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
5506#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
5507
5508/******************* Bit definition for CRC_POL register ********************/
5509#define CRC_POL_POL_Pos (0U)
5510#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
5511#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
5512
5513/******************************************************************************/
5514/* */
5515/* CRS Clock Recovery System */
5516/******************************************************************************/
5517
5518/******************* Bit definition for CRS_CR register *********************/
5519#define CRS_CR_SYNCOKIE_Pos (0U)
5520#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
5521#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
5522#define CRS_CR_SYNCWARNIE_Pos (1U)
5523#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
5524#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
5525#define CRS_CR_ERRIE_Pos (2U)
5526#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
5527#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
5528#define CRS_CR_ESYNCIE_Pos (3U)
5529#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
5530#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
5531#define CRS_CR_CEN_Pos (5U)
5532#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
5533#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
5534#define CRS_CR_AUTOTRIMEN_Pos (6U)
5535#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
5536#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
5537#define CRS_CR_SWSYNC_Pos (7U)
5538#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
5539#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
5540#define CRS_CR_TRIM_Pos (8U)
5541#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5542#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
5543
5544/******************* Bit definition for CRS_CFGR register *********************/
5545#define CRS_CFGR_RELOAD_Pos (0U)
5546#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
5547#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
5548#define CRS_CFGR_FELIM_Pos (16U)
5549#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
5550#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
5551
5552#define CRS_CFGR_SYNCDIV_Pos (24U)
5553#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
5554#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
5555#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
5556#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
5557#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
5558
5559#define CRS_CFGR_SYNCSRC_Pos (28U)
5560#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
5561#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
5562#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
5563#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
5564
5565#define CRS_CFGR_SYNCPOL_Pos (31U)
5566#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
5567#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
5568
5569/******************* Bit definition for CRS_ISR register *********************/
5570#define CRS_ISR_SYNCOKF_Pos (0U)
5571#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
5572#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
5573#define CRS_ISR_SYNCWARNF_Pos (1U)
5574#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
5575#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
5576#define CRS_ISR_ERRF_Pos (2U)
5577#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
5578#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
5579#define CRS_ISR_ESYNCF_Pos (3U)
5580#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
5581#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
5582#define CRS_ISR_SYNCERR_Pos (8U)
5583#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
5584#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
5585#define CRS_ISR_SYNCMISS_Pos (9U)
5586#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
5587#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
5588#define CRS_ISR_TRIMOVF_Pos (10U)
5589#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
5590#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
5591#define CRS_ISR_FEDIR_Pos (15U)
5592#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
5593#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
5594#define CRS_ISR_FECAP_Pos (16U)
5595#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
5596#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
5597
5598/******************* Bit definition for CRS_ICR register *********************/
5599#define CRS_ICR_SYNCOKC_Pos (0U)
5600#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
5601#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
5602#define CRS_ICR_SYNCWARNC_Pos (1U)
5603#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
5604#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
5605#define CRS_ICR_ERRC_Pos (2U)
5606#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
5607#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
5608#define CRS_ICR_ESYNCC_Pos (3U)
5609#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
5610#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
5611
5612/******************************************************************************/
5613/* */
5614/* Crypto Processor */
5615/* */
5616/******************************************************************************/
5617/******************************** CRYP VER **********************************/
5618#define CRYP_VER_2_2
5619/******************* Bits definition for CRYP_CR register ********************/
5620#define CRYP_CR_ALGODIR_Pos (2U)
5621#define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
5622#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
5623
5624#define CRYP_CR_ALGOMODE_Pos (3U)
5625#define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
5626#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
5627#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
5628#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
5629#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
5630#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
5631#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
5632#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
5633#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
5634#define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
5635#define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
5636#define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
5637#define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
5638#define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
5639#define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
5640#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
5641#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
5642#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
5643#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
5644#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
5645#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
5646#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
5647#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
5648#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
5649#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
5650#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
5651#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
5652#define CRYP_CR_ALGOMODE_AES_GCM_Pos (19U)
5653#define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */
5654#define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk
5655#define CRYP_CR_ALGOMODE_AES_CCM_Pos (3U)
5656#define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */
5657#define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk
5658
5659#define CRYP_CR_DATATYPE_Pos (6U)
5660#define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
5661#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
5662#define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
5663#define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
5664#define CRYP_CR_KEYSIZE_Pos (8U)
5665#define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
5666#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
5667#define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
5668#define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
5669#define CRYP_CR_FFLUSH_Pos (14U)
5670#define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
5671#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
5672#define CRYP_CR_CRYPEN_Pos (15U)
5673#define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
5674#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
5675
5676#define CRYP_CR_GCM_CCMPH_Pos (16U)
5677#define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
5678#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
5679#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
5680#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
5681#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
5682#define CRYP_CR_NPBLB_Pos (20U)
5683#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
5684#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
5685
5686/****************** Bits definition for CRYP_SR register *********************/
5687#define CRYP_SR_IFEM_Pos (0U)
5688#define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
5689#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
5690#define CRYP_SR_IFNF_Pos (1U)
5691#define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
5692#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
5693#define CRYP_SR_OFNE_Pos (2U)
5694#define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
5695#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
5696#define CRYP_SR_OFFU_Pos (3U)
5697#define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
5698#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
5699#define CRYP_SR_BUSY_Pos (4U)
5700#define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
5701#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
5702/****************** Bits definition for CRYP_DMACR register ******************/
5703#define CRYP_DMACR_DIEN_Pos (0U)
5704#define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
5705#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
5706#define CRYP_DMACR_DOEN_Pos (1U)
5707#define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
5708#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
5709/***************** Bits definition for CRYP_IMSCR register ******************/
5710#define CRYP_IMSCR_INIM_Pos (0U)
5711#define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
5712#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
5713#define CRYP_IMSCR_OUTIM_Pos (1U)
5714#define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
5715#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
5716/****************** Bits definition for CRYP_RISR register *******************/
5717#define CRYP_RISR_INRIS_Pos (0U)
5718#define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos) /*!< 0x00000001 */
5719#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
5720#define CRYP_RISR_OUTRIS_Pos (1U)
5721#define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000002 */
5722#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
5723/****************** Bits definition for CRYP_MISR register *******************/
5724#define CRYP_MISR_INMIS_Pos (0U)
5725#define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
5726#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
5727#define CRYP_MISR_OUTMIS_Pos (1U)
5728#define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
5729#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
5730
5731/******************************************************************************/
5732/* */
5733/* Digital to Analog Converter */
5734/* */
5735/******************************************************************************/
5736/******************** Bit definition for DAC_CR register ********************/
5737#define DAC_CR_EN1_Pos (0U)
5738#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5739#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5740#define DAC_CR_TEN1_Pos (1U)
5741#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
5742#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5743
5744#define DAC_CR_TSEL1_Pos (2U)
5745#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
5746#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5747#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
5748#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5749#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5750#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5751
5752
5753#define DAC_CR_WAVE1_Pos (6U)
5754#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5755#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5756#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5757#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5758
5759#define DAC_CR_MAMP1_Pos (8U)
5760#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5761#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5762#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5763#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5764#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5765#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5766
5767#define DAC_CR_DMAEN1_Pos (12U)
5768#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5769#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5770#define DAC_CR_DMAUDRIE1_Pos (13U)
5771#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5772#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
5773#define DAC_CR_CEN1_Pos (14U)
5774#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
5775#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
5776
5777#define DAC_CR_EN2_Pos (16U)
5778#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5779#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5780#define DAC_CR_TEN2_Pos (17U)
5781#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
5782#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5783
5784#define DAC_CR_TSEL2_Pos (18U)
5785#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
5786#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5787#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
5788#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5789#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5790#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5791
5792
5793#define DAC_CR_WAVE2_Pos (22U)
5794#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5795#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5796#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5797#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5798
5799#define DAC_CR_MAMP2_Pos (24U)
5800#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5801#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5802#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5803#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5804#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5805#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5806
5807#define DAC_CR_DMAEN2_Pos (28U)
5808#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5809#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5810#define DAC_CR_DMAUDRIE2_Pos (29U)
5811#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5812#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
5813#define DAC_CR_CEN2_Pos (30U)
5814#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
5815#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
5816
5817/***************** Bit definition for DAC_SWTRIGR register ******************/
5818#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5819#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5820#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5821#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5822#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5823#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5824
5825/***************** Bit definition for DAC_DHR12R1 register ******************/
5826#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5827#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5828#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5829
5830/***************** Bit definition for DAC_DHR12L1 register ******************/
5831#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5832#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5833#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5834
5835/****************** Bit definition for DAC_DHR8R1 register ******************/
5836#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5837#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5838#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5839
5840/***************** Bit definition for DAC_DHR12R2 register ******************/
5841#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5842#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5843#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5844
5845/***************** Bit definition for DAC_DHR12L2 register ******************/
5846#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5847#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5848#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5849
5850/****************** Bit definition for DAC_DHR8R2 register ******************/
5851#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5852#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5853#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5854
5855/***************** Bit definition for DAC_DHR12RD register ******************/
5856#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5857#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5858#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5859#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5860#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5861#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5862
5863/***************** Bit definition for DAC_DHR12LD register ******************/
5864#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5865#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5866#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5867#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5868#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5869#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5870
5871/****************** Bit definition for DAC_DHR8RD register ******************/
5872#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5873#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5874#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5875#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5876#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5877#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5878
5879/******************* Bit definition for DAC_DOR1 register *******************/
5880#define DAC_DOR1_DACC1DOR_Pos (0U)
5881#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5882#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5883
5884/******************* Bit definition for DAC_DOR2 register *******************/
5885#define DAC_DOR2_DACC2DOR_Pos (0U)
5886#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5887#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5888
5889/******************** Bit definition for DAC_SR register ********************/
5890#define DAC_SR_DMAUDR1_Pos (13U)
5891#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5892#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5893#define DAC_SR_CAL_FLAG1_Pos (14U)
5894#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
5895#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
5896#define DAC_SR_BWST1_Pos (15U)
5897#define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
5898#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
5899
5900#define DAC_SR_DMAUDR2_Pos (29U)
5901#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5902#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5903#define DAC_SR_CAL_FLAG2_Pos (30U)
5904#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
5905#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
5906#define DAC_SR_BWST2_Pos (31U)
5907#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
5908#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
5909
5910/******************* Bit definition for DAC_CCR register ********************/
5911#define DAC_CCR_OTRIM1_Pos (0U)
5912#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
5913#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
5914#define DAC_CCR_OTRIM2_Pos (16U)
5915#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
5916#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
5917
5918/******************* Bit definition for DAC_MCR register *******************/
5919#define DAC_MCR_MODE1_Pos (0U)
5920#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
5921#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
5922#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
5923#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
5924#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
5925
5926#define DAC_MCR_MODE2_Pos (16U)
5927#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
5928#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
5929#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
5930#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
5931#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
5932
5933/****************** Bit definition for DAC_SHSR1 register ******************/
5934#define DAC_SHSR1_TSAMPLE1_Pos (0U)
5935#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
5936#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
5937
5938/****************** Bit definition for DAC_SHSR2 register ******************/
5939#define DAC_SHSR2_TSAMPLE2_Pos (0U)
5940#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
5941#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
5942
5943/****************** Bit definition for DAC_SHHR register ******************/
5944#define DAC_SHHR_THOLD1_Pos (0U)
5945#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
5946#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
5947#define DAC_SHHR_THOLD2_Pos (16U)
5948#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
5949#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
5950
5951/****************** Bit definition for DAC_SHRR register ******************/
5952#define DAC_SHRR_TREFRESH1_Pos (0U)
5953#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
5954#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
5955#define DAC_SHRR_TREFRESH2_Pos (16U)
5956#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
5957#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
5958
5959/******************************************************************************/
5960/* */
5961/* DCMI */
5962/* */
5963/******************************************************************************/
5964/******************** Bits definition for DCMI_CR register ******************/
5965#define DCMI_CR_CAPTURE_Pos (0U)
5966#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
5967#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5968#define DCMI_CR_CM_Pos (1U)
5969#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
5970#define DCMI_CR_CM DCMI_CR_CM_Msk
5971#define DCMI_CR_CROP_Pos (2U)
5972#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
5973#define DCMI_CR_CROP DCMI_CR_CROP_Msk
5974#define DCMI_CR_JPEG_Pos (3U)
5975#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
5976#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5977#define DCMI_CR_ESS_Pos (4U)
5978#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
5979#define DCMI_CR_ESS DCMI_CR_ESS_Msk
5980#define DCMI_CR_PCKPOL_Pos (5U)
5981#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
5982#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5983#define DCMI_CR_HSPOL_Pos (6U)
5984#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
5985#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5986#define DCMI_CR_VSPOL_Pos (7U)
5987#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
5988#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5989#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
5990#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
5991#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
5992#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
5993#define DCMI_CR_CRE_Pos (12U)
5994#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
5995#define DCMI_CR_CRE DCMI_CR_CRE_Msk
5996#define DCMI_CR_ENABLE_Pos (14U)
5997#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
5998#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5999#define DCMI_CR_BSM_Pos (16U)
6000#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
6001#define DCMI_CR_BSM DCMI_CR_BSM_Msk
6002#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
6003#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
6004#define DCMI_CR_OEBS_Pos (18U)
6005#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
6006#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6007#define DCMI_CR_LSM_Pos (19U)
6008#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
6009#define DCMI_CR_LSM DCMI_CR_LSM_Msk
6010#define DCMI_CR_OELS_Pos (20U)
6011#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
6012#define DCMI_CR_OELS DCMI_CR_OELS_Msk
6013
6014/******************** Bits definition for DCMI_SR register ******************/
6015#define DCMI_SR_HSYNC_Pos (0U)
6016#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
6017#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6018#define DCMI_SR_VSYNC_Pos (1U)
6019#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
6020#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6021#define DCMI_SR_FNE_Pos (2U)
6022#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
6023#define DCMI_SR_FNE DCMI_SR_FNE_Msk
6024
6025/******************** Bits definition for DCMI_RIS register ****************/
6026#define DCMI_RIS_FRAME_RIS_Pos (0U)
6027#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
6028#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6029#define DCMI_RIS_OVR_RIS_Pos (1U)
6030#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
6031#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6032#define DCMI_RIS_ERR_RIS_Pos (2U)
6033#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
6034#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6035#define DCMI_RIS_VSYNC_RIS_Pos (3U)
6036#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
6037#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6038#define DCMI_RIS_LINE_RIS_Pos (4U)
6039#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
6040#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6041
6042/******************** Bits definition for DCMI_IER register *****************/
6043#define DCMI_IER_FRAME_IE_Pos (0U)
6044#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
6045#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6046#define DCMI_IER_OVR_IE_Pos (1U)
6047#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
6048#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6049#define DCMI_IER_ERR_IE_Pos (2U)
6050#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
6051#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6052#define DCMI_IER_VSYNC_IE_Pos (3U)
6053#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
6054#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6055#define DCMI_IER_LINE_IE_Pos (4U)
6056#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
6057#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6058
6059
6060/******************** Bits definition for DCMI_MIS register *****************/
6061#define DCMI_MIS_FRAME_MIS_Pos (0U)
6062#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
6063#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6064#define DCMI_MIS_OVR_MIS_Pos (1U)
6065#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
6066#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6067#define DCMI_MIS_ERR_MIS_Pos (2U)
6068#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
6069#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6070#define DCMI_MIS_VSYNC_MIS_Pos (3U)
6071#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
6072#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6073#define DCMI_MIS_LINE_MIS_Pos (4U)
6074#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
6075#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6076
6077
6078/******************** Bits definition for DCMI_ICR register *****************/
6079#define DCMI_ICR_FRAME_ISC_Pos (0U)
6080#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
6081#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6082#define DCMI_ICR_OVR_ISC_Pos (1U)
6083#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
6084#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6085#define DCMI_ICR_ERR_ISC_Pos (2U)
6086#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
6087#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6088#define DCMI_ICR_VSYNC_ISC_Pos (3U)
6089#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
6090#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6091#define DCMI_ICR_LINE_ISC_Pos (4U)
6092#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
6093#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6094
6095
6096/******************** Bits definition for DCMI_ESCR register ******************/
6097#define DCMI_ESCR_FSC_Pos (0U)
6098#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
6099#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6100#define DCMI_ESCR_LSC_Pos (8U)
6101#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
6102#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6103#define DCMI_ESCR_LEC_Pos (16U)
6104#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
6105#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6106#define DCMI_ESCR_FEC_Pos (24U)
6107#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
6108#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6109
6110/******************** Bits definition for DCMI_ESUR register ******************/
6111#define DCMI_ESUR_FSU_Pos (0U)
6112#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
6113#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6114#define DCMI_ESUR_LSU_Pos (8U)
6115#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
6116#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6117#define DCMI_ESUR_LEU_Pos (16U)
6118#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
6119#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6120#define DCMI_ESUR_FEU_Pos (24U)
6121#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
6122#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6123
6124/******************** Bits definition for DCMI_CWSTRT register ******************/
6125#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6126#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
6127#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6128#define DCMI_CWSTRT_VST_Pos (16U)
6129#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
6130#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6131
6132/******************** Bits definition for DCMI_CWSIZE register ******************/
6133#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6134#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
6135#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6136#define DCMI_CWSIZE_VLINE_Pos (16U)
6137#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
6138#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6139
6140/******************** Bits definition for DCMI_DR register ******************/
6141#define DCMI_DR_BYTE0_Pos (0U)
6142#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6143#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6144#define DCMI_DR_BYTE1_Pos (8U)
6145#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
6146#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6147#define DCMI_DR_BYTE2_Pos (16U)
6148#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
6149#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6150#define DCMI_DR_BYTE3_Pos (24U)
6151#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
6152#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6153
6154/******************************************************************************/
6155/* */
6156/* Digital Filter for Sigma Delta Modulators */
6157/* */
6158/******************************************************************************/
6159
6160/**************** DFSDM channel configuration registers ********************/
6161
6162/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6163#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6164#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
6165#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
6166#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6167#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
6168#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
6169#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6170#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
6171#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
6172#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6173#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
6174#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
6175#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
6176#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
6177#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6178#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
6179#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
6180#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
6181#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
6182#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6183#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
6184#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
6185#define DFSDM_CHCFGR1_CHEN_Pos (7U)
6186#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
6187#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
6188#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6189#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
6190#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
6191#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6192#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
6193#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
6194#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6195#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
6196#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
6197#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
6198#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
6199#define DFSDM_CHCFGR1_SITP_Pos (0U)
6200#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
6201#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
6202#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
6203#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
6204
6205/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6206#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6207#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
6208#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
6209#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6210#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
6211#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
6212
6213/****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6214#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6215#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
6216#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
6217#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
6218#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
6219#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6220#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
6221#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
6222#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6223#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
6224#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
6225#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6226#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
6227#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
6228
6229/**************** Bit definition for DFSDM_CHWDATR register *******************/
6230#define DFSDM_CHWDATR_WDATA_Pos (0U)
6231#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
6232#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
6233
6234/**************** Bit definition for DFSDM_CHDATINR register *****************/
6235#define DFSDM_CHDATINR_INDAT0_Pos (0U)
6236#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
6237#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
6238#define DFSDM_CHDATINR_INDAT1_Pos (16U)
6239#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
6240#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
6241
6242/**************** Bit definition for DFSDM_CHDLYR register *****************/
6243#define DFSDM_CHDLYR_PLSSKP_Pos (0U)
6244#define DFSDM_CHDLYR_PLSSKP_Msk (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos) /*!< 0x0000003F*/
6245#define DFSDM_CHDLYR_PLSSKP DFSDM_CHDLYR_PLSSKP_Msk
6246/************************ DFSDM module registers ****************************/
6247
6248/******************** Bit definition for DFSDM_FLTCR1 register *******************/
6249#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6250#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
6251#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
6252#define DFSDM_FLTCR1_FAST_Pos (29U)
6253#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
6254#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
6255#define DFSDM_FLTCR1_RCH_Pos (24U)
6256#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
6257#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
6258#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6259#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
6260#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
6261#define DFSDM_FLTCR1_RSYNC_Pos (19U)
6262#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
6263#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
6264#define DFSDM_FLTCR1_RCONT_Pos (18U)
6265#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
6266#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
6267#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6268#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
6269#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
6270#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6271#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
6272#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
6273#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
6274#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
6275#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6276#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
6277#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
6278#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
6279#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
6280#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
6281#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
6282#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
6283
6284#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6285#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
6286#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
6287#define DFSDM_FLTCR1_JSCAN_Pos (4U)
6288#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
6289#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
6290#define DFSDM_FLTCR1_JSYNC_Pos (3U)
6291#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
6292#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
6293#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6294#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
6295#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
6296#define DFSDM_FLTCR1_DFEN_Pos (0U)
6297#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
6298#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
6299
6300/******************** Bit definition for DFSDM_FLTCR2 register *******************/
6301#define DFSDM_FLTCR2_AWDCH_Pos (16U)
6302#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
6303#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
6304#define DFSDM_FLTCR2_EXCH_Pos (8U)
6305#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
6306#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
6307#define DFSDM_FLTCR2_CKABIE_Pos (6U)
6308#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
6309#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
6310#define DFSDM_FLTCR2_SCDIE_Pos (5U)
6311#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
6312#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
6313#define DFSDM_FLTCR2_AWDIE_Pos (4U)
6314#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
6315#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
6316#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6317#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
6318#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
6319#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6320#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
6321#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
6322#define DFSDM_FLTCR2_REOCIE_Pos (1U)
6323#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
6324#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
6325#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6326#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
6327#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
6328
6329/******************** Bit definition for DFSDM_FLTISR register *******************/
6330#define DFSDM_FLTISR_SCDF_Pos (24U)
6331#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
6332#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
6333#define DFSDM_FLTISR_CKABF_Pos (16U)
6334#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
6335#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
6336#define DFSDM_FLTISR_RCIP_Pos (14U)
6337#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
6338#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
6339#define DFSDM_FLTISR_JCIP_Pos (13U)
6340#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
6341#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
6342#define DFSDM_FLTISR_AWDF_Pos (4U)
6343#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
6344#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
6345#define DFSDM_FLTISR_ROVRF_Pos (3U)
6346#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
6347#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
6348#define DFSDM_FLTISR_JOVRF_Pos (2U)
6349#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
6350#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
6351#define DFSDM_FLTISR_REOCF_Pos (1U)
6352#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
6353#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
6354#define DFSDM_FLTISR_JEOCF_Pos (0U)
6355#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
6356#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
6357
6358/******************** Bit definition for DFSDM_FLTICR register *******************/
6359#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6360#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
6361#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
6362#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6363#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
6364#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
6365#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6366#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
6367#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
6368#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6369#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
6370#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
6371
6372/******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6373#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6374#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
6375#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
6376
6377/******************** Bit definition for DFSDM_FLTFCR register *******************/
6378#define DFSDM_FLTFCR_FORD_Pos (29U)
6379#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
6380#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
6381#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
6382#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
6383#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
6384#define DFSDM_FLTFCR_FOSR_Pos (16U)
6385#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
6386#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
6387#define DFSDM_FLTFCR_IOSR_Pos (0U)
6388#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
6389#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
6390
6391/****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6392#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6393#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
6394#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
6395#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6396#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
6397#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
6398
6399/****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6400#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6401#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
6402#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
6403#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6404#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
6405#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
6406#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6407#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
6408#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
6409
6410/****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6411#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6412#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
6413#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
6414#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6415#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
6416#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
6417
6418/****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6419#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6420#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
6421#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWHT[23:0] Analog watchdog low threshold */
6422#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6423#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
6424#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
6425
6426/****************** Bit definition for DFSDM_FLTAWSR register ******************/
6427#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6428#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
6429#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
6430#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6431#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
6432#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
6433
6434/****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
6435#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6436#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
6437#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
6438#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6439#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
6440#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
6441
6442/****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6443#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6444#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
6445#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
6446#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6447#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
6448#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
6449
6450/****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6451#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6452#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
6453#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
6454#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6455#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
6456#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
6457
6458/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6459#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6460#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
6461#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
6462
6463/******************************************************************************/
6464/* */
6465/* BDMA Controller */
6466/* */
6467/******************************************************************************/
6468
6469/******************* Bit definition for BDMA_ISR register ********************/
6470#define BDMA_ISR_GIF0_Pos (0U)
6471#define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos) /*!< 0x00000001 */
6472#define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk /*!< Channel 0 Global interrupt flag */
6473#define BDMA_ISR_TCIF0_Pos (1U)
6474#define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos) /*!< 0x00000002 */
6475#define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk /*!< Channel 0 Transfer Complete flag */
6476#define BDMA_ISR_HTIF0_Pos (2U)
6477#define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos) /*!< 0x00000004 */
6478#define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk /*!< Channel 0 Half Transfer flag */
6479#define BDMA_ISR_TEIF0_Pos (3U)
6480#define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos) /*!< 0x00000008 */
6481#define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk /*!< Channel 0 Transfer Error flag */
6482#define BDMA_ISR_GIF1_Pos (4U)
6483#define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos) /*!< 0x00000010 */
6484#define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
6485#define BDMA_ISR_TCIF1_Pos (5U)
6486#define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos) /*!< 0x00000020 */
6487#define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
6488#define BDMA_ISR_HTIF1_Pos (6U)
6489#define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos) /*!< 0x00000040 */
6490#define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
6491#define BDMA_ISR_TEIF1_Pos (7U)
6492#define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos) /*!< 0x00000080 */
6493#define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
6494#define BDMA_ISR_GIF2_Pos (8U)
6495#define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos) /*!< 0x00000100 */
6496#define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
6497#define BDMA_ISR_TCIF2_Pos (9U)
6498#define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos) /*!< 0x00000200 */
6499#define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
6500#define BDMA_ISR_HTIF2_Pos (10U)
6501#define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos) /*!< 0x00000400 */
6502#define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
6503#define BDMA_ISR_TEIF2_Pos (11U)
6504#define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos) /*!< 0x00000800 */
6505#define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
6506#define BDMA_ISR_GIF3_Pos (12U)
6507#define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos) /*!< 0x00001000 */
6508#define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
6509#define BDMA_ISR_TCIF3_Pos (13U)
6510#define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos) /*!< 0x00002000 */
6511#define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
6512#define BDMA_ISR_HTIF3_Pos (14U)
6513#define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos) /*!< 0x00004000 */
6514#define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
6515#define BDMA_ISR_TEIF3_Pos (15U)
6516#define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos) /*!< 0x00008000 */
6517#define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
6518#define BDMA_ISR_GIF4_Pos (16U)
6519#define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos) /*!< 0x00010000 */
6520#define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
6521#define BDMA_ISR_TCIF4_Pos (17U)
6522#define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos) /*!< 0x00020000 */
6523#define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
6524#define BDMA_ISR_HTIF4_Pos (18U)
6525#define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos) /*!< 0x00040000 */
6526#define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
6527#define BDMA_ISR_TEIF4_Pos (19U)
6528#define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos) /*!< 0x00080000 */
6529#define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
6530#define BDMA_ISR_GIF5_Pos (20U)
6531#define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos) /*!< 0x00100000 */
6532#define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
6533#define BDMA_ISR_TCIF5_Pos (21U)
6534#define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos) /*!< 0x00200000 */
6535#define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
6536#define BDMA_ISR_HTIF5_Pos (22U)
6537#define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos) /*!< 0x00400000 */
6538#define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
6539#define BDMA_ISR_TEIF5_Pos (23U)
6540#define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos) /*!< 0x00800000 */
6541#define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
6542#define BDMA_ISR_GIF6_Pos (24U)
6543#define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos) /*!< 0x01000000 */
6544#define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
6545#define BDMA_ISR_TCIF6_Pos (25U)
6546#define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos) /*!< 0x02000000 */
6547#define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
6548#define BDMA_ISR_HTIF6_Pos (26U)
6549#define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos) /*!< 0x04000000 */
6550#define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
6551#define BDMA_ISR_TEIF6_Pos (27U)
6552#define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos) /*!< 0x08000000 */
6553#define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
6554#define BDMA_ISR_GIF7_Pos (28U)
6555#define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos) /*!< 0x10000000 */
6556#define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
6557#define BDMA_ISR_TCIF7_Pos (29U)
6558#define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos) /*!< 0x20000000 */
6559#define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
6560#define BDMA_ISR_HTIF7_Pos (30U)
6561#define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos) /*!< 0x40000000 */
6562#define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
6563#define BDMA_ISR_TEIF7_Pos (31U)
6564#define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos) /*!< 0x80000000 */
6565#define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
6566
6567/******************* Bit definition for BDMA_IFCR register *******************/
6568#define BDMA_IFCR_CGIF0_Pos (0U)
6569#define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos) /*!< 0x00000001 */
6570#define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk /*!< Channel 0 Global interrupt clearr */
6571#define BDMA_IFCR_CTCIF0_Pos (1U)
6572#define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos) /*!< 0x00000002 */
6573#define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk /*!< Channel 0 Transfer Complete clear */
6574#define BDMA_IFCR_CHTIF0_Pos (2U)
6575#define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos) /*!< 0x00000004 */
6576#define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk /*!< Channel 0 Half Transfer clear */
6577#define BDMA_IFCR_CTEIF0_Pos (3U)
6578#define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos) /*!< 0x00000008 */
6579#define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk /*!< Channel 0 Transfer Error clear */
6580#define BDMA_IFCR_CGIF1_Pos (4U)
6581#define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos) /*!< 0x00000010 */
6582#define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
6583#define BDMA_IFCR_CTCIF1_Pos (5U)
6584#define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos) /*!< 0x00000020 */
6585#define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
6586#define BDMA_IFCR_CHTIF1_Pos (6U)
6587#define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos) /*!< 0x00000040 */
6588#define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
6589#define BDMA_IFCR_CTEIF1_Pos (7U)
6590#define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos) /*!< 0x00000080 */
6591#define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
6592#define BDMA_IFCR_CGIF2_Pos (8U)
6593#define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos) /*!< 0x00000100 */
6594#define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
6595#define BDMA_IFCR_CTCIF2_Pos (9U)
6596#define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos) /*!< 0x00000200 */
6597#define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
6598#define BDMA_IFCR_CHTIF2_Pos (10U)
6599#define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos) /*!< 0x00000400 */
6600#define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
6601#define BDMA_IFCR_CTEIF2_Pos (11U)
6602#define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos) /*!< 0x00000800 */
6603#define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
6604#define BDMA_IFCR_CGIF3_Pos (12U)
6605#define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos) /*!< 0x00001000 */
6606#define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
6607#define BDMA_IFCR_CTCIF3_Pos (13U)
6608#define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos) /*!< 0x00002000 */
6609#define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
6610#define BDMA_IFCR_CHTIF3_Pos (14U)
6611#define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos) /*!< 0x00004000 */
6612#define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
6613#define BDMA_IFCR_CTEIF3_Pos (15U)
6614#define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos) /*!< 0x00008000 */
6615#define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
6616#define BDMA_IFCR_CGIF4_Pos (16U)
6617#define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos) /*!< 0x00010000 */
6618#define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
6619#define BDMA_IFCR_CTCIF4_Pos (17U)
6620#define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos) /*!< 0x00020000 */
6621#define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
6622#define BDMA_IFCR_CHTIF4_Pos (18U)
6623#define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos) /*!< 0x00040000 */
6624#define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
6625#define BDMA_IFCR_CTEIF4_Pos (19U)
6626#define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos) /*!< 0x00080000 */
6627#define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
6628#define BDMA_IFCR_CGIF5_Pos (20U)
6629#define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos) /*!< 0x00100000 */
6630#define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
6631#define BDMA_IFCR_CTCIF5_Pos (21U)
6632#define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
6633#define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
6634#define BDMA_IFCR_CHTIF5_Pos (22U)
6635#define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos) /*!< 0x00400000 */
6636#define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
6637#define BDMA_IFCR_CTEIF5_Pos (23U)
6638#define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos) /*!< 0x00800000 */
6639#define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
6640#define BDMA_IFCR_CGIF6_Pos (24U)
6641#define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos) /*!< 0x01000000 */
6642#define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
6643#define BDMA_IFCR_CTCIF6_Pos (25U)
6644#define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos) /*!< 0x02000000 */
6645#define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
6646#define BDMA_IFCR_CHTIF6_Pos (26U)
6647#define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos) /*!< 0x04000000 */
6648#define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
6649#define BDMA_IFCR_CTEIF6_Pos (27U)
6650#define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos) /*!< 0x08000000 */
6651#define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
6652#define BDMA_IFCR_CGIF7_Pos (28U)
6653#define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos) /*!< 0x10000000 */
6654#define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
6655#define BDMA_IFCR_CTCIF7_Pos (29U)
6656#define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos) /*!< 0x20000000 */
6657#define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
6658#define BDMA_IFCR_CHTIF7_Pos (30U)
6659#define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos) /*!< 0x40000000 */
6660#define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
6661#define BDMA_IFCR_CTEIF7_Pos (31U)
6662#define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos) /*!< 0x80000000 */
6663#define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
6664
6665/******************* Bit definition for BDMA_CCR register ********************/
6666#define BDMA_CCR_EN_Pos (0U)
6667#define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos) /*!< 0x00000001 */
6668#define BDMA_CCR_EN BDMA_CCR_EN_Msk /*!< Channel enable */
6669#define BDMA_CCR_TCIE_Pos (1U)
6670#define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos) /*!< 0x00000002 */
6671#define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
6672#define BDMA_CCR_HTIE_Pos (2U)
6673#define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos) /*!< 0x00000004 */
6674#define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
6675#define BDMA_CCR_TEIE_Pos (3U)
6676#define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos) /*!< 0x00000008 */
6677#define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
6678#define BDMA_CCR_DIR_Pos (4U)
6679#define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos) /*!< 0x00000010 */
6680#define BDMA_CCR_DIR BDMA_CCR_DIR_Msk /*!< Data transfer direction */
6681#define BDMA_CCR_CIRC_Pos (5U)
6682#define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos) /*!< 0x00000020 */
6683#define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk /*!< Circular mode */
6684#define BDMA_CCR_PINC_Pos (6U)
6685#define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos) /*!< 0x00000040 */
6686#define BDMA_CCR_PINC BDMA_CCR_PINC_Msk /*!< Peripheral increment mode */
6687#define BDMA_CCR_MINC_Pos (7U)
6688#define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos) /*!< 0x00000080 */
6689#define BDMA_CCR_MINC BDMA_CCR_MINC_Msk /*!< Memory increment mode */
6690
6691#define BDMA_CCR_PSIZE_Pos (8U)
6692#define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
6693#define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
6694#define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
6695#define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
6696
6697#define BDMA_CCR_MSIZE_Pos (10U)
6698#define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
6699#define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
6700#define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
6701#define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
6702
6703#define BDMA_CCR_PL_Pos (12U)
6704#define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos) /*!< 0x00003000 */
6705#define BDMA_CCR_PL BDMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
6706#define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos) /*!< 0x00001000 */
6707#define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos) /*!< 0x00002000 */
6708
6709#define BDMA_CCR_MEM2MEM_Pos (14U)
6710#define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
6711#define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
6712#define BDMA_CCR_DBM_Pos (15U)
6713#define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos) /*!< 0x0000A000 */
6714#define BDMA_CCR_DBM BDMA_CCR_DBM_Msk /*!< Memory to memory mode */
6715#define BDMA_CCR_CT_Pos (16U)
6716#define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos) /*!< 0x00010000 */
6717#define BDMA_CCR_CT BDMA_CCR_CT_Msk /*!< Memory to memory mode */
6718
6719/****************** Bit definition for BDMA_CNDTR register *******************/
6720#define BDMA_CNDTR_NDT_Pos (0U)
6721#define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
6722#define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
6723
6724/****************** Bit definition for BDMA_CPAR register ********************/
6725#define BDMA_CPAR_PA_Pos (0U)
6726#define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
6727#define BDMA_CPAR_PA BDMA_CPAR_PA_Msk /*!< Peripheral Address */
6728
6729/****************** Bit definition for BDMA_CM0AR register ********************/
6730#define BDMA_CM0AR_MA_Pos (0U)
6731#define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos) /*!< 0xFFFFFFFF */
6732#define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk /*!< Memory Address */
6733
6734/****************** Bit definition for BDMA_CM1AR register ********************/
6735#define BDMA_CM1AR_MA_Pos (0U)
6736#define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos) /*!< 0xFFFFFFFF */
6737#define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk /*!< Memory Address */
6738
6739/******************************************************************************/
6740/* */
6741/* DMA Controller */
6742/* */
6743/******************************************************************************/
6744/******************** Bits definition for DMA_SxCR register *****************/
6745#define DMA_SxCR_MBURST_Pos (23U)
6746#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
6747#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk /*!< Memory burst transfer configuration */
6748#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
6749#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
6750#define DMA_SxCR_PBURST_Pos (21U)
6751#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
6752#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
6753#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
6754#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
6755#define DMA_SxCR_CT_Pos (19U)
6756#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
6757#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
6758#define DMA_SxCR_DBM_Pos (18U)
6759#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
6760#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk /*!< Double buffer mode */
6761#define DMA_SxCR_PL_Pos (16U)
6762#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
6763#define DMA_SxCR_PL DMA_SxCR_PL_Msk /*!< Priority level */
6764#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
6765#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
6766#define DMA_SxCR_PINCOS_Pos (15U)
6767#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
6768#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk /*!< Peripheral increment offset size */
6769#define DMA_SxCR_MSIZE_Pos (13U)
6770#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
6771#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk /*!< Memory data size */
6772#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
6773#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
6774#define DMA_SxCR_PSIZE_Pos (11U)
6775#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
6776#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
6777#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
6778#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
6779#define DMA_SxCR_MINC_Pos (10U)
6780#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
6781#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk /*!< Memory increment mode */
6782#define DMA_SxCR_PINC_Pos (9U)
6783#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
6784#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk /*!< Peripheral increment mode */
6785#define DMA_SxCR_CIRC_Pos (8U)
6786#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
6787#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk /*!< Circular mode */
6788#define DMA_SxCR_DIR_Pos (6U)
6789#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
6790#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk /*!< Data transfer direction */
6791#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
6792#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
6793#define DMA_SxCR_PFCTRL_Pos (5U)
6794#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
6795#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk /*!< Peripheral flow controller */
6796#define DMA_SxCR_TCIE_Pos (4U)
6797#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
6798#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk /*!< Transfer complete interrupt enable */
6799#define DMA_SxCR_HTIE_Pos (3U)
6800#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
6801#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk /*!< Half transfer interrupt enable */
6802#define DMA_SxCR_TEIE_Pos (2U)
6803#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
6804#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk /*!< Transfer error interrupt enable */
6805#define DMA_SxCR_DMEIE_Pos (1U)
6806#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
6807#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk /*!< Direct mode error interrupt enable */
6808#define DMA_SxCR_EN_Pos (0U)
6809#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
6810#define DMA_SxCR_EN DMA_SxCR_EN_Msk /*!< Stream enable / flag stream ready when read low */
6811
6812/******************** Bits definition for DMA_SxCNDTR register **************/
6813#define DMA_SxNDT_Pos (0U)
6814#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
6815#define DMA_SxNDT DMA_SxNDT_Msk /*!< Number of data items to transfer */
6816#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
6817#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
6818#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
6819#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
6820#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
6821#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
6822#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
6823#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
6824#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
6825#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
6826#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
6827#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
6828#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
6829#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
6830#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
6831#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
6832
6833/******************** Bits definition for DMA_SxFCR register ****************/
6834#define DMA_SxFCR_FEIE_Pos (7U)
6835#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
6836#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk /*!< FIFO error interrupt enable */
6837#define DMA_SxFCR_FS_Pos (3U)
6838#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
6839#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk /*!< FIFO status */
6840#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
6841#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
6842#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
6843#define DMA_SxFCR_DMDIS_Pos (2U)
6844#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
6845#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk /*!< Direct mode disable */
6846#define DMA_SxFCR_FTH_Pos (0U)
6847#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
6848#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk /*!< FIFO threshold selection */
6849#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
6850#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
6851
6852/******************** Bits definition for DMA_LISR register *****************/
6853#define DMA_LISR_TCIF3_Pos (27U)
6854#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
6855#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk /*!< Stream 3 transfer complete interrupt flag */
6856#define DMA_LISR_HTIF3_Pos (26U)
6857#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
6858#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk /*!< Stream 3 half transfer interrupt flag */
6859#define DMA_LISR_TEIF3_Pos (25U)
6860#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
6861#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk /*!< Stream 3 transfer error interrupt flag */
6862#define DMA_LISR_DMEIF3_Pos (24U)
6863#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
6864#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk /*!< Stream 3 direct mode error interrupt flag */
6865#define DMA_LISR_FEIF3_Pos (22U)
6866#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
6867#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk /*!< Stream 3 FIFO error interrupt flag */
6868#define DMA_LISR_TCIF2_Pos (21U)
6869#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
6870#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk /*!< Stream 2 transfer complete interrupt flag */
6871#define DMA_LISR_HTIF2_Pos (20U)
6872#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
6873#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk /*!< Stream 2 half transfer interrupt flag */
6874#define DMA_LISR_TEIF2_Pos (19U)
6875#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
6876#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk /*!< Stream 2 transfer error interrupt flag */
6877#define DMA_LISR_DMEIF2_Pos (18U)
6878#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
6879#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk /*!< Stream 2 direct mode error interrupt flag */
6880#define DMA_LISR_FEIF2_Pos (16U)
6881#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
6882#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk /*!< Stream 2 FIFO error interrupt flag */
6883#define DMA_LISR_TCIF1_Pos (11U)
6884#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
6885#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk /*!< Stream 1 transfer complete interrupt flag */
6886#define DMA_LISR_HTIF1_Pos (10U)
6887#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
6888#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk /*!< Stream 1 half transfer interrupt flag */
6889#define DMA_LISR_TEIF1_Pos (9U)
6890#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
6891#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk /*!< Stream 1 transfer error interrupt flag */
6892#define DMA_LISR_DMEIF1_Pos (8U)
6893#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
6894#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk /*!< Stream 1 direct mode error interrupt flag */
6895#define DMA_LISR_FEIF1_Pos (6U)
6896#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
6897#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk /*!< Stream 1 FIFO error interrupt flag */
6898#define DMA_LISR_TCIF0_Pos (5U)
6899#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
6900#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk /*!< Stream 0 transfer complete interrupt flag */
6901#define DMA_LISR_HTIF0_Pos (4U)
6902#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
6903#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk /*!< Stream 0 half transfer interrupt flag */
6904#define DMA_LISR_TEIF0_Pos (3U)
6905#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
6906#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk /*!< Stream 0 transfer error interrupt flag */
6907#define DMA_LISR_DMEIF0_Pos (2U)
6908#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
6909#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk /*!< Stream 0 direct mode error interrupt flag */
6910#define DMA_LISR_FEIF0_Pos (0U)
6911#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
6912#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk /*!< Stream 0 FIFO error interrupt flag */
6913
6914/******************** Bits definition for DMA_HISR register *****************/
6915#define DMA_HISR_TCIF7_Pos (27U)
6916#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
6917#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk /*!< Stream 7 transfer complete interrupt flag */
6918#define DMA_HISR_HTIF7_Pos (26U)
6919#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
6920#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk /*!< Stream 7 half transfer interrupt flag */
6921#define DMA_HISR_TEIF7_Pos (25U)
6922#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
6923#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk /*!< Stream 7 transfer error interrupt flag */
6924#define DMA_HISR_DMEIF7_Pos (24U)
6925#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
6926#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk /*!< Stream 7 direct mode error interrupt flag */
6927#define DMA_HISR_FEIF7_Pos (22U)
6928#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
6929#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk /*!< Stream 7 FIFO error interrupt flag */
6930#define DMA_HISR_TCIF6_Pos (21U)
6931#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
6932#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk /*!< Stream 6 transfer complete interrupt flag */
6933#define DMA_HISR_HTIF6_Pos (20U)
6934#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
6935#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk /*!< Stream 6 half transfer interrupt flag */
6936#define DMA_HISR_TEIF6_Pos (19U)
6937#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
6938#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk /*!< Stream 6 transfer error interrupt flag */
6939#define DMA_HISR_DMEIF6_Pos (18U)
6940#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
6941#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk /*!< Stream 6 direct mode error interrupt flag */
6942#define DMA_HISR_FEIF6_Pos (16U)
6943#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
6944#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk /*!< Stream 6 FIFO error interrupt flag */
6945#define DMA_HISR_TCIF5_Pos (11U)
6946#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6947#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk /*!< Stream 5 transfer complete interrupt flag */
6948#define DMA_HISR_HTIF5_Pos (10U)
6949#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6950#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk /*!< Stream 5 half transfer interrupt flag */
6951#define DMA_HISR_TEIF5_Pos (9U)
6952#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6953#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk /*!< Stream 5 transfer error interrupt flag */
6954#define DMA_HISR_DMEIF5_Pos (8U)
6955#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6956#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk /*!< Stream 5 direct mode error interrupt flag */
6957#define DMA_HISR_FEIF5_Pos (6U)
6958#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6959#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk /*!< Stream 5 FIFO error interrupt flag */
6960#define DMA_HISR_TCIF4_Pos (5U)
6961#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
6962#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk /*!< Stream 4 transfer complete interrupt flag */
6963#define DMA_HISR_HTIF4_Pos (4U)
6964#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
6965#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk /*!< Stream 4 half transfer interrupt flag */
6966#define DMA_HISR_TEIF4_Pos (3U)
6967#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6968#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk /*!< Stream 4 transfer error interrupt flag */
6969#define DMA_HISR_DMEIF4_Pos (2U)
6970#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
6971#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk /*!< Stream 4 direct mode error interrupt flag */
6972#define DMA_HISR_FEIF4_Pos (0U)
6973#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6974#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk /*!< Stream 4 FIFO error interrupt flag */
6975
6976/******************** Bits definition for DMA_LIFCR register ****************/
6977#define DMA_LIFCR_CTCIF3_Pos (27U)
6978#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
6979#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk /*!< Stream 3 clear transfer complete interrupt flag */
6980#define DMA_LIFCR_CHTIF3_Pos (26U)
6981#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
6982#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk /*!< Stream 3 clear half transfer interrupt flag */
6983#define DMA_LIFCR_CTEIF3_Pos (25U)
6984#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
6985#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk /*!< Stream 3 clear transfer error interrupt flag */
6986#define DMA_LIFCR_CDMEIF3_Pos (24U)
6987#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
6988#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk /*!< Stream 3 clear direct mode error interrupt flag */
6989#define DMA_LIFCR_CFEIF3_Pos (22U)
6990#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
6991#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk /*!< Stream 3 clear FIFO error interrupt flag */
6992#define DMA_LIFCR_CTCIF2_Pos (21U)
6993#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
6994#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk /*!< Stream 2 clear transfer complete interrupt flag */
6995#define DMA_LIFCR_CHTIF2_Pos (20U)
6996#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
6997#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk /*!< Stream 2 clear half transfer interrupt flag */
6998#define DMA_LIFCR_CTEIF2_Pos (19U)
6999#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
7000#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk /*!< Stream 2 clear transfer error interrupt flag */
7001#define DMA_LIFCR_CDMEIF2_Pos (18U)
7002#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
7003#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk /*!< Stream 2 clear direct mode error interrupt flag */
7004#define DMA_LIFCR_CFEIF2_Pos (16U)
7005#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
7006#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk /*!< Stream 2 clear FIFO error interrupt flag */
7007#define DMA_LIFCR_CTCIF1_Pos (11U)
7008#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
7009#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk /*!< Stream 1 clear transfer complete interrupt flag */
7010#define DMA_LIFCR_CHTIF1_Pos (10U)
7011#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
7012#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk /*!< Stream 1 clear half transfer interrupt flag */
7013#define DMA_LIFCR_CTEIF1_Pos (9U)
7014#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
7015#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk /*!< Stream 1 clear transfer error interrupt flag */
7016#define DMA_LIFCR_CDMEIF1_Pos (8U)
7017#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
7018#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk /*!< Stream 1 clear direct mode error interrupt flag */
7019#define DMA_LIFCR_CFEIF1_Pos (6U)
7020#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
7021#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk /*!< Stream 1 clear FIFO error interrupt flag */
7022#define DMA_LIFCR_CTCIF0_Pos (5U)
7023#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
7024#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk /*!< Stream 0 clear transfer complete interrupt flag */
7025#define DMA_LIFCR_CHTIF0_Pos (4U)
7026#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
7027#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk /*!< Stream 0 clear half transfer interrupt flag */
7028#define DMA_LIFCR_CTEIF0_Pos (3U)
7029#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
7030#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk /*!< Stream 0 clear transfer error interrupt flag */
7031#define DMA_LIFCR_CDMEIF0_Pos (2U)
7032#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
7033#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk /*!< Stream 0 clear direct mode error interrupt flag */
7034#define DMA_LIFCR_CFEIF0_Pos (0U)
7035#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
7036#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk /*!< Stream 0 clear FIFO error interrupt flag */
7037
7038/******************** Bits definition for DMA_HIFCR register ****************/
7039#define DMA_HIFCR_CTCIF7_Pos (27U)
7040#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
7041#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk /*!< Stream 7 clear transfer complete interrupt flag */
7042#define DMA_HIFCR_CHTIF7_Pos (26U)
7043#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
7044#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk /*!< Stream 7 clear half transfer interrupt flag */
7045#define DMA_HIFCR_CTEIF7_Pos (25U)
7046#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
7047#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk /*!< Stream 7 clear transfer error interrupt flag */
7048#define DMA_HIFCR_CDMEIF7_Pos (24U)
7049#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
7050#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk /*!< Stream 7 clear direct mode error interrupt flag */
7051#define DMA_HIFCR_CFEIF7_Pos (22U)
7052#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
7053#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk /*!< Stream 7 clear FIFO error interrupt flag */
7054#define DMA_HIFCR_CTCIF6_Pos (21U)
7055#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
7056#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk /*!< Stream 6 clear transfer complete interrupt flag */
7057#define DMA_HIFCR_CHTIF6_Pos (20U)
7058#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
7059#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk /*!< Stream 6 clear half transfer interrupt flag */
7060#define DMA_HIFCR_CTEIF6_Pos (19U)
7061#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
7062#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk /*!< Stream 6 clear transfer error interrupt flag */
7063#define DMA_HIFCR_CDMEIF6_Pos (18U)
7064#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
7065#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk /*!< Stream 6 clear direct mode error interrupt flag */
7066#define DMA_HIFCR_CFEIF6_Pos (16U)
7067#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
7068#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk /*!< Stream 6 clear FIFO error interrupt flag */
7069#define DMA_HIFCR_CTCIF5_Pos (11U)
7070#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
7071#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk /*!< Stream 5 clear transfer complete interrupt flag */
7072#define DMA_HIFCR_CHTIF5_Pos (10U)
7073#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
7074#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk /*!< Stream 5 clear half transfer interrupt flag */
7075#define DMA_HIFCR_CTEIF5_Pos (9U)
7076#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
7077#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk /*!< Stream 5 clear transfer error interrupt flag */
7078#define DMA_HIFCR_CDMEIF5_Pos (8U)
7079#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
7080#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk /*!< Stream 5 clear direct mode error interrupt flag */
7081#define DMA_HIFCR_CFEIF5_Pos (6U)
7082#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
7083#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk /*!< Stream 5 clear FIFO error interrupt flag */
7084#define DMA_HIFCR_CTCIF4_Pos (5U)
7085#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
7086#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk /*!< Stream 4 clear transfer complete interrupt flag */
7087#define DMA_HIFCR_CHTIF4_Pos (4U)
7088#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
7089#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk /*!< Stream 4 clear half transfer interrupt flag */
7090#define DMA_HIFCR_CTEIF4_Pos (3U)
7091#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
7092#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk /*!< Stream 4 clear transfer error interrupt flag */
7093#define DMA_HIFCR_CDMEIF4_Pos (2U)
7094#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
7095#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk /*!< Stream 4 clear direct mode error interrupt flag */
7096#define DMA_HIFCR_CFEIF4_Pos (0U)
7097#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
7098#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk /*!< Stream 4 clear FIFO error interrupt flag */
7099
7100/****************** Bit definition for DMA_SxPAR register ********************/
7101#define DMA_SxPAR_PA_Pos (0U)
7102#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
7103#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
7104
7105/****************** Bit definition for DMA_SxM0AR register ********************/
7106#define DMA_SxM0AR_M0A_Pos (0U)
7107#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
7108#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory 0 Address */
7109
7110/****************** Bit definition for DMA_SxM1AR register ********************/
7111#define DMA_SxM1AR_M1A_Pos (0U)
7112#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
7113#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory 1 Address */
7114
7115/******************************************************************************/
7116/* */
7117/* DMAMUX Controller */
7118/* */
7119/******************************************************************************/
7120/******************** Bits definition for DMAMUX_CxCR register **************/
7121#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
7122#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
7123#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA request identification */
7124#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
7125#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
7126#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
7127#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
7128#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
7129#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
7130#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
7131#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
7132#define DMAMUX_CxCR_SOIE_Pos (8U)
7133#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
7134#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchronization overrun interrupt enable */
7135#define DMAMUX_CxCR_EGE_Pos (9U)
7136#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
7137#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation enable */
7138#define DMAMUX_CxCR_SE_Pos (16U)
7139#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
7140#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
7141#define DMAMUX_CxCR_SPOL_Pos (17U)
7142#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
7143#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
7144#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
7145#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
7146#define DMAMUX_CxCR_NBREQ_Pos (19U)
7147#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
7148#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of DMA requests minus 1 to forward */
7149#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
7150#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
7151#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
7152#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
7153#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
7154#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
7155#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
7156#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization identification */
7157#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
7158#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
7159#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
7160#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
7161#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
7162
7163/******************** Bits definition for DMAMUX_CSR register **************/
7164#define DMAMUX_CSR_SOF0_Pos (0U)
7165#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
7166#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Channel 0 Synchronization overrun event flag */
7167#define DMAMUX_CSR_SOF1_Pos (1U)
7168#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
7169#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Channel 1 Synchronization overrun event flag */
7170#define DMAMUX_CSR_SOF2_Pos (2U)
7171#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
7172#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Channel 2 Synchronization overrun event flag */
7173#define DMAMUX_CSR_SOF3_Pos (3U)
7174#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
7175#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Channel 3 Synchronization overrun event flag */
7176#define DMAMUX_CSR_SOF4_Pos (4U)
7177#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
7178#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Channel 4 Synchronization overrun event flag */
7179#define DMAMUX_CSR_SOF5_Pos (5U)
7180#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
7181#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Channel 5 Synchronization overrun event flag */
7182#define DMAMUX_CSR_SOF6_Pos (6U)
7183#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
7184#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Channel 6 Synchronization overrun event flag */
7185#define DMAMUX_CSR_SOF7_Pos (7U)
7186#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
7187#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Channel 7 Synchronization overrun event flag */
7188#define DMAMUX_CSR_SOF8_Pos (8U)
7189#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
7190#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Channel 8 Synchronization overrun event flag */
7191#define DMAMUX_CSR_SOF9_Pos (9U)
7192#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
7193#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Channel 9 Synchronization overrun event flag */
7194#define DMAMUX_CSR_SOF10_Pos (10U)
7195#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
7196#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Channel 10 Synchronization overrun event flag */
7197#define DMAMUX_CSR_SOF11_Pos (11U)
7198#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
7199#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Channel 11 Synchronization overrun event flag */
7200#define DMAMUX_CSR_SOF12_Pos (12U)
7201#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
7202#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Channel 12 Synchronization overrun event flag */
7203#define DMAMUX_CSR_SOF13_Pos (13U)
7204#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
7205#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Channel 13 Synchronization overrun event flag */
7206#define DMAMUX_CSR_SOF14_Pos (14U)
7207#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos) /*!< 0x00004000 */
7208#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk /*!< Channel 14 Synchronization overrun event flag */
7209#define DMAMUX_CSR_SOF15_Pos (15U)
7210#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos) /*!< 0x00008000 */
7211#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk /*!< Channel 15 Synchronization overrun event flag */
7212
7213/******************** Bits definition for DMAMUX_CFR register **************/
7214#define DMAMUX_CFR_CSOF0_Pos (0U)
7215#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
7216#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Channel 0 Clear synchronization overrun event flag */
7217#define DMAMUX_CFR_CSOF1_Pos (1U)
7218#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
7219#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Channel 1 Clear synchronization overrun event flag */
7220#define DMAMUX_CFR_CSOF2_Pos (2U)
7221#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
7222#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Channel 2 Clear synchronization overrun event flag */
7223#define DMAMUX_CFR_CSOF3_Pos (3U)
7224#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
7225#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Channel 3 Clear synchronization overrun event flag */
7226#define DMAMUX_CFR_CSOF4_Pos (4U)
7227#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
7228#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Channel 4 Clear synchronization overrun event flag */
7229#define DMAMUX_CFR_CSOF5_Pos (5U)
7230#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
7231#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Channel 5 Clear synchronization overrun event flag */
7232#define DMAMUX_CFR_CSOF6_Pos (6U)
7233#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
7234#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Channel 6 Clear synchronization overrun event flag */
7235#define DMAMUX_CFR_CSOF7_Pos (7U)
7236#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
7237#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Channel 7 Clear synchronization overrun event flag */
7238#define DMAMUX_CFR_CSOF8_Pos (8U)
7239#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
7240#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Channel 8 Clear synchronization overrun event flag */
7241#define DMAMUX_CFR_CSOF9_Pos (9U)
7242#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
7243#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Channel 9 Clear synchronization overrun event flag */
7244#define DMAMUX_CFR_CSOF10_Pos (10U)
7245#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
7246#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Channel 10 Clear synchronization overrun event flag */
7247#define DMAMUX_CFR_CSOF11_Pos (11U)
7248#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
7249#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Channel 11 Clear synchronization overrun event flag */
7250#define DMAMUX_CFR_CSOF12_Pos (12U)
7251#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
7252#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Channel 12 Clear synchronization overrun event flag */
7253#define DMAMUX_CFR_CSOF13_Pos (13U)
7254#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
7255#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Channel 13 Clear synchronization overrun event flag */
7256#define DMAMUX_CFR_CSOF14_Pos (14U)
7257#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos) /*!< 0x00004000 */
7258#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk /*!< Channel 14 Clear synchronization overrun event flag */
7259#define DMAMUX_CFR_CSOF15_Pos (15U)
7260#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos) /*!< 0x00008000 */
7261#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk /*!< Channel 15 Clear synchronization overrun event flag */
7262
7263/******************** Bits definition for DMAMUX_RGxCR register ************/
7264#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
7265#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
7266#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal identification */
7267#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
7268#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
7269#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
7270#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
7271#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
7272#define DMAMUX_RGxCR_OIE_Pos (8U)
7273#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
7274#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Trigger overrun interrupt enable */
7275#define DMAMUX_RGxCR_GE_Pos (16U)
7276#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
7277#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< DMA request generator enable */
7278#define DMAMUX_RGxCR_GPOL_Pos (17U)
7279#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
7280#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< DMA request generator trigger polarity */
7281#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
7282#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
7283#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
7284#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
7285#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of DMA requests to be generated */
7286#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
7287#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
7288#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
7289#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
7290#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
7291
7292/******************** Bits definition for DMAMUX_RGSR register **************/
7293#define DMAMUX_RGSR_OF0_Pos (0U)
7294#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
7295#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Request generator channel 0 Trigger overrun event flag */
7296#define DMAMUX_RGSR_OF1_Pos (1U)
7297#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
7298#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Request generator channel 1 Trigger overrun event flag */
7299#define DMAMUX_RGSR_OF2_Pos (2U)
7300#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
7301#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Request generator channel 2 Trigger overrun event flag */
7302#define DMAMUX_RGSR_OF3_Pos (3U)
7303#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
7304#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Request generator channel 3 Trigger overrun event flag */
7305#define DMAMUX_RGSR_OF4_Pos (4U)
7306#define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos) /*!< 0x00000010 */
7307#define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk /*!< Request generator channel 4 Trigger overrun event flag */
7308#define DMAMUX_RGSR_OF5_Pos (5U)
7309#define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos) /*!< 0x00000020 */
7310#define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk /*!< Request generator channel 5 Trigger overrun event flag */
7311#define DMAMUX_RGSR_OF6_Pos (6U)
7312#define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos) /*!< 0x00000040 */
7313#define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk /*!< Request generator channel 6 Trigger overrun event flag */
7314#define DMAMUX_RGSR_OF7_Pos (7U)
7315#define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos) /*!< 0x00000080 */
7316#define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk /*!< Request generator channel 7 Trigger overrun event flag */
7317
7318/******************** Bits definition for DMAMUX_RGCFR register **************/
7319#define DMAMUX_RGCFR_COF0_Pos (0U)
7320#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
7321#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Request generator channel 0 Clear trigger overrun event flag */
7322#define DMAMUX_RGCFR_COF1_Pos (1U)
7323#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
7324#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Request generator channel 1 Clear trigger overrun event flag */
7325#define DMAMUX_RGCFR_COF2_Pos (2U)
7326#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
7327#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Request generator channel 2 Clear trigger overrun event flag */
7328#define DMAMUX_RGCFR_COF3_Pos (3U)
7329#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
7330#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Request generator channel 3 Clear trigger overrun event flag */
7331#define DMAMUX_RGCFR_COF4_Pos (4U)
7332#define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos) /*!< 0x00000010 */
7333#define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk /*!< Request generator channel 4 Clear trigger overrun event flag */
7334#define DMAMUX_RGCFR_COF5_Pos (5U)
7335#define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos) /*!< 0x00000020 */
7336#define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk /*!< Request generator channel 5 Clear trigger overrun event flag */
7337#define DMAMUX_RGCFR_COF6_Pos (6U)
7338#define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos) /*!< 0x00000040 */
7339#define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk /*!< Request generator channel 6 Clear trigger overrun event flag */
7340#define DMAMUX_RGCFR_COF7_Pos (7U)
7341#define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos) /*!< 0x00000080 */
7342#define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk /*!< Request generator channel 7 Clear trigger overrun event flag */
7343
7344/******************************************************************************/
7345/* */
7346/* AHB Master DMA2D Controller (DMA2D) */
7347/* */
7348/******************************************************************************/
7349
7350/******************** Bit definition for DMA2D_CR register ******************/
7351
7352#define DMA2D_CR_START_Pos (0U)
7353#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */
7354#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
7355#define DMA2D_CR_SUSP_Pos (1U)
7356#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
7357#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
7358#define DMA2D_CR_ABORT_Pos (2U)
7359#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
7360#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
7361#define DMA2D_CR_LOM_Pos (6U)
7362#define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos) /*!< 0x00000040 */
7363#define DMA2D_CR_LOM DMA2D_CR_LOM_Msk /*!< Line Offset Mode */
7364#define DMA2D_CR_TEIE_Pos (8U)
7365#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
7366#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
7367#define DMA2D_CR_TCIE_Pos (9U)
7368#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
7369#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
7370#define DMA2D_CR_TWIE_Pos (10U)
7371#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
7372#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
7373#define DMA2D_CR_CAEIE_Pos (11U)
7374#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
7375#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
7376#define DMA2D_CR_CTCIE_Pos (12U)
7377#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
7378#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
7379#define DMA2D_CR_CEIE_Pos (13U)
7380#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
7381#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
7382#define DMA2D_CR_MODE_Pos (16U)
7383#define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos) /*!< 0x00070000 */
7384#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[2:0] */
7385#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
7386#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
7387#define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos) /*!< 0x00040000 */
7388
7389/******************** Bit definition for DMA2D_ISR register *****************/
7390
7391#define DMA2D_ISR_TEIF_Pos (0U)
7392#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
7393#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
7394#define DMA2D_ISR_TCIF_Pos (1U)
7395#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
7396#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
7397#define DMA2D_ISR_TWIF_Pos (2U)
7398#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
7399#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
7400#define DMA2D_ISR_CAEIF_Pos (3U)
7401#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
7402#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
7403#define DMA2D_ISR_CTCIF_Pos (4U)
7404#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
7405#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
7406#define DMA2D_ISR_CEIF_Pos (5U)
7407#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
7408#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
7409
7410/******************** Bit definition for DMA2D_IFCR register ****************/
7411
7412#define DMA2D_IFCR_CTEIF_Pos (0U)
7413#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
7414#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
7415#define DMA2D_IFCR_CTCIF_Pos (1U)
7416#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
7417#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
7418#define DMA2D_IFCR_CTWIF_Pos (2U)
7419#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
7420#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
7421#define DMA2D_IFCR_CAECIF_Pos (3U)
7422#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
7423#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
7424#define DMA2D_IFCR_CCTCIF_Pos (4U)
7425#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
7426#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
7427#define DMA2D_IFCR_CCEIF_Pos (5U)
7428#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
7429#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
7430
7431/******************** Bit definition for DMA2D_FGMAR register ***************/
7432
7433#define DMA2D_FGMAR_MA_Pos (0U)
7434#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
7435#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Foreground Memory Address */
7436
7437/******************** Bit definition for DMA2D_FGOR register ****************/
7438
7439#define DMA2D_FGOR_LO_Pos (0U)
7440#define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x0000FFFF */
7441#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
7442
7443/******************** Bit definition for DMA2D_BGMAR register ***************/
7444
7445#define DMA2D_BGMAR_MA_Pos (0U)
7446#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
7447#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Background Memory Address */
7448
7449/******************** Bit definition for DMA2D_BGOR register ****************/
7450
7451#define DMA2D_BGOR_LO_Pos (0U)
7452#define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x0000FFFF */
7453#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
7454
7455/******************** Bit definition for DMA2D_FGPFCCR register *************/
7456
7457#define DMA2D_FGPFCCR_CM_Pos (0U)
7458#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
7459#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
7460#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
7461#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
7462#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
7463#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
7464#define DMA2D_FGPFCCR_CCM_Pos (4U)
7465#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
7466#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
7467#define DMA2D_FGPFCCR_START_Pos (5U)
7468#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
7469#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
7470#define DMA2D_FGPFCCR_CS_Pos (8U)
7471#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
7472#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
7473#define DMA2D_FGPFCCR_AM_Pos (16U)
7474#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
7475#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
7476#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
7477#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
7478#define DMA2D_FGPFCCR_CSS_Pos (18U)
7479#define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */
7480#define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
7481#define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */
7482#define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */
7483#define DMA2D_FGPFCCR_AI_Pos (20U)
7484#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
7485#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
7486#define DMA2D_FGPFCCR_RBS_Pos (21U)
7487#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
7488#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */
7489#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
7490#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
7491#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
7492
7493/******************** Bit definition for DMA2D_FGCOLR register **************/
7494
7495#define DMA2D_FGCOLR_BLUE_Pos (0U)
7496#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
7497#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Foreground Blue Value */
7498#define DMA2D_FGCOLR_GREEN_Pos (8U)
7499#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
7500#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Foreground Green Value */
7501#define DMA2D_FGCOLR_RED_Pos (16U)
7502#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
7503#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Foreground Red Value */
7504
7505/******************** Bit definition for DMA2D_BGPFCCR register *************/
7506
7507#define DMA2D_BGPFCCR_CM_Pos (0U)
7508#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
7509#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
7510#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
7511#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
7512#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
7513#define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */
7514#define DMA2D_BGPFCCR_CCM_Pos (4U)
7515#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
7516#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
7517#define DMA2D_BGPFCCR_START_Pos (5U)
7518#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
7519#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
7520#define DMA2D_BGPFCCR_CS_Pos (8U)
7521#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
7522#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
7523#define DMA2D_BGPFCCR_AM_Pos (16U)
7524#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
7525#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
7526#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
7527#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
7528#define DMA2D_BGPFCCR_AI_Pos (20U)
7529#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
7530#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */
7531#define DMA2D_BGPFCCR_RBS_Pos (21U)
7532#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
7533#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */
7534#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
7535#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
7536#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
7537
7538/******************** Bit definition for DMA2D_BGCOLR register **************/
7539
7540#define DMA2D_BGCOLR_BLUE_Pos (0U)
7541#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
7542#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Background Blue Value */
7543#define DMA2D_BGCOLR_GREEN_Pos (8U)
7544#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
7545#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Background Green Value */
7546#define DMA2D_BGCOLR_RED_Pos (16U)
7547#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
7548#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Background Red Value */
7549
7550/******************** Bit definition for DMA2D_FGCMAR register **************/
7551
7552#define DMA2D_FGCMAR_MA_Pos (0U)
7553#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
7554#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Foreground CLUT Memory Address */
7555
7556/******************** Bit definition for DMA2D_BGCMAR register **************/
7557
7558#define DMA2D_BGCMAR_MA_Pos (0U)
7559#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
7560#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Background CLUT Memory Address */
7561
7562/******************** Bit definition for DMA2D_OPFCCR register **************/
7563
7564#define DMA2D_OPFCCR_CM_Pos (0U)
7565#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
7566#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Output Color mode CM[2:0] */
7567#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
7568#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
7569#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
7570#define DMA2D_OPFCCR_SB_Pos (8U)
7571#define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos) /*!< 0x00000100 */
7572#define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk /*!< Swap Bytes */
7573#define DMA2D_OPFCCR_AI_Pos (20U)
7574#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
7575#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
7576#define DMA2D_OPFCCR_RBS_Pos (21U)
7577#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
7578#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */
7579
7580/******************** Bit definition for DMA2D_OCOLR register ***************/
7581
7582/*!<Mode_ARGB8888/RGB888 */
7583
7584#define DMA2D_OCOLR_BLUE_1_Pos (0U)
7585#define DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
7586#define DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk /*!< Output BLUE Value */
7587#define DMA2D_OCOLR_GREEN_1_Pos (8U)
7588#define DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
7589#define DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk /*!< Output GREEN Value */
7590#define DMA2D_OCOLR_RED_1_Pos (16U)
7591#define DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
7592#define DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk /*!< Output Red Value */
7593#define DMA2D_OCOLR_ALPHA_1_Pos (24U)
7594#define DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
7595#define DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk /*!< Output Alpha Channel Value */
7596
7597/*!<Mode_RGB565 */
7598#define DMA2D_OCOLR_BLUE_2_Pos (0U)
7599#define DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
7600#define DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk /*!< Output BLUE Value */
7601#define DMA2D_OCOLR_GREEN_2_Pos (5U)
7602#define DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
7603#define DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk /*!< Output GREEN Value */
7604#define DMA2D_OCOLR_RED_2_Pos (11U)
7605#define DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
7606#define DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk /*!< Output Red Value */
7607
7608/*!<Mode_ARGB1555 */
7609#define DMA2D_OCOLR_BLUE_3_Pos (0U)
7610#define DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
7611#define DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk /*!< Output BLUE Value */
7612#define DMA2D_OCOLR_GREEN_3_Pos (5U)
7613#define DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
7614#define DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk /*!< Output GREEN Value */
7615#define DMA2D_OCOLR_RED_3_Pos (10U)
7616#define DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
7617#define DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk /*!< Output Red Value */
7618#define DMA2D_OCOLR_ALPHA_3_Pos (15U)
7619#define DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
7620#define DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk /*!< Output Alpha Channel Value */
7621
7622/*!<Mode_ARGB4444 */
7623#define DMA2D_OCOLR_BLUE_4_Pos (0U)
7624#define DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
7625#define DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk /*!< Output BLUE Value */
7626#define DMA2D_OCOLR_GREEN_4_Pos (4U)
7627#define DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
7628#define DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk /*!< Output GREEN Value */
7629#define DMA2D_OCOLR_RED_4_Pos (8U)
7630#define DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
7631#define DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk /*!< Output Red Value */
7632#define DMA2D_OCOLR_ALPHA_4_Pos (12U)
7633#define DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
7634#define DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk /*!< Output Alpha Channel Value */
7635
7636/******************** Bit definition for DMA2D_OMAR register ****************/
7637
7638#define DMA2D_OMAR_MA_Pos (0U)
7639#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
7640#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Output Memory Address */
7641
7642/******************** Bit definition for DMA2D_OOR register *****************/
7643
7644#define DMA2D_OOR_LO_Pos (0U)
7645#define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos) /*!< 0x0000FFFF */
7646#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Output Line Offset */
7647
7648/******************** Bit definition for DMA2D_NLR register *****************/
7649
7650#define DMA2D_NLR_NL_Pos (0U)
7651#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
7652#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
7653#define DMA2D_NLR_PL_Pos (16U)
7654#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
7655#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
7656
7657/******************** Bit definition for DMA2D_LWR register *****************/
7658
7659#define DMA2D_LWR_LW_Pos (0U)
7660#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
7661#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
7662
7663/******************** Bit definition for DMA2D_AMTCR register ***************/
7664
7665#define DMA2D_AMTCR_EN_Pos (0U)
7666#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
7667#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
7668#define DMA2D_AMTCR_DT_Pos (8U)
7669#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
7670#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
7671
7672
7673/******************** Bit definition for DMA2D_FGCLUT register **************/
7674
7675/******************** Bit definition for DMA2D_BGCLUT register **************/
7676
7677
7678/******************************************************************************/
7679/* */
7680/* External Interrupt/Event Controller */
7681/* */
7682/******************************************************************************/
7683/****************** Bit definition for EXTI_RTSR1 register *******************/
7684#define EXTI_RTSR1_TR_Pos (0U)
7685#define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos) /*!< 0x003FFFFF */
7686#define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk /*!< Rising trigger event configuration bit */
7687#define EXTI_RTSR1_TR0_Pos (0U)
7688#define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos) /*!< 0x00000001 */
7689#define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
7690#define EXTI_RTSR1_TR1_Pos (1U)
7691#define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos) /*!< 0x00000002 */
7692#define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
7693#define EXTI_RTSR1_TR2_Pos (2U)
7694#define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos) /*!< 0x00000004 */
7695#define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
7696#define EXTI_RTSR1_TR3_Pos (3U)
7697#define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos) /*!< 0x00000008 */
7698#define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
7699#define EXTI_RTSR1_TR4_Pos (4U)
7700#define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos) /*!< 0x00000010 */
7701#define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
7702#define EXTI_RTSR1_TR5_Pos (5U)
7703#define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos) /*!< 0x00000020 */
7704#define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
7705#define EXTI_RTSR1_TR6_Pos (6U)
7706#define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos) /*!< 0x00000040 */
7707#define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
7708#define EXTI_RTSR1_TR7_Pos (7U)
7709#define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos) /*!< 0x00000080 */
7710#define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
7711#define EXTI_RTSR1_TR8_Pos (8U)
7712#define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos) /*!< 0x00000100 */
7713#define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
7714#define EXTI_RTSR1_TR9_Pos (9U)
7715#define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos) /*!< 0x00000200 */
7716#define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
7717#define EXTI_RTSR1_TR10_Pos (10U)
7718#define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos) /*!< 0x00000400 */
7719#define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
7720#define EXTI_RTSR1_TR11_Pos (11U)
7721#define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos) /*!< 0x00000800 */
7722#define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
7723#define EXTI_RTSR1_TR12_Pos (12U)
7724#define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos) /*!< 0x00001000 */
7725#define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
7726#define EXTI_RTSR1_TR13_Pos (13U)
7727#define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos) /*!< 0x00002000 */
7728#define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
7729#define EXTI_RTSR1_TR14_Pos (14U)
7730#define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos) /*!< 0x00004000 */
7731#define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
7732#define EXTI_RTSR1_TR15_Pos (15U)
7733#define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos) /*!< 0x00008000 */
7734#define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
7735#define EXTI_RTSR1_TR16_Pos (16U)
7736#define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos) /*!< 0x00010000 */
7737#define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
7738#define EXTI_RTSR1_TR17_Pos (17U)
7739#define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos) /*!< 0x00020000 */
7740#define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
7741#define EXTI_RTSR1_TR18_Pos (18U)
7742#define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos) /*!< 0x00040000 */
7743#define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
7744#define EXTI_RTSR1_TR19_Pos (19U)
7745#define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos) /*!< 0x00080000 */
7746#define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
7747#define EXTI_RTSR1_TR20_Pos (20U)
7748#define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos) /*!< 0x00100000 */
7749#define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
7750#define EXTI_RTSR1_TR21_Pos (21U)
7751#define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos) /*!< 0x00200000 */
7752#define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
7753
7754/****************** Bit definition for EXTI_FTSR1 register *******************/
7755#define EXTI_FTSR1_TR_Pos (0U)
7756#define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos) /*!< 0x003FFFFF */
7757#define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk /*!< Falling trigger event configuration bit */
7758#define EXTI_FTSR1_TR0_Pos (0U)
7759#define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos) /*!< 0x00000001 */
7760#define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
7761#define EXTI_FTSR1_TR1_Pos (1U)
7762#define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos) /*!< 0x00000002 */
7763#define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
7764#define EXTI_FTSR1_TR2_Pos (2U)
7765#define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos) /*!< 0x00000004 */
7766#define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
7767#define EXTI_FTSR1_TR3_Pos (3U)
7768#define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos) /*!< 0x00000008 */
7769#define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
7770#define EXTI_FTSR1_TR4_Pos (4U)
7771#define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos) /*!< 0x00000010 */
7772#define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
7773#define EXTI_FTSR1_TR5_Pos (5U)
7774#define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos) /*!< 0x00000020 */
7775#define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
7776#define EXTI_FTSR1_TR6_Pos (6U)
7777#define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos) /*!< 0x00000040 */
7778#define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
7779#define EXTI_FTSR1_TR7_Pos (7U)
7780#define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos) /*!< 0x00000080 */
7781#define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
7782#define EXTI_FTSR1_TR8_Pos (8U)
7783#define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos) /*!< 0x00000100 */
7784#define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
7785#define EXTI_FTSR1_TR9_Pos (9U)
7786#define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos) /*!< 0x00000200 */
7787#define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
7788#define EXTI_FTSR1_TR10_Pos (10U)
7789#define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos) /*!< 0x00000400 */
7790#define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
7791#define EXTI_FTSR1_TR11_Pos (11U)
7792#define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos) /*!< 0x00000800 */
7793#define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
7794#define EXTI_FTSR1_TR12_Pos (12U)
7795#define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos) /*!< 0x00001000 */
7796#define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
7797#define EXTI_FTSR1_TR13_Pos (13U)
7798#define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos) /*!< 0x00002000 */
7799#define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
7800#define EXTI_FTSR1_TR14_Pos (14U)
7801#define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos) /*!< 0x00004000 */
7802#define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
7803#define EXTI_FTSR1_TR15_Pos (15U)
7804#define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos) /*!< 0x00008000 */
7805#define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
7806#define EXTI_FTSR1_TR16_Pos (16U)
7807#define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos) /*!< 0x00010000 */
7808#define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
7809#define EXTI_FTSR1_TR17_Pos (17U)
7810#define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos) /*!< 0x00020000 */
7811#define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
7812#define EXTI_FTSR1_TR18_Pos (18U)
7813#define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos) /*!< 0x00040000 */
7814#define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
7815#define EXTI_FTSR1_TR19_Pos (19U)
7816#define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos) /*!< 0x00080000 */
7817#define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
7818#define EXTI_FTSR1_TR20_Pos (20U)
7819#define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos) /*!< 0x00100000 */
7820#define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
7821#define EXTI_FTSR1_TR21_Pos (21U)
7822#define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos) /*!< 0x00200000 */
7823#define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
7824
7825/****************** Bit definition for EXTI_SWIER1 register ******************/
7826#define EXTI_SWIER1_SWIER0_Pos (0U)
7827#define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos) /*!< 0x00000001 */
7828#define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk /*!< Software Interrupt on line 0 */
7829#define EXTI_SWIER1_SWIER1_Pos (1U)
7830#define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos) /*!< 0x00000002 */
7831#define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk /*!< Software Interrupt on line 1 */
7832#define EXTI_SWIER1_SWIER2_Pos (2U)
7833#define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos) /*!< 0x00000004 */
7834#define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk /*!< Software Interrupt on line 2 */
7835#define EXTI_SWIER1_SWIER3_Pos (3U)
7836#define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos) /*!< 0x00000008 */
7837#define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk /*!< Software Interrupt on line 3 */
7838#define EXTI_SWIER1_SWIER4_Pos (4U)
7839#define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos) /*!< 0x00000010 */
7840#define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk /*!< Software Interrupt on line 4 */
7841#define EXTI_SWIER1_SWIER5_Pos (5U)
7842#define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos) /*!< 0x00000020 */
7843#define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk /*!< Software Interrupt on line 5 */
7844#define EXTI_SWIER1_SWIER6_Pos (6U)
7845#define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos) /*!< 0x00000040 */
7846#define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk /*!< Software Interrupt on line 6 */
7847#define EXTI_SWIER1_SWIER7_Pos (7U)
7848#define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos) /*!< 0x00000080 */
7849#define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk /*!< Software Interrupt on line 7 */
7850#define EXTI_SWIER1_SWIER8_Pos (8U)
7851#define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos) /*!< 0x00000100 */
7852#define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk /*!< Software Interrupt on line 8 */
7853#define EXTI_SWIER1_SWIER9_Pos (9U)
7854#define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos) /*!< 0x00000200 */
7855#define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk /*!< Software Interrupt on line 9 */
7856#define EXTI_SWIER1_SWIER10_Pos (10U)
7857#define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos) /*!< 0x00000400 */
7858#define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk /*!< Software Interrupt on line 10 */
7859#define EXTI_SWIER1_SWIER11_Pos (11U)
7860#define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos) /*!< 0x00000800 */
7861#define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk /*!< Software Interrupt on line 11 */
7862#define EXTI_SWIER1_SWIER12_Pos (12U)
7863#define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos) /*!< 0x00001000 */
7864#define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk /*!< Software Interrupt on line 12 */
7865#define EXTI_SWIER1_SWIER13_Pos (13U)
7866#define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos) /*!< 0x00002000 */
7867#define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk /*!< Software Interrupt on line 13 */
7868#define EXTI_SWIER1_SWIER14_Pos (14U)
7869#define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos) /*!< 0x00004000 */
7870#define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk /*!< Software Interrupt on line 14 */
7871#define EXTI_SWIER1_SWIER15_Pos (15U)
7872#define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos) /*!< 0x00008000 */
7873#define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk /*!< Software Interrupt on line 15 */
7874#define EXTI_SWIER1_SWIER16_Pos (16U)
7875#define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos) /*!< 0x00010000 */
7876#define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk /*!< Software Interrupt on line 16 */
7877#define EXTI_SWIER1_SWIER17_Pos (17U)
7878#define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos) /*!< 0x00020000 */
7879#define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk /*!< Software Interrupt on line 17 */
7880#define EXTI_SWIER1_SWIER18_Pos (18U)
7881#define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos) /*!< 0x00040000 */
7882#define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk /*!< Software Interrupt on line 18 */
7883#define EXTI_SWIER1_SWIER19_Pos (19U)
7884#define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos) /*!< 0x00080000 */
7885#define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk /*!< Software Interrupt on line 19 */
7886#define EXTI_SWIER1_SWIER20_Pos (20U)
7887#define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos) /*!< 0x00100000 */
7888#define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk /*!< Software Interrupt on line 20 */
7889#define EXTI_SWIER1_SWIER21_Pos (21U)
7890#define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos) /*!< 0x00200000 */
7891#define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk /*!< Software Interrupt on line 21 */
7892
7893/****************** Bit definition for EXTI_D3PMR1 register ******************/
7894#define EXTI_D3PMR1_MR0_Pos (0U)
7895#define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos) /*!< 0x00000001 */
7896#define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk /*!< Pending Mask Event for line 0 */
7897#define EXTI_D3PMR1_MR1_Pos (1U)
7898#define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos) /*!< 0x00000002 */
7899#define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk /*!< Pending Mask Event for line 1 */
7900#define EXTI_D3PMR1_MR2_Pos (2U)
7901#define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos) /*!< 0x00000004 */
7902#define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk /*!< Pending Mask Event for line 2 */
7903#define EXTI_D3PMR1_MR3_Pos (3U)
7904#define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos) /*!< 0x00000008 */
7905#define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk /*!< Pending Mask Event for line 3 */
7906#define EXTI_D3PMR1_MR4_Pos (4U)
7907#define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos) /*!< 0x00000010 */
7908#define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk /*!< Pending Mask Event for line 4 */
7909#define EXTI_D3PMR1_MR5_Pos (5U)
7910#define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos) /*!< 0x00000020 */
7911#define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk /*!< Pending Mask Event for line 5 */
7912#define EXTI_D3PMR1_MR6_Pos (6U)
7913#define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos) /*!< 0x00000040 */
7914#define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk /*!< Pending Mask Event for line 6 */
7915#define EXTI_D3PMR1_MR7_Pos (7U)
7916#define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos) /*!< 0x00000080 */
7917#define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk /*!< Pending Mask Event for line 7 */
7918#define EXTI_D3PMR1_MR8_Pos (8U)
7919#define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos) /*!< 0x00000100 */
7920#define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk /*!< Pending Mask Event for line 8 */
7921#define EXTI_D3PMR1_MR9_Pos (9U)
7922#define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos) /*!< 0x00000200 */
7923#define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk /*!< Pending Mask Event for line 9 */
7924#define EXTI_D3PMR1_MR10_Pos (10U)
7925#define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos) /*!< 0x00000400 */
7926#define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk /*!< Pending Mask Event for line 10 */
7927#define EXTI_D3PMR1_MR11_Pos (11U)
7928#define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos) /*!< 0x00000800 */
7929#define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk /*!< Pending Mask Event for line 11 */
7930#define EXTI_D3PMR1_MR12_Pos (12U)
7931#define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos) /*!< 0x00001000 */
7932#define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk /*!< Pending Mask Event for line 12 */
7933#define EXTI_D3PMR1_MR13_Pos (13U)
7934#define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos) /*!< 0x00002000 */
7935#define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk /*!< Pending Mask Event for line 13 */
7936#define EXTI_D3PMR1_MR14_Pos (14U)
7937#define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos) /*!< 0x00004000 */
7938#define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk /*!< Pending Mask Event for line 14 */
7939#define EXTI_D3PMR1_MR15_Pos (15U)
7940#define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos) /*!< 0x00008000 */
7941#define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk /*!< Pending Mask Event for line 15 */
7942#define EXTI_D3PMR1_MR19_Pos (19U)
7943#define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos) /*!< 0x00080000 */
7944#define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk /*!< Pending Mask Event for line 19 */
7945#define EXTI_D3PMR1_MR20_Pos (20U)
7946#define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos) /*!< 0x00100000 */
7947#define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk /*!< Pending Mask Event for line 20 */
7948#define EXTI_D3PMR1_MR21_Pos (21U)
7949#define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos) /*!< 0x00200000 */
7950#define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk /*!< Pending Mask Event for line 21 */
7951#define EXTI_D3PMR1_MR25_Pos (24U)
7952#define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos) /*!< 0x01000000 */
7953#define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk /*!< Pending Mask Event for line 25 */
7954
7955/******************* Bit definition for EXTI_D3PCR1L register ****************/
7956#define EXTI_D3PCR1L_PCS0_Pos (0U)
7957#define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos) /*!< 0x00000003 */
7958#define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk /*!< D3 Pending request clear input signal selection on line 0 */
7959#define EXTI_D3PCR1L_PCS1_Pos (2U)
7960#define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos) /*!< 0x000000C0 */
7961#define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk /*!< D3 Pending request clear input signal selection on line 1 */
7962#define EXTI_D3PCR1L_PCS2_Pos (4U)
7963#define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos) /*!< 0x00000030 */
7964#define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk /*!< D3 Pending request clear input signal selection on line 2 */
7965#define EXTI_D3PCR1L_PCS3_Pos (6U)
7966#define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos) /*!< 0x000000C0 */
7967#define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk /*!< D3 Pending request clear input signal selection on line 3 */
7968#define EXTI_D3PCR1L_PCS4_Pos (8U)
7969#define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos) /*!< 0x00000300 */
7970#define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk /*!< D3 Pending request clear input signal selection on line 4 */
7971#define EXTI_D3PCR1L_PCS5_Pos (10U)
7972#define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos) /*!< 0x00000C00 */
7973#define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk /*!< D3 Pending request clear input signal selection on line 5 */