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1/**
2 ******************************************************************************
3 * @file stm32l041xx.h
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
6 * This file contains all the peripheral register's definitions, bits
7 * definitions and memory mapping for stm32l041xx devices.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44/** @addtogroup CMSIS
45 * @{
46 */
47
48/** @addtogroup stm32l041xx
49 * @{
50 */
51
52#ifndef __STM32L041xx_H
53#define __STM32L041xx_H
54
55#ifdef __cplusplus
56 extern "C" {
57#endif
58
59
60/** @addtogroup Configuration_section_for_CMSIS
61 * @{
62 */
63/**
64 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
65 */
66#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
67#define __MPU_PRESENT 0 /*!< STM32L0xx provides no MPU */
68#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
69#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
70#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
71
72/**
73 * @}
74 */
75
76/** @addtogroup Peripheral_interrupt_number_definition
77 * @{
78 */
79
80/**
81 * @brief stm32l041xx Interrupt Number Definition, according to the selected device
82 * in @ref Library_configuration_section
83 */
84
85/*!< Interrupt Number Definition */
86typedef enum
87{
88/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
90 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
91 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
92 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
93 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
94
95/****** STM32L-0 specific Interrupt Numbers *********************************************************/
96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
97 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
98 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
99 FLASH_IRQn = 3, /*!< FLASH Interrupt */
100 RCC_IRQn = 4, /*!< RCC Interrupt */
101 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
102 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
103 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
104 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
105 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
106 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
107 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
108 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
109 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
110 TIM21_IRQn = 20, /*!< TIM21 Interrupt */
111 TIM22_IRQn = 22, /*!< TIM22 Interrupt */
112 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
113 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
114 USART2_IRQn = 28, /*!< USART2 Interrupt */
115 AES_LPUART1_IRQn = 29, /*!< AES and LPUART1 Interrupts */
116} IRQn_Type;
117
118/**
119 * @}
120 */
121
122#include "core_cm0plus.h"
123#include "system_stm32l0xx.h"
124#include <stdint.h>
125
126/** @addtogroup Peripheral_registers_structures
127 * @{
128 */
129
130/**
131 * @brief Analog to Digital Converter
132 */
133
134typedef struct
135{
136 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
137 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
138 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
139 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
140 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
141 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
142 uint32_t RESERVED1; /*!< Reserved, 0x18 */
143 uint32_t RESERVED2; /*!< Reserved, 0x1C */
144 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
145 uint32_t RESERVED3; /*!< Reserved, 0x24 */
146 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
147 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
148 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
149 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
150 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
151} ADC_TypeDef;
152
153typedef struct
154{
155 __IO uint32_t CCR;
156} ADC_Common_TypeDef;
157
158/**
159 * @brief AES hardware accelerator
160 */
161
162typedef struct
163{
164 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
165 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
166 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
167 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
168 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
169 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
170 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
171 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
172 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
173 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
174 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
175 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
176} AES_TypeDef;
177
178/**
179 * @brief Comparator
180 */
181
182typedef struct
183{
184 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
185} COMP_TypeDef;
186
187typedef struct
188{
189 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
190} COMP_Common_TypeDef;
191
192
193/**
194* @brief CRC calculation unit
195*/
196
197typedef struct
198{
199__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
200__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
201uint8_t RESERVED0; /*!< Reserved, 0x05 */
202uint16_t RESERVED1; /*!< Reserved, 0x06 */
203__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
204uint32_t RESERVED2; /*!< Reserved, 0x0C */
205__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
206__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
207} CRC_TypeDef;
208
209/**
210 * @brief Debug MCU
211 */
212
213typedef struct
214{
215 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
216 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
217 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
218 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
219}DBGMCU_TypeDef;
220
221/**
222 * @brief DMA Controller
223 */
224
225typedef struct
226{
227 __IO uint32_t CCR; /*!< DMA channel x configuration register */
228 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
229 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
230 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
231} DMA_Channel_TypeDef;
232
233typedef struct
234{
235 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
236 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
237} DMA_TypeDef;
238
239typedef struct
240{
241 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
242} DMA_Request_TypeDef;
243
244/**
245 * @brief External Interrupt/Event Controller
246 */
247
248typedef struct
249{
250 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
251 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
252 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
253 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
254 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
255 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
256}EXTI_TypeDef;
257
258/**
259 * @brief FLASH Registers
260 */
261typedef struct
262{
263 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
264 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
265 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
266 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
267 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
268 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
269 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
270 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
271 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
272} FLASH_TypeDef;
273
274
275/**
276 * @brief Option Bytes Registers
277 */
278typedef struct
279{
280 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
281 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
282 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
283} OB_TypeDef;
284
285
286/**
287 * @brief General Purpose IO
288 */
289
290typedef struct
291{
292 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
293 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
294 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
295 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
296 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
297 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
298 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
299 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
300 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
301 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
302}GPIO_TypeDef;
303
304/**
305 * @brief LPTIMIMER
306 */
307typedef struct
308{
309 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
310 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
311 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
312 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
313 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
314 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
315 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
316 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
317} LPTIM_TypeDef;
318
319/**
320 * @brief SysTem Configuration
321 */
322
323typedef struct
324{
325 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
326 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
327 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
328 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
329 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
330} SYSCFG_TypeDef;
331
332
333
334/**
335 * @brief Inter-integrated Circuit Interface
336 */
337
338typedef struct
339{
340 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
341 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
342 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
343 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
344 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
345 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
346 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
347 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
348 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
349 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
350 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
351}I2C_TypeDef;
352
353
354/**
355 * @brief Independent WATCHDOG
356 */
357typedef struct
358{
359 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
360 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
361 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
362 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
363 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
364} IWDG_TypeDef;
365
366/**
367 * @brief Power Control
368 */
369typedef struct
370{
371 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
372 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
373} PWR_TypeDef;
374
375/**
376 * @brief Reset and Clock Control
377 */
378typedef struct
379{
380 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
381 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
382 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
383 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
384 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
385 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
386 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
387 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
388 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
389 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
390 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
391 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
392 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
393 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
394 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
395 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
396 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
397 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
398 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
399 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
400 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
401} RCC_TypeDef;
402
403/**
404 * @brief Real-Time Clock
405 */
406typedef struct
407{
408 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
409 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
410 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
411 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
412 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
413 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
414 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
415 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
416 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
417 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
418 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
419 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
420 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
421 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
422 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
423 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
424 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
425 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
426 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
427 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
428 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
429 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
430 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
431 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
432 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
433} RTC_TypeDef;
434
435
436/**
437 * @brief Serial Peripheral Interface
438 */
439typedef struct
440{
441 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
442 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
443 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
444 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
445 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
446 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
447 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
448} SPI_TypeDef;
449
450/**
451 * @brief TIM
452 */
453typedef struct
454{
455 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
456 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
457 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
458 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
459 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
460 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
461 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
462 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
463 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
464 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
465 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
466 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
467 uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
468 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
469 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
470 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
471 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
472 uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
473 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
474 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
475 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
476} TIM_TypeDef;
477
478/**
479 * @brief Universal Synchronous Asynchronous Receiver Transmitter
480 */
481typedef struct
482{
483 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
484 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
485 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
486 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
487 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
488 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
489 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
490 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
491 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
492 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
493 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
494} USART_TypeDef;
495
496/**
497 * @brief Window WATCHDOG
498 */
499typedef struct
500{
501 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
502 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
503 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
504} WWDG_TypeDef;
505
506
507/**
508 * @}
509 */
510
511/** @addtogroup Peripheral_memory_map
512 * @{
513 */
514#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
515#define FLASH_END ((uint32_t)0x08007FFFU) /*!< FLASH end address in the alias region */
516#define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
517#define DATA_EEPROM_END ((uint32_t)0x080803FFU) /*!< DATA EEPROM end address in the alias region */
518#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
519#define SRAM_SIZE_MAX ((uint32_t)0x00002000U) /*!< maximum SRAM size (up to 8KBytes) */
520
521#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
522
523/*!< Peripheral memory map */
524#define APBPERIPH_BASE PERIPH_BASE
525#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
526#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000U)
527
528#define TIM2_BASE (APBPERIPH_BASE + 0x00000000U)
529#define RTC_BASE (APBPERIPH_BASE + 0x00002800U)
530#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U)
531#define IWDG_BASE (APBPERIPH_BASE + 0x00003000U)
532#define USART2_BASE (APBPERIPH_BASE + 0x00004400U)
533#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800U)
534#define I2C1_BASE (APBPERIPH_BASE + 0x00005400U)
535#define PWR_BASE (APBPERIPH_BASE + 0x00007000U)
536#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U)
537
538#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000U)
539#define COMP1_BASE (APBPERIPH_BASE + 0x00010018U)
540#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CU)
541#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
542#define EXTI_BASE (APBPERIPH_BASE + 0x00010400U)
543#define TIM21_BASE (APBPERIPH_BASE + 0x00010800U)
544#define TIM22_BASE (APBPERIPH_BASE + 0x00011400U)
545#define ADC1_BASE (APBPERIPH_BASE + 0x00012400U)
546#define ADC_BASE (APBPERIPH_BASE + 0x00012708U)
547#define SPI1_BASE (APBPERIPH_BASE + 0x00013000U)
548#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800U)
549
550#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
551#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
552#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
553#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
554#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
555#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
556#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
557#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
558#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U)
559
560
561#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
562#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
563#define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
564#define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */
565#define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */
566#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
567#define AES_BASE (AHBPERIPH_BASE + 0x00006000U)
568
569#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U)
570#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U)
571#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800U)
572#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00U)
573
574/**
575 * @}
576 */
577
578/** @addtogroup Peripheral_declaration
579 * @{
580 */
581
582#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
583#define RTC ((RTC_TypeDef *) RTC_BASE)
584#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
585#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
586#define USART2 ((USART_TypeDef *) USART2_BASE)
587#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
588#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
589#define PWR ((PWR_TypeDef *) PWR_BASE)
590#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
591
592#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
593#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
594#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
595#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
596#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
597#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
598#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
599#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
600/* Legacy defines */
601#define ADC ADC1_COMMON
602#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
603#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
604
605#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
606#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
607#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
608#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
609#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
610#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
611#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
612#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
613#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
614
615
616#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
617#define OB ((OB_TypeDef *) OB_BASE)
618#define RCC ((RCC_TypeDef *) RCC_BASE)
619#define CRC ((CRC_TypeDef *) CRC_BASE)
620#define AES ((AES_TypeDef *) AES_BASE)
621
622#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
623#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
624#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
625#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
626
627/**
628 * @}
629 */
630
631/** @addtogroup Exported_constants
632 * @{
633 */
634
635 /** @addtogroup Peripheral_Registers_Bits_Definition
636 * @{
637 */
638
639/******************************************************************************/
640/* Peripheral Registers Bits Definition */
641/******************************************************************************/
642/******************************************************************************/
643/* */
644/* Analog to Digital Converter (ADC) */
645/* */
646/******************************************************************************/
647/******************** Bits definition for ADC_ISR register ******************/
648#define ADC_ISR_EOCAL_Pos (11U)
649#define ADC_ISR_EOCAL_Msk (0x1U << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
650#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
651#define ADC_ISR_AWD_Pos (7U)
652#define ADC_ISR_AWD_Msk (0x1U << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
653#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
654#define ADC_ISR_OVR_Pos (4U)
655#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
656#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
657#define ADC_ISR_EOSEQ_Pos (3U)
658#define ADC_ISR_EOSEQ_Msk (0x1U << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
659#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
660#define ADC_ISR_EOC_Pos (2U)
661#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
662#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
663#define ADC_ISR_EOSMP_Pos (1U)
664#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
665#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
666#define ADC_ISR_ADRDY_Pos (0U)
667#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
668#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
669
670/* Old EOSEQ bit definition, maintained for legacy purpose */
671#define ADC_ISR_EOS ADC_ISR_EOSEQ
672
673/******************** Bits definition for ADC_IER register ******************/
674#define ADC_IER_EOCALIE_Pos (11U)
675#define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
676#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
677#define ADC_IER_AWDIE_Pos (7U)
678#define ADC_IER_AWDIE_Msk (0x1U << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
679#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
680#define ADC_IER_OVRIE_Pos (4U)
681#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
682#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
683#define ADC_IER_EOSEQIE_Pos (3U)
684#define ADC_IER_EOSEQIE_Msk (0x1U << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
685#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
686#define ADC_IER_EOCIE_Pos (2U)
687#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
688#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
689#define ADC_IER_EOSMPIE_Pos (1U)
690#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
691#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
692#define ADC_IER_ADRDYIE_Pos (0U)
693#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
694#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
695
696/* Old EOSEQIE bit definition, maintained for legacy purpose */
697#define ADC_IER_EOSIE ADC_IER_EOSEQIE
698
699/******************** Bits definition for ADC_CR register *******************/
700#define ADC_CR_ADCAL_Pos (31U)
701#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
702#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
703#define ADC_CR_ADVREGEN_Pos (28U)
704#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
705#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
706#define ADC_CR_ADSTP_Pos (4U)
707#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
708#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
709#define ADC_CR_ADSTART_Pos (2U)
710#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
711#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
712#define ADC_CR_ADDIS_Pos (1U)
713#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
714#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
715#define ADC_CR_ADEN_Pos (0U)
716#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
717#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
718
719/******************* Bits definition for ADC_CFGR1 register *****************/
720#define ADC_CFGR1_AWDCH_Pos (26U)
721#define ADC_CFGR1_AWDCH_Msk (0x1FU << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
722#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
723#define ADC_CFGR1_AWDCH_0 (0x01U << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
724#define ADC_CFGR1_AWDCH_1 (0x02U << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
725#define ADC_CFGR1_AWDCH_2 (0x04U << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
726#define ADC_CFGR1_AWDCH_3 (0x08U << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
727#define ADC_CFGR1_AWDCH_4 (0x10U << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
728#define ADC_CFGR1_AWDEN_Pos (23U)
729#define ADC_CFGR1_AWDEN_Msk (0x1U << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
730#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
731#define ADC_CFGR1_AWDSGL_Pos (22U)
732#define ADC_CFGR1_AWDSGL_Msk (0x1U << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
733#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
734#define ADC_CFGR1_DISCEN_Pos (16U)
735#define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
736#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
737#define ADC_CFGR1_AUTOFF_Pos (15U)
738#define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
739#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
740#define ADC_CFGR1_WAIT_Pos (14U)
741#define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
742#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
743#define ADC_CFGR1_CONT_Pos (13U)
744#define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
745#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
746#define ADC_CFGR1_OVRMOD_Pos (12U)
747#define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
748#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
749#define ADC_CFGR1_EXTEN_Pos (10U)
750#define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
751#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
752#define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
753#define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
754#define ADC_CFGR1_EXTSEL_Pos (6U)
755#define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
756#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
757#define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
758#define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
759#define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
760#define ADC_CFGR1_ALIGN_Pos (5U)
761#define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
762#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
763#define ADC_CFGR1_RES_Pos (3U)
764#define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
765#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
766#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
767#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
768#define ADC_CFGR1_SCANDIR_Pos (2U)
769#define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
770#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
771#define ADC_CFGR1_DMACFG_Pos (1U)
772#define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
773#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
774#define ADC_CFGR1_DMAEN_Pos (0U)
775#define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
776#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
777
778/* Old WAIT bit definition, maintained for legacy purpose */
779#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
780
781/******************* Bits definition for ADC_CFGR2 register *****************/
782#define ADC_CFGR2_TOVS_Pos (9U)
783#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
784#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
785#define ADC_CFGR2_OVSS_Pos (5U)
786#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
787#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
788#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
789#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
790#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
791#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
792#define ADC_CFGR2_OVSR_Pos (2U)
793#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
794#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
795#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
796#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
797#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
798#define ADC_CFGR2_OVSE_Pos (0U)
799#define ADC_CFGR2_OVSE_Msk (0x1U << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
800#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
801#define ADC_CFGR2_CKMODE_Pos (30U)
802#define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
803#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
804#define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
805#define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
806
807
808/****************** Bit definition for ADC_SMPR register ********************/
809#define ADC_SMPR_SMP_Pos (0U)
810#define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
811#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
812#define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
813#define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
814#define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
815
816/* Legacy defines */
817#define ADC_SMPR_SMPR ADC_SMPR_SMP
818#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
819#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
820#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
821
822/******************* Bit definition for ADC_TR register ********************/
823#define ADC_TR_HT_Pos (16U)
824#define ADC_TR_HT_Msk (0xFFFU << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
825#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
826#define ADC_TR_LT_Pos (0U)
827#define ADC_TR_LT_Msk (0xFFFU << ADC_TR_LT_Pos) /*!< 0x00000FFF */
828#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
829
830/****************** Bit definition for ADC_CHSELR register ******************/
831#define ADC_CHSELR_CHSEL_Pos (0U)
832#define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
833#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
834#define ADC_CHSELR_CHSEL18_Pos (18U)
835#define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
836#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
837#define ADC_CHSELR_CHSEL17_Pos (17U)
838#define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
839#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
840#define ADC_CHSELR_CHSEL15_Pos (15U)
841#define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
842#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
843#define ADC_CHSELR_CHSEL14_Pos (14U)
844#define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
845#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
846#define ADC_CHSELR_CHSEL13_Pos (13U)
847#define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
848#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
849#define ADC_CHSELR_CHSEL12_Pos (12U)
850#define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
851#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
852#define ADC_CHSELR_CHSEL11_Pos (11U)
853#define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
854#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
855#define ADC_CHSELR_CHSEL10_Pos (10U)
856#define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
857#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
858#define ADC_CHSELR_CHSEL9_Pos (9U)
859#define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
860#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
861#define ADC_CHSELR_CHSEL8_Pos (8U)
862#define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
863#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
864#define ADC_CHSELR_CHSEL7_Pos (7U)
865#define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
866#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
867#define ADC_CHSELR_CHSEL6_Pos (6U)
868#define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
869#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
870#define ADC_CHSELR_CHSEL5_Pos (5U)
871#define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
872#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
873#define ADC_CHSELR_CHSEL4_Pos (4U)
874#define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
875#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
876#define ADC_CHSELR_CHSEL3_Pos (3U)
877#define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
878#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
879#define ADC_CHSELR_CHSEL2_Pos (2U)
880#define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
881#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
882#define ADC_CHSELR_CHSEL1_Pos (1U)
883#define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
884#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
885#define ADC_CHSELR_CHSEL0_Pos (0U)
886#define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
887#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
888
889/******************** Bit definition for ADC_DR register ********************/
890#define ADC_DR_DATA_Pos (0U)
891#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
892#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
893
894/******************** Bit definition for ADC_CALFACT register ********************/
895#define ADC_CALFACT_CALFACT_Pos (0U)
896#define ADC_CALFACT_CALFACT_Msk (0x7FU << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
897#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
898
899/******************* Bit definition for ADC_CCR register ********************/
900#define ADC_CCR_LFMEN_Pos (25U)
901#define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
902#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
903#define ADC_CCR_TSEN_Pos (23U)
904#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
905#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
906#define ADC_CCR_VREFEN_Pos (22U)
907#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
908#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
909#define ADC_CCR_PRESC_Pos (18U)
910#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
911#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
912#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
913#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
914#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
915#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
916
917/******************************************************************************/
918/* */
919/* Advanced Encryption Standard (AES) */
920/* */
921/******************************************************************************/
922/******************* Bit definition for AES_CR register *********************/
923#define AES_CR_EN_Pos (0U)
924#define AES_CR_EN_Msk (0x1U << AES_CR_EN_Pos) /*!< 0x00000001 */
925#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
926#define AES_CR_DATATYPE_Pos (1U)
927#define AES_CR_DATATYPE_Msk (0x3U << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
928#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
929#define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
930#define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
931
932#define AES_CR_MODE_Pos (3U)
933#define AES_CR_MODE_Msk (0x3U << AES_CR_MODE_Pos) /*!< 0x00000018 */
934#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
935#define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */
936#define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */
937
938#define AES_CR_CHMOD_Pos (5U)
939#define AES_CR_CHMOD_Msk (0x3U << AES_CR_CHMOD_Pos) /*!< 0x00000060 */
940#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
941#define AES_CR_CHMOD_0 (0x1U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
942#define AES_CR_CHMOD_1 (0x2U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
943
944#define AES_CR_CCFC_Pos (7U)
945#define AES_CR_CCFC_Msk (0x1U << AES_CR_CCFC_Pos) /*!< 0x00000080 */
946#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
947#define AES_CR_ERRC_Pos (8U)
948#define AES_CR_ERRC_Msk (0x1U << AES_CR_ERRC_Pos) /*!< 0x00000100 */
949#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
950#define AES_CR_CCIE_Pos (9U)
951#define AES_CR_CCIE_Msk (0x1U << AES_CR_CCIE_Pos) /*!< 0x00000200 */
952#define AES_CR_CCIE AES_CR_CCIE_Msk /*!< Computation Complete Interrupt Enable */
953#define AES_CR_ERRIE_Pos (10U)
954#define AES_CR_ERRIE_Msk (0x1U << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
955#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
956#define AES_CR_DMAINEN_Pos (11U)
957#define AES_CR_DMAINEN_Msk (0x1U << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
958#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA ENable managing the data input phase */
959#define AES_CR_DMAOUTEN_Pos (12U)
960#define AES_CR_DMAOUTEN_Msk (0x1U << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
961#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA Enable managing the data output phase */
962
963/******************* Bit definition for AES_SR register *********************/
964#define AES_SR_CCF_Pos (0U)
965#define AES_SR_CCF_Msk (0x1U << AES_SR_CCF_Pos) /*!< 0x00000001 */
966#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
967#define AES_SR_RDERR_Pos (1U)
968#define AES_SR_RDERR_Msk (0x1U << AES_SR_RDERR_Pos) /*!< 0x00000002 */
969#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
970#define AES_SR_WRERR_Pos (2U)
971#define AES_SR_WRERR_Msk (0x1U << AES_SR_WRERR_Pos) /*!< 0x00000004 */
972#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
973
974/******************* Bit definition for AES_DINR register *******************/
975#define AES_DINR_Pos (0U)
976#define AES_DINR_Msk (0xFFFFU << AES_DINR_Pos) /*!< 0x0000FFFF */
977#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
978
979/******************* Bit definition for AES_DOUTR register ******************/
980#define AES_DOUTR_Pos (0U)
981#define AES_DOUTR_Msk (0xFFFFU << AES_DOUTR_Pos) /*!< 0x0000FFFF */
982#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
983
984/******************* Bit definition for AES_KEYR0 register ******************/
985#define AES_KEYR0_Pos (0U)
986#define AES_KEYR0_Msk (0xFFFFU << AES_KEYR0_Pos) /*!< 0x0000FFFF */
987#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
988
989/******************* Bit definition for AES_KEYR1 register ******************/
990#define AES_KEYR1_Pos (0U)
991#define AES_KEYR1_Msk (0xFFFFU << AES_KEYR1_Pos) /*!< 0x0000FFFF */
992#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
993
994/******************* Bit definition for AES_KEYR2 register ******************/
995#define AES_KEYR2_Pos (0U)
996#define AES_KEYR2_Msk (0xFFFFU << AES_KEYR2_Pos) /*!< 0x0000FFFF */
997#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
998
999/******************* Bit definition for AES_KEYR3 register ******************/
1000#define AES_KEYR3_Pos (0U)
1001#define AES_KEYR3_Msk (0xFFFFU << AES_KEYR3_Pos) /*!< 0x0000FFFF */
1002#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
1003
1004/******************* Bit definition for AES_IVR0 register *******************/
1005#define AES_IVR0_Pos (0U)
1006#define AES_IVR0_Msk (0xFFFFU << AES_IVR0_Pos) /*!< 0x0000FFFF */
1007#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
1008
1009/******************* Bit definition for AES_IVR1 register *******************/
1010#define AES_IVR1_Pos (0U)
1011#define AES_IVR1_Msk (0xFFFFU << AES_IVR1_Pos) /*!< 0x0000FFFF */
1012#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
1013
1014/******************* Bit definition for AES_IVR2 register *******************/
1015#define AES_IVR2_Pos (0U)
1016#define AES_IVR2_Msk (0xFFFFU << AES_IVR2_Pos) /*!< 0x0000FFFF */
1017#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
1018
1019/******************* Bit definition for AES_IVR3 register *******************/
1020#define AES_IVR3_Pos (0U)
1021#define AES_IVR3_Msk (0xFFFFU << AES_IVR3_Pos) /*!< 0x0000FFFF */
1022#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
1023
1024/******************************************************************************/
1025/* */
1026/* Analog Comparators (COMP) */
1027/* */
1028/******************************************************************************/
1029/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
1030/* COMP1 bits definition */
1031#define COMP_CSR_COMP1EN_Pos (0U)
1032#define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
1033#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
1034#define COMP_CSR_COMP1INNSEL_Pos (4U)
1035#define COMP_CSR_COMP1INNSEL_Msk (0x3U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1036#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
1037#define COMP_CSR_COMP1INNSEL_0 (0x1U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1038#define COMP_CSR_COMP1INNSEL_1 (0x2U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
1039#define COMP_CSR_COMP1WM_Pos (8U)
1040#define COMP_CSR_COMP1WM_Msk (0x1U << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
1041#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
1042#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
1043#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
1044#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
1045#define COMP_CSR_COMP1POLARITY_Pos (15U)
1046#define COMP_CSR_COMP1POLARITY_Msk (0x1U << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
1047#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
1048#define COMP_CSR_COMP1VALUE_Pos (30U)
1049#define COMP_CSR_COMP1VALUE_Msk (0x1U << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
1050#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
1051#define COMP_CSR_COMP1LOCK_Pos (31U)
1052#define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
1053#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
1054/* COMP2 bits definition */
1055#define COMP_CSR_COMP2EN_Pos (0U)
1056#define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
1057#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
1058#define COMP_CSR_COMP2SPEED_Pos (3U)
1059#define COMP_CSR_COMP2SPEED_Msk (0x1U << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
1060#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
1061#define COMP_CSR_COMP2INNSEL_Pos (4U)
1062#define COMP_CSR_COMP2INNSEL_Msk (0x7U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
1063#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
1064#define COMP_CSR_COMP2INNSEL_0 (0x1U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
1065#define COMP_CSR_COMP2INNSEL_1 (0x2U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
1066#define COMP_CSR_COMP2INNSEL_2 (0x4U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1067#define COMP_CSR_COMP2INPSEL_Pos (8U)
1068#define COMP_CSR_COMP2INPSEL_Msk (0x7U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
1069#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
1070#define COMP_CSR_COMP2INPSEL_0 (0x1U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
1071#define COMP_CSR_COMP2INPSEL_1 (0x2U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
1072#define COMP_CSR_COMP2INPSEL_2 (0x4U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
1073#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
1074#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
1075#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
1076#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
1077#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
1078#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
1079#define COMP_CSR_COMP2POLARITY_Pos (15U)
1080#define COMP_CSR_COMP2POLARITY_Msk (0x1U << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
1081#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
1082#define COMP_CSR_COMP2VALUE_Pos (30U)
1083#define COMP_CSR_COMP2VALUE_Msk (0x1U << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
1084#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
1085#define COMP_CSR_COMP2LOCK_Pos (31U)
1086#define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
1087#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
1088
1089/********************** Bit definition for COMP_CSR register common ****************/
1090#define COMP_CSR_COMPxEN_Pos (0U)
1091#define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
1092#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
1093#define COMP_CSR_COMPxPOLARITY_Pos (15U)
1094#define COMP_CSR_COMPxPOLARITY_Msk (0x1U << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
1095#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
1096#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
1097#define COMP_CSR_COMPxOUTVALUE_Msk (0x1U << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
1098#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
1099#define COMP_CSR_COMPxLOCK_Pos (31U)
1100#define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
1101#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
1102
1103/* Reference defines */
1104#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
1105
1106/******************************************************************************/
1107/* */
1108/* CRC calculation unit (CRC) */
1109/* */
1110/******************************************************************************/
1111/******************* Bit definition for CRC_DR register *********************/
1112#define CRC_DR_DR_Pos (0U)
1113#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
1114#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
1115
1116/******************* Bit definition for CRC_IDR register ********************/
1117#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
1118
1119/******************** Bit definition for CRC_CR register ********************/
1120#define CRC_CR_RESET_Pos (0U)
1121#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
1122#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
1123#define CRC_CR_POLYSIZE_Pos (3U)
1124#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
1125#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
1126#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
1127#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
1128#define CRC_CR_REV_IN_Pos (5U)
1129#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
1130#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
1131#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
1132#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
1133#define CRC_CR_REV_OUT_Pos (7U)
1134#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
1135#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
1136
1137/******************* Bit definition for CRC_INIT register *******************/
1138#define CRC_INIT_INIT_Pos (0U)
1139#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
1140#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
1141
1142/******************* Bit definition for CRC_POL register ********************/
1143#define CRC_POL_POL_Pos (0U)
1144#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
1145#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
1146
1147/******************************************************************************/
1148/* */
1149/* Debug MCU (DBGMCU) */
1150/* */
1151/******************************************************************************/
1152
1153/**************** Bit definition for DBGMCU_IDCODE register *****************/
1154#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
1155#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
1156#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
1157
1158#define DBGMCU_IDCODE_REV_ID_Pos (16U)
1159#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
1160#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
1161#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
1162#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
1163#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
1164#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
1165#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
1166#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
1167#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
1168#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
1169#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
1170#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
1171#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
1172#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
1173#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
1174#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
1175#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
1176#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
1177
1178/****************** Bit definition for DBGMCU_CR register *******************/
1179#define DBGMCU_CR_DBG_Pos (0U)
1180#define DBGMCU_CR_DBG_Msk (0x7U << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
1181#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
1182#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
1183#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
1184#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
1185#define DBGMCU_CR_DBG_STOP_Pos (1U)
1186#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
1187#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
1188#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
1189#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
1190#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
1191
1192/****************** Bit definition for DBGMCU_APB1_FZ register **************/
1193#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
1194#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
1195#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
1196#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
1197#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
1198#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
1199#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
1200#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
1201#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
1202#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
1203#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
1204#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
1205#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
1206#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
1207#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
1208#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
1209#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
1210#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
1211/****************** Bit definition for DBGMCU_APB2_FZ register **************/
1212#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
1213#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
1214#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
1215#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
1216#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
1217#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
1218
1219/******************************************************************************/
1220/* */
1221/* DMA Controller (DMA) */
1222/* */
1223/******************************************************************************/
1224
1225/******************* Bit definition for DMA_ISR register ********************/
1226#define DMA_ISR_GIF1_Pos (0U)
1227#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
1228#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
1229#define DMA_ISR_TCIF1_Pos (1U)
1230#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
1231#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
1232#define DMA_ISR_HTIF1_Pos (2U)
1233#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
1234#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
1235#define DMA_ISR_TEIF1_Pos (3U)
1236#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
1237#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
1238#define DMA_ISR_GIF2_Pos (4U)
1239#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
1240#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
1241#define DMA_ISR_TCIF2_Pos (5U)
1242#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
1243#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
1244#define DMA_ISR_HTIF2_Pos (6U)
1245#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
1246#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
1247#define DMA_ISR_TEIF2_Pos (7U)
1248#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
1249#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
1250#define DMA_ISR_GIF3_Pos (8U)
1251#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
1252#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
1253#define DMA_ISR_TCIF3_Pos (9U)
1254#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
1255#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
1256#define DMA_ISR_HTIF3_Pos (10U)
1257#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
1258#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
1259#define DMA_ISR_TEIF3_Pos (11U)
1260#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
1261#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
1262#define DMA_ISR_GIF4_Pos (12U)
1263#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
1264#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
1265#define DMA_ISR_TCIF4_Pos (13U)
1266#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
1267#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
1268#define DMA_ISR_HTIF4_Pos (14U)
1269#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
1270#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
1271#define DMA_ISR_TEIF4_Pos (15U)
1272#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
1273#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
1274#define DMA_ISR_GIF5_Pos (16U)
1275#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
1276#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
1277#define DMA_ISR_TCIF5_Pos (17U)
1278#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
1279#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
1280#define DMA_ISR_HTIF5_Pos (18U)
1281#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
1282#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
1283#define DMA_ISR_TEIF5_Pos (19U)
1284#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
1285#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
1286#define DMA_ISR_GIF6_Pos (20U)
1287#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
1288#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
1289#define DMA_ISR_TCIF6_Pos (21U)
1290#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
1291#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
1292#define DMA_ISR_HTIF6_Pos (22U)
1293#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
1294#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
1295#define DMA_ISR_TEIF6_Pos (23U)
1296#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
1297#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
1298#define DMA_ISR_GIF7_Pos (24U)
1299#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
1300#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
1301#define DMA_ISR_TCIF7_Pos (25U)
1302#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
1303#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
1304#define DMA_ISR_HTIF7_Pos (26U)
1305#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
1306#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
1307#define DMA_ISR_TEIF7_Pos (27U)
1308#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
1309#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
1310
1311/******************* Bit definition for DMA_IFCR register *******************/
1312#define DMA_IFCR_CGIF1_Pos (0U)
1313#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
1314#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
1315#define DMA_IFCR_CTCIF1_Pos (1U)
1316#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1317#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
1318#define DMA_IFCR_CHTIF1_Pos (2U)
1319#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1320#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
1321#define DMA_IFCR_CTEIF1_Pos (3U)
1322#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1323#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
1324#define DMA_IFCR_CGIF2_Pos (4U)
1325#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
1326#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
1327#define DMA_IFCR_CTCIF2_Pos (5U)
1328#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1329#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
1330#define DMA_IFCR_CHTIF2_Pos (6U)
1331#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1332#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
1333#define DMA_IFCR_CTEIF2_Pos (7U)
1334#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
1335#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
1336#define DMA_IFCR_CGIF3_Pos (8U)
1337#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
1338#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
1339#define DMA_IFCR_CTCIF3_Pos (9U)
1340#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
1341#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
1342#define DMA_IFCR_CHTIF3_Pos (10U)
1343#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
1344#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
1345#define DMA_IFCR_CTEIF3_Pos (11U)
1346#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
1347#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
1348#define DMA_IFCR_CGIF4_Pos (12U)
1349#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
1350#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
1351#define DMA_IFCR_CTCIF4_Pos (13U)
1352#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
1353#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
1354#define DMA_IFCR_CHTIF4_Pos (14U)
1355#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
1356#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
1357#define DMA_IFCR_CTEIF4_Pos (15U)
1358#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
1359#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
1360#define DMA_IFCR_CGIF5_Pos (16U)
1361#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
1362#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
1363#define DMA_IFCR_CTCIF5_Pos (17U)
1364#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
1365#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
1366#define DMA_IFCR_CHTIF5_Pos (18U)
1367#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
1368#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
1369#define DMA_IFCR_CTEIF5_Pos (19U)
1370#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
1371#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
1372#define DMA_IFCR_CGIF6_Pos (20U)
1373#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
1374#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
1375#define DMA_IFCR_CTCIF6_Pos (21U)
1376#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
1377#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
1378#define DMA_IFCR_CHTIF6_Pos (22U)
1379#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
1380#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
1381#define DMA_IFCR_CTEIF6_Pos (23U)
1382#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
1383#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
1384#define DMA_IFCR_CGIF7_Pos (24U)
1385#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
1386#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
1387#define DMA_IFCR_CTCIF7_Pos (25U)
1388#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
1389#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
1390#define DMA_IFCR_CHTIF7_Pos (26U)
1391#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
1392#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
1393#define DMA_IFCR_CTEIF7_Pos (27U)
1394#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
1395#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
1396
1397/******************* Bit definition for DMA_CCR register ********************/
1398#define DMA_CCR_EN_Pos (0U)
1399#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
1400#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
1401#define DMA_CCR_TCIE_Pos (1U)
1402#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
1403#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
1404#define DMA_CCR_HTIE_Pos (2U)
1405#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
1406#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
1407#define DMA_CCR_TEIE_Pos (3U)
1408#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
1409#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
1410#define DMA_CCR_DIR_Pos (4U)
1411#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
1412#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
1413#define DMA_CCR_CIRC_Pos (5U)
1414#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
1415#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
1416#define DMA_CCR_PINC_Pos (6U)
1417#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
1418#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
1419#define DMA_CCR_MINC_Pos (7U)
1420#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1421#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
1422
1423#define DMA_CCR_PSIZE_Pos (8U)
1424#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
1425#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
1426#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
1427#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
1428
1429#define DMA_CCR_MSIZE_Pos (10U)
1430#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
1431#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
1432#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
1433#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
1434
1435#define DMA_CCR_PL_Pos (12U)
1436#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
1437#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
1438#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
1439#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
1440
1441#define DMA_CCR_MEM2MEM_Pos (14U)
1442#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
1443#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
1444
1445/****************** Bit definition for DMA_CNDTR register *******************/
1446#define DMA_CNDTR_NDT_Pos (0U)
1447#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
1448#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
1449
1450/****************** Bit definition for DMA_CPAR register ********************/
1451#define DMA_CPAR_PA_Pos (0U)
1452#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
1453#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
1454
1455/****************** Bit definition for DMA_CMAR register ********************/
1456#define DMA_CMAR_MA_Pos (0U)
1457#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
1458#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
1459
1460
1461/******************* Bit definition for DMA_CSELR register *******************/
1462#define DMA_CSELR_C1S_Pos (0U)
1463#define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
1464#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
1465#define DMA_CSELR_C2S_Pos (4U)
1466#define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
1467#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
1468#define DMA_CSELR_C3S_Pos (8U)
1469#define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
1470#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
1471#define DMA_CSELR_C4S_Pos (12U)
1472#define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
1473#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
1474#define DMA_CSELR_C5S_Pos (16U)
1475#define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
1476#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
1477#define DMA_CSELR_C6S_Pos (20U)
1478#define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
1479#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
1480#define DMA_CSELR_C7S_Pos (24U)
1481#define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
1482#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
1483
1484/******************************************************************************/
1485/* */
1486/* External Interrupt/Event Controller (EXTI) */
1487/* */
1488/******************************************************************************/
1489
1490/******************* Bit definition for EXTI_IMR register *******************/
1491#define EXTI_IMR_IM0_Pos (0U)
1492#define EXTI_IMR_IM0_Msk (0x1U << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
1493#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
1494#define EXTI_IMR_IM1_Pos (1U)
1495#define EXTI_IMR_IM1_Msk (0x1U << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
1496#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
1497#define EXTI_IMR_IM2_Pos (2U)
1498#define EXTI_IMR_IM2_Msk (0x1U << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
1499#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
1500#define EXTI_IMR_IM3_Pos (3U)
1501#define EXTI_IMR_IM3_Msk (0x1U << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
1502#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
1503#define EXTI_IMR_IM4_Pos (4U)
1504#define EXTI_IMR_IM4_Msk (0x1U << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
1505#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
1506#define EXTI_IMR_IM5_Pos (5U)
1507#define EXTI_IMR_IM5_Msk (0x1U << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
1508#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
1509#define EXTI_IMR_IM6_Pos (6U)
1510#define EXTI_IMR_IM6_Msk (0x1U << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
1511#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
1512#define EXTI_IMR_IM7_Pos (7U)
1513#define EXTI_IMR_IM7_Msk (0x1U << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
1514#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
1515#define EXTI_IMR_IM8_Pos (8U)
1516#define EXTI_IMR_IM8_Msk (0x1U << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
1517#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
1518#define EXTI_IMR_IM9_Pos (9U)
1519#define EXTI_IMR_IM9_Msk (0x1U << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
1520#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
1521#define EXTI_IMR_IM10_Pos (10U)
1522#define EXTI_IMR_IM10_Msk (0x1U << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
1523#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
1524#define EXTI_IMR_IM11_Pos (11U)
1525#define EXTI_IMR_IM11_Msk (0x1U << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
1526#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
1527#define EXTI_IMR_IM12_Pos (12U)
1528#define EXTI_IMR_IM12_Msk (0x1U << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
1529#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
1530#define EXTI_IMR_IM13_Pos (13U)
1531#define EXTI_IMR_IM13_Msk (0x1U << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
1532#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
1533#define EXTI_IMR_IM14_Pos (14U)
1534#define EXTI_IMR_IM14_Msk (0x1U << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
1535#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
1536#define EXTI_IMR_IM15_Pos (15U)
1537#define EXTI_IMR_IM15_Msk (0x1U << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
1538#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
1539#define EXTI_IMR_IM16_Pos (16U)
1540#define EXTI_IMR_IM16_Msk (0x1U << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
1541#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
1542#define EXTI_IMR_IM17_Pos (17U)
1543#define EXTI_IMR_IM17_Msk (0x1U << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
1544#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
1545#define EXTI_IMR_IM18_Pos (18U)
1546#define EXTI_IMR_IM18_Msk (0x1U << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
1547#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
1548#define EXTI_IMR_IM19_Pos (19U)
1549#define EXTI_IMR_IM19_Msk (0x1U << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
1550#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
1551#define EXTI_IMR_IM20_Pos (20U)
1552#define EXTI_IMR_IM20_Msk (0x1U << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
1553#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
1554#define EXTI_IMR_IM21_Pos (21U)
1555#define EXTI_IMR_IM21_Msk (0x1U << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
1556#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
1557#define EXTI_IMR_IM22_Pos (22U)
1558#define EXTI_IMR_IM22_Msk (0x1U << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
1559#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
1560#define EXTI_IMR_IM23_Pos (23U)
1561#define EXTI_IMR_IM23_Msk (0x1U << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
1562#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
1563#define EXTI_IMR_IM25_Pos (25U)
1564#define EXTI_IMR_IM25_Msk (0x1U << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
1565#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
1566#define EXTI_IMR_IM26_Pos (26U)
1567#define EXTI_IMR_IM26_Msk (0x1U << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
1568#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
1569#define EXTI_IMR_IM28_Pos (28U)
1570#define EXTI_IMR_IM28_Msk (0x1U << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
1571#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
1572#define EXTI_IMR_IM29_Pos (29U)
1573#define EXTI_IMR_IM29_Msk (0x1U << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
1574#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
1575
1576#define EXTI_IMR_IM_Pos (0U)
1577#define EXTI_IMR_IM_Msk (0x36FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
1578#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
1579
1580/****************** Bit definition for EXTI_EMR register ********************/
1581#define EXTI_EMR_EM0_Pos (0U)
1582#define EXTI_EMR_EM0_Msk (0x1U << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
1583#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
1584#define EXTI_EMR_EM1_Pos (1U)
1585#define EXTI_EMR_EM1_Msk (0x1U << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
1586#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
1587#define EXTI_EMR_EM2_Pos (2U)
1588#define EXTI_EMR_EM2_Msk (0x1U << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
1589#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
1590#define EXTI_EMR_EM3_Pos (3U)
1591#define EXTI_EMR_EM3_Msk (0x1U << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
1592#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
1593#define EXTI_EMR_EM4_Pos (4U)
1594#define EXTI_EMR_EM4_Msk (0x1U << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
1595#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
1596#define EXTI_EMR_EM5_Pos (5U)
1597#define EXTI_EMR_EM5_Msk (0x1U << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
1598#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
1599#define EXTI_EMR_EM6_Pos (6U)
1600#define EXTI_EMR_EM6_Msk (0x1U << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
1601#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
1602#define EXTI_EMR_EM7_Pos (7U)
1603#define EXTI_EMR_EM7_Msk (0x1U << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
1604#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
1605#define EXTI_EMR_EM8_Pos (8U)
1606#define EXTI_EMR_EM8_Msk (0x1U << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
1607#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
1608#define EXTI_EMR_EM9_Pos (9U)
1609#define EXTI_EMR_EM9_Msk (0x1U << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
1610#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
1611#define EXTI_EMR_EM10_Pos (10U)
1612#define EXTI_EMR_EM10_Msk (0x1U << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
1613#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
1614#define EXTI_EMR_EM11_Pos (11U)
1615#define EXTI_EMR_EM11_Msk (0x1U << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
1616#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
1617#define EXTI_EMR_EM12_Pos (12U)
1618#define EXTI_EMR_EM12_Msk (0x1U << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
1619#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
1620#define EXTI_EMR_EM13_Pos (13U)
1621#define EXTI_EMR_EM13_Msk (0x1U << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
1622#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
1623#define EXTI_EMR_EM14_Pos (14U)
1624#define EXTI_EMR_EM14_Msk (0x1U << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
1625#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
1626#define EXTI_EMR_EM15_Pos (15U)
1627#define EXTI_EMR_EM15_Msk (0x1U << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
1628#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
1629#define EXTI_EMR_EM16_Pos (16U)
1630#define EXTI_EMR_EM16_Msk (0x1U << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
1631#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
1632#define EXTI_EMR_EM17_Pos (17U)
1633#define EXTI_EMR_EM17_Msk (0x1U << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
1634#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
1635#define EXTI_EMR_EM18_Pos (18U)
1636#define EXTI_EMR_EM18_Msk (0x1U << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
1637#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
1638#define EXTI_EMR_EM19_Pos (19U)
1639#define EXTI_EMR_EM19_Msk (0x1U << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
1640#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
1641#define EXTI_EMR_EM20_Pos (20U)
1642#define EXTI_EMR_EM20_Msk (0x1U << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
1643#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
1644#define EXTI_EMR_EM21_Pos (21U)
1645#define EXTI_EMR_EM21_Msk (0x1U << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
1646#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
1647#define EXTI_EMR_EM22_Pos (22U)
1648#define EXTI_EMR_EM22_Msk (0x1U << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
1649#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
1650#define EXTI_EMR_EM23_Pos (23U)
1651#define EXTI_EMR_EM23_Msk (0x1U << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
1652#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
1653#define EXTI_EMR_EM25_Pos (25U)
1654#define EXTI_EMR_EM25_Msk (0x1U << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
1655#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
1656#define EXTI_EMR_EM26_Pos (26U)
1657#define EXTI_EMR_EM26_Msk (0x1U << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
1658#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
1659#define EXTI_EMR_EM28_Pos (28U)
1660#define EXTI_EMR_EM28_Msk (0x1U << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
1661#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
1662#define EXTI_EMR_EM29_Pos (29U)
1663#define EXTI_EMR_EM29_Msk (0x1U << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
1664#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
1665
1666/******************* Bit definition for EXTI_RTSR register ******************/
1667#define EXTI_RTSR_RT0_Pos (0U)
1668#define EXTI_RTSR_RT0_Msk (0x1U << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
1669#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
1670#define EXTI_RTSR_RT1_Pos (1U)
1671#define EXTI_RTSR_RT1_Msk (0x1U << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
1672#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
1673#define EXTI_RTSR_RT2_Pos (2U)
1674#define EXTI_RTSR_RT2_Msk (0x1U << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
1675#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
1676#define EXTI_RTSR_RT3_Pos (3U)
1677#define EXTI_RTSR_RT3_Msk (0x1U << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
1678#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
1679#define EXTI_RTSR_RT4_Pos (4U)
1680#define EXTI_RTSR_RT4_Msk (0x1U << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
1681#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
1682#define EXTI_RTSR_RT5_Pos (5U)
1683#define EXTI_RTSR_RT5_Msk (0x1U << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
1684#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
1685#define EXTI_RTSR_RT6_Pos (6U)
1686#define EXTI_RTSR_RT6_Msk (0x1U << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
1687#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
1688#define EXTI_RTSR_RT7_Pos (7U)
1689#define EXTI_RTSR_RT7_Msk (0x1U << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
1690#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
1691#define EXTI_RTSR_RT8_Pos (8U)
1692#define EXTI_RTSR_RT8_Msk (0x1U << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
1693#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
1694#define EXTI_RTSR_RT9_Pos (9U)
1695#define EXTI_RTSR_RT9_Msk (0x1U << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
1696#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
1697#define EXTI_RTSR_RT10_Pos (10U)
1698#define EXTI_RTSR_RT10_Msk (0x1U << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
1699#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
1700#define EXTI_RTSR_RT11_Pos (11U)
1701#define EXTI_RTSR_RT11_Msk (0x1U << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
1702#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
1703#define EXTI_RTSR_RT12_Pos (12U)
1704#define EXTI_RTSR_RT12_Msk (0x1U << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
1705#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
1706#define EXTI_RTSR_RT13_Pos (13U)
1707#define EXTI_RTSR_RT13_Msk (0x1U << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
1708#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
1709#define EXTI_RTSR_RT14_Pos (14U)
1710#define EXTI_RTSR_RT14_Msk (0x1U << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
1711#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
1712#define EXTI_RTSR_RT15_Pos (15U)
1713#define EXTI_RTSR_RT15_Msk (0x1U << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
1714#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
1715#define EXTI_RTSR_RT16_Pos (16U)
1716#define EXTI_RTSR_RT16_Msk (0x1U << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
1717#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
1718#define EXTI_RTSR_RT17_Pos (17U)
1719#define EXTI_RTSR_RT17_Msk (0x1U << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
1720#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
1721#define EXTI_RTSR_RT19_Pos (19U)
1722#define EXTI_RTSR_RT19_Msk (0x1U << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
1723#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
1724#define EXTI_RTSR_RT20_Pos (20U)
1725#define EXTI_RTSR_RT20_Msk (0x1U << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
1726#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
1727#define EXTI_RTSR_RT21_Pos (21U)
1728#define EXTI_RTSR_RT21_Msk (0x1U << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
1729#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
1730#define EXTI_RTSR_RT22_Pos (22U)
1731#define EXTI_RTSR_RT22_Msk (0x1U << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
1732#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
1733
1734/* Legacy defines */
1735#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
1736#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
1737#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
1738#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
1739#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
1740#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
1741#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
1742#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
1743#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
1744#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
1745#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
1746#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
1747#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
1748#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
1749#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
1750#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
1751#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
1752#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
1753#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
1754#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
1755#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
1756#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
1757
1758/******************* Bit definition for EXTI_FTSR register *******************/
1759#define EXTI_FTSR_FT0_Pos (0U)
1760#define EXTI_FTSR_FT0_Msk (0x1U << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
1761#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
1762#define EXTI_FTSR_FT1_Pos (1U)
1763#define EXTI_FTSR_FT1_Msk (0x1U << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
1764#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
1765#define EXTI_FTSR_FT2_Pos (2U)
1766#define EXTI_FTSR_FT2_Msk (0x1U << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
1767#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
1768#define EXTI_FTSR_FT3_Pos (3U)
1769#define EXTI_FTSR_FT3_Msk (0x1U << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
1770#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
1771#define EXTI_FTSR_FT4_Pos (4U)
1772#define EXTI_FTSR_FT4_Msk (0x1U << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
1773#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
1774#define EXTI_FTSR_FT5_Pos (5U)
1775#define EXTI_FTSR_FT5_Msk (0x1U << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
1776#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
1777#define EXTI_FTSR_FT6_Pos (6U)
1778#define EXTI_FTSR_FT6_Msk (0x1U << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
1779#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
1780#define EXTI_FTSR_FT7_Pos (7U)
1781#define EXTI_FTSR_FT7_Msk (0x1U << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
1782#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
1783#define EXTI_FTSR_FT8_Pos (8U)
1784#define EXTI_FTSR_FT8_Msk (0x1U << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
1785#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
1786#define EXTI_FTSR_FT9_Pos (9U)
1787#define EXTI_FTSR_FT9_Msk (0x1U << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
1788#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
1789#define EXTI_FTSR_FT10_Pos (10U)
1790#define EXTI_FTSR_FT10_Msk (0x1U << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
1791#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
1792#define EXTI_FTSR_FT11_Pos (11U)
1793#define EXTI_FTSR_FT11_Msk (0x1U << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
1794#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
1795#define EXTI_FTSR_FT12_Pos (12U)
1796#define EXTI_FTSR_FT12_Msk (0x1U << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
1797#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
1798#define EXTI_FTSR_FT13_Pos (13U)
1799#define EXTI_FTSR_FT13_Msk (0x1U << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
1800#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
1801#define EXTI_FTSR_FT14_Pos (14U)
1802#define EXTI_FTSR_FT14_Msk (0x1U << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
1803#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
1804#define EXTI_FTSR_FT15_Pos (15U)
1805#define EXTI_FTSR_FT15_Msk (0x1U << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
1806#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
1807#define EXTI_FTSR_FT16_Pos (16U)
1808#define EXTI_FTSR_FT16_Msk (0x1U << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
1809#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
1810#define EXTI_FTSR_FT17_Pos (17U)
1811#define EXTI_FTSR_FT17_Msk (0x1U << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
1812#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
1813#define EXTI_FTSR_FT19_Pos (19U)
1814#define EXTI_FTSR_FT19_Msk (0x1U << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
1815#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
1816#define EXTI_FTSR_FT20_Pos (20U)
1817#define EXTI_FTSR_FT20_Msk (0x1U << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
1818#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
1819#define EXTI_FTSR_FT21_Pos (21U)
1820#define EXTI_FTSR_FT21_Msk (0x1U << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
1821#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
1822#define EXTI_FTSR_FT22_Pos (22U)
1823#define EXTI_FTSR_FT22_Msk (0x1U << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
1824#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
1825
1826/* Legacy defines */
1827#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
1828#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
1829#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
1830#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
1831#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
1832#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
1833#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
1834#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
1835#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
1836#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
1837#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
1838#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
1839#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
1840#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
1841#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
1842#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
1843#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
1844#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
1845#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
1846#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
1847#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
1848#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
1849
1850/******************* Bit definition for EXTI_SWIER register *******************/
1851#define EXTI_SWIER_SWI0_Pos (0U)
1852#define EXTI_SWIER_SWI0_Msk (0x1U << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
1853#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
1854#define EXTI_SWIER_SWI1_Pos (1U)
1855#define EXTI_SWIER_SWI1_Msk (0x1U << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
1856#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
1857#define EXTI_SWIER_SWI2_Pos (2U)
1858#define EXTI_SWIER_SWI2_Msk (0x1U << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
1859#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
1860#define EXTI_SWIER_SWI3_Pos (3U)
1861#define EXTI_SWIER_SWI3_Msk (0x1U << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
1862#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
1863#define EXTI_SWIER_SWI4_Pos (4U)
1864#define EXTI_SWIER_SWI4_Msk (0x1U << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
1865#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
1866#define EXTI_SWIER_SWI5_Pos (5U)
1867#define EXTI_SWIER_SWI5_Msk (0x1U << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
1868#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
1869#define EXTI_SWIER_SWI6_Pos (6U)
1870#define EXTI_SWIER_SWI6_Msk (0x1U << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
1871#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
1872#define EXTI_SWIER_SWI7_Pos (7U)
1873#define EXTI_SWIER_SWI7_Msk (0x1U << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
1874#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
1875#define EXTI_SWIER_SWI8_Pos (8U)
1876#define EXTI_SWIER_SWI8_Msk (0x1U << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
1877#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
1878#define EXTI_SWIER_SWI9_Pos (9U)
1879#define EXTI_SWIER_SWI9_Msk (0x1U << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
1880#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
1881#define EXTI_SWIER_SWI10_Pos (10U)
1882#define EXTI_SWIER_SWI10_Msk (0x1U << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
1883#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
1884#define EXTI_SWIER_SWI11_Pos (11U)
1885#define EXTI_SWIER_SWI11_Msk (0x1U << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
1886#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
1887#define EXTI_SWIER_SWI12_Pos (12U)
1888#define EXTI_SWIER_SWI12_Msk (0x1U << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
1889#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
1890#define EXTI_SWIER_SWI13_Pos (13U)
1891#define EXTI_SWIER_SWI13_Msk (0x1U << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
1892#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
1893#define EXTI_SWIER_SWI14_Pos (14U)
1894#define EXTI_SWIER_SWI14_Msk (0x1U << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
1895#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
1896#define EXTI_SWIER_SWI15_Pos (15U)
1897#define EXTI_SWIER_SWI15_Msk (0x1U << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
1898#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
1899#define EXTI_SWIER_SWI16_Pos (16U)
1900#define EXTI_SWIER_SWI16_Msk (0x1U << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
1901#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
1902#define EXTI_SWIER_SWI17_Pos (17U)
1903#define EXTI_SWIER_SWI17_Msk (0x1U << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
1904#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
1905#define EXTI_SWIER_SWI19_Pos (19U)
1906#define EXTI_SWIER_SWI19_Msk (0x1U << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
1907#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
1908#define EXTI_SWIER_SWI20_Pos (20U)
1909#define EXTI_SWIER_SWI20_Msk (0x1U << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
1910#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
1911#define EXTI_SWIER_SWI21_Pos (21U)
1912#define EXTI_SWIER_SWI21_Msk (0x1U << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
1913#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
1914#define EXTI_SWIER_SWI22_Pos (22U)
1915#define EXTI_SWIER_SWI22_Msk (0x1U << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
1916#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
1917
1918/* Legacy defines */
1919#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
1920#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
1921#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
1922#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
1923#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
1924#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
1925#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
1926#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
1927#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
1928#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
1929#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
1930#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
1931#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
1932#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
1933#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
1934#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
1935#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
1936#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
1937#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
1938#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
1939#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
1940#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
1941
1942/****************** Bit definition for EXTI_PR register *********************/
1943#define EXTI_PR_PIF0_Pos (0U)
1944#define EXTI_PR_PIF0_Msk (0x1U << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
1945#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
1946#define EXTI_PR_PIF1_Pos (1U)
1947#define EXTI_PR_PIF1_Msk (0x1U << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
1948#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
1949#define EXTI_PR_PIF2_Pos (2U)
1950#define EXTI_PR_PIF2_Msk (0x1U << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
1951#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
1952#define EXTI_PR_PIF3_Pos (3U)
1953#define EXTI_PR_PIF3_Msk (0x1U << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
1954#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
1955#define EXTI_PR_PIF4_Pos (4U)
1956#define EXTI_PR_PIF4_Msk (0x1U << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
1957#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
1958#define EXTI_PR_PIF5_Pos (5U)
1959#define EXTI_PR_PIF5_Msk (0x1U << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
1960#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
1961#define EXTI_PR_PIF6_Pos (6U)
1962#define EXTI_PR_PIF6_Msk (0x1U << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
1963#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
1964#define EXTI_PR_PIF7_Pos (7U)
1965#define EXTI_PR_PIF7_Msk (0x1U << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
1966#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
1967#define EXTI_PR_PIF8_Pos (8U)
1968#define EXTI_PR_PIF8_Msk (0x1U << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
1969#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
1970#define EXTI_PR_PIF9_Pos (9U)
1971#define EXTI_PR_PIF9_Msk (0x1U << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
1972#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
1973#define EXTI_PR_PIF10_Pos (10U)
1974#define EXTI_PR_PIF10_Msk (0x1U << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
1975#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
1976#define EXTI_PR_PIF11_Pos (11U)
1977#define EXTI_PR_PIF11_Msk (0x1U << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
1978#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
1979#define EXTI_PR_PIF12_Pos (12U)
1980#define EXTI_PR_PIF12_Msk (0x1U << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
1981#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
1982#define EXTI_PR_PIF13_Pos (13U)
1983#define EXTI_PR_PIF13_Msk (0x1U << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
1984#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
1985#define EXTI_PR_PIF14_Pos (14U)
1986#define EXTI_PR_PIF14_Msk (0x1U << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
1987#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
1988#define EXTI_PR_PIF15_Pos (15U)
1989#define EXTI_PR_PIF15_Msk (0x1U << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
1990#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
1991#define EXTI_PR_PIF16_Pos (16U)
1992#define EXTI_PR_PIF16_Msk (0x1U << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
1993#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
1994#define EXTI_PR_PIF17_Pos (17U)
1995#define EXTI_PR_PIF17_Msk (0x1U << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
1996#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
1997#define EXTI_PR_PIF19_Pos (19U)
1998#define EXTI_PR_PIF19_Msk (0x1U << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
1999#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
2000#define EXTI_PR_PIF20_Pos (20U)
2001#define EXTI_PR_PIF20_Msk (0x1U << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
2002#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
2003#define EXTI_PR_PIF21_Pos (21U)
2004#define EXTI_PR_PIF21_Msk (0x1U << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
2005#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
2006#define EXTI_PR_PIF22_Pos (22U)
2007#define EXTI_PR_PIF22_Msk (0x1U << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
2008#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
2009
2010/* Legacy defines */
2011#define EXTI_PR_PR0 EXTI_PR_PIF0
2012#define EXTI_PR_PR1 EXTI_PR_PIF1
2013#define EXTI_PR_PR2 EXTI_PR_PIF2
2014#define EXTI_PR_PR3 EXTI_PR_PIF3
2015#define EXTI_PR_PR4 EXTI_PR_PIF4
2016#define EXTI_PR_PR5 EXTI_PR_PIF5
2017#define EXTI_PR_PR6 EXTI_PR_PIF6
2018#define EXTI_PR_PR7 EXTI_PR_PIF7
2019#define EXTI_PR_PR8 EXTI_PR_PIF8
2020#define EXTI_PR_PR9 EXTI_PR_PIF9
2021#define EXTI_PR_PR10 EXTI_PR_PIF10
2022#define EXTI_PR_PR11 EXTI_PR_PIF11
2023#define EXTI_PR_PR12 EXTI_PR_PIF12
2024#define EXTI_PR_PR13 EXTI_PR_PIF13
2025#define EXTI_PR_PR14 EXTI_PR_PIF14
2026#define EXTI_PR_PR15 EXTI_PR_PIF15
2027#define EXTI_PR_PR16 EXTI_PR_PIF16
2028#define EXTI_PR_PR17 EXTI_PR_PIF17
2029#define EXTI_PR_PR19 EXTI_PR_PIF19
2030#define EXTI_PR_PR20 EXTI_PR_PIF20
2031#define EXTI_PR_PR21 EXTI_PR_PIF21
2032#define EXTI_PR_PR22 EXTI_PR_PIF22
2033
2034/******************************************************************************/
2035/* */
2036/* FLASH and Option Bytes Registers */
2037/* */
2038/******************************************************************************/
2039
2040/******************* Bit definition for FLASH_ACR register ******************/
2041#define FLASH_ACR_LATENCY_Pos (0U)
2042#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
2043#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
2044#define FLASH_ACR_PRFTEN_Pos (1U)
2045#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
2046#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
2047#define FLASH_ACR_SLEEP_PD_Pos (3U)
2048#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
2049#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
2050#define FLASH_ACR_RUN_PD_Pos (4U)
2051#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
2052#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
2053#define FLASH_ACR_DISAB_BUF_Pos (5U)
2054#define FLASH_ACR_DISAB_BUF_Msk (0x1U << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
2055#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
2056#define FLASH_ACR_PRE_READ_Pos (6U)
2057#define FLASH_ACR_PRE_READ_Msk (0x1U << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
2058#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
2059
2060/******************* Bit definition for FLASH_PECR register ******************/
2061#define FLASH_PECR_PELOCK_Pos (0U)
2062#define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
2063#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
2064#define FLASH_PECR_PRGLOCK_Pos (1U)
2065#define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
2066#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
2067#define FLASH_PECR_OPTLOCK_Pos (2U)
2068#define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
2069#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
2070#define FLASH_PECR_PROG_Pos (3U)
2071#define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
2072#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
2073#define FLASH_PECR_DATA_Pos (4U)
2074#define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
2075#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
2076#define FLASH_PECR_FIX_Pos (8U)
2077#define FLASH_PECR_FIX_Msk (0x1U << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
2078#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
2079#define FLASH_PECR_ERASE_Pos (9U)
2080#define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
2081#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
2082#define FLASH_PECR_FPRG_Pos (10U)
2083#define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
2084#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
2085#define FLASH_PECR_EOPIE_Pos (16U)
2086#define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
2087#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
2088#define FLASH_PECR_ERRIE_Pos (17U)
2089#define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
2090#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
2091#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
2092#define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
2093#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
2094#define FLASH_PECR_HALF_ARRAY_Pos (19U)
2095#define FLASH_PECR_HALF_ARRAY_Msk (0x1U << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
2096#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
2097
2098/****************** Bit definition for FLASH_PDKEYR register ******************/
2099#define FLASH_PDKEYR_PDKEYR_Pos (0U)
2100#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
2101#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
2102
2103/****************** Bit definition for FLASH_PEKEYR register ******************/
2104#define FLASH_PEKEYR_PEKEYR_Pos (0U)
2105#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
2106#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
2107
2108/****************** Bit definition for FLASH_PRGKEYR register ******************/
2109#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
2110#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
2111#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
2112
2113/****************** Bit definition for FLASH_OPTKEYR register ******************/
2114#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
2115#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
2116#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
2117
2118/****************** Bit definition for FLASH_SR register *******************/
2119#define FLASH_SR_BSY_Pos (0U)
2120#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
2121#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
2122#define FLASH_SR_EOP_Pos (1U)
2123#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
2124#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
2125#define FLASH_SR_HVOFF_Pos (2U)
2126#define FLASH_SR_HVOFF_Msk (0x1U << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
2127#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
2128#define FLASH_SR_READY_Pos (3U)
2129#define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */
2130#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
2131
2132#define FLASH_SR_WRPERR_Pos (8U)
2133#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
2134#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
2135#define FLASH_SR_PGAERR_Pos (9U)
2136#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
2137#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
2138#define FLASH_SR_SIZERR_Pos (10U)
2139#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
2140#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
2141#define FLASH_SR_OPTVERR_Pos (11U)
2142#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
2143#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
2144#define FLASH_SR_RDERR_Pos (13U)
2145#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
2146#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
2147#define FLASH_SR_NOTZEROERR_Pos (16U)
2148#define FLASH_SR_NOTZEROERR_Msk (0x1U << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
2149#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
2150#define FLASH_SR_FWWERR_Pos (17U)
2151#define FLASH_SR_FWWERR_Msk (0x1U << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
2152#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
2153
2154/* Legacy defines */
2155#define FLASH_SR_FWWER FLASH_SR_FWWERR
2156#define FLASH_SR_ENHV FLASH_SR_HVOFF
2157#define FLASH_SR_ENDHV FLASH_SR_HVOFF
2158
2159/****************** Bit definition for FLASH_OPTR register *******************/
2160#define FLASH_OPTR_RDPROT_Pos (0U)
2161#define FLASH_OPTR_RDPROT_Msk (0xFFU << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
2162#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
2163#define FLASH_OPTR_WPRMOD_Pos (8U)
2164#define FLASH_OPTR_WPRMOD_Msk (0x1U << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
2165#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
2166#define FLASH_OPTR_BOR_LEV_Pos (16U)
2167#define FLASH_OPTR_BOR_LEV_Msk (0xFU << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
2168#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
2169#define FLASH_OPTR_IWDG_SW_Pos (20U)
2170#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
2171#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
2172#define FLASH_OPTR_nRST_STOP_Pos (21U)
2173#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
2174#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
2175#define FLASH_OPTR_nRST_STDBY_Pos (22U)
2176#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
2177#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
2178#define FLASH_OPTR_USER_Pos (20U)
2179#define FLASH_OPTR_USER_Msk (0x7U << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
2180#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
2181#define FLASH_OPTR_BOOT1_Pos (31U)
2182#define FLASH_OPTR_BOOT1_Msk (0x1U << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
2183#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
2184
2185/****************** Bit definition for FLASH_WRPR register ******************/
2186#define FLASH_WRPR_WRP_Pos (0U)
2187#define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
2188#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
2189
2190/******************************************************************************/
2191/* */
2192/* General Purpose IOs (GPIO) */
2193/* */
2194/******************************************************************************/
2195/******************* Bit definition for GPIO_MODER register *****************/
2196#define GPIO_MODER_MODE0_Pos (0U)
2197#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
2198#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
2199#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
2200#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
2201#define GPIO_MODER_MODE1_Pos (2U)
2202#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
2203#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
2204#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
2205#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
2206#define GPIO_MODER_MODE2_Pos (4U)
2207#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
2208#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
2209#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
2210#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
2211#define GPIO_MODER_MODE3_Pos (6U)
2212#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
2213#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
2214#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
2215#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
2216#define GPIO_MODER_MODE4_Pos (8U)
2217#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
2218#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
2219#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
2220#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
2221#define GPIO_MODER_MODE5_Pos (10U)
2222#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
2223#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
2224#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
2225#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
2226#define GPIO_MODER_MODE6_Pos (12U)
2227#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
2228#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
2229#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
2230#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
2231#define GPIO_MODER_MODE7_Pos (14U)
2232#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
2233#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
2234#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
2235#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
2236#define GPIO_MODER_MODE8_Pos (16U)
2237#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
2238#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
2239#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
2240#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
2241#define GPIO_MODER_MODE9_Pos (18U)
2242#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
2243#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
2244#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
2245#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
2246#define GPIO_MODER_MODE10_Pos (20U)
2247#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
2248#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
2249#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
2250#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
2251#define GPIO_MODER_MODE11_Pos (22U)
2252#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
2253#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
2254#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
2255#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
2256#define GPIO_MODER_MODE12_Pos (24U)
2257#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
2258#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
2259#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
2260#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
2261#define GPIO_MODER_MODE13_Pos (26U)
2262#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
2263#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
2264#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
2265#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
2266#define GPIO_MODER_MODE14_Pos (28U)
2267#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
2268#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
2269#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
2270#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
2271#define GPIO_MODER_MODE15_Pos (30U)
2272#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
2273#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
2274#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
2275#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
2276
2277/****************** Bit definition for GPIO_OTYPER register *****************/
2278#define GPIO_OTYPER_OT_0 (0x00000001U)
2279#define GPIO_OTYPER_OT_1 (0x00000002U)
2280#define GPIO_OTYPER_OT_2 (0x00000004U)
2281#define GPIO_OTYPER_OT_3 (0x00000008U)
2282#define GPIO_OTYPER_OT_4 (0x00000010U)
2283#define GPIO_OTYPER_OT_5 (0x00000020U)
2284#define GPIO_OTYPER_OT_6 (0x00000040U)
2285#define GPIO_OTYPER_OT_7 (0x00000080U)
2286#define GPIO_OTYPER_OT_8 (0x00000100U)
2287#define GPIO_OTYPER_OT_9 (0x00000200U)
2288#define GPIO_OTYPER_OT_10 (0x00000400U)
2289#define GPIO_OTYPER_OT_11 (0x00000800U)
2290#define GPIO_OTYPER_OT_12 (0x00001000U)
2291#define GPIO_OTYPER_OT_13 (0x00002000U)
2292#define GPIO_OTYPER_OT_14 (0x00004000U)
2293#define GPIO_OTYPER_OT_15 (0x00008000U)
2294
2295/**************** Bit definition for GPIO_OSPEEDR register ******************/
2296#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
2297#define GPIO_OSPEEDER_OSPEED0_Msk (0x3U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
2298#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
2299#define GPIO_OSPEEDER_OSPEED0_0 (0x1U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
2300#define GPIO_OSPEEDER_OSPEED0_1 (0x2U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
2301#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
2302#define GPIO_OSPEEDER_OSPEED1_Msk (0x3U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
2303#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
2304#define GPIO_OSPEEDER_OSPEED1_0 (0x1U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
2305#define GPIO_OSPEEDER_OSPEED1_1 (0x2U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
2306#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
2307#define GPIO_OSPEEDER_OSPEED2_Msk (0x3U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
2308#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
2309#define GPIO_OSPEEDER_OSPEED2_0 (0x1U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
2310#define GPIO_OSPEEDER_OSPEED2_1 (0x2U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
2311#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
2312#define GPIO_OSPEEDER_OSPEED3_Msk (0x3U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
2313#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
2314#define GPIO_OSPEEDER_OSPEED3_0 (0x1U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
2315#define GPIO_OSPEEDER_OSPEED3_1 (0x2U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
2316#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
2317#define GPIO_OSPEEDER_OSPEED4_Msk (0x3U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
2318#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
2319#define GPIO_OSPEEDER_OSPEED4_0 (0x1U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
2320#define GPIO_OSPEEDER_OSPEED4_1 (0x2U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
2321#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
2322#define GPIO_OSPEEDER_OSPEED5_Msk (0x3U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
2323#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
2324#define GPIO_OSPEEDER_OSPEED5_0 (0x1U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
2325#define GPIO_OSPEEDER_OSPEED5_1 (0x2U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
2326#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
2327#define GPIO_OSPEEDER_OSPEED6_Msk (0x3U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
2328#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
2329#define GPIO_OSPEEDER_OSPEED6_0 (0x1U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
2330#define GPIO_OSPEEDER_OSPEED6_1 (0x2U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
2331#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
2332#define GPIO_OSPEEDER_OSPEED7_Msk (0x3U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
2333#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
2334#define GPIO_OSPEEDER_OSPEED7_0 (0x1U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
2335#define GPIO_OSPEEDER_OSPEED7_1 (0x2U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
2336#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
2337#define GPIO_OSPEEDER_OSPEED8_Msk (0x3U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
2338#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
2339#define GPIO_OSPEEDER_OSPEED8_0 (0x1U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
2340#define GPIO_OSPEEDER_OSPEED8_1 (0x2U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
2341#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
2342#define GPIO_OSPEEDER_OSPEED9_Msk (0x3U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
2343#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
2344#define GPIO_OSPEEDER_OSPEED9_0 (0x1U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
2345#define GPIO_OSPEEDER_OSPEED9_1 (0x2U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
2346#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
2347#define GPIO_OSPEEDER_OSPEED10_Msk (0x3U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
2348#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
2349#define GPIO_OSPEEDER_OSPEED10_0 (0x1U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
2350#define GPIO_OSPEEDER_OSPEED10_1 (0x2U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
2351#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
2352#define GPIO_OSPEEDER_OSPEED11_Msk (0x3U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
2353#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
2354#define GPIO_OSPEEDER_OSPEED11_0 (0x1U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
2355#define GPIO_OSPEEDER_OSPEED11_1 (0x2U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
2356#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
2357#define GPIO_OSPEEDER_OSPEED12_Msk (0x3U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
2358#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
2359#define GPIO_OSPEEDER_OSPEED12_0 (0x1U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
2360#define GPIO_OSPEEDER_OSPEED12_1 (0x2U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
2361#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
2362#define GPIO_OSPEEDER_OSPEED13_Msk (0x3U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
2363#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
2364#define GPIO_OSPEEDER_OSPEED13_0 (0x1U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
2365#define GPIO_OSPEEDER_OSPEED13_1 (0x2U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
2366#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
2367#define GPIO_OSPEEDER_OSPEED14_Msk (0x3U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
2368#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
2369#define GPIO_OSPEEDER_OSPEED14_0 (0x1U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
2370#define GPIO_OSPEEDER_OSPEED14_1 (0x2U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
2371#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
2372#define GPIO_OSPEEDER_OSPEED15_Msk (0x3U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
2373#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
2374#define GPIO_OSPEEDER_OSPEED15_0 (0x1U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
2375#define GPIO_OSPEEDER_OSPEED15_1 (0x2U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
2376
2377/******************* Bit definition for GPIO_PUPDR register ******************/
2378#define GPIO_PUPDR_PUPD0_Pos (0U)
2379#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
2380#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
2381#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
2382#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
2383#define GPIO_PUPDR_PUPD1_Pos (2U)
2384#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
2385#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
2386#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
2387#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
2388#define GPIO_PUPDR_PUPD2_Pos (4U)
2389#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
2390#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
2391#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
2392#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
2393#define GPIO_PUPDR_PUPD3_Pos (6U)
2394#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
2395#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
2396#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
2397#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
2398#define GPIO_PUPDR_PUPD4_Pos (8U)
2399#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
2400#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
2401#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
2402#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
2403#define GPIO_PUPDR_PUPD5_Pos (10U)
2404#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
2405#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
2406#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
2407#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
2408#define GPIO_PUPDR_PUPD6_Pos (12U)
2409#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
2410#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
2411#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
2412#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
2413#define GPIO_PUPDR_PUPD7_Pos (14U)
2414#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
2415#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
2416#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
2417#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
2418#define GPIO_PUPDR_PUPD8_Pos (16U)
2419#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
2420#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
2421#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
2422#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
2423#define GPIO_PUPDR_PUPD9_Pos (18U)
2424#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
2425#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
2426#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
2427#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
2428#define GPIO_PUPDR_PUPD10_Pos (20U)
2429#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
2430#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
2431#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
2432#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
2433#define GPIO_PUPDR_PUPD11_Pos (22U)
2434#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
2435#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
2436#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
2437#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
2438#define GPIO_PUPDR_PUPD12_Pos (24U)
2439#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
2440#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
2441#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
2442#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
2443#define GPIO_PUPDR_PUPD13_Pos (26U)
2444#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
2445#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
2446#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
2447#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
2448#define GPIO_PUPDR_PUPD14_Pos (28U)
2449#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
2450#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
2451#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
2452#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
2453#define GPIO_PUPDR_PUPD15_Pos (30U)
2454#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
2455#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
2456#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
2457#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
2458
2459/******************* Bit definition for GPIO_IDR register *******************/
2460#define GPIO_IDR_ID0_Pos (0U)
2461#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
2462#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
2463#define GPIO_IDR_ID1_Pos (1U)
2464#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
2465#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
2466#define GPIO_IDR_ID2_Pos (2U)
2467#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
2468#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
2469#define GPIO_IDR_ID3_Pos (3U)
2470#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
2471#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
2472#define GPIO_IDR_ID4_Pos (4U)
2473#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
2474#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
2475#define GPIO_IDR_ID5_Pos (5U)
2476#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
2477#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
2478#define GPIO_IDR_ID6_Pos (6U)
2479#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
2480#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
2481#define GPIO_IDR_ID7_Pos (7U)
2482#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
2483#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
2484#define GPIO_IDR_ID8_Pos (8U)
2485#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
2486#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
2487#define GPIO_IDR_ID9_Pos (9U)
2488#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
2489#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
2490#define GPIO_IDR_ID10_Pos (10U)
2491#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
2492#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
2493#define GPIO_IDR_ID11_Pos (11U)
2494#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
2495#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
2496#define GPIO_IDR_ID12_Pos (12U)
2497#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
2498#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
2499#define GPIO_IDR_ID13_Pos (13U)
2500#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
2501#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
2502#define GPIO_IDR_ID14_Pos (14U)
2503#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
2504#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
2505#define GPIO_IDR_ID15_Pos (15U)
2506#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
2507#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
2508
2509/****************** Bit definition for GPIO_ODR register ********************/
2510#define GPIO_ODR_OD0_Pos (0U)
2511#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
2512#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
2513#define GPIO_ODR_OD1_Pos (1U)
2514#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
2515#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
2516#define GPIO_ODR_OD2_Pos (2U)
2517#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
2518#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
2519#define GPIO_ODR_OD3_Pos (3U)
2520#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
2521#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
2522#define GPIO_ODR_OD4_Pos (4U)
2523#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
2524#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
2525#define GPIO_ODR_OD5_Pos (5U)
2526#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
2527#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
2528#define GPIO_ODR_OD6_Pos (6U)
2529#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
2530#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
2531#define GPIO_ODR_OD7_Pos (7U)
2532#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
2533#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
2534#define GPIO_ODR_OD8_Pos (8U)
2535#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
2536#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
2537#define GPIO_ODR_OD9_Pos (9U)
2538#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
2539#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
2540#define GPIO_ODR_OD10_Pos (10U)
2541#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
2542#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
2543#define GPIO_ODR_OD11_Pos (11U)
2544#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
2545#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
2546#define GPIO_ODR_OD12_Pos (12U)
2547#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
2548#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
2549#define GPIO_ODR_OD13_Pos (13U)
2550#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
2551#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
2552#define GPIO_ODR_OD14_Pos (14U)
2553#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
2554#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
2555#define GPIO_ODR_OD15_Pos (15U)
2556#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
2557#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
2558
2559/****************** Bit definition for GPIO_BSRR register ********************/
2560#define GPIO_BSRR_BS_0 (0x00000001U)
2561#define GPIO_BSRR_BS_1 (0x00000002U)
2562#define GPIO_BSRR_BS_2 (0x00000004U)
2563#define GPIO_BSRR_BS_3 (0x00000008U)
2564#define GPIO_BSRR_BS_4 (0x00000010U)
2565#define GPIO_BSRR_BS_5 (0x00000020U)
2566#define GPIO_BSRR_BS_6 (0x00000040U)
2567#define GPIO_BSRR_BS_7 (0x00000080U)
2568#define GPIO_BSRR_BS_8 (0x00000100U)
2569#define GPIO_BSRR_BS_9 (0x00000200U)
2570#define GPIO_BSRR_BS_10 (0x00000400U)
2571#define GPIO_BSRR_BS_11 (0x00000800U)
2572#define GPIO_BSRR_BS_12 (0x00001000U)
2573#define GPIO_BSRR_BS_13 (0x00002000U)
2574#define GPIO_BSRR_BS_14 (0x00004000U)
2575#define GPIO_BSRR_BS_15 (0x00008000U)
2576#define GPIO_BSRR_BR_0 (0x00010000U)
2577#define GPIO_BSRR_BR_1 (0x00020000U)
2578#define GPIO_BSRR_BR_2 (0x00040000U)
2579#define GPIO_BSRR_BR_3 (0x00080000U)
2580#define GPIO_BSRR_BR_4 (0x00100000U)
2581#define GPIO_BSRR_BR_5 (0x00200000U)
2582#define GPIO_BSRR_BR_6 (0x00400000U)
2583#define GPIO_BSRR_BR_7 (0x00800000U)
2584#define GPIO_BSRR_BR_8 (0x01000000U)
2585#define GPIO_BSRR_BR_9 (0x02000000U)
2586#define GPIO_BSRR_BR_10 (0x04000000U)
2587#define GPIO_BSRR_BR_11 (0x08000000U)
2588#define GPIO_BSRR_BR_12 (0x10000000U)
2589#define GPIO_BSRR_BR_13 (0x20000000U)
2590#define GPIO_BSRR_BR_14 (0x40000000U)
2591#define GPIO_BSRR_BR_15 (0x80000000U)
2592
2593/****************** Bit definition for GPIO_LCKR register ********************/
2594#define GPIO_LCKR_LCK0_Pos (0U)
2595#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
2596#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
2597#define GPIO_LCKR_LCK1_Pos (1U)
2598#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
2599#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
2600#define GPIO_LCKR_LCK2_Pos (2U)
2601#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
2602#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
2603#define GPIO_LCKR_LCK3_Pos (3U)
2604#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
2605#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
2606#define GPIO_LCKR_LCK4_Pos (4U)
2607#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
2608#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
2609#define GPIO_LCKR_LCK5_Pos (5U)
2610#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
2611#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
2612#define GPIO_LCKR_LCK6_Pos (6U)
2613#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
2614#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
2615#define GPIO_LCKR_LCK7_Pos (7U)
2616#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
2617#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
2618#define GPIO_LCKR_LCK8_Pos (8U)
2619#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
2620#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
2621#define GPIO_LCKR_LCK9_Pos (9U)
2622#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
2623#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
2624#define GPIO_LCKR_LCK10_Pos (10U)
2625#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
2626#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
2627#define GPIO_LCKR_LCK11_Pos (11U)
2628#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
2629#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
2630#define GPIO_LCKR_LCK12_Pos (12U)
2631#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
2632#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
2633#define GPIO_LCKR_LCK13_Pos (13U)
2634#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
2635#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
2636#define GPIO_LCKR_LCK14_Pos (14U)
2637#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
2638#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
2639#define GPIO_LCKR_LCK15_Pos (15U)
2640#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
2641#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
2642#define GPIO_LCKR_LCKK_Pos (16U)
2643#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
2644#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
2645
2646/****************** Bit definition for GPIO_AFRL register ********************/
2647#define GPIO_AFRL_AFRL0_Pos (0U)
2648#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
2649#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
2650#define GPIO_AFRL_AFRL1_Pos (4U)
2651#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
2652#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
2653#define GPIO_AFRL_AFRL2_Pos (8U)
2654#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
2655#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
2656#define GPIO_AFRL_AFRL3_Pos (12U)
2657#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
2658#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
2659#define GPIO_AFRL_AFRL4_Pos (16U)
2660#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
2661#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
2662#define GPIO_AFRL_AFRL5_Pos (20U)
2663#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
2664#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
2665#define GPIO_AFRL_AFRL6_Pos (24U)
2666#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
2667#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
2668#define GPIO_AFRL_AFRL7_Pos (28U)
2669#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
2670#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
2671
2672/****************** Bit definition for GPIO_AFRH register ********************/
2673#define GPIO_AFRH_AFRH0_Pos (0U)
2674#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
2675#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
2676#define GPIO_AFRH_AFRH1_Pos (4U)
2677#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
2678#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
2679#define GPIO_AFRH_AFRH2_Pos (8U)
2680#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
2681#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
2682#define GPIO_AFRH_AFRH3_Pos (12U)
2683#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
2684#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
2685#define GPIO_AFRH_AFRH4_Pos (16U)
2686#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
2687#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
2688#define GPIO_AFRH_AFRH5_Pos (20U)
2689#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
2690#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
2691#define GPIO_AFRH_AFRH6_Pos (24U)
2692#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
2693#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
2694#define GPIO_AFRH_AFRH7_Pos (28U)
2695#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
2696#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
2697
2698/****************** Bit definition for GPIO_BRR register *********************/
2699#define GPIO_BRR_BR_0 (0x00000001U)
2700#define GPIO_BRR_BR_1 (0x00000002U)
2701#define GPIO_BRR_BR_2 (0x00000004U)
2702#define GPIO_BRR_BR_3 (0x00000008U)
2703#define GPIO_BRR_BR_4 (0x00000010U)
2704#define GPIO_BRR_BR_5 (0x00000020U)
2705#define GPIO_BRR_BR_6 (0x00000040U)
2706#define GPIO_BRR_BR_7 (0x00000080U)
2707#define GPIO_BRR_BR_8 (0x00000100U)
2708#define GPIO_BRR_BR_9 (0x00000200U)
2709#define GPIO_BRR_BR_10 (0x00000400U)
2710#define GPIO_BRR_BR_11 (0x00000800U)
2711#define GPIO_BRR_BR_12 (0x00001000U)
2712#define GPIO_BRR_BR_13 (0x00002000U)
2713#define GPIO_BRR_BR_14 (0x00004000U)
2714#define GPIO_BRR_BR_15 (0x00008000U)
2715
2716/******************************************************************************/
2717/* */
2718/* Inter-integrated Circuit Interface (I2C) */
2719/* */
2720/******************************************************************************/
2721
2722/******************* Bit definition for I2C_CR1 register *******************/
2723#define I2C_CR1_PE_Pos (0U)
2724#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
2725#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
2726#define I2C_CR1_TXIE_Pos (1U)
2727#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
2728#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
2729#define I2C_CR1_RXIE_Pos (2U)
2730#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
2731#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
2732#define I2C_CR1_ADDRIE_Pos (3U)
2733#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
2734#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
2735#define I2C_CR1_NACKIE_Pos (4U)
2736#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
2737#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
2738#define I2C_CR1_STOPIE_Pos (5U)
2739#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
2740#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
2741#define I2C_CR1_TCIE_Pos (6U)
2742#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
2743#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
2744#define I2C_CR1_ERRIE_Pos (7U)
2745#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
2746#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
2747#define I2C_CR1_DNF_Pos (8U)
2748#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
2749#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
2750#define I2C_CR1_ANFOFF_Pos (12U)
2751#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
2752#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
2753#define I2C_CR1_TXDMAEN_Pos (14U)
2754#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
2755#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
2756#define I2C_CR1_RXDMAEN_Pos (15U)
2757#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
2758#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
2759#define I2C_CR1_SBC_Pos (16U)
2760#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
2761#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
2762#define I2C_CR1_NOSTRETCH_Pos (17U)
2763#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
2764#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
2765#define I2C_CR1_WUPEN_Pos (18U)
2766#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
2767#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
2768#define I2C_CR1_GCEN_Pos (19U)
2769#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
2770#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
2771#define I2C_CR1_SMBHEN_Pos (20U)
2772#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
2773#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
2774#define I2C_CR1_SMBDEN_Pos (21U)
2775#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
2776#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
2777#define I2C_CR1_ALERTEN_Pos (22U)
2778#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
2779#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
2780#define I2C_CR1_PECEN_Pos (23U)
2781#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
2782#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
2783
2784/****************** Bit definition for I2C_CR2 register ********************/
2785#define I2C_CR2_SADD_Pos (0U)
2786#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
2787#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
2788#define I2C_CR2_RD_WRN_Pos (10U)
2789#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
2790#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
2791#define I2C_CR2_ADD10_Pos (11U)
2792#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
2793#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
2794#define I2C_CR2_HEAD10R_Pos (12U)
2795#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
2796#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
2797#define I2C_CR2_START_Pos (13U)
2798#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
2799#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
2800#define I2C_CR2_STOP_Pos (14U)
2801#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
2802#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
2803#define I2C_CR2_NACK_Pos (15U)
2804#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
2805#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
2806#define I2C_CR2_NBYTES_Pos (16U)
2807#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
2808#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
2809#define I2C_CR2_RELOAD_Pos (24U)
2810#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
2811#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
2812#define I2C_CR2_AUTOEND_Pos (25U)
2813#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
2814#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
2815#define I2C_CR2_PECBYTE_Pos (26U)
2816#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
2817#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
2818
2819/******************* Bit definition for I2C_OAR1 register ******************/
2820#define I2C_OAR1_OA1_Pos (0U)
2821#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
2822#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
2823#define I2C_OAR1_OA1MODE_Pos (10U)
2824#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
2825#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
2826#define I2C_OAR1_OA1EN_Pos (15U)
2827#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
2828#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
2829
2830/******************* Bit definition for I2C_OAR2 register ******************/
2831#define I2C_OAR2_OA2_Pos (1U)
2832#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
2833#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
2834#define I2C_OAR2_OA2MSK_Pos (8U)
2835#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
2836#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
2837#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
2838#define I2C_OAR2_OA2MASK01_Pos (8U)
2839#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
2840#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
2841#define I2C_OAR2_OA2MASK02_Pos (9U)
2842#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
2843#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
2844#define I2C_OAR2_OA2MASK03_Pos (8U)
2845#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
2846#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
2847#define I2C_OAR2_OA2MASK04_Pos (10U)
2848#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
2849#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
2850#define I2C_OAR2_OA2MASK05_Pos (8U)
2851#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
2852#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
2853#define I2C_OAR2_OA2MASK06_Pos (9U)
2854#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
2855#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
2856#define I2C_OAR2_OA2MASK07_Pos (8U)
2857#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
2858#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
2859#define I2C_OAR2_OA2EN_Pos (15U)
2860#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
2861#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
2862
2863/******************* Bit definition for I2C_TIMINGR register *******************/
2864#define I2C_TIMINGR_SCLL_Pos (0U)
2865#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
2866#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
2867#define I2C_TIMINGR_SCLH_Pos (8U)
2868#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
2869#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
2870#define I2C_TIMINGR_SDADEL_Pos (16U)
2871#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
2872#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
2873#define I2C_TIMINGR_SCLDEL_Pos (20U)
2874#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
2875#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
2876#define I2C_TIMINGR_PRESC_Pos (28U)
2877#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
2878#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
2879
2880/******************* Bit definition for I2C_TIMEOUTR register *******************/
2881#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
2882#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
2883#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
2884#define I2C_TIMEOUTR_TIDLE_Pos (12U)
2885#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
2886#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
2887#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
2888#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
2889#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
2890#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
2891#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
2892#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
2893#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
2894#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
2895#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
2896
2897/****************** Bit definition for I2C_ISR register *********************/
2898#define I2C_ISR_TXE_Pos (0U)
2899#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
2900#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
2901#define I2C_ISR_TXIS_Pos (1U)
2902#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
2903#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
2904#define I2C_ISR_RXNE_Pos (2U)
2905#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
2906#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
2907#define I2C_ISR_ADDR_Pos (3U)
2908#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
2909#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
2910#define I2C_ISR_NACKF_Pos (4U)
2911#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
2912#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
2913#define I2C_ISR_STOPF_Pos (5U)
2914#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
2915#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
2916#define I2C_ISR_TC_Pos (6U)
2917#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
2918#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
2919#define I2C_ISR_TCR_Pos (7U)
2920#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
2921#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
2922#define I2C_ISR_BERR_Pos (8U)
2923#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
2924#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
2925#define I2C_ISR_ARLO_Pos (9U)
2926#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
2927#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
2928#define I2C_ISR_OVR_Pos (10U)
2929#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
2930#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
2931#define I2C_ISR_PECERR_Pos (11U)
2932#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
2933#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
2934#define I2C_ISR_TIMEOUT_Pos (12U)
2935#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
2936#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
2937#define I2C_ISR_ALERT_Pos (13U)
2938#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
2939#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
2940#define I2C_ISR_BUSY_Pos (15U)
2941#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
2942#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
2943#define I2C_ISR_DIR_Pos (16U)
2944#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
2945#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
2946#define I2C_ISR_ADDCODE_Pos (17U)
2947#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
2948#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
2949
2950/****************** Bit definition for I2C_ICR register *********************/
2951#define I2C_ICR_ADDRCF_Pos (3U)
2952#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
2953#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
2954#define I2C_ICR_NACKCF_Pos (4U)
2955#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
2956#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
2957#define I2C_ICR_STOPCF_Pos (5U)
2958#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
2959#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
2960#define I2C_ICR_BERRCF_Pos (8U)
2961#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
2962#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
2963#define I2C_ICR_ARLOCF_Pos (9U)
2964#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
2965#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
2966#define I2C_ICR_OVRCF_Pos (10U)
2967#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
2968#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
2969#define I2C_ICR_PECCF_Pos (11U)
2970#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
2971#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
2972#define I2C_ICR_TIMOUTCF_Pos (12U)
2973#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
2974#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
2975#define I2C_ICR_ALERTCF_Pos (13U)
2976#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
2977#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
2978
2979/****************** Bit definition for I2C_PECR register *********************/
2980#define I2C_PECR_PEC_Pos (0U)
2981#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
2982#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
2983
2984/****************** Bit definition for I2C_RXDR register *********************/
2985#define I2C_RXDR_RXDATA_Pos (0U)
2986#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
2987#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
2988
2989/****************** Bit definition for I2C_TXDR register *********************/
2990#define I2C_TXDR_TXDATA_Pos (0U)
2991#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
2992#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
2993
2994/******************************************************************************/
2995/* */
2996/* Independent WATCHDOG (IWDG) */
2997/* */
2998/******************************************************************************/
2999/******************* Bit definition for IWDG_KR register ********************/
3000#define IWDG_KR_KEY_Pos (0U)
3001#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
3002#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
3003
3004/******************* Bit definition for IWDG_PR register ********************/
3005#define IWDG_PR_PR_Pos (0U)
3006#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
3007#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
3008#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
3009#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
3010#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
3011
3012/******************* Bit definition for IWDG_RLR register *******************/
3013#define IWDG_RLR_RL_Pos (0U)
3014#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
3015#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
3016
3017/******************* Bit definition for IWDG_SR register ********************/
3018#define IWDG_SR_PVU_Pos (0U)
3019#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
3020#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
3021#define IWDG_SR_RVU_Pos (1U)
3022#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
3023#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
3024#define IWDG_SR_WVU_Pos (2U)
3025#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
3026#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
3027
3028/******************* Bit definition for IWDG_KR register ********************/
3029#define IWDG_WINR_WIN_Pos (0U)
3030#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
3031#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
3032
3033/******************************************************************************/
3034/* */
3035/* Low Power Timer (LPTTIM) */
3036/* */
3037/******************************************************************************/
3038/****************** Bit definition for LPTIM_ISR register *******************/
3039#define LPTIM_ISR_CMPM_Pos (0U)
3040#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
3041#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
3042#define LPTIM_ISR_ARRM_Pos (1U)
3043#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
3044#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
3045#define LPTIM_ISR_EXTTRIG_Pos (2U)
3046#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
3047#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
3048#define LPTIM_ISR_CMPOK_Pos (3U)
3049#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
3050#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
3051#define LPTIM_ISR_ARROK_Pos (4U)
3052#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
3053#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
3054#define LPTIM_ISR_UP_Pos (5U)
3055#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
3056#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
3057#define LPTIM_ISR_DOWN_Pos (6U)
3058#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
3059#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
3060
3061/****************** Bit definition for LPTIM_ICR register *******************/
3062#define LPTIM_ICR_CMPMCF_Pos (0U)
3063#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
3064#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
3065#define LPTIM_ICR_ARRMCF_Pos (1U)
3066#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
3067#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
3068#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
3069#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
3070#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
3071#define LPTIM_ICR_CMPOKCF_Pos (3U)
3072#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
3073#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
3074#define LPTIM_ICR_ARROKCF_Pos (4U)
3075#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
3076#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
3077#define LPTIM_ICR_UPCF_Pos (5U)
3078#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
3079#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
3080#define LPTIM_ICR_DOWNCF_Pos (6U)
3081#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
3082#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
3083
3084/****************** Bit definition for LPTIM_IER register ********************/
3085#define LPTIM_IER_CMPMIE_Pos (0U)
3086#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
3087#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
3088#define LPTIM_IER_ARRMIE_Pos (1U)
3089#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
3090#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
3091#define LPTIM_IER_EXTTRIGIE_Pos (2U)
3092#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
3093#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
3094#define LPTIM_IER_CMPOKIE_Pos (3U)
3095#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
3096#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
3097#define LPTIM_IER_ARROKIE_Pos (4U)
3098#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
3099#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
3100#define LPTIM_IER_UPIE_Pos (5U)
3101#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
3102#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
3103#define LPTIM_IER_DOWNIE_Pos (6U)
3104#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
3105#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
3106
3107/****************** Bit definition for LPTIM_CFGR register *******************/
3108#define LPTIM_CFGR_CKSEL_Pos (0U)
3109#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
3110#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
3111
3112#define LPTIM_CFGR_CKPOL_Pos (1U)
3113#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
3114#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
3115#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
3116#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
3117
3118#define LPTIM_CFGR_CKFLT_Pos (3U)
3119#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
3120#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
3121#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
3122#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
3123
3124#define LPTIM_CFGR_TRGFLT_Pos (6U)
3125#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
3126#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
3127#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
3128#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
3129
3130#define LPTIM_CFGR_PRESC_Pos (9U)
3131#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
3132#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
3133#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
3134#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
3135#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
3136
3137#define LPTIM_CFGR_TRIGSEL_Pos (13U)
3138#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
3139#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
3140#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
3141#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
3142#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
3143
3144#define LPTIM_CFGR_TRIGEN_Pos (17U)
3145#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
3146#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
3147#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
3148#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
3149
3150#define LPTIM_CFGR_TIMOUT_Pos (19U)
3151#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
3152#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
3153#define LPTIM_CFGR_WAVE_Pos (20U)
3154#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
3155#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
3156#define LPTIM_CFGR_WAVPOL_Pos (21U)
3157#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
3158#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
3159#define LPTIM_CFGR_PRELOAD_Pos (22U)
3160#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
3161#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
3162#define LPTIM_CFGR_COUNTMODE_Pos (23U)
3163#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
3164#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
3165#define LPTIM_CFGR_ENC_Pos (24U)
3166#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
3167#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
3168
3169/****************** Bit definition for LPTIM_CR register ********************/
3170#define LPTIM_CR_ENABLE_Pos (0U)
3171#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
3172#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
3173#define LPTIM_CR_SNGSTRT_Pos (1U)
3174#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
3175#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
3176#define LPTIM_CR_CNTSTRT_Pos (2U)
3177#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
3178#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
3179
3180/****************** Bit definition for LPTIM_CMP register *******************/
3181#define LPTIM_CMP_CMP_Pos (0U)
3182#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
3183#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
3184
3185/****************** Bit definition for LPTIM_ARR register *******************/
3186#define LPTIM_ARR_ARR_Pos (0U)
3187#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
3188#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
3189
3190/****************** Bit definition for LPTIM_CNT register *******************/
3191#define LPTIM_CNT_CNT_Pos (0U)
3192#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
3193#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
3194
3195/******************************************************************************/
3196/* */
3197/* Power Control (PWR) */
3198/* */
3199/******************************************************************************/
3200
3201#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
3202
3203/******************** Bit definition for PWR_CR register ********************/
3204#define PWR_CR_LPSDSR_Pos (0U)
3205#define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
3206#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
3207#define PWR_CR_PDDS_Pos (1U)
3208#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
3209#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
3210#define PWR_CR_CWUF_Pos (2U)
3211#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
3212#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
3213#define PWR_CR_CSBF_Pos (3U)
3214#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
3215#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
3216#define PWR_CR_PVDE_Pos (4U)
3217#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
3218#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
3219
3220#define PWR_CR_PLS_Pos (5U)
3221#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
3222#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
3223#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
3224#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
3225#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
3226
3227/*!< PVD level configuration */
3228#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
3229#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
3230#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
3231#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
3232#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
3233#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
3234#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
3235#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
3236
3237#define PWR_CR_DBP_Pos (8U)
3238#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
3239#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
3240#define PWR_CR_ULP_Pos (9U)
3241#define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */
3242#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
3243#define PWR_CR_FWU_Pos (10U)
3244#define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */
3245#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
3246
3247#define PWR_CR_VOS_Pos (11U)
3248#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */
3249#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
3250#define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */
3251#define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */
3252#define PWR_CR_DSEEKOFF_Pos (13U)
3253#define PWR_CR_DSEEKOFF_Msk (0x1U << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
3254#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
3255#define PWR_CR_LPRUN_Pos (14U)
3256#define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
3257#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
3258
3259/******************* Bit definition for PWR_CSR register ********************/
3260#define PWR_CSR_WUF_Pos (0U)
3261#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
3262#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
3263#define PWR_CSR_SBF_Pos (1U)
3264#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
3265#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
3266#define PWR_CSR_PVDO_Pos (2U)
3267#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
3268#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
3269#define PWR_CSR_VREFINTRDYF_Pos (3U)
3270#define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
3271#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
3272#define PWR_CSR_VOSF_Pos (4U)
3273#define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
3274#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
3275#define PWR_CSR_REGLPF_Pos (5U)
3276#define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
3277#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
3278
3279#define PWR_CSR_EWUP1_Pos (8U)
3280#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
3281#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
3282#define PWR_CSR_EWUP2_Pos (9U)
3283#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
3284#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
3285#define PWR_CSR_EWUP3_Pos (10U)
3286#define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
3287#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
3288
3289/******************************************************************************/
3290/* */
3291/* Reset and Clock Control */
3292/* */
3293/******************************************************************************/
3294
3295#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
3296
3297/******************** Bit definition for RCC_CR register ********************/
3298#define RCC_CR_HSION_Pos (0U)
3299#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
3300#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
3301#define RCC_CR_HSIKERON_Pos (1U)
3302#define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
3303#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
3304#define RCC_CR_HSIRDY_Pos (2U)
3305#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
3306#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
3307#define RCC_CR_HSIDIVEN_Pos (3U)
3308#define RCC_CR_HSIDIVEN_Msk (0x1U << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
3309#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
3310#define RCC_CR_HSIDIVF_Pos (4U)
3311#define RCC_CR_HSIDIVF_Msk (0x1U << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
3312#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
3313#define RCC_CR_HSIOUTEN_Pos (5U)
3314#define RCC_CR_HSIOUTEN_Msk (0x1U << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
3315#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
3316#define RCC_CR_MSION_Pos (8U)
3317#define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */
3318#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
3319#define RCC_CR_MSIRDY_Pos (9U)
3320#define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
3321#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
3322#define RCC_CR_HSEON_Pos (16U)
3323#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
3324#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
3325#define RCC_CR_HSERDY_Pos (17U)
3326#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
3327#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
3328#define RCC_CR_HSEBYP_Pos (18U)
3329#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
3330#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
3331#define RCC_CR_CSSHSEON_Pos (19U)
3332#define RCC_CR_CSSHSEON_Msk (0x1U << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
3333#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
3334#define RCC_CR_RTCPRE_Pos (20U)
3335#define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
3336#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
3337#define RCC_CR_RTCPRE_0 (0x1U << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
3338#define RCC_CR_RTCPRE_1 (0x2U << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
3339#define RCC_CR_PLLON_Pos (24U)
3340#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
3341#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
3342#define RCC_CR_PLLRDY_Pos (25U)
3343#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
3344#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
3345
3346/* Reference defines */
3347#define RCC_CR_CSSON RCC_CR_CSSHSEON
3348
3349/******************** Bit definition for RCC_ICSCR register *****************/
3350#define RCC_ICSCR_HSICAL_Pos (0U)
3351#define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
3352#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
3353#define RCC_ICSCR_HSITRIM_Pos (8U)
3354#define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
3355#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
3356
3357#define RCC_ICSCR_MSIRANGE_Pos (13U)
3358#define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
3359#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
3360#define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
3361#define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
3362#define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
3363#define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
3364#define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
3365#define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
3366#define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
3367#define RCC_ICSCR_MSICAL_Pos (16U)
3368#define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
3369#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
3370#define RCC_ICSCR_MSITRIM_Pos (24U)
3371#define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
3372#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
3373
3374
3375/******************* Bit definition for RCC_CFGR register *******************/
3376/*!< SW configuration */
3377#define RCC_CFGR_SW_Pos (0U)
3378#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
3379#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
3380#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
3381#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
3382
3383#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
3384#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
3385#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
3386#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
3387
3388/*!< SWS configuration */
3389#define RCC_CFGR_SWS_Pos (2U)
3390#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
3391#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
3392#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
3393#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
3394
3395#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
3396#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
3397#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
3398#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
3399
3400/*!< HPRE configuration */
3401#define RCC_CFGR_HPRE_Pos (4U)
3402#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
3403#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
3404#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
3405#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
3406#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
3407#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
3408
3409#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
3410#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
3411#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
3412#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
3413#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
3414#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
3415#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
3416#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
3417#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
3418
3419/*!< PPRE1 configuration */
3420#define RCC_CFGR_PPRE1_Pos (8U)
3421#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
3422#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
3423#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
3424#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
3425#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
3426
3427#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
3428#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
3429#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
3430#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
3431#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
3432
3433/*!< PPRE2 configuration */
3434#define RCC_CFGR_PPRE2_Pos (11U)
3435#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
3436#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
3437#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
3438#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
3439#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
3440
3441#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
3442#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
3443#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
3444#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
3445#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
3446
3447#define RCC_CFGR_STOPWUCK_Pos (15U)
3448#define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
3449#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
3450
3451/*!< PLL entry clock source*/
3452#define RCC_CFGR_PLLSRC_Pos (16U)
3453#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
3454#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
3455
3456#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
3457#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
3458
3459
3460/*!< PLLMUL configuration */
3461#define RCC_CFGR_PLLMUL_Pos (18U)
3462#define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
3463#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
3464#define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
3465#define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
3466#define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
3467#define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
3468
3469#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
3470#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
3471#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
3472#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
3473#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
3474#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
3475#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
3476#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
3477#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
3478
3479/*!< PLLDIV configuration */
3480#define RCC_CFGR_PLLDIV_Pos (22U)
3481#define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
3482#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
3483#define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
3484#define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
3485
3486#define RCC_CFGR_PLLDIV2_Pos (22U)
3487#define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
3488#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
3489#define RCC_CFGR_PLLDIV3_Pos (23U)
3490#define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
3491#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
3492#define RCC_CFGR_PLLDIV4_Pos (22U)
3493#define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
3494#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
3495
3496/*!< MCO configuration */
3497#define RCC_CFGR_MCOSEL_Pos (24U)
3498#define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
3499#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
3500#define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
3501#define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
3502#define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
3503#define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
3504
3505#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
3506#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
3507#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
3508#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
3509#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
3510#define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
3511#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
3512#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
3513#define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
3514#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
3515#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
3516#define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
3517#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
3518#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
3519#define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
3520#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
3521#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
3522#define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
3523#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
3524#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
3525#define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
3526#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
3527
3528#define RCC_CFGR_MCOPRE_Pos (28U)
3529#define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
3530#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
3531#define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
3532#define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
3533#define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
3534
3535#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
3536#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
3537#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
3538#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
3539#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
3540
3541/* Legacy defines */
3542#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
3543#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
3544#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
3545#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
3546#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
3547#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
3548#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
3549#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
3550#ifdef RCC_CFGR_MCOSEL_HSI48
3551#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
3552#endif
3553
3554#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
3555#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
3556#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
3557#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */