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1/**
2 ******************************************************************************
3 * @file stm32l052xx.h
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
6 * This file contains all the peripheral register's definitions, bits
7 * definitions and memory mapping for stm32l052xx devices.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44/** @addtogroup CMSIS
45 * @{
46 */
47
48/** @addtogroup stm32l052xx
49 * @{
50 */
51
52#ifndef __STM32L052xx_H
53#define __STM32L052xx_H
54
55#ifdef __cplusplus
56 extern "C" {
57#endif
58
59
60/** @addtogroup Configuration_section_for_CMSIS
61 * @{
62 */
63/**
64 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
65 */
66#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
67#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */
68#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
69#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
70#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
71
72/**
73 * @}
74 */
75
76/** @addtogroup Peripheral_interrupt_number_definition
77 * @{
78 */
79
80/**
81 * @brief stm32l052xx Interrupt Number Definition, according to the selected device
82 * in @ref Library_configuration_section
83 */
84
85/*!< Interrupt Number Definition */
86typedef enum
87{
88/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
90 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
91 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
92 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
93 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
94
95/****** STM32L-0 specific Interrupt Numbers *********************************************************/
96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
97 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
98 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
99 FLASH_IRQn = 3, /*!< FLASH Interrupt */
100 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
101 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
102 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
103 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
104 TSC_IRQn = 8, /*!< TSC Interrupt */
105 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
106 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
107 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
108 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
109 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
110 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
111 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
112 TIM21_IRQn = 20, /*!< TIM21 Interrupt */
113 TIM22_IRQn = 22, /*!< TIM22 Interrupt */
114 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
115 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
116 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
117 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
118 USART1_IRQn = 27, /*!< USART1 Interrupt */
119 USART2_IRQn = 28, /*!< USART2 Interrupt */
120 RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
121 USB_IRQn = 31, /*!< USB global Interrupt */
122} IRQn_Type;
123
124/**
125 * @}
126 */
127
128#include "core_cm0plus.h"
129#include "system_stm32l0xx.h"
130#include <stdint.h>
131
132/** @addtogroup Peripheral_registers_structures
133 * @{
134 */
135
136/**
137 * @brief Analog to Digital Converter
138 */
139
140typedef struct
141{
142 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
143 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
144 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
145 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
146 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
147 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
148 uint32_t RESERVED1; /*!< Reserved, 0x18 */
149 uint32_t RESERVED2; /*!< Reserved, 0x1C */
150 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
151 uint32_t RESERVED3; /*!< Reserved, 0x24 */
152 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
153 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
154 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
155 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
156 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
157} ADC_TypeDef;
158
159typedef struct
160{
161 __IO uint32_t CCR;
162} ADC_Common_TypeDef;
163
164
165/**
166 * @brief Comparator
167 */
168
169typedef struct
170{
171 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
172} COMP_TypeDef;
173
174typedef struct
175{
176 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
177} COMP_Common_TypeDef;
178
179
180/**
181* @brief CRC calculation unit
182*/
183
184typedef struct
185{
186__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
187__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
188uint8_t RESERVED0; /*!< Reserved, 0x05 */
189uint16_t RESERVED1; /*!< Reserved, 0x06 */
190__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
191uint32_t RESERVED2; /*!< Reserved, 0x0C */
192__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
193__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
194} CRC_TypeDef;
195
196/**
197 * @brief Clock Recovery System
198 */
199
200typedef struct
201{
202__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
203__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
204__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
205__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
206} CRS_TypeDef;
207
208/**
209 * @brief Digital to Analog Converter
210 */
211
212typedef struct
213{
214 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
215 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
216 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
217 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
218 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
219 uint32_t RESERVED0[6]; /*!< 0x14-0x28 */
220 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
221 uint32_t RESERVED1; /*!< 0x30 */
222 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
223} DAC_TypeDef;
224
225/**
226 * @brief Debug MCU
227 */
228
229typedef struct
230{
231 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
232 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
233 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
234 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
235}DBGMCU_TypeDef;
236
237/**
238 * @brief DMA Controller
239 */
240
241typedef struct
242{
243 __IO uint32_t CCR; /*!< DMA channel x configuration register */
244 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
245 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
246 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
247} DMA_Channel_TypeDef;
248
249typedef struct
250{
251 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
252 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
253} DMA_TypeDef;
254
255typedef struct
256{
257 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
258} DMA_Request_TypeDef;
259
260/**
261 * @brief External Interrupt/Event Controller
262 */
263
264typedef struct
265{
266 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
267 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
268 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
269 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
270 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
271 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
272}EXTI_TypeDef;
273
274/**
275 * @brief FLASH Registers
276 */
277typedef struct
278{
279 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
280 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
281 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
282 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
283 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
284 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
285 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
286 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
287 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
288} FLASH_TypeDef;
289
290
291/**
292 * @brief Option Bytes Registers
293 */
294typedef struct
295{
296 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
297 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
298 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
299} OB_TypeDef;
300
301
302/**
303 * @brief General Purpose IO
304 */
305
306typedef struct
307{
308 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
309 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
310 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
311 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
312 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
313 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
314 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
315 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
316 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
317 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
318}GPIO_TypeDef;
319
320/**
321 * @brief LPTIMIMER
322 */
323typedef struct
324{
325 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
326 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
327 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
328 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
329 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
330 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
331 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
332 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
333} LPTIM_TypeDef;
334
335/**
336 * @brief SysTem Configuration
337 */
338
339typedef struct
340{
341 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
342 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
343 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
344 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
345 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
346} SYSCFG_TypeDef;
347
348
349
350/**
351 * @brief Inter-integrated Circuit Interface
352 */
353
354typedef struct
355{
356 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
357 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
358 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
359 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
360 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
361 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
362 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
363 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
364 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
365 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
366 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
367}I2C_TypeDef;
368
369
370/**
371 * @brief Independent WATCHDOG
372 */
373typedef struct
374{
375 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
376 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
377 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
378 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
379 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
380} IWDG_TypeDef;
381
382/**
383 * @brief MIFARE Firewall
384 */
385typedef struct
386{
387 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
388 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
389 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
390 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
391 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
392 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
393 __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
394 __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
395 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
396
397} FIREWALL_TypeDef;
398
399/**
400 * @brief Power Control
401 */
402typedef struct
403{
404 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
405 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
406} PWR_TypeDef;
407
408/**
409 * @brief Reset and Clock Control
410 */
411typedef struct
412{
413 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
414 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
415 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
416 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
417 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
418 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
419 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
420 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
421 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
422 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
423 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
424 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
425 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
426 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
427 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
428 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
429 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
430 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
431 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
432 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
433 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
434} RCC_TypeDef;
435
436/**
437 * @brief Random numbers generator
438 */
439typedef struct
440{
441 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
442 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
443 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
444} RNG_TypeDef;
445
446/**
447 * @brief Real-Time Clock
448 */
449typedef struct
450{
451 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
452 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
453 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
454 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
455 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
456 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
457 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
458 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
459 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
460 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
461 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
462 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
463 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
464 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
465 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
466 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
467 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
468 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
469 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
470 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
471 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
472 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
473 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
474 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
475 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
476} RTC_TypeDef;
477
478
479/**
480 * @brief Serial Peripheral Interface
481 */
482typedef struct
483{
484 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
485 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
486 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
487 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
488 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
489 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
490 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
491 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
492 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
493} SPI_TypeDef;
494
495/**
496 * @brief TIM
497 */
498typedef struct
499{
500 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
501 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
502 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
503 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
504 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
505 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
506 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
507 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
508 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
509 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
510 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
511 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
512 uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
513 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
514 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
515 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
516 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
517 uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
518 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
519 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
520 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
521} TIM_TypeDef;
522
523/**
524 * @brief Touch Sensing Controller (TSC)
525 */
526typedef struct
527{
528 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
529 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
530 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
531 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
532 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
533 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
534 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
535 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
536 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
537 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
538 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
539 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
540 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
541 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
542} TSC_TypeDef;
543
544/**
545 * @brief Universal Synchronous Asynchronous Receiver Transmitter
546 */
547typedef struct
548{
549 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
550 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
551 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
552 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
553 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
554 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
555 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
556 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
557 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
558 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
559 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
560} USART_TypeDef;
561
562/**
563 * @brief Window WATCHDOG
564 */
565typedef struct
566{
567 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
568 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
569 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
570} WWDG_TypeDef;
571
572/**
573 * @brief Universal Serial Bus Full Speed Device
574 */
575typedef struct
576{
577 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
578 __IO uint16_t RESERVED0; /*!< Reserved */
579 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
580 __IO uint16_t RESERVED1; /*!< Reserved */
581 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
582 __IO uint16_t RESERVED2; /*!< Reserved */
583 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
584 __IO uint16_t RESERVED3; /*!< Reserved */
585 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
586 __IO uint16_t RESERVED4; /*!< Reserved */
587 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
588 __IO uint16_t RESERVED5; /*!< Reserved */
589 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
590 __IO uint16_t RESERVED6; /*!< Reserved */
591 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
592 __IO uint16_t RESERVED7[17]; /*!< Reserved */
593 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
594 __IO uint16_t RESERVED8; /*!< Reserved */
595 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
596 __IO uint16_t RESERVED9; /*!< Reserved */
597 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
598 __IO uint16_t RESERVEDA; /*!< Reserved */
599 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
600 __IO uint16_t RESERVEDB; /*!< Reserved */
601 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
602 __IO uint16_t RESERVEDC; /*!< Reserved */
603 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
604 __IO uint16_t RESERVEDD; /*!< Reserved */
605 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
606 __IO uint16_t RESERVEDE; /*!< Reserved */
607} USB_TypeDef;
608
609/**
610 * @}
611 */
612
613/** @addtogroup Peripheral_memory_map
614 * @{
615 */
616#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
617#define FLASH_END ((uint32_t)0x0800FFFFU) /*!< FLASH end address in the alias region */
618#define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
619#define DATA_EEPROM_END ((uint32_t)0x080807FFU) /*!< DATA EEPROM end address in the alias region */
620#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
621#define SRAM_SIZE_MAX ((uint32_t)0x00002000U) /*!< maximum SRAM size (up to 8KBytes) */
622
623#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
624
625/*!< Peripheral memory map */
626#define APBPERIPH_BASE PERIPH_BASE
627#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
628#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000U)
629
630#define TIM2_BASE (APBPERIPH_BASE + 0x00000000U)
631#define TIM6_BASE (APBPERIPH_BASE + 0x00001000U)
632#define RTC_BASE (APBPERIPH_BASE + 0x00002800U)
633#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U)
634#define IWDG_BASE (APBPERIPH_BASE + 0x00003000U)
635#define SPI2_BASE (APBPERIPH_BASE + 0x00003800U)
636#define USART2_BASE (APBPERIPH_BASE + 0x00004400U)
637#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800U)
638#define I2C1_BASE (APBPERIPH_BASE + 0x00005400U)
639#define I2C2_BASE (APBPERIPH_BASE + 0x00005800U)
640#define CRS_BASE (APBPERIPH_BASE + 0x00006C00U)
641#define PWR_BASE (APBPERIPH_BASE + 0x00007000U)
642#define DAC_BASE (APBPERIPH_BASE + 0x00007400U)
643#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U)
644
645#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000U)
646#define COMP1_BASE (APBPERIPH_BASE + 0x00010018U)
647#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CU)
648#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
649#define EXTI_BASE (APBPERIPH_BASE + 0x00010400U)
650#define TIM21_BASE (APBPERIPH_BASE + 0x00010800U)
651#define TIM22_BASE (APBPERIPH_BASE + 0x00011400U)
652#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00U)
653#define ADC1_BASE (APBPERIPH_BASE + 0x00012400U)
654#define ADC_BASE (APBPERIPH_BASE + 0x00012708U)
655#define SPI1_BASE (APBPERIPH_BASE + 0x00013000U)
656#define USART1_BASE (APBPERIPH_BASE + 0x00013800U)
657#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800U)
658
659#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
660#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
661#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
662#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
663#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
664#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
665#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
666#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
667#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U)
668
669
670#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
671#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
672#define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
673#define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */
674#define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */
675#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
676#define TSC_BASE (AHBPERIPH_BASE + 0x00004000U)
677#define RNG_BASE (AHBPERIPH_BASE + 0x00005000U)
678
679#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U)
680#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U)
681#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800U)
682#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00U)
683#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00U)
684
685/**
686 * @}
687 */
688
689/** @addtogroup Peripheral_declaration
690 * @{
691 */
692
693#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
694#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
695#define RTC ((RTC_TypeDef *) RTC_BASE)
696#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
697#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
698#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
699#define USART2 ((USART_TypeDef *) USART2_BASE)
700#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
701#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
702#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
703#define CRS ((CRS_TypeDef *) CRS_BASE)
704#define PWR ((PWR_TypeDef *) PWR_BASE)
705#define DAC ((DAC_TypeDef *) DAC_BASE)
706#define DAC1 ((DAC_TypeDef *) DAC_BASE)
707#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
708
709#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
710#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
711#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
712#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
713#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
714#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
715#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
716#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
717#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
718/* Legacy defines */
719#define ADC ADC1_COMMON
720#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
721#define USART1 ((USART_TypeDef *) USART1_BASE)
722#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
723
724#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
725#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
726#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
727#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
728#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
729#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
730#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
731#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
732#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
733
734
735#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
736#define OB ((OB_TypeDef *) OB_BASE)
737#define RCC ((RCC_TypeDef *) RCC_BASE)
738#define CRC ((CRC_TypeDef *) CRC_BASE)
739#define TSC ((TSC_TypeDef *) TSC_BASE)
740#define RNG ((RNG_TypeDef *) RNG_BASE)
741
742#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
743#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
744#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
745#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
746#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
747
748#define USB ((USB_TypeDef *) USB_BASE)
749
750/**
751 * @}
752 */
753
754/** @addtogroup Exported_constants
755 * @{
756 */
757
758 /** @addtogroup Peripheral_Registers_Bits_Definition
759 * @{
760 */
761
762/******************************************************************************/
763/* Peripheral Registers Bits Definition */
764/******************************************************************************/
765/******************************************************************************/
766/* */
767/* Analog to Digital Converter (ADC) */
768/* */
769/******************************************************************************/
770/******************** Bits definition for ADC_ISR register ******************/
771#define ADC_ISR_EOCAL_Pos (11U)
772#define ADC_ISR_EOCAL_Msk (0x1U << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
773#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
774#define ADC_ISR_AWD_Pos (7U)
775#define ADC_ISR_AWD_Msk (0x1U << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
776#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
777#define ADC_ISR_OVR_Pos (4U)
778#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
779#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
780#define ADC_ISR_EOSEQ_Pos (3U)
781#define ADC_ISR_EOSEQ_Msk (0x1U << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
782#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
783#define ADC_ISR_EOC_Pos (2U)
784#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
785#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
786#define ADC_ISR_EOSMP_Pos (1U)
787#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
788#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
789#define ADC_ISR_ADRDY_Pos (0U)
790#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
791#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
792
793/* Old EOSEQ bit definition, maintained for legacy purpose */
794#define ADC_ISR_EOS ADC_ISR_EOSEQ
795
796/******************** Bits definition for ADC_IER register ******************/
797#define ADC_IER_EOCALIE_Pos (11U)
798#define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
799#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
800#define ADC_IER_AWDIE_Pos (7U)
801#define ADC_IER_AWDIE_Msk (0x1U << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
802#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
803#define ADC_IER_OVRIE_Pos (4U)
804#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
805#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
806#define ADC_IER_EOSEQIE_Pos (3U)
807#define ADC_IER_EOSEQIE_Msk (0x1U << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
808#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
809#define ADC_IER_EOCIE_Pos (2U)
810#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
811#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
812#define ADC_IER_EOSMPIE_Pos (1U)
813#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
814#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
815#define ADC_IER_ADRDYIE_Pos (0U)
816#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
817#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
818
819/* Old EOSEQIE bit definition, maintained for legacy purpose */
820#define ADC_IER_EOSIE ADC_IER_EOSEQIE
821
822/******************** Bits definition for ADC_CR register *******************/
823#define ADC_CR_ADCAL_Pos (31U)
824#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
825#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
826#define ADC_CR_ADVREGEN_Pos (28U)
827#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
828#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
829#define ADC_CR_ADSTP_Pos (4U)
830#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
831#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
832#define ADC_CR_ADSTART_Pos (2U)
833#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
834#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
835#define ADC_CR_ADDIS_Pos (1U)
836#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
837#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
838#define ADC_CR_ADEN_Pos (0U)
839#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
840#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
841
842/******************* Bits definition for ADC_CFGR1 register *****************/
843#define ADC_CFGR1_AWDCH_Pos (26U)
844#define ADC_CFGR1_AWDCH_Msk (0x1FU << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
845#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
846#define ADC_CFGR1_AWDCH_0 (0x01U << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
847#define ADC_CFGR1_AWDCH_1 (0x02U << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
848#define ADC_CFGR1_AWDCH_2 (0x04U << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
849#define ADC_CFGR1_AWDCH_3 (0x08U << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
850#define ADC_CFGR1_AWDCH_4 (0x10U << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
851#define ADC_CFGR1_AWDEN_Pos (23U)
852#define ADC_CFGR1_AWDEN_Msk (0x1U << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
853#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
854#define ADC_CFGR1_AWDSGL_Pos (22U)
855#define ADC_CFGR1_AWDSGL_Msk (0x1U << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
856#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
857#define ADC_CFGR1_DISCEN_Pos (16U)
858#define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
859#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
860#define ADC_CFGR1_AUTOFF_Pos (15U)
861#define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
862#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
863#define ADC_CFGR1_WAIT_Pos (14U)
864#define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
865#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
866#define ADC_CFGR1_CONT_Pos (13U)
867#define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
868#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
869#define ADC_CFGR1_OVRMOD_Pos (12U)
870#define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
871#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
872#define ADC_CFGR1_EXTEN_Pos (10U)
873#define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
874#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
875#define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
876#define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
877#define ADC_CFGR1_EXTSEL_Pos (6U)
878#define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
879#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
880#define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
881#define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
882#define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
883#define ADC_CFGR1_ALIGN_Pos (5U)
884#define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
885#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
886#define ADC_CFGR1_RES_Pos (3U)
887#define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
888#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
889#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
890#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
891#define ADC_CFGR1_SCANDIR_Pos (2U)
892#define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
893#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
894#define ADC_CFGR1_DMACFG_Pos (1U)
895#define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
896#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
897#define ADC_CFGR1_DMAEN_Pos (0U)
898#define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
899#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
900
901/* Old WAIT bit definition, maintained for legacy purpose */
902#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
903
904/******************* Bits definition for ADC_CFGR2 register *****************/
905#define ADC_CFGR2_TOVS_Pos (9U)
906#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
907#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
908#define ADC_CFGR2_OVSS_Pos (5U)
909#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
910#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
911#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
912#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
913#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
914#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
915#define ADC_CFGR2_OVSR_Pos (2U)
916#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
917#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
918#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
919#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
920#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
921#define ADC_CFGR2_OVSE_Pos (0U)
922#define ADC_CFGR2_OVSE_Msk (0x1U << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
923#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
924#define ADC_CFGR2_CKMODE_Pos (30U)
925#define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
926#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
927#define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
928#define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
929
930
931/****************** Bit definition for ADC_SMPR register ********************/
932#define ADC_SMPR_SMP_Pos (0U)
933#define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
934#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
935#define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
936#define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
937#define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
938
939/* Legacy defines */
940#define ADC_SMPR_SMPR ADC_SMPR_SMP
941#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
942#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
943#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
944
945/******************* Bit definition for ADC_TR register ********************/
946#define ADC_TR_HT_Pos (16U)
947#define ADC_TR_HT_Msk (0xFFFU << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
948#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
949#define ADC_TR_LT_Pos (0U)
950#define ADC_TR_LT_Msk (0xFFFU << ADC_TR_LT_Pos) /*!< 0x00000FFF */
951#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
952
953/****************** Bit definition for ADC_CHSELR register ******************/
954#define ADC_CHSELR_CHSEL_Pos (0U)
955#define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
956#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
957#define ADC_CHSELR_CHSEL18_Pos (18U)
958#define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
959#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
960#define ADC_CHSELR_CHSEL17_Pos (17U)
961#define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
962#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
963#define ADC_CHSELR_CHSEL15_Pos (15U)
964#define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
965#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
966#define ADC_CHSELR_CHSEL14_Pos (14U)
967#define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
968#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
969#define ADC_CHSELR_CHSEL13_Pos (13U)
970#define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
971#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
972#define ADC_CHSELR_CHSEL12_Pos (12U)
973#define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
974#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
975#define ADC_CHSELR_CHSEL11_Pos (11U)
976#define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
977#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
978#define ADC_CHSELR_CHSEL10_Pos (10U)
979#define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
980#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
981#define ADC_CHSELR_CHSEL9_Pos (9U)
982#define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
983#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
984#define ADC_CHSELR_CHSEL8_Pos (8U)
985#define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
986#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
987#define ADC_CHSELR_CHSEL7_Pos (7U)
988#define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
989#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
990#define ADC_CHSELR_CHSEL6_Pos (6U)
991#define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
992#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
993#define ADC_CHSELR_CHSEL5_Pos (5U)
994#define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
995#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
996#define ADC_CHSELR_CHSEL4_Pos (4U)
997#define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
998#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
999#define ADC_CHSELR_CHSEL3_Pos (3U)
1000#define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
1001#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
1002#define ADC_CHSELR_CHSEL2_Pos (2U)
1003#define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
1004#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
1005#define ADC_CHSELR_CHSEL1_Pos (1U)
1006#define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
1007#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
1008#define ADC_CHSELR_CHSEL0_Pos (0U)
1009#define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
1010#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
1011
1012/******************** Bit definition for ADC_DR register ********************/
1013#define ADC_DR_DATA_Pos (0U)
1014#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1015#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
1016
1017/******************** Bit definition for ADC_CALFACT register ********************/
1018#define ADC_CALFACT_CALFACT_Pos (0U)
1019#define ADC_CALFACT_CALFACT_Msk (0x7FU << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
1020#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
1021
1022/******************* Bit definition for ADC_CCR register ********************/
1023#define ADC_CCR_LFMEN_Pos (25U)
1024#define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
1025#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
1026#define ADC_CCR_TSEN_Pos (23U)
1027#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
1028#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
1029#define ADC_CCR_VREFEN_Pos (22U)
1030#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
1031#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
1032#define ADC_CCR_PRESC_Pos (18U)
1033#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
1034#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
1035#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
1036#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
1037#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
1038#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
1039
1040/******************************************************************************/
1041/* */
1042/* Analog Comparators (COMP) */
1043/* */
1044/******************************************************************************/
1045/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
1046/* COMP1 bits definition */
1047#define COMP_CSR_COMP1EN_Pos (0U)
1048#define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
1049#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
1050#define COMP_CSR_COMP1INNSEL_Pos (4U)
1051#define COMP_CSR_COMP1INNSEL_Msk (0x3U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1052#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
1053#define COMP_CSR_COMP1INNSEL_0 (0x1U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1054#define COMP_CSR_COMP1INNSEL_1 (0x2U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
1055#define COMP_CSR_COMP1WM_Pos (8U)
1056#define COMP_CSR_COMP1WM_Msk (0x1U << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
1057#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
1058#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
1059#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
1060#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
1061#define COMP_CSR_COMP1POLARITY_Pos (15U)
1062#define COMP_CSR_COMP1POLARITY_Msk (0x1U << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
1063#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
1064#define COMP_CSR_COMP1VALUE_Pos (30U)
1065#define COMP_CSR_COMP1VALUE_Msk (0x1U << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
1066#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
1067#define COMP_CSR_COMP1LOCK_Pos (31U)
1068#define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
1069#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
1070/* COMP2 bits definition */
1071#define COMP_CSR_COMP2EN_Pos (0U)
1072#define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
1073#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
1074#define COMP_CSR_COMP2SPEED_Pos (3U)
1075#define COMP_CSR_COMP2SPEED_Msk (0x1U << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
1076#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
1077#define COMP_CSR_COMP2INNSEL_Pos (4U)
1078#define COMP_CSR_COMP2INNSEL_Msk (0x7U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
1079#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
1080#define COMP_CSR_COMP2INNSEL_0 (0x1U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
1081#define COMP_CSR_COMP2INNSEL_1 (0x2U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
1082#define COMP_CSR_COMP2INNSEL_2 (0x4U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1083#define COMP_CSR_COMP2INPSEL_Pos (8U)
1084#define COMP_CSR_COMP2INPSEL_Msk (0x7U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
1085#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
1086#define COMP_CSR_COMP2INPSEL_0 (0x1U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
1087#define COMP_CSR_COMP2INPSEL_1 (0x2U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
1088#define COMP_CSR_COMP2INPSEL_2 (0x4U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
1089#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
1090#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
1091#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
1092#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
1093#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
1094#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
1095#define COMP_CSR_COMP2POLARITY_Pos (15U)
1096#define COMP_CSR_COMP2POLARITY_Msk (0x1U << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
1097#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
1098#define COMP_CSR_COMP2VALUE_Pos (30U)
1099#define COMP_CSR_COMP2VALUE_Msk (0x1U << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
1100#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
1101#define COMP_CSR_COMP2LOCK_Pos (31U)
1102#define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
1103#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
1104
1105/********************** Bit definition for COMP_CSR register common ****************/
1106#define COMP_CSR_COMPxEN_Pos (0U)
1107#define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
1108#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
1109#define COMP_CSR_COMPxPOLARITY_Pos (15U)
1110#define COMP_CSR_COMPxPOLARITY_Msk (0x1U << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
1111#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
1112#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
1113#define COMP_CSR_COMPxOUTVALUE_Msk (0x1U << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
1114#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
1115#define COMP_CSR_COMPxLOCK_Pos (31U)
1116#define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
1117#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
1118
1119/* Reference defines */
1120#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
1121
1122/******************************************************************************/
1123/* */
1124/* CRC calculation unit (CRC) */
1125/* */
1126/******************************************************************************/
1127/******************* Bit definition for CRC_DR register *********************/
1128#define CRC_DR_DR_Pos (0U)
1129#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
1130#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
1131
1132/******************* Bit definition for CRC_IDR register ********************/
1133#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
1134
1135/******************** Bit definition for CRC_CR register ********************/
1136#define CRC_CR_RESET_Pos (0U)
1137#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
1138#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
1139#define CRC_CR_POLYSIZE_Pos (3U)
1140#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
1141#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
1142#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
1143#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
1144#define CRC_CR_REV_IN_Pos (5U)
1145#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
1146#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
1147#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
1148#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
1149#define CRC_CR_REV_OUT_Pos (7U)
1150#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
1151#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
1152
1153/******************* Bit definition for CRC_INIT register *******************/
1154#define CRC_INIT_INIT_Pos (0U)
1155#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
1156#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
1157
1158/******************* Bit definition for CRC_POL register ********************/
1159#define CRC_POL_POL_Pos (0U)
1160#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
1161#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
1162
1163/******************************************************************************/
1164/* */
1165/* CRS Clock Recovery System */
1166/* */
1167/******************************************************************************/
1168
1169/******************* Bit definition for CRS_CR register *********************/
1170#define CRS_CR_SYNCOKIE_Pos (0U)
1171#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
1172#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */
1173#define CRS_CR_SYNCWARNIE_Pos (1U)
1174#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
1175#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */
1176#define CRS_CR_ERRIE_Pos (2U)
1177#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
1178#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */
1179#define CRS_CR_ESYNCIE_Pos (3U)
1180#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
1181#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/
1182#define CRS_CR_CEN_Pos (5U)
1183#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
1184#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */
1185#define CRS_CR_AUTOTRIMEN_Pos (6U)
1186#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
1187#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */
1188#define CRS_CR_SWSYNC_Pos (7U)
1189#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
1190#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */
1191#define CRS_CR_TRIM_Pos (8U)
1192#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
1193#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */
1194
1195/******************* Bit definition for CRS_CFGR register *********************/
1196#define CRS_CFGR_RELOAD_Pos (0U)
1197#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
1198#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */
1199#define CRS_CFGR_FELIM_Pos (16U)
1200#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
1201#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */
1202
1203#define CRS_CFGR_SYNCDIV_Pos (24U)
1204#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
1205#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */
1206#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
1207#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
1208#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
1209
1210#define CRS_CFGR_SYNCSRC_Pos (28U)
1211#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
1212#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */
1213#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
1214#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
1215
1216#define CRS_CFGR_SYNCPOL_Pos (31U)
1217#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
1218#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */
1219
1220/******************* Bit definition for CRS_ISR register *********************/
1221#define CRS_ISR_SYNCOKF_Pos (0U)
1222#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
1223#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */
1224#define CRS_ISR_SYNCWARNF_Pos (1U)
1225#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
1226#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */
1227#define CRS_ISR_ERRF_Pos (2U)
1228#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
1229#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */
1230#define CRS_ISR_ESYNCF_Pos (3U)
1231#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
1232#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */
1233#define CRS_ISR_SYNCERR_Pos (8U)
1234#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
1235#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */
1236#define CRS_ISR_SYNCMISS_Pos (9U)
1237#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
1238#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */
1239#define CRS_ISR_TRIMOVF_Pos (10U)
1240#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
1241#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */
1242#define CRS_ISR_FEDIR_Pos (15U)
1243#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
1244#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */
1245#define CRS_ISR_FECAP_Pos (16U)
1246#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
1247#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */
1248
1249/******************* Bit definition for CRS_ICR register *********************/
1250#define CRS_ICR_SYNCOKC_Pos (0U)
1251#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
1252#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */
1253#define CRS_ICR_SYNCWARNC_Pos (1U)
1254#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
1255#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */
1256#define CRS_ICR_ERRC_Pos (2U)
1257#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
1258#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */
1259#define CRS_ICR_ESYNCC_Pos (3U)
1260#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
1261#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */
1262
1263/******************************************************************************/
1264/* */
1265/* Digital to Analog Converter (DAC) */
1266/* */
1267/******************************************************************************/
1268
1269/*
1270 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
1271 */
1272/* Note: No specific macro feature on this device */
1273
1274/******************** Bit definition for DAC_CR register ********************/
1275#define DAC_CR_EN1_Pos (0U)
1276#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
1277#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
1278#define DAC_CR_BOFF1_Pos (1U)
1279#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
1280#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
1281#define DAC_CR_TEN1_Pos (2U)
1282#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
1283#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
1284
1285#define DAC_CR_TSEL1_Pos (3U)
1286#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
1287#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
1288#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
1289#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
1290#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
1291
1292#define DAC_CR_WAVE1_Pos (6U)
1293#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
1294#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1295#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
1296#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
1297
1298#define DAC_CR_MAMP1_Pos (8U)
1299#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
1300#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1301#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
1302#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
1303#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
1304#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
1305
1306#define DAC_CR_DMAEN1_Pos (12U)
1307#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
1308#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
1309#define DAC_CR_DMAUDRIE1_Pos (13U)
1310#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
1311#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */
1312
1313/***************** Bit definition for DAC_SWTRIGR register ******************/
1314#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
1315#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
1316#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
1317
1318/***************** Bit definition for DAC_DHR12R1 register ******************/
1319#define DAC_DHR12R1_DACC1DHR_Pos (0U)
1320#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
1321#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
1322
1323/***************** Bit definition for DAC_DHR12L1 register ******************/
1324#define DAC_DHR12L1_DACC1DHR_Pos (4U)
1325#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
1326#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
1327
1328/****************** Bit definition for DAC_DHR8R1 register ******************/
1329#define DAC_DHR8R1_DACC1DHR_Pos (0U)
1330#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
1331#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
1332
1333/******************* Bit definition for DAC_DOR1 register *******************/
1334#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */
1335
1336/******************** Bit definition for DAC_SR register ********************/
1337#define DAC_SR_DMAUDR1_Pos (13U)
1338#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
1339#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
1340
1341/******************************************************************************/
1342/* */
1343/* Debug MCU (DBGMCU) */
1344/* */
1345/******************************************************************************/
1346
1347/**************** Bit definition for DBGMCU_IDCODE register *****************/
1348#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
1349#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
1350#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
1351
1352#define DBGMCU_IDCODE_REV_ID_Pos (16U)
1353#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
1354#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
1355#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
1356#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
1357#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
1358#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
1359#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
1360#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
1361#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
1362#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
1363#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
1364#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
1365#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
1366#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
1367#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
1368#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
1369#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
1370#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
1371
1372/****************** Bit definition for DBGMCU_CR register *******************/
1373#define DBGMCU_CR_DBG_Pos (0U)
1374#define DBGMCU_CR_DBG_Msk (0x7U << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
1375#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
1376#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
1377#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
1378#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
1379#define DBGMCU_CR_DBG_STOP_Pos (1U)
1380#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
1381#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
1382#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
1383#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
1384#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
1385
1386/****************** Bit definition for DBGMCU_APB1_FZ register **************/
1387#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
1388#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
1389#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
1390#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
1391#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
1392#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
1393#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
1394#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
1395#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
1396#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
1397#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
1398#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
1399#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
1400#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
1401#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
1402#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
1403#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
1404#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
1405#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
1406#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
1407#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
1408#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
1409#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
1410#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
1411/****************** Bit definition for DBGMCU_APB2_FZ register **************/
1412#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
1413#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
1414#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
1415#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
1416#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
1417#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
1418
1419/******************************************************************************/
1420/* */
1421/* DMA Controller (DMA) */
1422/* */
1423/******************************************************************************/
1424
1425/******************* Bit definition for DMA_ISR register ********************/
1426#define DMA_ISR_GIF1_Pos (0U)
1427#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
1428#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
1429#define DMA_ISR_TCIF1_Pos (1U)
1430#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
1431#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
1432#define DMA_ISR_HTIF1_Pos (2U)
1433#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
1434#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
1435#define DMA_ISR_TEIF1_Pos (3U)
1436#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
1437#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
1438#define DMA_ISR_GIF2_Pos (4U)
1439#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
1440#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
1441#define DMA_ISR_TCIF2_Pos (5U)
1442#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
1443#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
1444#define DMA_ISR_HTIF2_Pos (6U)
1445#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
1446#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
1447#define DMA_ISR_TEIF2_Pos (7U)
1448#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
1449#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
1450#define DMA_ISR_GIF3_Pos (8U)
1451#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
1452#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
1453#define DMA_ISR_TCIF3_Pos (9U)
1454#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
1455#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
1456#define DMA_ISR_HTIF3_Pos (10U)
1457#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
1458#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
1459#define DMA_ISR_TEIF3_Pos (11U)
1460#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
1461#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
1462#define DMA_ISR_GIF4_Pos (12U)
1463#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
1464#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
1465#define DMA_ISR_TCIF4_Pos (13U)
1466#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
1467#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
1468#define DMA_ISR_HTIF4_Pos (14U)
1469#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
1470#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
1471#define DMA_ISR_TEIF4_Pos (15U)
1472#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
1473#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
1474#define DMA_ISR_GIF5_Pos (16U)
1475#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
1476#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
1477#define DMA_ISR_TCIF5_Pos (17U)
1478#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
1479#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
1480#define DMA_ISR_HTIF5_Pos (18U)
1481#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
1482#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
1483#define DMA_ISR_TEIF5_Pos (19U)
1484#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
1485#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
1486#define DMA_ISR_GIF6_Pos (20U)
1487#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
1488#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
1489#define DMA_ISR_TCIF6_Pos (21U)
1490#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
1491#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
1492#define DMA_ISR_HTIF6_Pos (22U)
1493#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
1494#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
1495#define DMA_ISR_TEIF6_Pos (23U)
1496#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
1497#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
1498#define DMA_ISR_GIF7_Pos (24U)
1499#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
1500#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
1501#define DMA_ISR_TCIF7_Pos (25U)
1502#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
1503#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
1504#define DMA_ISR_HTIF7_Pos (26U)
1505#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
1506#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
1507#define DMA_ISR_TEIF7_Pos (27U)
1508#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
1509#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
1510
1511/******************* Bit definition for DMA_IFCR register *******************/
1512#define DMA_IFCR_CGIF1_Pos (0U)
1513#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
1514#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
1515#define DMA_IFCR_CTCIF1_Pos (1U)
1516#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1517#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
1518#define DMA_IFCR_CHTIF1_Pos (2U)
1519#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1520#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
1521#define DMA_IFCR_CTEIF1_Pos (3U)
1522#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1523#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
1524#define DMA_IFCR_CGIF2_Pos (4U)
1525#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
1526#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
1527#define DMA_IFCR_CTCIF2_Pos (5U)
1528#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1529#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
1530#define DMA_IFCR_CHTIF2_Pos (6U)
1531#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1532#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
1533#define DMA_IFCR_CTEIF2_Pos (7U)
1534#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
1535#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
1536#define DMA_IFCR_CGIF3_Pos (8U)
1537#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
1538#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
1539#define DMA_IFCR_CTCIF3_Pos (9U)
1540#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
1541#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
1542#define DMA_IFCR_CHTIF3_Pos (10U)
1543#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
1544#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
1545#define DMA_IFCR_CTEIF3_Pos (11U)
1546#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
1547#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
1548#define DMA_IFCR_CGIF4_Pos (12U)
1549#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
1550#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
1551#define DMA_IFCR_CTCIF4_Pos (13U)
1552#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
1553#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
1554#define DMA_IFCR_CHTIF4_Pos (14U)
1555#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
1556#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
1557#define DMA_IFCR_CTEIF4_Pos (15U)
1558#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
1559#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
1560#define DMA_IFCR_CGIF5_Pos (16U)
1561#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
1562#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
1563#define DMA_IFCR_CTCIF5_Pos (17U)
1564#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
1565#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
1566#define DMA_IFCR_CHTIF5_Pos (18U)
1567#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
1568#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
1569#define DMA_IFCR_CTEIF5_Pos (19U)
1570#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
1571#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
1572#define DMA_IFCR_CGIF6_Pos (20U)
1573#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
1574#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
1575#define DMA_IFCR_CTCIF6_Pos (21U)
1576#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
1577#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
1578#define DMA_IFCR_CHTIF6_Pos (22U)
1579#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
1580#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
1581#define DMA_IFCR_CTEIF6_Pos (23U)
1582#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
1583#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
1584#define DMA_IFCR_CGIF7_Pos (24U)
1585#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
1586#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
1587#define DMA_IFCR_CTCIF7_Pos (25U)
1588#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
1589#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
1590#define DMA_IFCR_CHTIF7_Pos (26U)
1591#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
1592#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
1593#define DMA_IFCR_CTEIF7_Pos (27U)
1594#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
1595#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
1596
1597/******************* Bit definition for DMA_CCR register ********************/
1598#define DMA_CCR_EN_Pos (0U)
1599#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
1600#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
1601#define DMA_CCR_TCIE_Pos (1U)
1602#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
1603#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
1604#define DMA_CCR_HTIE_Pos (2U)
1605#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
1606#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
1607#define DMA_CCR_TEIE_Pos (3U)
1608#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
1609#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
1610#define DMA_CCR_DIR_Pos (4U)
1611#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
1612#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
1613#define DMA_CCR_CIRC_Pos (5U)
1614#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
1615#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
1616#define DMA_CCR_PINC_Pos (6U)
1617#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
1618#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
1619#define DMA_CCR_MINC_Pos (7U)
1620#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1621#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
1622
1623#define DMA_CCR_PSIZE_Pos (8U)
1624#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
1625#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
1626#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
1627#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
1628
1629#define DMA_CCR_MSIZE_Pos (10U)
1630#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
1631#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
1632#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
1633#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
1634
1635#define DMA_CCR_PL_Pos (12U)
1636#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
1637#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
1638#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
1639#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
1640
1641#define DMA_CCR_MEM2MEM_Pos (14U)
1642#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
1643#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
1644
1645/****************** Bit definition for DMA_CNDTR register *******************/
1646#define DMA_CNDTR_NDT_Pos (0U)
1647#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
1648#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
1649
1650/****************** Bit definition for DMA_CPAR register ********************/
1651#define DMA_CPAR_PA_Pos (0U)
1652#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
1653#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
1654
1655/****************** Bit definition for DMA_CMAR register ********************/
1656#define DMA_CMAR_MA_Pos (0U)
1657#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
1658#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
1659
1660
1661/******************* Bit definition for DMA_CSELR register *******************/
1662#define DMA_CSELR_C1S_Pos (0U)
1663#define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
1664#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
1665#define DMA_CSELR_C2S_Pos (4U)
1666#define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
1667#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
1668#define DMA_CSELR_C3S_Pos (8U)
1669#define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
1670#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
1671#define DMA_CSELR_C4S_Pos (12U)
1672#define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
1673#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
1674#define DMA_CSELR_C5S_Pos (16U)
1675#define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
1676#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
1677#define DMA_CSELR_C6S_Pos (20U)
1678#define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
1679#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
1680#define DMA_CSELR_C7S_Pos (24U)
1681#define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
1682#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
1683
1684/******************************************************************************/
1685/* */
1686/* External Interrupt/Event Controller (EXTI) */
1687/* */
1688/******************************************************************************/
1689
1690/******************* Bit definition for EXTI_IMR register *******************/
1691#define EXTI_IMR_IM0_Pos (0U)
1692#define EXTI_IMR_IM0_Msk (0x1U << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
1693#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
1694#define EXTI_IMR_IM1_Pos (1U)
1695#define EXTI_IMR_IM1_Msk (0x1U << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
1696#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
1697#define EXTI_IMR_IM2_Pos (2U)
1698#define EXTI_IMR_IM2_Msk (0x1U << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
1699#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
1700#define EXTI_IMR_IM3_Pos (3U)
1701#define EXTI_IMR_IM3_Msk (0x1U << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
1702#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
1703#define EXTI_IMR_IM4_Pos (4U)
1704#define EXTI_IMR_IM4_Msk (0x1U << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
1705#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
1706#define EXTI_IMR_IM5_Pos (5U)
1707#define EXTI_IMR_IM5_Msk (0x1U << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
1708#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
1709#define EXTI_IMR_IM6_Pos (6U)
1710#define EXTI_IMR_IM6_Msk (0x1U << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
1711#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
1712#define EXTI_IMR_IM7_Pos (7U)
1713#define EXTI_IMR_IM7_Msk (0x1U << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
1714#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
1715#define EXTI_IMR_IM8_Pos (8U)
1716#define EXTI_IMR_IM8_Msk (0x1U << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
1717#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
1718#define EXTI_IMR_IM9_Pos (9U)
1719#define EXTI_IMR_IM9_Msk (0x1U << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
1720#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
1721#define EXTI_IMR_IM10_Pos (10U)
1722#define EXTI_IMR_IM10_Msk (0x1U << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
1723#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
1724#define EXTI_IMR_IM11_Pos (11U)
1725#define EXTI_IMR_IM11_Msk (0x1U << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
1726#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
1727#define EXTI_IMR_IM12_Pos (12U)
1728#define EXTI_IMR_IM12_Msk (0x1U << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
1729#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
1730#define EXTI_IMR_IM13_Pos (13U)
1731#define EXTI_IMR_IM13_Msk (0x1U << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
1732#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
1733#define EXTI_IMR_IM14_Pos (14U)
1734#define EXTI_IMR_IM14_Msk (0x1U << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
1735#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
1736#define EXTI_IMR_IM15_Pos (15U)
1737#define EXTI_IMR_IM15_Msk (0x1U << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
1738#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
1739#define EXTI_IMR_IM16_Pos (16U)
1740#define EXTI_IMR_IM16_Msk (0x1U << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
1741#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
1742#define EXTI_IMR_IM17_Pos (17U)
1743#define EXTI_IMR_IM17_Msk (0x1U << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
1744#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
1745#define EXTI_IMR_IM18_Pos (18U)
1746#define EXTI_IMR_IM18_Msk (0x1U << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
1747#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
1748#define EXTI_IMR_IM19_Pos (19U)
1749#define EXTI_IMR_IM19_Msk (0x1U << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
1750#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
1751#define EXTI_IMR_IM20_Pos (20U)
1752#define EXTI_IMR_IM20_Msk (0x1U << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
1753#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
1754#define EXTI_IMR_IM21_Pos (21U)
1755#define EXTI_IMR_IM21_Msk (0x1U << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
1756#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
1757#define EXTI_IMR_IM22_Pos (22U)
1758#define EXTI_IMR_IM22_Msk (0x1U << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
1759#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
1760#define EXTI_IMR_IM23_Pos (23U)
1761#define EXTI_IMR_IM23_Msk (0x1U << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
1762#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
1763#define EXTI_IMR_IM25_Pos (25U)
1764#define EXTI_IMR_IM25_Msk (0x1U << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
1765#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
1766#define EXTI_IMR_IM26_Pos (26U)
1767#define EXTI_IMR_IM26_Msk (0x1U << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
1768#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
1769#define EXTI_IMR_IM28_Pos (28U)
1770#define EXTI_IMR_IM28_Msk (0x1U << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
1771#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
1772#define EXTI_IMR_IM29_Pos (29U)
1773#define EXTI_IMR_IM29_Msk (0x1U << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
1774#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
1775
1776#define EXTI_IMR_IM_Pos (0U)
1777#define EXTI_IMR_IM_Msk (0x36FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
1778#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
1779
1780/****************** Bit definition for EXTI_EMR register ********************/
1781#define EXTI_EMR_EM0_Pos (0U)
1782#define EXTI_EMR_EM0_Msk (0x1U << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
1783#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
1784#define EXTI_EMR_EM1_Pos (1U)
1785#define EXTI_EMR_EM1_Msk (0x1U << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
1786#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
1787#define EXTI_EMR_EM2_Pos (2U)
1788#define EXTI_EMR_EM2_Msk (0x1U << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
1789#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
1790#define EXTI_EMR_EM3_Pos (3U)
1791#define EXTI_EMR_EM3_Msk (0x1U << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
1792#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
1793#define EXTI_EMR_EM4_Pos (4U)
1794#define EXTI_EMR_EM4_Msk (0x1U << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
1795#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
1796#define EXTI_EMR_EM5_Pos (5U)
1797#define EXTI_EMR_EM5_Msk (0x1U << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
1798#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
1799#define EXTI_EMR_EM6_Pos (6U)
1800#define EXTI_EMR_EM6_Msk (0x1U << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
1801#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
1802#define EXTI_EMR_EM7_Pos (7U)
1803#define EXTI_EMR_EM7_Msk (0x1U << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
1804#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
1805#define EXTI_EMR_EM8_Pos (8U)
1806#define EXTI_EMR_EM8_Msk (0x1U << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
1807#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
1808#define EXTI_EMR_EM9_Pos (9U)
1809#define EXTI_EMR_EM9_Msk (0x1U << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
1810#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
1811#define EXTI_EMR_EM10_Pos (10U)
1812#define EXTI_EMR_EM10_Msk (0x1U << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
1813#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
1814#define EXTI_EMR_EM11_Pos (11U)
1815#define EXTI_EMR_EM11_Msk (0x1U << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
1816#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
1817#define EXTI_EMR_EM12_Pos (12U)
1818#define EXTI_EMR_EM12_Msk (0x1U << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
1819#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
1820#define EXTI_EMR_EM13_Pos (13U)
1821#define EXTI_EMR_EM13_Msk (0x1U << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
1822#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
1823#define EXTI_EMR_EM14_Pos (14U)
1824#define EXTI_EMR_EM14_Msk (0x1U << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
1825#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
1826#define EXTI_EMR_EM15_Pos (15U)
1827#define EXTI_EMR_EM15_Msk (0x1U << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
1828#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
1829#define EXTI_EMR_EM16_Pos (16U)
1830#define EXTI_EMR_EM16_Msk (0x1U << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
1831#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
1832#define EXTI_EMR_EM17_Pos (17U)
1833#define EXTI_EMR_EM17_Msk (0x1U << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
1834#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
1835#define EXTI_EMR_EM18_Pos (18U)
1836#define EXTI_EMR_EM18_Msk (0x1U << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
1837#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
1838#define EXTI_EMR_EM19_Pos (19U)
1839#define EXTI_EMR_EM19_Msk (0x1U << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
1840#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
1841#define EXTI_EMR_EM20_Pos (20U)
1842#define EXTI_EMR_EM20_Msk (0x1U << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
1843#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
1844#define EXTI_EMR_EM21_Pos (21U)
1845#define EXTI_EMR_EM21_Msk (0x1U << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
1846#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
1847#define EXTI_EMR_EM22_Pos (22U)
1848#define EXTI_EMR_EM22_Msk (0x1U << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
1849#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
1850#define EXTI_EMR_EM23_Pos (23U)
1851#define EXTI_EMR_EM23_Msk (0x1U << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
1852#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
1853#define EXTI_EMR_EM25_Pos (25U)
1854#define EXTI_EMR_EM25_Msk (0x1U << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
1855#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
1856#define EXTI_EMR_EM26_Pos (26U)
1857#define EXTI_EMR_EM26_Msk (0x1U << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
1858#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
1859#define EXTI_EMR_EM28_Pos (28U)
1860#define EXTI_EMR_EM28_Msk (0x1U << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
1861#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
1862#define EXTI_EMR_EM29_Pos (29U)
1863#define EXTI_EMR_EM29_Msk (0x1U << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
1864#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
1865
1866/******************* Bit definition for EXTI_RTSR register ******************/
1867#define EXTI_RTSR_RT0_Pos (0U)
1868#define EXTI_RTSR_RT0_Msk (0x1U << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
1869#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
1870#define EXTI_RTSR_RT1_Pos (1U)
1871#define EXTI_RTSR_RT1_Msk (0x1U << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
1872#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
1873#define EXTI_RTSR_RT2_Pos (2U)
1874#define EXTI_RTSR_RT2_Msk (0x1U << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
1875#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
1876#define EXTI_RTSR_RT3_Pos (3U)
1877#define EXTI_RTSR_RT3_Msk (0x1U << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
1878#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
1879#define EXTI_RTSR_RT4_Pos (4U)
1880#define EXTI_RTSR_RT4_Msk (0x1U << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
1881#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
1882#define EXTI_RTSR_RT5_Pos (5U)
1883#define EXTI_RTSR_RT5_Msk (0x1U << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
1884#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
1885#define EXTI_RTSR_RT6_Pos (6U)
1886#define EXTI_RTSR_RT6_Msk (0x1U << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
1887#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
1888#define EXTI_RTSR_RT7_Pos (7U)
1889#define EXTI_RTSR_RT7_Msk (0x1U << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
1890#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
1891#define EXTI_RTSR_RT8_Pos (8U)
1892#define EXTI_RTSR_RT8_Msk (0x1U << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
1893#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
1894#define EXTI_RTSR_RT9_Pos (9U)
1895#define EXTI_RTSR_RT9_Msk (0x1U << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
1896#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
1897#define EXTI_RTSR_RT10_Pos (10U)
1898#define EXTI_RTSR_RT10_Msk (0x1U << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
1899#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
1900#define EXTI_RTSR_RT11_Pos (11U)
1901#define EXTI_RTSR_RT11_Msk (0x1U << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
1902#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
1903#define EXTI_RTSR_RT12_Pos (12U)
1904#define EXTI_RTSR_RT12_Msk (0x1U << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
1905#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
1906#define EXTI_RTSR_RT13_Pos (13U)
1907#define EXTI_RTSR_RT13_Msk (0x1U << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
1908#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
1909#define EXTI_RTSR_RT14_Pos (14U)
1910#define EXTI_RTSR_RT14_Msk (0x1U << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
1911#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
1912#define EXTI_RTSR_RT15_Pos (15U)
1913#define EXTI_RTSR_RT15_Msk (0x1U << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
1914#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
1915#define EXTI_RTSR_RT16_Pos (16U)
1916#define EXTI_RTSR_RT16_Msk (0x1U << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
1917#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
1918#define EXTI_RTSR_RT17_Pos (17U)
1919#define EXTI_RTSR_RT17_Msk (0x1U << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
1920#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
1921#define EXTI_RTSR_RT19_Pos (19U)
1922#define EXTI_RTSR_RT19_Msk (0x1U << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
1923#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
1924#define EXTI_RTSR_RT20_Pos (20U)
1925#define EXTI_RTSR_RT20_Msk (0x1U << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
1926#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
1927#define EXTI_RTSR_RT21_Pos (21U)
1928#define EXTI_RTSR_RT21_Msk (0x1U << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
1929#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
1930#define EXTI_RTSR_RT22_Pos (22U)
1931#define EXTI_RTSR_RT22_Msk (0x1U << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
1932#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
1933
1934/* Legacy defines */
1935#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
1936#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
1937#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
1938#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
1939#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
1940#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
1941#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
1942#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
1943#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
1944#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
1945#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
1946#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
1947#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
1948#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
1949#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
1950#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
1951#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
1952#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
1953#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
1954#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
1955#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
1956#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
1957
1958/******************* Bit definition for EXTI_FTSR register *******************/
1959#define EXTI_FTSR_FT0_Pos (0U)
1960#define EXTI_FTSR_FT0_Msk (0x1U << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
1961#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
1962#define EXTI_FTSR_FT1_Pos (1U)
1963#define EXTI_FTSR_FT1_Msk (0x1U << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
1964#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
1965#define EXTI_FTSR_FT2_Pos (2U)
1966#define EXTI_FTSR_FT2_Msk (0x1U << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
1967#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
1968#define EXTI_FTSR_FT3_Pos (3U)
1969#define EXTI_FTSR_FT3_Msk (0x1U << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
1970#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
1971#define EXTI_FTSR_FT4_Pos (4U)
1972#define EXTI_FTSR_FT4_Msk (0x1U << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
1973#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
1974#define EXTI_FTSR_FT5_Pos (5U)
1975#define EXTI_FTSR_FT5_Msk (0x1U << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
1976#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
1977#define EXTI_FTSR_FT6_Pos (6U)
1978#define EXTI_FTSR_FT6_Msk (0x1U << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
1979#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
1980#define EXTI_FTSR_FT7_Pos (7U)
1981#define EXTI_FTSR_FT7_Msk (0x1U << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
1982#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
1983#define EXTI_FTSR_FT8_Pos (8U)
1984#define EXTI_FTSR_FT8_Msk (0x1U << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
1985#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
1986#define EXTI_FTSR_FT9_Pos (9U)
1987#define EXTI_FTSR_FT9_Msk (0x1U << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
1988#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
1989#define EXTI_FTSR_FT10_Pos (10U)
1990#define EXTI_FTSR_FT10_Msk (0x1U << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
1991#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
1992#define EXTI_FTSR_FT11_Pos (11U)
1993#define EXTI_FTSR_FT11_Msk (0x1U << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
1994#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
1995#define EXTI_FTSR_FT12_Pos (12U)
1996#define EXTI_FTSR_FT12_Msk (0x1U << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
1997#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
1998#define EXTI_FTSR_FT13_Pos (13U)
1999#define EXTI_FTSR_FT13_Msk (0x1U << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
2000#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
2001#define EXTI_FTSR_FT14_Pos (14U)
2002#define EXTI_FTSR_FT14_Msk (0x1U << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
2003#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
2004#define EXTI_FTSR_FT15_Pos (15U)
2005#define EXTI_FTSR_FT15_Msk (0x1U << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
2006#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
2007#define EXTI_FTSR_FT16_Pos (16U)
2008#define EXTI_FTSR_FT16_Msk (0x1U << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
2009#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
2010#define EXTI_FTSR_FT17_Pos (17U)
2011#define EXTI_FTSR_FT17_Msk (0x1U << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
2012#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
2013#define EXTI_FTSR_FT19_Pos (19U)
2014#define EXTI_FTSR_FT19_Msk (0x1U << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
2015#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
2016#define EXTI_FTSR_FT20_Pos (20U)
2017#define EXTI_FTSR_FT20_Msk (0x1U << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
2018#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
2019#define EXTI_FTSR_FT21_Pos (21U)
2020#define EXTI_FTSR_FT21_Msk (0x1U << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
2021#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
2022#define EXTI_FTSR_FT22_Pos (22U)
2023#define EXTI_FTSR_FT22_Msk (0x1U << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
2024#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
2025
2026/* Legacy defines */
2027#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
2028#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
2029#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
2030#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
2031#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
2032#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
2033#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
2034#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
2035#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
2036#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
2037#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
2038#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
2039#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
2040#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
2041#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
2042#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
2043#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
2044#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
2045#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
2046#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
2047#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
2048#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
2049
2050/******************* Bit definition for EXTI_SWIER register *******************/
2051#define EXTI_SWIER_SWI0_Pos (0U)
2052#define EXTI_SWIER_SWI0_Msk (0x1U << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
2053#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
2054#define EXTI_SWIER_SWI1_Pos (1U)
2055#define EXTI_SWIER_SWI1_Msk (0x1U << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
2056#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
2057#define EXTI_SWIER_SWI2_Pos (2U)
2058#define EXTI_SWIER_SWI2_Msk (0x1U << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
2059#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
2060#define EXTI_SWIER_SWI3_Pos (3U)
2061#define EXTI_SWIER_SWI3_Msk (0x1U << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
2062#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
2063#define EXTI_SWIER_SWI4_Pos (4U)
2064#define EXTI_SWIER_SWI4_Msk (0x1U << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
2065#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
2066#define EXTI_SWIER_SWI5_Pos (5U)
2067#define EXTI_SWIER_SWI5_Msk (0x1U << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
2068#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
2069#define EXTI_SWIER_SWI6_Pos (6U)
2070#define EXTI_SWIER_SWI6_Msk (0x1U << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
2071#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
2072#define EXTI_SWIER_SWI7_Pos (7U)
2073#define EXTI_SWIER_SWI7_Msk (0x1U << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
2074#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
2075#define EXTI_SWIER_SWI8_Pos (8U)
2076#define EXTI_SWIER_SWI8_Msk (0x1U << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
2077#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
2078#define EXTI_SWIER_SWI9_Pos (9U)
2079#define EXTI_SWIER_SWI9_Msk (0x1U << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
2080#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
2081#define EXTI_SWIER_SWI10_Pos (10U)
2082#define EXTI_SWIER_SWI10_Msk (0x1U << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
2083#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
2084#define EXTI_SWIER_SWI11_Pos (11U)
2085#define EXTI_SWIER_SWI11_Msk (0x1U << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
2086#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
2087#define EXTI_SWIER_SWI12_Pos (12U)
2088#define EXTI_SWIER_SWI12_Msk (0x1U << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
2089#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
2090#define EXTI_SWIER_SWI13_Pos (13U)
2091#define EXTI_SWIER_SWI13_Msk (0x1U << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
2092#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
2093#define EXTI_SWIER_SWI14_Pos (14U)
2094#define EXTI_SWIER_SWI14_Msk (0x1U << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
2095#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
2096#define EXTI_SWIER_SWI15_Pos (15U)
2097#define EXTI_SWIER_SWI15_Msk (0x1U << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
2098#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
2099#define EXTI_SWIER_SWI16_Pos (16U)
2100#define EXTI_SWIER_SWI16_Msk (0x1U << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
2101#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
2102#define EXTI_SWIER_SWI17_Pos (17U)
2103#define EXTI_SWIER_SWI17_Msk (0x1U << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
2104#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
2105#define EXTI_SWIER_SWI19_Pos (19U)
2106#define EXTI_SWIER_SWI19_Msk (0x1U << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
2107#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
2108#define EXTI_SWIER_SWI20_Pos (20U)
2109#define EXTI_SWIER_SWI20_Msk (0x1U << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
2110#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
2111#define EXTI_SWIER_SWI21_Pos (21U)
2112#define EXTI_SWIER_SWI21_Msk (0x1U << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
2113#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
2114#define EXTI_SWIER_SWI22_Pos (22U)
2115#define EXTI_SWIER_SWI22_Msk (0x1U << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
2116#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
2117
2118/* Legacy defines */
2119#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
2120#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
2121#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
2122#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
2123#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
2124#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
2125#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
2126#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
2127#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
2128#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
2129#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
2130#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
2131#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
2132#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
2133#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
2134#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
2135#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
2136#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
2137#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
2138#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
2139#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
2140#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
2141
2142/****************** Bit definition for EXTI_PR register *********************/
2143#define EXTI_PR_PIF0_Pos (0U)
2144#define EXTI_PR_PIF0_Msk (0x1U << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
2145#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
2146#define EXTI_PR_PIF1_Pos (1U)
2147#define EXTI_PR_PIF1_Msk (0x1U << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
2148#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
2149#define EXTI_PR_PIF2_Pos (2U)
2150#define EXTI_PR_PIF2_Msk (0x1U << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
2151#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
2152#define EXTI_PR_PIF3_Pos (3U)
2153#define EXTI_PR_PIF3_Msk (0x1U << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
2154#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
2155#define EXTI_PR_PIF4_Pos (4U)
2156#define EXTI_PR_PIF4_Msk (0x1U << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
2157#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
2158#define EXTI_PR_PIF5_Pos (5U)
2159#define EXTI_PR_PIF5_Msk (0x1U << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
2160#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
2161#define EXTI_PR_PIF6_Pos (6U)
2162#define EXTI_PR_PIF6_Msk (0x1U << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
2163#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
2164#define EXTI_PR_PIF7_Pos (7U)
2165#define EXTI_PR_PIF7_Msk (0x1U << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
2166#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
2167#define EXTI_PR_PIF8_Pos (8U)
2168#define EXTI_PR_PIF8_Msk (0x1U << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
2169#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
2170#define EXTI_PR_PIF9_Pos (9U)
2171#define EXTI_PR_PIF9_Msk (0x1U << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
2172#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
2173#define EXTI_PR_PIF10_Pos (10U)
2174#define EXTI_PR_PIF10_Msk (0x1U << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
2175#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
2176#define EXTI_PR_PIF11_Pos (11U)
2177#define EXTI_PR_PIF11_Msk (0x1U << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
2178#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
2179#define EXTI_PR_PIF12_Pos (12U)
2180#define EXTI_PR_PIF12_Msk (0x1U << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
2181#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
2182#define EXTI_PR_PIF13_Pos (13U)
2183#define EXTI_PR_PIF13_Msk (0x1U << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
2184#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
2185#define EXTI_PR_PIF14_Pos (14U)
2186#define EXTI_PR_PIF14_Msk (0x1U << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
2187#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
2188#define EXTI_PR_PIF15_Pos (15U)
2189#define EXTI_PR_PIF15_Msk (0x1U << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
2190#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
2191#define EXTI_PR_PIF16_Pos (16U)
2192#define EXTI_PR_PIF16_Msk (0x1U << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
2193#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
2194#define EXTI_PR_PIF17_Pos (17U)
2195#define EXTI_PR_PIF17_Msk (0x1U << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
2196#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
2197#define EXTI_PR_PIF19_Pos (19U)
2198#define EXTI_PR_PIF19_Msk (0x1U << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
2199#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
2200#define EXTI_PR_PIF20_Pos (20U)
2201#define EXTI_PR_PIF20_Msk (0x1U << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
2202#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
2203#define EXTI_PR_PIF21_Pos (21U)
2204#define EXTI_PR_PIF21_Msk (0x1U << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
2205#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
2206#define EXTI_PR_PIF22_Pos (22U)
2207#define EXTI_PR_PIF22_Msk (0x1U << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
2208#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
2209
2210/* Legacy defines */
2211#define EXTI_PR_PR0 EXTI_PR_PIF0
2212#define EXTI_PR_PR1 EXTI_PR_PIF1
2213#define EXTI_PR_PR2 EXTI_PR_PIF2
2214#define EXTI_PR_PR3 EXTI_PR_PIF3
2215#define EXTI_PR_PR4 EXTI_PR_PIF4
2216#define EXTI_PR_PR5 EXTI_PR_PIF5
2217#define EXTI_PR_PR6 EXTI_PR_PIF6
2218#define EXTI_PR_PR7 EXTI_PR_PIF7
2219#define EXTI_PR_PR8 EXTI_PR_PIF8
2220#define EXTI_PR_PR9 EXTI_PR_PIF9
2221#define EXTI_PR_PR10 EXTI_PR_PIF10
2222#define EXTI_PR_PR11 EXTI_PR_PIF11
2223#define EXTI_PR_PR12 EXTI_PR_PIF12
2224#define EXTI_PR_PR13 EXTI_PR_PIF13
2225#define EXTI_PR_PR14 EXTI_PR_PIF14
2226#define EXTI_PR_PR15 EXTI_PR_PIF15
2227#define EXTI_PR_PR16 EXTI_PR_PIF16
2228#define EXTI_PR_PR17 EXTI_PR_PIF17
2229#define EXTI_PR_PR19 EXTI_PR_PIF19
2230#define EXTI_PR_PR20 EXTI_PR_PIF20
2231#define EXTI_PR_PR21 EXTI_PR_PIF21
2232#define EXTI_PR_PR22 EXTI_PR_PIF22
2233
2234/******************************************************************************/
2235/* */
2236/* FLASH and Option Bytes Registers */
2237/* */
2238/******************************************************************************/
2239
2240/******************* Bit definition for FLASH_ACR register ******************/
2241#define FLASH_ACR_LATENCY_Pos (0U)
2242#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
2243#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
2244#define FLASH_ACR_PRFTEN_Pos (1U)
2245#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
2246#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
2247#define FLASH_ACR_SLEEP_PD_Pos (3U)
2248#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
2249#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
2250#define FLASH_ACR_RUN_PD_Pos (4U)
2251#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
2252#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
2253#define FLASH_ACR_DISAB_BUF_Pos (5U)
2254#define FLASH_ACR_DISAB_BUF_Msk (0x1U << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
2255#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
2256#define FLASH_ACR_PRE_READ_Pos (6U)
2257#define FLASH_ACR_PRE_READ_Msk (0x1U << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
2258#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
2259
2260/******************* Bit definition for FLASH_PECR register ******************/
2261#define FLASH_PECR_PELOCK_Pos (0U)
2262#define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
2263#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
2264#define FLASH_PECR_PRGLOCK_Pos (1U)
2265#define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
2266#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
2267#define FLASH_PECR_OPTLOCK_Pos (2U)
2268#define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
2269#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
2270#define FLASH_PECR_PROG_Pos (3U)
2271#define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
2272#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
2273#define FLASH_PECR_DATA_Pos (4U)
2274#define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
2275#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
2276#define FLASH_PECR_FIX_Pos (8U)
2277#define FLASH_PECR_FIX_Msk (0x1U << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
2278#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
2279#define FLASH_PECR_ERASE_Pos (9U)
2280#define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
2281#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
2282#define FLASH_PECR_FPRG_Pos (10U)
2283#define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
2284#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
2285#define FLASH_PECR_EOPIE_Pos (16U)
2286#define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
2287#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
2288#define FLASH_PECR_ERRIE_Pos (17U)
2289#define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
2290#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
2291#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
2292#define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
2293#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
2294#define FLASH_PECR_HALF_ARRAY_Pos (19U)
2295#define FLASH_PECR_HALF_ARRAY_Msk (0x1U << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
2296#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
2297
2298/****************** Bit definition for FLASH_PDKEYR register ******************/
2299#define FLASH_PDKEYR_PDKEYR_Pos (0U)
2300#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
2301#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
2302
2303/****************** Bit definition for FLASH_PEKEYR register ******************/
2304#define FLASH_PEKEYR_PEKEYR_Pos (0U)
2305#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
2306#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
2307
2308/****************** Bit definition for FLASH_PRGKEYR register ******************/
2309#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
2310#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
2311#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
2312
2313/****************** Bit definition for FLASH_OPTKEYR register ******************/
2314#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
2315#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
2316#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
2317
2318/****************** Bit definition for FLASH_SR register *******************/
2319#define FLASH_SR_BSY_Pos (0U)
2320#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
2321#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
2322#define FLASH_SR_EOP_Pos (1U)
2323#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
2324#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
2325#define FLASH_SR_HVOFF_Pos (2U)
2326#define FLASH_SR_HVOFF_Msk (0x1U << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
2327#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
2328#define FLASH_SR_READY_Pos (3U)
2329#define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */
2330#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
2331
2332#define FLASH_SR_WRPERR_Pos (8U)
2333#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
2334#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
2335#define FLASH_SR_PGAERR_Pos (9U)
2336#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
2337#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
2338#define FLASH_SR_SIZERR_Pos (10U)
2339#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
2340#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
2341#define FLASH_SR_OPTVERR_Pos (11U)
2342#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
2343#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
2344#define FLASH_SR_RDERR_Pos (13U)
2345#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
2346#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
2347#define FLASH_SR_NOTZEROERR_Pos (16U)
2348#define FLASH_SR_NOTZEROERR_Msk (0x1U << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
2349#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
2350#define FLASH_SR_FWWERR_Pos (17U)
2351#define FLASH_SR_FWWERR_Msk (0x1U << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
2352#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
2353
2354/* Legacy defines */
2355#define FLASH_SR_FWWER FLASH_SR_FWWERR
2356#define FLASH_SR_ENHV FLASH_SR_HVOFF
2357#define FLASH_SR_ENDHV FLASH_SR_HVOFF
2358
2359/****************** Bit definition for FLASH_OPTR register *******************/
2360#define FLASH_OPTR_RDPROT_Pos (0U)
2361#define FLASH_OPTR_RDPROT_Msk (0xFFU << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
2362#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
2363#define FLASH_OPTR_WPRMOD_Pos (8U)
2364#define FLASH_OPTR_WPRMOD_Msk (0x1U << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
2365#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
2366#define FLASH_OPTR_BOR_LEV_Pos (16U)
2367#define FLASH_OPTR_BOR_LEV_Msk (0xFU << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
2368#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
2369#define FLASH_OPTR_IWDG_SW_Pos (20U)
2370#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
2371#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
2372#define FLASH_OPTR_nRST_STOP_Pos (21U)
2373#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
2374#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
2375#define FLASH_OPTR_nRST_STDBY_Pos (22U)
2376#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
2377#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
2378#define FLASH_OPTR_USER_Pos (20U)
2379#define FLASH_OPTR_USER_Msk (0x7U << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
2380#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
2381#define FLASH_OPTR_BOOT1_Pos (31U)
2382#define FLASH_OPTR_BOOT1_Msk (0x1U << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
2383#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
2384
2385/****************** Bit definition for FLASH_WRPR register ******************/
2386#define FLASH_WRPR_WRP_Pos (0U)
2387#define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
2388#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
2389
2390/******************************************************************************/
2391/* */
2392/* General Purpose IOs (GPIO) */
2393/* */
2394/******************************************************************************/
2395/******************* Bit definition for GPIO_MODER register *****************/
2396#define GPIO_MODER_MODE0_Pos (0U)
2397#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
2398#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
2399#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
2400#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
2401#define GPIO_MODER_MODE1_Pos (2U)
2402#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
2403#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
2404#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
2405#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
2406#define GPIO_MODER_MODE2_Pos (4U)
2407#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
2408#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
2409#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
2410#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
2411#define GPIO_MODER_MODE3_Pos (6U)
2412#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
2413#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
2414#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
2415#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
2416#define GPIO_MODER_MODE4_Pos (8U)
2417#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
2418#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
2419#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
2420#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
2421#define GPIO_MODER_MODE5_Pos (10U)
2422#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
2423#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
2424#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
2425#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
2426#define GPIO_MODER_MODE6_Pos (12U)
2427#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
2428#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
2429#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
2430#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
2431#define GPIO_MODER_MODE7_Pos (14U)
2432#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
2433#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
2434#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
2435#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
2436#define GPIO_MODER_MODE8_Pos (16U)
2437#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
2438#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
2439#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
2440#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
2441#define GPIO_MODER_MODE9_Pos (18U)
2442#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
2443#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
2444#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
2445#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
2446#define GPIO_MODER_MODE10_Pos (20U)
2447#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
2448#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
2449#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
2450#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
2451#define GPIO_MODER_MODE11_Pos (22U)
2452#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
2453#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
2454#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
2455#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
2456#define GPIO_MODER_MODE12_Pos (24U)
2457#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
2458#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
2459#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
2460#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
2461#define GPIO_MODER_MODE13_Pos (26U)
2462#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
2463#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
2464#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
2465#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
2466#define GPIO_MODER_MODE14_Pos (28U)
2467#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
2468#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
2469#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
2470#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
2471#define GPIO_MODER_MODE15_Pos (30U)
2472#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
2473#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
2474#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
2475#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
2476
2477/****************** Bit definition for GPIO_OTYPER register *****************/
2478#define GPIO_OTYPER_OT_0 (0x00000001U)
2479#define GPIO_OTYPER_OT_1 (0x00000002U)
2480#define GPIO_OTYPER_OT_2 (0x00000004U)
2481#define GPIO_OTYPER_OT_3 (0x00000008U)
2482#define GPIO_OTYPER_OT_4 (0x00000010U)
2483#define GPIO_OTYPER_OT_5 (0x00000020U)
2484#define GPIO_OTYPER_OT_6 (0x00000040U)
2485#define GPIO_OTYPER_OT_7 (0x00000080U)
2486#define GPIO_OTYPER_OT_8 (0x00000100U)
2487#define GPIO_OTYPER_OT_9 (0x00000200U)
2488#define GPIO_OTYPER_OT_10 (0x00000400U)
2489#define GPIO_OTYPER_OT_11 (0x00000800U)
2490#define GPIO_OTYPER_OT_12 (0x00001000U)
2491#define GPIO_OTYPER_OT_13 (0x00002000U)
2492#define GPIO_OTYPER_OT_14 (0x00004000U)
2493#define GPIO_OTYPER_OT_15 (0x00008000U)
2494
2495/**************** Bit definition for GPIO_OSPEEDR register ******************/
2496#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
2497#define GPIO_OSPEEDER_OSPEED0_Msk (0x3U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
2498#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
2499#define GPIO_OSPEEDER_OSPEED0_0 (0x1U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
2500#define GPIO_OSPEEDER_OSPEED0_1 (0x2U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
2501#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
2502#define GPIO_OSPEEDER_OSPEED1_Msk (0x3U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
2503#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
2504#define GPIO_OSPEEDER_OSPEED1_0 (0x1U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
2505#define GPIO_OSPEEDER_OSPEED1_1 (0x2U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
2506#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
2507#define GPIO_OSPEEDER_OSPEED2_Msk (0x3U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
2508#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
2509#define GPIO_OSPEEDER_OSPEED2_0 (0x1U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
2510#define GPIO_OSPEEDER_OSPEED2_1 (0x2U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
2511#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
2512#define GPIO_OSPEEDER_OSPEED3_Msk (0x3U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
2513#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
2514#define GPIO_OSPEEDER_OSPEED3_0 (0x1U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
2515#define GPIO_OSPEEDER_OSPEED3_1 (0x2U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
2516#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
2517#define GPIO_OSPEEDER_OSPEED4_Msk (0x3U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
2518#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
2519#define GPIO_OSPEEDER_OSPEED4_0 (0x1U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
2520#define GPIO_OSPEEDER_OSPEED4_1 (0x2U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
2521#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
2522#define GPIO_OSPEEDER_OSPEED5_Msk (0x3U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
2523#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
2524#define GPIO_OSPEEDER_OSPEED5_0 (0x1U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
2525#define GPIO_OSPEEDER_OSPEED5_1 (0x2U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
2526#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
2527#define GPIO_OSPEEDER_OSPEED6_Msk (0x3U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
2528#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
2529#define GPIO_OSPEEDER_OSPEED6_0 (0x1U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
2530#define GPIO_OSPEEDER_OSPEED6_1 (0x2U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
2531#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
2532#define GPIO_OSPEEDER_OSPEED7_Msk (0x3U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
2533#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
2534#define GPIO_OSPEEDER_OSPEED7_0 (0x1U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
2535#define GPIO_OSPEEDER_OSPEED7_1 (0x2U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
2536#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
2537#define GPIO_OSPEEDER_OSPEED8_Msk (0x3U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
2538#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
2539#define GPIO_OSPEEDER_OSPEED8_0 (0x1U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
2540#define GPIO_OSPEEDER_OSPEED8_1 (0x2U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
2541#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
2542#define GPIO_OSPEEDER_OSPEED9_Msk (0x3U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
2543#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
2544#define GPIO_OSPEEDER_OSPEED9_0 (0x1U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
2545#define GPIO_OSPEEDER_OSPEED9_1 (0x2U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
2546#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
2547#define GPIO_OSPEEDER_OSPEED10_Msk (0x3U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
2548#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
2549#define GPIO_OSPEEDER_OSPEED10_0 (0x1U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
2550#define GPIO_OSPEEDER_OSPEED10_1 (0x2U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
2551#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
2552#define GPIO_OSPEEDER_OSPEED11_Msk (0x3U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
2553#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
2554#define GPIO_OSPEEDER_OSPEED11_0 (0x1U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
2555#define GPIO_OSPEEDER_OSPEED11_1 (0x2U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
2556#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
2557#define GPIO_OSPEEDER_OSPEED12_Msk (0x3U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
2558#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
2559#define GPIO_OSPEEDER_OSPEED12_0 (0x1U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
2560#define GPIO_OSPEEDER_OSPEED12_1 (0x2U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
2561#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
2562#define GPIO_OSPEEDER_OSPEED13_Msk (0x3U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
2563#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
2564#define GPIO_OSPEEDER_OSPEED13_0 (0x1U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
2565#define GPIO_OSPEEDER_OSPEED13_1 (0x2U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
2566#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
2567#define GPIO_OSPEEDER_OSPEED14_Msk (0x3U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
2568#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
2569#define GPIO_OSPEEDER_OSPEED14_0 (0x1U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
2570#define GPIO_OSPEEDER_OSPEED14_1 (0x2U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
2571#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
2572#define GPIO_OSPEEDER_OSPEED15_Msk (0x3U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
2573#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
2574#define GPIO_OSPEEDER_OSPEED15_0 (0x1U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
2575#define GPIO_OSPEEDER_OSPEED15_1 (0x2U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
2576
2577/******************* Bit definition for GPIO_PUPDR register ******************/
2578#define GPIO_PUPDR_PUPD0_Pos (0U)
2579#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
2580#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
2581#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
2582#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
2583#define GPIO_PUPDR_PUPD1_Pos (2U)
2584#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
2585#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
2586#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
2587#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
2588#define GPIO_PUPDR_PUPD2_Pos (4U)
2589#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
2590#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
2591#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
2592#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
2593#define GPIO_PUPDR_PUPD3_Pos (6U)
2594#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
2595#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
2596#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
2597#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
2598#define GPIO_PUPDR_PUPD4_Pos (8U)
2599#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
2600#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
2601#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
2602#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
2603#define GPIO_PUPDR_PUPD5_Pos (10U)
2604#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
2605#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
2606#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
2607#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
2608#define GPIO_PUPDR_PUPD6_Pos (12U)
2609#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
2610#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
2611#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
2612#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
2613#define GPIO_PUPDR_PUPD7_Pos (14U)
2614#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
2615#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
2616#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
2617#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
2618#define GPIO_PUPDR_PUPD8_Pos (16U)
2619#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
2620#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
2621#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
2622#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
2623#define GPIO_PUPDR_PUPD9_Pos (18U)
2624#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
2625#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
2626#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
2627#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
2628#define GPIO_PUPDR_PUPD10_Pos (20U)
2629#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
2630#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
2631#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
2632#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
2633#define GPIO_PUPDR_PUPD11_Pos (22U)
2634#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
2635#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
2636#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
2637#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
2638#define GPIO_PUPDR_PUPD12_Pos (24U)
2639#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
2640#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
2641#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
2642#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
2643#define GPIO_PUPDR_PUPD13_Pos (26U)
2644#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
2645#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
2646#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
2647#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
2648#define GPIO_PUPDR_PUPD14_Pos (28U)
2649#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
2650#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
2651#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
2652#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
2653#define GPIO_PUPDR_PUPD15_Pos (30U)
2654#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
2655#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
2656#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
2657#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
2658
2659/******************* Bit definition for GPIO_IDR register *******************/
2660#define GPIO_IDR_ID0_Pos (0U)
2661#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
2662#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
2663#define GPIO_IDR_ID1_Pos (1U)
2664#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
2665#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
2666#define GPIO_IDR_ID2_Pos (2U)
2667#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
2668#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
2669#define GPIO_IDR_ID3_Pos (3U)
2670#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
2671#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
2672#define GPIO_IDR_ID4_Pos (4U)
2673#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
2674#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
2675#define GPIO_IDR_ID5_Pos (5U)
2676#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
2677#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
2678#define GPIO_IDR_ID6_Pos (6U)
2679#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
2680#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
2681#define GPIO_IDR_ID7_Pos (7U)
2682#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
2683#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
2684#define GPIO_IDR_ID8_Pos (8U)
2685#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
2686#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
2687#define GPIO_IDR_ID9_Pos (9U)
2688#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
2689#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
2690#define GPIO_IDR_ID10_Pos (10U)
2691#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
2692#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
2693#define GPIO_IDR_ID11_Pos (11U)
2694#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
2695#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
2696#define GPIO_IDR_ID12_Pos (12U)
2697#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
2698#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
2699#define GPIO_IDR_ID13_Pos (13U)
2700#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
2701#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
2702#define GPIO_IDR_ID14_Pos (14U)
2703#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
2704#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
2705#define GPIO_IDR_ID15_Pos (15U)
2706#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
2707#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
2708
2709/****************** Bit definition for GPIO_ODR register ********************/
2710#define GPIO_ODR_OD0_Pos (0U)
2711#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
2712#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
2713#define GPIO_ODR_OD1_Pos (1U)
2714#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
2715#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
2716#define GPIO_ODR_OD2_Pos (2U)
2717#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
2718#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
2719#define GPIO_ODR_OD3_Pos (3U)
2720#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
2721#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
2722#define GPIO_ODR_OD4_Pos (4U)
2723#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
2724#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
2725#define GPIO_ODR_OD5_Pos (5U)
2726#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
2727#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
2728#define GPIO_ODR_OD6_Pos (6U)
2729#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
2730#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
2731#define GPIO_ODR_OD7_Pos (7U)
2732#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
2733#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
2734#define GPIO_ODR_OD8_Pos (8U)
2735#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
2736#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
2737#define GPIO_ODR_OD9_Pos (9U)
2738#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
2739#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
2740#define GPIO_ODR_OD10_Pos (10U)
2741#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
2742#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
2743#define GPIO_ODR_OD11_Pos (11U)
2744#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
2745#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
2746#define GPIO_ODR_OD12_Pos (12U)
2747#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
2748#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
2749#define GPIO_ODR_OD13_Pos (13U)
2750#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
2751#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
2752#define GPIO_ODR_OD14_Pos (14U)
2753#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
2754#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
2755#define GPIO_ODR_OD15_Pos (15U)
2756#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
2757#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
2758
2759/****************** Bit definition for GPIO_BSRR register ********************/
2760#define GPIO_BSRR_BS_0 (0x00000001U)
2761#define GPIO_BSRR_BS_1 (0x00000002U)
2762#define GPIO_BSRR_BS_2 (0x00000004U)
2763#define GPIO_BSRR_BS_3 (0x00000008U)
2764#define GPIO_BSRR_BS_4 (0x00000010U)
2765#define GPIO_BSRR_BS_5 (0x00000020U)
2766#define GPIO_BSRR_BS_6 (0x00000040U)
2767#define GPIO_BSRR_BS_7 (0x00000080U)
2768#define GPIO_BSRR_BS_8 (0x00000100U)
2769#define GPIO_BSRR_BS_9 (0x00000200U)
2770#define GPIO_BSRR_BS_10 (0x00000400U)
2771#define GPIO_BSRR_BS_11 (0x00000800U)
2772#define GPIO_BSRR_BS_12 (0x00001000U)
2773#define GPIO_BSRR_BS_13 (0x00002000U)
2774#define GPIO_BSRR_BS_14 (0x00004000U)
2775#define GPIO_BSRR_BS_15 (0x00008000U)
2776#define GPIO_BSRR_BR_0 (0x00010000U)
2777#define GPIO_BSRR_BR_1 (0x00020000U)
2778#define GPIO_BSRR_BR_2 (0x00040000U)
2779#define GPIO_BSRR_BR_3 (0x00080000U)
2780#define GPIO_BSRR_BR_4 (0x00100000U)
2781#define GPIO_BSRR_BR_5 (0x00200000U)
2782#define GPIO_BSRR_BR_6 (0x00400000U)
2783#define GPIO_BSRR_BR_7 (0x00800000U)
2784#define GPIO_BSRR_BR_8 (0x01000000U)
2785#define GPIO_BSRR_BR_9 (0x02000000U)
2786#define GPIO_BSRR_BR_10 (0x04000000U)
2787#define GPIO_BSRR_BR_11 (0x08000000U)
2788#define GPIO_BSRR_BR_12 (0x10000000U)
2789#define GPIO_BSRR_BR_13 (0x20000000U)
2790#define GPIO_BSRR_BR_14 (0x40000000U)
2791#define GPIO_BSRR_BR_15 (0x80000000U)
2792
2793/****************** Bit definition for GPIO_LCKR register ********************/
2794#define GPIO_LCKR_LCK0_Pos (0U)
2795#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
2796#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
2797#define GPIO_LCKR_LCK1_Pos (1U)
2798#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
2799#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
2800#define GPIO_LCKR_LCK2_Pos (2U)
2801#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
2802#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
2803#define GPIO_LCKR_LCK3_Pos (3U)
2804#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
2805#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
2806#define GPIO_LCKR_LCK4_Pos (4U)
2807#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
2808#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
2809#define GPIO_LCKR_LCK5_Pos (5U)
2810#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
2811#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
2812#define GPIO_LCKR_LCK6_Pos (6U)
2813#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
2814#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
2815#define GPIO_LCKR_LCK7_Pos (7U)
2816#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
2817#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
2818#define GPIO_LCKR_LCK8_Pos (8U)
2819#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
2820#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
2821#define GPIO_LCKR_LCK9_Pos (9U)
2822#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
2823#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
2824#define GPIO_LCKR_LCK10_Pos (10U)
2825#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
2826#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
2827#define GPIO_LCKR_LCK11_Pos (11U)
2828#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
2829#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
2830#define GPIO_LCKR_LCK12_Pos (12U)
2831#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
2832#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
2833#define GPIO_LCKR_LCK13_Pos (13U)
2834#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
2835#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
2836#define GPIO_LCKR_LCK14_Pos (14U)
2837#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
2838#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
2839#define GPIO_LCKR_LCK15_Pos (15U)
2840#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
2841#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
2842#define GPIO_LCKR_LCKK_Pos (16U)
2843#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
2844#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
2845
2846/****************** Bit definition for GPIO_AFRL register ********************/
2847#define GPIO_AFRL_AFRL0_Pos (0U)
2848#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
2849#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
2850#define GPIO_AFRL_AFRL1_Pos (4U)
2851#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
2852#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
2853#define GPIO_AFRL_AFRL2_Pos (8U)
2854#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
2855#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
2856#define GPIO_AFRL_AFRL3_Pos (12U)
2857#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
2858#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
2859#define GPIO_AFRL_AFRL4_Pos (16U)
2860#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
2861#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
2862#define GPIO_AFRL_AFRL5_Pos (20U)
2863#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
2864#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
2865#define GPIO_AFRL_AFRL6_Pos (24U)
2866#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
2867#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
2868#define GPIO_AFRL_AFRL7_Pos (28U)
2869#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
2870#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
2871
2872/****************** Bit definition for GPIO_AFRH register ********************/
2873#define GPIO_AFRH_AFRH0_Pos (0U)
2874#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
2875#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
2876#define GPIO_AFRH_AFRH1_Pos (4U)
2877#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
2878#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
2879#define GPIO_AFRH_AFRH2_Pos (8U)
2880#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
2881#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
2882#define GPIO_AFRH_AFRH3_Pos (12U)
2883#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
2884#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
2885#define GPIO_AFRH_AFRH4_Pos (16U)
2886#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
2887#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
2888#define GPIO_AFRH_AFRH5_Pos (20U)
2889#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
2890#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
2891#define GPIO_AFRH_AFRH6_Pos (24U)
2892#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
2893#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
2894#define GPIO_AFRH_AFRH7_Pos (28U)
2895#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
2896#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
2897
2898/****************** Bit definition for GPIO_BRR register *********************/
2899#define GPIO_BRR_BR_0 (0x00000001U)
2900#define GPIO_BRR_BR_1 (0x00000002U)
2901#define GPIO_BRR_BR_2 (0x00000004U)
2902#define GPIO_BRR_BR_3 (0x00000008U)
2903#define GPIO_BRR_BR_4 (0x00000010U)
2904#define GPIO_BRR_BR_5 (0x00000020U)
2905#define GPIO_BRR_BR_6 (0x00000040U)
2906#define GPIO_BRR_BR_7 (0x00000080U)
2907#define GPIO_BRR_BR_8 (0x00000100U)
2908#define GPIO_BRR_BR_9 (0x00000200U)
2909#define GPIO_BRR_BR_10 (0x00000400U)
2910#define GPIO_BRR_BR_11 (0x00000800U)
2911#define GPIO_BRR_BR_12 (0x00001000U)
2912#define GPIO_BRR_BR_13 (0x00002000U)
2913#define GPIO_BRR_BR_14 (0x00004000U)
2914#define GPIO_BRR_BR_15 (0x00008000U)
2915
2916/******************************************************************************/
2917/* */
2918/* Inter-integrated Circuit Interface (I2C) */
2919/* */
2920/******************************************************************************/
2921
2922/******************* Bit definition for I2C_CR1 register *******************/
2923#define I2C_CR1_PE_Pos (0U)
2924#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
2925#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
2926#define I2C_CR1_TXIE_Pos (1U)
2927#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
2928#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
2929#define I2C_CR1_RXIE_Pos (2U)
2930#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
2931#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
2932#define I2C_CR1_ADDRIE_Pos (3U)
2933#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
2934#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
2935#define I2C_CR1_NACKIE_Pos (4U)
2936#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
2937#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
2938#define I2C_CR1_STOPIE_Pos (5U)
2939#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
2940#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
2941#define I2C_CR1_TCIE_Pos (6U)
2942#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
2943#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
2944#define I2C_CR1_ERRIE_Pos (7U)
2945#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
2946#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
2947#define I2C_CR1_DNF_Pos (8U)
2948#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
2949#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
2950#define I2C_CR1_ANFOFF_Pos (12U)
2951#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
2952#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
2953#define I2C_CR1_TXDMAEN_Pos (14U)
2954#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
2955#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
2956#define I2C_CR1_RXDMAEN_Pos (15U)
2957#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
2958#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
2959#define I2C_CR1_SBC_Pos (16U)
2960#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
2961#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
2962#define I2C_CR1_NOSTRETCH_Pos (17U)
2963#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
2964#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
2965#define I2C_CR1_WUPEN_Pos (18U)
2966#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
2967#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
2968#define I2C_CR1_GCEN_Pos (19U)
2969#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
2970#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
2971#define I2C_CR1_SMBHEN_Pos (20U)
2972#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
2973#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
2974#define I2C_CR1_SMBDEN_Pos (21U)
2975#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
2976#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
2977#define I2C_CR1_ALERTEN_Pos (22U)
2978#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
2979#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
2980#define I2C_CR1_PECEN_Pos (23U)
2981#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
2982#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
2983
2984/****************** Bit definition for I2C_CR2 register ********************/
2985#define I2C_CR2_SADD_Pos (0U)
2986#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
2987#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
2988#define I2C_CR2_RD_WRN_Pos (10U)
2989#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
2990#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
2991#define I2C_CR2_ADD10_Pos (11U)
2992#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
2993#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
2994#define I2C_CR2_HEAD10R_Pos (12U)
2995#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
2996#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
2997#define I2C_CR2_START_Pos (13U)
2998#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
2999#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
3000#define I2C_CR2_STOP_Pos (14U)
3001#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
3002#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
3003#define I2C_CR2_NACK_Pos (15U)
3004#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
3005#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
3006#define I2C_CR2_NBYTES_Pos (16U)
3007#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
3008#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
3009#define I2C_CR2_RELOAD_Pos (24U)
3010#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
3011#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
3012#define I2C_CR2_AUTOEND_Pos (25U)
3013#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
3014#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
3015#define I2C_CR2_PECBYTE_Pos (26U)
3016#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
3017#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
3018
3019/******************* Bit definition for I2C_OAR1 register ******************/
3020#define I2C_OAR1_OA1_Pos (0U)
3021#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
3022#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
3023#define I2C_OAR1_OA1MODE_Pos (10U)
3024#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
3025#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
3026#define I2C_OAR1_OA1EN_Pos (15U)
3027#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
3028#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
3029
3030/******************* Bit definition for I2C_OAR2 register ******************/
3031#define I2C_OAR2_OA2_Pos (1U)
3032#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
3033#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
3034#define I2C_OAR2_OA2MSK_Pos (8U)
3035#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
3036#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
3037#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
3038#define I2C_OAR2_OA2MASK01_Pos (8U)
3039#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
3040#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
3041#define I2C_OAR2_OA2MASK02_Pos (9U)
3042#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
3043#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
3044#define I2C_OAR2_OA2MASK03_Pos (8U)
3045#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
3046#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
3047#define I2C_OAR2_OA2MASK04_Pos (10U)
3048#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
3049#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
3050#define I2C_OAR2_OA2MASK05_Pos (8U)
3051#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
3052#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
3053#define I2C_OAR2_OA2MASK06_Pos (9U)
3054#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
3055#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
3056#define I2C_OAR2_OA2MASK07_Pos (8U)
3057#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
3058#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
3059#define I2C_OAR2_OA2EN_Pos (15U)
3060#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
3061#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
3062
3063/******************* Bit definition for I2C_TIMINGR register *******************/
3064#define I2C_TIMINGR_SCLL_Pos (0U)
3065#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
3066#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
3067#define I2C_TIMINGR_SCLH_Pos (8U)
3068#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
3069#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
3070#define I2C_TIMINGR_SDADEL_Pos (16U)
3071#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
3072#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
3073#define I2C_TIMINGR_SCLDEL_Pos (20U)
3074#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
3075#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
3076#define I2C_TIMINGR_PRESC_Pos (28U)
3077#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
3078#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
3079
3080/******************* Bit definition for I2C_TIMEOUTR register *******************/
3081#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
3082#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
3083#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
3084#define I2C_TIMEOUTR_TIDLE_Pos (12U)
3085#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
3086#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
3087#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
3088#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
3089#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
3090#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
3091#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
3092#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
3093#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
3094#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
3095#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
3096
3097/****************** Bit definition for I2C_ISR register *********************/
3098#define I2C_ISR_TXE_Pos (0U)
3099#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
3100#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
3101#define I2C_ISR_TXIS_Pos (1U)
3102#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
3103#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
3104#define I2C_ISR_RXNE_Pos (2U)
3105#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
3106#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
3107#define I2C_ISR_ADDR_Pos (3U)
3108#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
3109#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
3110#define I2C_ISR_NACKF_Pos (4U)
3111#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
3112#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
3113#define I2C_ISR_STOPF_Pos (5U)
3114#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
3115#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
3116#define I2C_ISR_TC_Pos (6U)
3117#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
3118#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
3119#define I2C_ISR_TCR_Pos (7U)
3120#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
3121#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
3122#define I2C_ISR_BERR_Pos (8U)
3123#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
3124#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
3125#define I2C_ISR_ARLO_Pos (9U)
3126#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
3127#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
3128#define I2C_ISR_OVR_Pos (10U)
3129#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
3130#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
3131#define I2C_ISR_PECERR_Pos (11U)
3132#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
3133#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
3134#define I2C_ISR_TIMEOUT_Pos (12U)
3135#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
3136#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
3137#define I2C_ISR_ALERT_Pos (13U)
3138#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
3139#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
3140#define I2C_ISR_BUSY_Pos (15U)
3141#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
3142#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
3143#define I2C_ISR_DIR_Pos (16U)
3144#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
3145#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
3146#define I2C_ISR_ADDCODE_Pos (17U)
3147#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
3148#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
3149
3150/****************** Bit definition for I2C_ICR register *********************/
3151#define I2C_ICR_ADDRCF_Pos (3U)
3152#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
3153#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
3154#define I2C_ICR_NACKCF_Pos (4U)
3155#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
3156#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
3157#define I2C_ICR_STOPCF_Pos (5U)
3158#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
3159#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
3160#define I2C_ICR_BERRCF_Pos (8U)
3161#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
3162#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
3163#define I2C_ICR_ARLOCF_Pos (9U)
3164#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
3165#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
3166#define I2C_ICR_OVRCF_Pos (10U)
3167#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
3168#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
3169#define I2C_ICR_PECCF_Pos (11U)
3170#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
3171#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
3172#define I2C_ICR_TIMOUTCF_Pos (12U)
3173#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
3174#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
3175#define I2C_ICR_ALERTCF_Pos (13U)
3176#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
3177#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
3178
3179/****************** Bit definition for I2C_PECR register *********************/
3180#define I2C_PECR_PEC_Pos (0U)
3181#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
3182#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
3183
3184/****************** Bit definition for I2C_RXDR register *********************/
3185#define I2C_RXDR_RXDATA_Pos (0U)
3186#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
3187#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
3188
3189/****************** Bit definition for I2C_TXDR register *********************/
3190#define I2C_TXDR_TXDATA_Pos (0U)
3191#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
3192#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
3193
3194/******************************************************************************/
3195/* */
3196/* Independent WATCHDOG (IWDG) */
3197/* */
3198/******************************************************************************/
3199/******************* Bit definition for IWDG_KR register ********************/
3200#define IWDG_KR_KEY_Pos (0U)
3201#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
3202#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
3203
3204/******************* Bit definition for IWDG_PR register ********************/
3205#define IWDG_PR_PR_Pos (0U)
3206#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
3207#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
3208#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
3209#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
3210#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
3211
3212/******************* Bit definition for IWDG_RLR register *******************/
3213#define IWDG_RLR_RL_Pos (0U)
3214#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
3215#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
3216
3217/******************* Bit definition for IWDG_SR register ********************/
3218#define IWDG_SR_PVU_Pos (0U)
3219#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
3220#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
3221#define IWDG_SR_RVU_Pos (1U)
3222#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
3223#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
3224#define IWDG_SR_WVU_Pos (2U)
3225#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
3226#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
3227
3228/******************* Bit definition for IWDG_KR register ********************/
3229#define IWDG_WINR_WIN_Pos (0U)
3230#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
3231#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
3232
3233/******************************************************************************/
3234/* */
3235/* Low Power Timer (LPTTIM) */
3236/* */
3237/******************************************************************************/
3238/****************** Bit definition for LPTIM_ISR register *******************/
3239#define LPTIM_ISR_CMPM_Pos (0U)
3240#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
3241#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
3242#define LPTIM_ISR_ARRM_Pos (1U)
3243#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
3244#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
3245#define LPTIM_ISR_EXTTRIG_Pos (2U)
3246#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
3247#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
3248#define LPTIM_ISR_CMPOK_Pos (3U)
3249#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
3250#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
3251#define LPTIM_ISR_ARROK_Pos (4U)
3252#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
3253#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
3254#define LPTIM_ISR_UP_Pos (5U)
3255#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
3256#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
3257#define LPTIM_ISR_DOWN_Pos (6U)
3258#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
3259#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
3260
3261/****************** Bit definition for LPTIM_ICR register *******************/
3262#define LPTIM_ICR_CMPMCF_Pos (0U)
3263#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
3264#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
3265#define LPTIM_ICR_ARRMCF_Pos (1U)
3266#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
3267#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
3268#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
3269#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
3270#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
3271#define LPTIM_ICR_CMPOKCF_Pos (3U)
3272#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
3273#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
3274#define LPTIM_ICR_ARROKCF_Pos (4U)
3275#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
3276#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
3277#define LPTIM_ICR_UPCF_Pos (5U)
3278#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
3279#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
3280#define LPTIM_ICR_DOWNCF_Pos (6U)
3281#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
3282#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
3283
3284/****************** Bit definition for LPTIM_IER register ********************/
3285#define LPTIM_IER_CMPMIE_Pos (0U)
3286#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
3287#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
3288#define LPTIM_IER_ARRMIE_Pos (1U)
3289#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
3290#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
3291#define LPTIM_IER_EXTTRIGIE_Pos (2U)
3292#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
3293#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
3294#define LPTIM_IER_CMPOKIE_Pos (3U)
3295#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
3296#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
3297#define LPTIM_IER_ARROKIE_Pos (4U)
3298#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
3299#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
3300#define LPTIM_IER_UPIE_Pos (5U)
3301#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
3302#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
3303#define LPTIM_IER_DOWNIE_Pos (6U)
3304#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
3305#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
3306
3307/****************** Bit definition for LPTIM_CFGR register *******************/
3308#define LPTIM_CFGR_CKSEL_Pos (0U)
3309#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
3310#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
3311
3312#define LPTIM_CFGR_CKPOL_Pos (1U)
3313#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
3314#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
3315#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
3316#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
3317
3318#define LPTIM_CFGR_CKFLT_Pos (3U)
3319#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
3320#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
3321#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
3322#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
3323
3324#define LPTIM_CFGR_TRGFLT_Pos (6U)
3325#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
3326#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
3327#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
3328#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
3329
3330#define LPTIM_CFGR_PRESC_Pos (9U)
3331#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
3332#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
3333#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
3334#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
3335#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
3336
3337#define LPTIM_CFGR_TRIGSEL_Pos (13U)
3338#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
3339#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
3340#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
3341#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
3342#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
3343
3344#define LPTIM_CFGR_TRIGEN_Pos (17U)
3345#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
3346#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
3347#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
3348#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
3349
3350#define LPTIM_CFGR_TIMOUT_Pos (19U)
3351#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
3352#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
3353#define LPTIM_CFGR_WAVE_Pos (20U)
3354#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
3355#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
3356#define LPTIM_CFGR_WAVPOL_Pos (21U)
3357#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
3358#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
3359#define LPTIM_CFGR_PRELOAD_Pos (22U)
3360#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
3361#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
3362#define LPTIM_CFGR_COUNTMODE_Pos (23U)
3363#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
3364#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
3365#define LPTIM_CFGR_ENC_Pos (24U)
3366#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
3367#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
3368
3369/****************** Bit definition for LPTIM_CR register ********************/
3370#define LPTIM_CR_ENABLE_Pos (0U)
3371#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
3372#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
3373#define LPTIM_CR_SNGSTRT_Pos (1U)
3374#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
3375#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
3376#define LPTIM_CR_CNTSTRT_Pos (2U)
3377#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
3378#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
3379
3380/****************** Bit definition for LPTIM_CMP register *******************/
3381#define LPTIM_CMP_CMP_Pos (0U)
3382#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
3383#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
3384
3385/****************** Bit definition for LPTIM_ARR register *******************/
3386#define LPTIM_ARR_ARR_Pos (0U)
3387#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
3388#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
3389
3390/****************** Bit definition for LPTIM_CNT register *******************/
3391#define LPTIM_CNT_CNT_Pos (0U)
3392#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
3393#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
3394
3395/******************************************************************************/
3396/* */
3397/* MIFARE Firewall */
3398/* */
3399/******************************************************************************/
3400
3401/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
3402#define FW_CSSA_ADD_Pos (8U)
3403#define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
3404#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
3405#define FW_CSL_LENG_Pos (8U)
3406#define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
3407#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
3408#define FW_NVDSSA_ADD_Pos (8U)
3409#define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
3410#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
3411#define FW_NVDSL_LENG_Pos (8U)
3412#define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
3413#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
3414#define FW_VDSSA_ADD_Pos (6U)
3415#define FW_VDSSA_ADD_Msk (0x3FFU << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
3416#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
3417#define FW_VDSL_LENG_Pos (6U)
3418#define FW_VDSL_LENG_Msk (0x3FFU << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
3419#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
3420
3421/**************************Bit definition for CR register *********************/
3422#define FW_CR_FPA_Pos (0U)
3423#define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
3424#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
3425#define FW_CR_VDS_Pos (1U)
3426#define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
3427#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
3428#define FW_CR_VDE_Pos (2U)
3429#define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
3430#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
3431
3432/******************************************************************************/
3433/* */
3434/* Power Control (PWR) */
3435/* */
3436/******************************************************************************/
3437
3438#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
3439
3440/******************** Bit definition for PWR_CR register ********************/
3441#define PWR_CR_LPSDSR_Pos (0U)
3442#define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
3443#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
3444#define PWR_CR_PDDS_Pos (1U)
3445#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
3446#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
3447#define PWR_CR_CWUF_Pos (2U)
3448#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
3449#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
3450#define PWR_CR_CSBF_Pos (3U)
3451#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
3452#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
3453#define PWR_CR_PVDE_Pos (4U)
3454#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
3455#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
3456
3457#define PWR_CR_PLS_Pos (5U)
3458#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
3459#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
3460#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
3461#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
3462#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
3463
3464/*!< PVD level configuration */
3465#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
3466#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
3467#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
3468#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
3469#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
3470#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
3471#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
3472#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
3473
3474#define PWR_CR_DBP_Pos (8U)
3475#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
3476#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
3477#define PWR_CR_ULP_Pos (9U)
3478#define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */
3479#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
3480#define PWR_CR_FWU_Pos (10U)
3481#define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */
3482#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
3483
3484#define PWR_CR_VOS_Pos (11U)
3485#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */
3486#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
3487#define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */
3488#define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */
3489#define PWR_CR_DSEEKOFF_Pos (13U)
3490#define PWR_CR_DSEEKOFF_Msk (0x1U << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
3491#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
3492#define PWR_CR_LPRUN_Pos (14U)
3493#define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
3494#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
3495
3496/******************* Bit definition for PWR_CSR register ********************/
3497#define PWR_CSR_WUF_Pos (0U)
3498#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
3499#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
3500#define PWR_CSR_SBF_Pos (1U)
3501#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
3502#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
3503#define PWR_CSR_PVDO_Pos (2U)
3504#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
3505#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
3506#define PWR_CSR_VREFINTRDYF_Pos (3U)
3507#define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
3508#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
3509#define PWR_CSR_VOSF_Pos (4U)
3510#define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
3511#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
3512#define PWR_CSR_REGLPF_Pos (5U)
3513#define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
3514#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
3515
3516#define PWR_CSR_EWUP1_Pos (8U)
3517#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
3518#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
3519#define PWR_CSR_EWUP2_Pos (9U)
3520#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
3521#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
3522
3523/******************************************************************************/
3524/* */
3525/* Reset and Clock Control */
3526/* */
3527/******************************************************************************/
3528
3529#define RCC_HSI48_SUPPORT /*!< HSI48 feature support */
3530#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
3531
3532/******************** Bit definition for RCC_CR register ********************/
3533#define RCC_CR_HSION_Pos (0U)
3534#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
3535#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
3536#define RCC_CR_HSIKERON_Pos (1U)
3537#define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
3538#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
3539#define RCC_CR_HSIRDY_Pos (2U)
3540#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */