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1/**
2 ******************************************************************************
3 * @file stm32l062xx.h
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
6 * This file contains all the peripheral register's definitions, bits
7 * definitions and memory mapping for stm32l062xx devices.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44/** @addtogroup CMSIS
45 * @{
46 */
47
48/** @addtogroup stm32l062xx
49 * @{
50 */
51
52#ifndef __STM32L062xx_H
53#define __STM32L062xx_H
54
55#ifdef __cplusplus
56 extern "C" {
57#endif
58
59
60/** @addtogroup Configuration_section_for_CMSIS
61 * @{
62 */
63/**
64 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
65 */
66#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
67#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */
68#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
69#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
70#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
71
72/**
73 * @}
74 */
75
76/** @addtogroup Peripheral_interrupt_number_definition
77 * @{
78 */
79
80/**
81 * @brief stm32l062xx Interrupt Number Definition, according to the selected device
82 * in @ref Library_configuration_section
83 */
84
85/*!< Interrupt Number Definition */
86typedef enum
87{
88/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
90 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
91 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
92 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
93 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
94
95/****** STM32L-0 specific Interrupt Numbers *********************************************************/
96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
97 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
98 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
99 FLASH_IRQn = 3, /*!< FLASH Interrupt */
100 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
101 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
102 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
103 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
104 TSC_IRQn = 8, /*!< TSC Interrupt */
105 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
106 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
107 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
108 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
109 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
110 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
111 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
112 TIM21_IRQn = 20, /*!< TIM21 Interrupt */
113 TIM22_IRQn = 22, /*!< TIM22 Interrupt */
114 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
115 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
116 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
117 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
118 USART1_IRQn = 27, /*!< USART1 Interrupt */
119 USART2_IRQn = 28, /*!< USART2 Interrupt */
120 AES_RNG_LPUART1_IRQn = 29, /*!< AES and RNG and LPUART1 Interrupts */
121 USB_IRQn = 31, /*!< USB global Interrupt */
122} IRQn_Type;
123
124/**
125 * @}
126 */
127
128#include "core_cm0plus.h"
129#include "system_stm32l0xx.h"
130#include <stdint.h>
131
132/** @addtogroup Peripheral_registers_structures
133 * @{
134 */
135
136/**
137 * @brief Analog to Digital Converter
138 */
139
140typedef struct
141{
142 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
143 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
144 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
145 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
146 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
147 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
148 uint32_t RESERVED1; /*!< Reserved, 0x18 */
149 uint32_t RESERVED2; /*!< Reserved, 0x1C */
150 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
151 uint32_t RESERVED3; /*!< Reserved, 0x24 */
152 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
153 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
154 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
155 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
156 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
157} ADC_TypeDef;
158
159typedef struct
160{
161 __IO uint32_t CCR;
162} ADC_Common_TypeDef;
163
164/**
165 * @brief AES hardware accelerator
166 */
167
168typedef struct
169{
170 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
171 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
172 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
173 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
174 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
175 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
176 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
177 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
178 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
179 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
180 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
181 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
182} AES_TypeDef;
183
184/**
185 * @brief Comparator
186 */
187
188typedef struct
189{
190 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
191} COMP_TypeDef;
192
193typedef struct
194{
195 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
196} COMP_Common_TypeDef;
197
198
199/**
200* @brief CRC calculation unit
201*/
202
203typedef struct
204{
205__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
206__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
207uint8_t RESERVED0; /*!< Reserved, 0x05 */
208uint16_t RESERVED1; /*!< Reserved, 0x06 */
209__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
210uint32_t RESERVED2; /*!< Reserved, 0x0C */
211__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
212__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
213} CRC_TypeDef;
214
215/**
216 * @brief Clock Recovery System
217 */
218
219typedef struct
220{
221__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
222__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
223__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
224__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
225} CRS_TypeDef;
226
227/**
228 * @brief Digital to Analog Converter
229 */
230
231typedef struct
232{
233 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
234 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
235 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
236 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
237 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
238 uint32_t RESERVED0[6]; /*!< 0x14-0x28 */
239 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
240 uint32_t RESERVED1; /*!< 0x30 */
241 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
242} DAC_TypeDef;
243
244/**
245 * @brief Debug MCU
246 */
247
248typedef struct
249{
250 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
251 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
252 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
253 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
254}DBGMCU_TypeDef;
255
256/**
257 * @brief DMA Controller
258 */
259
260typedef struct
261{
262 __IO uint32_t CCR; /*!< DMA channel x configuration register */
263 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
264 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
265 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
266} DMA_Channel_TypeDef;
267
268typedef struct
269{
270 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
271 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
272} DMA_TypeDef;
273
274typedef struct
275{
276 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
277} DMA_Request_TypeDef;
278
279/**
280 * @brief External Interrupt/Event Controller
281 */
282
283typedef struct
284{
285 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
286 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
287 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
288 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
289 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
290 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
291}EXTI_TypeDef;
292
293/**
294 * @brief FLASH Registers
295 */
296typedef struct
297{
298 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
299 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
300 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
301 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
302 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
303 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
304 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
305 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
306 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
307} FLASH_TypeDef;
308
309
310/**
311 * @brief Option Bytes Registers
312 */
313typedef struct
314{
315 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
316 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
317 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
318} OB_TypeDef;
319
320
321/**
322 * @brief General Purpose IO
323 */
324
325typedef struct
326{
327 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
328 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
329 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
330 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
331 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
332 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
333 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
334 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
335 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
336 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
337}GPIO_TypeDef;
338
339/**
340 * @brief LPTIMIMER
341 */
342typedef struct
343{
344 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
345 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
346 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
347 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
348 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
349 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
350 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
351 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
352} LPTIM_TypeDef;
353
354/**
355 * @brief SysTem Configuration
356 */
357
358typedef struct
359{
360 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
361 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
362 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
363 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
364 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
365} SYSCFG_TypeDef;
366
367
368
369/**
370 * @brief Inter-integrated Circuit Interface
371 */
372
373typedef struct
374{
375 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
376 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
377 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
378 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
379 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
380 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
381 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
382 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
383 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
384 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
385 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
386}I2C_TypeDef;
387
388
389/**
390 * @brief Independent WATCHDOG
391 */
392typedef struct
393{
394 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
395 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
396 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
397 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
398 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
399} IWDG_TypeDef;
400
401/**
402 * @brief MIFARE Firewall
403 */
404typedef struct
405{
406 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
407 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
408 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
409 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
410 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
411 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
412 __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
413 __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
414 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
415
416} FIREWALL_TypeDef;
417
418/**
419 * @brief Power Control
420 */
421typedef struct
422{
423 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
424 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
425} PWR_TypeDef;
426
427/**
428 * @brief Reset and Clock Control
429 */
430typedef struct
431{
432 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
433 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
434 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
435 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
436 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
437 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
438 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
439 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
440 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
441 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
442 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
443 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
444 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
445 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
446 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
447 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
448 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
449 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
450 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
451 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
452 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
453} RCC_TypeDef;
454
455/**
456 * @brief Random numbers generator
457 */
458typedef struct
459{
460 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
461 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
462 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
463} RNG_TypeDef;
464
465/**
466 * @brief Real-Time Clock
467 */
468typedef struct
469{
470 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
471 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
472 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
473 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
474 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
475 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
476 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
477 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
478 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
479 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
480 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
481 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
482 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
483 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
484 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
485 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
486 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
487 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
488 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
489 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
490 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
491 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
492 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
493 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
494 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
495} RTC_TypeDef;
496
497
498/**
499 * @brief Serial Peripheral Interface
500 */
501typedef struct
502{
503 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
504 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
505 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
506 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
507 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
508 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
509 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
510 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
511 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
512} SPI_TypeDef;
513
514/**
515 * @brief TIM
516 */
517typedef struct
518{
519 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
520 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
521 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
522 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
523 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
524 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
525 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
526 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
527 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
528 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
529 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
530 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
531 uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
532 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
533 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
534 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
535 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
536 uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
537 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
538 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
539 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
540} TIM_TypeDef;
541
542/**
543 * @brief Touch Sensing Controller (TSC)
544 */
545typedef struct
546{
547 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
548 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
549 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
550 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
551 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
552 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
553 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
554 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
555 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
556 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
557 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
558 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
559 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
560 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
561} TSC_TypeDef;
562
563/**
564 * @brief Universal Synchronous Asynchronous Receiver Transmitter
565 */
566typedef struct
567{
568 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
569 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
570 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
571 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
572 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
573 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
574 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
575 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
576 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
577 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
578 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
579} USART_TypeDef;
580
581/**
582 * @brief Window WATCHDOG
583 */
584typedef struct
585{
586 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
587 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
588 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
589} WWDG_TypeDef;
590
591/**
592 * @brief Universal Serial Bus Full Speed Device
593 */
594typedef struct
595{
596 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
597 __IO uint16_t RESERVED0; /*!< Reserved */
598 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
599 __IO uint16_t RESERVED1; /*!< Reserved */
600 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
601 __IO uint16_t RESERVED2; /*!< Reserved */
602 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
603 __IO uint16_t RESERVED3; /*!< Reserved */
604 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
605 __IO uint16_t RESERVED4; /*!< Reserved */
606 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
607 __IO uint16_t RESERVED5; /*!< Reserved */
608 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
609 __IO uint16_t RESERVED6; /*!< Reserved */
610 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
611 __IO uint16_t RESERVED7[17]; /*!< Reserved */
612 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
613 __IO uint16_t RESERVED8; /*!< Reserved */
614 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
615 __IO uint16_t RESERVED9; /*!< Reserved */
616 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
617 __IO uint16_t RESERVEDA; /*!< Reserved */
618 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
619 __IO uint16_t RESERVEDB; /*!< Reserved */
620 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
621 __IO uint16_t RESERVEDC; /*!< Reserved */
622 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
623 __IO uint16_t RESERVEDD; /*!< Reserved */
624 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
625 __IO uint16_t RESERVEDE; /*!< Reserved */
626} USB_TypeDef;
627
628/**
629 * @}
630 */
631
632/** @addtogroup Peripheral_memory_map
633 * @{
634 */
635#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
636#define FLASH_END ((uint32_t)0x0800FFFFU) /*!< FLASH end address in the alias region */
637#define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
638#define DATA_EEPROM_END ((uint32_t)0x080807FFU) /*!< DATA EEPROM end address in the alias region */
639#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
640#define SRAM_SIZE_MAX ((uint32_t)0x00002000U) /*!< maximum SRAM size (up to 8KBytes) */
641
642#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
643
644/*!< Peripheral memory map */
645#define APBPERIPH_BASE PERIPH_BASE
646#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
647#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000U)
648
649#define TIM2_BASE (APBPERIPH_BASE + 0x00000000U)
650#define TIM6_BASE (APBPERIPH_BASE + 0x00001000U)
651#define RTC_BASE (APBPERIPH_BASE + 0x00002800U)
652#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U)
653#define IWDG_BASE (APBPERIPH_BASE + 0x00003000U)
654#define SPI2_BASE (APBPERIPH_BASE + 0x00003800U)
655#define USART2_BASE (APBPERIPH_BASE + 0x00004400U)
656#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800U)
657#define I2C1_BASE (APBPERIPH_BASE + 0x00005400U)
658#define I2C2_BASE (APBPERIPH_BASE + 0x00005800U)
659#define CRS_BASE (APBPERIPH_BASE + 0x00006C00U)
660#define PWR_BASE (APBPERIPH_BASE + 0x00007000U)
661#define DAC_BASE (APBPERIPH_BASE + 0x00007400U)
662#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U)
663
664#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000U)
665#define COMP1_BASE (APBPERIPH_BASE + 0x00010018U)
666#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CU)
667#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
668#define EXTI_BASE (APBPERIPH_BASE + 0x00010400U)
669#define TIM21_BASE (APBPERIPH_BASE + 0x00010800U)
670#define TIM22_BASE (APBPERIPH_BASE + 0x00011400U)
671#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00U)
672#define ADC1_BASE (APBPERIPH_BASE + 0x00012400U)
673#define ADC_BASE (APBPERIPH_BASE + 0x00012708U)
674#define SPI1_BASE (APBPERIPH_BASE + 0x00013000U)
675#define USART1_BASE (APBPERIPH_BASE + 0x00013800U)
676#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800U)
677
678#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
679#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
680#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
681#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
682#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
683#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
684#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
685#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
686#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U)
687
688
689#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
690#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
691#define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
692#define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */
693#define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */
694#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
695#define TSC_BASE (AHBPERIPH_BASE + 0x00004000U)
696#define RNG_BASE (AHBPERIPH_BASE + 0x00005000U)
697#define AES_BASE (AHBPERIPH_BASE + 0x00006000U)
698
699#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U)
700#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U)
701#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800U)
702#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00U)
703#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00U)
704
705/**
706 * @}
707 */
708
709/** @addtogroup Peripheral_declaration
710 * @{
711 */
712
713#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
714#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
715#define RTC ((RTC_TypeDef *) RTC_BASE)
716#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
717#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
718#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
719#define USART2 ((USART_TypeDef *) USART2_BASE)
720#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
721#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
722#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
723#define CRS ((CRS_TypeDef *) CRS_BASE)
724#define PWR ((PWR_TypeDef *) PWR_BASE)
725#define DAC ((DAC_TypeDef *) DAC_BASE)
726#define DAC1 ((DAC_TypeDef *) DAC_BASE)
727#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
728
729#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
730#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
731#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
732#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
733#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
734#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
735#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
736#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
737#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
738/* Legacy defines */
739#define ADC ADC1_COMMON
740#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
741#define USART1 ((USART_TypeDef *) USART1_BASE)
742#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
743
744#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
745#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
746#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
747#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
748#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
749#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
750#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
751#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
752#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
753
754
755#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
756#define OB ((OB_TypeDef *) OB_BASE)
757#define RCC ((RCC_TypeDef *) RCC_BASE)
758#define CRC ((CRC_TypeDef *) CRC_BASE)
759#define TSC ((TSC_TypeDef *) TSC_BASE)
760#define AES ((AES_TypeDef *) AES_BASE)
761#define RNG ((RNG_TypeDef *) RNG_BASE)
762
763#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
764#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
765#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
766#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
767#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
768
769#define USB ((USB_TypeDef *) USB_BASE)
770
771/**
772 * @}
773 */
774
775/** @addtogroup Exported_constants
776 * @{
777 */
778
779 /** @addtogroup Peripheral_Registers_Bits_Definition
780 * @{
781 */
782
783/******************************************************************************/
784/* Peripheral Registers Bits Definition */
785/******************************************************************************/
786/******************************************************************************/
787/* */
788/* Analog to Digital Converter (ADC) */
789/* */
790/******************************************************************************/
791/******************** Bits definition for ADC_ISR register ******************/
792#define ADC_ISR_EOCAL_Pos (11U)
793#define ADC_ISR_EOCAL_Msk (0x1U << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
794#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
795#define ADC_ISR_AWD_Pos (7U)
796#define ADC_ISR_AWD_Msk (0x1U << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
797#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
798#define ADC_ISR_OVR_Pos (4U)
799#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
800#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
801#define ADC_ISR_EOSEQ_Pos (3U)
802#define ADC_ISR_EOSEQ_Msk (0x1U << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
803#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
804#define ADC_ISR_EOC_Pos (2U)
805#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
806#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
807#define ADC_ISR_EOSMP_Pos (1U)
808#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
809#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
810#define ADC_ISR_ADRDY_Pos (0U)
811#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
812#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
813
814/* Old EOSEQ bit definition, maintained for legacy purpose */
815#define ADC_ISR_EOS ADC_ISR_EOSEQ
816
817/******************** Bits definition for ADC_IER register ******************/
818#define ADC_IER_EOCALIE_Pos (11U)
819#define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
820#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
821#define ADC_IER_AWDIE_Pos (7U)
822#define ADC_IER_AWDIE_Msk (0x1U << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
823#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
824#define ADC_IER_OVRIE_Pos (4U)
825#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
826#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
827#define ADC_IER_EOSEQIE_Pos (3U)
828#define ADC_IER_EOSEQIE_Msk (0x1U << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
829#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
830#define ADC_IER_EOCIE_Pos (2U)
831#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
832#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
833#define ADC_IER_EOSMPIE_Pos (1U)
834#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
835#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
836#define ADC_IER_ADRDYIE_Pos (0U)
837#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
838#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
839
840/* Old EOSEQIE bit definition, maintained for legacy purpose */
841#define ADC_IER_EOSIE ADC_IER_EOSEQIE
842
843/******************** Bits definition for ADC_CR register *******************/
844#define ADC_CR_ADCAL_Pos (31U)
845#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
846#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
847#define ADC_CR_ADVREGEN_Pos (28U)
848#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
849#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
850#define ADC_CR_ADSTP_Pos (4U)
851#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
852#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
853#define ADC_CR_ADSTART_Pos (2U)
854#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
855#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
856#define ADC_CR_ADDIS_Pos (1U)
857#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
858#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
859#define ADC_CR_ADEN_Pos (0U)
860#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
861#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
862
863/******************* Bits definition for ADC_CFGR1 register *****************/
864#define ADC_CFGR1_AWDCH_Pos (26U)
865#define ADC_CFGR1_AWDCH_Msk (0x1FU << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
866#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
867#define ADC_CFGR1_AWDCH_0 (0x01U << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
868#define ADC_CFGR1_AWDCH_1 (0x02U << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
869#define ADC_CFGR1_AWDCH_2 (0x04U << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
870#define ADC_CFGR1_AWDCH_3 (0x08U << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
871#define ADC_CFGR1_AWDCH_4 (0x10U << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
872#define ADC_CFGR1_AWDEN_Pos (23U)
873#define ADC_CFGR1_AWDEN_Msk (0x1U << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
874#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
875#define ADC_CFGR1_AWDSGL_Pos (22U)
876#define ADC_CFGR1_AWDSGL_Msk (0x1U << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
877#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
878#define ADC_CFGR1_DISCEN_Pos (16U)
879#define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
880#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
881#define ADC_CFGR1_AUTOFF_Pos (15U)
882#define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
883#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
884#define ADC_CFGR1_WAIT_Pos (14U)
885#define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
886#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
887#define ADC_CFGR1_CONT_Pos (13U)
888#define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
889#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
890#define ADC_CFGR1_OVRMOD_Pos (12U)
891#define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
892#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
893#define ADC_CFGR1_EXTEN_Pos (10U)
894#define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
895#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
896#define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
897#define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
898#define ADC_CFGR1_EXTSEL_Pos (6U)
899#define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
900#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
901#define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
902#define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
903#define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
904#define ADC_CFGR1_ALIGN_Pos (5U)
905#define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
906#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
907#define ADC_CFGR1_RES_Pos (3U)
908#define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
909#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
910#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
911#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
912#define ADC_CFGR1_SCANDIR_Pos (2U)
913#define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
914#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
915#define ADC_CFGR1_DMACFG_Pos (1U)
916#define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
917#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
918#define ADC_CFGR1_DMAEN_Pos (0U)
919#define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
920#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
921
922/* Old WAIT bit definition, maintained for legacy purpose */
923#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
924
925/******************* Bits definition for ADC_CFGR2 register *****************/
926#define ADC_CFGR2_TOVS_Pos (9U)
927#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
928#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
929#define ADC_CFGR2_OVSS_Pos (5U)
930#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
931#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
932#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
933#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
934#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
935#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
936#define ADC_CFGR2_OVSR_Pos (2U)
937#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
938#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
939#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
940#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
941#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
942#define ADC_CFGR2_OVSE_Pos (0U)
943#define ADC_CFGR2_OVSE_Msk (0x1U << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
944#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
945#define ADC_CFGR2_CKMODE_Pos (30U)
946#define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
947#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
948#define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
949#define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
950
951
952/****************** Bit definition for ADC_SMPR register ********************/
953#define ADC_SMPR_SMP_Pos (0U)
954#define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
955#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
956#define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
957#define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
958#define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
959
960/* Legacy defines */
961#define ADC_SMPR_SMPR ADC_SMPR_SMP
962#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
963#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
964#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
965
966/******************* Bit definition for ADC_TR register ********************/
967#define ADC_TR_HT_Pos (16U)
968#define ADC_TR_HT_Msk (0xFFFU << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
969#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
970#define ADC_TR_LT_Pos (0U)
971#define ADC_TR_LT_Msk (0xFFFU << ADC_TR_LT_Pos) /*!< 0x00000FFF */
972#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
973
974/****************** Bit definition for ADC_CHSELR register ******************/
975#define ADC_CHSELR_CHSEL_Pos (0U)
976#define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
977#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
978#define ADC_CHSELR_CHSEL18_Pos (18U)
979#define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
980#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
981#define ADC_CHSELR_CHSEL17_Pos (17U)
982#define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
983#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
984#define ADC_CHSELR_CHSEL15_Pos (15U)
985#define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
986#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
987#define ADC_CHSELR_CHSEL14_Pos (14U)
988#define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
989#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
990#define ADC_CHSELR_CHSEL13_Pos (13U)
991#define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
992#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
993#define ADC_CHSELR_CHSEL12_Pos (12U)
994#define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
995#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
996#define ADC_CHSELR_CHSEL11_Pos (11U)
997#define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
998#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
999#define ADC_CHSELR_CHSEL10_Pos (10U)
1000#define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
1001#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
1002#define ADC_CHSELR_CHSEL9_Pos (9U)
1003#define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
1004#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
1005#define ADC_CHSELR_CHSEL8_Pos (8U)
1006#define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
1007#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
1008#define ADC_CHSELR_CHSEL7_Pos (7U)
1009#define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
1010#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
1011#define ADC_CHSELR_CHSEL6_Pos (6U)
1012#define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
1013#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
1014#define ADC_CHSELR_CHSEL5_Pos (5U)
1015#define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
1016#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
1017#define ADC_CHSELR_CHSEL4_Pos (4U)
1018#define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
1019#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
1020#define ADC_CHSELR_CHSEL3_Pos (3U)
1021#define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
1022#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
1023#define ADC_CHSELR_CHSEL2_Pos (2U)
1024#define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
1025#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
1026#define ADC_CHSELR_CHSEL1_Pos (1U)
1027#define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
1028#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
1029#define ADC_CHSELR_CHSEL0_Pos (0U)
1030#define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
1031#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
1032
1033/******************** Bit definition for ADC_DR register ********************/
1034#define ADC_DR_DATA_Pos (0U)
1035#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1036#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
1037
1038/******************** Bit definition for ADC_CALFACT register ********************/
1039#define ADC_CALFACT_CALFACT_Pos (0U)
1040#define ADC_CALFACT_CALFACT_Msk (0x7FU << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
1041#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
1042
1043/******************* Bit definition for ADC_CCR register ********************/
1044#define ADC_CCR_LFMEN_Pos (25U)
1045#define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
1046#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
1047#define ADC_CCR_TSEN_Pos (23U)
1048#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
1049#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
1050#define ADC_CCR_VREFEN_Pos (22U)
1051#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
1052#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
1053#define ADC_CCR_PRESC_Pos (18U)
1054#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
1055#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
1056#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
1057#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
1058#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
1059#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
1060
1061/******************************************************************************/
1062/* */
1063/* Advanced Encryption Standard (AES) */
1064/* */
1065/******************************************************************************/
1066/******************* Bit definition for AES_CR register *********************/
1067#define AES_CR_EN_Pos (0U)
1068#define AES_CR_EN_Msk (0x1U << AES_CR_EN_Pos) /*!< 0x00000001 */
1069#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
1070#define AES_CR_DATATYPE_Pos (1U)
1071#define AES_CR_DATATYPE_Msk (0x3U << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
1072#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
1073#define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
1074#define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
1075
1076#define AES_CR_MODE_Pos (3U)
1077#define AES_CR_MODE_Msk (0x3U << AES_CR_MODE_Pos) /*!< 0x00000018 */
1078#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
1079#define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */
1080#define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */
1081
1082#define AES_CR_CHMOD_Pos (5U)
1083#define AES_CR_CHMOD_Msk (0x3U << AES_CR_CHMOD_Pos) /*!< 0x00000060 */
1084#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
1085#define AES_CR_CHMOD_0 (0x1U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
1086#define AES_CR_CHMOD_1 (0x2U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
1087
1088#define AES_CR_CCFC_Pos (7U)
1089#define AES_CR_CCFC_Msk (0x1U << AES_CR_CCFC_Pos) /*!< 0x00000080 */
1090#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
1091#define AES_CR_ERRC_Pos (8U)
1092#define AES_CR_ERRC_Msk (0x1U << AES_CR_ERRC_Pos) /*!< 0x00000100 */
1093#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
1094#define AES_CR_CCIE_Pos (9U)
1095#define AES_CR_CCIE_Msk (0x1U << AES_CR_CCIE_Pos) /*!< 0x00000200 */
1096#define AES_CR_CCIE AES_CR_CCIE_Msk /*!< Computation Complete Interrupt Enable */
1097#define AES_CR_ERRIE_Pos (10U)
1098#define AES_CR_ERRIE_Msk (0x1U << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
1099#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
1100#define AES_CR_DMAINEN_Pos (11U)
1101#define AES_CR_DMAINEN_Msk (0x1U << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
1102#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA ENable managing the data input phase */
1103#define AES_CR_DMAOUTEN_Pos (12U)
1104#define AES_CR_DMAOUTEN_Msk (0x1U << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
1105#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA Enable managing the data output phase */
1106
1107/******************* Bit definition for AES_SR register *********************/
1108#define AES_SR_CCF_Pos (0U)
1109#define AES_SR_CCF_Msk (0x1U << AES_SR_CCF_Pos) /*!< 0x00000001 */
1110#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
1111#define AES_SR_RDERR_Pos (1U)
1112#define AES_SR_RDERR_Msk (0x1U << AES_SR_RDERR_Pos) /*!< 0x00000002 */
1113#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
1114#define AES_SR_WRERR_Pos (2U)
1115#define AES_SR_WRERR_Msk (0x1U << AES_SR_WRERR_Pos) /*!< 0x00000004 */
1116#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
1117
1118/******************* Bit definition for AES_DINR register *******************/
1119#define AES_DINR_Pos (0U)
1120#define AES_DINR_Msk (0xFFFFU << AES_DINR_Pos) /*!< 0x0000FFFF */
1121#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
1122
1123/******************* Bit definition for AES_DOUTR register ******************/
1124#define AES_DOUTR_Pos (0U)
1125#define AES_DOUTR_Msk (0xFFFFU << AES_DOUTR_Pos) /*!< 0x0000FFFF */
1126#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
1127
1128/******************* Bit definition for AES_KEYR0 register ******************/
1129#define AES_KEYR0_Pos (0U)
1130#define AES_KEYR0_Msk (0xFFFFU << AES_KEYR0_Pos) /*!< 0x0000FFFF */
1131#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
1132
1133/******************* Bit definition for AES_KEYR1 register ******************/
1134#define AES_KEYR1_Pos (0U)
1135#define AES_KEYR1_Msk (0xFFFFU << AES_KEYR1_Pos) /*!< 0x0000FFFF */
1136#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
1137
1138/******************* Bit definition for AES_KEYR2 register ******************/
1139#define AES_KEYR2_Pos (0U)
1140#define AES_KEYR2_Msk (0xFFFFU << AES_KEYR2_Pos) /*!< 0x0000FFFF */
1141#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
1142
1143/******************* Bit definition for AES_KEYR3 register ******************/
1144#define AES_KEYR3_Pos (0U)
1145#define AES_KEYR3_Msk (0xFFFFU << AES_KEYR3_Pos) /*!< 0x0000FFFF */
1146#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
1147
1148/******************* Bit definition for AES_IVR0 register *******************/
1149#define AES_IVR0_Pos (0U)
1150#define AES_IVR0_Msk (0xFFFFU << AES_IVR0_Pos) /*!< 0x0000FFFF */
1151#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
1152
1153/******************* Bit definition for AES_IVR1 register *******************/
1154#define AES_IVR1_Pos (0U)
1155#define AES_IVR1_Msk (0xFFFFU << AES_IVR1_Pos) /*!< 0x0000FFFF */
1156#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
1157
1158/******************* Bit definition for AES_IVR2 register *******************/
1159#define AES_IVR2_Pos (0U)
1160#define AES_IVR2_Msk (0xFFFFU << AES_IVR2_Pos) /*!< 0x0000FFFF */
1161#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
1162
1163/******************* Bit definition for AES_IVR3 register *******************/
1164#define AES_IVR3_Pos (0U)
1165#define AES_IVR3_Msk (0xFFFFU << AES_IVR3_Pos) /*!< 0x0000FFFF */
1166#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
1167
1168/******************************************************************************/
1169/* */
1170/* Analog Comparators (COMP) */
1171/* */
1172/******************************************************************************/
1173/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
1174/* COMP1 bits definition */
1175#define COMP_CSR_COMP1EN_Pos (0U)
1176#define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
1177#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
1178#define COMP_CSR_COMP1INNSEL_Pos (4U)
1179#define COMP_CSR_COMP1INNSEL_Msk (0x3U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1180#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
1181#define COMP_CSR_COMP1INNSEL_0 (0x1U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1182#define COMP_CSR_COMP1INNSEL_1 (0x2U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
1183#define COMP_CSR_COMP1WM_Pos (8U)
1184#define COMP_CSR_COMP1WM_Msk (0x1U << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
1185#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
1186#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
1187#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
1188#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
1189#define COMP_CSR_COMP1POLARITY_Pos (15U)
1190#define COMP_CSR_COMP1POLARITY_Msk (0x1U << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
1191#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
1192#define COMP_CSR_COMP1VALUE_Pos (30U)
1193#define COMP_CSR_COMP1VALUE_Msk (0x1U << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
1194#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
1195#define COMP_CSR_COMP1LOCK_Pos (31U)
1196#define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
1197#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
1198/* COMP2 bits definition */
1199#define COMP_CSR_COMP2EN_Pos (0U)
1200#define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
1201#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
1202#define COMP_CSR_COMP2SPEED_Pos (3U)
1203#define COMP_CSR_COMP2SPEED_Msk (0x1U << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
1204#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
1205#define COMP_CSR_COMP2INNSEL_Pos (4U)
1206#define COMP_CSR_COMP2INNSEL_Msk (0x7U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
1207#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
1208#define COMP_CSR_COMP2INNSEL_0 (0x1U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
1209#define COMP_CSR_COMP2INNSEL_1 (0x2U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
1210#define COMP_CSR_COMP2INNSEL_2 (0x4U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1211#define COMP_CSR_COMP2INPSEL_Pos (8U)
1212#define COMP_CSR_COMP2INPSEL_Msk (0x7U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
1213#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
1214#define COMP_CSR_COMP2INPSEL_0 (0x1U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
1215#define COMP_CSR_COMP2INPSEL_1 (0x2U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
1216#define COMP_CSR_COMP2INPSEL_2 (0x4U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
1217#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
1218#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
1219#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
1220#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
1221#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
1222#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
1223#define COMP_CSR_COMP2POLARITY_Pos (15U)
1224#define COMP_CSR_COMP2POLARITY_Msk (0x1U << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
1225#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
1226#define COMP_CSR_COMP2VALUE_Pos (30U)
1227#define COMP_CSR_COMP2VALUE_Msk (0x1U << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
1228#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
1229#define COMP_CSR_COMP2LOCK_Pos (31U)
1230#define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
1231#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
1232
1233/********************** Bit definition for COMP_CSR register common ****************/
1234#define COMP_CSR_COMPxEN_Pos (0U)
1235#define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
1236#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
1237#define COMP_CSR_COMPxPOLARITY_Pos (15U)
1238#define COMP_CSR_COMPxPOLARITY_Msk (0x1U << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
1239#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
1240#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
1241#define COMP_CSR_COMPxOUTVALUE_Msk (0x1U << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
1242#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
1243#define COMP_CSR_COMPxLOCK_Pos (31U)
1244#define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
1245#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
1246
1247/* Reference defines */
1248#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
1249
1250/******************************************************************************/
1251/* */
1252/* CRC calculation unit (CRC) */
1253/* */
1254/******************************************************************************/
1255/******************* Bit definition for CRC_DR register *********************/
1256#define CRC_DR_DR_Pos (0U)
1257#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
1258#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
1259
1260/******************* Bit definition for CRC_IDR register ********************/
1261#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
1262
1263/******************** Bit definition for CRC_CR register ********************/
1264#define CRC_CR_RESET_Pos (0U)
1265#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
1266#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
1267#define CRC_CR_POLYSIZE_Pos (3U)
1268#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
1269#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
1270#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
1271#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
1272#define CRC_CR_REV_IN_Pos (5U)
1273#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
1274#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
1275#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
1276#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
1277#define CRC_CR_REV_OUT_Pos (7U)
1278#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
1279#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
1280
1281/******************* Bit definition for CRC_INIT register *******************/
1282#define CRC_INIT_INIT_Pos (0U)
1283#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
1284#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
1285
1286/******************* Bit definition for CRC_POL register ********************/
1287#define CRC_POL_POL_Pos (0U)
1288#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
1289#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
1290
1291/******************************************************************************/
1292/* */
1293/* CRS Clock Recovery System */
1294/* */
1295/******************************************************************************/
1296
1297/******************* Bit definition for CRS_CR register *********************/
1298#define CRS_CR_SYNCOKIE_Pos (0U)
1299#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
1300#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */
1301#define CRS_CR_SYNCWARNIE_Pos (1U)
1302#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
1303#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */
1304#define CRS_CR_ERRIE_Pos (2U)
1305#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
1306#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */
1307#define CRS_CR_ESYNCIE_Pos (3U)
1308#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
1309#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/
1310#define CRS_CR_CEN_Pos (5U)
1311#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
1312#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */
1313#define CRS_CR_AUTOTRIMEN_Pos (6U)
1314#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
1315#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */
1316#define CRS_CR_SWSYNC_Pos (7U)
1317#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
1318#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */
1319#define CRS_CR_TRIM_Pos (8U)
1320#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
1321#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */
1322
1323/******************* Bit definition for CRS_CFGR register *********************/
1324#define CRS_CFGR_RELOAD_Pos (0U)
1325#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
1326#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */
1327#define CRS_CFGR_FELIM_Pos (16U)
1328#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
1329#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */
1330
1331#define CRS_CFGR_SYNCDIV_Pos (24U)
1332#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
1333#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */
1334#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
1335#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
1336#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
1337
1338#define CRS_CFGR_SYNCSRC_Pos (28U)
1339#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
1340#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */
1341#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
1342#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
1343
1344#define CRS_CFGR_SYNCPOL_Pos (31U)
1345#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
1346#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */
1347
1348/******************* Bit definition for CRS_ISR register *********************/
1349#define CRS_ISR_SYNCOKF_Pos (0U)
1350#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
1351#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */
1352#define CRS_ISR_SYNCWARNF_Pos (1U)
1353#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
1354#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */
1355#define CRS_ISR_ERRF_Pos (2U)
1356#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
1357#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */
1358#define CRS_ISR_ESYNCF_Pos (3U)
1359#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
1360#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */
1361#define CRS_ISR_SYNCERR_Pos (8U)
1362#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
1363#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */
1364#define CRS_ISR_SYNCMISS_Pos (9U)
1365#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
1366#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */
1367#define CRS_ISR_TRIMOVF_Pos (10U)
1368#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
1369#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */
1370#define CRS_ISR_FEDIR_Pos (15U)
1371#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
1372#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */
1373#define CRS_ISR_FECAP_Pos (16U)
1374#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
1375#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */
1376
1377/******************* Bit definition for CRS_ICR register *********************/
1378#define CRS_ICR_SYNCOKC_Pos (0U)
1379#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
1380#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */
1381#define CRS_ICR_SYNCWARNC_Pos (1U)
1382#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
1383#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */
1384#define CRS_ICR_ERRC_Pos (2U)
1385#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
1386#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */
1387#define CRS_ICR_ESYNCC_Pos (3U)
1388#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
1389#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */
1390
1391/******************************************************************************/
1392/* */
1393/* Digital to Analog Converter (DAC) */
1394/* */
1395/******************************************************************************/
1396
1397/*
1398 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
1399 */
1400/* Note: No specific macro feature on this device */
1401
1402/******************** Bit definition for DAC_CR register ********************/
1403#define DAC_CR_EN1_Pos (0U)
1404#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
1405#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
1406#define DAC_CR_BOFF1_Pos (1U)
1407#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
1408#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
1409#define DAC_CR_TEN1_Pos (2U)
1410#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
1411#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
1412
1413#define DAC_CR_TSEL1_Pos (3U)
1414#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
1415#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
1416#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
1417#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
1418#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
1419
1420#define DAC_CR_WAVE1_Pos (6U)
1421#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
1422#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1423#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
1424#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
1425
1426#define DAC_CR_MAMP1_Pos (8U)
1427#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
1428#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1429#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
1430#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
1431#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
1432#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
1433
1434#define DAC_CR_DMAEN1_Pos (12U)
1435#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
1436#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
1437#define DAC_CR_DMAUDRIE1_Pos (13U)
1438#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
1439#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */
1440
1441/***************** Bit definition for DAC_SWTRIGR register ******************/
1442#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
1443#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
1444#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
1445
1446/***************** Bit definition for DAC_DHR12R1 register ******************/
1447#define DAC_DHR12R1_DACC1DHR_Pos (0U)
1448#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
1449#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
1450
1451/***************** Bit definition for DAC_DHR12L1 register ******************/
1452#define DAC_DHR12L1_DACC1DHR_Pos (4U)
1453#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
1454#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
1455
1456/****************** Bit definition for DAC_DHR8R1 register ******************/
1457#define DAC_DHR8R1_DACC1DHR_Pos (0U)
1458#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
1459#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
1460
1461/******************* Bit definition for DAC_DOR1 register *******************/
1462#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */
1463
1464/******************** Bit definition for DAC_SR register ********************/
1465#define DAC_SR_DMAUDR1_Pos (13U)
1466#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
1467#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
1468
1469/******************************************************************************/
1470/* */
1471/* Debug MCU (DBGMCU) */
1472/* */
1473/******************************************************************************/
1474
1475/**************** Bit definition for DBGMCU_IDCODE register *****************/
1476#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
1477#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
1478#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
1479
1480#define DBGMCU_IDCODE_REV_ID_Pos (16U)
1481#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
1482#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
1483#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
1484#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
1485#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
1486#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
1487#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
1488#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
1489#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
1490#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
1491#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
1492#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
1493#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
1494#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
1495#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
1496#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
1497#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
1498#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
1499
1500/****************** Bit definition for DBGMCU_CR register *******************/
1501#define DBGMCU_CR_DBG_Pos (0U)
1502#define DBGMCU_CR_DBG_Msk (0x7U << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
1503#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
1504#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
1505#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
1506#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
1507#define DBGMCU_CR_DBG_STOP_Pos (1U)
1508#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
1509#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
1510#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
1511#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
1512#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
1513
1514/****************** Bit definition for DBGMCU_APB1_FZ register **************/
1515#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
1516#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
1517#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
1518#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
1519#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
1520#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
1521#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
1522#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
1523#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
1524#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
1525#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
1526#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
1527#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
1528#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
1529#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
1530#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
1531#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
1532#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
1533#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
1534#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
1535#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
1536#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
1537#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
1538#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
1539/****************** Bit definition for DBGMCU_APB2_FZ register **************/
1540#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
1541#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
1542#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
1543#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
1544#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
1545#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
1546
1547/******************************************************************************/
1548/* */
1549/* DMA Controller (DMA) */
1550/* */
1551/******************************************************************************/
1552
1553/******************* Bit definition for DMA_ISR register ********************/
1554#define DMA_ISR_GIF1_Pos (0U)
1555#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
1556#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
1557#define DMA_ISR_TCIF1_Pos (1U)
1558#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
1559#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
1560#define DMA_ISR_HTIF1_Pos (2U)
1561#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
1562#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
1563#define DMA_ISR_TEIF1_Pos (3U)
1564#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
1565#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
1566#define DMA_ISR_GIF2_Pos (4U)
1567#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
1568#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
1569#define DMA_ISR_TCIF2_Pos (5U)
1570#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
1571#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
1572#define DMA_ISR_HTIF2_Pos (6U)
1573#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
1574#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
1575#define DMA_ISR_TEIF2_Pos (7U)
1576#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
1577#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
1578#define DMA_ISR_GIF3_Pos (8U)
1579#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
1580#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
1581#define DMA_ISR_TCIF3_Pos (9U)
1582#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
1583#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
1584#define DMA_ISR_HTIF3_Pos (10U)
1585#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
1586#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
1587#define DMA_ISR_TEIF3_Pos (11U)
1588#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
1589#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
1590#define DMA_ISR_GIF4_Pos (12U)
1591#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
1592#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
1593#define DMA_ISR_TCIF4_Pos (13U)
1594#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
1595#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
1596#define DMA_ISR_HTIF4_Pos (14U)
1597#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
1598#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
1599#define DMA_ISR_TEIF4_Pos (15U)
1600#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
1601#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
1602#define DMA_ISR_GIF5_Pos (16U)
1603#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
1604#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
1605#define DMA_ISR_TCIF5_Pos (17U)
1606#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
1607#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
1608#define DMA_ISR_HTIF5_Pos (18U)
1609#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
1610#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
1611#define DMA_ISR_TEIF5_Pos (19U)
1612#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
1613#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
1614#define DMA_ISR_GIF6_Pos (20U)
1615#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
1616#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
1617#define DMA_ISR_TCIF6_Pos (21U)
1618#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
1619#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
1620#define DMA_ISR_HTIF6_Pos (22U)
1621#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
1622#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
1623#define DMA_ISR_TEIF6_Pos (23U)
1624#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
1625#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
1626#define DMA_ISR_GIF7_Pos (24U)
1627#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
1628#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
1629#define DMA_ISR_TCIF7_Pos (25U)
1630#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
1631#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
1632#define DMA_ISR_HTIF7_Pos (26U)
1633#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
1634#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
1635#define DMA_ISR_TEIF7_Pos (27U)
1636#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
1637#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
1638
1639/******************* Bit definition for DMA_IFCR register *******************/
1640#define DMA_IFCR_CGIF1_Pos (0U)
1641#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
1642#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
1643#define DMA_IFCR_CTCIF1_Pos (1U)
1644#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1645#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
1646#define DMA_IFCR_CHTIF1_Pos (2U)
1647#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1648#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
1649#define DMA_IFCR_CTEIF1_Pos (3U)
1650#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1651#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
1652#define DMA_IFCR_CGIF2_Pos (4U)
1653#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
1654#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
1655#define DMA_IFCR_CTCIF2_Pos (5U)
1656#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1657#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
1658#define DMA_IFCR_CHTIF2_Pos (6U)
1659#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1660#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
1661#define DMA_IFCR_CTEIF2_Pos (7U)
1662#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
1663#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
1664#define DMA_IFCR_CGIF3_Pos (8U)
1665#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
1666#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
1667#define DMA_IFCR_CTCIF3_Pos (9U)
1668#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
1669#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
1670#define DMA_IFCR_CHTIF3_Pos (10U)
1671#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
1672#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
1673#define DMA_IFCR_CTEIF3_Pos (11U)
1674#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
1675#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
1676#define DMA_IFCR_CGIF4_Pos (12U)
1677#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
1678#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
1679#define DMA_IFCR_CTCIF4_Pos (13U)
1680#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
1681#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
1682#define DMA_IFCR_CHTIF4_Pos (14U)
1683#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
1684#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
1685#define DMA_IFCR_CTEIF4_Pos (15U)
1686#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
1687#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
1688#define DMA_IFCR_CGIF5_Pos (16U)
1689#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
1690#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
1691#define DMA_IFCR_CTCIF5_Pos (17U)
1692#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
1693#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
1694#define DMA_IFCR_CHTIF5_Pos (18U)
1695#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
1696#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
1697#define DMA_IFCR_CTEIF5_Pos (19U)
1698#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
1699#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
1700#define DMA_IFCR_CGIF6_Pos (20U)
1701#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
1702#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
1703#define DMA_IFCR_CTCIF6_Pos (21U)
1704#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
1705#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
1706#define DMA_IFCR_CHTIF6_Pos (22U)
1707#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
1708#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
1709#define DMA_IFCR_CTEIF6_Pos (23U)
1710#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
1711#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
1712#define DMA_IFCR_CGIF7_Pos (24U)
1713#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
1714#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
1715#define DMA_IFCR_CTCIF7_Pos (25U)
1716#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
1717#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
1718#define DMA_IFCR_CHTIF7_Pos (26U)
1719#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
1720#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
1721#define DMA_IFCR_CTEIF7_Pos (27U)
1722#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
1723#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
1724
1725/******************* Bit definition for DMA_CCR register ********************/
1726#define DMA_CCR_EN_Pos (0U)
1727#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
1728#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
1729#define DMA_CCR_TCIE_Pos (1U)
1730#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
1731#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
1732#define DMA_CCR_HTIE_Pos (2U)
1733#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
1734#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
1735#define DMA_CCR_TEIE_Pos (3U)
1736#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
1737#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
1738#define DMA_CCR_DIR_Pos (4U)
1739#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
1740#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
1741#define DMA_CCR_CIRC_Pos (5U)
1742#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
1743#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
1744#define DMA_CCR_PINC_Pos (6U)
1745#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
1746#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
1747#define DMA_CCR_MINC_Pos (7U)
1748#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1749#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
1750
1751#define DMA_CCR_PSIZE_Pos (8U)
1752#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
1753#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
1754#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
1755#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
1756
1757#define DMA_CCR_MSIZE_Pos (10U)
1758#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
1759#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
1760#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
1761#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
1762
1763#define DMA_CCR_PL_Pos (12U)
1764#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
1765#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
1766#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
1767#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
1768
1769#define DMA_CCR_MEM2MEM_Pos (14U)
1770#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
1771#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
1772
1773/****************** Bit definition for DMA_CNDTR register *******************/
1774#define DMA_CNDTR_NDT_Pos (0U)
1775#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
1776#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
1777
1778/****************** Bit definition for DMA_CPAR register ********************/
1779#define DMA_CPAR_PA_Pos (0U)
1780#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
1781#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
1782
1783/****************** Bit definition for DMA_CMAR register ********************/
1784#define DMA_CMAR_MA_Pos (0U)
1785#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
1786#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
1787
1788
1789/******************* Bit definition for DMA_CSELR register *******************/
1790#define DMA_CSELR_C1S_Pos (0U)
1791#define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
1792#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
1793#define DMA_CSELR_C2S_Pos (4U)
1794#define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
1795#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
1796#define DMA_CSELR_C3S_Pos (8U)
1797#define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
1798#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
1799#define DMA_CSELR_C4S_Pos (12U)
1800#define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
1801#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
1802#define DMA_CSELR_C5S_Pos (16U)
1803#define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
1804#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
1805#define DMA_CSELR_C6S_Pos (20U)
1806#define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
1807#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
1808#define DMA_CSELR_C7S_Pos (24U)
1809#define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
1810#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
1811
1812/******************************************************************************/
1813/* */
1814/* External Interrupt/Event Controller (EXTI) */
1815/* */
1816/******************************************************************************/
1817
1818/******************* Bit definition for EXTI_IMR register *******************/
1819#define EXTI_IMR_IM0_Pos (0U)
1820#define EXTI_IMR_IM0_Msk (0x1U << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
1821#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
1822#define EXTI_IMR_IM1_Pos (1U)
1823#define EXTI_IMR_IM1_Msk (0x1U << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
1824#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
1825#define EXTI_IMR_IM2_Pos (2U)
1826#define EXTI_IMR_IM2_Msk (0x1U << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
1827#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
1828#define EXTI_IMR_IM3_Pos (3U)
1829#define EXTI_IMR_IM3_Msk (0x1U << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
1830#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
1831#define EXTI_IMR_IM4_Pos (4U)
1832#define EXTI_IMR_IM4_Msk (0x1U << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
1833#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
1834#define EXTI_IMR_IM5_Pos (5U)
1835#define EXTI_IMR_IM5_Msk (0x1U << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
1836#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
1837#define EXTI_IMR_IM6_Pos (6U)
1838#define EXTI_IMR_IM6_Msk (0x1U << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
1839#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
1840#define EXTI_IMR_IM7_Pos (7U)
1841#define EXTI_IMR_IM7_Msk (0x1U << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
1842#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
1843#define EXTI_IMR_IM8_Pos (8U)
1844#define EXTI_IMR_IM8_Msk (0x1U << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
1845#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
1846#define EXTI_IMR_IM9_Pos (9U)
1847#define EXTI_IMR_IM9_Msk (0x1U << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
1848#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
1849#define EXTI_IMR_IM10_Pos (10U)
1850#define EXTI_IMR_IM10_Msk (0x1U << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
1851#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
1852#define EXTI_IMR_IM11_Pos (11U)
1853#define EXTI_IMR_IM11_Msk (0x1U << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
1854#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
1855#define EXTI_IMR_IM12_Pos (12U)
1856#define EXTI_IMR_IM12_Msk (0x1U << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
1857#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
1858#define EXTI_IMR_IM13_Pos (13U)
1859#define EXTI_IMR_IM13_Msk (0x1U << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
1860#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
1861#define EXTI_IMR_IM14_Pos (14U)
1862#define EXTI_IMR_IM14_Msk (0x1U << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
1863#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
1864#define EXTI_IMR_IM15_Pos (15U)
1865#define EXTI_IMR_IM15_Msk (0x1U << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
1866#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
1867#define EXTI_IMR_IM16_Pos (16U)
1868#define EXTI_IMR_IM16_Msk (0x1U << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
1869#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
1870#define EXTI_IMR_IM17_Pos (17U)
1871#define EXTI_IMR_IM17_Msk (0x1U << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
1872#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
1873#define EXTI_IMR_IM18_Pos (18U)
1874#define EXTI_IMR_IM18_Msk (0x1U << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
1875#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
1876#define EXTI_IMR_IM19_Pos (19U)
1877#define EXTI_IMR_IM19_Msk (0x1U << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
1878#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
1879#define EXTI_IMR_IM20_Pos (20U)
1880#define EXTI_IMR_IM20_Msk (0x1U << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
1881#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
1882#define EXTI_IMR_IM21_Pos (21U)
1883#define EXTI_IMR_IM21_Msk (0x1U << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
1884#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
1885#define EXTI_IMR_IM22_Pos (22U)
1886#define EXTI_IMR_IM22_Msk (0x1U << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
1887#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
1888#define EXTI_IMR_IM23_Pos (23U)
1889#define EXTI_IMR_IM23_Msk (0x1U << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
1890#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
1891#define EXTI_IMR_IM25_Pos (25U)
1892#define EXTI_IMR_IM25_Msk (0x1U << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
1893#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
1894#define EXTI_IMR_IM26_Pos (26U)
1895#define EXTI_IMR_IM26_Msk (0x1U << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
1896#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
1897#define EXTI_IMR_IM28_Pos (28U)
1898#define EXTI_IMR_IM28_Msk (0x1U << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
1899#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
1900#define EXTI_IMR_IM29_Pos (29U)
1901#define EXTI_IMR_IM29_Msk (0x1U << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
1902#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
1903
1904#define EXTI_IMR_IM_Pos (0U)
1905#define EXTI_IMR_IM_Msk (0x36FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
1906#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
1907
1908/****************** Bit definition for EXTI_EMR register ********************/
1909#define EXTI_EMR_EM0_Pos (0U)
1910#define EXTI_EMR_EM0_Msk (0x1U << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
1911#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
1912#define EXTI_EMR_EM1_Pos (1U)
1913#define EXTI_EMR_EM1_Msk (0x1U << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
1914#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
1915#define EXTI_EMR_EM2_Pos (2U)
1916#define EXTI_EMR_EM2_Msk (0x1U << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
1917#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
1918#define EXTI_EMR_EM3_Pos (3U)
1919#define EXTI_EMR_EM3_Msk (0x1U << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
1920#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
1921#define EXTI_EMR_EM4_Pos (4U)
1922#define EXTI_EMR_EM4_Msk (0x1U << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
1923#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
1924#define EXTI_EMR_EM5_Pos (5U)
1925#define EXTI_EMR_EM5_Msk (0x1U << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
1926#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
1927#define EXTI_EMR_EM6_Pos (6U)
1928#define EXTI_EMR_EM6_Msk (0x1U << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
1929#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
1930#define EXTI_EMR_EM7_Pos (7U)
1931#define EXTI_EMR_EM7_Msk (0x1U << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
1932#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
1933#define EXTI_EMR_EM8_Pos (8U)
1934#define EXTI_EMR_EM8_Msk (0x1U << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
1935#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
1936#define EXTI_EMR_EM9_Pos (9U)
1937#define EXTI_EMR_EM9_Msk (0x1U << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
1938#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
1939#define EXTI_EMR_EM10_Pos (10U)
1940#define EXTI_EMR_EM10_Msk (0x1U << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
1941#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
1942#define EXTI_EMR_EM11_Pos (11U)
1943#define EXTI_EMR_EM11_Msk (0x1U << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
1944#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
1945#define EXTI_EMR_EM12_Pos (12U)
1946#define EXTI_EMR_EM12_Msk (0x1U << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
1947#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
1948#define EXTI_EMR_EM13_Pos (13U)
1949#define EXTI_EMR_EM13_Msk (0x1U << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
1950#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
1951#define EXTI_EMR_EM14_Pos (14U)
1952#define EXTI_EMR_EM14_Msk (0x1U << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
1953#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
1954#define EXTI_EMR_EM15_Pos (15U)
1955#define EXTI_EMR_EM15_Msk (0x1U << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
1956#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
1957#define EXTI_EMR_EM16_Pos (16U)
1958#define EXTI_EMR_EM16_Msk (0x1U << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
1959#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
1960#define EXTI_EMR_EM17_Pos (17U)
1961#define EXTI_EMR_EM17_Msk (0x1U << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
1962#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
1963#define EXTI_EMR_EM18_Pos (18U)
1964#define EXTI_EMR_EM18_Msk (0x1U << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
1965#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
1966#define EXTI_EMR_EM19_Pos (19U)
1967#define EXTI_EMR_EM19_Msk (0x1U << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
1968#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
1969#define EXTI_EMR_EM20_Pos (20U)
1970#define EXTI_EMR_EM20_Msk (0x1U << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
1971#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
1972#define EXTI_EMR_EM21_Pos (21U)
1973#define EXTI_EMR_EM21_Msk (0x1U << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
1974#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
1975#define EXTI_EMR_EM22_Pos (22U)
1976#define EXTI_EMR_EM22_Msk (0x1U << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
1977#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
1978#define EXTI_EMR_EM23_Pos (23U)
1979#define EXTI_EMR_EM23_Msk (0x1U << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
1980#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
1981#define EXTI_EMR_EM25_Pos (25U)
1982#define EXTI_EMR_EM25_Msk (0x1U << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
1983#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
1984#define EXTI_EMR_EM26_Pos (26U)
1985#define EXTI_EMR_EM26_Msk (0x1U << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
1986#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
1987#define EXTI_EMR_EM28_Pos (28U)
1988#define EXTI_EMR_EM28_Msk (0x1U << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
1989#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
1990#define EXTI_EMR_EM29_Pos (29U)
1991#define EXTI_EMR_EM29_Msk (0x1U << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
1992#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
1993
1994/******************* Bit definition for EXTI_RTSR register ******************/
1995#define EXTI_RTSR_RT0_Pos (0U)
1996#define EXTI_RTSR_RT0_Msk (0x1U << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
1997#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
1998#define EXTI_RTSR_RT1_Pos (1U)
1999#define EXTI_RTSR_RT1_Msk (0x1U << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
2000#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
2001#define EXTI_RTSR_RT2_Pos (2U)
2002#define EXTI_RTSR_RT2_Msk (0x1U << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
2003#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
2004#define EXTI_RTSR_RT3_Pos (3U)
2005#define EXTI_RTSR_RT3_Msk (0x1U << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
2006#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
2007#define EXTI_RTSR_RT4_Pos (4U)
2008#define EXTI_RTSR_RT4_Msk (0x1U << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
2009#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
2010#define EXTI_RTSR_RT5_Pos (5U)
2011#define EXTI_RTSR_RT5_Msk (0x1U << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
2012#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
2013#define EXTI_RTSR_RT6_Pos (6U)
2014#define EXTI_RTSR_RT6_Msk (0x1U << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
2015#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
2016#define EXTI_RTSR_RT7_Pos (7U)
2017#define EXTI_RTSR_RT7_Msk (0x1U << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
2018#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
2019#define EXTI_RTSR_RT8_Pos (8U)
2020#define EXTI_RTSR_RT8_Msk (0x1U << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
2021#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
2022#define EXTI_RTSR_RT9_Pos (9U)
2023#define EXTI_RTSR_RT9_Msk (0x1U << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
2024#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
2025#define EXTI_RTSR_RT10_Pos (10U)
2026#define EXTI_RTSR_RT10_Msk (0x1U << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
2027#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
2028#define EXTI_RTSR_RT11_Pos (11U)
2029#define EXTI_RTSR_RT11_Msk (0x1U << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
2030#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
2031#define EXTI_RTSR_RT12_Pos (12U)
2032#define EXTI_RTSR_RT12_Msk (0x1U << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
2033#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
2034#define EXTI_RTSR_RT13_Pos (13U)
2035#define EXTI_RTSR_RT13_Msk (0x1U << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
2036#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
2037#define EXTI_RTSR_RT14_Pos (14U)
2038#define EXTI_RTSR_RT14_Msk (0x1U << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
2039#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
2040#define EXTI_RTSR_RT15_Pos (15U)
2041#define EXTI_RTSR_RT15_Msk (0x1U << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
2042#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
2043#define EXTI_RTSR_RT16_Pos (16U)
2044#define EXTI_RTSR_RT16_Msk (0x1U << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
2045#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
2046#define EXTI_RTSR_RT17_Pos (17U)
2047#define EXTI_RTSR_RT17_Msk (0x1U << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
2048#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
2049#define EXTI_RTSR_RT19_Pos (19U)
2050#define EXTI_RTSR_RT19_Msk (0x1U << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
2051#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
2052#define EXTI_RTSR_RT20_Pos (20U)
2053#define EXTI_RTSR_RT20_Msk (0x1U << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
2054#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
2055#define EXTI_RTSR_RT21_Pos (21U)
2056#define EXTI_RTSR_RT21_Msk (0x1U << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
2057#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
2058#define EXTI_RTSR_RT22_Pos (22U)
2059#define EXTI_RTSR_RT22_Msk (0x1U << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
2060#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
2061
2062/* Legacy defines */
2063#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
2064#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
2065#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
2066#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
2067#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
2068#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
2069#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
2070#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
2071#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
2072#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
2073#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
2074#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
2075#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
2076#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
2077#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
2078#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
2079#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
2080#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
2081#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
2082#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
2083#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
2084#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
2085
2086/******************* Bit definition for EXTI_FTSR register *******************/
2087#define EXTI_FTSR_FT0_Pos (0U)
2088#define EXTI_FTSR_FT0_Msk (0x1U << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
2089#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
2090#define EXTI_FTSR_FT1_Pos (1U)
2091#define EXTI_FTSR_FT1_Msk (0x1U << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
2092#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
2093#define EXTI_FTSR_FT2_Pos (2U)
2094#define EXTI_FTSR_FT2_Msk (0x1U << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
2095#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
2096#define EXTI_FTSR_FT3_Pos (3U)
2097#define EXTI_FTSR_FT3_Msk (0x1U << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
2098#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
2099#define EXTI_FTSR_FT4_Pos (4U)
2100#define EXTI_FTSR_FT4_Msk (0x1U << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
2101#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
2102#define EXTI_FTSR_FT5_Pos (5U)
2103#define EXTI_FTSR_FT5_Msk (0x1U << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
2104#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
2105#define EXTI_FTSR_FT6_Pos (6U)
2106#define EXTI_FTSR_FT6_Msk (0x1U << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
2107#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
2108#define EXTI_FTSR_FT7_Pos (7U)
2109#define EXTI_FTSR_FT7_Msk (0x1U << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
2110#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
2111#define EXTI_FTSR_FT8_Pos (8U)
2112#define EXTI_FTSR_FT8_Msk (0x1U << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
2113#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
2114#define EXTI_FTSR_FT9_Pos (9U)
2115#define EXTI_FTSR_FT9_Msk (0x1U << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
2116#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
2117#define EXTI_FTSR_FT10_Pos (10U)
2118#define EXTI_FTSR_FT10_Msk (0x1U << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
2119#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
2120#define EXTI_FTSR_FT11_Pos (11U)
2121#define EXTI_FTSR_FT11_Msk (0x1U << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
2122#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
2123#define EXTI_FTSR_FT12_Pos (12U)
2124#define EXTI_FTSR_FT12_Msk (0x1U << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
2125#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
2126#define EXTI_FTSR_FT13_Pos (13U)
2127#define EXTI_FTSR_FT13_Msk (0x1U << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
2128#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
2129#define EXTI_FTSR_FT14_Pos (14U)
2130#define EXTI_FTSR_FT14_Msk (0x1U << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
2131#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
2132#define EXTI_FTSR_FT15_Pos (15U)
2133#define EXTI_FTSR_FT15_Msk (0x1U << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
2134#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
2135#define EXTI_FTSR_FT16_Pos (16U)
2136#define EXTI_FTSR_FT16_Msk (0x1U << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
2137#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
2138#define EXTI_FTSR_FT17_Pos (17U)
2139#define EXTI_FTSR_FT17_Msk (0x1U << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
2140#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
2141#define EXTI_FTSR_FT19_Pos (19U)
2142#define EXTI_FTSR_FT19_Msk (0x1U << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
2143#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
2144#define EXTI_FTSR_FT20_Pos (20U)
2145#define EXTI_FTSR_FT20_Msk (0x1U << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
2146#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
2147#define EXTI_FTSR_FT21_Pos (21U)
2148#define EXTI_FTSR_FT21_Msk (0x1U << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
2149#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
2150#define EXTI_FTSR_FT22_Pos (22U)
2151#define EXTI_FTSR_FT22_Msk (0x1U << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
2152#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
2153
2154/* Legacy defines */
2155#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
2156#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
2157#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
2158#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
2159#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
2160#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
2161#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
2162#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
2163#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
2164#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
2165#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
2166#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
2167#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
2168#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
2169#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
2170#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
2171#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
2172#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
2173#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
2174#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
2175#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
2176#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
2177
2178/******************* Bit definition for EXTI_SWIER register *******************/
2179#define EXTI_SWIER_SWI0_Pos (0U)
2180#define EXTI_SWIER_SWI0_Msk (0x1U << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
2181#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
2182#define EXTI_SWIER_SWI1_Pos (1U)
2183#define EXTI_SWIER_SWI1_Msk (0x1U << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
2184#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
2185#define EXTI_SWIER_SWI2_Pos (2U)
2186#define EXTI_SWIER_SWI2_Msk (0x1U << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
2187#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
2188#define EXTI_SWIER_SWI3_Pos (3U)
2189#define EXTI_SWIER_SWI3_Msk (0x1U << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
2190#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
2191#define EXTI_SWIER_SWI4_Pos (4U)
2192#define EXTI_SWIER_SWI4_Msk (0x1U << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
2193#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
2194#define EXTI_SWIER_SWI5_Pos (5U)
2195#define EXTI_SWIER_SWI5_Msk (0x1U << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
2196#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
2197#define EXTI_SWIER_SWI6_Pos (6U)
2198#define EXTI_SWIER_SWI6_Msk (0x1U << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
2199#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
2200#define EXTI_SWIER_SWI7_Pos (7U)
2201#define EXTI_SWIER_SWI7_Msk (0x1U << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
2202#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
2203#define EXTI_SWIER_SWI8_Pos (8U)
2204#define EXTI_SWIER_SWI8_Msk (0x1U << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
2205#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
2206#define EXTI_SWIER_SWI9_Pos (9U)
2207#define EXTI_SWIER_SWI9_Msk (0x1U << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
2208#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
2209#define EXTI_SWIER_SWI10_Pos (10U)
2210#define EXTI_SWIER_SWI10_Msk (0x1U << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
2211#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
2212#define EXTI_SWIER_SWI11_Pos (11U)
2213#define EXTI_SWIER_SWI11_Msk (0x1U << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
2214#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
2215#define EXTI_SWIER_SWI12_Pos (12U)
2216#define EXTI_SWIER_SWI12_Msk (0x1U << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
2217#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
2218#define EXTI_SWIER_SWI13_Pos (13U)
2219#define EXTI_SWIER_SWI13_Msk (0x1U << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
2220#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
2221#define EXTI_SWIER_SWI14_Pos (14U)
2222#define EXTI_SWIER_SWI14_Msk (0x1U << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
2223#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
2224#define EXTI_SWIER_SWI15_Pos (15U)
2225#define EXTI_SWIER_SWI15_Msk (0x1U << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
2226#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
2227#define EXTI_SWIER_SWI16_Pos (16U)
2228#define EXTI_SWIER_SWI16_Msk (0x1U << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
2229#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
2230#define EXTI_SWIER_SWI17_Pos (17U)
2231#define EXTI_SWIER_SWI17_Msk (0x1U << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
2232#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
2233#define EXTI_SWIER_SWI19_Pos (19U)
2234#define EXTI_SWIER_SWI19_Msk (0x1U << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
2235#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
2236#define EXTI_SWIER_SWI20_Pos (20U)
2237#define EXTI_SWIER_SWI20_Msk (0x1U << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
2238#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
2239#define EXTI_SWIER_SWI21_Pos (21U)
2240#define EXTI_SWIER_SWI21_Msk (0x1U << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
2241#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
2242#define EXTI_SWIER_SWI22_Pos (22U)
2243#define EXTI_SWIER_SWI22_Msk (0x1U << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
2244#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
2245
2246/* Legacy defines */
2247#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
2248#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
2249#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
2250#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
2251#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
2252#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
2253#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
2254#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
2255#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
2256#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
2257#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
2258#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
2259#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
2260#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
2261#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
2262#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
2263#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
2264#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
2265#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
2266#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
2267#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
2268#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
2269
2270/****************** Bit definition for EXTI_PR register *********************/
2271#define EXTI_PR_PIF0_Pos (0U)
2272#define EXTI_PR_PIF0_Msk (0x1U << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
2273#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
2274#define EXTI_PR_PIF1_Pos (1U)
2275#define EXTI_PR_PIF1_Msk (0x1U << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
2276#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
2277#define EXTI_PR_PIF2_Pos (2U)
2278#define EXTI_PR_PIF2_Msk (0x1U << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
2279#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
2280#define EXTI_PR_PIF3_Pos (3U)
2281#define EXTI_PR_PIF3_Msk (0x1U << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
2282#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
2283#define EXTI_PR_PIF4_Pos (4U)
2284#define EXTI_PR_PIF4_Msk (0x1U << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
2285#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
2286#define EXTI_PR_PIF5_Pos (5U)
2287#define EXTI_PR_PIF5_Msk (0x1U << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
2288#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
2289#define EXTI_PR_PIF6_Pos (6U)
2290#define EXTI_PR_PIF6_Msk (0x1U << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
2291#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
2292#define EXTI_PR_PIF7_Pos (7U)
2293#define EXTI_PR_PIF7_Msk (0x1U << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
2294#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
2295#define EXTI_PR_PIF8_Pos (8U)
2296#define EXTI_PR_PIF8_Msk (0x1U << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
2297#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
2298#define EXTI_PR_PIF9_Pos (9U)
2299#define EXTI_PR_PIF9_Msk (0x1U << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
2300#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
2301#define EXTI_PR_PIF10_Pos (10U)
2302#define EXTI_PR_PIF10_Msk (0x1U << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
2303#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
2304#define EXTI_PR_PIF11_Pos (11U)
2305#define EXTI_PR_PIF11_Msk (0x1U << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
2306#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
2307#define EXTI_PR_PIF12_Pos (12U)
2308#define EXTI_PR_PIF12_Msk (0x1U << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
2309#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
2310#define EXTI_PR_PIF13_Pos (13U)
2311#define EXTI_PR_PIF13_Msk (0x1U << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
2312#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
2313#define EXTI_PR_PIF14_Pos (14U)
2314#define EXTI_PR_PIF14_Msk (0x1U << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
2315#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
2316#define EXTI_PR_PIF15_Pos (15U)
2317#define EXTI_PR_PIF15_Msk (0x1U << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
2318#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
2319#define EXTI_PR_PIF16_Pos (16U)
2320#define EXTI_PR_PIF16_Msk (0x1U << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
2321#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
2322#define EXTI_PR_PIF17_Pos (17U)
2323#define EXTI_PR_PIF17_Msk (0x1U << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
2324#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
2325#define EXTI_PR_PIF19_Pos (19U)
2326#define EXTI_PR_PIF19_Msk (0x1U << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
2327#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
2328#define EXTI_PR_PIF20_Pos (20U)
2329#define EXTI_PR_PIF20_Msk (0x1U << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
2330#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
2331#define EXTI_PR_PIF21_Pos (21U)
2332#define EXTI_PR_PIF21_Msk (0x1U << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
2333#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
2334#define EXTI_PR_PIF22_Pos (22U)
2335#define EXTI_PR_PIF22_Msk (0x1U << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
2336#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
2337
2338/* Legacy defines */
2339#define EXTI_PR_PR0 EXTI_PR_PIF0
2340#define EXTI_PR_PR1 EXTI_PR_PIF1
2341#define EXTI_PR_PR2 EXTI_PR_PIF2
2342#define EXTI_PR_PR3 EXTI_PR_PIF3
2343#define EXTI_PR_PR4 EXTI_PR_PIF4
2344#define EXTI_PR_PR5 EXTI_PR_PIF5
2345#define EXTI_PR_PR6 EXTI_PR_PIF6
2346#define EXTI_PR_PR7 EXTI_PR_PIF7
2347#define EXTI_PR_PR8 EXTI_PR_PIF8
2348#define EXTI_PR_PR9 EXTI_PR_PIF9
2349#define EXTI_PR_PR10 EXTI_PR_PIF10
2350#define EXTI_PR_PR11 EXTI_PR_PIF11
2351#define EXTI_PR_PR12 EXTI_PR_PIF12
2352#define EXTI_PR_PR13 EXTI_PR_PIF13
2353#define EXTI_PR_PR14 EXTI_PR_PIF14
2354#define EXTI_PR_PR15 EXTI_PR_PIF15
2355#define EXTI_PR_PR16 EXTI_PR_PIF16
2356#define EXTI_PR_PR17 EXTI_PR_PIF17
2357#define EXTI_PR_PR19 EXTI_PR_PIF19
2358#define EXTI_PR_PR20 EXTI_PR_PIF20
2359#define EXTI_PR_PR21 EXTI_PR_PIF21
2360#define EXTI_PR_PR22 EXTI_PR_PIF22
2361
2362/******************************************************************************/
2363/* */
2364/* FLASH and Option Bytes Registers */
2365/* */
2366/******************************************************************************/
2367
2368/******************* Bit definition for FLASH_ACR register ******************/
2369#define FLASH_ACR_LATENCY_Pos (0U)
2370#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
2371#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
2372#define FLASH_ACR_PRFTEN_Pos (1U)
2373#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
2374#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
2375#define FLASH_ACR_SLEEP_PD_Pos (3U)
2376#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
2377#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
2378#define FLASH_ACR_RUN_PD_Pos (4U)
2379#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
2380#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
2381#define FLASH_ACR_DISAB_BUF_Pos (5U)
2382#define FLASH_ACR_DISAB_BUF_Msk (0x1U << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
2383#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
2384#define FLASH_ACR_PRE_READ_Pos (6U)
2385#define FLASH_ACR_PRE_READ_Msk (0x1U << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
2386#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
2387
2388/******************* Bit definition for FLASH_PECR register ******************/
2389#define FLASH_PECR_PELOCK_Pos (0U)
2390#define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
2391#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
2392#define FLASH_PECR_PRGLOCK_Pos (1U)
2393#define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
2394#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
2395#define FLASH_PECR_OPTLOCK_Pos (2U)
2396#define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
2397#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
2398#define FLASH_PECR_PROG_Pos (3U)
2399#define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
2400#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
2401#define FLASH_PECR_DATA_Pos (4U)
2402#define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
2403#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
2404#define FLASH_PECR_FIX_Pos (8U)
2405#define FLASH_PECR_FIX_Msk (0x1U << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
2406#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
2407#define FLASH_PECR_ERASE_Pos (9U)
2408#define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
2409#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
2410#define FLASH_PECR_FPRG_Pos (10U)
2411#define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
2412#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
2413#define FLASH_PECR_EOPIE_Pos (16U)
2414#define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
2415#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
2416#define FLASH_PECR_ERRIE_Pos (17U)
2417#define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
2418#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
2419#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
2420#define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
2421#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
2422#define FLASH_PECR_HALF_ARRAY_Pos (19U)
2423#define FLASH_PECR_HALF_ARRAY_Msk (0x1U << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
2424#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
2425
2426/****************** Bit definition for FLASH_PDKEYR register ******************/
2427#define FLASH_PDKEYR_PDKEYR_Pos (0U)
2428#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
2429#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
2430
2431/****************** Bit definition for FLASH_PEKEYR register ******************/
2432#define FLASH_PEKEYR_PEKEYR_Pos (0U)
2433#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
2434#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
2435
2436/****************** Bit definition for FLASH_PRGKEYR register ******************/
2437#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
2438#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
2439#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
2440
2441/****************** Bit definition for FLASH_OPTKEYR register ******************/
2442#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
2443#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
2444#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
2445
2446/****************** Bit definition for FLASH_SR register *******************/
2447#define FLASH_SR_BSY_Pos (0U)
2448#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
2449#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
2450#define FLASH_SR_EOP_Pos (1U)
2451#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
2452#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
2453#define FLASH_SR_HVOFF_Pos (2U)
2454#define FLASH_SR_HVOFF_Msk (0x1U << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
2455#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
2456#define FLASH_SR_READY_Pos (3U)
2457#define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */
2458#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
2459
2460#define FLASH_SR_WRPERR_Pos (8U)
2461#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
2462#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
2463#define FLASH_SR_PGAERR_Pos (9U)
2464#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
2465#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
2466#define FLASH_SR_SIZERR_Pos (10U)
2467#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
2468#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
2469#define FLASH_SR_OPTVERR_Pos (11U)
2470#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
2471#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
2472#define FLASH_SR_RDERR_Pos (13U)
2473#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
2474#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
2475#define FLASH_SR_NOTZEROERR_Pos (16U)
2476#define FLASH_SR_NOTZEROERR_Msk (0x1U << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
2477#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
2478#define FLASH_SR_FWWERR_Pos (17U)
2479#define FLASH_SR_FWWERR_Msk (0x1U << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
2480#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
2481
2482/* Legacy defines */
2483#define FLASH_SR_FWWER FLASH_SR_FWWERR
2484#define FLASH_SR_ENHV FLASH_SR_HVOFF
2485#define FLASH_SR_ENDHV FLASH_SR_HVOFF
2486
2487/****************** Bit definition for FLASH_OPTR register *******************/
2488#define FLASH_OPTR_RDPROT_Pos (0U)
2489#define FLASH_OPTR_RDPROT_Msk (0xFFU << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
2490#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
2491#define FLASH_OPTR_WPRMOD_Pos (8U)
2492#define FLASH_OPTR_WPRMOD_Msk (0x1U << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
2493#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
2494#define FLASH_OPTR_BOR_LEV_Pos (16U)
2495#define FLASH_OPTR_BOR_LEV_Msk (0xFU << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
2496#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
2497#define FLASH_OPTR_IWDG_SW_Pos (20U)
2498#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
2499#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
2500#define FLASH_OPTR_nRST_STOP_Pos (21U)
2501#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
2502#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
2503#define FLASH_OPTR_nRST_STDBY_Pos (22U)
2504#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
2505#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
2506#define FLASH_OPTR_USER_Pos (20U)
2507#define FLASH_OPTR_USER_Msk (0x7U << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
2508#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
2509#define FLASH_OPTR_BOOT1_Pos (31U)
2510#define FLASH_OPTR_BOOT1_Msk (0x1U << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
2511#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
2512
2513/****************** Bit definition for FLASH_WRPR register ******************/
2514#define FLASH_WRPR_WRP_Pos (0U)
2515#define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
2516#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
2517
2518/******************************************************************************/
2519/* */
2520/* General Purpose IOs (GPIO) */
2521/* */
2522/******************************************************************************/
2523/******************* Bit definition for GPIO_MODER register *****************/
2524#define GPIO_MODER_MODE0_Pos (0U)
2525#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
2526#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
2527#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
2528#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
2529#define GPIO_MODER_MODE1_Pos (2U)
2530#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
2531#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
2532#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
2533#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
2534#define GPIO_MODER_MODE2_Pos (4U)
2535#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
2536#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
2537#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
2538#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
2539#define GPIO_MODER_MODE3_Pos (6U)
2540#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
2541#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
2542#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
2543#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
2544#define GPIO_MODER_MODE4_Pos (8U)
2545#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
2546#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
2547#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
2548#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
2549#define GPIO_MODER_MODE5_Pos (10U)
2550#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
2551#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
2552#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
2553#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
2554#define GPIO_MODER_MODE6_Pos (12U)
2555#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
2556#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
2557#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
2558#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
2559#define GPIO_MODER_MODE7_Pos (14U)
2560#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
2561#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
2562#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
2563#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
2564#define GPIO_MODER_MODE8_Pos (16U)
2565#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
2566#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
2567#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
2568#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
2569#define GPIO_MODER_MODE9_Pos (18U)
2570#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
2571#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
2572#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
2573#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
2574#define GPIO_MODER_MODE10_Pos (20U)
2575#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
2576#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
2577#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
2578#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
2579#define GPIO_MODER_MODE11_Pos (22U)
2580#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
2581#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
2582#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
2583#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
2584#define GPIO_MODER_MODE12_Pos (24U)
2585#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
2586#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
2587#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
2588#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
2589#define GPIO_MODER_MODE13_Pos (26U)
2590#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
2591#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
2592#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
2593#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
2594#define GPIO_MODER_MODE14_Pos (28U)
2595#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
2596#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
2597#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
2598#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
2599#define GPIO_MODER_MODE15_Pos (30U)
2600#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
2601#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
2602#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
2603#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
2604
2605/****************** Bit definition for GPIO_OTYPER register *****************/
2606#define GPIO_OTYPER_OT_0 (0x00000001U)
2607#define GPIO_OTYPER_OT_1 (0x00000002U)
2608#define GPIO_OTYPER_OT_2 (0x00000004U)
2609#define GPIO_OTYPER_OT_3 (0x00000008U)
2610#define GPIO_OTYPER_OT_4 (0x00000010U)
2611#define GPIO_OTYPER_OT_5 (0x00000020U)
2612#define GPIO_OTYPER_OT_6 (0x00000040U)
2613#define GPIO_OTYPER_OT_7 (0x00000080U)
2614#define GPIO_OTYPER_OT_8 (0x00000100U)
2615#define GPIO_OTYPER_OT_9 (0x00000200U)
2616#define GPIO_OTYPER_OT_10 (0x00000400U)
2617#define GPIO_OTYPER_OT_11 (0x00000800U)
2618#define GPIO_OTYPER_OT_12 (0x00001000U)
2619#define GPIO_OTYPER_OT_13 (0x00002000U)
2620#define GPIO_OTYPER_OT_14 (0x00004000U)
2621#define GPIO_OTYPER_OT_15 (0x00008000U)
2622
2623/**************** Bit definition for GPIO_OSPEEDR register ******************/
2624#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
2625#define GPIO_OSPEEDER_OSPEED0_Msk (0x3U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
2626#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
2627#define GPIO_OSPEEDER_OSPEED0_0 (0x1U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
2628#define GPIO_OSPEEDER_OSPEED0_1 (0x2U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
2629#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
2630#define GPIO_OSPEEDER_OSPEED1_Msk (0x3U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
2631#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
2632#define GPIO_OSPEEDER_OSPEED1_0 (0x1U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
2633#define GPIO_OSPEEDER_OSPEED1_1 (0x2U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
2634#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
2635#define GPIO_OSPEEDER_OSPEED2_Msk (0x3U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
2636#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
2637#define GPIO_OSPEEDER_OSPEED2_0 (0x1U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
2638#define GPIO_OSPEEDER_OSPEED2_1 (0x2U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
2639#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
2640#define GPIO_OSPEEDER_OSPEED3_Msk (0x3U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
2641#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
2642#define GPIO_OSPEEDER_OSPEED3_0 (0x1U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
2643#define GPIO_OSPEEDER_OSPEED3_1 (0x2U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
2644#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
2645#define GPIO_OSPEEDER_OSPEED4_Msk (0x3U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
2646#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
2647#define GPIO_OSPEEDER_OSPEED4_0 (0x1U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
2648#define GPIO_OSPEEDER_OSPEED4_1 (0x2U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
2649#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
2650#define GPIO_OSPEEDER_OSPEED5_Msk (0x3U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
2651#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
2652#define GPIO_OSPEEDER_OSPEED5_0 (0x1U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
2653#define GPIO_OSPEEDER_OSPEED5_1 (0x2U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
2654#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
2655#define GPIO_OSPEEDER_OSPEED6_Msk (0x3U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
2656#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
2657#define GPIO_OSPEEDER_OSPEED6_0 (0x1U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
2658#define GPIO_OSPEEDER_OSPEED6_1 (0x2U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
2659#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
2660#define GPIO_OSPEEDER_OSPEED7_Msk (0x3U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
2661#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
2662#define GPIO_OSPEEDER_OSPEED7_0 (0x1U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
2663#define GPIO_OSPEEDER_OSPEED7_1 (0x2U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
2664#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
2665#define GPIO_OSPEEDER_OSPEED8_Msk (0x3U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
2666#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
2667#define GPIO_OSPEEDER_OSPEED8_0 (0x1U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
2668#define GPIO_OSPEEDER_OSPEED8_1 (0x2U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
2669#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
2670#define GPIO_OSPEEDER_OSPEED9_Msk (0x3U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
2671#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
2672#define GPIO_OSPEEDER_OSPEED9_0 (0x1U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
2673#define GPIO_OSPEEDER_OSPEED9_1 (0x2U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
2674#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
2675#define GPIO_OSPEEDER_OSPEED10_Msk (0x3U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
2676#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
2677#define GPIO_OSPEEDER_OSPEED10_0 (0x1U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
2678#define GPIO_OSPEEDER_OSPEED10_1 (0x2U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
2679#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
2680#define GPIO_OSPEEDER_OSPEED11_Msk (0x3U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
2681#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
2682#define GPIO_OSPEEDER_OSPEED11_0 (0x1U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
2683#define GPIO_OSPEEDER_OSPEED11_1 (0x2U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
2684#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
2685#define GPIO_OSPEEDER_OSPEED12_Msk (0x3U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
2686#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
2687#define GPIO_OSPEEDER_OSPEED12_0 (0x1U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
2688#define GPIO_OSPEEDER_OSPEED12_1 (0x2U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
2689#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
2690#define GPIO_OSPEEDER_OSPEED13_Msk (0x3U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
2691#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
2692#define GPIO_OSPEEDER_OSPEED13_0 (0x1U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
2693#define GPIO_OSPEEDER_OSPEED13_1 (0x2U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
2694#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
2695#define GPIO_OSPEEDER_OSPEED14_Msk (0x3U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
2696#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
2697#define GPIO_OSPEEDER_OSPEED14_0 (0x1U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
2698#define GPIO_OSPEEDER_OSPEED14_1 (0x2U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
2699#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
2700#define GPIO_OSPEEDER_OSPEED15_Msk (0x3U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
2701#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
2702#define GPIO_OSPEEDER_OSPEED15_0 (0x1U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
2703#define GPIO_OSPEEDER_OSPEED15_1 (0x2U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
2704
2705/******************* Bit definition for GPIO_PUPDR register ******************/
2706#define GPIO_PUPDR_PUPD0_Pos (0U)
2707#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
2708#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
2709#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
2710#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
2711#define GPIO_PUPDR_PUPD1_Pos (2U)
2712#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
2713#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
2714#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
2715#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
2716#define GPIO_PUPDR_PUPD2_Pos (4U)
2717#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
2718#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
2719#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
2720#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
2721#define GPIO_PUPDR_PUPD3_Pos (6U)
2722#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
2723#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
2724#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
2725#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
2726#define GPIO_PUPDR_PUPD4_Pos (8U)
2727#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
2728#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
2729#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
2730#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
2731#define GPIO_PUPDR_PUPD5_Pos (10U)
2732#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
2733#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
2734#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
2735#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
2736#define GPIO_PUPDR_PUPD6_Pos (12U)
2737#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
2738#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
2739#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
2740#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
2741#define GPIO_PUPDR_PUPD7_Pos (14U)
2742#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
2743#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
2744#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
2745#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
2746#define GPIO_PUPDR_PUPD8_Pos (16U)
2747#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
2748#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
2749#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
2750#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
2751#define GPIO_PUPDR_PUPD9_Pos (18U)
2752#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
2753#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
2754#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
2755#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
2756#define GPIO_PUPDR_PUPD10_Pos (20U)
2757#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
2758#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
2759#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
2760#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
2761#define GPIO_PUPDR_PUPD11_Pos (22U)
2762#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
2763#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
2764#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
2765#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
2766#define GPIO_PUPDR_PUPD12_Pos (24U)
2767#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
2768#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
2769#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
2770#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
2771#define GPIO_PUPDR_PUPD13_Pos (26U)
2772#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
2773#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
2774#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
2775#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
2776#define GPIO_PUPDR_PUPD14_Pos (28U)
2777#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
2778#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
2779#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
2780#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
2781#define GPIO_PUPDR_PUPD15_Pos (30U)
2782#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
2783#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
2784#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
2785#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
2786
2787/******************* Bit definition for GPIO_IDR register *******************/
2788#define GPIO_IDR_ID0_Pos (0U)
2789#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
2790#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
2791#define GPIO_IDR_ID1_Pos (1U)
2792#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
2793#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
2794#define GPIO_IDR_ID2_Pos (2U)
2795#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
2796#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
2797#define GPIO_IDR_ID3_Pos (3U)
2798#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
2799#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
2800#define GPIO_IDR_ID4_Pos (4U)
2801#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
2802#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
2803#define GPIO_IDR_ID5_Pos (5U)
2804#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
2805#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
2806#define GPIO_IDR_ID6_Pos (6U)
2807#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
2808#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
2809#define GPIO_IDR_ID7_Pos (7U)
2810#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
2811#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
2812#define GPIO_IDR_ID8_Pos (8U)
2813#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
2814#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
2815#define GPIO_IDR_ID9_Pos (9U)
2816#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
2817#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
2818#define GPIO_IDR_ID10_Pos (10U)
2819#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
2820#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
2821#define GPIO_IDR_ID11_Pos (11U)
2822#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
2823#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
2824#define GPIO_IDR_ID12_Pos (12U)
2825#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
2826#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
2827#define GPIO_IDR_ID13_Pos (13U)
2828#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
2829#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
2830#define GPIO_IDR_ID14_Pos (14U)
2831#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
2832#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
2833#define GPIO_IDR_ID15_Pos (15U)
2834#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
2835#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
2836
2837/****************** Bit definition for GPIO_ODR register ********************/
2838#define GPIO_ODR_OD0_Pos (0U)
2839#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
2840#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
2841#define GPIO_ODR_OD1_Pos (1U)
2842#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
2843#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
2844#define GPIO_ODR_OD2_Pos (2U)
2845#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
2846#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
2847#define GPIO_ODR_OD3_Pos (3U)
2848#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
2849#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
2850#define GPIO_ODR_OD4_Pos (4U)
2851#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
2852#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
2853#define GPIO_ODR_OD5_Pos (5U)
2854#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
2855#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
2856#define GPIO_ODR_OD6_Pos (6U)
2857#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
2858#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
2859#define GPIO_ODR_OD7_Pos (7U)
2860#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
2861#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
2862#define GPIO_ODR_OD8_Pos (8U)
2863#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
2864#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
2865#define GPIO_ODR_OD9_Pos (9U)
2866#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
2867#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
2868#define GPIO_ODR_OD10_Pos (10U)
2869#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
2870#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
2871#define GPIO_ODR_OD11_Pos (11U)
2872#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
2873#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
2874#define GPIO_ODR_OD12_Pos (12U)
2875#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
2876#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
2877#define GPIO_ODR_OD13_Pos (13U)
2878#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
2879#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
2880#define GPIO_ODR_OD14_Pos (14U)
2881#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
2882#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
2883#define GPIO_ODR_OD15_Pos (15U)
2884#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
2885#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
2886
2887/****************** Bit definition for GPIO_BSRR register ********************/
2888#define GPIO_BSRR_BS_0 (0x00000001U)
2889#define GPIO_BSRR_BS_1 (0x00000002U)
2890#define GPIO_BSRR_BS_2 (0x00000004U)
2891#define GPIO_BSRR_BS_3 (0x00000008U)
2892#define GPIO_BSRR_BS_4 (0x00000010U)
2893#define GPIO_BSRR_BS_5 (0x00000020U)
2894#define GPIO_BSRR_BS_6 (0x00000040U)
2895#define GPIO_BSRR_BS_7 (0x00000080U)
2896#define GPIO_BSRR_BS_8 (0x00000100U)
2897#define GPIO_BSRR_BS_9 (0x00000200U)
2898#define GPIO_BSRR_BS_10 (0x00000400U)
2899#define GPIO_BSRR_BS_11 (0x00000800U)
2900#define GPIO_BSRR_BS_12 (0x00001000U)
2901#define GPIO_BSRR_BS_13 (0x00002000U)
2902#define GPIO_BSRR_BS_14 (0x00004000U)
2903#define GPIO_BSRR_BS_15 (0x00008000U)
2904#define GPIO_BSRR_BR_0 (0x00010000U)
2905#define GPIO_BSRR_BR_1 (0x00020000U)
2906#define GPIO_BSRR_BR_2 (0x00040000U)
2907#define GPIO_BSRR_BR_3 (0x00080000U)
2908#define GPIO_BSRR_BR_4 (0x00100000U)
2909#define GPIO_BSRR_BR_5 (0x00200000U)
2910#define GPIO_BSRR_BR_6 (0x00400000U)
2911#define GPIO_BSRR_BR_7 (0x00800000U)
2912#define GPIO_BSRR_BR_8 (0x01000000U)
2913#define GPIO_BSRR_BR_9 (0x02000000U)
2914#define GPIO_BSRR_BR_10 (0x04000000U)
2915#define GPIO_BSRR_BR_11 (0x08000000U)
2916#define GPIO_BSRR_BR_12 (0x10000000U)
2917#define GPIO_BSRR_BR_13 (0x20000000U)
2918#define GPIO_BSRR_BR_14 (0x40000000U)
2919#define GPIO_BSRR_BR_15 (0x80000000U)
2920
2921/****************** Bit definition for GPIO_LCKR register ********************/
2922#define GPIO_LCKR_LCK0_Pos (0U)
2923#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
2924#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
2925#define GPIO_LCKR_LCK1_Pos (1U)
2926#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
2927#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
2928#define GPIO_LCKR_LCK2_Pos (2U)
2929#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
2930#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
2931#define GPIO_LCKR_LCK3_Pos (3U)
2932#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
2933#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
2934#define GPIO_LCKR_LCK4_Pos (4U)
2935#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
2936#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
2937#define GPIO_LCKR_LCK5_Pos (5U)
2938#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
2939#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
2940#define GPIO_LCKR_LCK6_Pos (6U)
2941#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
2942#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
2943#define GPIO_LCKR_LCK7_Pos (7U)
2944#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
2945#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
2946#define GPIO_LCKR_LCK8_Pos (8U)
2947#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
2948#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
2949#define GPIO_LCKR_LCK9_Pos (9U)
2950#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
2951#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
2952#define GPIO_LCKR_LCK10_Pos (10U)
2953#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
2954#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
2955#define GPIO_LCKR_LCK11_Pos (11U)
2956#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
2957#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
2958#define GPIO_LCKR_LCK12_Pos (12U)
2959#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
2960#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
2961#define GPIO_LCKR_LCK13_Pos (13U)
2962#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
2963#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
2964#define GPIO_LCKR_LCK14_Pos (14U)
2965#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
2966#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
2967#define GPIO_LCKR_LCK15_Pos (15U)
2968#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
2969#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
2970#define GPIO_LCKR_LCKK_Pos (16U)
2971#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
2972#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
2973
2974/****************** Bit definition for GPIO_AFRL register ********************/
2975#define GPIO_AFRL_AFRL0_Pos (0U)
2976#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
2977#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
2978#define GPIO_AFRL_AFRL1_Pos (4U)
2979#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
2980#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
2981#define GPIO_AFRL_AFRL2_Pos (8U)
2982#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
2983#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
2984#define GPIO_AFRL_AFRL3_Pos (12U)
2985#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
2986#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
2987#define GPIO_AFRL_AFRL4_Pos (16U)
2988#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
2989#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
2990#define GPIO_AFRL_AFRL5_Pos (20U)
2991#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
2992#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
2993#define GPIO_AFRL_AFRL6_Pos (24U)
2994#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
2995#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
2996#define GPIO_AFRL_AFRL7_Pos (28U)
2997#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
2998#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
2999
3000/****************** Bit definition for GPIO_AFRH register ********************/
3001#define GPIO_AFRH_AFRH0_Pos (0U)
3002#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
3003#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
3004#define GPIO_AFRH_AFRH1_Pos (4U)
3005#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
3006#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
3007#define GPIO_AFRH_AFRH2_Pos (8U)
3008#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
3009#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
3010#define GPIO_AFRH_AFRH3_Pos (12U)
3011#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
3012#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
3013#define GPIO_AFRH_AFRH4_Pos (16U)
3014#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
3015#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
3016#define GPIO_AFRH_AFRH5_Pos (20U)
3017#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
3018#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
3019#define GPIO_AFRH_AFRH6_Pos (24U)
3020#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
3021#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
3022#define GPIO_AFRH_AFRH7_Pos (28U)
3023#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
3024#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
3025
3026/****************** Bit definition for GPIO_BRR register *********************/
3027#define GPIO_BRR_BR_0 (0x00000001U)
3028#define GPIO_BRR_BR_1 (0x00000002U)
3029#define GPIO_BRR_BR_2 (0x00000004U)
3030#define GPIO_BRR_BR_3 (0x00000008U)
3031#define GPIO_BRR_BR_4 (0x00000010U)
3032#define GPIO_BRR_BR_5 (0x00000020U)
3033#define GPIO_BRR_BR_6 (0x00000040U)
3034#define GPIO_BRR_BR_7 (0x00000080U)
3035#define GPIO_BRR_BR_8 (0x00000100U)
3036#define GPIO_BRR_BR_9 (0x00000200U)
3037#define GPIO_BRR_BR_10 (0x00000400U)
3038#define GPIO_BRR_BR_11 (0x00000800U)
3039#define GPIO_BRR_BR_12 (0x00001000U)
3040#define GPIO_BRR_BR_13 (0x00002000U)
3041#define GPIO_BRR_BR_14 (0x00004000U)
3042#define GPIO_BRR_BR_15 (0x00008000U)
3043
3044/******************************************************************************/
3045/* */
3046/* Inter-integrated Circuit Interface (I2C) */
3047/* */
3048/******************************************************************************/
3049
3050/******************* Bit definition for I2C_CR1 register *******************/
3051#define I2C_CR1_PE_Pos (0U)
3052#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
3053#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
3054#define I2C_CR1_TXIE_Pos (1U)
3055#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
3056#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
3057#define I2C_CR1_RXIE_Pos (2U)
3058#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
3059#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
3060#define I2C_CR1_ADDRIE_Pos (3U)
3061#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
3062#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
3063#define I2C_CR1_NACKIE_Pos (4U)
3064#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
3065#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
3066#define I2C_CR1_STOPIE_Pos (5U)
3067#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
3068#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
3069#define I2C_CR1_TCIE_Pos (6U)
3070#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
3071#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
3072#define I2C_CR1_ERRIE_Pos (7U)
3073#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
3074#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
3075#define I2C_CR1_DNF_Pos (8U)
3076#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
3077#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
3078#define I2C_CR1_ANFOFF_Pos (12U)
3079#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
3080#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
3081#define I2C_CR1_TXDMAEN_Pos (14U)
3082#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
3083#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
3084#define I2C_CR1_RXDMAEN_Pos (15U)
3085#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
3086#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
3087#define I2C_CR1_SBC_Pos (16U)
3088#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
3089#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
3090#define I2C_CR1_NOSTRETCH_Pos (17U)
3091#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
3092#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
3093#define I2C_CR1_WUPEN_Pos (18U)
3094#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
3095#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
3096#define I2C_CR1_GCEN_Pos (19U)
3097#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
3098#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
3099#define I2C_CR1_SMBHEN_Pos (20U)
3100#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
3101#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
3102#define I2C_CR1_SMBDEN_Pos (21U)
3103#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
3104#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
3105#define I2C_CR1_ALERTEN_Pos (22U)
3106#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
3107#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
3108#define I2C_CR1_PECEN_Pos (23U)
3109#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
3110#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
3111
3112/****************** Bit definition for I2C_CR2 register ********************/
3113#define I2C_CR2_SADD_Pos (0U)
3114#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
3115#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
3116#define I2C_CR2_RD_WRN_Pos (10U)
3117#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
3118#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
3119#define I2C_CR2_ADD10_Pos (11U)
3120#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
3121#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
3122#define I2C_CR2_HEAD10R_Pos (12U)
3123#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
3124#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
3125#define I2C_CR2_START_Pos (13U)
3126#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
3127#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
3128#define I2C_CR2_STOP_Pos (14U)
3129#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
3130#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
3131#define I2C_CR2_NACK_Pos (15U)
3132#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
3133#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
3134#define I2C_CR2_NBYTES_Pos (16U)
3135#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
3136#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
3137#define I2C_CR2_RELOAD_Pos (24U)
3138#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
3139#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
3140#define I2C_CR2_AUTOEND_Pos (25U)
3141#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
3142#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
3143#define I2C_CR2_PECBYTE_Pos (26U)
3144#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
3145#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
3146
3147/******************* Bit definition for I2C_OAR1 register ******************/
3148#define I2C_OAR1_OA1_Pos (0U)
3149#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
3150#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
3151#define I2C_OAR1_OA1MODE_Pos (10U)
3152#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
3153#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
3154#define I2C_OAR1_OA1EN_Pos (15U)
3155#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
3156#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
3157
3158/******************* Bit definition for I2C_OAR2 register ******************/
3159#define I2C_OAR2_OA2_Pos (1U)
3160#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
3161#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
3162#define I2C_OAR2_OA2MSK_Pos (8U)
3163#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
3164#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
3165#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
3166#define I2C_OAR2_OA2MASK01_Pos (8U)
3167#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
3168#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
3169#define I2C_OAR2_OA2MASK02_Pos (9U)
3170#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
3171#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
3172#define I2C_OAR2_OA2MASK03_Pos (8U)
3173#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
3174#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
3175#define I2C_OAR2_OA2MASK04_Pos (10U)
3176#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
3177#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
3178#define I2C_OAR2_OA2MASK05_Pos (8U)
3179#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
3180#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
3181#define I2C_OAR2_OA2MASK06_Pos (9U)
3182#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
3183#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
3184#define I2C_OAR2_OA2MASK07_Pos (8U)
3185#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
3186#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
3187#define I2C_OAR2_OA2EN_Pos (15U)
3188#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
3189#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
3190
3191/******************* Bit definition for I2C_TIMINGR register *******************/
3192#define I2C_TIMINGR_SCLL_Pos (0U)
3193#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
3194#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
3195#define I2C_TIMINGR_SCLH_Pos (8U)
3196#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
3197#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
3198#define I2C_TIMINGR_SDADEL_Pos (16U)
3199#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
3200#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
3201#define I2C_TIMINGR_SCLDEL_Pos (20U)
3202#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
3203#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
3204#define I2C_TIMINGR_PRESC_Pos (28U)
3205#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
3206#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
3207
3208/******************* Bit definition for I2C_TIMEOUTR register *******************/
3209#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
3210#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
3211#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
3212#define I2C_TIMEOUTR_TIDLE_Pos (12U)
3213#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
3214#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
3215#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
3216#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
3217#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
3218#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
3219#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
3220#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
3221#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
3222#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
3223#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
3224
3225/****************** Bit definition for I2C_ISR register *********************/
3226#define I2C_ISR_TXE_Pos (0U)
3227#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
3228#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
3229#define I2C_ISR_TXIS_Pos (1U)
3230#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
3231#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
3232#define I2C_ISR_RXNE_Pos (2U)
3233#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
3234#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
3235#define I2C_ISR_ADDR_Pos (3U)
3236#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
3237#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
3238#define I2C_ISR_NACKF_Pos (4U)
3239#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
3240#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
3241#define I2C_ISR_STOPF_Pos (5U)
3242#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
3243#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
3244#define I2C_ISR_TC_Pos (6U)
3245#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
3246#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
3247#define I2C_ISR_TCR_Pos (7U)
3248#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
3249#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
3250#define I2C_ISR_BERR_Pos (8U)
3251#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
3252#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
3253#define I2C_ISR_ARLO_Pos (9U)
3254#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
3255#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
3256#define I2C_ISR_OVR_Pos (10U)
3257#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
3258#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
3259#define I2C_ISR_PECERR_Pos (11U)
3260#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
3261#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
3262#define I2C_ISR_TIMEOUT_Pos (12U)
3263#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
3264#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
3265#define I2C_ISR_ALERT_Pos (13U)
3266#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
3267#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
3268#define I2C_ISR_BUSY_Pos (15U)
3269#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
3270#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
3271#define I2C_ISR_DIR_Pos (16U)
3272#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
3273#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
3274#define I2C_ISR_ADDCODE_Pos (17U)
3275#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
3276#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
3277
3278/****************** Bit definition for I2C_ICR register *********************/
3279#define I2C_ICR_ADDRCF_Pos (3U)
3280#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
3281#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
3282#define I2C_ICR_NACKCF_Pos (4U)
3283#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
3284#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
3285#define I2C_ICR_STOPCF_Pos (5U)
3286#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
3287#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
3288#define I2C_ICR_BERRCF_Pos (8U)
3289#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
3290#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
3291#define I2C_ICR_ARLOCF_Pos (9U)
3292#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
3293#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
3294#define I2C_ICR_OVRCF_Pos (10U)
3295#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
3296#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
3297#define I2C_ICR_PECCF_Pos (11U)
3298#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
3299#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
3300#define I2C_ICR_TIMOUTCF_Pos (12U)
3301#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
3302#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
3303#define I2C_ICR_ALERTCF_Pos (13U)
3304#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
3305#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
3306
3307/****************** Bit definition for I2C_PECR register *********************/
3308#define I2C_PECR_PEC_Pos (0U)
3309#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
3310#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
3311
3312/****************** Bit definition for I2C_RXDR register *********************/
3313#define I2C_RXDR_RXDATA_Pos (0U)
3314#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
3315#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
3316
3317/****************** Bit definition for I2C_TXDR register *********************/
3318#define I2C_TXDR_TXDATA_Pos (0U)
3319#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
3320#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
3321
3322/******************************************************************************/
3323/* */
3324/* Independent WATCHDOG (IWDG) */
3325/* */
3326/******************************************************************************/
3327/******************* Bit definition for IWDG_KR register ********************/
3328#define IWDG_KR_KEY_Pos (0U)
3329#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
3330#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
3331
3332/******************* Bit definition for IWDG_PR register ********************/
3333#define IWDG_PR_PR_Pos (0U)
3334#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
3335#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
3336#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
3337#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
3338#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
3339
3340/******************* Bit definition for IWDG_RLR register *******************/
3341#define IWDG_RLR_RL_Pos (0U)
3342#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
3343#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
3344
3345/******************* Bit definition for IWDG_SR register ********************/
3346#define IWDG_SR_PVU_Pos (0U)
3347#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
3348#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
3349#define IWDG_SR_RVU_Pos (1U)
3350#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
3351#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
3352#define IWDG_SR_WVU_Pos (2U)
3353#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
3354#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
3355
3356/******************* Bit definition for IWDG_KR register ********************/
3357#define IWDG_WINR_WIN_Pos (0U)
3358#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
3359#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
3360
3361/******************************************************************************/
3362/* */
3363/* Low Power Timer (LPTTIM) */
3364/* */
3365/******************************************************************************/
3366/****************** Bit definition for LPTIM_ISR register *******************/
3367#define LPTIM_ISR_CMPM_Pos (0U)
3368#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
3369#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
3370#define LPTIM_ISR_ARRM_Pos (1U)
3371#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
3372#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
3373#define LPTIM_ISR_EXTTRIG_Pos (2U)
3374#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
3375#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
3376#define LPTIM_ISR_CMPOK_Pos (3U)
3377#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
3378#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
3379#define LPTIM_ISR_ARROK_Pos (4U)
3380#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
3381#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
3382#define LPTIM_ISR_UP_Pos (5U)
3383#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
3384#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
3385#define LPTIM_ISR_DOWN_Pos (6U)
3386#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
3387#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
3388
3389/****************** Bit definition for LPTIM_ICR register *******************/
3390#define LPTIM_ICR_CMPMCF_Pos (0U)
3391#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
3392#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
3393#define LPTIM_ICR_ARRMCF_Pos (1U)
3394#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
3395#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
3396#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
3397#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
3398#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
3399#define LPTIM_ICR_CMPOKCF_Pos (3U)
3400#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
3401#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
3402#define LPTIM_ICR_ARROKCF_Pos (4U)
3403#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
3404#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
3405#define LPTIM_ICR_UPCF_Pos (5U)
3406#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
3407#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
3408#define LPTIM_ICR_DOWNCF_Pos (6U)
3409#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
3410#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
3411
3412/****************** Bit definition for LPTIM_IER register ********************/
3413#define LPTIM_IER_CMPMIE_Pos (0U)
3414#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
3415#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
3416#define LPTIM_IER_ARRMIE_Pos (1U)
3417#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
3418#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
3419#define LPTIM_IER_EXTTRIGIE_Pos (2U)
3420#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
3421#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
3422#define LPTIM_IER_CMPOKIE_Pos (3U)
3423#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
3424#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
3425#define LPTIM_IER_ARROKIE_Pos (4U)
3426#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
3427#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
3428#define LPTIM_IER_UPIE_Pos (5U)
3429#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
3430#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
3431#define LPTIM_IER_DOWNIE_Pos (6U)
3432#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
3433#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
3434
3435/****************** Bit definition for LPTIM_CFGR register *******************/
3436#define LPTIM_CFGR_CKSEL_Pos (0U)
3437#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
3438#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
3439
3440#define LPTIM_CFGR_CKPOL_Pos (1U)
3441#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
3442#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
3443#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
3444#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
3445
3446#define LPTIM_CFGR_CKFLT_Pos (3U)
3447#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
3448#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
3449#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
3450#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
3451
3452#define LPTIM_CFGR_TRGFLT_Pos (6U)
3453#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
3454#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
3455#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
3456#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
3457
3458#define LPTIM_CFGR_PRESC_Pos (9U)
3459#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
3460#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
3461#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
3462#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
3463#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
3464
3465#define LPTIM_CFGR_TRIGSEL_Pos (13U)
3466#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
3467#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
3468#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
3469#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
3470#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
3471
3472#define LPTIM_CFGR_TRIGEN_Pos (17U)
3473#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
3474#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
3475#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
3476#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
3477
3478#define LPTIM_CFGR_TIMOUT_Pos (19U)
3479#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
3480#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
3481#define LPTIM_CFGR_WAVE_Pos (20U)
3482#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
3483#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
3484#define LPTIM_CFGR_WAVPOL_Pos (21U)
3485#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
3486#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
3487#define LPTIM_CFGR_PRELOAD_Pos (22U)
3488#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
3489#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
3490#define LPTIM_CFGR_COUNTMODE_Pos (23U)
3491#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
3492#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
3493#define LPTIM_CFGR_ENC_Pos (24U)
3494#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
3495#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
3496
3497/****************** Bit definition for LPTIM_CR register ********************/
3498#define LPTIM_CR_ENABLE_Pos (0U)
3499#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
3500#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
3501#define LPTIM_CR_SNGSTRT_Pos (1U)
3502#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
3503#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
3504#define LPTIM_CR_CNTSTRT_Pos (2U)
3505#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
3506#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
3507
3508/****************** Bit definition for LPTIM_CMP register *******************/
3509#define LPTIM_CMP_CMP_Pos (0U)
3510#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
3511#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
3512
3513/****************** Bit definition for LPTIM_ARR register *******************/
3514#define LPTIM_ARR_ARR_Pos (0U)
3515#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
3516#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
3517
3518/****************** Bit definition for LPTIM_CNT register *******************/
3519#define LPTIM_CNT_CNT_Pos (0U)
3520#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
3521#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
3522
3523/******************************************************************************/
3524/* */
3525/* MIFARE Firewall */
3526/* */
3527/******************************************************************************/
3528
3529/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
3530#define FW_CSSA_ADD_Pos (8U)
3531#define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
3532#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
3533#define FW_CSL_LENG_Pos (8U)
3534#define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
3535#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
3536#define FW_NVDSSA_ADD_Pos (8U)
3537#define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
3538#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
3539#define FW_NVDSL_LENG_Pos (8U)
3540#define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
3541#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
3542#define FW_VDSSA_ADD_Pos (6U)
3543#define FW_VDSSA_ADD_Msk (0x3FFU << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
3544#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
3545#define FW_VDSL_LENG_Pos (6U)
3546#define FW_VDSL_LENG_Msk (0x3FFU << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
3547#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
3548
3549/**************************Bit definition for CR register *********************/
3550#define FW_CR_FPA_Pos (0U)
3551#define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
3552#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
3553#define FW_CR_VDS_Pos (1U)
3554#define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
3555#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/