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1/**
2 ******************************************************************************
3 * @file stm32l083xx.h
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
6 * This file contains all the peripheral register's definitions, bits
7 * definitions and memory mapping for stm32l083xx devices.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44/** @addtogroup CMSIS
45 * @{
46 */
47
48/** @addtogroup stm32l083xx
49 * @{
50 */
51
52#ifndef __STM32L083xx_H
53#define __STM32L083xx_H
54
55#ifdef __cplusplus
56 extern "C" {
57#endif
58
59
60/** @addtogroup Configuration_section_for_CMSIS
61 * @{
62 */
63/**
64 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
65 */
66#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
67#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */
68#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
69#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
70#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
71
72/**
73 * @}
74 */
75
76/** @addtogroup Peripheral_interrupt_number_definition
77 * @{
78 */
79
80/**
81 * @brief stm32l083xx Interrupt Number Definition, according to the selected device
82 * in @ref Library_configuration_section
83 */
84
85/*!< Interrupt Number Definition */
86typedef enum
87{
88/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
90 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
91 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
92 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
93 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
94
95/****** STM32L-0 specific Interrupt Numbers *********************************************************/
96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
97 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
98 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
99 FLASH_IRQn = 3, /*!< FLASH Interrupt */
100 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
101 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
102 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
103 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
104 TSC_IRQn = 8, /*!< TSC Interrupt */
105 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
106 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
107 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
108 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
109 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
110 USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */
111 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
112 TIM3_IRQn = 16, /*!< TIM3 Interrupt */
113 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
114 TIM7_IRQn = 18, /*!< TIM7 Interrupt */
115 TIM21_IRQn = 20, /*!< TIM21 Interrupt */
116 I2C3_IRQn = 21, /*!< I2C3 Interrupt */
117 TIM22_IRQn = 22, /*!< TIM22 Interrupt */
118 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
119 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
120 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
121 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
122 USART1_IRQn = 27, /*!< USART1 Interrupt */
123 USART2_IRQn = 28, /*!< USART2 Interrupt */
124 AES_RNG_LPUART1_IRQn = 29, /*!< AES and RNG and LPUART1 Interrupts */
125 LCD_IRQn = 30, /*!< LCD Interrupt */
126 USB_IRQn = 31, /*!< USB global Interrupt */
127} IRQn_Type;
128
129/**
130 * @}
131 */
132
133#include "core_cm0plus.h"
134#include "system_stm32l0xx.h"
135#include <stdint.h>
136
137/** @addtogroup Peripheral_registers_structures
138 * @{
139 */
140
141/**
142 * @brief Analog to Digital Converter
143 */
144
145typedef struct
146{
147 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
148 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
149 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
150 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
151 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
152 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
153 uint32_t RESERVED1; /*!< Reserved, 0x18 */
154 uint32_t RESERVED2; /*!< Reserved, 0x1C */
155 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
156 uint32_t RESERVED3; /*!< Reserved, 0x24 */
157 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
158 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
159 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
160 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
161 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
162} ADC_TypeDef;
163
164typedef struct
165{
166 __IO uint32_t CCR;
167} ADC_Common_TypeDef;
168
169/**
170 * @brief AES hardware accelerator
171 */
172
173typedef struct
174{
175 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
176 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
177 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
178 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
179 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
180 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
181 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
182 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
183 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
184 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
185 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
186 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
187} AES_TypeDef;
188
189/**
190 * @brief Comparator
191 */
192
193typedef struct
194{
195 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
196} COMP_TypeDef;
197
198typedef struct
199{
200 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
201} COMP_Common_TypeDef;
202
203
204/**
205* @brief CRC calculation unit
206*/
207
208typedef struct
209{
210__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
211__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
212uint8_t RESERVED0; /*!< Reserved, 0x05 */
213uint16_t RESERVED1; /*!< Reserved, 0x06 */
214__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
215uint32_t RESERVED2; /*!< Reserved, 0x0C */
216__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
217__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
218} CRC_TypeDef;
219
220/**
221 * @brief Clock Recovery System
222 */
223
224typedef struct
225{
226__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
227__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
228__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
229__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
230} CRS_TypeDef;
231
232/**
233 * @brief Digital to Analog Converter
234 */
235
236typedef struct
237{
238 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
239 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
240 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
241 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
242 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
243 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
244 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
245 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
246 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
247 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
248 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
249 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
250 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
251 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
252} DAC_TypeDef;
253
254/**
255 * @brief Debug MCU
256 */
257
258typedef struct
259{
260 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
261 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
262 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
263 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
264}DBGMCU_TypeDef;
265
266/**
267 * @brief DMA Controller
268 */
269
270typedef struct
271{
272 __IO uint32_t CCR; /*!< DMA channel x configuration register */
273 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
274 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
275 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
276} DMA_Channel_TypeDef;
277
278typedef struct
279{
280 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
281 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
282} DMA_TypeDef;
283
284typedef struct
285{
286 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
287} DMA_Request_TypeDef;
288
289/**
290 * @brief External Interrupt/Event Controller
291 */
292
293typedef struct
294{
295 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
296 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
297 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
298 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
299 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
300 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
301}EXTI_TypeDef;
302
303/**
304 * @brief FLASH Registers
305 */
306typedef struct
307{
308 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
309 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
310 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
311 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
312 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
313 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
314 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
315 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
316 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
317 __IO uint32_t RESERVED1[23]; /*!< Reserved1, Address offset: 0x24 */
318 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
319} FLASH_TypeDef;
320
321
322/**
323 * @brief Option Bytes Registers
324 */
325typedef struct
326{
327 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
328 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
329 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
330 __IO uint32_t WRP23; /*!< write protection Bytes 2 and 3 Address offset: 0x0C */
331 __IO uint32_t WRP45; /*!< write protection Bytes 4 and 5 Address offset: 0x10 */
332} OB_TypeDef;
333
334
335/**
336 * @brief General Purpose IO
337 */
338
339typedef struct
340{
341 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
342 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
343 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
344 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
345 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
346 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
347 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
348 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
349 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
350 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
351}GPIO_TypeDef;
352
353/**
354 * @brief LPTIMIMER
355 */
356typedef struct
357{
358 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
359 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
360 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
361 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
362 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
363 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
364 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
365 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
366} LPTIM_TypeDef;
367
368/**
369 * @brief SysTem Configuration
370 */
371
372typedef struct
373{
374 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
375 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
376 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
377 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
378 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
379} SYSCFG_TypeDef;
380
381
382
383/**
384 * @brief Inter-integrated Circuit Interface
385 */
386
387typedef struct
388{
389 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
390 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
391 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
392 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
393 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
394 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
395 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
396 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
397 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
398 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
399 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
400}I2C_TypeDef;
401
402
403/**
404 * @brief Independent WATCHDOG
405 */
406typedef struct
407{
408 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
409 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
410 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
411 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
412 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
413} IWDG_TypeDef;
414
415/**
416 * @brief LCD
417 */
418typedef struct
419{
420 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
421 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
422 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
423 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
424 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
425 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
426} LCD_TypeDef;
427
428/**
429 * @brief MIFARE Firewall
430 */
431typedef struct
432{
433 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
434 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
435 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
436 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
437 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
438 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
439 __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
440 __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
441 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
442
443} FIREWALL_TypeDef;
444
445/**
446 * @brief Power Control
447 */
448typedef struct
449{
450 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
451 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
452} PWR_TypeDef;
453
454/**
455 * @brief Reset and Clock Control
456 */
457typedef struct
458{
459 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
460 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
461 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
462 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
463 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
464 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
465 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
466 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
467 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
468 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
469 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
470 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
471 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
472 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
473 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
474 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
475 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
476 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
477 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
478 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
479 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
480} RCC_TypeDef;
481
482/**
483 * @brief Random numbers generator
484 */
485typedef struct
486{
487 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
488 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
489 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
490} RNG_TypeDef;
491
492/**
493 * @brief Real-Time Clock
494 */
495typedef struct
496{
497 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
498 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
499 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
500 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
501 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
502 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
503 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
504 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
505 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
506 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
507 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
508 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
509 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
510 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
511 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
512 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
513 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
514 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
515 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
516 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
517 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
518 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
519 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
520 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
521 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
522} RTC_TypeDef;
523
524
525/**
526 * @brief Serial Peripheral Interface
527 */
528typedef struct
529{
530 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
531 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
532 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
533 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
534 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
535 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
536 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
537 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
538 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
539} SPI_TypeDef;
540
541/**
542 * @brief TIM
543 */
544typedef struct
545{
546 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
547 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
548 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
549 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
550 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
551 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
552 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
553 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
554 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
555 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
556 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
557 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
558 uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
559 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
560 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
561 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
562 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
563 uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
564 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
565 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
566 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
567} TIM_TypeDef;
568
569/**
570 * @brief Touch Sensing Controller (TSC)
571 */
572typedef struct
573{
574 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
575 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
576 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
577 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
578 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
579 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
580 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
581 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
582 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
583 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
584 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
585 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
586 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
587 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
588} TSC_TypeDef;
589
590/**
591 * @brief Universal Synchronous Asynchronous Receiver Transmitter
592 */
593typedef struct
594{
595 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
596 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
597 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
598 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
599 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
600 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
601 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
602 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
603 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
604 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
605 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
606} USART_TypeDef;
607
608/**
609 * @brief Window WATCHDOG
610 */
611typedef struct
612{
613 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
614 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
615 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
616} WWDG_TypeDef;
617
618/**
619 * @brief Universal Serial Bus Full Speed Device
620 */
621typedef struct
622{
623 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
624 __IO uint16_t RESERVED0; /*!< Reserved */
625 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
626 __IO uint16_t RESERVED1; /*!< Reserved */
627 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
628 __IO uint16_t RESERVED2; /*!< Reserved */
629 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
630 __IO uint16_t RESERVED3; /*!< Reserved */
631 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
632 __IO uint16_t RESERVED4; /*!< Reserved */
633 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
634 __IO uint16_t RESERVED5; /*!< Reserved */
635 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
636 __IO uint16_t RESERVED6; /*!< Reserved */
637 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
638 __IO uint16_t RESERVED7[17]; /*!< Reserved */
639 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
640 __IO uint16_t RESERVED8; /*!< Reserved */
641 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
642 __IO uint16_t RESERVED9; /*!< Reserved */
643 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
644 __IO uint16_t RESERVEDA; /*!< Reserved */
645 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
646 __IO uint16_t RESERVEDB; /*!< Reserved */
647 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
648 __IO uint16_t RESERVEDC; /*!< Reserved */
649 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
650 __IO uint16_t RESERVEDD; /*!< Reserved */
651 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
652 __IO uint16_t RESERVEDE; /*!< Reserved */
653} USB_TypeDef;
654
655/**
656 * @}
657 */
658
659/** @addtogroup Peripheral_memory_map
660 * @{
661 */
662#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
663#define FLASH_BANK2_BASE ((uint32_t)0x08018000U) /*!< FLASH BANK2 base address in the alias region */
664#define FLASH_BANK1_END ((uint32_t)0x08017FFFU) /*!< Program end FLASH BANK1 address */
665#define FLASH_BANK2_END ((uint32_t)0x0802FFFFU) /*!< Program end FLASH BANK2 address */
666#define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
667#define DATA_EEPROM_BANK2_BASE ((uint32_t)0x08080C00U) /*!< DATA EEPROM BANK2 base address in the alias region */
668#define DATA_EEPROM_BANK1_END ((uint32_t)0x08080BFFU) /*!< Program end DATA EEPROM BANK1 address */
669#define DATA_EEPROM_BANK2_END ((uint32_t)0x080817FFU) /*!< Program end DATA EEPROM BANK2 address */
670#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
671#define SRAM_SIZE_MAX ((uint32_t)0x00005000U) /*!< maximum SRAM size (up to 20KBytes) */
672
673#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
674
675/*!< Peripheral memory map */
676#define APBPERIPH_BASE PERIPH_BASE
677#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
678#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000U)
679
680#define TIM2_BASE (APBPERIPH_BASE + 0x00000000U)
681#define TIM3_BASE (APBPERIPH_BASE + 0x00000400U)
682#define TIM6_BASE (APBPERIPH_BASE + 0x00001000U)
683#define TIM7_BASE (APBPERIPH_BASE + 0x00001400U)
684#define LCD_BASE (APBPERIPH_BASE + 0x00002400U)
685#define RTC_BASE (APBPERIPH_BASE + 0x00002800U)
686#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U)
687#define IWDG_BASE (APBPERIPH_BASE + 0x00003000U)
688#define SPI2_BASE (APBPERIPH_BASE + 0x00003800U)
689#define USART2_BASE (APBPERIPH_BASE + 0x00004400U)
690#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800U)
691#define USART4_BASE (APBPERIPH_BASE + 0x00004C00U)
692#define USART5_BASE (APBPERIPH_BASE + 0x00005000U)
693#define I2C1_BASE (APBPERIPH_BASE + 0x00005400U)
694#define I2C2_BASE (APBPERIPH_BASE + 0x00005800U)
695#define CRS_BASE (APBPERIPH_BASE + 0x00006C00U)
696#define PWR_BASE (APBPERIPH_BASE + 0x00007000U)
697#define DAC_BASE (APBPERIPH_BASE + 0x00007400U)
698#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U)
699#define I2C3_BASE (APBPERIPH_BASE + 0x00007800U)
700
701#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000U)
702#define COMP1_BASE (APBPERIPH_BASE + 0x00010018U)
703#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CU)
704#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
705#define EXTI_BASE (APBPERIPH_BASE + 0x00010400U)
706#define TIM21_BASE (APBPERIPH_BASE + 0x00010800U)
707#define TIM22_BASE (APBPERIPH_BASE + 0x00011400U)
708#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00U)
709#define ADC1_BASE (APBPERIPH_BASE + 0x00012400U)
710#define ADC_BASE (APBPERIPH_BASE + 0x00012708U)
711#define SPI1_BASE (APBPERIPH_BASE + 0x00013000U)
712#define USART1_BASE (APBPERIPH_BASE + 0x00013800U)
713#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800U)
714
715#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
716#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
717#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
718#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
719#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
720#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
721#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
722#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
723#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U)
724
725
726#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
727#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
728#define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
729#define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */
730#define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */
731#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
732#define TSC_BASE (AHBPERIPH_BASE + 0x00004000U)
733#define RNG_BASE (AHBPERIPH_BASE + 0x00005000U)
734#define AES_BASE (AHBPERIPH_BASE + 0x00006000U)
735
736#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U)
737#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U)
738#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800U)
739#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00U)
740#define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000U)
741#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00U)
742
743/**
744 * @}
745 */
746
747/** @addtogroup Peripheral_declaration
748 * @{
749 */
750
751#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
752#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
753#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
754#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
755#define RTC ((RTC_TypeDef *) RTC_BASE)
756#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
757#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
758#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
759#define USART2 ((USART_TypeDef *) USART2_BASE)
760#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
761#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
762#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
763#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
764#define CRS ((CRS_TypeDef *) CRS_BASE)
765#define PWR ((PWR_TypeDef *) PWR_BASE)
766#define DAC ((DAC_TypeDef *) DAC_BASE)
767#define DAC1 ((DAC_TypeDef *) DAC_BASE)
768#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
769#define LCD ((LCD_TypeDef *) LCD_BASE)
770#define USART4 ((USART_TypeDef *) USART4_BASE)
771#define USART5 ((USART_TypeDef *) USART5_BASE)
772
773#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
774#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
775#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
776#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
777#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
778#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
779#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
780#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
781#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
782/* Legacy defines */
783#define ADC ADC1_COMMON
784#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
785#define USART1 ((USART_TypeDef *) USART1_BASE)
786#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
787
788#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
789#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
790#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
791#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
792#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
793#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
794#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
795#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
796#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
797
798
799#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
800#define OB ((OB_TypeDef *) OB_BASE)
801#define RCC ((RCC_TypeDef *) RCC_BASE)
802#define CRC ((CRC_TypeDef *) CRC_BASE)
803#define TSC ((TSC_TypeDef *) TSC_BASE)
804#define AES ((AES_TypeDef *) AES_BASE)
805#define RNG ((RNG_TypeDef *) RNG_BASE)
806
807#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
808#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
809#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
810#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
811#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
812#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
813
814#define USB ((USB_TypeDef *) USB_BASE)
815
816/**
817 * @}
818 */
819
820/** @addtogroup Exported_constants
821 * @{
822 */
823
824 /** @addtogroup Peripheral_Registers_Bits_Definition
825 * @{
826 */
827
828/******************************************************************************/
829/* Peripheral Registers Bits Definition */
830/******************************************************************************/
831/******************************************************************************/
832/* */
833/* Analog to Digital Converter (ADC) */
834/* */
835/******************************************************************************/
836/******************** Bits definition for ADC_ISR register ******************/
837#define ADC_ISR_EOCAL_Pos (11U)
838#define ADC_ISR_EOCAL_Msk (0x1U << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
839#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
840#define ADC_ISR_AWD_Pos (7U)
841#define ADC_ISR_AWD_Msk (0x1U << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
842#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
843#define ADC_ISR_OVR_Pos (4U)
844#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
845#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
846#define ADC_ISR_EOSEQ_Pos (3U)
847#define ADC_ISR_EOSEQ_Msk (0x1U << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
848#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
849#define ADC_ISR_EOC_Pos (2U)
850#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
851#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
852#define ADC_ISR_EOSMP_Pos (1U)
853#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
854#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
855#define ADC_ISR_ADRDY_Pos (0U)
856#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
857#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
858
859/* Old EOSEQ bit definition, maintained for legacy purpose */
860#define ADC_ISR_EOS ADC_ISR_EOSEQ
861
862/******************** Bits definition for ADC_IER register ******************/
863#define ADC_IER_EOCALIE_Pos (11U)
864#define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
865#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
866#define ADC_IER_AWDIE_Pos (7U)
867#define ADC_IER_AWDIE_Msk (0x1U << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
868#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
869#define ADC_IER_OVRIE_Pos (4U)
870#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
871#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
872#define ADC_IER_EOSEQIE_Pos (3U)
873#define ADC_IER_EOSEQIE_Msk (0x1U << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
874#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
875#define ADC_IER_EOCIE_Pos (2U)
876#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
877#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
878#define ADC_IER_EOSMPIE_Pos (1U)
879#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
880#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
881#define ADC_IER_ADRDYIE_Pos (0U)
882#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
883#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
884
885/* Old EOSEQIE bit definition, maintained for legacy purpose */
886#define ADC_IER_EOSIE ADC_IER_EOSEQIE
887
888/******************** Bits definition for ADC_CR register *******************/
889#define ADC_CR_ADCAL_Pos (31U)
890#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
891#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
892#define ADC_CR_ADVREGEN_Pos (28U)
893#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
894#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
895#define ADC_CR_ADSTP_Pos (4U)
896#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
897#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
898#define ADC_CR_ADSTART_Pos (2U)
899#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
900#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
901#define ADC_CR_ADDIS_Pos (1U)
902#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
903#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
904#define ADC_CR_ADEN_Pos (0U)
905#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
906#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
907
908/******************* Bits definition for ADC_CFGR1 register *****************/
909#define ADC_CFGR1_AWDCH_Pos (26U)
910#define ADC_CFGR1_AWDCH_Msk (0x1FU << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
911#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
912#define ADC_CFGR1_AWDCH_0 (0x01U << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
913#define ADC_CFGR1_AWDCH_1 (0x02U << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
914#define ADC_CFGR1_AWDCH_2 (0x04U << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
915#define ADC_CFGR1_AWDCH_3 (0x08U << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
916#define ADC_CFGR1_AWDCH_4 (0x10U << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
917#define ADC_CFGR1_AWDEN_Pos (23U)
918#define ADC_CFGR1_AWDEN_Msk (0x1U << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
919#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
920#define ADC_CFGR1_AWDSGL_Pos (22U)
921#define ADC_CFGR1_AWDSGL_Msk (0x1U << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
922#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
923#define ADC_CFGR1_DISCEN_Pos (16U)
924#define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
925#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
926#define ADC_CFGR1_AUTOFF_Pos (15U)
927#define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
928#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
929#define ADC_CFGR1_WAIT_Pos (14U)
930#define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
931#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
932#define ADC_CFGR1_CONT_Pos (13U)
933#define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
934#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
935#define ADC_CFGR1_OVRMOD_Pos (12U)
936#define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
937#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
938#define ADC_CFGR1_EXTEN_Pos (10U)
939#define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
940#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
941#define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
942#define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
943#define ADC_CFGR1_EXTSEL_Pos (6U)
944#define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
945#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
946#define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
947#define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
948#define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
949#define ADC_CFGR1_ALIGN_Pos (5U)
950#define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
951#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
952#define ADC_CFGR1_RES_Pos (3U)
953#define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
954#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
955#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
956#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
957#define ADC_CFGR1_SCANDIR_Pos (2U)
958#define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
959#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
960#define ADC_CFGR1_DMACFG_Pos (1U)
961#define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
962#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
963#define ADC_CFGR1_DMAEN_Pos (0U)
964#define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
965#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
966
967/* Old WAIT bit definition, maintained for legacy purpose */
968#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
969
970/******************* Bits definition for ADC_CFGR2 register *****************/
971#define ADC_CFGR2_TOVS_Pos (9U)
972#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
973#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
974#define ADC_CFGR2_OVSS_Pos (5U)
975#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
976#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
977#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
978#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
979#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
980#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
981#define ADC_CFGR2_OVSR_Pos (2U)
982#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
983#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
984#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
985#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
986#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
987#define ADC_CFGR2_OVSE_Pos (0U)
988#define ADC_CFGR2_OVSE_Msk (0x1U << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
989#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
990#define ADC_CFGR2_CKMODE_Pos (30U)
991#define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
992#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
993#define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
994#define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
995
996
997/****************** Bit definition for ADC_SMPR register ********************/
998#define ADC_SMPR_SMP_Pos (0U)
999#define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
1000#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
1001#define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
1002#define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
1003#define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
1004
1005/* Legacy defines */
1006#define ADC_SMPR_SMPR ADC_SMPR_SMP
1007#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
1008#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
1009#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
1010
1011/******************* Bit definition for ADC_TR register ********************/
1012#define ADC_TR_HT_Pos (16U)
1013#define ADC_TR_HT_Msk (0xFFFU << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
1014#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
1015#define ADC_TR_LT_Pos (0U)
1016#define ADC_TR_LT_Msk (0xFFFU << ADC_TR_LT_Pos) /*!< 0x00000FFF */
1017#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
1018
1019/****************** Bit definition for ADC_CHSELR register ******************/
1020#define ADC_CHSELR_CHSEL_Pos (0U)
1021#define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
1022#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
1023#define ADC_CHSELR_CHSEL18_Pos (18U)
1024#define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
1025#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
1026#define ADC_CHSELR_CHSEL17_Pos (17U)
1027#define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
1028#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
1029#define ADC_CHSELR_CHSEL16_Pos (16U)
1030#define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
1031#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< Channel 16 selection */
1032#define ADC_CHSELR_CHSEL15_Pos (15U)
1033#define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
1034#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
1035#define ADC_CHSELR_CHSEL14_Pos (14U)
1036#define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
1037#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
1038#define ADC_CHSELR_CHSEL13_Pos (13U)
1039#define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
1040#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
1041#define ADC_CHSELR_CHSEL12_Pos (12U)
1042#define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
1043#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
1044#define ADC_CHSELR_CHSEL11_Pos (11U)
1045#define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
1046#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
1047#define ADC_CHSELR_CHSEL10_Pos (10U)
1048#define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
1049#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
1050#define ADC_CHSELR_CHSEL9_Pos (9U)
1051#define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
1052#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
1053#define ADC_CHSELR_CHSEL8_Pos (8U)
1054#define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
1055#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
1056#define ADC_CHSELR_CHSEL7_Pos (7U)
1057#define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
1058#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
1059#define ADC_CHSELR_CHSEL6_Pos (6U)
1060#define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
1061#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
1062#define ADC_CHSELR_CHSEL5_Pos (5U)
1063#define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
1064#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
1065#define ADC_CHSELR_CHSEL4_Pos (4U)
1066#define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
1067#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
1068#define ADC_CHSELR_CHSEL3_Pos (3U)
1069#define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
1070#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
1071#define ADC_CHSELR_CHSEL2_Pos (2U)
1072#define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
1073#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
1074#define ADC_CHSELR_CHSEL1_Pos (1U)
1075#define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
1076#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
1077#define ADC_CHSELR_CHSEL0_Pos (0U)
1078#define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
1079#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
1080
1081/******************** Bit definition for ADC_DR register ********************/
1082#define ADC_DR_DATA_Pos (0U)
1083#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1084#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
1085
1086/******************** Bit definition for ADC_CALFACT register ********************/
1087#define ADC_CALFACT_CALFACT_Pos (0U)
1088#define ADC_CALFACT_CALFACT_Msk (0x7FU << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
1089#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
1090
1091/******************* Bit definition for ADC_CCR register ********************/
1092#define ADC_CCR_LFMEN_Pos (25U)
1093#define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
1094#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
1095#define ADC_CCR_VLCDEN_Pos (24U)
1096#define ADC_CCR_VLCDEN_Msk (0x1U << ADC_CCR_VLCDEN_Pos) /*!< 0x01000000 */
1097#define ADC_CCR_VLCDEN ADC_CCR_VLCDEN_Msk /*!< Voltage LCD enable */
1098#define ADC_CCR_TSEN_Pos (23U)
1099#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
1100#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
1101#define ADC_CCR_VREFEN_Pos (22U)
1102#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
1103#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
1104#define ADC_CCR_PRESC_Pos (18U)
1105#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
1106#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
1107#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
1108#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
1109#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
1110#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
1111
1112/******************************************************************************/
1113/* */
1114/* Advanced Encryption Standard (AES) */
1115/* */
1116/******************************************************************************/
1117/******************* Bit definition for AES_CR register *********************/
1118#define AES_CR_EN_Pos (0U)
1119#define AES_CR_EN_Msk (0x1U << AES_CR_EN_Pos) /*!< 0x00000001 */
1120#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
1121#define AES_CR_DATATYPE_Pos (1U)
1122#define AES_CR_DATATYPE_Msk (0x3U << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
1123#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
1124#define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
1125#define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
1126
1127#define AES_CR_MODE_Pos (3U)
1128#define AES_CR_MODE_Msk (0x3U << AES_CR_MODE_Pos) /*!< 0x00000018 */
1129#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
1130#define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */
1131#define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */
1132
1133#define AES_CR_CHMOD_Pos (5U)
1134#define AES_CR_CHMOD_Msk (0x3U << AES_CR_CHMOD_Pos) /*!< 0x00000060 */
1135#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
1136#define AES_CR_CHMOD_0 (0x1U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
1137#define AES_CR_CHMOD_1 (0x2U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
1138
1139#define AES_CR_CCFC_Pos (7U)
1140#define AES_CR_CCFC_Msk (0x1U << AES_CR_CCFC_Pos) /*!< 0x00000080 */
1141#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
1142#define AES_CR_ERRC_Pos (8U)
1143#define AES_CR_ERRC_Msk (0x1U << AES_CR_ERRC_Pos) /*!< 0x00000100 */
1144#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
1145#define AES_CR_CCIE_Pos (9U)
1146#define AES_CR_CCIE_Msk (0x1U << AES_CR_CCIE_Pos) /*!< 0x00000200 */
1147#define AES_CR_CCIE AES_CR_CCIE_Msk /*!< Computation Complete Interrupt Enable */
1148#define AES_CR_ERRIE_Pos (10U)
1149#define AES_CR_ERRIE_Msk (0x1U << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
1150#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
1151#define AES_CR_DMAINEN_Pos (11U)
1152#define AES_CR_DMAINEN_Msk (0x1U << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
1153#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA ENable managing the data input phase */
1154#define AES_CR_DMAOUTEN_Pos (12U)
1155#define AES_CR_DMAOUTEN_Msk (0x1U << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
1156#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA Enable managing the data output phase */
1157
1158/******************* Bit definition for AES_SR register *********************/
1159#define AES_SR_CCF_Pos (0U)
1160#define AES_SR_CCF_Msk (0x1U << AES_SR_CCF_Pos) /*!< 0x00000001 */
1161#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
1162#define AES_SR_RDERR_Pos (1U)
1163#define AES_SR_RDERR_Msk (0x1U << AES_SR_RDERR_Pos) /*!< 0x00000002 */
1164#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
1165#define AES_SR_WRERR_Pos (2U)
1166#define AES_SR_WRERR_Msk (0x1U << AES_SR_WRERR_Pos) /*!< 0x00000004 */
1167#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
1168
1169/******************* Bit definition for AES_DINR register *******************/
1170#define AES_DINR_Pos (0U)
1171#define AES_DINR_Msk (0xFFFFU << AES_DINR_Pos) /*!< 0x0000FFFF */
1172#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
1173
1174/******************* Bit definition for AES_DOUTR register ******************/
1175#define AES_DOUTR_Pos (0U)
1176#define AES_DOUTR_Msk (0xFFFFU << AES_DOUTR_Pos) /*!< 0x0000FFFF */
1177#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
1178
1179/******************* Bit definition for AES_KEYR0 register ******************/
1180#define AES_KEYR0_Pos (0U)
1181#define AES_KEYR0_Msk (0xFFFFU << AES_KEYR0_Pos) /*!< 0x0000FFFF */
1182#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
1183
1184/******************* Bit definition for AES_KEYR1 register ******************/
1185#define AES_KEYR1_Pos (0U)
1186#define AES_KEYR1_Msk (0xFFFFU << AES_KEYR1_Pos) /*!< 0x0000FFFF */
1187#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
1188
1189/******************* Bit definition for AES_KEYR2 register ******************/
1190#define AES_KEYR2_Pos (0U)
1191#define AES_KEYR2_Msk (0xFFFFU << AES_KEYR2_Pos) /*!< 0x0000FFFF */
1192#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
1193
1194/******************* Bit definition for AES_KEYR3 register ******************/
1195#define AES_KEYR3_Pos (0U)
1196#define AES_KEYR3_Msk (0xFFFFU << AES_KEYR3_Pos) /*!< 0x0000FFFF */
1197#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
1198
1199/******************* Bit definition for AES_IVR0 register *******************/
1200#define AES_IVR0_Pos (0U)
1201#define AES_IVR0_Msk (0xFFFFU << AES_IVR0_Pos) /*!< 0x0000FFFF */
1202#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
1203
1204/******************* Bit definition for AES_IVR1 register *******************/
1205#define AES_IVR1_Pos (0U)
1206#define AES_IVR1_Msk (0xFFFFU << AES_IVR1_Pos) /*!< 0x0000FFFF */
1207#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
1208
1209/******************* Bit definition for AES_IVR2 register *******************/
1210#define AES_IVR2_Pos (0U)
1211#define AES_IVR2_Msk (0xFFFFU << AES_IVR2_Pos) /*!< 0x0000FFFF */
1212#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
1213
1214/******************* Bit definition for AES_IVR3 register *******************/
1215#define AES_IVR3_Pos (0U)
1216#define AES_IVR3_Msk (0xFFFFU << AES_IVR3_Pos) /*!< 0x0000FFFF */
1217#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
1218
1219/******************************************************************************/
1220/* */
1221/* Analog Comparators (COMP) */
1222/* */
1223/******************************************************************************/
1224/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
1225/* COMP1 bits definition */
1226#define COMP_CSR_COMP1EN_Pos (0U)
1227#define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
1228#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
1229#define COMP_CSR_COMP1INNSEL_Pos (4U)
1230#define COMP_CSR_COMP1INNSEL_Msk (0x3U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1231#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
1232#define COMP_CSR_COMP1INNSEL_0 (0x1U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1233#define COMP_CSR_COMP1INNSEL_1 (0x2U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
1234#define COMP_CSR_COMP1WM_Pos (8U)
1235#define COMP_CSR_COMP1WM_Msk (0x1U << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
1236#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
1237#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
1238#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
1239#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
1240#define COMP_CSR_COMP1POLARITY_Pos (15U)
1241#define COMP_CSR_COMP1POLARITY_Msk (0x1U << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
1242#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
1243#define COMP_CSR_COMP1VALUE_Pos (30U)
1244#define COMP_CSR_COMP1VALUE_Msk (0x1U << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
1245#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
1246#define COMP_CSR_COMP1LOCK_Pos (31U)
1247#define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
1248#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
1249/* COMP2 bits definition */
1250#define COMP_CSR_COMP2EN_Pos (0U)
1251#define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
1252#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
1253#define COMP_CSR_COMP2SPEED_Pos (3U)
1254#define COMP_CSR_COMP2SPEED_Msk (0x1U << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
1255#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
1256#define COMP_CSR_COMP2INNSEL_Pos (4U)
1257#define COMP_CSR_COMP2INNSEL_Msk (0x7U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
1258#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
1259#define COMP_CSR_COMP2INNSEL_0 (0x1U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
1260#define COMP_CSR_COMP2INNSEL_1 (0x2U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
1261#define COMP_CSR_COMP2INNSEL_2 (0x4U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1262#define COMP_CSR_COMP2INPSEL_Pos (8U)
1263#define COMP_CSR_COMP2INPSEL_Msk (0x7U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
1264#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
1265#define COMP_CSR_COMP2INPSEL_0 (0x1U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
1266#define COMP_CSR_COMP2INPSEL_1 (0x2U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
1267#define COMP_CSR_COMP2INPSEL_2 (0x4U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
1268#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
1269#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
1270#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
1271#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
1272#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
1273#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
1274#define COMP_CSR_COMP2POLARITY_Pos (15U)
1275#define COMP_CSR_COMP2POLARITY_Msk (0x1U << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
1276#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
1277#define COMP_CSR_COMP2VALUE_Pos (30U)
1278#define COMP_CSR_COMP2VALUE_Msk (0x1U << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
1279#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
1280#define COMP_CSR_COMP2LOCK_Pos (31U)
1281#define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
1282#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
1283
1284/********************** Bit definition for COMP_CSR register common ****************/
1285#define COMP_CSR_COMPxEN_Pos (0U)
1286#define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
1287#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
1288#define COMP_CSR_COMPxPOLARITY_Pos (15U)
1289#define COMP_CSR_COMPxPOLARITY_Msk (0x1U << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
1290#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
1291#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
1292#define COMP_CSR_COMPxOUTVALUE_Msk (0x1U << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
1293#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
1294#define COMP_CSR_COMPxLOCK_Pos (31U)
1295#define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
1296#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
1297
1298/* Reference defines */
1299#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
1300
1301/******************************************************************************/
1302/* */
1303/* CRC calculation unit (CRC) */
1304/* */
1305/******************************************************************************/
1306/******************* Bit definition for CRC_DR register *********************/
1307#define CRC_DR_DR_Pos (0U)
1308#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
1309#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
1310
1311/******************* Bit definition for CRC_IDR register ********************/
1312#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
1313
1314/******************** Bit definition for CRC_CR register ********************/
1315#define CRC_CR_RESET_Pos (0U)
1316#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
1317#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
1318#define CRC_CR_POLYSIZE_Pos (3U)
1319#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
1320#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
1321#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
1322#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
1323#define CRC_CR_REV_IN_Pos (5U)
1324#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
1325#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
1326#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
1327#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
1328#define CRC_CR_REV_OUT_Pos (7U)
1329#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
1330#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
1331
1332/******************* Bit definition for CRC_INIT register *******************/
1333#define CRC_INIT_INIT_Pos (0U)
1334#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
1335#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
1336
1337/******************* Bit definition for CRC_POL register ********************/
1338#define CRC_POL_POL_Pos (0U)
1339#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
1340#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
1341
1342/******************************************************************************/
1343/* */
1344/* CRS Clock Recovery System */
1345/* */
1346/******************************************************************************/
1347
1348/******************* Bit definition for CRS_CR register *********************/
1349#define CRS_CR_SYNCOKIE_Pos (0U)
1350#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
1351#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */
1352#define CRS_CR_SYNCWARNIE_Pos (1U)
1353#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
1354#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */
1355#define CRS_CR_ERRIE_Pos (2U)
1356#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
1357#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */
1358#define CRS_CR_ESYNCIE_Pos (3U)
1359#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
1360#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/
1361#define CRS_CR_CEN_Pos (5U)
1362#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
1363#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */
1364#define CRS_CR_AUTOTRIMEN_Pos (6U)
1365#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
1366#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */
1367#define CRS_CR_SWSYNC_Pos (7U)
1368#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
1369#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */
1370#define CRS_CR_TRIM_Pos (8U)
1371#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
1372#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */
1373
1374/******************* Bit definition for CRS_CFGR register *********************/
1375#define CRS_CFGR_RELOAD_Pos (0U)
1376#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
1377#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */
1378#define CRS_CFGR_FELIM_Pos (16U)
1379#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
1380#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */
1381
1382#define CRS_CFGR_SYNCDIV_Pos (24U)
1383#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
1384#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */
1385#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
1386#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
1387#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
1388
1389#define CRS_CFGR_SYNCSRC_Pos (28U)
1390#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
1391#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */
1392#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
1393#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
1394
1395#define CRS_CFGR_SYNCPOL_Pos (31U)
1396#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
1397#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */
1398
1399/******************* Bit definition for CRS_ISR register *********************/
1400#define CRS_ISR_SYNCOKF_Pos (0U)
1401#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
1402#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */
1403#define CRS_ISR_SYNCWARNF_Pos (1U)
1404#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
1405#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */
1406#define CRS_ISR_ERRF_Pos (2U)
1407#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
1408#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */
1409#define CRS_ISR_ESYNCF_Pos (3U)
1410#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
1411#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */
1412#define CRS_ISR_SYNCERR_Pos (8U)
1413#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
1414#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */
1415#define CRS_ISR_SYNCMISS_Pos (9U)
1416#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
1417#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */
1418#define CRS_ISR_TRIMOVF_Pos (10U)
1419#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
1420#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */
1421#define CRS_ISR_FEDIR_Pos (15U)
1422#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
1423#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */
1424#define CRS_ISR_FECAP_Pos (16U)
1425#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
1426#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */
1427
1428/******************* Bit definition for CRS_ICR register *********************/
1429#define CRS_ICR_SYNCOKC_Pos (0U)
1430#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
1431#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */
1432#define CRS_ICR_SYNCWARNC_Pos (1U)
1433#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
1434#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */
1435#define CRS_ICR_ERRC_Pos (2U)
1436#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
1437#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */
1438#define CRS_ICR_ESYNCC_Pos (3U)
1439#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
1440#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */
1441
1442/******************************************************************************/
1443/* */
1444/* Digital to Analog Converter (DAC) */
1445/* */
1446/******************************************************************************/
1447
1448/*
1449 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
1450 */
1451#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
1452
1453/******************** Bit definition for DAC_CR register ********************/
1454#define DAC_CR_EN1_Pos (0U)
1455#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
1456#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
1457#define DAC_CR_BOFF1_Pos (1U)
1458#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
1459#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
1460#define DAC_CR_TEN1_Pos (2U)
1461#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
1462#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
1463
1464#define DAC_CR_TSEL1_Pos (3U)
1465#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
1466#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
1467#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
1468#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
1469#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
1470
1471#define DAC_CR_WAVE1_Pos (6U)
1472#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
1473#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1474#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
1475#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
1476
1477#define DAC_CR_MAMP1_Pos (8U)
1478#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
1479#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1480#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
1481#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
1482#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
1483#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
1484
1485#define DAC_CR_DMAEN1_Pos (12U)
1486#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
1487#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
1488#define DAC_CR_DMAUDRIE1_Pos (13U)
1489#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
1490#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */
1491
1492#define DAC_CR_EN2_Pos (16U)
1493#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
1494#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
1495#define DAC_CR_BOFF2_Pos (17U)
1496#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
1497#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
1498#define DAC_CR_TEN2_Pos (18U)
1499#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
1500#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
1501
1502#define DAC_CR_TSEL2_Pos (19U)
1503#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
1504#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
1505#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
1506#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
1507#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
1508
1509#define DAC_CR_WAVE2_Pos (22U)
1510#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
1511#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
1512#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
1513#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
1514
1515#define DAC_CR_MAMP2_Pos (24U)
1516#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
1517#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
1518#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
1519#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
1520#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
1521#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
1522
1523#define DAC_CR_DMAEN2_Pos (28U)
1524#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
1525#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
1526#define DAC_CR_DMAUDRIE2_Pos (29U)
1527#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
1528#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel12DMA Underrun interrupt enable */
1529
1530/***************** Bit definition for DAC_SWTRIGR register ******************/
1531#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
1532#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
1533#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
1534#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
1535#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
1536#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
1537
1538/***************** Bit definition for DAC_DHR12R1 register ******************/
1539#define DAC_DHR12R1_DACC1DHR_Pos (0U)
1540#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
1541#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
1542
1543/***************** Bit definition for DAC_DHR12L1 register ******************/
1544#define DAC_DHR12L1_DACC1DHR_Pos (4U)
1545#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
1546#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
1547
1548/****************** Bit definition for DAC_DHR8R1 register ******************/
1549#define DAC_DHR8R1_DACC1DHR_Pos (0U)
1550#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
1551#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
1552
1553/***************** Bit definition for DAC_DHR12R2 register ******************/
1554#define DAC_DHR12R2_DACC2DHR_Pos (0U)
1555#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
1556#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
1557
1558/***************** Bit definition for DAC_DHR12L2 register ******************/
1559#define DAC_DHR12L2_DACC2DHR_Pos (4U)
1560#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
1561#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
1562
1563/****************** Bit definition for DAC_DHR8R2 register ******************/
1564#define DAC_DHR8R2_DACC2DHR_Pos (0U)
1565#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
1566#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
1567
1568/***************** Bit definition for DAC_DHR12RD register ******************/
1569#define DAC_DHR12RD_DACC1DHR_Pos (0U)
1570#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
1571#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
1572#define DAC_DHR12RD_DACC2DHR_Pos (16U)
1573#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
1574#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
1575
1576/***************** Bit definition for DAC_DHR12LD register ******************/
1577#define DAC_DHR12LD_DACC1DHR_Pos (4U)
1578#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
1579#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
1580#define DAC_DHR12LD_DACC2DHR_Pos (20U)
1581#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
1582#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
1583
1584/****************** Bit definition for DAC_DHR8RD register ******************/
1585#define DAC_DHR8RD_DACC1DHR_Pos (0U)
1586#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
1587#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
1588#define DAC_DHR8RD_DACC2DHR_Pos (8U)
1589#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
1590#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
1591
1592/******************* Bit definition for DAC_DOR1 register *******************/
1593#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */
1594
1595/******************* Bit definition for DAC_DOR2 register *******************/
1596#define DAC_DOR2_DACC2DOR_Pos (0U)
1597#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
1598#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
1599
1600/******************** Bit definition for DAC_SR register ********************/
1601#define DAC_SR_DMAUDR1_Pos (13U)
1602#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
1603#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
1604#define DAC_SR_DMAUDR2_Pos (29U)
1605#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
1606#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
1607
1608/******************************************************************************/
1609/* */
1610/* Debug MCU (DBGMCU) */
1611/* */
1612/******************************************************************************/
1613
1614/**************** Bit definition for DBGMCU_IDCODE register *****************/
1615#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
1616#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
1617#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
1618
1619#define DBGMCU_IDCODE_DIV_ID_Pos (12U)
1620#define DBGMCU_IDCODE_DIV_ID_Msk (0xFU << DBGMCU_IDCODE_DIV_ID_Pos) /*!< 0x0000F000 */
1621#define DBGMCU_IDCODE_DIV_ID DBGMCU_IDCODE_DIV_ID_Msk /*!< Division Identifier */
1622#define DBGMCU_IDCODE_MCD_DIV_ID_Pos (13U)
1623#define DBGMCU_IDCODE_MCD_DIV_ID_Msk (0x3U << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */
1624#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD divsion ID is 6 */
1625#define DBGMCU_IDCODE_REV_ID_Pos (16U)
1626#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
1627#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
1628#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
1629#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
1630#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
1631#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
1632#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
1633#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
1634#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
1635#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
1636#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
1637#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
1638#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
1639#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
1640#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
1641#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
1642#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
1643#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
1644
1645/****************** Bit definition for DBGMCU_CR register *******************/
1646#define DBGMCU_CR_DBG_Pos (0U)
1647#define DBGMCU_CR_DBG_Msk (0x7U << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
1648#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
1649#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
1650#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
1651#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
1652#define DBGMCU_CR_DBG_STOP_Pos (1U)
1653#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
1654#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
1655#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
1656#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
1657#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
1658
1659/****************** Bit definition for DBGMCU_APB1_FZ register **************/
1660#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
1661#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
1662#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
1663#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
1664#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
1665#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
1666#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
1667#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
1668#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
1669#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
1670#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
1671#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
1672#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
1673#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
1674#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
1675#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
1676#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
1677#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
1678#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
1679#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
1680#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
1681#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
1682#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
1683#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
1684#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
1685#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
1686#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
1687#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (23U)
1688#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
1689#define DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
1690#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
1691#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
1692#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
1693/****************** Bit definition for DBGMCU_APB2_FZ register **************/
1694#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
1695#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
1696#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
1697#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
1698#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
1699#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
1700
1701/******************************************************************************/
1702/* */
1703/* DMA Controller (DMA) */
1704/* */
1705/******************************************************************************/
1706
1707/******************* Bit definition for DMA_ISR register ********************/
1708#define DMA_ISR_GIF1_Pos (0U)
1709#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
1710#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
1711#define DMA_ISR_TCIF1_Pos (1U)
1712#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
1713#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
1714#define DMA_ISR_HTIF1_Pos (2U)
1715#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
1716#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
1717#define DMA_ISR_TEIF1_Pos (3U)
1718#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
1719#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
1720#define DMA_ISR_GIF2_Pos (4U)
1721#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
1722#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
1723#define DMA_ISR_TCIF2_Pos (5U)
1724#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
1725#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
1726#define DMA_ISR_HTIF2_Pos (6U)
1727#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
1728#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
1729#define DMA_ISR_TEIF2_Pos (7U)
1730#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
1731#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
1732#define DMA_ISR_GIF3_Pos (8U)
1733#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
1734#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
1735#define DMA_ISR_TCIF3_Pos (9U)
1736#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
1737#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
1738#define DMA_ISR_HTIF3_Pos (10U)
1739#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
1740#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
1741#define DMA_ISR_TEIF3_Pos (11U)
1742#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
1743#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
1744#define DMA_ISR_GIF4_Pos (12U)
1745#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
1746#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
1747#define DMA_ISR_TCIF4_Pos (13U)
1748#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
1749#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
1750#define DMA_ISR_HTIF4_Pos (14U)
1751#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
1752#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
1753#define DMA_ISR_TEIF4_Pos (15U)
1754#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
1755#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
1756#define DMA_ISR_GIF5_Pos (16U)
1757#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
1758#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
1759#define DMA_ISR_TCIF5_Pos (17U)
1760#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
1761#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
1762#define DMA_ISR_HTIF5_Pos (18U)
1763#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
1764#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
1765#define DMA_ISR_TEIF5_Pos (19U)
1766#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
1767#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
1768#define DMA_ISR_GIF6_Pos (20U)
1769#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
1770#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
1771#define DMA_ISR_TCIF6_Pos (21U)
1772#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
1773#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
1774#define DMA_ISR_HTIF6_Pos (22U)
1775#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
1776#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
1777#define DMA_ISR_TEIF6_Pos (23U)
1778#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
1779#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
1780#define DMA_ISR_GIF7_Pos (24U)
1781#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
1782#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
1783#define DMA_ISR_TCIF7_Pos (25U)
1784#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
1785#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
1786#define DMA_ISR_HTIF7_Pos (26U)
1787#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
1788#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
1789#define DMA_ISR_TEIF7_Pos (27U)
1790#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
1791#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
1792
1793/******************* Bit definition for DMA_IFCR register *******************/
1794#define DMA_IFCR_CGIF1_Pos (0U)
1795#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
1796#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
1797#define DMA_IFCR_CTCIF1_Pos (1U)
1798#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1799#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
1800#define DMA_IFCR_CHTIF1_Pos (2U)
1801#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1802#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
1803#define DMA_IFCR_CTEIF1_Pos (3U)
1804#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1805#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
1806#define DMA_IFCR_CGIF2_Pos (4U)
1807#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
1808#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
1809#define DMA_IFCR_CTCIF2_Pos (5U)
1810#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1811#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
1812#define DMA_IFCR_CHTIF2_Pos (6U)
1813#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1814#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
1815#define DMA_IFCR_CTEIF2_Pos (7U)
1816#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
1817#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
1818#define DMA_IFCR_CGIF3_Pos (8U)
1819#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
1820#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
1821#define DMA_IFCR_CTCIF3_Pos (9U)
1822#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
1823#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
1824#define DMA_IFCR_CHTIF3_Pos (10U)
1825#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
1826#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
1827#define DMA_IFCR_CTEIF3_Pos (11U)
1828#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
1829#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
1830#define DMA_IFCR_CGIF4_Pos (12U)
1831#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
1832#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
1833#define DMA_IFCR_CTCIF4_Pos (13U)
1834#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
1835#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
1836#define DMA_IFCR_CHTIF4_Pos (14U)
1837#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
1838#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
1839#define DMA_IFCR_CTEIF4_Pos (15U)
1840#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
1841#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
1842#define DMA_IFCR_CGIF5_Pos (16U)
1843#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
1844#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
1845#define DMA_IFCR_CTCIF5_Pos (17U)
1846#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
1847#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
1848#define DMA_IFCR_CHTIF5_Pos (18U)
1849#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
1850#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
1851#define DMA_IFCR_CTEIF5_Pos (19U)
1852#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
1853#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
1854#define DMA_IFCR_CGIF6_Pos (20U)
1855#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
1856#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
1857#define DMA_IFCR_CTCIF6_Pos (21U)
1858#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
1859#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
1860#define DMA_IFCR_CHTIF6_Pos (22U)
1861#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
1862#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
1863#define DMA_IFCR_CTEIF6_Pos (23U)
1864#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
1865#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
1866#define DMA_IFCR_CGIF7_Pos (24U)
1867#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
1868#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
1869#define DMA_IFCR_CTCIF7_Pos (25U)
1870#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
1871#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
1872#define DMA_IFCR_CHTIF7_Pos (26U)
1873#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
1874#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
1875#define DMA_IFCR_CTEIF7_Pos (27U)
1876#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
1877#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
1878
1879/******************* Bit definition for DMA_CCR register ********************/
1880#define DMA_CCR_EN_Pos (0U)
1881#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
1882#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
1883#define DMA_CCR_TCIE_Pos (1U)
1884#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
1885#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
1886#define DMA_CCR_HTIE_Pos (2U)
1887#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
1888#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
1889#define DMA_CCR_TEIE_Pos (3U)
1890#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
1891#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
1892#define DMA_CCR_DIR_Pos (4U)
1893#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
1894#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
1895#define DMA_CCR_CIRC_Pos (5U)
1896#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
1897#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
1898#define DMA_CCR_PINC_Pos (6U)
1899#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
1900#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
1901#define DMA_CCR_MINC_Pos (7U)
1902#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1903#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
1904
1905#define DMA_CCR_PSIZE_Pos (8U)
1906#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
1907#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
1908#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
1909#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
1910
1911#define DMA_CCR_MSIZE_Pos (10U)
1912#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
1913#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
1914#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
1915#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
1916
1917#define DMA_CCR_PL_Pos (12U)
1918#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
1919#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
1920#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
1921#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
1922
1923#define DMA_CCR_MEM2MEM_Pos (14U)
1924#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
1925#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
1926
1927/****************** Bit definition for DMA_CNDTR register *******************/
1928#define DMA_CNDTR_NDT_Pos (0U)
1929#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
1930#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
1931
1932/****************** Bit definition for DMA_CPAR register ********************/
1933#define DMA_CPAR_PA_Pos (0U)
1934#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
1935#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
1936
1937/****************** Bit definition for DMA_CMAR register ********************/
1938#define DMA_CMAR_MA_Pos (0U)
1939#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
1940#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
1941
1942
1943/******************* Bit definition for DMA_CSELR register *******************/
1944#define DMA_CSELR_C1S_Pos (0U)
1945#define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
1946#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
1947#define DMA_CSELR_C2S_Pos (4U)
1948#define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
1949#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
1950#define DMA_CSELR_C3S_Pos (8U)
1951#define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
1952#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
1953#define DMA_CSELR_C4S_Pos (12U)
1954#define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
1955#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
1956#define DMA_CSELR_C5S_Pos (16U)
1957#define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
1958#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
1959#define DMA_CSELR_C6S_Pos (20U)
1960#define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
1961#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
1962#define DMA_CSELR_C7S_Pos (24U)
1963#define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
1964#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
1965
1966/******************************************************************************/
1967/* */
1968/* External Interrupt/Event Controller (EXTI) */
1969/* */
1970/******************************************************************************/
1971
1972/******************* Bit definition for EXTI_IMR register *******************/
1973#define EXTI_IMR_IM0_Pos (0U)
1974#define EXTI_IMR_IM0_Msk (0x1U << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
1975#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
1976#define EXTI_IMR_IM1_Pos (1U)
1977#define EXTI_IMR_IM1_Msk (0x1U << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
1978#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
1979#define EXTI_IMR_IM2_Pos (2U)
1980#define EXTI_IMR_IM2_Msk (0x1U << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
1981#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
1982#define EXTI_IMR_IM3_Pos (3U)
1983#define EXTI_IMR_IM3_Msk (0x1U << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
1984#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
1985#define EXTI_IMR_IM4_Pos (4U)
1986#define EXTI_IMR_IM4_Msk (0x1U << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
1987#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
1988#define EXTI_IMR_IM5_Pos (5U)
1989#define EXTI_IMR_IM5_Msk (0x1U << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
1990#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
1991#define EXTI_IMR_IM6_Pos (6U)
1992#define EXTI_IMR_IM6_Msk (0x1U << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
1993#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
1994#define EXTI_IMR_IM7_Pos (7U)
1995#define EXTI_IMR_IM7_Msk (0x1U << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
1996#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
1997#define EXTI_IMR_IM8_Pos (8U)
1998#define EXTI_IMR_IM8_Msk (0x1U << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
1999#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
2000#define EXTI_IMR_IM9_Pos (9U)
2001#define EXTI_IMR_IM9_Msk (0x1U << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
2002#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
2003#define EXTI_IMR_IM10_Pos (10U)
2004#define EXTI_IMR_IM10_Msk (0x1U << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
2005#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
2006#define EXTI_IMR_IM11_Pos (11U)
2007#define EXTI_IMR_IM11_Msk (0x1U << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
2008#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
2009#define EXTI_IMR_IM12_Pos (12U)
2010#define EXTI_IMR_IM12_Msk (0x1U << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
2011#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
2012#define EXTI_IMR_IM13_Pos (13U)
2013#define EXTI_IMR_IM13_Msk (0x1U << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
2014#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
2015#define EXTI_IMR_IM14_Pos (14U)
2016#define EXTI_IMR_IM14_Msk (0x1U << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
2017#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
2018#define EXTI_IMR_IM15_Pos (15U)
2019#define EXTI_IMR_IM15_Msk (0x1U << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
2020#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
2021#define EXTI_IMR_IM16_Pos (16U)
2022#define EXTI_IMR_IM16_Msk (0x1U << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
2023#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
2024#define EXTI_IMR_IM17_Pos (17U)
2025#define EXTI_IMR_IM17_Msk (0x1U << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
2026#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
2027#define EXTI_IMR_IM18_Pos (18U)
2028#define EXTI_IMR_IM18_Msk (0x1U << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
2029#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
2030#define EXTI_IMR_IM19_Pos (19U)
2031#define EXTI_IMR_IM19_Msk (0x1U << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
2032#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
2033#define EXTI_IMR_IM20_Pos (20U)
2034#define EXTI_IMR_IM20_Msk (0x1U << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
2035#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
2036#define EXTI_IMR_IM21_Pos (21U)
2037#define EXTI_IMR_IM21_Msk (0x1U << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
2038#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
2039#define EXTI_IMR_IM22_Pos (22U)
2040#define EXTI_IMR_IM22_Msk (0x1U << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
2041#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
2042#define EXTI_IMR_IM23_Pos (23U)
2043#define EXTI_IMR_IM23_Msk (0x1U << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
2044#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
2045#define EXTI_IMR_IM24_Pos (24U)
2046#define EXTI_IMR_IM24_Msk (0x1U << EXTI_IMR_IM24_Pos) /*!< 0x01000000 */
2047#define EXTI_IMR_IM24 EXTI_IMR_IM24_Msk /*!< Interrupt Mask on line 24 */
2048#define EXTI_IMR_IM25_Pos (25U)
2049#define EXTI_IMR_IM25_Msk (0x1U << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
2050#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
2051#define EXTI_IMR_IM26_Pos (26U)
2052#define EXTI_IMR_IM26_Msk (0x1U << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
2053#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
2054#define EXTI_IMR_IM28_Pos (28U)
2055#define EXTI_IMR_IM28_Msk (0x1U << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
2056#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
2057#define EXTI_IMR_IM29_Pos (29U)
2058#define EXTI_IMR_IM29_Msk (0x1U << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
2059#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
2060
2061#define EXTI_IMR_IM_Pos (0U)
2062#define EXTI_IMR_IM_Msk (0x37FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x37FFFFFF */
2063#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
2064
2065/****************** Bit definition for EXTI_EMR register ********************/
2066#define EXTI_EMR_EM0_Pos (0U)
2067#define EXTI_EMR_EM0_Msk (0x1U << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
2068#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
2069#define EXTI_EMR_EM1_Pos (1U)
2070#define EXTI_EMR_EM1_Msk (0x1U << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
2071#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
2072#define EXTI_EMR_EM2_Pos (2U)
2073#define EXTI_EMR_EM2_Msk (0x1U << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
2074#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
2075#define EXTI_EMR_EM3_Pos (3U)
2076#define EXTI_EMR_EM3_Msk (0x1U << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
2077#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
2078#define EXTI_EMR_EM4_Pos (4U)
2079#define EXTI_EMR_EM4_Msk (0x1U << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
2080#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
2081#define EXTI_EMR_EM5_Pos (5U)
2082#define EXTI_EMR_EM5_Msk (0x1U << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
2083#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
2084#define EXTI_EMR_EM6_Pos (6U)
2085#define EXTI_EMR_EM6_Msk (0x1U << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
2086#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
2087#define EXTI_EMR_EM7_Pos (7U)
2088#define EXTI_EMR_EM7_Msk (0x1U << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
2089#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
2090#define EXTI_EMR_EM8_Pos (8U)
2091#define EXTI_EMR_EM8_Msk (0x1U << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
2092#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
2093#define EXTI_EMR_EM9_Pos (9U)
2094#define EXTI_EMR_EM9_Msk (0x1U << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
2095#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
2096#define EXTI_EMR_EM10_Pos (10U)
2097#define EXTI_EMR_EM10_Msk (0x1U << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
2098#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
2099#define EXTI_EMR_EM11_Pos (11U)
2100#define EXTI_EMR_EM11_Msk (0x1U << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
2101#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
2102#define EXTI_EMR_EM12_Pos (12U)
2103#define EXTI_EMR_EM12_Msk (0x1U << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
2104#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
2105#define EXTI_EMR_EM13_Pos (13U)
2106#define EXTI_EMR_EM13_Msk (0x1U << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
2107#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
2108#define EXTI_EMR_EM14_Pos (14U)
2109#define EXTI_EMR_EM14_Msk (0x1U << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
2110#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
2111#define EXTI_EMR_EM15_Pos (15U)
2112#define EXTI_EMR_EM15_Msk (0x1U << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
2113#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
2114#define EXTI_EMR_EM16_Pos (16U)
2115#define EXTI_EMR_EM16_Msk (0x1U << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
2116#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
2117#define EXTI_EMR_EM17_Pos (17U)
2118#define EXTI_EMR_EM17_Msk (0x1U << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
2119#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
2120#define EXTI_EMR_EM18_Pos (18U)
2121#define EXTI_EMR_EM18_Msk (0x1U << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
2122#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
2123#define EXTI_EMR_EM19_Pos (19U)
2124#define EXTI_EMR_EM19_Msk (0x1U << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
2125#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
2126#define EXTI_EMR_EM20_Pos (20U)
2127#define EXTI_EMR_EM20_Msk (0x1U << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
2128#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
2129#define EXTI_EMR_EM21_Pos (21U)
2130#define EXTI_EMR_EM21_Msk (0x1U << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
2131#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
2132#define EXTI_EMR_EM22_Pos (22U)
2133#define EXTI_EMR_EM22_Msk (0x1U << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
2134#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
2135#define EXTI_EMR_EM23_Pos (23U)
2136#define EXTI_EMR_EM23_Msk (0x1U << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
2137#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
2138#define EXTI_EMR_EM24_Pos (24U)
2139#define EXTI_EMR_EM24_Msk (0x1U << EXTI_EMR_EM24_Pos) /*!< 0x01000000 */
2140#define EXTI_EMR_EM24 EXTI_EMR_EM24_Msk /*!< Event Mask on line 24 */
2141#define EXTI_EMR_EM25_Pos (25U)
2142#define EXTI_EMR_EM25_Msk (0x1U << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
2143#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
2144#define EXTI_EMR_EM26_Pos (26U)
2145#define EXTI_EMR_EM26_Msk (0x1U << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
2146#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
2147#define EXTI_EMR_EM28_Pos (28U)
2148#define EXTI_EMR_EM28_Msk (0x1U << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
2149#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
2150#define EXTI_EMR_EM29_Pos (29U)
2151#define EXTI_EMR_EM29_Msk (0x1U << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
2152#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
2153
2154/******************* Bit definition for EXTI_RTSR register ******************/
2155#define EXTI_RTSR_RT0_Pos (0U)
2156#define EXTI_RTSR_RT0_Msk (0x1U << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
2157#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
2158#define EXTI_RTSR_RT1_Pos (1U)
2159#define EXTI_RTSR_RT1_Msk (0x1U << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
2160#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
2161#define EXTI_RTSR_RT2_Pos (2U)
2162#define EXTI_RTSR_RT2_Msk (0x1U << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
2163#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
2164#define EXTI_RTSR_RT3_Pos (3U)
2165#define EXTI_RTSR_RT3_Msk (0x1U << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
2166#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
2167#define EXTI_RTSR_RT4_Pos (4U)
2168#define EXTI_RTSR_RT4_Msk (0x1U << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
2169#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
2170#define EXTI_RTSR_RT5_Pos (5U)
2171#define EXTI_RTSR_RT5_Msk (0x1U << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
2172#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
2173#define EXTI_RTSR_RT6_Pos (6U)
2174#define EXTI_RTSR_RT6_Msk (0x1U << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
2175#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
2176#define EXTI_RTSR_RT7_Pos (7U)
2177#define EXTI_RTSR_RT7_Msk (0x1U << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
2178#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
2179#define EXTI_RTSR_RT8_Pos (8U)
2180#define EXTI_RTSR_RT8_Msk (0x1U << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
2181#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
2182#define EXTI_RTSR_RT9_Pos (9U)
2183#define EXTI_RTSR_RT9_Msk (0x1U << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
2184#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
2185#define EXTI_RTSR_RT10_Pos (10U)
2186#define EXTI_RTSR_RT10_Msk (0x1U << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
2187#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
2188#define EXTI_RTSR_RT11_Pos (11U)
2189#define EXTI_RTSR_RT11_Msk (0x1U << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
2190#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
2191#define EXTI_RTSR_RT12_Pos (12U)
2192#define EXTI_RTSR_RT12_Msk (0x1U << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
2193#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
2194#define EXTI_RTSR_RT13_Pos (13U)
2195#define EXTI_RTSR_RT13_Msk (0x1U << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
2196#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
2197#define EXTI_RTSR_RT14_Pos (14U)
2198#define EXTI_RTSR_RT14_Msk (0x1U << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
2199#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
2200#define EXTI_RTSR_RT15_Pos (15U)
2201#define EXTI_RTSR_RT15_Msk (0x1U << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
2202#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
2203#define EXTI_RTSR_RT16_Pos (16U)
2204#define EXTI_RTSR_RT16_Msk (0x1U << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
2205#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
2206#define EXTI_RTSR_RT17_Pos (17U)
2207#define EXTI_RTSR_RT17_Msk (0x1U << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
2208#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
2209#define EXTI_RTSR_RT19_Pos (19U)
2210#define EXTI_RTSR_RT19_Msk (0x1U << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
2211#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
2212#define EXTI_RTSR_RT20_Pos (20U)
2213#define EXTI_RTSR_RT20_Msk (0x1U << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
2214#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
2215#define EXTI_RTSR_RT21_Pos (21U)
2216#define EXTI_RTSR_RT21_Msk (0x1U << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
2217#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
2218#define EXTI_RTSR_RT22_Pos (22U)
2219#define EXTI_RTSR_RT22_Msk (0x1U << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
2220#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
2221
2222/* Legacy defines */
2223#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
2224#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
2225#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
2226#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
2227#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
2228#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
2229#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
2230#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
2231#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
2232#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
2233#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
2234#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
2235#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
2236#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
2237#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
2238#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
2239#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
2240#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
2241#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
2242#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
2243#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
2244#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
2245
2246/******************* Bit definition for EXTI_FTSR register *******************/
2247#define EXTI_FTSR_FT0_Pos (0U)
2248#define EXTI_FTSR_FT0_Msk (0x1U << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
2249#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
2250#define EXTI_FTSR_FT1_Pos (1U)
2251#define EXTI_FTSR_FT1_Msk (0x1U << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
2252#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
2253#define EXTI_FTSR_FT2_Pos (2U)
2254#define EXTI_FTSR_FT2_Msk (0x1U << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
2255#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
2256#define EXTI_FTSR_FT3_Pos (3U)
2257#define EXTI_FTSR_FT3_Msk (0x1U << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
2258#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
2259#define EXTI_FTSR_FT4_Pos (4U)
2260#define EXTI_FTSR_FT4_Msk (0x1U << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
2261#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
2262#define EXTI_FTSR_FT5_Pos (5U)
2263#define EXTI_FTSR_FT5_Msk (0x1U << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
2264#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
2265#define EXTI_FTSR_FT6_Pos (6U)
2266#define EXTI_FTSR_FT6_Msk (0x1U << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
2267#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
2268#define EXTI_FTSR_FT7_Pos (7U)
2269#define EXTI_FTSR_FT7_Msk (0x1U << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
2270#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
2271#define EXTI_FTSR_FT8_Pos (8U)
2272#define EXTI_FTSR_FT8_Msk (0x1U << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
2273#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
2274#define EXTI_FTSR_FT9_Pos (9U)
2275#define EXTI_FTSR_FT9_Msk (0x1U << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
2276#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
2277#define EXTI_FTSR_FT10_Pos (10U)
2278#define EXTI_FTSR_FT10_Msk (0x1U << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
2279#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
2280#define EXTI_FTSR_FT11_Pos (11U)
2281#define EXTI_FTSR_FT11_Msk (0x1U << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
2282#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
2283#define EXTI_FTSR_FT12_Pos (12U)
2284#define EXTI_FTSR_FT12_Msk (0x1U << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
2285#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
2286#define EXTI_FTSR_FT13_Pos (13U)
2287#define EXTI_FTSR_FT13_Msk (0x1U << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
2288#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
2289#define EXTI_FTSR_FT14_Pos (14U)
2290#define EXTI_FTSR_FT14_Msk (0x1U << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
2291#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
2292#define EXTI_FTSR_FT15_Pos (15U)
2293#define EXTI_FTSR_FT15_Msk (0x1U << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
2294#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
2295#define EXTI_FTSR_FT16_Pos (16U)
2296#define EXTI_FTSR_FT16_Msk (0x1U << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
2297#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
2298#define EXTI_FTSR_FT17_Pos (17U)
2299#define EXTI_FTSR_FT17_Msk (0x1U << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
2300#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
2301#define EXTI_FTSR_FT19_Pos (19U)
2302#define EXTI_FTSR_FT19_Msk (0x1U << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
2303#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
2304#define EXTI_FTSR_FT20_Pos (20U)
2305#define EXTI_FTSR_FT20_Msk (0x1U << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
2306#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
2307#define EXTI_FTSR_FT21_Pos (21U)
2308#define EXTI_FTSR_FT21_Msk (0x1U << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
2309#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
2310#define EXTI_FTSR_FT22_Pos (22U)
2311#define EXTI_FTSR_FT22_Msk (0x1U << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
2312#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
2313
2314/* Legacy defines */
2315#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
2316#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
2317#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
2318#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
2319#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
2320#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
2321#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
2322#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
2323#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
2324#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
2325#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
2326#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
2327#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
2328#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
2329#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
2330#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
2331#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
2332#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
2333#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
2334#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
2335#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
2336#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
2337
2338/******************* Bit definition for EXTI_SWIER register *******************/
2339#define EXTI_SWIER_SWI0_Pos (0U)
2340#define EXTI_SWIER_SWI0_Msk (0x1U << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
2341#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
2342#define EXTI_SWIER_SWI1_Pos (1U)
2343#define EXTI_SWIER_SWI1_Msk (0x1U << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
2344#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
2345#define EXTI_SWIER_SWI2_Pos (2U)
2346#define EXTI_SWIER_SWI2_Msk (0x1U << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
2347#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
2348#define EXTI_SWIER_SWI3_Pos (3U)
2349#define EXTI_SWIER_SWI3_Msk (0x1U << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
2350#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
2351#define EXTI_SWIER_SWI4_Pos (4U)
2352#define EXTI_SWIER_SWI4_Msk (0x1U << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
2353#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
2354#define EXTI_SWIER_SWI5_Pos (5U)
2355#define EXTI_SWIER_SWI5_Msk (0x1U << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
2356#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
2357#define EXTI_SWIER_SWI6_Pos (6U)
2358#define EXTI_SWIER_SWI6_Msk (0x1U << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
2359#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
2360#define EXTI_SWIER_SWI7_Pos (7U)
2361#define EXTI_SWIER_SWI7_Msk (0x1U << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
2362#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
2363#define EXTI_SWIER_SWI8_Pos (8U)
2364#define EXTI_SWIER_SWI8_Msk (0x1U << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
2365#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
2366#define EXTI_SWIER_SWI9_Pos (9U)
2367#define EXTI_SWIER_SWI9_Msk (0x1U << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
2368#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
2369#define EXTI_SWIER_SWI10_Pos (10U)
2370#define EXTI_SWIER_SWI10_Msk (0x1U << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
2371#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
2372#define EXTI_SWIER_SWI11_Pos (11U)
2373#define EXTI_SWIER_SWI11_Msk (0x1U << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
2374#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
2375#define EXTI_SWIER_SWI12_Pos (12U)
2376#define EXTI_SWIER_SWI12_Msk (0x1U << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
2377#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
2378#define EXTI_SWIER_SWI13_Pos (13U)
2379#define EXTI_SWIER_SWI13_Msk (0x1U << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
2380#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
2381#define EXTI_SWIER_SWI14_Pos (14U)
2382#define EXTI_SWIER_SWI14_Msk (0x1U << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
2383#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
2384#define EXTI_SWIER_SWI15_Pos (15U)
2385#define EXTI_SWIER_SWI15_Msk (0x1U << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
2386#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
2387#define EXTI_SWIER_SWI16_Pos (16U)
2388#define EXTI_SWIER_SWI16_Msk (0x1U << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
2389#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
2390#define EXTI_SWIER_SWI17_Pos (17U)
2391#define EXTI_SWIER_SWI17_Msk (0x1U << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
2392#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
2393#define EXTI_SWIER_SWI19_Pos (19U)
2394#define EXTI_SWIER_SWI19_Msk (0x1U << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
2395#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
2396#define EXTI_SWIER_SWI20_Pos (20U)
2397#define EXTI_SWIER_SWI20_Msk (0x1U << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
2398#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
2399#define EXTI_SWIER_SWI21_Pos (21U)
2400#define EXTI_SWIER_SWI21_Msk (0x1U << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
2401#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
2402#define EXTI_SWIER_SWI22_Pos (22U)
2403#define EXTI_SWIER_SWI22_Msk (0x1U << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
2404#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
2405
2406/* Legacy defines */
2407#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
2408#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
2409#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
2410#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
2411#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
2412#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
2413#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
2414#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
2415#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
2416#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
2417#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
2418#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
2419#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
2420#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
2421#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
2422#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
2423#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
2424#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
2425#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
2426#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
2427#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
2428#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
2429
2430/****************** Bit definition for EXTI_PR register *********************/
2431#define EXTI_PR_PIF0_Pos (0U)
2432#define EXTI_PR_PIF0_Msk (0x1U << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
2433#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
2434#define EXTI_PR_PIF1_Pos (1U)
2435#define EXTI_PR_PIF1_Msk (0x1U << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
2436#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
2437#define EXTI_PR_PIF2_Pos (2U)
2438#define EXTI_PR_PIF2_Msk (0x1U << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
2439#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
2440#define EXTI_PR_PIF3_Pos (3U)
2441#define EXTI_PR_PIF3_Msk (0x1U << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
2442#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
2443#define EXTI_PR_PIF4_Pos (4U)
2444#define EXTI_PR_PIF4_Msk (0x1U << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
2445#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
2446#define EXTI_PR_PIF5_Pos (5U)
2447#define EXTI_PR_PIF5_Msk (0x1U << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
2448#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
2449#define EXTI_PR_PIF6_Pos (6U)
2450#define EXTI_PR_PIF6_Msk (0x1U << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
2451#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
2452#define EXTI_PR_PIF7_Pos (7U)
2453#define EXTI_PR_PIF7_Msk (0x1U << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
2454#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
2455#define EXTI_PR_PIF8_Pos (8U)
2456#define EXTI_PR_PIF8_Msk (0x1U << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
2457#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
2458#define EXTI_PR_PIF9_Pos (9U)
2459#define EXTI_PR_PIF9_Msk (0x1U << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
2460#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
2461#define EXTI_PR_PIF10_Pos (10U)
2462#define EXTI_PR_PIF10_Msk (0x1U << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
2463#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
2464#define EXTI_PR_PIF11_Pos (11U)
2465#define EXTI_PR_PIF11_Msk (0x1U << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
2466#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
2467#define EXTI_PR_PIF12_Pos (12U)
2468#define EXTI_PR_PIF12_Msk (0x1U << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
2469#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
2470#define EXTI_PR_PIF13_Pos (13U)
2471#define EXTI_PR_PIF13_Msk (0x1U << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
2472#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
2473#define EXTI_PR_PIF14_Pos (14U)
2474#define EXTI_PR_PIF14_Msk (0x1U << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
2475#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
2476#define EXTI_PR_PIF15_Pos (15U)
2477#define EXTI_PR_PIF15_Msk (0x1U << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
2478#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
2479#define EXTI_PR_PIF16_Pos (16U)
2480#define EXTI_PR_PIF16_Msk (0x1U << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
2481#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
2482#define EXTI_PR_PIF17_Pos (17U)
2483#define EXTI_PR_PIF17_Msk (0x1U << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
2484#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
2485#define EXTI_PR_PIF19_Pos (19U)
2486#define EXTI_PR_PIF19_Msk (0x1U << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
2487#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
2488#define EXTI_PR_PIF20_Pos (20U)
2489#define EXTI_PR_PIF20_Msk (0x1U << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
2490#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
2491#define EXTI_PR_PIF21_Pos (21U)
2492#define EXTI_PR_PIF21_Msk (0x1U << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
2493#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
2494#define EXTI_PR_PIF22_Pos (22U)
2495#define EXTI_PR_PIF22_Msk (0x1U << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
2496#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
2497
2498/* Legacy defines */
2499#define EXTI_PR_PR0 EXTI_PR_PIF0
2500#define EXTI_PR_PR1 EXTI_PR_PIF1
2501#define EXTI_PR_PR2 EXTI_PR_PIF2
2502#define EXTI_PR_PR3 EXTI_PR_PIF3
2503#define EXTI_PR_PR4 EXTI_PR_PIF4
2504#define EXTI_PR_PR5 EXTI_PR_PIF5
2505#define EXTI_PR_PR6 EXTI_PR_PIF6
2506#define EXTI_PR_PR7 EXTI_PR_PIF7
2507#define EXTI_PR_PR8 EXTI_PR_PIF8
2508#define EXTI_PR_PR9 EXTI_PR_PIF9
2509#define EXTI_PR_PR10 EXTI_PR_PIF10
2510#define EXTI_PR_PR11 EXTI_PR_PIF11
2511#define EXTI_PR_PR12 EXTI_PR_PIF12
2512#define EXTI_PR_PR13 EXTI_PR_PIF13
2513#define EXTI_PR_PR14 EXTI_PR_PIF14
2514#define EXTI_PR_PR15 EXTI_PR_PIF15
2515#define EXTI_PR_PR16 EXTI_PR_PIF16
2516#define EXTI_PR_PR17 EXTI_PR_PIF17
2517#define EXTI_PR_PR19 EXTI_PR_PIF19
2518#define EXTI_PR_PR20 EXTI_PR_PIF20
2519#define EXTI_PR_PR21 EXTI_PR_PIF21
2520#define EXTI_PR_PR22 EXTI_PR_PIF22
2521
2522/******************************************************************************/
2523/* */
2524/* FLASH and Option Bytes Registers */
2525/* */
2526/******************************************************************************/
2527
2528/******************* Bit definition for FLASH_ACR register ******************/
2529#define FLASH_ACR_LATENCY_Pos (0U)
2530#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
2531#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
2532#define FLASH_ACR_PRFTEN_Pos (1U)
2533#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
2534#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
2535#define FLASH_ACR_SLEEP_PD_Pos (3U)
2536#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
2537#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
2538#define FLASH_ACR_RUN_PD_Pos (4U)
2539#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
2540#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
2541#define FLASH_ACR_DISAB_BUF_Pos (5U)
2542#define FLASH_ACR_DISAB_BUF_Msk (0x1U << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
2543#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
2544#define FLASH_ACR_PRE_READ_Pos (6U)
2545#define FLASH_ACR_PRE_READ_Msk (0x1U << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
2546#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
2547
2548/******************* Bit definition for FLASH_PECR register ******************/
2549#define FLASH_PECR_PELOCK_Pos (0U)
2550#define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
2551#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
2552#define FLASH_PECR_PRGLOCK_Pos (1U)
2553#define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
2554#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
2555#define FLASH_PECR_OPTLOCK_Pos (2U)
2556#define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
2557#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
2558#define FLASH_PECR_PROG_Pos (3U)
2559#define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
2560#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
2561#define FLASH_PECR_DATA_Pos (4U)
2562#define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
2563#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
2564#define FLASH_PECR_FIX_Pos (8U)
2565#define FLASH_PECR_FIX_Msk (0x1U << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
2566#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
2567#define FLASH_PECR_ERASE_Pos (9U)
2568#define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
2569#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
2570#define FLASH_PECR_FPRG_Pos (10U)
2571#define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
2572#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
2573#define FLASH_PECR_PARALLBANK_Pos (15U)
2574#define FLASH_PECR_PARALLBANK_Msk (0x1U << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
2575#define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */
2576#define FLASH_PECR_EOPIE_Pos (16U)
2577#define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
2578#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
2579#define FLASH_PECR_ERRIE_Pos (17U)
2580#define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
2581#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
2582#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
2583#define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
2584#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
2585#define FLASH_PECR_HALF_ARRAY_Pos (19U)
2586#define FLASH_PECR_HALF_ARRAY_Msk (0x1U << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
2587#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
2588#define FLASH_PECR_NZDISABLE_Pos (22U)
2589#define FLASH_PECR_NZDISABLE_Msk (0x1U << FLASH_PECR_NZDISABLE_Pos) /*!< 0x00400000 */
2590#define FLASH_PECR_NZDISABLE FLASH_PECR_NZDISABLE_Msk /*!< Non-Zero check disable */
2591
2592/****************** Bit definition for FLASH_PDKEYR register ******************/
2593#define FLASH_PDKEYR_PDKEYR_Pos (0U)
2594#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
2595#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
2596
2597/****************** Bit definition for FLASH_PEKEYR register ******************/
2598#define FLASH_PEKEYR_PEKEYR_Pos (0U)
2599#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
2600#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
2601
2602/****************** Bit definition for FLASH_PRGKEYR register ******************/
2603#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
2604#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
2605#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
2606
2607/****************** Bit definition for FLASH_OPTKEYR register ******************/
2608#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
2609#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
2610#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
2611
2612/****************** Bit definition for FLASH_SR register *******************/
2613#define FLASH_SR_BSY_Pos (0U)
2614#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
2615#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
2616#define FLASH_SR_EOP_Pos (1U)
2617#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
2618#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
2619#define FLASH_SR_HVOFF_Pos (2U)
2620#define FLASH_SR_HVOFF_Msk (0x1U << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
2621#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
2622#define FLASH_SR_READY_Pos (3U)
2623#define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */
2624#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
2625
2626#define FLASH_SR_WRPERR_Pos (8U)
2627#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
2628#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
2629#define FLASH_SR_PGAERR_Pos (9U)
2630#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
2631#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
2632#define FLASH_SR_SIZERR_Pos (10U)
2633#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
2634#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
2635#define FLASH_SR_OPTVERR_Pos (11U)
2636#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
2637#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
2638#define FLASH_SR_RDERR_Pos (13U)
2639#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
2640#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
2641#define FLASH_SR_NOTZEROERR_Pos (16U)
2642#define FLASH_SR_NOTZEROERR_Msk (0x1U << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
2643#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
2644#define FLASH_SR_FWWERR_Pos (17U)
2645#define FLASH_SR_FWWERR_Msk (0x1U << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
2646#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
2647
2648/* Legacy defines */
2649#define FLASH_SR_FWWER FLASH_SR_FWWERR
2650#define FLASH_SR_ENHV FLASH_SR_HVOFF
2651#define FLASH_SR_ENDHV FLASH_SR_HVOFF
2652
2653/****************** Bit definition for FLASH_OPTR register *******************/
2654#define FLASH_OPTR_RDPROT_Pos (0U)
2655#define FLASH_OPTR_RDPROT_Msk (0xFFU << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
2656#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
2657#define FLASH_OPTR_WPRMOD_Pos (8U)
2658#define FLASH_OPTR_WPRMOD_Msk (0x1U << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
2659#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
2660#define FLASH_OPTR_BOR_LEV_Pos (16U)
2661#define FLASH_OPTR_BOR_LEV_Msk (0xFU << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
2662#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
2663#define FLASH_OPTR_IWDG_SW_Pos (20U)
2664#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
2665#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
2666#define FLASH_OPTR_nRST_STOP_Pos (21U)
2667#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
2668#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
2669#define FLASH_OPTR_nRST_STDBY_Pos (22U)
2670#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
2671#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
2672#define FLASH_OPTR_BFB2_Pos (23U)
2673#define FLASH_OPTR_BFB2_Msk (0x1U << FLASH_OPTR_BFB2_Pos) /*!< 0x00800000 */
2674#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk /*!< BFB2 */
2675#define FLASH_OPTR_USER_Pos (20U)
2676#define FLASH_OPTR_USER_Msk (0x7U << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
2677#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
2678#define FLASH_OPTR_BOOT1_Pos (31U)
2679#define FLASH_OPTR_BOOT1_Msk (0x1U << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
2680#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
2681
2682/****************** Bit definition for FLASH_WRPR register ******************/
2683#define FLASH_WRPR_WRP_Pos (0U)
2684#define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
2685#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
2686
2687/******************************************************************************/
2688/* */
2689/* General Purpose IOs (GPIO) */
2690/* */
2691/******************************************************************************/
2692/******************* Bit definition for GPIO_MODER register *****************/
2693#define GPIO_MODER_MODE0_Pos (0U)
2694#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
2695#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
2696#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
2697#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
2698#define GPIO_MODER_MODE1_Pos (2U)
2699#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
2700#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
2701#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
2702#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
2703#define GPIO_MODER_MODE2_Pos (4U)
2704#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
2705#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
2706#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
2707#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
2708#define GPIO_MODER_MODE3_Pos (6U)
2709#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
2710#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
2711#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
2712#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
2713#define GPIO_MODER_MODE4_Pos (8U)
2714#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
2715#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
2716#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
2717#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
2718#define GPIO_MODER_MODE5_Pos (10U)
2719#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
2720#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
2721#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
2722#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
2723#define GPIO_MODER_MODE6_Pos (12U)
2724#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
2725#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
2726#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
2727#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
2728#define GPIO_MODER_MODE7_Pos (14U)
2729#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
2730#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
2731#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
2732#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
2733#define GPIO_MODER_MODE8_Pos (16U)
2734#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
2735#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
2736#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
2737#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
2738#define GPIO_MODER_MODE9_Pos (18U)
2739#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
2740#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
2741#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
2742#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
2743#define GPIO_MODER_MODE10_Pos (20U)
2744#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
2745#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
2746#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
2747#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
2748#define GPIO_MODER_MODE11_Pos (22U)
2749#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
2750#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
2751#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
2752#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
2753#define GPIO_MODER_MODE12_Pos (24U)
2754#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
2755#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
2756#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
2757#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
2758#define GPIO_MODER_MODE13_Pos (26U)
2759#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
2760#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
2761#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
2762#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
2763#define GPIO_MODER_MODE14_Pos (28U)
2764#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
2765#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
2766#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
2767#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
2768#define GPIO_MODER_MODE15_Pos (30U)
2769#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
2770#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
2771#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
2772#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
2773
2774/****************** Bit definition for GPIO_OTYPER register *****************/
2775#define GPIO_OTYPER_OT_0 (0x00000001U)
2776#define GPIO_OTYPER_OT_1 (0x00000002U)
2777#define GPIO_OTYPER_OT_2 (0x00000004U)
2778#define GPIO_OTYPER_OT_3 (0x00000008U)
2779#define GPIO_OTYPER_OT_4 (0x00000010U)
2780#define GPIO_OTYPER_OT_5 (0x00000020U)
2781#define GPIO_OTYPER_OT_6 (0x00000040U)
2782#define GPIO_OTYPER_OT_7 (0x00000080U)
2783#define GPIO_OTYPER_OT_8 (0x00000100U)
2784#define GPIO_OTYPER_OT_9 (0x00000200U)
2785#define GPIO_OTYPER_OT_10 (0x00000400U)
2786#define GPIO_OTYPER_OT_11 (0x00000800U)
2787#define GPIO_OTYPER_OT_12 (0x00001000U)
2788#define GPIO_OTYPER_OT_13 (0x00002000U)
2789#define GPIO_OTYPER_OT_14 (0x00004000U)
2790#define GPIO_OTYPER_OT_15 (0x00008000U)
2791
2792/**************** Bit definition for GPIO_OSPEEDR register ******************/
2793#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
2794#define GPIO_OSPEEDER_OSPEED0_Msk (0x3U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
2795#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
2796#define GPIO_OSPEEDER_OSPEED0_0 (0x1U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
2797#define GPIO_OSPEEDER_OSPEED0_1 (0x2U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
2798#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
2799#define GPIO_OSPEEDER_OSPEED1_Msk (0x3U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
2800#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
2801#define GPIO_OSPEEDER_OSPEED1_0 (0x1U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
2802#define GPIO_OSPEEDER_OSPEED1_1 (0x2U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
2803#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
2804#define GPIO_OSPEEDER_OSPEED2_Msk (0x3U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
2805#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
2806#define GPIO_OSPEEDER_OSPEED2_0 (0x1U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
2807#define GPIO_OSPEEDER_OSPEED2_1 (0x2U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
2808#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
2809#define GPIO_OSPEEDER_OSPEED3_Msk (0x3U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
2810#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
2811#define GPIO_OSPEEDER_OSPEED3_0 (0x1U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
2812#define GPIO_OSPEEDER_OSPEED3_1 (0x2U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
2813#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
2814#define GPIO_OSPEEDER_OSPEED4_Msk (0x3U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
2815#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
2816#define GPIO_OSPEEDER_OSPEED4_0 (0x1U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
2817#define GPIO_OSPEEDER_OSPEED4_1 (0x2U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
2818#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
2819#define GPIO_OSPEEDER_OSPEED5_Msk (0x3U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
2820#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
2821#define GPIO_OSPEEDER_OSPEED5_0 (0x1U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
2822#define GPIO_OSPEEDER_OSPEED5_1 (0x2U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
2823#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
2824#define GPIO_OSPEEDER_OSPEED6_Msk (0x3U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
2825#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
2826#define GPIO_OSPEEDER_OSPEED6_0 (0x1U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
2827#define GPIO_OSPEEDER_OSPEED6_1 (0x2U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
2828#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
2829#define GPIO_OSPEEDER_OSPEED7_Msk (0x3U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
2830#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
2831#define GPIO_OSPEEDER_OSPEED7_0 (0x1U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
2832#define GPIO_OSPEEDER_OSPEED7_1 (0x2U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
2833#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
2834#define GPIO_OSPEEDER_OSPEED8_Msk (0x3U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
2835#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
2836#define GPIO_OSPEEDER_OSPEED8_0 (0x1U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
2837#define GPIO_OSPEEDER_OSPEED8_1 (0x2U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
2838#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
2839#define GPIO_OSPEEDER_OSPEED9_Msk (0x3U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
2840#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
2841#define GPIO_OSPEEDER_OSPEED9_0 (0x1U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
2842#define GPIO_OSPEEDER_OSPEED9_1 (0x2U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
2843#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
2844#define GPIO_OSPEEDER_OSPEED10_Msk (0x3U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
2845#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
2846#define GPIO_OSPEEDER_OSPEED10_0 (0x1U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
2847#define GPIO_OSPEEDER_OSPEED10_1 (0x2U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
2848#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
2849#define GPIO_OSPEEDER_OSPEED11_Msk (0x3U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
2850#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
2851#define GPIO_OSPEEDER_OSPEED11_0 (0x1U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
2852#define GPIO_OSPEEDER_OSPEED11_1 (0x2U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
2853#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
2854#define GPIO_OSPEEDER_OSPEED12_Msk (0x3U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
2855#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
2856#define GPIO_OSPEEDER_OSPEED12_0 (0x1U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
2857#define GPIO_OSPEEDER_OSPEED12_1 (0x2U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
2858#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
2859#define GPIO_OSPEEDER_OSPEED13_Msk (0x3U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
2860#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
2861#define GPIO_OSPEEDER_OSPEED13_0 (0x1U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
2862#define GPIO_OSPEEDER_OSPEED13_1 (0x2U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
2863#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
2864#define GPIO_OSPEEDER_OSPEED14_Msk (0x3U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
2865#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
2866#define GPIO_OSPEEDER_OSPEED14_0 (0x1U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
2867#define GPIO_OSPEEDER_OSPEED14_1 (0x2U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
2868#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
2869#define GPIO_OSPEEDER_OSPEED15_Msk (0x3U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
2870#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
2871#define GPIO_OSPEEDER_OSPEED15_0 (0x1U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
2872#define GPIO_OSPEEDER_OSPEED15_1 (0x2U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
2873
2874/******************* Bit definition for GPIO_PUPDR register ******************/
2875#define GPIO_PUPDR_PUPD0_Pos (0U)
2876#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
2877#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
2878#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
2879#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
2880#define GPIO_PUPDR_PUPD1_Pos (2U)
2881#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
2882#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
2883#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
2884#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
2885#define GPIO_PUPDR_PUPD2_Pos (4U)
2886#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
2887#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
2888#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
2889#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
2890#define GPIO_PUPDR_PUPD3_Pos (6U)
2891#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
2892#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
2893#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
2894#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
2895#define GPIO_PUPDR_PUPD4_Pos (8U)
2896#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
2897#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
2898#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
2899#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
2900#define GPIO_PUPDR_PUPD5_Pos (10U)
2901#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
2902#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
2903#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
2904#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
2905#define GPIO_PUPDR_PUPD6_Pos (12U)
2906#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
2907#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
2908#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
2909#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
2910#define GPIO_PUPDR_PUPD7_Pos (14U)
2911#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
2912#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
2913#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
2914#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
2915#define GPIO_PUPDR_PUPD8_Pos (16U)
2916#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
2917#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
2918#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
2919#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
2920#define GPIO_PUPDR_PUPD9_Pos (18U)
2921#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
2922#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
2923#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
2924#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
2925#define GPIO_PUPDR_PUPD10_Pos (20U)
2926#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
2927#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
2928#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
2929#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
2930#define GPIO_PUPDR_PUPD11_Pos (22U)
2931#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
2932#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
2933#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
2934#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
2935#define GPIO_PUPDR_PUPD12_Pos (24U)
2936#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
2937#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
2938#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
2939#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
2940#define GPIO_PUPDR_PUPD13_Pos (26U)
2941#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
2942#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
2943#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
2944#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
2945#define GPIO_PUPDR_PUPD14_Pos (28U)
2946#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
2947#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
2948#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
2949#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
2950#define GPIO_PUPDR_PUPD15_Pos (30U)
2951#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
2952#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
2953#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
2954#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
2955
2956/******************* Bit definition for GPIO_IDR register *******************/
2957#define GPIO_IDR_ID0_Pos (0U)
2958#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
2959#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
2960#define GPIO_IDR_ID1_Pos (1U)
2961#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
2962#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
2963#define GPIO_IDR_ID2_Pos (2U)
2964#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
2965#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
2966#define GPIO_IDR_ID3_Pos (3U)
2967#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
2968#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
2969#define GPIO_IDR_ID4_Pos (4U)
2970#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
2971#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
2972#define GPIO_IDR_ID5_Pos (5U)
2973#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
2974#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
2975#define GPIO_IDR_ID6_Pos (6U)
2976#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
2977#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
2978#define GPIO_IDR_ID7_Pos (7U)
2979#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
2980#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
2981#define GPIO_IDR_ID8_Pos (8U)
2982#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
2983#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
2984#define GPIO_IDR_ID9_Pos (9U)
2985#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
2986#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
2987#define GPIO_IDR_ID10_Pos (10U)
2988#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
2989#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
2990#define GPIO_IDR_ID11_Pos (11U)
2991#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
2992#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
2993#define GPIO_IDR_ID12_Pos (12U)
2994#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
2995#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
2996#define GPIO_IDR_ID13_Pos (13U)
2997#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
2998#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
2999#define GPIO_IDR_ID14_Pos (14U)
3000#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
3001#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
3002#define GPIO_IDR_ID15_Pos (15U)
3003#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
3004#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
3005
3006/****************** Bit definition for GPIO_ODR register ********************/
3007#define GPIO_ODR_OD0_Pos (0U)
3008#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
3009#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
3010#define GPIO_ODR_OD1_Pos (1U)
3011#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
3012#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
3013#define GPIO_ODR_OD2_Pos (2U)
3014#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
3015#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
3016#define GPIO_ODR_OD3_Pos (3U)
3017#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
3018#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
3019#define GPIO_ODR_OD4_Pos (4U)
3020#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
3021#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
3022#define GPIO_ODR_OD5_Pos (5U)
3023#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
3024#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
3025#define GPIO_ODR_OD6_Pos (6U)
3026#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
3027#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
3028#define GPIO_ODR_OD7_Pos (7U)
3029#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
3030#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
3031#define GPIO_ODR_OD8_Pos (8U)
3032#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
3033#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
3034#define GPIO_ODR_OD9_Pos (9U)
3035#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
3036#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
3037#define GPIO_ODR_OD10_Pos (10U)
3038#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
3039#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
3040#define GPIO_ODR_OD11_Pos (11U)
3041#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
3042#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
3043#define GPIO_ODR_OD12_Pos (12U)
3044#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
3045#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
3046#define GPIO_ODR_OD13_Pos (13U)
3047#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
3048#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
3049#define GPIO_ODR_OD14_Pos (14U)
3050#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
3051#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
3052#define GPIO_ODR_OD15_Pos (15U)
3053#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
3054#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
3055
3056/****************** Bit definition for GPIO_BSRR register ********************/
3057#define GPIO_BSRR_BS_0 (0x00000001U)
3058#define GPIO_BSRR_BS_1 (0x00000002U)
3059#define GPIO_BSRR_BS_2 (0x00000004U)
3060#define GPIO_BSRR_BS_3 (0x00000008U)
3061#define GPIO_BSRR_BS_4 (0x00000010U)
3062#define GPIO_BSRR_BS_5 (0x00000020U)
3063#define GPIO_BSRR_BS_6 (0x00000040U)
3064#define GPIO_BSRR_BS_7 (0x00000080U)
3065#define GPIO_BSRR_BS_8 (0x00000100U)
3066#define GPIO_BSRR_BS_9 (0x00000200U)
3067#define GPIO_BSRR_BS_10 (0x00000400U)
3068#define GPIO_BSRR_BS_11 (0x00000800U)
3069#define GPIO_BSRR_BS_12 (0x00001000U)
3070#define GPIO_BSRR_BS_13 (0x00002000U)
3071#define GPIO_BSRR_BS_14 (0x00004000U)
3072#define GPIO_BSRR_BS_15 (0x00008000U)
3073#define GPIO_BSRR_BR_0 (0x00010000U)
3074#define GPIO_BSRR_BR_1 (0x00020000U)
3075#define GPIO_BSRR_BR_2 (0x00040000U)
3076#define GPIO_BSRR_BR_3 (0x00080000U)
3077#define GPIO_BSRR_BR_4 (0x00100000U)
3078#define GPIO_BSRR_BR_5 (0x00200000U)
3079#define GPIO_BSRR_BR_6 (0x00400000U)
3080#define GPIO_BSRR_BR_7 (0x00800000U)
3081#define GPIO_BSRR_BR_8 (0x01000000U)
3082#define GPIO_BSRR_BR_9 (0x02000000U)
3083#define GPIO_BSRR_BR_10 (0x04000000U)
3084#define GPIO_BSRR_BR_11 (0x08000000U)
3085#define GPIO_BSRR_BR_12 (0x10000000U)
3086#define GPIO_BSRR_BR_13 (0x20000000U)
3087#define GPIO_BSRR_BR_14 (0x40000000U)
3088#define GPIO_BSRR_BR_15 (0x80000000U)
3089
3090/****************** Bit definition for GPIO_LCKR register ********************/
3091#define GPIO_LCKR_LCK0_Pos (0U)
3092#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
3093#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
3094#define GPIO_LCKR_LCK1_Pos (1U)
3095#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
3096#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
3097#define GPIO_LCKR_LCK2_Pos (2U)
3098#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
3099#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
3100#define GPIO_LCKR_LCK3_Pos (3U)
3101#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
3102#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
3103#define GPIO_LCKR_LCK4_Pos (4U)
3104#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
3105#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
3106#define GPIO_LCKR_LCK5_Pos (5U)
3107#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
3108#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
3109#define GPIO_LCKR_LCK6_Pos (6U)
3110#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
3111#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
3112#define GPIO_LCKR_LCK7_Pos (7U)
3113#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
3114#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
3115#define GPIO_LCKR_LCK8_Pos (8U)
3116#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
3117#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
3118#define GPIO_LCKR_LCK9_Pos (9U)
3119#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
3120#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
3121#define GPIO_LCKR_LCK10_Pos (10U)
3122#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
3123#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
3124#define GPIO_LCKR_LCK11_Pos (11U)
3125#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
3126#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
3127#define GPIO_LCKR_LCK12_Pos (12U)
3128#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
3129#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
3130#define GPIO_LCKR_LCK13_Pos (13U)
3131#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
3132#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
3133#define GPIO_LCKR_LCK14_Pos (14U)
3134#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
3135#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
3136#define GPIO_LCKR_LCK15_Pos (15U)
3137#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
3138#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
3139#define GPIO_LCKR_LCKK_Pos (16U)
3140#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
3141#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
3142
3143/****************** Bit definition for GPIO_AFRL register ********************/
3144#define GPIO_AFRL_AFRL0_Pos (0U)
3145#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
3146#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
3147#define GPIO_AFRL_AFRL1_Pos (4U)
3148#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
3149#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
3150#define GPIO_AFRL_AFRL2_Pos (8U)
3151#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
3152#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
3153#define GPIO_AFRL_AFRL3_Pos (12U)
3154#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
3155#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
3156#define GPIO_AFRL_AFRL4_Pos (16U)
3157#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
3158#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
3159#define GPIO_AFRL_AFRL5_Pos (20U)
3160#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
3161#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
3162#define GPIO_AFRL_AFRL6_Pos (24U)
3163#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
3164#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
3165#define GPIO_AFRL_AFRL7_Pos (28U)
3166#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
3167#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
3168
3169/****************** Bit definition for GPIO_AFRH register ********************/
3170#define GPIO_AFRH_AFRH0_Pos (0U)
3171#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
3172#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
3173#define GPIO_AFRH_AFRH1_Pos (4U)
3174#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
3175#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
3176#define GPIO_AFRH_AFRH2_Pos (8U)
3177#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
3178#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
3179#define GPIO_AFRH_AFRH3_Pos (12U)
3180#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
3181#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
3182#define GPIO_AFRH_AFRH4_Pos (16U)
3183#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
3184#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
3185#define GPIO_AFRH_AFRH5_Pos (20U)
3186#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
3187#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
3188#define GPIO_AFRH_AFRH6_Pos (24U)
3189#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
3190#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
3191#define GPIO_AFRH_AFRH7_Pos (28U)
3192#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
3193#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
3194
3195/****************** Bit definition for GPIO_BRR register *********************/
3196#define GPIO_BRR_BR_0 (0x00000001U)
3197#define GPIO_BRR_BR_1 (0x00000002U)
3198#define GPIO_BRR_BR_2 (0x00000004U)
3199#define GPIO_BRR_BR_3 (0x00000008U)
3200#define GPIO_BRR_BR_4 (0x00000010U)
3201#define GPIO_BRR_BR_5 (0x00000020U)
3202#define GPIO_BRR_BR_6 (0x00000040U)
3203#define GPIO_BRR_BR_7 (0x00000080U)
3204#define GPIO_BRR_BR_8 (0x00000100U)
3205#define GPIO_BRR_BR_9 (0x00000200U)
3206#define GPIO_BRR_BR_10 (0x00000400U)
3207#define GPIO_BRR_BR_11 (0x00000800U)
3208#define GPIO_BRR_BR_12 (0x00001000U)
3209#define GPIO_BRR_BR_13 (0x00002000U)
3210#define GPIO_BRR_BR_14 (0x00004000U)
3211#define GPIO_BRR_BR_15 (0x00008000U)
3212
3213/******************************************************************************/
3214/* */
3215/* Inter-integrated Circuit Interface (I2C) */
3216/* */
3217/******************************************************************************/
3218
3219/******************* Bit definition for I2C_CR1 register *******************/
3220#define I2C_CR1_PE_Pos (0U)
3221#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
3222#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
3223#define I2C_CR1_TXIE_Pos (1U)
3224#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
3225#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
3226#define I2C_CR1_RXIE_Pos (2U)
3227#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
3228#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
3229#define I2C_CR1_ADDRIE_Pos (3U)
3230#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
3231#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
3232#define I2C_CR1_NACKIE_Pos (4U)
3233#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
3234#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
3235#define I2C_CR1_STOPIE_Pos (5U)
3236#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
3237#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
3238#define I2C_CR1_TCIE_Pos (6U)
3239#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
3240#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
3241#define I2C_CR1_ERRIE_Pos (7U)
3242#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
3243#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
3244#define I2C_CR1_DNF_Pos (8U)
3245#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
3246#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
3247#define I2C_CR1_ANFOFF_Pos (12U)
3248#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
3249#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
3250#define I2C_CR1_TXDMAEN_Pos (14U)
3251#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
3252#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
3253#define I2C_CR1_RXDMAEN_Pos (15U)
3254#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
3255#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
3256#define I2C_CR1_SBC_Pos (16U)
3257#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
3258#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
3259#define I2C_CR1_NOSTRETCH_Pos (17U)
3260#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
3261#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
3262#define I2C_CR1_WUPEN_Pos (18U)
3263#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
3264#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
3265#define I2C_CR1_GCEN_Pos (19U)
3266#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
3267#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
3268#define I2C_CR1_SMBHEN_Pos (20U)
3269#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
3270#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
3271#define I2C_CR1_SMBDEN_Pos (21U)
3272#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
3273#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
3274#define I2C_CR1_ALERTEN_Pos (22U)
3275#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
3276#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
3277#define I2C_CR1_PECEN_Pos (23U)
3278#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
3279#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
3280
3281/****************** Bit definition for I2C_CR2 register ********************/
3282#define I2C_CR2_SADD_Pos (0U)
3283#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
3284#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
3285#define I2C_CR2_RD_WRN_Pos (10U)
3286#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
3287#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
3288#define I2C_CR2_ADD10_Pos (11U)
3289#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
3290#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
3291#define I2C_CR2_HEAD10R_Pos (12U)
3292#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
3293#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
3294#define I2C_CR2_START_Pos (13U)
3295#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
3296#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
3297#define I2C_CR2_STOP_Pos (14U)
3298#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
3299#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
3300#define I2C_CR2_NACK_Pos (15U)
3301#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
3302#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
3303#define I2C_CR2_NBYTES_Pos (16U)
3304#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
3305#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
3306#define I2C_CR2_RELOAD_Pos (24U)
3307#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
3308#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
3309#define I2C_CR2_AUTOEND_Pos (25U)
3310#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
3311#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
3312#define I2C_CR2_PECBYTE_Pos (26U)
3313#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
3314#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
3315
3316/******************* Bit definition for I2C_OAR1 register ******************/
3317#define I2C_OAR1_OA1_Pos (0U)
3318#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
3319#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
3320#define I2C_OAR1_OA1MODE_Pos (10U)
3321#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
3322#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
3323#define I2C_OAR1_OA1EN_Pos (15U)
3324#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
3325#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
3326
3327/******************* Bit definition for I2C_OAR2 register ******************/
3328#define I2C_OAR2_OA2_Pos (1U)
3329#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
3330#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
3331#define I2C_OAR2_OA2MSK_Pos (8U)
3332#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
3333#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
3334#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
3335#define I2C_OAR2_OA2MASK01_Pos (8U)
3336#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
3337#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
3338#define I2C_OAR2_OA2MASK02_Pos (9U)
3339#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
3340#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
3341#define I2C_OAR2_OA2MASK03_Pos (8U)
3342#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
3343#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
3344#define I2C_OAR2_OA2MASK04_Pos (10U)
3345#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
3346#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
3347#define I2C_OAR2_OA2MASK05_Pos (8U)
3348#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
3349#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
3350#define I2C_OAR2_OA2MASK06_Pos (9U)
3351#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
3352#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
3353#define I2C_OAR2_OA2MASK07_Pos (8U)
3354#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
3355#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
3356#define I2C_OAR2_OA2EN_Pos (15U)
3357#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
3358#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
3359
3360/******************* Bit definition for I2C_TIMINGR register *******************/
3361#define I2C_TIMINGR_SCLL_Pos (0U)
3362#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
3363#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
3364#define I2C_TIMINGR_SCLH_Pos (8U)
3365#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
3366#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
3367#define I2C_TIMINGR_SDADEL_Pos (16U)
3368#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
3369#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
3370#define I2C_TIMINGR_SCLDEL_Pos (20U)
3371#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
3372#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
3373#define I2C_TIMINGR_PRESC_Pos (28U)
3374#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
3375#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
3376
3377/******************* Bit definition for I2C_TIMEOUTR register *******************/
3378#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
3379#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
3380#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
3381#define I2C_TIMEOUTR_TIDLE_Pos (12U)
3382#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
3383#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
3384#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
3385#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
3386#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
3387#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
3388#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
3389#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
3390#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
3391#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
3392#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
3393
3394/****************** Bit definition for I2C_ISR register *********************/
3395#define I2C_ISR_TXE_Pos (0U)
3396#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
3397#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
3398#define I2C_ISR_TXIS_Pos (1U)
3399#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
3400#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
3401#define I2C_ISR_RXNE_Pos (2U)
3402#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
3403#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
3404#define I2C_ISR_ADDR_Pos (3U)
3405#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
3406#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
3407#define I2C_ISR_NACKF_Pos (4U)
3408#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
3409#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
3410#define I2C_ISR_STOPF_Pos (5U)
3411#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
3412#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
3413#define I2C_ISR_TC_Pos (6U)
3414#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
3415#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
3416#define I2C_ISR_TCR_Pos (7U)
3417#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
3418#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
3419#define I2C_ISR_BERR_Pos (8U)
3420#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
3421#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
3422#define I2C_ISR_ARLO_Pos (9U)
3423#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
3424#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
3425#define I2C_ISR_OVR_Pos (10U)
3426#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
3427#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
3428#define I2C_ISR_PECERR_Pos (11U)
3429#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
3430#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
3431#define I2C_ISR_TIMEOUT_Pos (12U)
3432#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
3433#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
3434#define I2C_ISR_ALERT_Pos (13U)
3435#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
3436#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
3437#define I2C_ISR_BUSY_Pos (15U)
3438#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
3439#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
3440#define I2C_ISR_DIR_Pos (16U)
3441#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
3442#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
3443#define I2C_ISR_ADDCODE_Pos (17U)
3444#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
3445#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
3446
3447/****************** Bit definition for I2C_ICR register *********************/
3448#define I2C_ICR_ADDRCF_Pos (3U)
3449#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
3450#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
3451#define I2C_ICR_NACKCF_Pos (4U)
3452#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
3453#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
3454#define I2C_ICR_STOPCF_Pos (5U)
3455#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
3456#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
3457#define I2C_ICR_BERRCF_Pos (8U)
3458#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
3459#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
3460#define I2C_ICR_ARLOCF_Pos (9U)
3461#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
3462#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
3463#define I2C_ICR_OVRCF_Pos (10U)
3464#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
3465#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
3466#define I2C_ICR_PECCF_Pos (11U)
3467#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
3468#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
3469#define I2C_ICR_TIMOUTCF_Pos (12U)
3470#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
3471#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
3472#define I2C_ICR_ALERTCF_Pos (13U)
3473#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
3474#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
3475
3476/****************** Bit definition for I2C_PECR register *********************/
3477#define I2C_PECR_PEC_Pos (0U)
3478#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
3479#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
3480
3481/****************** Bit definition for I2C_RXDR register *********************/
3482#define I2C_RXDR_RXDATA_Pos (0U)
3483#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
3484#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
3485
3486/****************** Bit definition for I2C_TXDR register *********************/
3487#define I2C_TXDR_TXDATA_Pos (0U)
3488#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
3489#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
3490
3491/******************************************************************************/
3492/* */
3493/* Independent WATCHDOG (IWDG) */
3494/* */
3495/******************************************************************************/
3496/******************* Bit definition for IWDG_KR register ********************/
3497#define IWDG_KR_KEY_Pos (0U)
3498#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
3499#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
3500
3501/******************* Bit definition for IWDG_PR register ********************/
3502#define IWDG_PR_PR_Pos (0U)
3503#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
3504#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
3505#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
3506#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
3507#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
3508
3509/******************* Bit definition for IWDG_RLR register *******************/
3510#define IWDG_RLR_RL_Pos (0U)
3511#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
3512#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
3513
3514/******************* Bit definition for IWDG_SR register ********************/
3515#define IWDG_SR_PVU_Pos (0U)
3516#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
3517#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
3518#define IWDG_SR_RVU_Pos (1U)
3519#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
3520#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
3521#define IWDG_SR_WVU_Pos (2U)
3522#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
3523#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
3524
3525/******************* Bit definition for IWDG_KR register ********************/
3526#define IWDG_WINR_WIN_Pos (0U)
3527#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
3528#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
3529
3530/******************************************************************************/
3531/* */
3532/* LCD Controller (LCD) */
3533/* */
3534/******************************************************************************/
3535
3536/******************* Bit definition for LCD_CR register *********************/
3537#define LCD_CR_LCDEN_Pos (0U)
3538#define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */
3539#define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */
3540#define LCD_CR_VSEL_Pos (1U)
3541#define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */
3542#define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */
3543
3544#define LCD_CR_DUTY_Pos (2U)
3545#define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */
3546#define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */
3547#define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */
3548#define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */
3549#define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */
3550
3551#define LCD_CR_BIAS_Pos (5U)
3552#define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */
3553#define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */
3554#define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */
3555#define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */
3556
3557#define LCD_CR_MUX_SEG_Pos (7U)
3558#define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */
3559#define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */
3560
3561#define LCD_CR_BUFEN_Pos (8U)
3562#define LCD_CR_BUFEN_Msk (0x1U << LCD_CR_BUFEN_Pos) /*!< 0x00000100 */
3563#define LCD_CR_BUFEN LCD_CR_BUFEN_Msk /*!< Voltage output buffer enable Bit */
3564
3565/******************* Bit definition for LCD_FCR register ********************/
3566#define LCD_FCR_HD_Pos (0U)
3567#define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */
3568#define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */
3569#define LCD_FCR_SOFIE_Pos (1U)
3570#define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */
3571#define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */
3572#define LCD_FCR_UDDIE_Pos (3U)
3573#define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */
3574#define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */
3575
3576#define LCD_FCR_PON_Pos (4U)
3577#define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */
3578#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
3579#define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */
3580#define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */
3581#define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */
3582
3583#define LCD_FCR_DEAD_Pos