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1/**
2 ******************************************************************************
3 * @file stm32l432xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32L432xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral�s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42/** @addtogroup CMSIS_Device
43 * @{
44 */
45
46/** @addtogroup stm32l432xx
47 * @{
48 */
49
50#ifndef __STM32L432xx_H
51#define __STM32L432xx_H
52
53#ifdef __cplusplus
54 extern "C" {
55#endif /* __cplusplus */
56
57/** @addtogroup Configuration_section_for_CMSIS
58 * @{
59 */
60
61/**
62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63 */
64#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
65#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
66#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
67#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
68#define __FPU_PRESENT 1 /*!< FPU present */
69
70/**
71 * @}
72 */
73
74/** @addtogroup Peripheral_interrupt_number_definition
75 * @{
76 */
77
78/**
79 * @brief STM32L4XX Interrupt Number Definition, according to the selected device
80 * in @ref Library_configuration_section
81 */
82typedef enum
83{
84/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
86 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
87 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
88 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
89 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
90 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
91 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
92 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
93 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
94/****** STM32 specific Interrupt Numbers **********************************************************************/
95 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
96 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
97 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
98 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
99 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
100 RCC_IRQn = 5, /*!< RCC global Interrupt */
101 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
102 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
103 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
104 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
105 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
106 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
107 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
108 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
109 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
110 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
111 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
112 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
113 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
114 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
115 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
116 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
117 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
118 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
119 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
120 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
121 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
122 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
123 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
124 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
125 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
126 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
127 USART1_IRQn = 37, /*!< USART1 global Interrupt */
128 USART2_IRQn = 38, /*!< USART2 global Interrupt */
129 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
130 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
131 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
132 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
133 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
134 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
135 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
136 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
137 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
138 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
139 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
140 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
141 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
142 USB_IRQn = 67, /*!< USB event Interrupt */
143 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
144 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
145 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
146 QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
147 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
148 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
149 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
150 SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */
151 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
152 RNG_IRQn = 80, /*!< RNG global interrupt */
153 FPU_IRQn = 81, /*!< FPU global interrupt */
154 CRS_IRQn = 82 /*!< CRS global interrupt */
155} IRQn_Type;
156
157/**
158 * @}
159 */
160
161#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
162#include "system_stm32l4xx.h"
163#include <stdint.h>
164
165/** @addtogroup Peripheral_registers_structures
166 * @{
167 */
168
169/**
170 * @brief Analog to Digital Converter
171 */
172
173typedef struct
174{
175 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
176 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
177 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
178 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
179 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
180 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
181 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
182 uint32_t RESERVED1; /*!< Reserved, 0x1C */
183 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
184 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
185 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
186 uint32_t RESERVED2; /*!< Reserved, 0x2C */
187 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
188 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
189 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
190 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
191 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
192 uint32_t RESERVED3; /*!< Reserved, 0x44 */
193 uint32_t RESERVED4; /*!< Reserved, 0x48 */
194 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
195 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
196 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
197 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
198 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
199 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
200 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
201 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
202 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
203 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
204 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
205 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
206 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
207 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
208 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
209 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
210 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
211 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
212
213} ADC_TypeDef;
214
215typedef struct
216{
217 uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */
218 uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
219 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
220 uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */
221} ADC_Common_TypeDef;
222
223
224/**
225 * @brief Controller Area Network TxMailBox
226 */
227
228typedef struct
229{
230 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
231 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
232 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
233 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
234} CAN_TxMailBox_TypeDef;
235
236/**
237 * @brief Controller Area Network FIFOMailBox
238 */
239
240typedef struct
241{
242 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
243 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
244 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
245 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
246} CAN_FIFOMailBox_TypeDef;
247
248/**
249 * @brief Controller Area Network FilterRegister
250 */
251
252typedef struct
253{
254 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
255 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
256} CAN_FilterRegister_TypeDef;
257
258/**
259 * @brief Controller Area Network
260 */
261
262typedef struct
263{
264 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
265 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
266 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
267 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
268 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
269 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
270 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
271 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
272 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
273 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
274 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
275 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
276 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
277 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
278 uint32_t RESERVED2; /*!< Reserved, 0x208 */
279 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
280 uint32_t RESERVED3; /*!< Reserved, 0x210 */
281 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
282 uint32_t RESERVED4; /*!< Reserved, 0x218 */
283 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
284 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
285 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
286} CAN_TypeDef;
287
288
289/**
290 * @brief Comparator
291 */
292
293typedef struct
294{
295 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
296} COMP_TypeDef;
297
298typedef struct
299{
300 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
301} COMP_Common_TypeDef;
302
303/**
304 * @brief CRC calculation unit
305 */
306
307typedef struct
308{
309 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
310 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
311 uint8_t RESERVED0; /*!< Reserved, 0x05 */
312 uint16_t RESERVED1; /*!< Reserved, 0x06 */
313 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
314 uint32_t RESERVED2; /*!< Reserved, 0x0C */
315 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
316 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
317} CRC_TypeDef;
318
319/**
320 * @brief Clock Recovery System
321 */
322typedef struct
323{
324__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
325__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
326__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
327__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
328} CRS_TypeDef;
329
330/**
331 * @brief Digital to Analog Converter
332 */
333
334typedef struct
335{
336 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
337 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
338 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
339 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
340 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
341 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
342 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
343 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
344 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
345 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
346 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
347 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
348 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
349 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
350 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
351 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
352 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
353 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
354 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
355 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
356} DAC_TypeDef;
357
358
359/**
360 * @brief Debug MCU
361 */
362
363typedef struct
364{
365 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
366 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
367 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
368 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
369 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
370} DBGMCU_TypeDef;
371
372
373/**
374 * @brief DMA Controller
375 */
376
377typedef struct
378{
379 __IO uint32_t CCR; /*!< DMA channel x configuration register */
380 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
381 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
382 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
383} DMA_Channel_TypeDef;
384
385typedef struct
386{
387 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
388 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
389} DMA_TypeDef;
390
391typedef struct
392{
393 __IO uint32_t CSELR; /*!< DMA channel selection register */
394} DMA_Request_TypeDef;
395
396/* Legacy define */
397#define DMA_request_TypeDef DMA_Request_TypeDef
398
399
400/**
401 * @brief External Interrupt/Event Controller
402 */
403
404typedef struct
405{
406 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
407 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
408 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
409 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
410 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
411 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
412 uint32_t RESERVED1; /*!< Reserved, 0x18 */
413 uint32_t RESERVED2; /*!< Reserved, 0x1C */
414 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
415 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
416 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
417 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
418 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
419 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
420} EXTI_TypeDef;
421
422
423/**
424 * @brief Firewall
425 */
426
427typedef struct
428{
429 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
430 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
431 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
432 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
433 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
434 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
435 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
436 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
437 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
438} FIREWALL_TypeDef;
439
440
441/**
442 * @brief FLASH Registers
443 */
444
445typedef struct
446{
447 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
448 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
449 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
450 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
451 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
452 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
453 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
454 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
455 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
456 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
457 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
458 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
459 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
460} FLASH_TypeDef;
461
462
463
464/**
465 * @brief General Purpose I/O
466 */
467
468typedef struct
469{
470 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
471 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
472 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
473 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
474 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
475 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
476 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
477 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
478 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
479 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
480
481} GPIO_TypeDef;
482
483
484/**
485 * @brief Inter-integrated Circuit Interface
486 */
487
488typedef struct
489{
490 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
491 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
492 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
493 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
494 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
495 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
496 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
497 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
498 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
499 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
500 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
501} I2C_TypeDef;
502
503/**
504 * @brief Independent WATCHDOG
505 */
506
507typedef struct
508{
509 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
510 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
511 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
512 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
513 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
514} IWDG_TypeDef;
515
516/**
517 * @brief LPTIMER
518 */
519typedef struct
520{
521 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
522 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
523 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
524 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
525 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
526 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
527 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
528 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
529 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
530} LPTIM_TypeDef;
531
532/**
533 * @brief Operational Amplifier (OPAMP)
534 */
535
536typedef struct
537{
538 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
539 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
540 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
541} OPAMP_TypeDef;
542
543typedef struct
544{
545 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
546} OPAMP_Common_TypeDef;
547
548/**
549 * @brief Power Control
550 */
551
552typedef struct
553{
554 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
555 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
556 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
557 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
558 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
559 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
560 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
561 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
562 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
563 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
564 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
565 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
566 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
567 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
568 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
569 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
570 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
571 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
572 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */
573 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */
574 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */
575 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */
576 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
577 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
578} PWR_TypeDef;
579
580
581/**
582 * @brief QUAD Serial Peripheral Interface
583 */
584
585typedef struct
586{
587 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
588 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
589 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
590 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
591 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
592 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
593 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
594 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
595 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
596 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
597 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
598 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
599 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
600} QUADSPI_TypeDef;
601
602
603/**
604 * @brief Reset and Clock Control
605 */
606
607typedef struct
608{
609 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
610 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
611 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
612 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
613 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
614 uint32_t RESERVED; /*!< Reserved, Address offset: 0x14 */
615 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
616 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
617 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
618 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
619 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
620 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
621 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
622 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
623 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
624 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
625 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
626 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
627 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
628 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
629 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
630 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
631 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
632 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
633 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
634 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
635 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
636 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
637 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
638 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
639 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
640 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
641 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
642 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
643 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
644 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
645 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
646 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
647 __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
648} RCC_TypeDef;
649
650/**
651 * @brief Real-Time Clock
652 */
653
654typedef struct
655{
656 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
657 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
658 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
659 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
660 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
661 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
662 uint32_t reserved; /*!< Reserved */
663 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
664 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
665 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
666 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
667 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
668 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
669 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
670 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
671 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
672 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
673 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
674 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
675 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
676 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
677 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
678 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
679 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
680 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
681 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
682 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
683 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
684 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
685 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
686 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
687 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
688 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
689 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
690 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
691 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
692 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
693 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
694 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
695 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
696 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
697 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
698 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
699 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
700 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
701 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
702 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
703 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
704 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
705 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
706 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
707 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
708} RTC_TypeDef;
709
710
711/**
712 * @brief Serial Audio Interface
713 */
714
715typedef struct
716{
717 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
718} SAI_TypeDef;
719
720typedef struct
721{
722 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
723 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
724 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
725 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
726 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
727 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
728 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
729 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
730} SAI_Block_TypeDef;
731
732
733/**
734 * @brief Serial Peripheral Interface
735 */
736
737typedef struct
738{
739 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
740 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
741 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
742 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
743 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
744 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
745 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
746} SPI_TypeDef;
747
748
749/**
750 * @brief Single Wire Protocol Master Interface SPWMI
751 */
752
753typedef struct
754{
755 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
756 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
757 uint32_t RESERVED1; /*!< Reserved, 0x08 */
758 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
759 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
760 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
761 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
762 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
763 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
764 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
765} SWPMI_TypeDef;
766
767
768/**
769 * @brief System configuration controller
770 */
771
772typedef struct
773{
774 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
775 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
776 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
777 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
778 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
779 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
780 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
781} SYSCFG_TypeDef;
782
783
784/**
785 * @brief TIM
786 */
787
788typedef struct
789{
790 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
791 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
792 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
793 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
794 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
795 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
796 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
797 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
798 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
799 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
800 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
801 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
802 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
803 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
804 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
805 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
806 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
807 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
808 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
809 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
810 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
811 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
812 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
813 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
814 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
815 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
816} TIM_TypeDef;
817
818
819/**
820 * @brief Touch Sensing Controller (TSC)
821 */
822
823typedef struct
824{
825 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
826 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
827 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
828 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
829 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
830 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
831 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
832 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
833 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
834 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
835 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
836 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
837 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
838 __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */
839} TSC_TypeDef;
840
841/**
842 * @brief Universal Synchronous Asynchronous Receiver Transmitter
843 */
844
845typedef struct
846{
847 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
848 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
849 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
850 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
851 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
852 uint16_t RESERVED2; /*!< Reserved, 0x12 */
853 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
854 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
855 uint16_t RESERVED3; /*!< Reserved, 0x1A */
856 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
857 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
858 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
859 uint16_t RESERVED4; /*!< Reserved, 0x26 */
860 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
861 uint16_t RESERVED5; /*!< Reserved, 0x2A */
862} USART_TypeDef;
863
864/**
865 * @brief Universal Serial Bus Full Speed Device
866 */
867
868typedef struct
869{
870 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
871 __IO uint16_t RESERVED0; /*!< Reserved */
872 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
873 __IO uint16_t RESERVED1; /*!< Reserved */
874 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
875 __IO uint16_t RESERVED2; /*!< Reserved */
876 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
877 __IO uint16_t RESERVED3; /*!< Reserved */
878 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
879 __IO uint16_t RESERVED4; /*!< Reserved */
880 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
881 __IO uint16_t RESERVED5; /*!< Reserved */
882 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
883 __IO uint16_t RESERVED6; /*!< Reserved */
884 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
885 __IO uint16_t RESERVED7[17]; /*!< Reserved */
886 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
887 __IO uint16_t RESERVED8; /*!< Reserved */
888 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
889 __IO uint16_t RESERVED9; /*!< Reserved */
890 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
891 __IO uint16_t RESERVEDA; /*!< Reserved */
892 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
893 __IO uint16_t RESERVEDB; /*!< Reserved */
894 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
895 __IO uint16_t RESERVEDC; /*!< Reserved */
896 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
897 __IO uint16_t RESERVEDD; /*!< Reserved */
898 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
899 __IO uint16_t RESERVEDE; /*!< Reserved */
900} USB_TypeDef;
901
902
903/**
904 * @brief Window WATCHDOG
905 */
906
907typedef struct
908{
909 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
910 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
911 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
912} WWDG_TypeDef;
913
914/**
915 * @brief RNG
916 */
917
918typedef struct
919{
920 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
921 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
922 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
923} RNG_TypeDef;
924
925/**
926 * @}
927 */
928
929/** @addtogroup Peripheral_memory_map
930 * @{
931 */
932#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */
933#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */
934#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */
935#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
936#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */
937
938#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
939#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
940#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
941
942/* Legacy defines */
943#define SRAM_BASE SRAM1_BASE
944#define SRAM_BB_BASE SRAM1_BB_BASE
945
946#define SRAM1_SIZE_MAX ((uint32_t)0x0000C000U) /*!< maximum SRAM1 size (up to 48 KBytes) */
947#define SRAM2_SIZE ((uint32_t)0x00004000U) /*!< SRAM2 size (16 KBytes) */
948
949/*!< Peripheral memory map */
950#define APB1PERIPH_BASE PERIPH_BASE
951#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
952#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
953#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
954
955
956/*!< APB1 peripherals */
957#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
958#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
959#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
960#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
961#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
962#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
963#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
964#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
965#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
966#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
967#define CRS_BASE (APB1PERIPH_BASE + 0x6000U)
968#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
969#define USB_BASE (APB1PERIPH_BASE + 0x6800U) /*!< USB_IP Peripheral Registers base address */
970#define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00U) /*!< USB_IP Packet Memory Area base address */
971#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
972#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
973#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
974#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
975#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
976#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
977#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
978#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U)
979#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
980
981
982/*!< APB2 peripherals */
983#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
984#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
985#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
986#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
987#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
988#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
989#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
990#define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
991#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
992#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
993#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
994#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
995#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
996
997/*!< AHB1 peripherals */
998#define DMA1_BASE (AHB1PERIPH_BASE)
999#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
1000#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
1001#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
1002#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1003#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
1004
1005
1006#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
1007#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
1008#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
1009#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
1010#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
1011#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
1012#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
1013#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U)
1014
1015
1016#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
1017#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
1018#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
1019#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
1020#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
1021#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
1022#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
1023#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U)
1024
1025
1026/*!< AHB2 peripherals */
1027#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
1028#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
1029#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
1030#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
1031
1032
1033#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
1034#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
1035
1036
1037#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
1038
1039
1040
1041/* Debug MCU registers base address */
1042#define DBGMCU_BASE ((uint32_t)0xE0042000U)
1043
1044
1045#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
1046#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
1047#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
1048/**
1049 * @}
1050 */
1051
1052/** @addtogroup Peripheral_declaration
1053 * @{
1054 */
1055#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1056#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1057#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1058#define RTC ((RTC_TypeDef *) RTC_BASE)
1059#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1060#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1061#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1062#define USART2 ((USART_TypeDef *) USART2_BASE)
1063#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1064#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1065#define CRS ((CRS_TypeDef *) CRS_BASE)
1066#define CAN ((CAN_TypeDef *) CAN1_BASE)
1067#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1068#define USB ((USB_TypeDef *) USB_BASE)
1069#define PWR ((PWR_TypeDef *) PWR_BASE)
1070#define DAC ((DAC_TypeDef *) DAC1_BASE)
1071#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1072#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1073#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1074#define OPAMP1_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1075#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1076#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1077#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
1078#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
1079
1080#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1081#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1082#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1083#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
1084#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1085#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
1086#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1087#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1088#define USART1 ((USART_TypeDef *) USART1_BASE)
1089#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1090#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1091#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1092#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1093#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1094#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1095#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1096#define RCC ((RCC_TypeDef *) RCC_BASE)
1097#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1098#define CRC ((CRC_TypeDef *) CRC_BASE)
1099#define TSC ((TSC_TypeDef *) TSC_BASE)
1100
1101#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1102#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1103#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1104#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1105#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1106#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
1107#define RNG ((RNG_TypeDef *) RNG_BASE)
1108
1109
1110#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1111#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1112#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1113#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1114#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1115#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1116#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1117#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
1118
1119
1120#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1121#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1122#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1123#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1124#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1125#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1126#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1127#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
1128
1129
1130
1131#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1132
1133#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1134
1135/**
1136 * @}
1137 */
1138
1139/** @addtogroup Exported_constants
1140 * @{
1141 */
1142
1143/** @addtogroup Peripheral_Registers_Bits_Definition
1144 * @{
1145 */
1146
1147/******************************************************************************/
1148/* Peripheral Registers_Bits_Definition */
1149/******************************************************************************/
1150
1151/******************************************************************************/
1152/* */
1153/* Analog to Digital Converter */
1154/* */
1155/******************************************************************************/
1156
1157/*
1158 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
1159 */
1160/* Note: No specific macro feature on this device */
1161
1162/******************** Bit definition for ADC_ISR register *******************/
1163#define ADC_ISR_ADRDY_Pos (0U)
1164#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
1165#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
1166#define ADC_ISR_EOSMP_Pos (1U)
1167#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
1168#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
1169#define ADC_ISR_EOC_Pos (2U)
1170#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
1171#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
1172#define ADC_ISR_EOS_Pos (3U)
1173#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
1174#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
1175#define ADC_ISR_OVR_Pos (4U)
1176#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
1177#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
1178#define ADC_ISR_JEOC_Pos (5U)
1179#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
1180#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
1181#define ADC_ISR_JEOS_Pos (6U)
1182#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
1183#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
1184#define ADC_ISR_AWD1_Pos (7U)
1185#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
1186#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
1187#define ADC_ISR_AWD2_Pos (8U)
1188#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
1189#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
1190#define ADC_ISR_AWD3_Pos (9U)
1191#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
1192#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
1193#define ADC_ISR_JQOVF_Pos (10U)
1194#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
1195#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
1196
1197/******************** Bit definition for ADC_IER register *******************/
1198#define ADC_IER_ADRDYIE_Pos (0U)
1199#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
1200#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
1201#define ADC_IER_EOSMPIE_Pos (1U)
1202#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
1203#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
1204#define ADC_IER_EOCIE_Pos (2U)
1205#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
1206#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
1207#define ADC_IER_EOSIE_Pos (3U)
1208#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
1209#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
1210#define ADC_IER_OVRIE_Pos (4U)
1211#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
1212#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
1213#define ADC_IER_JEOCIE_Pos (5U)
1214#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
1215#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
1216#define ADC_IER_JEOSIE_Pos (6U)
1217#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
1218#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
1219#define ADC_IER_AWD1IE_Pos (7U)
1220#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
1221#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
1222#define ADC_IER_AWD2IE_Pos (8U)
1223#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
1224#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
1225#define ADC_IER_AWD3IE_Pos (9U)
1226#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
1227#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
1228#define ADC_IER_JQOVFIE_Pos (10U)
1229#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
1230#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
1231
1232/* Legacy defines */
1233#define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
1234#define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
1235#define ADC_IER_EOC (ADC_IER_EOCIE)
1236#define ADC_IER_EOS (ADC_IER_EOSIE)
1237#define ADC_IER_OVR (ADC_IER_OVRIE)
1238#define ADC_IER_JEOC (ADC_IER_JEOCIE)
1239#define ADC_IER_JEOS (ADC_IER_JEOSIE)
1240#define ADC_IER_AWD1 (ADC_IER_AWD1IE)
1241#define ADC_IER_AWD2 (ADC_IER_AWD2IE)
1242#define ADC_IER_AWD3 (ADC_IER_AWD3IE)
1243#define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
1244
1245/******************** Bit definition for ADC_CR register ********************/
1246#define ADC_CR_ADEN_Pos (0U)
1247#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
1248#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
1249#define ADC_CR_ADDIS_Pos (1U)
1250#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
1251#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
1252#define ADC_CR_ADSTART_Pos (2U)
1253#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
1254#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
1255#define ADC_CR_JADSTART_Pos (3U)
1256#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
1257#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
1258#define ADC_CR_ADSTP_Pos (4U)
1259#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
1260#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
1261#define ADC_CR_JADSTP_Pos (5U)
1262#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
1263#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
1264#define ADC_CR_ADVREGEN_Pos (28U)
1265#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
1266#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
1267#define ADC_CR_DEEPPWD_Pos (29U)
1268#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
1269#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
1270#define ADC_CR_ADCALDIF_Pos (30U)
1271#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
1272#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
1273#define ADC_CR_ADCAL_Pos (31U)
1274#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
1275#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
1276
1277/******************** Bit definition for ADC_CFGR register ******************/
1278#define ADC_CFGR_DMAEN_Pos (0U)
1279#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
1280#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
1281#define ADC_CFGR_DMACFG_Pos (1U)
1282#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
1283#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
1284
1285#define ADC_CFGR_RES_Pos (3U)
1286#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
1287#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
1288#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
1289#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
1290
1291#define ADC_CFGR_ALIGN_Pos (5U)
1292#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
1293#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1294
1295#define ADC_CFGR_EXTSEL_Pos (6U)
1296#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
1297#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
1298#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
1299#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
1300#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
1301#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
1302
1303#define ADC_CFGR_EXTEN_Pos (10U)
1304#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
1305#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
1306#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
1307#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
1308
1309#define ADC_CFGR_OVRMOD_Pos (12U)
1310#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
1311#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
1312#define ADC_CFGR_CONT_Pos (13U)
1313#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
1314#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
1315#define ADC_CFGR_AUTDLY_Pos (14U)
1316#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
1317#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
1318
1319#define ADC_CFGR_DISCEN_Pos (16U)
1320#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
1321#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
1322
1323#define ADC_CFGR_DISCNUM_Pos (17U)
1324#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
1325#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
1326#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
1327#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
1328#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
1329
1330#define ADC_CFGR_JDISCEN_Pos (20U)
1331#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
1332#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
1333#define ADC_CFGR_JQM_Pos (21U)
1334#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
1335#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
1336#define ADC_CFGR_AWD1SGL_Pos (22U)
1337#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
1338#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1339#define ADC_CFGR_AWD1EN_Pos (23U)
1340#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
1341#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1342#define ADC_CFGR_JAWD1EN_Pos (24U)
1343#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
1344#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1345#define ADC_CFGR_JAUTO_Pos (25U)
1346#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
1347#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
1348
1349#define ADC_CFGR_AWD1CH_Pos (26U)
1350#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
1351#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
1352#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
1353#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
1354#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
1355#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
1356#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
1357
1358#define ADC_CFGR_JQDIS_Pos (31U)
1359#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
1360#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
1361
1362/******************** Bit definition for ADC_CFGR2 register *****************/
1363#define ADC_CFGR2_ROVSE_Pos (0U)
1364#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
1365#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
1366#define ADC_CFGR2_JOVSE_Pos (1U)
1367#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
1368#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
1369
1370#define ADC_CFGR2_OVSR_Pos (2U)
1371#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
1372#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
1373#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
1374#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
1375#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
1376
1377#define ADC_CFGR2_OVSS_Pos (5U)
1378#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
1379#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
1380#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
1381#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
1382#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
1383#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
1384
1385#define ADC_CFGR2_TROVS_Pos (9U)
1386#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
1387#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1388#define ADC_CFGR2_ROVSM_Pos (10U)
1389#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
1390#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1391
1392/******************** Bit definition for ADC_SMPR1 register *****************/
1393#define ADC_SMPR1_SMP0_Pos (0U)
1394#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
1395#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
1396#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
1397#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
1398#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
1399
1400#define ADC_SMPR1_SMP1_Pos (3U)
1401#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
1402#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
1403#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
1404#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
1405#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
1406
1407#define ADC_SMPR1_SMP2_Pos (6U)
1408#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
1409#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
1410#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
1411#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
1412#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
1413
1414#define ADC_SMPR1_SMP3_Pos (9U)
1415#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
1416#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
1417#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
1418#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
1419#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
1420
1421#define ADC_SMPR1_SMP4_Pos (12U)
1422#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
1423#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
1424#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
1425#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
1426#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
1427
1428#define ADC_SMPR1_SMP5_Pos (15U)
1429#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
1430#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
1431#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
1432#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
1433#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
1434
1435#define ADC_SMPR1_SMP6_Pos (18U)
1436#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
1437#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
1438#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
1439#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
1440#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
1441
1442#define ADC_SMPR1_SMP7_Pos (21U)
1443#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
1444#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
1445#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
1446#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
1447#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
1448
1449#define ADC_SMPR1_SMP8_Pos (24U)
1450#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
1451#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
1452#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
1453#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
1454#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
1455
1456#define ADC_SMPR1_SMP9_Pos (27U)
1457#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
1458#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
1459#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
1460#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
1461#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
1462
1463/******************** Bit definition for ADC_SMPR2 register *****************/
1464#define ADC_SMPR2_SMP10_Pos (0U)
1465#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
1466#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
1467#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
1468#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
1469#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
1470
1471#define ADC_SMPR2_SMP11_Pos (3U)
1472#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
1473#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
1474#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
1475#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
1476#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
1477
1478#define ADC_SMPR2_SMP12_Pos (6U)
1479#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
1480#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
1481#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
1482#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
1483#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
1484
1485#define ADC_SMPR2_SMP13_Pos (9U)
1486#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
1487#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
1488#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
1489#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
1490#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
1491
1492#define ADC_SMPR2_SMP14_Pos (12U)
1493#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
1494#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
1495#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
1496#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
1497#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
1498
1499#define ADC_SMPR2_SMP15_Pos (15U)
1500#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
1501#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
1502#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
1503#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
1504#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
1505
1506#define ADC_SMPR2_SMP16_Pos (18U)
1507#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
1508#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
1509#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
1510#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
1511#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
1512
1513#define ADC_SMPR2_SMP17_Pos (21U)
1514#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
1515#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
1516#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
1517#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
1518#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
1519
1520#define ADC_SMPR2_SMP18_Pos (24U)
1521#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
1522#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
1523#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
1524#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
1525#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
1526
1527/******************** Bit definition for ADC_TR1 register *******************/
1528#define ADC_TR1_LT1_Pos (0U)
1529#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
1530#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
1531#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
1532#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
1533#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
1534#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
1535#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
1536#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
1537#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
1538#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
1539#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
1540#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
1541#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
1542#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
1543
1544#define ADC_TR1_HT1_Pos (16U)
1545#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
1546#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
1547#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
1548#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
1549#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
1550#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
1551#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
1552#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
1553#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
1554#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
1555#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
1556#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
1557#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
1558#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
1559
1560/******************** Bit definition for ADC_TR2 register *******************/
1561#define ADC_TR2_LT2_Pos (0U)
1562#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
1563#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
1564#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
1565#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
1566#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
1567#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
1568#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
1569#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
1570#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
1571#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
1572
1573#define ADC_TR2_HT2_Pos (16U)
1574#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
1575#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
1576#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
1577#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
1578#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
1579#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
1580#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
1581#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
1582#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
1583#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
1584
1585/******************** Bit definition for ADC_TR3 register *******************/
1586#define ADC_TR3_LT3_Pos (0U)
1587#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
1588#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
1589#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
1590#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
1591#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
1592#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
1593#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
1594#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
1595#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
1596#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
1597
1598#define ADC_TR3_HT3_Pos (16U)
1599#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
1600#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
1601#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
1602#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
1603#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
1604#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
1605#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
1606#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
1607#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
1608#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
1609
1610/******************** Bit definition for ADC_SQR1 register ******************/
1611#define ADC_SQR1_L_Pos (0U)
1612#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
1613#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
1614#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
1615#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
1616#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
1617#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
1618
1619#define ADC_SQR1_SQ1_Pos (6U)
1620#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
1621#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
1622#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
1623#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
1624#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
1625#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
1626#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
1627
1628#define ADC_SQR1_SQ2_Pos (12U)
1629#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
1630#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
1631#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
1632#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
1633#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
1634#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
1635#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
1636
1637#define ADC_SQR1_SQ3_Pos (18U)
1638#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
1639#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
1640#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
1641#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
1642#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
1643#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
1644#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
1645
1646#define ADC_SQR1_SQ4_Pos (24U)
1647#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
1648#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
1649#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
1650#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
1651#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
1652#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
1653#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
1654
1655/******************** Bit definition for ADC_SQR2 register ******************/
1656#define ADC_SQR2_SQ5_Pos (0U)
1657#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
1658#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
1659#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
1660#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
1661#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
1662#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
1663#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
1664
1665#define ADC_SQR2_SQ6_Pos (6U)
1666#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
1667#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
1668#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
1669#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
1670#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
1671#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
1672#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
1673
1674#define ADC_SQR2_SQ7_Pos (12U)
1675#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
1676#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
1677#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
1678#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
1679#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
1680#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
1681#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
1682
1683#define ADC_SQR2_SQ8_Pos (18U)
1684#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
1685#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
1686#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
1687#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
1688#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
1689#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
1690#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
1691
1692#define ADC_SQR2_SQ9_Pos (24U)
1693#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
1694#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
1695#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
1696#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
1697#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
1698#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
1699#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
1700
1701/******************** Bit definition for ADC_SQR3 register ******************/
1702#define ADC_SQR3_SQ10_Pos (0U)
1703#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
1704#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
1705#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
1706#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
1707#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
1708#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
1709#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
1710
1711#define ADC_SQR3_SQ11_Pos (6U)
1712#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
1713#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
1714#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
1715#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
1716#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
1717#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
1718#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
1719
1720#define ADC_SQR3_SQ12_Pos (12U)
1721#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
1722#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
1723#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
1724#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
1725#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
1726#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
1727#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
1728
1729#define ADC_SQR3_SQ13_Pos (18U)
1730#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
1731#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
1732#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
1733#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
1734#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
1735#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
1736#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
1737
1738#define ADC_SQR3_SQ14_Pos (24U)
1739#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
1740#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
1741#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
1742#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
1743#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
1744#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
1745#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
1746
1747/******************** Bit definition for ADC_SQR4 register ******************/
1748#define ADC_SQR4_SQ15_Pos (0U)
1749#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
1750#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
1751#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
1752#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
1753#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
1754#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
1755#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
1756
1757#define ADC_SQR4_SQ16_Pos (6U)
1758#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
1759#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
1760#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
1761#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
1762#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
1763#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
1764#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
1765
1766/******************** Bit definition for ADC_DR register ********************/
1767#define ADC_DR_RDATA_Pos (0U)
1768#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
1769#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
1770#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
1771#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
1772#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
1773#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
1774#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
1775#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
1776#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
1777#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
1778#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
1779#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
1780#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
1781#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
1782#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
1783#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
1784#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
1785#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
1786
1787/******************** Bit definition for ADC_JSQR register ******************/
1788#define ADC_JSQR_JL_Pos (0U)
1789#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
1790#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
1791#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
1792#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
1793
1794#define ADC_JSQR_JEXTSEL_Pos (2U)
1795#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
1796#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
1797#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
1798#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
1799#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
1800#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
1801
1802#define ADC_JSQR_JEXTEN_Pos (6U)
1803#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
1804#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
1805#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
1806#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
1807
1808#define ADC_JSQR_JSQ1_Pos (8U)
1809#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
1810#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
1811#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
1812#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
1813#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
1814#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
1815#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
1816
1817#define ADC_JSQR_JSQ2_Pos (14U)
1818#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
1819#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
1820#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
1821#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
1822#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
1823#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
1824#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
1825
1826#define ADC_JSQR_JSQ3_Pos (20U)
1827#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
1828#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
1829#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
1830#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
1831#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
1832#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
1833#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
1834
1835#define ADC_JSQR_JSQ4_Pos (26U)
1836#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
1837#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
1838#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
1839#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
1840#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
1841#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
1842#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
1843
1844/******************** Bit definition for ADC_OFR1 register ******************/
1845#define ADC_OFR1_OFFSET1_Pos (0U)
1846#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
1847#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
1848#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
1849#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
1850#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
1851#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
1852#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
1853#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
1854#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
1855#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
1856#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
1857#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
1858#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
1859#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
1860
1861#define ADC_OFR1_OFFSET1_CH_Pos (26U)
1862#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
1863#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
1864#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
1865#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
1866#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
1867#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
1868#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
1869
1870#define ADC_OFR1_OFFSET1_EN_Pos (31U)
1871#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
1872#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
1873
1874/******************** Bit definition for ADC_OFR2 register ******************/
1875#define ADC_OFR2_OFFSET2_Pos (0U)
1876#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
1877#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
1878#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
1879#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
1880#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
1881#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
1882#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
1883#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
1884#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
1885#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
1886#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
1887#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
1888#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
1889#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
1890
1891#define ADC_OFR2_OFFSET2_CH_Pos (26U)
1892#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
1893#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
1894#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
1895#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
1896#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
1897#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
1898#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
1899
1900#define ADC_OFR2_OFFSET2_EN_Pos (31U)
1901#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
1902#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
1903
1904/******************** Bit definition for ADC_OFR3 register ******************/
1905#define ADC_OFR3_OFFSET3_Pos (0U)
1906#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
1907#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
1908#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
1909#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
1910#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
1911#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
1912#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
1913#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
1914#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
1915#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
1916#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
1917#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
1918#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
1919#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
1920
1921#define ADC_OFR3_OFFSET3_CH_Pos (26U)
1922#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
1923#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
1924#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
1925#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
1926#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
1927#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
1928#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
1929
1930#define ADC_OFR3_OFFSET3_EN_Pos (31U)
1931#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
1932#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
1933
1934/******************** Bit definition for ADC_OFR4 register ******************/
1935#define ADC_OFR4_OFFSET4_Pos (0U)
1936#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
1937#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
1938#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
1939#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
1940#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
1941#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
1942#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
1943#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
1944#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
1945#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
1946#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
1947#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
1948#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
1949#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
1950
1951#define ADC_OFR4_OFFSET4_CH_Pos (26U)
1952#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
1953#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
1954#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
1955#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
1956#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
1957#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
1958#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
1959
1960#define ADC_OFR4_OFFSET4_EN_Pos (31U)
1961#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
1962#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
1963
1964/******************** Bit definition for ADC_JDR1 register ******************/
1965#define ADC_JDR1_JDATA_Pos (0U)
1966#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1967#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
1968#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
1969#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
1970#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
1971#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
1972#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
1973#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
1974#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
1975#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
1976#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
1977#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
1978#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
1979#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
1980#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
1981#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
1982#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
1983#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
1984
1985/******************** Bit definition for ADC_JDR2 register ******************/
1986#define ADC_JDR2_JDATA_Pos (0U)
1987#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1988#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
1989#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
1990#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
1991#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
1992#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
1993#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
1994#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
1995#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
1996#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
1997#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
1998#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
1999#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
2000#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
2001#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
2002#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
2003#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
2004#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
2005
2006/******************** Bit definition for ADC_JDR3 register ******************/
2007#define ADC_JDR3_JDATA_Pos (0U)
2008#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
2009#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
2010#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
2011#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
2012#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
2013#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
2014#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
2015#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
2016#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
2017#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
2018#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
2019#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
2020#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
2021#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
2022#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
2023#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
2024#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
2025#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
2026
2027/******************** Bit definition for ADC_JDR4 register ******************/
2028#define ADC_JDR4_JDATA_Pos (0U)
2029#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
2030#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
2031#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
2032#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
2033#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
2034#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
2035#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
2036#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
2037#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
2038#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
2039#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
2040#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
2041#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
2042#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
2043#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
2044#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
2045#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
2046#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
2047
2048/******************** Bit definition for ADC_AWD2CR register ****************/
2049#define ADC_AWD2CR_AWD2CH_Pos (0U)
2050#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
2051#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
2052#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
2053#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
2054#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
2055#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
2056#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
2057#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
2058#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
2059#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
2060#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
2061#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
2062#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
2063#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
2064#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
2065#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
2066#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
2067#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
2068#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
2069#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
2070#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
2071
2072/******************** Bit definition for ADC_AWD3CR register ****************/
2073#define ADC_AWD3CR_AWD3CH_Pos (0U)
2074#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
2075#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
2076#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
2077#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
2078#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
2079#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
2080#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
2081#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
2082#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
2083#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
2084#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
2085#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
2086#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
2087#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
2088#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
2089#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
2090#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
2091#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
2092#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
2093#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
2094#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
2095
2096/******************** Bit definition for ADC_DIFSEL register ****************/
2097#define ADC_DIFSEL_DIFSEL_Pos (0U)
2098#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
2099#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
2100#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
2101#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
2102#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
2103#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
2104#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
2105#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
2106#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
2107#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
2108#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
2109#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
2110#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
2111#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
2112#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
2113#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
2114#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
2115#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
2116#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
2117#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
2118#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
2119
2120/******************** Bit definition for ADC_CALFACT register ***************/
2121#define ADC_CALFACT_CALFACT_S_Pos (0U)
2122#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
2123#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
2124#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
2125#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
2126#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
2127#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
2128#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
2129#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
2130#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
2131
2132#define ADC_CALFACT_CALFACT_D_Pos (16U)
2133#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
2134#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
2135#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
2136#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
2137#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
2138#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
2139#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
2140#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
2141#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
2142
2143/************************* ADC Common registers *****************************/
2144/******************** Bit definition for ADC_CCR register *******************/
2145#define ADC_CCR_CKMODE_Pos (16U)
2146#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
2147#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2148#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
2149#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
2150
2151#define ADC_CCR_PRESC_Pos (18U)
2152#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
2153#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
2154#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
2155#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
2156#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
2157#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
2158
2159#define ADC_CCR_VREFEN_Pos (22U)
2160#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
2161#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
2162#define ADC_CCR_TSEN_Pos (23U)
2163#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
2164#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
2165#define ADC_CCR_VBATEN_Pos (24U)
2166#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
2167#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
2168
2169/******************************************************************************/
2170/* */
2171/* Controller Area Network */
2172/* */
2173/******************************************************************************/
2174/*!<CAN control and status registers */
2175/******************* Bit definition for CAN_MCR register ********************/
2176#define CAN_MCR_INRQ_Pos (0U)
2177#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
2178#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
2179#define CAN_MCR_SLEEP_Pos (1U)
2180#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
2181#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
2182#define CAN_MCR_TXFP_Pos (2U)
2183#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
2184#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
2185#define CAN_MCR_RFLM_Pos (3U)
2186#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
2187#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
2188#define CAN_MCR_NART_Pos (4U)
2189#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
2190#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
2191#define CAN_MCR_AWUM_Pos (5U)
2192#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
2193#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
2194#define CAN_MCR_ABOM_Pos (6U)
2195#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
2196#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
2197#define CAN_MCR_TTCM_Pos (7U)
2198#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
2199#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
2200#define CAN_MCR_RESET_Pos (15U)
2201#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
2202#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
2203
2204/******************* Bit definition for CAN_MSR register ********************/
2205#define CAN_MSR_INAK_Pos (0U)
2206#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
2207#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
2208#define CAN_MSR_SLAK_Pos (1U)
2209#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
2210#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
2211#define CAN_MSR_ERRI_Pos (2U)
2212#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
2213#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
2214#define CAN_MSR_WKUI_Pos (3U)
2215#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
2216#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
2217#define CAN_MSR_SLAKI_Pos (4U)
2218#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
2219#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
2220#define CAN_MSR_TXM_Pos (8U)
2221#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
2222#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
2223#define CAN_MSR_RXM_Pos (9U)
2224#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
2225#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
2226#define CAN_MSR_SAMP_Pos (10U)
2227#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
2228#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
2229#define CAN_MSR_RX_Pos (11U)
2230#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
2231#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
2232
2233/******************* Bit definition for CAN_TSR register ********************/
2234#define CAN_TSR_RQCP0_Pos (0U)
2235#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
2236#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
2237#define CAN_TSR_TXOK0_Pos (1U)
2238#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
2239#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
2240#define CAN_TSR_ALST0_Pos (2U)
2241#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
2242#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
2243#define CAN_TSR_TERR0_Pos (3U)
2244#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
2245#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
2246#define CAN_TSR_ABRQ0_Pos (7U)
2247#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
2248#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
2249#define CAN_TSR_RQCP1_Pos (8U)
2250#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
2251#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
2252#define CAN_TSR_TXOK1_Pos (9U)
2253#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
2254#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
2255#define CAN_TSR_ALST1_Pos (10U)
2256#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
2257#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
2258#define CAN_TSR_TERR1_Pos (11U)
2259#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
2260#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
2261#define CAN_TSR_ABRQ1_Pos (15U)
2262#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
2263#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
2264#define CAN_TSR_RQCP2_Pos (16U)
2265#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
2266#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
2267#define CAN_TSR_TXOK2_Pos (17U)
2268#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
2269#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
2270#define CAN_TSR_ALST2_Pos (18U)
2271#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
2272#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
2273#define CAN_TSR_TERR2_Pos (19U)
2274#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
2275#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
2276#define CAN_TSR_ABRQ2_Pos (23U)
2277#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
2278#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
2279#define CAN_TSR_CODE_Pos (24U)
2280#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
2281#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
2282
2283#define CAN_TSR_TME_Pos (26U)
2284#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
2285#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
2286#define CAN_TSR_TME0_Pos (26U)
2287#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
2288#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
2289#define CAN_TSR_TME1_Pos (27U)
2290#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
2291#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
2292#define CAN_TSR_TME2_Pos (28U)
2293#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
2294#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
2295
2296#define CAN_TSR_LOW_Pos (29U)
2297#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
2298#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
2299#define CAN_TSR_LOW0_Pos (29U)
2300#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
2301#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
2302#define CAN_TSR_LOW1_Pos (30U)
2303#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
2304#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
2305#define CAN_TSR_LOW2_Pos (31U)
2306#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
2307#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
2308
2309/******************* Bit definition for CAN_RF0R register *******************/
2310#define CAN_RF0R_FMP0_Pos (0U)
2311#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
2312#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
2313#define CAN_RF0R_FULL0_Pos (3U)
2314#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
2315#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
2316#define CAN_RF0R_FOVR0_Pos (4U)
2317#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
2318#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
2319#define CAN_RF0R_RFOM0_Pos (5U)
2320#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
2321#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
2322
2323/******************* Bit definition for CAN_RF1R register *******************/
2324#define CAN_RF1R_FMP1_Pos (0U)
2325#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
2326#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
2327#define CAN_RF1R_FULL1_Pos (3U)
2328#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
2329#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
2330#define CAN_RF1R_FOVR1_Pos (4U)
2331#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
2332#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
2333#define CAN_RF1R_RFOM1_Pos (5U)
2334#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
2335#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
2336
2337/******************** Bit definition for CAN_IER register *******************/
2338#define CAN_IER_TMEIE_Pos (0U)
2339#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
2340#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
2341#define CAN_IER_FMPIE0_Pos (1U)
2342#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
2343#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
2344#define CAN_IER_FFIE0_Pos (2U)
2345#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
2346#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
2347#define CAN_IER_FOVIE0_Pos (3U)
2348#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
2349#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2350#define CAN_IER_FMPIE1_Pos (4U)
2351#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2352#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2353#define CAN_IER_FFIE1_Pos (5U)
2354#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2355#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2356#define CAN_IER_FOVIE1_Pos (6U)
2357#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2358#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2359#define CAN_IER_EWGIE_Pos (8U)
2360#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2361#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2362#define CAN_IER_EPVIE_Pos (9U)
2363#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2364#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2365#define CAN_IER_BOFIE_Pos (10U)
2366#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2367#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2368#define CAN_IER_LECIE_Pos (11U)
2369#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
2370#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
2371#define CAN_IER_ERRIE_Pos (15U)
2372#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2373#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2374#define CAN_IER_WKUIE_Pos (16U)
2375#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2376#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2377#define CAN_IER_SLKIE_Pos (17U)
2378#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2379#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2380
2381/******************** Bit definition for CAN_ESR register *******************/
2382#define CAN_ESR_EWGF_Pos (0U)
2383#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2384#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2385#define CAN_ESR_EPVF_Pos (1U)
2386#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2387#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2388#define CAN_ESR_BOFF_Pos (2U)
2389#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2390#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2391
2392#define CAN_ESR_LEC_Pos (4U)
2393#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2394#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2395#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2396#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2397#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2398
2399#define CAN_ESR_TEC_Pos (16U)
2400#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2401#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2402#define CAN_ESR_REC_Pos (24U)
2403#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2404#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2405
2406/******************* Bit definition for CAN_BTR register ********************/
2407#define CAN_BTR_BRP_Pos (0U)
2408#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2409#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2410#define CAN_BTR_TS1_Pos (16U)
2411#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2412#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2413#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2414#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2415#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2416#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2417#define CAN_BTR_TS2_Pos (20U)
2418#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2419#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2420#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2421#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2422#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2423#define CAN_BTR_SJW_Pos (24U)
2424#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2425#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2426#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2427#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2428#define CAN_BTR_LBKM_Pos (30U)
2429#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2430#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2431#define CAN_BTR_SILM_Pos (31U)
2432#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2433#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2434
2435/*!<Mailbox registers */
2436/****************** Bit definition for CAN_TI0R register ********************/
2437#define CAN_TI0R_TXRQ_Pos (0U)
2438#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2439#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2440#define CAN_TI0R_RTR_Pos (1U)
2441#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2442#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2443#define CAN_TI0R_IDE_Pos (2U)
2444#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2445#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2446#define CAN_TI0R_EXID_Pos (3U)
2447#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2448#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2449#define CAN_TI0R_STID_Pos (21U)
2450#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2451#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2452
2453/****************** Bit definition for CAN_TDT0R register *******************/
2454#define CAN_TDT0R_DLC_Pos (0U)
2455#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2456#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2457#define CAN_TDT0R_TGT_Pos (8U)
2458#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2459#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2460#define CAN_TDT0R_TIME_Pos (16U)
2461#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2462#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2463
2464/****************** Bit definition for CAN_TDL0R register *******************/
2465#define CAN_TDL0R_DATA0_Pos (0U)
2466#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2467#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2468#define CAN_TDL0R_DATA1_Pos (8U)
2469#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2470#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2471#define CAN_TDL0R_DATA2_Pos (16U)
2472#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2473#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2474#define CAN_TDL0R_DATA3_Pos (24U)
2475#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2476#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2477
2478/****************** Bit definition for CAN_TDH0R register *******************/
2479#define CAN_TDH0R_DATA4_Pos (0U)
2480#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2481#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2482#define CAN_TDH0R_DATA5_Pos (8U)
2483#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2484#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2485#define CAN_TDH0R_DATA6_Pos (16U)
2486#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2487#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2488#define CAN_TDH0R_DATA7_Pos (24U)
2489#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2490#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2491
2492/******************* Bit definition for CAN_TI1R register *******************/
2493#define CAN_TI1R_TXRQ_Pos (0U)
2494#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2495#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2496#define CAN_TI1R_RTR_Pos (1U)
2497#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2498#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2499#define CAN_TI1R_IDE_Pos (2U)
2500#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2501#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2502#define CAN_TI1R_EXID_Pos (3U)
2503#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2504#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2505#define CAN_TI1R_STID_Pos (21U)
2506#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2507#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2508
2509/******************* Bit definition for CAN_TDT1R register ******************/
2510#define CAN_TDT1R_DLC_Pos (0U)
2511#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2512#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2513#define CAN_TDT1R_TGT_Pos (8U)
2514#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2515#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2516#define CAN_TDT1R_TIME_Pos (16U)
2517#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2518#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2519
2520/******************* Bit definition for CAN_TDL1R register ******************/
2521#define CAN_TDL1R_DATA0_Pos (0U)
2522#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2523#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2524#define CAN_TDL1R_DATA1_Pos (8U)
2525#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2526#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2527#define CAN_TDL1R_DATA2_Pos (16U)
2528#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2529#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2530#define CAN_TDL1R_DATA3_Pos (24U)
2531#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2532#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2533
2534/******************* Bit definition for CAN_TDH1R register ******************/
2535#define CAN_TDH1R_DATA4_Pos (0U)
2536#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2537#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2538#define CAN_TDH1R_DATA5_Pos (8U)
2539#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2540#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2541#define CAN_TDH1R_DATA6_Pos (16U)
2542#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2543#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2544#define CAN_TDH1R_DATA7_Pos (24U)
2545#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2546#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2547
2548/******************* Bit definition for CAN_TI2R register *******************/
2549#define CAN_TI2R_TXRQ_Pos (0U)
2550#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2551#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2552#define CAN_TI2R_RTR_Pos (1U)
2553#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2554#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2555#define CAN_TI2R_IDE_Pos (2U)
2556#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2557#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2558#define CAN_TI2R_EXID_Pos (3U)
2559#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2560#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2561#define CAN_TI2R_STID_Pos (21U)
2562#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2563#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2564
2565/******************* Bit definition for CAN_TDT2R register ******************/
2566#define CAN_TDT2R_DLC_Pos (0U)
2567#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2568#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2569#define CAN_TDT2R_TGT_Pos (8U)
2570#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2571#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2572#define CAN_TDT2R_TIME_Pos (16U)
2573#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2574#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2575
2576/******************* Bit definition for CAN_TDL2R register ******************/
2577#define CAN_TDL2R_DATA0_Pos (0U)
2578#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2579#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2580#define CAN_TDL2R_DATA1_Pos (8U)
2581#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2582#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2583#define CAN_TDL2R_DATA2_Pos (16U)
2584#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2585#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2586#define CAN_TDL2R_DATA3_Pos (24U)
2587#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2588#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2589
2590/******************* Bit definition for CAN_TDH2R register ******************/
2591#define CAN_TDH2R_DATA4_Pos (0U)
2592#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2593#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2594#define CAN_TDH2R_DATA5_Pos (8U)
2595#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2596#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2597#define CAN_TDH2R_DATA6_Pos (16U)
2598#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2599#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2600#define CAN_TDH2R_DATA7_Pos (24U)
2601#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2602#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2603
2604/******************* Bit definition for CAN_RI0R register *******************/
2605#define CAN_RI0R_RTR_Pos (1U)
2606#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2607#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2608#define CAN_RI0R_IDE_Pos (2U)
2609#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2610#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2611#define CAN_RI0R_EXID_Pos (3U)
2612#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2613#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2614#define CAN_RI0R_STID_Pos (21U)
2615#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2616#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2617
2618/******************* Bit definition for CAN_RDT0R register ******************/
2619#define CAN_RDT0R_DLC_Pos (0U)
2620#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2621#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2622#define CAN_RDT0R_FMI_Pos (8U)
2623#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2624#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2625#define CAN_RDT0R_TIME_Pos (16U)
2626#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2627#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2628
2629/******************* Bit definition for CAN_RDL0R register ******************/
2630#define CAN_RDL0R_DATA0_Pos (0U)
2631#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2632#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2633#define CAN_RDL0R_DATA1_Pos (8U)
2634#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2635#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2636#define CAN_RDL0R_DATA2_Pos (16U)
2637#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2638#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2639#define CAN_RDL0R_DATA3_Pos (24U)
2640#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2641#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2642
2643/******************* Bit definition for CAN_RDH0R register ******************/
2644#define CAN_RDH0R_DATA4_Pos (0U)
2645#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2646#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2647#define CAN_RDH0R_DATA5_Pos (8U)
2648#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2649#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2650#define CAN_RDH0R_DATA6_Pos (16U)
2651#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2652#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2653#define CAN_RDH0R_DATA7_Pos (24U)
2654#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2655#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2656
2657/******************* Bit definition for CAN_RI1R register *******************/
2658#define CAN_RI1R_RTR_Pos (1U)
2659#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2660#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2661#define CAN_RI1R_IDE_Pos (2U)
2662#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2663#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2664#define CAN_RI1R_EXID_Pos (3U)
2665#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2666#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2667#define CAN_RI1R_STID_Pos (21U)
2668#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2669#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2670
2671/******************* Bit definition for CAN_RDT1R register ******************/
2672#define CAN_RDT1R_DLC_Pos (0U)
2673#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2674#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2675#define CAN_RDT1R_FMI_Pos (8U)
2676#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2677#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2678#define CAN_RDT1R_TIME_Pos (16U)
2679#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2680#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2681
2682/******************* Bit definition for CAN_RDL1R register ******************/
2683#define CAN_RDL1R_DATA0_Pos (0U)
2684#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2685#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2686#define CAN_RDL1R_DATA1_Pos (8U)
2687#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2688#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2689#define CAN_RDL1R_DATA2_Pos (16U)
2690#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2691#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2692#define CAN_RDL1R_DATA3_Pos (24U)
2693#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2694#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2695
2696/******************* Bit definition for CAN_RDH1R register ******************/
2697#define CAN_RDH1R_DATA4_Pos (0U)
2698#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2699#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2700#define CAN_RDH1R_DATA5_Pos (8U)
2701#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2702#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2703#define CAN_RDH1R_DATA6_Pos (16U)
2704#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2705#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2706#define CAN_RDH1R_DATA7_Pos (24U)
2707#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2708#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2709
2710/*!<CAN filter registers */
2711/******************* Bit definition for CAN_FMR register ********************/
2712#define CAN_FMR_FINIT_Pos (0U)
2713#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
2714#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
2715
2716/******************* Bit definition for CAN_FM1R register *******************/
2717#define CAN_FM1R_FBM_Pos (0U)
2718#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
2719#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2720#define CAN_FM1R_FBM0_Pos (0U)
2721#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2722#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2723#define CAN_FM1R_FBM1_Pos (1U)
2724#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2725#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2726#define CAN_FM1R_FBM2_Pos (2U)
2727#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2728#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2729#define CAN_FM1R_FBM3_Pos (3U)
2730#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2731#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2732#define CAN_FM1R_FBM4_Pos (4U)
2733#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2734#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2735#define CAN_FM1R_FBM5_Pos (5U)
2736#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2737#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2738#define CAN_FM1R_FBM6_Pos (6U)
2739#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2740#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2741#define CAN_FM1R_FBM7_Pos (7U)
2742#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2743#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2744#define CAN_FM1R_FBM8_Pos (8U)
2745#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2746#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2747#define CAN_FM1R_FBM9_Pos (9U)
2748#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2749#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2750#define CAN_FM1R_FBM10_Pos (10U)
2751#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2752#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2753#define CAN_FM1R_FBM11_Pos (11U)
2754#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2755#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2756#define CAN_FM1R_FBM12_Pos (12U)
2757#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2758#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2759#define CAN_FM1R_FBM13_Pos (13U)
2760#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2761#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2762
2763/******************* Bit definition for CAN_FS1R register *******************/
2764#define CAN_FS1R_FSC_Pos (0U)
2765#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
2766#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2767#define CAN_FS1R_FSC0_Pos (0U)
2768#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2769#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2770#define CAN_FS1R_FSC1_Pos (1U)
2771#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2772#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2773#define CAN_FS1R_FSC2_Pos (2U)
2774#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2775#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2776#define CAN_FS1R_FSC3_Pos (3U)
2777#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2778#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2779#define CAN_FS1R_FSC4_Pos (4U)
2780#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2781#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2782#define CAN_FS1R_FSC5_Pos (5U)
2783#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2784#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2785#define CAN_FS1R_FSC6_Pos (6U)
2786#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2787#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2788#define CAN_FS1R_FSC7_Pos (7U)
2789#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2790#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2791#define CAN_FS1R_FSC8_Pos (8U)
2792#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
2793#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
2794#define CAN_FS1R_FSC9_Pos (9U)
2795#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
2796#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
2797#define CAN_FS1R_FSC10_Pos (10U)
2798#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
2799#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
2800#define CAN_FS1R_FSC11_Pos (11U)
2801#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
2802#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
2803#define CAN_FS1R_FSC12_Pos (12U)
2804#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
2805#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
2806#define CAN_FS1R_FSC13_Pos (13U)
2807#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
2808#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
2809
2810/****************** Bit definition for CAN_FFA1R register *******************/
2811#define CAN_FFA1R_FFA_Pos (0U)
2812#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
2813#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
2814#define CAN_FFA1R_FFA0_Pos (0U)
2815#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
2816#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
2817#define CAN_FFA1R_FFA1_Pos (1U)
2818#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
2819#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
2820#define CAN_FFA1R_FFA2_Pos (2U)
2821#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
2822#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
2823#define CAN_FFA1R_FFA3_Pos (3U)
2824#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
2825#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
2826#define CAN_FFA1R_FFA4_Pos (4U)
2827#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
2828#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
2829#define CAN_FFA1R_FFA5_Pos (5U)
2830#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
2831#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
2832#define CAN_FFA1R_FFA6_Pos (6U)
2833#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
2834#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
2835#define CAN_FFA1R_FFA7_Pos (7U)
2836#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
2837#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
2838#define CAN_FFA1R_FFA8_Pos (8U)
2839#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
2840#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
2841#define CAN_FFA1R_FFA9_Pos (9U)
2842#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
2843#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
2844#define CAN_FFA1R_FFA10_Pos (10U)
2845#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
2846#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
2847#define CAN_FFA1R_FFA11_Pos (11U)
2848#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
2849#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
2850#define CAN_FFA1R_FFA12_Pos (12U)
2851#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
2852#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
2853#define CAN_FFA1R_FFA13_Pos (13U)
2854#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
2855#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
2856
2857/******************* Bit definition for CAN_FA1R register *******************/
2858#define CAN_FA1R_FACT_Pos (0U)
2859#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
2860#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
2861#define CAN_FA1R_FACT0_Pos (0U)
2862#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
2863#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
2864#define CAN_FA1R_FACT1_Pos (1U)
2865#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
2866#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
2867#define CAN_FA1R_FACT2_Pos (2U)
2868#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
2869#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
2870#define CAN_FA1R_FACT3_Pos (3U)
2871#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
2872#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
2873#define CAN_FA1R_FACT4_Pos (4U)
2874#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
2875#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
2876#define CAN_FA1R_FACT5_Pos (5U)
2877#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
2878#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
2879#define CAN_FA1R_FACT6_Pos (6U)
2880#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
2881#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
2882#define CAN_FA1R_FACT7_Pos (7U)
2883#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
2884#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
2885#define CAN_FA1R_FACT8_Pos (8U)
2886#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
2887#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
2888#define CAN_FA1R_FACT9_Pos (9U)
2889#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
2890#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
2891#define CAN_FA1R_FACT10_Pos (10U)
2892#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
2893#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
2894#define CAN_FA1R_FACT11_Pos (11U)
2895#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
2896#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
2897#define CAN_FA1R_FACT12_Pos (12U)
2898#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
2899#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
2900#define CAN_FA1R_FACT13_Pos (13U)
2901#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
2902#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
2903
2904/******************* Bit definition for CAN_F0R1 register *******************/
2905#define CAN_F0R1_FB0_Pos (0U)
2906#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
2907#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
2908#define CAN_F0R1_FB1_Pos (1U)
2909#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
2910#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
2911#define CAN_F0R1_FB2_Pos (2U)
2912#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
2913#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
2914#define CAN_F0R1_FB3_Pos (3U)
2915#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
2916#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
2917#define CAN_F0R1_FB4_Pos (4U)
2918#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
2919#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
2920#define CAN_F0R1_FB5_Pos (5U)
2921#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
2922#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
2923#define CAN_F0R1_FB6_Pos (6U)
2924#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
2925#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
2926#define CAN_F0R1_FB7_Pos (7U)
2927#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
2928#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
2929#define CAN_F0R1_FB8_Pos (8U)
2930#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
2931#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
2932#define CAN_F0R1_FB9_Pos (9U)
2933#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
2934#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
2935#define CAN_F0R1_FB10_Pos (10U)
2936#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
2937#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
2938#define CAN_F0R1_FB11_Pos (11U)
2939#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
2940#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
2941#define CAN_F0R1_FB12_Pos (12U)
2942#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
2943#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
2944#define CAN_F0R1_FB13_Pos (13U)
2945#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
2946#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
2947#define CAN_F0R1_FB14_Pos (14U)
2948#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
2949#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
2950#define CAN_F0R1_FB15_Pos (15U)
2951#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
2952#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
2953#define CAN_F0R1_FB16_Pos (16U)
2954#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
2955#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
2956#define CAN_F0R1_FB17_Pos (17U)
2957#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
2958#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
2959#define CAN_F0R1_FB18_Pos (18U)
2960#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
2961#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
2962#define CAN_F0R1_FB19_Pos (19U)
2963#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
2964#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
2965#define CAN_F0R1_FB20_Pos (20U)
2966#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
2967#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
2968#define CAN_F0R1_FB21_Pos (21U)
2969#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
2970#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
2971#define CAN_F0R1_FB22_Pos (22U)
2972#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
2973#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
2974#define CAN_F0R1_FB23_Pos (23U)
2975#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
2976#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
2977#define CAN_F0R1_FB24_Pos (24U)
2978#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
2979#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
2980#define CAN_F0R1_FB25_Pos (25U)
2981#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
2982#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
2983#define CAN_F0R1_FB26_Pos (26U)
2984#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
2985#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
2986#define CAN_F0R1_FB27_Pos (27U)
2987#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
2988#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
2989#define CAN_F0R1_FB28_Pos (28U)
2990#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
2991#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
2992#define CAN_F0R1_FB29_Pos (29U)
2993#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
2994#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
2995#define CAN_F0R1_FB30_Pos (30U)
2996#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
2997#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
2998#define CAN_F0R1_FB31_Pos (31U)
2999#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
3000#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
3001
3002/******************* Bit definition for CAN_F1R1 register *******************/
3003#define CAN_F1R1_FB0_Pos (0U)
3004#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
3005#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
3006#define CAN_F1R1_FB1_Pos (1U)
3007#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
3008#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
3009#define CAN_F1R1_FB2_Pos (2U)
3010#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
3011#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
3012#define CAN_F1R1_FB3_Pos (3U)
3013#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
3014#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
3015#define CAN_F1R1_FB4_Pos (4U)
3016#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
3017#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
3018#define CAN_F1R1_FB5_Pos (5U)
3019#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
3020#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
3021#define CAN_F1R1_FB6_Pos (6U)
3022#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
3023#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
3024#define CAN_F1R1_FB7_Pos (7U)
3025#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
3026#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
3027#define CAN_F1R1_FB8_Pos (8U)
3028#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
3029#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
3030#define CAN_F1R1_FB9_Pos (9U)
3031#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
3032#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
3033#define CAN_F1R1_FB10_Pos (10U)
3034#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
3035#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
3036#define CAN_F1R1_FB11_Pos (11U)
3037#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
3038#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
3039#define CAN_F1R1_FB12_Pos (12U)
3040#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
3041#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
3042#define CAN_F1R1_FB13_Pos (13U)
3043#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
3044#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
3045#define CAN_F1R1_FB14_Pos (14U)
3046#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
3047#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
3048#define CAN_F1R1_FB15_Pos (15U)
3049#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
3050#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
3051#define CAN_F1R1_FB16_Pos (16U)
3052#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
3053#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
3054#define CAN_F1R1_FB17_Pos (17U)
3055#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
3056#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
3057#define CAN_F1R1_FB18_Pos (18U)
3058#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
3059#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
3060#define CAN_F1R1_FB19_Pos (19U)
3061#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
3062#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
3063#define CAN_F1R1_FB20_Pos (20U)
3064#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
3065#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
3066#define CAN_F1R1_FB21_Pos (21U)
3067#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
3068#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
3069#define CAN_F1R1_FB22_Pos (22U)
3070#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
3071#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
3072#define CAN_F1R1_FB23_Pos (23U)
3073#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
3074#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
3075#define CAN_F1R1_FB24_Pos (24U)
3076#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
3077#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
3078#define CAN_F1R1_FB25_Pos (25U)
3079#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
3080#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
3081#define CAN_F1R1_FB26_Pos (26U)
3082#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
3083#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
3084#define CAN_F1R1_FB27_Pos (27U)
3085#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
3086#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
3087#define CAN_F1R1_FB28_Pos (28U)
3088#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
3089#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
3090#define CAN_F1R1_FB29_Pos (29U)
3091#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
3092#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
3093#define CAN_F1R1_FB30_Pos (30U)
3094#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
3095#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
3096#define CAN_F1R1_FB31_Pos (31U)
3097#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
3098#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
3099
3100/******************* Bit definition for CAN_F2R1 register *******************/
3101#define CAN_F2R1_FB0_Pos (0U)
3102#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
3103#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
3104#define CAN_F2R1_FB1_Pos (1U)
3105#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
3106#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
3107#define CAN_F2R1_FB2_Pos (2U)
3108#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
3109#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
3110#define CAN_F2R1_FB3_Pos (3U)
3111#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
3112#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
3113#define CAN_F2R1_FB4_Pos (4U)
3114#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
3115#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
3116#define CAN_F2R1_FB5_Pos (5U)
3117#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
3118#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
3119#define CAN_F2R1_FB6_Pos (6U)
3120#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
3121#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
3122#define CAN_F2R1_FB7_Pos (7U)
3123#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
3124#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
3125#define CAN_F2R1_FB8_Pos (8U)
3126#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
3127#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
3128#define CAN_F2R1_FB9_Pos (9U)
3129#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
3130#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
3131#define CAN_F2R1_FB10_Pos (10U)
3132#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
3133#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
3134#define CAN_F2R1_FB11_Pos (11U)
3135#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
3136#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
3137#define CAN_F2R1_FB12_Pos (12U)
3138#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
3139#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
3140#define CAN_F2R1_FB13_Pos (13U)
3141#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
3142#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
3143#define CAN_F2R1_FB14_Pos (14U)
3144#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
3145#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
3146#define CAN_F2R1_FB15_Pos (15U)
3147#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
3148#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
3149#define CAN_F2R1_FB16_Pos (16U)
3150#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
3151#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
3152#define CAN_F2R1_FB17_Pos (17U)
3153#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
3154#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
3155#define CAN_F2R1_FB18_Pos (18U)
3156#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
3157#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
3158#define CAN_F2R1_FB19_Pos (19U)
3159#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
3160#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
3161#define CAN_F2R1_FB20_Pos (20U)
3162#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
3163#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
3164#define CAN_F2R1_FB21_Pos (21U)
3165#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
3166#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
3167#define CAN_F2R1_FB22_Pos (22U)
3168#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
3169#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
3170#define CAN_F2R1_FB23_Pos (23U)
3171#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
3172#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
3173#define CAN_F2R1_FB24_Pos (24U)
3174#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
3175#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
3176#define CAN_F2R1_FB25_Pos (25U)
3177#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
3178#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
3179#define CAN_F2R1_FB26_Pos (26U)
3180#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
3181#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
3182#define CAN_F2R1_FB27_Pos (27U)
3183#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
3184#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
3185#define CAN_F2R1_FB28_Pos (28U)
3186#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
3187#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
3188#define CAN_F2R1_FB29_Pos (29U)
3189#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
3190#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
3191#define CAN_F2R1_FB30_Pos (30U)
3192#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
3193#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
3194#define CAN_F2R1_FB31_Pos (31U)
3195#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
3196#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
3197
3198/******************* Bit definition for CAN_F3R1 register *******************/
3199#define CAN_F3R1_FB0_Pos (0U)
3200#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
3201#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3202#define CAN_F3R1_FB1_Pos (1U)
3203#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3204#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3205#define CAN_F3R1_FB2_Pos (2U)
3206#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3207#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3208#define CAN_F3R1_FB3_Pos (3U)
3209#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3210#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3211#define CAN_F3R1_FB4_Pos (4U)
3212#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3213#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3214#define CAN_F3R1_FB5_Pos (5U)
3215#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3216#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3217#define CAN_F3R1_FB6_Pos (6U)
3218#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3219#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3220#define CAN_F3R1_FB7_Pos (7U)
3221#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3222#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3223#define CAN_F3R1_FB8_Pos (8U)
3224#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3225#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3226#define CAN_F3R1_FB9_Pos (9U)
3227#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3228#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3229#define CAN_F3R1_FB10_Pos (10U)
3230#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3231#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3232#define CAN_F3R1_FB11_Pos (11U)
3233#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3234#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3235#define CAN_F3R1_FB12_Pos (12U)
3236#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3237#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3238#define CAN_F3R1_FB13_Pos (13U)
3239#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3240#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3241#define CAN_F3R1_FB14_Pos (14U)
3242#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3243#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3244#define CAN_F3R1_FB15_Pos (15U)
3245#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3246#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3247#define CAN_F3R1_FB16_Pos (16U)
3248#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3249#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3250#define CAN_F3R1_FB17_Pos (17U)
3251#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3252#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3253#define CAN_F3R1_FB18_Pos (18U)
3254#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3255#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3256#define CAN_F3R1_FB19_Pos (19U)
3257#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3258#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3259#define CAN_F3R1_FB20_Pos (20U)
3260#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3261#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3262#define CAN_F3R1_FB21_Pos (21U)
3263#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3264#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3265#define CAN_F3R1_FB22_Pos (22U)
3266#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3267#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3268#define CAN_F3R1_FB23_Pos (23U)
3269#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3270#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3271#define CAN_F3R1_FB24_Pos (24U)
3272#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3273#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3274#define CAN_F3R1_FB25_Pos (25U)
3275#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3276#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3277#define CAN_F3R1_FB26_Pos (26U)
3278#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3279#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3280#define CAN_F3R1_FB27_Pos (27U)
3281#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3282#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3283#define CAN_F3R1_FB28_Pos (28U)
3284#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3285#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3286#define CAN_F3R1_FB29_Pos (29U)
3287#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3288#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3289#define CAN_F3R1_FB30_Pos (30U)
3290#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3291#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3292#define CAN_F3R1_FB31_Pos (31U)
3293#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3294#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3295
3296/******************* Bit definition for CAN_F4R1 register *******************/
3297#define CAN_F4R1_FB0_Pos (0U)
3298#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3299#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3300#define CAN_F4R1_FB1_Pos (1U)
3301#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3302#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3303#define CAN_F4R1_FB2_Pos (2U)
3304#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3305#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3306#define CAN_F4R1_FB3_Pos (3U)
3307#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3308#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3309#define CAN_F4R1_FB4_Pos (4U)
3310#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3311#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3312#define CAN_F4R1_FB5_Pos (5U)
3313#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3314#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3315#define CAN_F4R1_FB6_Pos (6U)
3316#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3317#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3318#define CAN_F4R1_FB7_Pos (7U)
3319#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3320#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3321#define CAN_F4R1_FB8_Pos (8U)
3322#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3323#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3324#define CAN_F4R1_FB9_Pos (9U)
3325#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3326#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3327#define CAN_F4R1_FB10_Pos (10U)
3328#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3329#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3330#define CAN_F4R1_FB11_Pos (11U)
3331#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3332#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3333#define CAN_F4R1_FB12_Pos (12U)
3334#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3335#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3336#define CAN_F4R1_FB13_Pos (13U)
3337#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3338#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3339#define CAN_F4R1_FB14_Pos (14U)
3340#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3341#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3342#define CAN_F4R1_FB15_Pos (15U)
3343#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3344#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3345#define CAN_F4R1_FB16_Pos (16U)
3346#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3347#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3348#define CAN_F4R1_FB17_Pos (17U)
3349#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3350#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3351#define CAN_F4R1_FB18_Pos (18U)
3352#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3353#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3354#define CAN_F4R1_FB19_Pos (19U)
3355#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3356#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3357#define CAN_F4R1_FB20_Pos (20U)
3358#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3359#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3360#define CAN_F4R1_FB21_Pos (21U)
3361#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3362#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3363#define CAN_F4R1_FB22_Pos (22U)
3364#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3365#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3366#define CAN_F4R1_FB23_Pos (23U)
3367#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3368#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3369#define CAN_F4R1_FB24_Pos (24U)
3370#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3371#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3372#define CAN_F4R1_FB25_Pos (25U)
3373#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3374#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3375#define CAN_F4R1_FB26_Pos (26U)
3376#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3377#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3378#define CAN_F4R1_FB27_Pos (27U)
3379#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3380#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3381#define CAN_F4R1_FB28_Pos (28U)
3382#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3383#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3384#define CAN_F4R1_FB29_Pos (29U)
3385#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3386#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3387#define CAN_F4R1_FB30_Pos (30U)
3388#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3389#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3390#define CAN_F4R1_FB31_Pos (31U)
3391#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3392#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3393
3394/******************* Bit definition for CAN_F5R1 register *******************/
3395#define CAN_F5R1_FB0_Pos (0U)
3396#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3397#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3398#define CAN_F5R1_FB1_Pos (1U)
3399#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3400#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3401#define CAN_F5R1_FB2_Pos (2U)
3402#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3403#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3404#define CAN_F5R1_FB3_Pos (3U)
3405#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3406#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3407#define CAN_F5R1_FB4_Pos (4U)
3408#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3409#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3410#define CAN_F5R1_FB5_Pos (5U)
3411#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3412#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3413#define CAN_F5R1_FB6_Pos (6U)
3414#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3415#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3416#define CAN_F5R1_FB7_Pos (7U)
3417#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3418#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3419#define CAN_F5R1_FB8_Pos (8U)
3420#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3421#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3422#define CAN_F5R1_FB9_Pos (9U)
3423#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3424#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3425#define CAN_F5R1_FB10_Pos (10U)
3426#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3427#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3428#define CAN_F5R1_FB11_Pos (11U)
3429#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3430#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3431#define CAN_F5R1_FB12_Pos (12U)
3432#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3433#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3434#define CAN_F5R1_FB13_Pos (13U)
3435#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3436#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3437#define CAN_F5R1_FB14_Pos (14U)
3438#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3439#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3440#define CAN_F5R1_FB15_Pos (15U)
3441#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3442#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3443#define CAN_F5R1_FB16_Pos (16U)
3444#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3445#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3446#define CAN_F5R1_FB17_Pos (17U)
3447#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3448#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3449#define CAN_F5R1_FB18_Pos (18U)
3450#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3451#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3452#define CAN_F5R1_FB19_Pos (19U)
3453#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3454#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3455#define CAN_F5R1_FB20_Pos (20U)
3456#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3457#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3458#define CAN_F5R1_FB21_Pos (21U)
3459#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3460#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3461#define CAN_F5R1_FB22_Pos (22U)
3462#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3463#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3464#define CAN_F5R1_FB23_Pos (23U)
3465#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3466#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3467#define CAN_F5R1_FB24_Pos (24U)
3468#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3469#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3470#define CAN_F5R1_FB25_Pos (25U)
3471#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3472#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3473#define CAN_F5R1_FB26_Pos (26U)
3474#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3475#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3476#define CAN_F5R1_FB27_Pos (27U)
3477#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3478#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3479#define CAN_F5R1_FB28_Pos (28U)
3480#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3481#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3482#define CAN_F5R1_FB29_Pos (29U)
3483#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3484#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3485#define CAN_F5R1_FB30_Pos (30U)
3486#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3487#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3488#define CAN_F5R1_FB31_Pos (31U)
3489#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3490#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3491
3492/******************* Bit definition for CAN_F6R1 register *******************/
3493#define CAN_F6R1_FB0_Pos (0U)
3494#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3495#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3496#define CAN_F6R1_FB1_Pos (1U)
3497#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3498#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3499#define CAN_F6R1_FB2_Pos (2U)
3500#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3501#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3502#define CAN_F6R1_FB3_Pos (3U)
3503#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3504#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3505#define CAN_F6R1_FB4_Pos (4U)
3506#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3507#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3508#define CAN_F6R1_FB5_Pos (5U)
3509#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3510#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3511#define CAN_F6R1_FB6_Pos (6U)
3512#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3513#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3514#define CAN_F6R1_FB7_Pos (7U)
3515#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3516#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3517#define CAN_F6R1_FB8_Pos (8U)
3518#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3519#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3520#define CAN_F6R1_FB9_Pos (9U)
3521#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3522#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3523#define CAN_F6R1_FB10_Pos (10U)
3524#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3525#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3526#define CAN_F6R1_FB11_Pos (11U)
3527#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3528#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3529#define CAN_F6R1_FB12_Pos (12U)
3530#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3531#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3532#define CAN_F6R1_FB13_Pos (13U)
3533#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3534#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3535#define CAN_F6R1_FB14_Pos (14U)
3536#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3537#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3538#define CAN_F6R1_FB15_Pos (15U)
3539#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3540#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3541#define CAN_F6R1_FB16_Pos (16U)
3542#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3543#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3544#define CAN_F6R1_FB17_Pos (17U)
3545#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3546#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3547#define CAN_F6R1_FB18_Pos (18U)
3548#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3549#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3550#define CAN_F6R1_FB19_Pos (19U)
3551#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3552#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3553#define CAN_F6R1_FB20_Pos (20U)
3554#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3555#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3556#define CAN_F6R1_FB21_Pos (21U)
3557#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3558#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3559#define CAN_F6R1_FB22_Pos (22U)
3560#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3561#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3562#define CAN_F6R1_FB23_Pos (23U)
3563#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3564#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3565#define CAN_F6R1_FB24_Pos (24U)
3566#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3567#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3568#define CAN_F6R1_FB25_Pos (25U)
3569#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3570#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3571#define CAN_F6R1_FB26_Pos (26U)
3572#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3573#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3574#define CAN_F6R1_FB27_Pos (27U)
3575#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3576#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3577#define CAN_F6R1_FB28_Pos (28U)
3578#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3579#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3580#define CAN_F6R1_FB29_Pos (29U)
3581#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3582#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3583#define CAN_F6R1_FB30_Pos (30U)
3584#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3585#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3586#define CAN_F6R1_FB31_Pos (31U)
3587#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3588#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3589
3590/******************* Bit definition for CAN_F7R1 register *******************/
3591#define CAN_F7R1_FB0_Pos (0U)
3592#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3593#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3594#define CAN_F7R1_FB1_Pos (1U)
3595#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3596#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3597#define CAN_F7R1_FB2_Pos (2U)
3598#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3599#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3600#define CAN_F7R1_FB3_Pos (3U)
3601#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3602#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3603#define CAN_F7R1_FB4_Pos (4U)
3604#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3605#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3606#define CAN_F7R1_FB5_Pos (5U)
3607#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3608#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3609#define CAN_F7R1_FB6_Pos (6U)
3610#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3611#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3612#define CAN_F7R1_FB7_Pos (7U)
3613#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3614#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3615#define CAN_F7R1_FB8_Pos (8U)
3616#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3617#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3618#define CAN_F7R1_FB9_Pos (9U)
3619#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3620#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3621#define CAN_F7R1_FB10_Pos (10U)
3622#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3623#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3624#define CAN_F7R1_FB11_Pos (11U)
3625#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3626#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3627#define CAN_F7R1_FB12_Pos (12U)
3628#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3629#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3630#define CAN_F7R1_FB13_Pos (13U)
3631#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3632#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3633#define CAN_F7R1_FB14_Pos (14U)
3634#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3635#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3636#define CAN_F7R1_FB15_Pos (15U)
3637#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3638#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3639#define CAN_F7R1_FB16_Pos (16U)
3640#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3641#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3642#define CAN_F7R1_FB17_Pos (17U)
3643#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3644#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3645#define CAN_F7R1_FB18_Pos (18U)
3646#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3647#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3648#define CAN_F7R1_FB19_Pos (19U)
3649#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3650#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3651#define CAN_F7R1_FB20_Pos (20U)
3652#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3653#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3654#define CAN_F7R1_FB21_Pos (21U)
3655#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3656#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3657#define CAN_F7R1_FB22_Pos (22U)
3658#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3659#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3660#define CAN_F7R1_FB23_Pos (23U)
3661#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3662#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3663#define CAN_F7R1_FB24_Pos (24U)
3664#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3665#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3666#define CAN_F7R1_FB25_Pos (25U)
3667#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3668#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3669#define CAN_F7R1_FB26_Pos (26U)
3670#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3671#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3672#define CAN_F7R1_FB27_Pos (27U)
3673#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3674#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3675#define CAN_F7R1_FB28_Pos (28U)
3676#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3677#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3678#define CAN_F7R1_FB29_Pos (29U)
3679#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3680#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3681#define CAN_F7R1_FB30_Pos (30U)
3682#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3683#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3684#define CAN_F7R1_FB31_Pos (31U)
3685#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3686#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3687
3688/******************* Bit definition for CAN_F8R1 register *******************/
3689#define CAN_F8R1_FB0_Pos (0U)
3690#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3691#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3692#define CAN_F8R1_FB1_Pos (1U)
3693#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3694#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3695#define CAN_F8R1_FB2_Pos (2U)
3696#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3697#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3698#define CAN_F8R1_FB3_Pos (3U)
3699#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3700#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3701#define CAN_F8R1_FB4_Pos (4U)
3702#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3703#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3704#define CAN_F8R1_FB5_Pos (5U)
3705#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3706#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3707#define CAN_F8R1_FB6_Pos (6U)
3708#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3709#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3710#define CAN_F8R1_FB7_Pos (7U)
3711#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3712#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3713#define CAN_F8R1_FB8_Pos (8U)
3714#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3715#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3716#define CAN_F8R1_FB9_Pos (9U)
3717#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3718#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3719#define CAN_F8R1_FB10_Pos (10U)
3720#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3721#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3722#define CAN_F8R1_FB11_Pos (11U)
3723#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3724#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3725#define CAN_F8R1_FB12_Pos (12U)
3726#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3727#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3728#define CAN_F8R1_FB13_Pos (13U)
3729#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3730#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3731#define CAN_F8R1_FB14_Pos (14U)
3732#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3733#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3734#define CAN_F8R1_FB15_Pos (15U)
3735#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3736#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3737#define CAN_F8R1_FB16_Pos (16U)
3738#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3739#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3740#define CAN_F8R1_FB17_Pos (17U)
3741#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3742#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3743#define CAN_F8R1_FB18_Pos (18U)
3744#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3745#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3746#define CAN_F8R1_FB19_Pos (19U)
3747#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3748#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3749#define CAN_F8R1_FB20_Pos (20U)
3750#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3751#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3752#define CAN_F8R1_FB21_Pos (21U)
3753#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3754#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3755#define CAN_F8R1_FB22_Pos (22U)
3756#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3757#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3758#define CAN_F8R1_FB23_Pos (23U)
3759#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3760#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3761#define CAN_F8R1_FB24_Pos (24U)
3762#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3763#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3764#define CAN_F8R1_FB25_Pos (25U)
3765#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3766#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3767#define CAN_F8R1_FB26_Pos (26U)
3768#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3769#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3770#define CAN_F8R1_FB27_Pos (27U)
3771#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3772#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3773#define CAN_F8R1_FB28_Pos (28U)
3774#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3775#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3776#define CAN_F8R1_FB29_Pos (29U)
3777#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3778#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3779#define CAN_F8R1_FB30_Pos (30U)
3780#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3781#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3782#define CAN_F8R1_FB31_Pos (31U)
3783#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3784#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3785
3786/******************* Bit definition for CAN_F9R1 register *******************/
3787#define CAN_F9R1_FB0_Pos (0U)
3788#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3789#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3790#define CAN_F9R1_FB1_Pos (1U)
3791#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3792#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
3793#define CAN_F9R1_FB2_Pos (2U)
3794#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
3795#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
3796#define CAN_F9R1_FB3_Pos (3U)
3797#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
3798#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
3799#define CAN_F9R1_FB4_Pos (4U)
3800#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
3801#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
3802#define CAN_F9R1_FB5_Pos (5U)
3803#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
3804#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
3805#define CAN_F9R1_FB6_Pos (6U)
3806#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
3807#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
3808#define CAN_F9R1_FB7_Pos (7U)
3809#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
3810#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
3811#define CAN_F9R1_FB8_Pos (8U)
3812#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
3813#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
3814#define CAN_F9R1_FB9_Pos (9U)
3815#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
3816#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
3817#define CAN_F9R1_FB10_Pos (10U)
3818#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
3819#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
3820#define CAN_F9R1_FB11_Pos (11U)
3821#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
3822#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
3823#define CAN_F9R1_FB12_Pos (12U)
3824#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
3825#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
3826#define CAN_F9R1_FB13_Pos (13U)
3827#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
3828#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
3829#define CAN_F9R1_FB14_Pos (14U)
3830#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
3831#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
3832#define CAN_F9R1_FB15_Pos (15U)
3833#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
3834#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
3835#define CAN_F9R1_FB16_Pos (16U)
3836#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
3837#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
3838#define CAN_F9R1_FB17_Pos (17U)
3839#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
3840#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
3841#define CAN_F9R1_FB18_Pos (18U)
3842#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
3843#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
3844#define CAN_F9R1_FB19_Pos (19U)
3845#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
3846#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
3847#define CAN_F9R1_FB20_Pos (20U)
3848#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
3849#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
3850#define CAN_F9R1_FB21_Pos (21U)
3851#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
3852#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
3853#define CAN_F9R1_FB22_Pos (22U)
3854#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
3855#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
3856#define CAN_F9R1_FB23_Pos (23U)
3857#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
3858#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
3859#define CAN_F9R1_FB24_Pos (24U)
3860#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
3861#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
3862#define CAN_F9R1_FB25_Pos (25U)
3863#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
3864#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
3865#define CAN_F9R1_FB26_Pos (26U)
3866#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
3867#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
3868#define CAN_F9R1_FB27_Pos (27U)
3869#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
3870#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
3871#define CAN_F9R1_FB28_Pos (28U)
3872#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
3873#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
3874#define CAN_F9R1_FB29_Pos (29U)
3875#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
3876#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
3877#define CAN_F9R1_FB30_Pos (30U)
3878#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
3879#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
3880#define CAN_F9R1_FB31_Pos (31U)
3881#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
3882#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
3883
3884/******************* Bit definition for CAN_F10R1 register ******************/
3885#define CAN_F10R1_FB0_Pos (0U)
3886#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
3887#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
3888#define CAN_F10R1_FB1_Pos (1U)
3889#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
3890#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
3891#define CAN_F10R1_FB2_Pos (2U)
3892#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
3893#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
3894#define CAN_F10R1_FB3_Pos (3U)
3895#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
3896#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
3897#define CAN_F10R1_FB4_Pos (4U)
3898#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
3899#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
3900#define CAN_F10R1_FB5_Pos (5U)
3901#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
3902#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
3903#define CAN_F10R1_FB6_Pos (6U)
3904#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
3905#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
3906#define CAN_F10R1_FB7_Pos (7U)
3907#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
3908#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
3909#define CAN_F10R1_FB8_Pos (8U)
3910#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
3911#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
3912#define CAN_F10R1_FB9_Pos (9U)
3913#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
3914#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
3915#define CAN_F10R1_FB10_Pos (10U)
3916#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
3917#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
3918#define CAN_F10R1_FB11_Pos (11U)
3919#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
3920#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
3921#define CAN_F10R1_FB12_Pos (12U)
3922#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
3923#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
3924#define CAN_F10R1_FB13_Pos (13U)
3925#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
3926#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
3927#define CAN_F10R1_FB14_Pos (14U)
3928#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
3929#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
3930#define CAN_F10R1_FB15_Pos (15U)
3931#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
3932#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
3933#define CAN_F10R1_FB16_Pos (16U)
3934#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
3935#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
3936#define CAN_F10R1_FB17_Pos (17U)
3937#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
3938#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
3939#define CAN_F10R1_FB18_Pos (18U)
3940#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
3941#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
3942#define CAN_F10R1_FB19_Pos (19U)
3943#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
3944#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
3945#define CAN_F10R1_FB20_Pos (20U)
3946#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
3947#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
3948#define CAN_F10R1_FB21_Pos (21U)
3949#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
3950#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
3951#define CAN_F10R1_FB22_Pos (22U)
3952#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
3953#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
3954#define CAN_F10R1_FB23_Pos (23U)
3955#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
3956#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
3957#define CAN_F10R1_FB24_Pos (24U)
3958#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
3959#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
3960#define CAN_F10R1_FB25_Pos (25U)
3961#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
3962#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
3963#define CAN_F10R1_FB26_Pos (26U)
3964#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
3965#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
3966#define CAN_F10R1_FB27_Pos (27U)
3967#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
3968#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
3969#define CAN_F10R1_FB28_Pos (28U)
3970#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
3971#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
3972#define CAN_F10R1_FB29_Pos (29U)
3973#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
3974#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
3975#define CAN_F10R1_FB30_Pos (30U)
3976#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
3977#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
3978#define CAN_F10R1_FB31_Pos (31U)
3979#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
3980#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
3981
3982/******************* Bit definition for CAN_F11R1 register ******************/
3983#define CAN_F11R1_FB0_Pos (0U)
3984#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
3985#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
3986#define CAN_F11R1_FB1_Pos (1U)
3987#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
3988#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
3989#define CAN_F11R1_FB2_Pos (2U)
3990#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
3991#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
3992#define CAN_F11R1_FB3_Pos (3U)
3993#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
3994#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
3995#define CAN_F11R1_FB4_Pos (4U)
3996#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
3997#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
3998#define CAN_F11R1_FB5_Pos (5U)
3999#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
4000#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
4001#define CAN_F11R1_FB6_Pos (6U)
4002#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
4003#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
4004#define CAN_F11R1_FB7_Pos (7U)
4005#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
4006#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
4007#define CAN_F11R1_FB8_Pos (8U)
4008#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
4009#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
4010#define CAN_F11R1_FB9_Pos (9U)
4011#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
4012#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
4013#define CAN_F11R1_FB10_Pos (10U)
4014#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
4015#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
4016#define CAN_F11R1_FB11_Pos (11U)
4017#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
4018#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
4019#define CAN_F11R1_FB12_Pos (12U)
4020#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
4021#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
4022#define CAN_F11R1_FB13_Pos (13U)
4023#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
4024#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
4025#define CAN_F11R1_FB14_Pos (14U)
4026#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
4027#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
4028#define CAN_F11R1_FB15_Pos (15U)
4029#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
4030#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
4031#define CAN_F11R1_FB16_Pos (16U)
4032#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
4033#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
4034#define CAN_F11R1_FB17_Pos (17U)
4035#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
4036#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
4037#define CAN_F11R1_FB18_Pos (18U)
4038#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
4039#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
4040#define CAN_F11R1_FB19_Pos (19U)
4041#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
4042#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
4043#define CAN_F11R1_FB20_Pos (20U)
4044#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
4045#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
4046#define CAN_F11R1_FB21_Pos (21U)
4047#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
4048#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
4049#define CAN_F11R1_FB22_Pos (22U)
4050#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
4051#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
4052#define CAN_F11R1_FB23_Pos (23U)
4053#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
4054#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
4055#define CAN_F11R1_FB24_Pos (24U)
4056#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
4057#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
4058#define CAN_F11R1_FB25_Pos (25U)
4059#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
4060#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
4061#define CAN_F11R1_FB26_Pos (26U)
4062#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
4063#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
4064#define CAN_F11R1_FB27_Pos (27U)
4065#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
4066#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
4067#define CAN_F11R1_FB28_Pos (28U)
4068#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
4069#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
4070#define CAN_F11R1_FB29_Pos (29U)
4071#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
4072#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
4073#define CAN_F11R1_FB30_Pos (30U)
4074#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
4075#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
4076#define CAN_F11R1_FB31_Pos (31U)
4077#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
4078#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
4079
4080/******************* Bit definition for CAN_F12R1 register ******************/
4081#define CAN_F12R1_FB0_Pos (0U)
4082#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
4083#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
4084#define CAN_F12R1_FB1_Pos (1U)
4085#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
4086#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
4087#define CAN_F12R1_FB2_Pos (2U)
4088#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
4089#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
4090#define CAN_F12R1_FB3_Pos (3U)
4091#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
4092#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
4093#define CAN_F12R1_FB4_Pos (4U)
4094#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
4095#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
4096#define CAN_F12R1_FB5_Pos (5U)
4097#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
4098#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
4099#define CAN_F12R1_FB6_Pos (6U)
4100#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
4101#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
4102#define CAN_F12R1_FB7_Pos (7U)
4103#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
4104#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
4105#define CAN_F12R1_FB8_Pos (8U)
4106#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
4107#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
4108#define CAN_F12R1_FB9_Pos (9U)
4109#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
4110#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
4111#define CAN_F12R1_FB10_Pos (10U)
4112#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
4113#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
4114#define CAN_F12R1_FB11_Pos (11U)
4115#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
4116#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
4117#define CAN_F12R1_FB12_Pos (12U)
4118#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
4119#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
4120#define CAN_F12R1_FB13_Pos (13U)
4121#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
4122#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
4123#define CAN_F12R1_FB14_Pos (14U)
4124#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
4125#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
4126#define CAN_F12R1_FB15_Pos (15U)
4127#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
4128#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
4129#define CAN_F12R1_FB16_Pos (16U)
4130#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
4131#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
4132#define CAN_F12R1_FB17_Pos (17U)
4133#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
4134#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
4135#define CAN_F12R1_FB18_Pos (18U)
4136#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
4137#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
4138#define CAN_F12R1_FB19_Pos (19U)
4139#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
4140#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
4141#define CAN_F12R1_FB20_Pos (20U)
4142#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
4143#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
4144#define CAN_F12R1_FB21_Pos (21U)
4145#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
4146#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
4147#define CAN_F12R1_FB22_Pos (22U)
4148#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
4149#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
4150#define CAN_F12R1_FB23_Pos (23U)
4151#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
4152#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
4153#define CAN_F12R1_FB24_Pos (24U)
4154#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
4155#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
4156#define CAN_F12R1_FB25_Pos (25U)
4157#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
4158#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
4159#define CAN_F12R1_FB26_Pos (26U)
4160#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
4161#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
4162#define CAN_F12R1_FB27_Pos (27U)
4163#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
4164#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
4165#define CAN_F12R1_FB28_Pos (28U)
4166#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
4167#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
4168#define CAN_F12R1_FB29_Pos (29U)
4169#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
4170#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
4171#define CAN_F12R1_FB30_Pos (30U)
4172#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
4173#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
4174#define CAN_F12R1_FB31_Pos (31U)
4175#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
4176#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
4177
4178/******************* Bit definition for CAN_F13R1 register ******************/
4179#define CAN_F13R1_FB0_Pos (0U)
4180#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
4181#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
4182#define CAN_F13R1_FB1_Pos (1U)
4183#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
4184#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
4185#define CAN_F13R1_FB2_Pos (2U)
4186#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
4187#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
4188#define CAN_F13R1_FB3_Pos (3U)
4189#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
4190#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
4191#define CAN_F13R1_FB4_Pos (4U)
4192#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
4193#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
4194#define CAN_F13R1_FB5_Pos (5U)
4195#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
4196#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
4197#define CAN_F13R1_FB6_Pos (6U)
4198#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
4199#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
4200#define CAN_F13R1_FB7_Pos (7U)
4201#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
4202#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
4203#define CAN_F13R1_FB8_Pos (8U)
4204#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
4205#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
4206#define CAN_F13R1_FB9_Pos (9U)
4207#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
4208#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
4209#define CAN_F13R1_FB10_Pos (10U)
4210#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
4211#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
4212#define CAN_F13R1_FB11_Pos (11U)
4213#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
4214#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
4215#define CAN_F13R1_FB12_Pos (12U)
4216#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4217#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4218#define CAN_F13R1_FB13_Pos (13U)
4219#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4220#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4221#define CAN_F13R1_FB14_Pos (14U)
4222#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4223#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4224#define CAN_F13R1_FB15_Pos (15U)
4225#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4226#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4227#define CAN_F13R1_FB16_Pos (16U)
4228#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4229#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4230#define CAN_F13R1_FB17_Pos (17U)
4231#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4232#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4233#define CAN_F13R1_FB18_Pos (18U)
4234#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4235#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4236#define CAN_F13R1_FB19_Pos (19U)
4237#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4238#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4239#define CAN_F13R1_FB20_Pos (20U)
4240#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4241#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4242#define CAN_F13R1_FB21_Pos (21U)
4243#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4244#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4245#define CAN_F13R1_FB22_Pos (22U)
4246#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4247#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4248#define CAN_F13R1_FB23_Pos (23U)
4249#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4250#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4251#define CAN_F13R1_FB24_Pos (24U)
4252#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4253#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4254#define CAN_F13R1_FB25_Pos (25U)
4255#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4256#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4257#define CAN_F13R1_FB26_Pos (26U)
4258#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4259#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4260#define CAN_F13R1_FB27_Pos (27U)
4261#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4262#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4263#define CAN_F13R1_FB28_Pos (28U)
4264#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4265#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4266#define CAN_F13R1_FB29_Pos (29U)
4267#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4268#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4269#define CAN_F13R1_FB30_Pos (30U)
4270#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4271#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4272#define CAN_F13R1_FB31_Pos (31U)
4273#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4274#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4275
4276/******************* Bit definition for CAN_F0R2 register *******************/
4277#define CAN_F0R2_FB0_Pos (0U)
4278#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4279#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4280#define CAN_F0R2_FB1_Pos (1U)
4281#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4282#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4283#define CAN_F0R2_FB2_Pos (2U)
4284#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4285#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4286#define CAN_F0R2_FB3_Pos (3U)
4287#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4288#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4289#define CAN_F0R2_FB4_Pos (4U)
4290#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4291#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4292#define CAN_F0R2_FB5_Pos (5U)
4293#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4294#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4295#define CAN_F0R2_FB6_Pos (6U)
4296#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4297#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4298#define CAN_F0R2_FB7_Pos (7U)
4299#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4300#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4301#define CAN_F0R2_FB8_Pos (8U)
4302#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4303#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4304#define CAN_F0R2_FB9_Pos (9U)
4305#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4306#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4307#define CAN_F0R2_FB10_Pos (10U)
4308#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4309#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4310#define CAN_F0R2_FB11_Pos (11U)
4311#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4312#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4313#define CAN_F0R2_FB12_Pos (12U)
4314#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4315#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4316#define CAN_F0R2_FB13_Pos (13U)
4317#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4318#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4319#define CAN_F0R2_FB14_Pos (14U)
4320#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4321#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4322#define CAN_F0R2_FB15_Pos (15U)
4323#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4324#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4325#define CAN_F0R2_FB16_Pos (16U)
4326#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4327#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4328#define CAN_F0R2_FB17_Pos (17U)
4329#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4330#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4331#define CAN_F0R2_FB18_Pos (18U)
4332#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4333#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4334#define CAN_F0R2_FB19_Pos (19U)
4335#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4336#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4337#define CAN_F0R2_FB20_Pos (20U)
4338#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4339#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4340#define CAN_F0R2_FB21_Pos (21U)
4341#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4342#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4343#define CAN_F0R2_FB22_Pos (22U)
4344#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4345#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4346#define CAN_F0R2_FB23_Pos (23U)
4347#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4348#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4349#define CAN_F0R2_FB24_Pos (24U)
4350#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4351#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4352#define CAN_F0R2_FB25_Pos (25U)
4353#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4354#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4355#define CAN_F0R2_FB26_Pos (26U)
4356#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4357#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4358#define CAN_F0R2_FB27_Pos (27U)
4359#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4360#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4361#define CAN_F0R2_FB28_Pos (28U)
4362#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4363#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4364#define CAN_F0R2_FB29_Pos (29U)
4365#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4366#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4367#define CAN_F0R2_FB30_Pos (30U)
4368#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4369#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4370#define CAN_F0R2_FB31_Pos (31U)
4371#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4372#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4373
4374/******************* Bit definition for CAN_F1R2 register *******************/
4375#define CAN_F1R2_FB0_Pos (0U)
4376#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4377#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4378#define CAN_F1R2_FB1_Pos (1U)
4379#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4380#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4381#define CAN_F1R2_FB2_Pos (2U)
4382#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4383#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4384#define CAN_F1R2_FB3_Pos (3U)
4385#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4386#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4387#define CAN_F1R2_FB4_Pos (4U)
4388#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4389#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4390#define CAN_F1R2_FB5_Pos (5U)
4391#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4392#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4393#define CAN_F1R2_FB6_Pos (6U)
4394#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4395#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4396#define CAN_F1R2_FB7_Pos (7U)
4397#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4398#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4399#define CAN_F1R2_FB8_Pos (8U)
4400#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4401#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4402#define CAN_F1R2_FB9_Pos (9U)
4403#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4404#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4405#define CAN_F1R2_FB10_Pos (10U)
4406#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4407#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4408#define CAN_F1R2_FB11_Pos (11U)
4409#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4410#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4411#define CAN_F1R2_FB12_Pos (12U)
4412#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4413#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4414#define CAN_F1R2_FB13_Pos (13U)
4415#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4416#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4417#define CAN_F1R2_FB14_Pos (14U)
4418#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4419#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4420#define CAN_F1R2_FB15_Pos (15U)
4421#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4422#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4423#define CAN_F1R2_FB16_Pos (16U)
4424#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4425#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4426#define CAN_F1R2_FB17_Pos (17U)
4427#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4428#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4429#define CAN_F1R2_FB18_Pos (18U)
4430#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4431#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4432#define CAN_F1R2_FB19_Pos (19U)
4433#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4434#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4435#define CAN_F1R2_FB20_Pos (20U)
4436#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4437#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4438#define CAN_F1R2_FB21_Pos (21U)
4439#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4440#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4441#define CAN_F1R2_FB22_Pos (22U)
4442#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4443#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4444#define CAN_F1R2_FB23_Pos (23U)
4445#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4446#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4447#define CAN_F1R2_FB24_Pos (24U)
4448#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4449#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4450#define CAN_F1R2_FB25_Pos (25U)
4451#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4452#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4453#define CAN_F1R2_FB26_Pos (26U)
4454#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4455#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4456#define CAN_F1R2_FB27_Pos (27U)
4457#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4458#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4459#define CAN_F1R2_FB28_Pos (28U)
4460#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4461#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4462#define CAN_F1R2_FB29_Pos (29U)
4463#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4464#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4465#define CAN_F1R2_FB30_Pos (30U)
4466#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4467#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4468#define CAN_F1R2_FB31_Pos (31U)
4469#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4470#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4471
4472/******************* Bit definition for CAN_F2R2 register *******************/
4473#define CAN_F2R2_FB0_Pos (0U)
4474#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4475#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4476#define CAN_F2R2_FB1_Pos (1U)
4477#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4478#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4479#define CAN_F2R2_FB2_Pos (2U)
4480#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4481#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4482#define CAN_F2R2_FB3_Pos (3U)
4483#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4484#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4485#define CAN_F2R2_FB4_Pos (4U)
4486#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4487#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4488#define CAN_F2R2_FB5_Pos (5U)
4489#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4490#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4491#define CAN_F2R2_FB6_Pos (6U)
4492#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4493#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4494#define CAN_F2R2_FB7_Pos (7U)
4495#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4496#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4497#define CAN_F2R2_FB8_Pos (8U)
4498#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4499#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4500#define CAN_F2R2_FB9_Pos (9U)
4501#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4502#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4503#define CAN_F2R2_FB10_Pos (10U)
4504#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4505#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4506#define CAN_F2R2_FB11_Pos (11U)
4507#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4508#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4509#define CAN_F2R2_FB12_Pos (12U)
4510#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4511#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4512#define CAN_F2R2_FB13_Pos (13U)
4513#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4514#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4515#define CAN_F2R2_FB14_Pos (14U)
4516#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4517#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4518#define CAN_F2R2_FB15_Pos (15U)
4519#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4520#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4521#define CAN_F2R2_FB16_Pos (16U)
4522#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4523#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4524#define CAN_F2R2_FB17_Pos (17U)
4525#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4526#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4527#define CAN_F2R2_FB18_Pos (18U)
4528#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4529#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4530#define CAN_F2R2_FB19_Pos (19U)
4531#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4532#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4533#define CAN_F2R2_FB20_Pos (20U)
4534#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
4535#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
4536#define CAN_F2R2_FB21_Pos (21U)
4537#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
4538#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
4539#define CAN_F2R2_FB22_Pos (22U)
4540#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
4541#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
4542#define CAN_F2R2_FB23_Pos (23U)
4543#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
4544#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
4545#define CAN_F2R2_FB24_Pos (24U)
4546#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
4547#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
4548#define CAN_F2R2_FB25_Pos (25U)
4549#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
4550#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
4551#define CAN_F2R2_FB26_Pos (26U)
4552#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
4553#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
4554#define CAN_F2R2_FB27_Pos (27U)
4555#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
4556#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
4557#define CAN_F2R2_FB28_Pos (28U)
4558#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
4559#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
4560#define CAN_F2R2_FB29_Pos (29U)
4561#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
4562#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
4563#define CAN_F2R2_FB30_Pos (30U)
4564#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
4565#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
4566#define CAN_F2R2_FB31_Pos (31U)
4567#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
4568#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
4569
4570/******************* Bit definition for CAN_F3R2 register *******************/
4571#define CAN_F3R2_FB0_Pos (0U)
4572#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
4573#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
4574#define CAN_F3R2_FB1_Pos (1U)
4575#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
4576#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
4577#define CAN_F3R2_FB2_Pos (2U)
4578#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
4579#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
4580#define CAN_F3R2_FB3_Pos (3U)
4581#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
4582#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
4583#define CAN_F3R2_FB4_Pos (4U)
4584#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
4585#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
4586#define CAN_F3R2_FB5_Pos (5U)
4587#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
4588#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
4589#define CAN_F3R2_FB6_Pos (6U)
4590#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
4591#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
4592#define CAN_F3R2_FB7_Pos (7U)
4593#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
4594#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
4595#define CAN_F3R2_FB8_Pos (8U)
4596#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
4597#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
4598#define CAN_F3R2_FB9_Pos (9U)
4599#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
4600#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
4601#define CAN_F3R2_FB10_Pos (10U)
4602#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
4603#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
4604#define CAN_F3R2_FB11_Pos (11U)
4605#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
4606#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
4607#define CAN_F3R2_FB12_Pos (12U)
4608#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
4609#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
4610#define CAN_F3R2_FB13_Pos (13U)
4611#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
4612#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
4613#define CAN_F3R2_FB14_Pos (14U)
4614#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
4615#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
4616#define CAN_F3R2_FB15_Pos (15U)
4617#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
4618#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
4619#define CAN_F3R2_FB16_Pos (16U)
4620#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
4621#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
4622#define CAN_F3R2_FB17_Pos (17U)
4623#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
4624#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
4625#define CAN_F3R2_FB18_Pos (18U)
4626#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
4627#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
4628#define CAN_F3R2_FB19_Pos (19U)
4629#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
4630#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
4631#define CAN_F3R2_FB20_Pos (20U)
4632#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
4633#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
4634#define CAN_F3R2_FB21_Pos (21U)
4635#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
4636#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
4637#define CAN_F3R2_FB22_Pos (22U)
4638#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
4639#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
4640#define CAN_F3R2_FB23_Pos (23U)
4641#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
4642#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
4643#define CAN_F3R2_FB24_Pos (24U)
4644#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
4645#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
4646#define CAN_F3R2_FB25_Pos (25U)
4647#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
4648#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
4649#define CAN_F3R2_FB26_Pos (26U)
4650#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
4651#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
4652#define CAN_F3R2_FB27_Pos (27U)
4653#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
4654#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
4655#define CAN_F3R2_FB28_Pos (28U)
4656#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
4657#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
4658#define CAN_F3R2_FB29_Pos (29U)
4659#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
4660#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
4661#define CAN_F3R2_FB30_Pos (30U)
4662#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
4663#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
4664#define CAN_F3R2_FB31_Pos (31U)
4665#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
4666#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
4667
4668/******************* Bit definition for CAN_F4R2 register *******************/
4669#define CAN_F4R2_FB0_Pos (0U)
4670#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
4671#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
4672#define CAN_F4R2_FB1_Pos (1U)
4673#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
4674#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
4675#define CAN_F4R2_FB2_Pos (2U)
4676#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
4677#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
4678#define CAN_F4R2_FB3_Pos (3U)
4679#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
4680#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
4681#define CAN_F4R2_FB4_Pos (4U)
4682#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
4683#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
4684#define CAN_F4R2_FB5_Pos (5U)
4685#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
4686#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
4687#define CAN_F4R2_FB6_Pos (6U)
4688#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
4689#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
4690#define CAN_F4R2_FB7_Pos (7U)
4691#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
4692#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
4693#define CAN_F4R2_FB8_Pos (8U)
4694#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
4695#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
4696#define CAN_F4R2_FB9_Pos (9U)
4697#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
4698#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
4699#define CAN_F4R2_FB10_Pos (10U)
4700#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
4701#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
4702#define CAN_F4R2_FB11_Pos (11U)
4703#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
4704#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
4705#define CAN_F4R2_FB12_Pos (12U)
4706#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
4707#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
4708#define CAN_F4R2_FB13_Pos (13U)
4709#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
4710#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
4711#define CAN_F4R2_FB14_Pos (14U)
4712#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
4713#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
4714#define CAN_F4R2_FB15_Pos (15U)
4715#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
4716#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
4717#define CAN_F4R2_FB16_Pos (16U)
4718#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
4719#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
4720#define CAN_F4R2_FB17_Pos (17U)
4721#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
4722#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
4723#define CAN_F4R2_FB18_Pos (18U)
4724#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
4725#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
4726#define CAN_F4R2_FB19_Pos (19U)
4727#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
4728#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
4729#define CAN_F4R2_FB20_Pos (20U)
4730#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
4731#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
4732#define CAN_F4R2_FB21_Pos (21U)
4733#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
4734#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
4735#define CAN_F4R2_FB22_Pos (22U)
4736#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
4737#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
4738#define CAN_F4R2_FB23_Pos (23U)
4739#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
4740#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
4741#define CAN_F4R2_FB24_Pos (24U)
4742#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
4743#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
4744#define CAN_F4R2_FB25_Pos (25U)
4745#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
4746#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
4747#define CAN_F4R2_FB26_Pos (26U)
4748#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
4749#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
4750#define CAN_F4R2_FB27_Pos (27U)
4751#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
4752#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
4753#define CAN_F4R2_FB28_Pos (28U)
4754#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
4755#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
4756#define CAN_F4R2_FB29_Pos (29U)
4757#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
4758#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
4759#define CAN_F4R2_FB30_Pos (30U)
4760#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
4761#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
4762#define CAN_F4R2_FB31_Pos (31U)
4763#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
4764#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
4765
4766/******************* Bit definition for CAN_F5R2 register *******************/
4767#define CAN_F5R2_FB0_Pos (0U)
4768#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
4769#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
4770#define CAN_F5R2_FB1_Pos (1U)
4771#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
4772#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
4773#define CAN_F5R2_FB2_Pos (2U)
4774#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
4775#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
4776#define CAN_F5R2_FB3_Pos (3U)
4777#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
4778#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
4779#define CAN_F5R2_FB4_Pos (4U)
4780#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
4781#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
4782#define CAN_F5R2_FB5_Pos (5U)
4783#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
4784#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
4785#define CAN_F5R2_FB6_Pos (6U)
4786#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
4787#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
4788#define CAN_F5R2_FB7_Pos (7U)
4789#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
4790#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
4791#define CAN_F5R2_FB8_Pos (8U)
4792#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
4793#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
4794#define CAN_F5R2_FB9_Pos (9U)
4795#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
4796#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
4797#define CAN_F5R2_FB10_Pos (10U)
4798#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
4799#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
4800#define CAN_F5R2_FB11_Pos (11U)
4801#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
4802#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
4803#define CAN_F5R2_FB12_Pos (12U)
4804#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
4805#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
4806#define CAN_F5R2_FB13_Pos (13U)
4807#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
4808#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
4809#define CAN_F5R2_FB14_Pos (14U)
4810#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
4811#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
4812#define CAN_F5R2_FB15_Pos (15U)
4813#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
4814#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
4815#define CAN_F5R2_FB16_Pos (16U)
4816#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
4817#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
4818#define CAN_F5R2_FB17_Pos (17U)
4819#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
4820#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
4821#define CAN_F5R2_FB18_Pos (18U)
4822#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
4823#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
4824#define CAN_F5R2_FB19_Pos (19U)
4825#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
4826#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
4827#define CAN_F5R2_FB20_Pos (20U)
4828#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
4829#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
4830#define CAN_F5R2_FB21_Pos (21U)
4831#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
4832#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
4833#define CAN_F5R2_FB22_Pos (22U)
4834#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
4835#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
4836#define CAN_F5R2_FB23_Pos (23U)
4837#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
4838#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
4839#define CAN_F5R2_FB24_Pos (24U)
4840#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
4841#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
4842#define CAN_F5R2_FB25_Pos (25U)
4843#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
4844#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
4845#define CAN_F5R2_FB26_Pos (26U)
4846#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
4847#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
4848#define CAN_F5R2_FB27_Pos (27U)
4849#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
4850#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
4851#define CAN_F5R2_FB28_Pos (28U)
4852#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
4853#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
4854#define CAN_F5R2_FB29_Pos (29U)
4855#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
4856#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
4857#define CAN_F5R2_FB30_Pos (30U)
4858#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
4859#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
4860#define CAN_F5R2_FB31_Pos (31U)
4861#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
4862#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
4863
4864/******************* Bit definition for CAN_F6R2 register *******************/
4865#define CAN_F6R2_FB0_Pos (0U)
4866#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
4867#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
4868#define CAN_F6R2_FB1_Pos (1U)
4869#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
4870#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
4871#define CAN_F6R2_FB2_Pos (2U)
4872#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
4873#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
4874#define CAN_F6R2_FB3_Pos (3U)
4875#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
4876#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
4877#define CAN_F6R2_FB4_Pos (4U)
4878#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
4879#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
4880#define CAN_F6R2_FB5_Pos (5U)
4881#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
4882#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
4883#define CAN_F6R2_FB6_Pos (6U)
4884#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
4885#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
4886#define CAN_F6R2_FB7_Pos (7U)
4887#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
4888#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
4889#define CAN_F6R2_FB8_Pos (8U)
4890#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
4891#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
4892#define CAN_F6R2_FB9_Pos (9U)
4893#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
4894#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
4895#define CAN_F6R2_FB10_Pos (10U)
4896#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
4897#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
4898#define CAN_F6R2_FB11_Pos (11U)
4899#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
4900#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
4901#define CAN_F6R2_FB12_Pos (12U)
4902#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
4903#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
4904#define CAN_F6R2_FB13_Pos (13U)
4905#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
4906#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
4907#define CAN_F6R2_FB14_Pos (14U)
4908#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
4909#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
4910#define CAN_F6R2_FB15_Pos (15U)
4911#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
4912#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
4913#define CAN_F6R2_FB16_Pos (16U)
4914#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
4915#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
4916#define CAN_F6R2_FB17_Pos (17U)
4917#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
4918#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
4919#define CAN_F6R2_FB18_Pos (18U)
4920#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
4921#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
4922#define CAN_F6R2_FB19_Pos (19U)
4923#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
4924#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
4925#define CAN_F6R2_FB20_Pos (20U)
4926#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
4927#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
4928#define CAN_F6R2_FB21_Pos (21U)
4929#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
4930#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
4931#define CAN_F6R2_FB22_Pos (22U)
4932#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
4933#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
4934#define CAN_F6R2_FB23_Pos (23U)
4935#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
4936#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
4937#define CAN_F6R2_FB24_Pos (24U)
4938#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
4939#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
4940#define CAN_F6R2_FB25_Pos (25U)
4941#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
4942#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
4943#define CAN_F6R2_FB26_Pos (26U)
4944#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
4945#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
4946#define CAN_F6R2_FB27_Pos (27U)
4947#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
4948#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
4949#define CAN_F6R2_FB28_Pos (28U)
4950#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
4951#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
4952#define CAN_F6R2_FB29_Pos (29U)
4953#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
4954#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
4955#define CAN_F6R2_FB30_Pos (30U)
4956#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
4957#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
4958#define CAN_F6R2_FB31_Pos (31U)
4959#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
4960#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
4961
4962/******************* Bit definition for CAN_F7R2 register *******************/
4963#define CAN_F7R2_FB0_Pos (0U)
4964#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
4965#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
4966#define CAN_F7R2_FB1_Pos (1U)
4967#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
4968#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
4969#define CAN_F7R2_FB2_Pos (2U)
4970#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
4971#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
4972#define CAN_F7R2_FB3_Pos (3U)
4973#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
4974#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
4975#define CAN_F7R2_FB4_Pos (4U)
4976#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
4977#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
4978#define CAN_F7R2_FB5_Pos (5U)
4979#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
4980#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
4981#define CAN_F7R2_FB6_Pos (6U)
4982#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
4983#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
4984#define CAN_F7R2_FB7_Pos (7U)
4985#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
4986#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
4987#define CAN_F7R2_FB8_Pos (8U)
4988#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
4989#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
4990#define CAN_F7R2_FB9_Pos (9U)
4991#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
4992#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
4993#define CAN_F7R2_FB10_Pos (10U)
4994#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
4995#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
4996#define CAN_F7R2_FB11_Pos (11U)
4997#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
4998#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
4999#define CAN_F7R2_FB12_Pos (12U)
5000#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
5001#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
5002#define CAN_F7R2_FB13_Pos (13U)
5003#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
5004#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
5005#define CAN_F7R2_FB14_Pos (14U)
5006#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
5007#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
5008#define CAN_F7R2_FB15_Pos (15U)
5009#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
5010#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
5011#define CAN_F7R2_FB16_Pos (16U)
5012#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
5013#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
5014#define CAN_F7R2_FB17_Pos (17U)
5015#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
5016#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
5017#define CAN_F7R2_FB18_Pos (18U)
5018#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
5019#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
5020#define CAN_F7R2_FB19_Pos (19U)
5021#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
5022#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
5023#define CAN_F7R2_FB20_Pos (20U)
5024#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
5025#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
5026#define CAN_F7R2_FB21_Pos (21U)
5027#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
5028#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
5029#define CAN_F7R2_FB22_Pos (22U)
5030#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
5031#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
5032#define CAN_F7R2_FB23_Pos (23U)
5033#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
5034#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
5035#define CAN_F7R2_FB24_Pos (24U)
5036#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
5037#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
5038#define CAN_F7R2_FB25_Pos (25U)
5039#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
5040#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
5041#define CAN_F7R2_FB26_Pos (26U)
5042#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
5043#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
5044#define CAN_F7R2_FB27_Pos (27U)
5045#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
5046#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
5047#define CAN_F7R2_FB28_Pos (28U)
5048#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
5049#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
5050#define CAN_F7R2_FB29_Pos (29U)
5051#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
5052#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
5053#define CAN_F7R2_FB30_Pos (30U)
5054#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
5055#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
5056#define CAN_F7R2_FB31_Pos (31U)
5057#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
5058#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
5059
5060/******************* Bit definition for CAN_F8R2 register *******************/
5061#define CAN_F8R2_FB0_Pos (0U)
5062#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
5063#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
5064#define CAN_F8R2_FB1_Pos (1U)
5065#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
5066#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
5067#define CAN_F8R2_FB2_Pos (2U)
5068#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
5069#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
5070#define CAN_F8R2_FB3_Pos (3U)
5071#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
5072#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
5073#define CAN_F8R2_FB4_Pos (4U)
5074#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
5075#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
5076#define CAN_F8R2_FB5_Pos (5U)
5077#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
5078#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
5079#define CAN_F8R2_FB6_Pos (6U)
5080#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
5081#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
5082#define CAN_F8R2_FB7_Pos (7U)
5083#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
5084#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
5085#define CAN_F8R2_FB8_Pos (8U)
5086#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
5087#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
5088#define CAN_F8R2_FB9_Pos (9U)
5089#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
5090#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
5091#define CAN_F8R2_FB10_Pos (10U)
5092#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
5093#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
5094#define CAN_F8R2_FB11_Pos (11U)
5095#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
5096#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
5097#define CAN_F8R2_FB12_Pos (12U)
5098#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
5099#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
5100#define CAN_F8R2_FB13_Pos (13U)
5101#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
5102#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
5103#define CAN_F8R2_FB14_Pos (14U)
5104#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
5105#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
5106#define CAN_F8R2_FB15_Pos (15U)
5107#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
5108#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
5109#define CAN_F8R2_FB16_Pos (16U)
5110#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
5111#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
5112#define CAN_F8R2_FB17_Pos (17U)
5113#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
5114#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
5115#define CAN_F8R2_FB18_Pos (18U)
5116#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
5117#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
5118#define CAN_F8R2_FB19_Pos (19U)
5119#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
5120#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
5121#define CAN_F8R2_FB20_Pos (20U)
5122#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
5123#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
5124#define CAN_F8R2_FB21_Pos (21U)
5125#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
5126#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
5127#define CAN_F8R2_FB22_Pos (22U)
5128#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
5129#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
5130#define CAN_F8R2_FB23_Pos (23U)
5131#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
5132#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
5133#define CAN_F8R2_FB24_Pos (24U)
5134#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
5135#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
5136#define CAN_F8R2_FB25_Pos (25U)
5137#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
5138#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
5139#define CAN_F8R2_FB26_Pos (26U)
5140#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
5141#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
5142#define CAN_F8R2_FB27_Pos (27U)
5143#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
5144#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
5145#define CAN_F8R2_FB28_Pos (28U)
5146#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
5147#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
5148#define CAN_F8R2_FB29_Pos (29U)
5149#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
5150#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
5151#define CAN_F8R2_FB30_Pos (30U)
5152#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
5153#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
5154#define CAN_F8R2_FB31_Pos (31U)
5155#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
5156#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
5157
5158/******************* Bit definition for CAN_F9R2 register *******************/
5159#define CAN_F9R2_FB0_Pos (0U)
5160#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
5161#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
5162#define CAN_F9R2_FB1_Pos (1U)
5163#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
5164#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
5165#define CAN_F9R2_FB2_Pos (2U)
5166#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
5167#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
5168#define CAN_F9R2_FB3_Pos (3U)
5169#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
5170#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
5171#define CAN_F9R2_FB4_Pos (4U)
5172#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
5173#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
5174#define CAN_F9R2_FB5_Pos (5U)
5175#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
5176#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
5177#define CAN_F9R2_FB6_Pos (6U)
5178#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
5179#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
5180#define CAN_F9R2_FB7_Pos (7U)
5181#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
5182#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
5183#define CAN_F9R2_FB8_Pos (8U)
5184#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
5185#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
5186#define CAN_F9R2_FB9_Pos (9U)
5187#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
5188#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
5189#define CAN_F9R2_FB10_Pos (10U)
5190#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
5191#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
5192#define CAN_F9R2_FB11_Pos (11U)
5193#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
5194#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
5195#define CAN_F9R2_FB12_Pos (12U)
5196#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
5197#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
5198#define CAN_F9R2_FB13_Pos (13U)
5199#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
5200#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
5201#define CAN_F9R2_FB14_Pos (14U)
5202#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
5203#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
5204#define CAN_F9R2_FB15_Pos (15U)
5205#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
5206#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
5207#define CAN_F9R2_FB16_Pos (16U)
5208#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
5209#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
5210#define CAN_F9R2_FB17_Pos (17U)
5211#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
5212#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
5213#define CAN_F9R2_FB18_Pos (18U)
5214#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
5215#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
5216#define CAN_F9R2_FB19_Pos (19U)
5217#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5218#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5219#define CAN_F9R2_FB20_Pos (20U)
5220#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5221#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5222#define CAN_F9R2_FB21_Pos (21U)
5223#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5224#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5225#define CAN_F9R2_FB22_Pos (22U)
5226#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5227#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5228#define CAN_F9R2_FB23_Pos (23U)
5229#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5230#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5231#define CAN_F9R2_FB24_Pos (24U)
5232#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5233#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5234#define CAN_F9R2_FB25_Pos (25U)
5235#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5236#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5237#define CAN_F9R2_FB26_Pos (26U)
5238#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5239#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5240#define CAN_F9R2_FB27_Pos (27U)
5241#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5242#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5243#define CAN_F9R2_FB28_Pos (28U)
5244#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5245#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5246#define CAN_F9R2_FB29_Pos (29U)
5247#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5248#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5249#define CAN_F9R2_FB30_Pos (30U)
5250#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5251#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5252#define CAN_F9R2_FB31_Pos (31U)
5253#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5254#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5255
5256/******************* Bit definition for CAN_F10R2 register ******************/
5257#define CAN_F10R2_FB0_Pos (0U)
5258#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5259#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5260#define CAN_F10R2_FB1_Pos (1U)
5261#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5262#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5263#define CAN_F10R2_FB2_Pos (2U)
5264#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5265#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5266#define CAN_F10R2_FB3_Pos (3U)
5267#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5268#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5269#define CAN_F10R2_FB4_Pos (4U)
5270#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5271#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5272#define CAN_F10R2_FB5_Pos (5U)
5273#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5274#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5275#define CAN_F10R2_FB6_Pos (6U)
5276#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5277#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5278#define CAN_F10R2_FB7_Pos (7U)
5279#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5280#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5281#define CAN_F10R2_FB8_Pos (8U)
5282#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5283#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5284#define CAN_F10R2_FB9_Pos (9U)
5285#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5286#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5287#define CAN_F10R2_FB10_Pos (10U)
5288#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5289#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5290#define CAN_F10R2_FB11_Pos (11U)
5291#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5292#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5293#define CAN_F10R2_FB12_Pos (12U)
5294#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5295#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5296#define CAN_F10R2_FB13_Pos (13U)
5297#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5298#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5299#define CAN_F10R2_FB14_Pos (14U)
5300#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5301#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5302#define CAN_F10R2_FB15_Pos (15U)
5303#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5304#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5305#define CAN_F10R2_FB16_Pos (16U)
5306#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5307#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5308#define CAN_F10R2_FB17_Pos (17U)
5309#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5310#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5311#define CAN_F10R2_FB18_Pos (18U)
5312#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5313#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5314#define CAN_F10R2_FB19_Pos (19U)
5315#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5316#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5317#define CAN_F10R2_FB20_Pos (20U)
5318#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5319#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5320#define CAN_F10R2_FB21_Pos (21U)
5321#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5322#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5323#define CAN_F10R2_FB22_Pos (22U)
5324#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5325#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5326#define CAN_F10R2_FB23_Pos (23U)
5327#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5328#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5329#define CAN_F10R2_FB24_Pos (24U)
5330#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5331#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5332#define CAN_F10R2_FB25_Pos (25U)
5333#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5334#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5335#define CAN_F10R2_FB26_Pos (26U)
5336#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5337#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5338#define CAN_F10R2_FB27_Pos (27U)
5339#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5340#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5341#define CAN_F10R2_FB28_Pos (28U)
5342#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5343#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5344#define CAN_F10R2_FB29_Pos (29U)
5345#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5346#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5347#define CAN_F10R2_FB30_Pos (30U)
5348#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5349#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5350#define CAN_F10R2_FB31_Pos (31U)
5351#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5352#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5353
5354/******************* Bit definition for CAN_F11R2 register ******************/
5355#define CAN_F11R2_FB0_Pos (0U)
5356#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5357#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5358#define CAN_F11R2_FB1_Pos (1U)
5359#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5360#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5361#define CAN_F11R2_FB2_Pos (2U)
5362#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5363#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5364#define CAN_F11R2_FB3_Pos (3U)
5365#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5366#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5367#define CAN_F11R2_FB4_Pos (4U)
5368#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5369#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5370#define CAN_F11R2_FB5_Pos (5U)
5371#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5372#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5373#define CAN_F11R2_FB6_Pos (6U)
5374#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5375#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5376#define CAN_F11R2_FB7_Pos (7U)
5377#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5378#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5379#define CAN_F11R2_FB8_Pos (8U)
5380#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5381#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5382#define CAN_F11R2_FB9_Pos (9U)
5383#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5384#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5385#define CAN_F11R2_FB10_Pos (10U)
5386#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5387#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5388#define CAN_F11R2_FB11_Pos (11U)
5389#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5390#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5391#define CAN_F11R2_FB12_Pos (12U)
5392#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5393#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5394#define CAN_F11R2_FB13_Pos (13U)
5395#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5396#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5397#define CAN_F11R2_FB14_Pos (14U)
5398#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5399#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5400#define CAN_F11R2_FB15_Pos (15U)
5401#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5402#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5403#define CAN_F11R2_FB16_Pos (16U)
5404#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5405#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5406#define CAN_F11R2_FB17_Pos (17U)
5407#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5408#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5409#define CAN_F11R2_FB18_Pos (18U)
5410#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5411#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5412#define CAN_F11R2_FB19_Pos (19U)
5413#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5414#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5415#define CAN_F11R2_FB20_Pos (20U)
5416#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5417#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5418#define CAN_F11R2_FB21_Pos (21U)
5419#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5420#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5421#define CAN_F11R2_FB22_Pos (22U)
5422#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5423#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5424#define CAN_F11R2_FB23_Pos (23U)
5425#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5426#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5427#define CAN_F11R2_FB24_Pos (24U)
5428#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5429#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5430#define CAN_F11R2_FB25_Pos (25U)
5431#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5432#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5433#define CAN_F11R2_FB26_Pos (26U)
5434#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5435#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5436#define CAN_F11R2_FB27_Pos (27U)
5437#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5438#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5439#define CAN_F11R2_FB28_Pos (28U)
5440#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5441#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5442#define CAN_F11R2_FB29_Pos (29U)
5443#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5444#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5445#define CAN_F11R2_FB30_Pos (30U)
5446#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5447#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5448#define CAN_F11R2_FB31_Pos (31U)
5449#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5450#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5451
5452/******************* Bit definition for CAN_F12R2 register ******************/
5453#define CAN_F12R2_FB0_Pos (0U)
5454#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5455#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5456#define CAN_F12R2_FB1_Pos (1U)
5457#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5458#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5459#define CAN_F12R2_FB2_Pos (2U)
5460#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5461#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5462#define CAN_F12R2_FB3_Pos (3U)
5463#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5464#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5465#define CAN_F12R2_FB4_Pos (4U)
5466#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5467#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5468#define CAN_F12R2_FB5_Pos (5U)
5469#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5470#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5471#define CAN_F12R2_FB6_Pos (6U)
5472#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5473#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5474#define CAN_F12R2_FB7_Pos (7U)
5475#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5476#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5477#define CAN_F12R2_FB8_Pos (8U)
5478#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5479#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5480#define CAN_F12R2_FB9_Pos (9U)
5481#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5482#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5483#define CAN_F12R2_FB10_Pos (10U)
5484#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5485#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5486#define CAN_F12R2_FB11_Pos (11U)
5487#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5488#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5489#define CAN_F12R2_FB12_Pos (12U)
5490#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5491#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5492#define CAN_F12R2_FB13_Pos (13U)
5493#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5494#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5495#define CAN_F12R2_FB14_Pos (14U)
5496#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5497#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5498#define CAN_F12R2_FB15_Pos (15U)
5499#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5500#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5501#define CAN_F12R2_FB16_Pos (16U)
5502#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5503#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5504#define CAN_F12R2_FB17_Pos (17U)
5505#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5506#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5507#define CAN_F12R2_FB18_Pos (18U)
5508#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5509#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5510#define CAN_F12R2_FB19_Pos (19U)
5511#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5512#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5513#define CAN_F12R2_FB20_Pos (20U)
5514#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5515#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5516#define CAN_F12R2_FB21_Pos (21U)
5517#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5518#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5519#define CAN_F12R2_FB22_Pos (22U)
5520#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5521#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5522#define CAN_F12R2_FB23_Pos (23U)
5523#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5524#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5525#define CAN_F12R2_FB24_Pos (24U)
5526#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5527#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5528#define CAN_F12R2_FB25_Pos (25U)
5529#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5530#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5531#define CAN_F12R2_FB26_Pos (26U)
5532#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5533#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
5534#define CAN_F12R2_FB27_Pos (27U)
5535#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
5536#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
5537#define CAN_F12R2_FB28_Pos (28U)
5538#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
5539#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
5540#define CAN_F12R2_FB29_Pos (29U)
5541#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
5542#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
5543#define CAN_F12R2_FB30_Pos (30U)
5544#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
5545#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
5546#define CAN_F12R2_FB31_Pos (31U)
5547#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
5548#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
5549
5550/******************* Bit definition for CAN_F13R2 register ******************/
5551#define CAN_F13R2_FB0_Pos (0U)
5552#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
5553#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
5554#define CAN_F13R2_FB1_Pos (1U)
5555#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
5556#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
5557#define CAN_F13R2_FB2_Pos (2U)
5558#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
5559#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
5560#define CAN_F13R2_FB3_Pos (3U)
5561#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
5562#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
5563#define CAN_F13R2_FB4_Pos (4U)
5564#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
5565#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
5566#define CAN_F13R2_FB5_Pos (5U)
5567#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
5568#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
5569#define CAN_F13R2_FB6_Pos (6U)
5570#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
5571#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
5572#define CAN_F13R2_FB7_Pos (7U)
5573#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
5574#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
5575#define CAN_F13R2_FB8_Pos (8U)
5576#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
5577#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
5578#define CAN_F13R2_FB9_Pos (9U)
5579#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
5580#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
5581#define CAN_F13R2_FB10_Pos (10U)
5582#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
5583#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
5584#define CAN_F13R2_FB11_Pos (11U)
5585#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
5586#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
5587#define CAN_F13R2_FB12_Pos (12U)
5588#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
5589#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
5590#define CAN_F13R2_FB13_Pos (13U)
5591#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
5592#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
5593#define CAN_F13R2_FB14_Pos (14U)
5594#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
5595#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
5596#define CAN_F13R2_FB15_Pos (15U)
5597#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
5598#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
5599#define CAN_F13R2_FB16_Pos (16U)
5600#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
5601#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
5602#define CAN_F13R2_FB17_Pos (17U)
5603#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
5604#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
5605#define CAN_F13R2_FB18_Pos (18U)
5606#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
5607#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
5608#define CAN_F13R2_FB19_Pos (19U)
5609#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
5610#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
5611#define CAN_F13R2_FB20_Pos (20U)
5612#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
5613#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
5614#define CAN_F13R2_FB21_Pos (21U)
5615#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
5616#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
5617#define CAN_F13R2_FB22_Pos (22U)
5618#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
5619#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
5620#define CAN_F13R2_FB23_Pos (23U)
5621#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
5622#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
5623#define CAN_F13R2_FB24_Pos (24U)
5624#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
5625#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
5626#define CAN_F13R2_FB25_Pos (25U)
5627#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
5628#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
5629#define CAN_F13R2_FB26_Pos (26U)
5630#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
5631#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
5632#define CAN_F13R2_FB27_Pos (27U)
5633#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
5634#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
5635#define CAN_F13R2_FB28_Pos (28U)
5636#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
5637#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
5638#define CAN_F13R2_FB29_Pos (29U)
5639#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
5640#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
5641#define CAN_F13R2_FB30_Pos (30U)
5642#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
5643#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
5644#define CAN_F13R2_FB31_Pos (31U)
5645#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
5646#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
5647
5648/******************************************************************************/
5649/* */
5650/* CRC calculation unit */
5651/* */
5652/******************************************************************************/
5653/******************* Bit definition for CRC_DR register *********************/
5654#define CRC_DR_DR_Pos (0U)
5655#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5656#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5657
5658/******************* Bit definition for CRC_IDR register ********************/
5659#define CRC_IDR_IDR_Pos (0U)
5660#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5661#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
5662
5663/******************** Bit definition for CRC_CR register ********************/
5664#define CRC_CR_RESET_Pos (0U)
5665#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5666#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
5667#define CRC_CR_POLYSIZE_Pos (3U)
5668#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
5669#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
5670#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
5671#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
5672#define CRC_CR_REV_IN_Pos (5U)
5673#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
5674#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
5675#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
5676#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
5677#define CRC_CR_REV_OUT_Pos (7U)
5678#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
5679#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
5680
5681/******************* Bit definition for CRC_INIT register *******************/
5682#define CRC_INIT_INIT_Pos (0U)
5683#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
5684#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
5685
5686/******************* Bit definition for CRC_POL register ********************/
5687#define CRC_POL_POL_Pos (0U)
5688#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
5689#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
5690
5691/******************************************************************************/
5692/* */
5693/* CRS Clock Recovery System */
5694/******************************************************************************/
5695
5696/******************* Bit definition for CRS_CR register *********************/
5697#define CRS_CR_SYNCOKIE_Pos (0U)
5698#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
5699#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
5700#define CRS_CR_SYNCWARNIE_Pos (1U)
5701#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
5702#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
5703#define CRS_CR_ERRIE_Pos (2U)
5704#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
5705#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
5706#define CRS_CR_ESYNCIE_Pos (3U)
5707#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
5708#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
5709#define CRS_CR_CEN_Pos (5U)
5710#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
5711#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
5712#define CRS_CR_AUTOTRIMEN_Pos (6U)
5713#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
5714#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
5715#define CRS_CR_SWSYNC_Pos (7U)
5716#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
5717#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
5718#define CRS_CR_TRIM_Pos (8U)
5719#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5720#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
5721
5722/******************* Bit definition for CRS_CFGR register *********************/
5723#define CRS_CFGR_RELOAD_Pos (0U)
5724#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
5725#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
5726#define CRS_CFGR_FELIM_Pos (16U)
5727#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
5728#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
5729
5730#define CRS_CFGR_SYNCDIV_Pos (24U)
5731#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
5732#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
5733#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
5734#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
5735#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
5736
5737#define CRS_CFGR_SYNCSRC_Pos (28U)
5738#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
5739#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
5740#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
5741#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
5742
5743#define CRS_CFGR_SYNCPOL_Pos (31U)
5744#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
5745#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
5746
5747/******************* Bit definition for CRS_ISR register *********************/
5748#define CRS_ISR_SYNCOKF_Pos (0U)
5749#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
5750#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
5751#define CRS_ISR_SYNCWARNF_Pos (1U)
5752#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
5753#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
5754#define CRS_ISR_ERRF_Pos (2U)
5755#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
5756#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
5757#define CRS_ISR_ESYNCF_Pos (3U)
5758#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
5759#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
5760#define CRS_ISR_SYNCERR_Pos (8U)
5761#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
5762#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
5763#define CRS_ISR_SYNCMISS_Pos (9U)
5764#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
5765#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
5766#define CRS_ISR_TRIMOVF_Pos (10U)
5767#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
5768#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
5769#define CRS_ISR_FEDIR_Pos (15U)
5770#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
5771#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
5772#define CRS_ISR_FECAP_Pos (16U)
5773#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
5774#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
5775
5776/******************* Bit definition for CRS_ICR register *********************/
5777#define CRS_ICR_SYNCOKC_Pos (0U)
5778#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
5779#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
5780#define CRS_ICR_SYNCWARNC_Pos (1U)
5781#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
5782#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
5783#define CRS_ICR_ERRC_Pos (2U)
5784#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
5785#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
5786#define CRS_ICR_ESYNCC_Pos (3U)
5787#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
5788#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
5789
5790/******************************************************************************/
5791/* */
5792/* Digital to Analog Converter */
5793/* */
5794/******************************************************************************/
5795/*
5796 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
5797 */
5798#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
5799
5800/******************** Bit definition for DAC_CR register ********************/
5801#define DAC_CR_EN1_Pos (0U)
5802#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5803#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5804#define DAC_CR_TEN1_Pos (2U)
5805#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
5806#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5807
5808#define DAC_CR_TSEL1_Pos (3U)
5809#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
5810#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5811#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5812#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5813#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5814
5815#define DAC_CR_WAVE1_Pos (6U)
5816#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5817#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5818#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5819#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5820
5821#define DAC_CR_MAMP1_Pos (8U)
5822#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5823#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5824#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5825#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5826#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5827#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5828
5829#define DAC_CR_DMAEN1_Pos (12U)
5830#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5831#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5832#define DAC_CR_DMAUDRIE1_Pos (13U)
5833#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5834#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
5835#define DAC_CR_CEN1_Pos (14U)
5836#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
5837#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
5838
5839#define DAC_CR_EN2_Pos (16U)
5840#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5841#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5842#define DAC_CR_TEN2_Pos (18U)
5843#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
5844#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5845
5846#define DAC_CR_TSEL2_Pos (19U)
5847#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
5848#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5849#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5850#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5851#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5852
5853#define DAC_CR_WAVE2_Pos (22U)
5854#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5855#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5856#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5857#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5858
5859#define DAC_CR_MAMP2_Pos (24U)
5860#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5861#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5862#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5863#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5864#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5865#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5866
5867#define DAC_CR_DMAEN2_Pos (28U)
5868#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5869#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5870#define DAC_CR_DMAUDRIE2_Pos (29U)
5871#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5872#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
5873#define DAC_CR_CEN2_Pos (30U)
5874#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
5875#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
5876
5877/***************** Bit definition for DAC_SWTRIGR register ******************/
5878#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5879#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5880#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5881#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5882#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5883#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5884
5885/***************** Bit definition for DAC_DHR12R1 register ******************/
5886#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5887#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5888#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5889
5890/***************** Bit definition for DAC_DHR12L1 register ******************/
5891#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5892#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5893#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5894
5895/****************** Bit definition for DAC_DHR8R1 register ******************/
5896#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5897#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5898#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5899
5900/***************** Bit definition for DAC_DHR12R2 register ******************/
5901#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5902#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5903#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5904
5905/***************** Bit definition for DAC_DHR12L2 register ******************/
5906#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5907#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5908#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5909
5910/****************** Bit definition for DAC_DHR8R2 register ******************/
5911#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5912#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5913#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5914
5915/***************** Bit definition for DAC_DHR12RD register ******************/
5916#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5917#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5918#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5919#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5920#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5921#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5922
5923/***************** Bit definition for DAC_DHR12LD register ******************/
5924#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5925#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5926#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5927#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5928#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5929#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5930
5931/****************** Bit definition for DAC_DHR8RD register ******************/
5932#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5933#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5934#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5935#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5936#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5937#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5938
5939/******************* Bit definition for DAC_DOR1 register *******************/
5940#define DAC_DOR1_DACC1DOR_Pos (0U)
5941#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5942#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5943
5944/******************* Bit definition for DAC_DOR2 register *******************/
5945#define DAC_DOR2_DACC2DOR_Pos (0U)
5946#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5947#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5948
5949/******************** Bit definition for DAC_SR register ********************/
5950#define DAC_SR_DMAUDR1_Pos (13U)
5951#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5952#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5953#define DAC_SR_CAL_FLAG1_Pos (14U)
5954#define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
5955#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
5956#define DAC_SR_BWST1_Pos (15U)
5957#define DAC_SR_BWST1_Msk (0x1U << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
5958#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
5959
5960#define DAC_SR_DMAUDR2_Pos (29U)
5961#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5962#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5963#define DAC_SR_CAL_FLAG2_Pos (30U)
5964#define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
5965#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
5966#define DAC_SR_BWST2_Pos (31U)
5967#define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
5968#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
5969
5970/******************* Bit definition for DAC_CCR register ********************/
5971#define DAC_CCR_OTRIM1_Pos (0U)
5972#define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
5973#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
5974#define DAC_CCR_OTRIM2_Pos (16U)
5975#define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
5976#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
5977
5978/******************* Bit definition for DAC_MCR register *******************/
5979#define DAC_MCR_MODE1_Pos (0U)
5980#define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
5981#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
5982#define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
5983#define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
5984#define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
5985
5986#define DAC_MCR_MODE2_Pos (16U)
5987#define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
5988#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
5989#define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
5990#define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
5991#define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
5992
5993/****************** Bit definition for DAC_SHSR1 register ******************/
5994#define DAC_SHSR1_TSAMPLE1_Pos (0U)
5995#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
5996#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
5997
5998/****************** Bit definition for DAC_SHSR2 register ******************/
5999#define DAC_SHSR2_TSAMPLE2_Pos (0U)
6000#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
6001#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
6002
6003/****************** Bit definition for DAC_SHHR register ******************/
6004#define DAC_SHHR_THOLD1_Pos (0U)
6005#define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
6006#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
6007#define DAC_SHHR_THOLD2_Pos (16U)
6008#define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
6009#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
6010
6011/****************** Bit definition for DAC_SHRR register ******************/
6012#define DAC_SHRR_TREFRESH1_Pos (0U)
6013#define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
6014#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
6015#define DAC_SHRR_TREFRESH2_Pos (16U)
6016#define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
6017#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
6018
6019/******************************************************************************/
6020/* */
6021/* DMA Controller (DMA) */
6022/* */
6023/******************************************************************************/
6024
6025/******************* Bit definition for DMA_ISR register ********************/
6026#define DMA_ISR_GIF1_Pos (0U)
6027#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
6028#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
6029#define DMA_ISR_TCIF1_Pos (1U)
6030#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
6031#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
6032#define DMA_ISR_HTIF1_Pos (2U)
6033#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
6034#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
6035#define DMA_ISR_TEIF1_Pos (3U)
6036#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
6037#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
6038#define DMA_ISR_GIF2_Pos (4U)
6039#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
6040#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
6041#define DMA_ISR_TCIF2_Pos (5U)
6042#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
6043#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
6044#define DMA_ISR_HTIF2_Pos (6U)
6045#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
6046#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
6047#define DMA_ISR_TEIF2_Pos (7U)
6048#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
6049#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
6050#define DMA_ISR_GIF3_Pos (8U)
6051#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
6052#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
6053#define DMA_ISR_TCIF3_Pos (9U)
6054#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
6055#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
6056#define DMA_ISR_HTIF3_Pos (10U)
6057#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
6058#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
6059#define DMA_ISR_TEIF3_Pos (11U)
6060#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
6061#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
6062#define DMA_ISR_GIF4_Pos (12U)
6063#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
6064#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
6065#define DMA_ISR_TCIF4_Pos (13U)
6066#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
6067#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
6068#define DMA_ISR_HTIF4_Pos (14U)
6069#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
6070#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
6071#define DMA_ISR_TEIF4_Pos (15U)
6072#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
6073#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
6074#define DMA_ISR_GIF5_Pos (16U)
6075#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
6076#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
6077#define DMA_ISR_TCIF5_Pos (17U)
6078#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
6079#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
6080#define DMA_ISR_HTIF5_Pos (18U)
6081#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
6082#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
6083#define DMA_ISR_TEIF5_Pos (19U)
6084#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
6085#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
6086#define DMA_ISR_GIF6_Pos (20U)
6087#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
6088#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
6089#define DMA_ISR_TCIF6_Pos (21U)
6090#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
6091#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
6092#define DMA_ISR_HTIF6_Pos (22U)
6093#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
6094#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
6095#define DMA_ISR_TEIF6_Pos (23U)
6096#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
6097#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
6098#define DMA_ISR_GIF7_Pos (24U)
6099#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
6100#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
6101#define DMA_ISR_TCIF7_Pos (25U)
6102#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
6103#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
6104#define DMA_ISR_HTIF7_Pos (26U)
6105#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
6106#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
6107#define DMA_ISR_TEIF7_Pos (27U)
6108#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
6109#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
6110
6111/******************* Bit definition for DMA_IFCR register *******************/
6112#define DMA_IFCR_CGIF1_Pos (0U)
6113#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
6114#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
6115#define DMA_IFCR_CTCIF1_Pos (1U)
6116#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
6117#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
6118#define DMA_IFCR_CHTIF1_Pos (2U)
6119#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
6120#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
6121#define DMA_IFCR_CTEIF1_Pos (3U)
6122#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
6123#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
6124#define DMA_IFCR_CGIF2_Pos (4U)
6125#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
6126#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
6127#define DMA_IFCR_CTCIF2_Pos (5U)
6128#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
6129#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
6130#define DMA_IFCR_CHTIF2_Pos (6U)
6131#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
6132#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
6133#define DMA_IFCR_CTEIF2_Pos (7U)
6134#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
6135#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
6136#define DMA_IFCR_CGIF3_Pos (8U)
6137#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
6138#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
6139#define DMA_IFCR_CTCIF3_Pos (9U)
6140#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
6141#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
6142#define DMA_IFCR_CHTIF3_Pos (10U)
6143#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
6144#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
6145#define DMA_IFCR_CTEIF3_Pos (11U)
6146#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
6147#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
6148#define DMA_IFCR_CGIF4_Pos (12U)
6149#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
6150#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
6151#define DMA_IFCR_CTCIF4_Pos (13U)
6152#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
6153#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
6154#define DMA_IFCR_CHTIF4_Pos (14U)
6155#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
6156#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
6157#define DMA_IFCR_CTEIF4_Pos (15U)
6158#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
6159#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
6160#define DMA_IFCR_CGIF5_Pos (16U)
6161#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
6162#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
6163#define DMA_IFCR_CTCIF5_Pos (17U)
6164#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
6165#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
6166#define DMA_IFCR_CHTIF5_Pos (18U)
6167#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
6168#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
6169#define DMA_IFCR_CTEIF5_Pos (19U)
6170#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
6171#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
6172#define DMA_IFCR_CGIF6_Pos (20U)
6173#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
6174#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
6175#define DMA_IFCR_CTCIF6_Pos (21U)
6176#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
6177#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
6178#define DMA_IFCR_CHTIF6_Pos (22U)
6179#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
6180#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
6181#define DMA_IFCR_CTEIF6_Pos (23U)
6182#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
6183#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
6184#define DMA_IFCR_CGIF7_Pos (24U)
6185#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
6186#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
6187#define DMA_IFCR_CTCIF7_Pos (25U)
6188#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
6189#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
6190#define DMA_IFCR_CHTIF7_Pos (26U)
6191#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
6192#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
6193#define DMA_IFCR_CTEIF7_Pos (27U)
6194#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
6195#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
6196
6197/******************* Bit definition for DMA_CCR register ********************/
6198#define DMA_CCR_EN_Pos (0U)
6199#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
6200#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
6201#define DMA_CCR_TCIE_Pos (1U)
6202#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
6203#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
6204#define DMA_CCR_HTIE_Pos (2U)
6205#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
6206#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
6207#define DMA_CCR_TEIE_Pos (3U)
6208#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
6209#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
6210#define DMA_CCR_DIR_Pos (4U)
6211#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
6212#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
6213#define DMA_CCR_CIRC_Pos (5U)
6214#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
6215#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
6216#define DMA_CCR_PINC_Pos (6U)
6217#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
6218#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
6219#define DMA_CCR_MINC_Pos (7U)
6220#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
6221#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
6222
6223#define DMA_CCR_PSIZE_Pos (8U)
6224#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
6225#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
6226#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
6227#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
6228
6229#define DMA_CCR_MSIZE_Pos (10U)
6230#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
6231#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
6232#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
6233#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
6234
6235#define DMA_CCR_PL_Pos (12U)
6236#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
6237#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
6238#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
6239#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
6240
6241#define DMA_CCR_MEM2MEM_Pos (14U)
6242#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
6243#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
6244
6245/****************** Bit definition for DMA_CNDTR register *******************/
6246#define DMA_CNDTR_NDT_Pos (0U)
6247#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
6248#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
6249
6250/****************** Bit definition for DMA_CPAR register ********************/
6251#define DMA_CPAR_PA_Pos (0U)
6252#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
6253#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
6254
6255/****************** Bit definition for DMA_CMAR register ********************/
6256#define DMA_CMAR_MA_Pos (0U)
6257#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
6258#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
6259
6260
6261/******************* Bit definition for DMA_CSELR register *******************/
6262#define DMA_CSELR_C1S_Pos (0U)
6263#define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
6264#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
6265#define DMA_CSELR_C2S_Pos (4U)
6266#define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
6267#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
6268#define DMA_CSELR_C3S_Pos (8U)
6269#define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
6270#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
6271#define DMA_CSELR_C4S_Pos (12U)
6272#define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
6273#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
6274#define DMA_CSELR_C5S_Pos (16U)
6275#define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
6276#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
6277#define DMA_CSELR_C6S_Pos (20U)
6278#define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
6279#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
6280#define DMA_CSELR_C7S_Pos (24U)
6281#define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
6282#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
6283
6284/******************************************************************************/
6285/* */
6286/* External Interrupt/Event Controller */
6287/* */
6288/******************************************************************************/
6289/******************* Bit definition for EXTI_IMR1 register ******************/
6290#define EXTI_IMR1_IM0_Pos (0U)
6291#define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
6292#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
6293#define EXTI_IMR1_IM1_Pos (1U)
6294#define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
6295#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
6296#define EXTI_IMR1_IM2_Pos (2U)
6297#define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
6298#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
6299#define EXTI_IMR1_IM3_Pos (3U)
6300#define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
6301#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
6302#define EXTI_IMR1_IM4_Pos (4U)
6303#define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
6304#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
6305#define EXTI_IMR1_IM5_Pos (5U)
6306#define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
6307#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
6308#define EXTI_IMR1_IM6_Pos (6U)
6309#define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
6310#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
6311#define EXTI_IMR1_IM7_Pos (7U)
6312#define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
6313#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
6314#define EXTI_IMR1_IM8_Pos (8U)
6315#define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
6316#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
6317#define EXTI_IMR1_IM9_Pos (9U)
6318#define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
6319#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
6320#define EXTI_IMR1_IM10_Pos (10U)
6321#define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
6322#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
6323#define EXTI_IMR1_IM11_Pos (11U)
6324#define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
6325#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
6326#define EXTI_IMR1_IM12_Pos (12U)
6327#define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
6328#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
6329#define EXTI_IMR1_IM13_Pos (13U)
6330#define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
6331#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
6332#define EXTI_IMR1_IM14_Pos (14U)
6333#define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
6334#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
6335#define EXTI_IMR1_IM15_Pos (15U)
6336#define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
6337#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
6338#define EXTI_IMR1_IM16_Pos (16U)
6339#define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
6340#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
6341#define EXTI_IMR1_IM17_Pos (17U)
6342#define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
6343#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
6344#define EXTI_IMR1_IM18_Pos (18U)
6345#define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
6346#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
6347#define EXTI_IMR1_IM19_Pos (19U)
6348#define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
6349#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
6350#define EXTI_IMR1_IM20_Pos (20U)
6351#define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
6352#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
6353#define EXTI_IMR1_IM21_Pos (21U)
6354#define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
6355#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
6356#define EXTI_IMR1_IM22_Pos (22U)
6357#define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
6358#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
6359#define EXTI_IMR1_IM23_Pos (23U)
6360#define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
6361#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
6362#define EXTI_IMR1_IM24_Pos (24U)
6363#define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
6364#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
6365#define EXTI_IMR1_IM25_Pos (25U)
6366#define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
6367#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
6368#define EXTI_IMR1_IM26_Pos (26U)
6369#define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
6370#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
6371#define EXTI_IMR1_IM27_Pos (27U)
6372#define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
6373#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
6374#define EXTI_IMR1_IM28_Pos (28U)
6375#define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
6376#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
6377#define EXTI_IMR1_IM31_Pos (31U)
6378#define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
6379#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
6380#define EXTI_IMR1_IM_Pos (0U)
6381#define EXTI_IMR1_IM_Msk (0x9FFFFFFFU << EXTI_IMR1_IM_Pos) /*!< 0x9FFFFFFF */
6382#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
6383
6384/******************* Bit definition for EXTI_EMR1 register ******************/
6385#define EXTI_EMR1_EM0_Pos (0U)
6386#define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
6387#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
6388#define EXTI_EMR1_EM1_Pos (1U)
6389#define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
6390#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
6391#define EXTI_EMR1_EM2_Pos (2U)
6392#define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
6393#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
6394#define EXTI_EMR1_EM3_Pos (3U)
6395#define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
6396#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
6397#define EXTI_EMR1_EM4_Pos (4U)
6398#define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
6399#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
6400#define EXTI_EMR1_EM5_Pos (5U)
6401#define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
6402#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
6403#define EXTI_EMR1_EM6_Pos (6U)
6404#define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
6405#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
6406#define EXTI_EMR1_EM7_Pos (7U)
6407#define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
6408#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
6409#define EXTI_EMR1_EM8_Pos (8U)
6410#define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
6411#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
6412#define EXTI_EMR1_EM9_Pos (9U)
6413#define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
6414#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
6415#define EXTI_EMR1_EM10_Pos (10U)
6416#define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
6417#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
6418#define EXTI_EMR1_EM11_Pos (11U)
6419#define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
6420#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
6421#define EXTI_EMR1_EM12_Pos (12U)
6422#define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
6423#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
6424#define EXTI_EMR1_EM13_Pos (13U)
6425#define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
6426#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
6427#define EXTI_EMR1_EM14_Pos (14U)
6428#define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
6429#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
6430#define EXTI_EMR1_EM15_Pos (15U)
6431#define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
6432#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
6433#define EXTI_EMR1_EM16_Pos (16U)
6434#define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
6435#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
6436#define EXTI_EMR1_EM17_Pos (17U)
6437#define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
6438#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
6439#define EXTI_EMR1_EM18_Pos (18U)
6440#define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
6441#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
6442#define EXTI_EMR1_EM19_Pos (19U)
6443#define EXTI_EMR1_EM19_Msk (0x1U << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
6444#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
6445#define EXTI_EMR1_EM20_Pos (20U)
6446#define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
6447#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
6448#define EXTI_EMR1_EM21_Pos (21U)
6449#define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
6450#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
6451#define EXTI_EMR1_EM22_Pos (22U)
6452#define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
6453#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
6454#define EXTI_EMR1_EM23_Pos (23U)
6455#define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
6456#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
6457#define EXTI_EMR1_EM24_Pos (24U)
6458#define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
6459#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
6460#define EXTI_EMR1_EM25_Pos (25U)
6461#define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
6462#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
6463#define EXTI_EMR1_EM26_Pos (26U)
6464#define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
6465#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
6466#define EXTI_EMR1_EM27_Pos (27U)
6467#define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
6468#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
6469#define EXTI_EMR1_EM28_Pos (28U)
6470#define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
6471#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
6472#define EXTI_EMR1_EM31_Pos (31U)
6473#define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
6474#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
6475
6476/****************** Bit definition for EXTI_RTSR1 register ******************/
6477#define EXTI_RTSR1_RT0_Pos (0U)
6478#define EXTI_RTSR1_RT0_Msk (0x1U << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
6479#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
6480#define EXTI_RTSR1_RT1_Pos (1U)
6481#define EXTI_RTSR1_RT1_Msk (0x1U << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
6482#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
6483#define EXTI_RTSR1_RT2_Pos (2U)
6484#define EXTI_RTSR1_RT2_Msk (0x1U << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
6485#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
6486#define EXTI_RTSR1_RT3_Pos (3U)
6487#define EXTI_RTSR1_RT3_Msk (0x1U << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
6488#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
6489#define EXTI_RTSR1_RT4_Pos (4U)
6490#define EXTI_RTSR1_RT4_Msk (0x1U << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
6491#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
6492#define EXTI_RTSR1_RT5_Pos (5U)
6493#define EXTI_RTSR1_RT5_Msk (0x1U << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
6494#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
6495#define EXTI_RTSR1_RT6_Pos (6U)
6496#define EXTI_RTSR1_RT6_Msk (0x1U << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
6497#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
6498#define EXTI_RTSR1_RT7_Pos (7U)
6499#define EXTI_RTSR1_RT7_Msk (0x1U << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
6500#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
6501#define EXTI_RTSR1_RT8_Pos (8U)
6502#define EXTI_RTSR1_RT8_Msk (0x1U << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
6503#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
6504#define EXTI_RTSR1_RT9_Pos (9U)
6505#define EXTI_RTSR1_RT9_Msk (0x1U << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
6506#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
6507#define EXTI_RTSR1_RT10_Pos (10U)
6508#define EXTI_RTSR1_RT10_Msk (0x1U << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
6509#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
6510#define EXTI_RTSR1_RT11_Pos (11U)
6511#define EXTI_RTSR1_RT11_Msk (0x1U << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
6512#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
6513#define EXTI_RTSR1_RT12_Pos (12U)
6514#define EXTI_RTSR1_RT12_Msk (0x1U << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
6515#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
6516#define EXTI_RTSR1_RT13_Pos (13U)
6517#define EXTI_RTSR1_RT13_Msk (0x1U << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
6518#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
6519#define EXTI_RTSR1_RT14_Pos (14U)
6520#define EXTI_RTSR1_RT14_Msk (0x1U << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
6521#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
6522#define EXTI_RTSR1_RT15_Pos (15U)
6523#define EXTI_RTSR1_RT15_Msk (0x1U << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
6524#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
6525#define EXTI_RTSR1_RT16_Pos (16U)
6526#define EXTI_RTSR1_RT16_Msk (0x1U << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
6527#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
6528#define EXTI_RTSR1_RT18_Pos (18U)
6529#define EXTI_RTSR1_RT18_Msk (0x1U << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
6530#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
6531#define EXTI_RTSR1_RT19_Pos (19U)
6532#define EXTI_RTSR1_RT19_Msk (0x1U << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
6533#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
6534#define EXTI_RTSR1_RT20_Pos (20U)
6535#define EXTI_RTSR1_RT20_Msk (0x1U << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
6536#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
6537#define EXTI_RTSR1_RT21_Pos (21U)
6538#define EXTI_RTSR1_RT21_Msk (0x1U << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
6539#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
6540#define EXTI_RTSR1_RT22_Pos (22U)
6541#define EXTI_RTSR1_RT22_Msk (0x1U << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
6542#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
6543
6544/****************** Bit definition for EXTI_FTSR1 register ******************/
6545#define EXTI_FTSR1_FT0_Pos (0U)
6546#define EXTI_FTSR1_FT0_Msk (0x1U << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
6547#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
6548#define EXTI_FTSR1_FT1_Pos (1U)
6549#define EXTI_FTSR1_FT1_Msk (0x1U << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
6550#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
6551#define EXTI_FTSR1_FT2_Pos (2U)
6552#define EXTI_FTSR1_FT2_Msk (0x1U << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
6553#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
6554#define EXTI_FTSR1_FT3_Pos (3U)
6555#define EXTI_FTSR1_FT3_Msk (0x1U << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
6556#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
6557#define EXTI_FTSR1_FT4_Pos (4U)
6558#define EXTI_FTSR1_FT4_Msk (0x1U << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
6559#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
6560#define EXTI_FTSR1_FT5_Pos (5U)
6561#define EXTI_FTSR1_FT5_Msk (0x1U << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
6562#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
6563#define EXTI_FTSR1_FT6_Pos (6U)
6564#define EXTI_FTSR1_FT6_Msk (0x1U << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
6565#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
6566#define EXTI_FTSR1_FT7_Pos (7U)
6567#define EXTI_FTSR1_FT7_Msk (0x1U << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
6568#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
6569#define EXTI_FTSR1_FT8_Pos (8U)
6570#define EXTI_FTSR1_FT8_Msk (0x1U << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
6571#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
6572#define EXTI_FTSR1_FT9_Pos (9U)
6573#define EXTI_FTSR1_FT9_Msk (0x1U << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
6574#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
6575#define EXTI_FTSR1_FT10_Pos (10U)
6576#define EXTI_FTSR1_FT10_Msk (0x1U << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
6577#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
6578#define EXTI_FTSR1_FT11_Pos (11U)
6579#define EXTI_FTSR1_FT11_Msk (0x1U << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
6580#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
6581#define EXTI_FTSR1_FT12_Pos (12U)
6582#define EXTI_FTSR1_FT12_Msk (0x1U << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
6583#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
6584#define EXTI_FTSR1_FT13_Pos (13U)
6585#define EXTI_FTSR1_FT13_Msk (0x1U << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
6586#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
6587#define EXTI_FTSR1_FT14_Pos (14U)
6588#define EXTI_FTSR1_FT14_Msk (0x1U << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
6589#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
6590#define EXTI_FTSR1_FT15_Pos (15U)
6591#define EXTI_FTSR1_FT15_Msk (0x1U << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
6592#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
6593#define EXTI_FTSR1_FT16_Pos (16U)
6594#define EXTI_FTSR1_FT16_Msk (0x1U << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
6595#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
6596#define EXTI_FTSR1_FT18_Pos (18U)
6597#define EXTI_FTSR1_FT18_Msk (0x1U << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
6598#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */
6599#define EXTI_FTSR1_FT19_Pos (19U)
6600#define EXTI_FTSR1_FT19_Msk (0x1U << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
6601#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
6602#define EXTI_FTSR1_FT20_Pos (20U)
6603#define EXTI_FTSR1_FT20_Msk (0x1U << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
6604#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
6605#define EXTI_FTSR1_FT21_Pos (21U)
6606#define EXTI_FTSR1_FT21_Msk (0x1U << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
6607#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
6608#define EXTI_FTSR1_FT22_Pos (22U)
6609#define EXTI_FTSR1_FT22_Msk (0x1U << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
6610#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
6611
6612/****************** Bit definition for EXTI_SWIER1 register *****************/
6613#define EXTI_SWIER1_SWI0_Pos (0U)
6614#define EXTI_SWIER1_SWI0_Msk (0x1U << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
6615#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
6616#define EXTI_SWIER1_SWI1_Pos (1U)
6617#define EXTI_SWIER1_SWI1_Msk (0x1U << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
6618#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
6619#define EXTI_SWIER1_SWI2_Pos (2U)
6620#define EXTI_SWIER1_SWI2_Msk (0x1U << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
6621#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
6622#define EXTI_SWIER1_SWI3_Pos (3U)
6623#define EXTI_SWIER1_SWI3_Msk (0x1U << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
6624#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
6625#define EXTI_SWIER1_SWI4_Pos (4U)
6626#define EXTI_SWIER1_SWI4_Msk (0x1U << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
6627#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
6628#define EXTI_SWIER1_SWI5_Pos (5U)
6629#define EXTI_SWIER1_SWI5_Msk (0x1U << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
6630#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
6631#define EXTI_SWIER1_SWI6_Pos (6U)
6632#define EXTI_SWIER1_SWI6_Msk (0x1U << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
6633#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
6634#define EXTI_SWIER1_SWI7_Pos (7U)
6635#define EXTI_SWIER1_SWI7_Msk (0x1U << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
6636#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
6637#define EXTI_SWIER1_SWI8_Pos (8U)
6638#define EXTI_SWIER1_SWI8_Msk (0x1U << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
6639#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
6640#define EXTI_SWIER1_SWI9_Pos (9U)
6641#define EXTI_SWIER1_SWI9_Msk (0x1U << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
6642#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
6643#define EXTI_SWIER1_SWI10_Pos (10U)
6644#define EXTI_SWIER1_SWI10_Msk (0x1U << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
6645#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
6646#define EXTI_SWIER1_SWI11_Pos (11U)
6647#define EXTI_SWIER1_SWI11_Msk (0x1U << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
6648#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
6649#define EXTI_SWIER1_SWI12_Pos (12U)
6650#define EXTI_SWIER1_SWI12_Msk (0x1U << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
6651#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
6652#define EXTI_SWIER1_SWI13_Pos (13U)
6653#define EXTI_SWIER1_SWI13_Msk (0x1U << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
6654#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
6655#define EXTI_SWIER1_SWI14_Pos (14U)
6656#define EXTI_SWIER1_SWI14_Msk (0x1U << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
6657#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
6658#define EXTI_SWIER1_SWI15_Pos (15U)
6659#define EXTI_SWIER1_SWI15_Msk (0x1U << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
6660#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
6661#define EXTI_SWIER1_SWI16_Pos (16U)
6662#define EXTI_SWIER1_SWI16_Msk (0x1U << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
6663#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
6664#define EXTI_SWIER1_SWI18_Pos (18U)
6665#define EXTI_SWIER1_SWI18_Msk (0x1U << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
6666#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
6667#define EXTI_SWIER1_SWI19_Pos (19U)
6668#define EXTI_SWIER1_SWI19_Msk (0x1U << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
6669#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
6670#define EXTI_SWIER1_SWI20_Pos (20U)
6671#define EXTI_SWIER1_SWI20_Msk (0x1U << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
6672#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
6673#define EXTI_SWIER1_SWI21_Pos (21U)
6674#define EXTI_SWIER1_SWI21_Msk (0x1U << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
6675#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
6676#define EXTI_SWIER1_SWI22_Pos (22U)
6677#define EXTI_SWIER1_SWI22_Msk (0x1U << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
6678#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
6679
6680/******************* Bit definition for EXTI_PR1 register *******************/
6681#define EXTI_PR1_PIF0_Pos (0U)
6682#define EXTI_PR1_PIF0_Msk (0x1U << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
6683#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
6684#define EXTI_PR1_PIF1_Pos (1U)
6685#define EXTI_PR1_PIF1_Msk (0x1U << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
6686#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
6687#define EXTI_PR1_PIF2_Pos (2U)
6688#define EXTI_PR1_PIF2_Msk (0x1U << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
6689#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
6690#define EXTI_PR1_PIF3_Pos (3U)
6691#define EXTI_PR1_PIF3_Msk (0x1U << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
6692#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
6693#define EXTI_PR1_PIF4_Pos (4U)
6694#define EXTI_PR1_PIF4_Msk (0x1U << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
6695#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
6696#define EXTI_PR1_PIF5_Pos (5U)
6697#define EXTI_PR1_PIF5_Msk (0x1U << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
6698#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
6699#define EXTI_PR1_PIF6_Pos (6U)
6700#define EXTI_PR1_PIF6_Msk (0x1U << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
6701#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
6702#define EXTI_PR1_PIF7_Pos (7U)
6703#define EXTI_PR1_PIF7_Msk (0x1U << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
6704#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
6705#define EXTI_PR1_PIF8_Pos (8U)
6706#define EXTI_PR1_PIF8_Msk (0x1U << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
6707#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
6708#define EXTI_PR1_PIF9_Pos (9U)
6709#define EXTI_PR1_PIF9_Msk (0x1U << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
6710#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
6711#define EXTI_PR1_PIF10_Pos (10U)
6712#define EXTI_PR1_PIF10_Msk (0x1U << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
6713#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
6714#define EXTI_PR1_PIF11_Pos (11U)
6715#define EXTI_PR1_PIF11_Msk (0x1U << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
6716#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
6717#define EXTI_PR1_PIF12_Pos (12U)
6718#define EXTI_PR1_PIF12_Msk (0x1U << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
6719#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
6720#define EXTI_PR1_PIF13_Pos (13U)
6721#define EXTI_PR1_PIF13_Msk (0x1U << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
6722#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
6723#define EXTI_PR1_PIF14_Pos (14U)
6724#define EXTI_PR1_PIF14_Msk (0x1U << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
6725#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
6726#define EXTI_PR1_PIF15_Pos (15U)
6727#define EXTI_PR1_PIF15_Msk (0x1U << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
6728#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
6729#define EXTI_PR1_PIF16_Pos (16U)
6730#define EXTI_PR1_PIF16_Msk (0x1U << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
6731#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
6732#define EXTI_PR1_PIF18_Pos (18U)
6733#define EXTI_PR1_PIF18_Msk (0x1U << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */
6734#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */
6735#define EXTI_PR1_PIF19_Pos (19U)
6736#define EXTI_PR1_PIF19_Msk (0x1U << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
6737#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
6738#define EXTI_PR1_PIF20_Pos (20U)
6739#define EXTI_PR1_PIF20_Msk (0x1U << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
6740#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
6741#define EXTI_PR1_PIF21_Pos (21U)
6742#define EXTI_PR1_PIF21_Msk (0x1U << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
6743#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
6744#define EXTI_PR1_PIF22_Pos (22U)
6745#define EXTI_PR1_PIF22_Msk (0x1U << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
6746#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
6747
6748/******************* Bit definition for EXTI_IMR2 register ******************/
6749#define EXTI_IMR2_IM32_Pos (0U)
6750#define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
6751#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
6752#define EXTI_IMR2_IM33_Pos (1U)
6753#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
6754#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
6755#define EXTI_IMR2_IM34_Pos (2U)
6756#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
6757#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
6758#define EXTI_IMR2_IM35_Pos (3U)
6759#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
6760#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
6761#define EXTI_IMR2_IM37_Pos (5U)
6762#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
6763#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
6764#define EXTI_IMR2_IM38_Pos (6U)
6765#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
6766#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
6767#define EXTI_IMR2_IM_Pos (0U)
6768#define EXTI_IMR2_IM_Msk (0x6FU << EXTI_IMR2_IM_Pos) /*!< 0x0000006F */
6769#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
6770
6771/******************* Bit definition for EXTI_EMR2 register ******************/
6772#define EXTI_EMR2_EM32_Pos (0U)
6773#define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
6774#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
6775#define EXTI_EMR2_EM33_Pos (1U)
6776#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
6777#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
6778#define EXTI_EMR2_EM34_Pos (2U)
6779#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
6780#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
6781#define EXTI_EMR2_EM35_Pos (3U)
6782#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
6783#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
6784#define EXTI_EMR2_EM37_Pos (5U)
6785#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
6786#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
6787#define EXTI_EMR2_EM38_Pos (6U)
6788#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
6789#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
6790#define EXTI_EMR2_EM_Pos (0U)
6791#define EXTI_EMR2_EM_Msk (0x6FU << EXTI_EMR2_EM_Pos) /*!< 0x0000006F */
6792#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
6793
6794/****************** Bit definition for EXTI_RTSR2 register ******************/
6795#define EXTI_RTSR2_RT35_Pos (3U)
6796#define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
6797#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
6798#define EXTI_RTSR2_RT37_Pos (5U)
6799#define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
6800#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
6801#define EXTI_RTSR2_RT38_Pos (6U)
6802#define EXTI_RTSR2_RT38_Msk (0x1U << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
6803#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
6804
6805/****************** Bit definition for EXTI_FTSR2 register ******************/
6806#define EXTI_FTSR2_FT35_Pos (3U)
6807#define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
6808#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
6809#define EXTI_FTSR2_FT37_Pos (5U)
6810#define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
6811#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
6812#define EXTI_FTSR2_FT38_Pos (6U)
6813#define EXTI_FTSR2_FT38_Msk (0x1U << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
6814#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
6815
6816/****************** Bit definition for EXTI_SWIER2 register *****************/
6817#define EXTI_SWIER2_SWI35_Pos (3U)
6818#define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
6819#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
6820#define EXTI_SWIER2_SWI37_Pos (5U)
6821#define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
6822#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
6823#define EXTI_SWIER2_SWI38_Pos (6U)
6824#define EXTI_SWIER2_SWI38_Msk (0x1U << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
6825#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
6826
6827/******************* Bit definition for EXTI_PR2 register *******************/
6828#define EXTI_PR2_PIF35_Pos (3U)
6829#define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
6830#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
6831#define EXTI_PR2_PIF37_Pos (5U)
6832#define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
6833#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
6834#define EXTI_PR2_PIF38_Pos (6U)
6835#define EXTI_PR2_PIF38_Msk (0x1U << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
6836#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
6837
6838
6839/******************************************************************************/
6840/* */
6841/* FLASH */
6842/* */
6843/******************************************************************************/
6844/******************* Bits definition for FLASH_ACR register *****************/
6845#define FLASH_ACR_LATENCY_Pos (0U)
6846#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
6847#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6848#define FLASH_ACR_LATENCY_0WS (0x00000000U)
6849#define FLASH_ACR_LATENCY_1WS (0x00000001U)
6850#define FLASH_ACR_LATENCY_2WS (0x00000002U)
6851#define FLASH_ACR_LATENCY_3WS (0x00000003U)
6852#define FLASH_ACR_LATENCY_4WS (0x00000004U)
6853#define FLASH_ACR_PRFTEN_Pos (8U)
6854#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
6855#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6856#define FLASH_ACR_ICEN_Pos (9U)
6857#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
6858#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6859#define FLASH_ACR_DCEN_Pos (10U)
6860#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
6861#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6862#define FLASH_ACR_ICRST_Pos (11U)
6863#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
6864#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6865#define FLASH_ACR_DCRST_Pos (12U)
6866#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
6867#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6868#define FLASH_ACR_RUN_PD_Pos (13U)
6869#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
6870#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
6871#define FLASH_ACR_SLEEP_PD_Pos (14U)
6872#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
6873#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
6874
6875/******************* Bits definition for FLASH_SR register ******************/
6876#define FLASH_SR_EOP_Pos (0U)
6877#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
6878#define FLASH_SR_EOP FLASH_SR_EOP_Msk
6879#define FLASH_SR_OPERR_Pos (1U)
6880#define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
6881#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
6882#define FLASH_SR_PROGERR_Pos (3U)
6883#define FLASH_SR_PROGERR_Msk (0x1U << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
6884#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
6885#define FLASH_SR_WRPERR_Pos (4U)
6886#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
6887#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6888#define FLASH_SR_PGAERR_Pos (5U)
6889#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
6890#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6891#define FLASH_SR_SIZERR_Pos (6U)
6892#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
6893#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
6894#define FLASH_SR_PGSERR_Pos (7U)
6895#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
6896#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6897#define FLASH_SR_MISERR_Pos (8U)
6898#define FLASH_SR_MISERR_Msk (0x1U << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
6899#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
6900#define FLASH_SR_FASTERR_Pos (9U)
6901#define FLASH_SR_FASTERR_Msk (0x1U << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
6902#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
6903#define FLASH_SR_RDERR_Pos (14U)
6904#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
6905#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
6906#define FLASH_SR_OPTVERR_Pos (15U)
6907#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
6908#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
6909#define FLASH_SR_BSY_Pos (16U)
6910#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
6911#define FLASH_SR_BSY FLASH_SR_BSY_Msk
6912#define FLASH_SR_PEMPTY_Pos (17U)
6913#define FLASH_SR_PEMPTY_Msk (0x1U << FLASH_SR_PEMPTY_Pos) /*!< 0x00020000 */
6914#define FLASH_SR_PEMPTY FLASH_SR_PEMPTY_Msk
6915
6916/******************* Bits definition for FLASH_CR register ******************/
6917#define FLASH_CR_PG_Pos (0U)
6918#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
6919#define FLASH_CR_PG FLASH_CR_PG_Msk
6920#define FLASH_CR_PER_Pos (1U)
6921#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
6922#define FLASH_CR_PER FLASH_CR_PER_Msk
6923#define FLASH_CR_MER1_Pos (2U)
6924#define FLASH_CR_MER1_Msk (0x1U << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
6925#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
6926#define FLASH_CR_PNB_Pos (3U)
6927#define FLASH_CR_PNB_Msk (0xFFU << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
6928#define FLASH_CR_PNB FLASH_CR_PNB_Msk
6929#define FLASH_CR_STRT_Pos (16U)
6930#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
6931#define FLASH_CR_STRT FLASH_CR_STRT_Msk
6932#define FLASH_CR_OPTSTRT_Pos (17U)
6933#define FLASH_CR_OPTSTRT_Msk (0x1U << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
6934#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
6935#define FLASH_CR_FSTPG_Pos (18U)
6936#define FLASH_CR_FSTPG_Msk (0x1U << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
6937#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
6938#define FLASH_CR_EOPIE_Pos (24U)
6939#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
6940#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6941#define FLASH_CR_ERRIE_Pos (25U)
6942#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
6943#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
6944#define FLASH_CR_RDERRIE_Pos (26U)
6945#define FLASH_CR_RDERRIE_Msk (0x1U << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
6946#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
6947#define FLASH_CR_OBL_LAUNCH_Pos (27U)
6948#define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
6949#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
6950#define FLASH_CR_OPTLOCK_Pos (30U)
6951#define FLASH_CR_OPTLOCK_Msk (0x1U << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
6952#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
6953#define FLASH_CR_LOCK_Pos (31U)
6954#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
6955#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6956
6957/******************* Bits definition for FLASH_ECCR register ***************/
6958#define FLASH_ECCR_ADDR_ECC_Pos (0U)
6959#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
6960#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
6961#define FLASH_ECCR_SYSF_ECC_Pos (20U)
6962#define FLASH_ECCR_SYSF_ECC_Msk (0x1U << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
6963#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
6964#define FLASH_ECCR_ECCIE_Pos (24U)
6965#define FLASH_ECCR_ECCIE_Msk (0x1U << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
6966#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
6967#define FLASH_ECCR_ECCC_Pos (30U)
6968#define FLASH_ECCR_ECCC_Msk (0x1U << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
6969#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
6970#define FLASH_ECCR_ECCD_Pos (31U)
6971#define FLASH_ECCR_ECCD_Msk (0x1U << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
6972#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
6973
6974/******************* Bits definition for FLASH_OPTR register ***************/
6975#define FLASH_OPTR_RDP_Pos (0U)
6976#define FLASH_OPTR_RDP_Msk (0xFFU << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
6977#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
6978#define FLASH_OPTR_BOR_LEV_Pos (8U)
6979#define FLASH_OPTR_BOR_LEV_Msk (0x7U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
6980#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
6981#define FLASH_OPTR_BOR_LEV_0 (0x0U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
6982#define FLASH_OPTR_BOR_LEV_1 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
6983#define FLASH_OPTR_BOR_LEV_2 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
6984#define FLASH_OPTR_BOR_LEV_3 (0x3U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
6985#define FLASH_OPTR_BOR_LEV_4 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
6986#define FLASH_OPTR_nRST_STOP_Pos (12U)
6987#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
6988#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
6989#define FLASH_OPTR_nRST_STDBY_Pos (13U)
6990#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
6991#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
6992#define FLASH_OPTR_nRST_SHDW_Pos (14U)
6993#define FLASH_OPTR_nRST_SHDW_Msk (0x1U << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
6994#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
6995#define FLASH_OPTR_IWDG_SW_Pos (16U)
6996#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
6997#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
6998#define FLASH_OPTR_IWDG_STOP_Pos (17U)
6999#define FLASH_OPTR_IWDG_STOP_Msk (0x1U << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
7000#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
7001#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
7002#define FLASH_OPTR_IWDG_STDBY_Msk (0x1U << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
7003#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
7004#define FLASH_OPTR_WWDG_SW_Pos (19U)
7005#define FLASH_OPTR_WWDG_SW_Msk (0x1U << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
7006#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
7007#define FLASH_OPTR_nBOOT1_Pos (23U)
7008#define FLASH_OPTR_nBOOT1_Msk (0x1U << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
7009#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
7010#define FLASH_OPTR_SRAM2_PE_Pos (24U)
7011#define FLASH_OPTR_SRAM2_PE_Msk (0x1U << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
7012#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
7013#define FLASH_OPTR_SRAM2_RST_Pos (25U)
7014#define FLASH_OPTR_SRAM2_RST_Msk (0x1U << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
7015#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
7016#define FLASH_OPTR_nSWBOOT0_Pos (26U)
7017#define FLASH_OPTR_nSWBOOT0_Msk (0x1U << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
7018#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
7019#define FLASH_OPTR_nBOOT0_Pos (27U)
7020#define FLASH_OPTR_nBOOT0_Msk (0x1U << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
7021#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
7022
7023/****************** Bits definition for FLASH_PCROP1SR register **********/
7024#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
7025#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
7026#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
7027
7028/****************** Bits definition for FLASH_PCROP1ER register ***********/
7029#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
7030#define FLASH_PCROP1ER_PCROP1_END_Msk (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
7031#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
7032#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
7033#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
7034#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
7035
7036/****************** Bits definition for FLASH_WRP1AR register ***************/
7037#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
7038#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
7039#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
7040#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
7041#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
7042#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
7043
7044/****************** Bits definition for FLASH_WRPB1R register ***************/
7045#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
7046#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
7047#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
7048#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
7049#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
7050#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
7051
7052
7053
7054
7055/******************************************************************************/
7056/* */
7057/* General Purpose IOs (GPIO) */
7058/* */
7059/******************************************************************************/
7060/****************** Bits definition for GPIO_MODER register *****************/
7061#define GPIO_MODER_MODE0_Pos (0U)
7062#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
7063#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
7064#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
7065#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
7066#define GPIO_MODER_MODE1_Pos (2U)
7067#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
7068#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
7069#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
7070#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
7071#define GPIO_MODER_MODE2_Pos (4U)
7072#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
7073#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
7074#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
7075#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
7076#define GPIO_MODER_MODE3_Pos (6U)
7077#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
7078#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
7079#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
7080#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
7081#define GPIO_MODER_MODE4_Pos (8U)
7082#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
7083#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
7084#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
7085#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
7086#define GPIO_MODER_MODE5_Pos (10U)
7087#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
7088#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
7089#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
7090#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
7091#define GPIO_MODER_MODE6_Pos (12U)
7092#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
7093#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
7094#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
7095#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
7096#define GPIO_MODER_MODE7_Pos (14U)
7097#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
7098#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
7099#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
7100#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
7101#define GPIO_MODER_MODE8_Pos (16U)
7102#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
7103#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
7104#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
7105#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
7106#define GPIO_MODER_MODE9_Pos (18U)
7107#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
7108#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
7109#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
7110#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
7111#define GPIO_MODER_MODE10_Pos (20U)
7112#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
7113#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
7114#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
7115#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
7116#define GPIO_MODER_MODE11_Pos (22U)
7117#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
7118#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
7119#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
7120#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
7121#define GPIO_MODER_MODE12_Pos (24U)
7122#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
7123#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
7124#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
7125#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
7126#define GPIO_MODER_MODE13_Pos (26U)
7127#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
7128#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
7129#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
7130#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
7131#define GPIO_MODER_MODE14_Pos (28U)
7132#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
7133#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
7134#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
7135#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
7136#define GPIO_MODER_MODE15_Pos (30U)
7137#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
7138#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
7139#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
7140#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
7141
7142/* Legacy defines */
7143#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
7144#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
7145#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
7146#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
7147#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
7148#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
7149#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
7150#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
7151#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
7152#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
7153#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
7154#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
7155#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
7156#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
7157#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
7158#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
7159#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
7160#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
7161#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
7162#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
7163#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
7164#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
7165#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
7166#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
7167#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
7168#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
7169#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
7170#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
7171#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
7172#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
7173#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
7174#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
7175#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
7176#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
7177#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
7178#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
7179#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
7180#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
7181#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
7182#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
7183#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
7184#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
7185#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
7186#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
7187#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
7188#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
7189#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
7190#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
7191
7192/****************** Bits definition for GPIO_OTYPER register ****************/
7193#define GPIO_OTYPER_OT0_Pos (0U)
7194#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
7195#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
7196#define GPIO_OTYPER_OT1_Pos (1U)
7197#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
7198#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
7199#define GPIO_OTYPER_OT2_Pos (2U)
7200#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
7201#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
7202#define GPIO_OTYPER_OT3_Pos (3U)
7203#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
7204#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
7205#define GPIO_OTYPER_OT4_Pos (4U)
7206#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
7207#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
7208#define GPIO_OTYPER_OT5_Pos (5U)
7209#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
7210#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
7211#define GPIO_OTYPER_OT6_Pos (6U)
7212#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
7213#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
7214#define GPIO_OTYPER_OT7_Pos (7U)
7215#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
7216#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
7217#define GPIO_OTYPER_OT8_Pos (8U)
7218#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
7219#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
7220#define GPIO_OTYPER_OT9_Pos (9U)
7221#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
7222#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
7223#define GPIO_OTYPER_OT10_Pos (10U)
7224#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
7225#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
7226#define GPIO_OTYPER_OT11_Pos (11U)
7227#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
7228#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
7229#define GPIO_OTYPER_OT12_Pos (12U)
7230#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
7231#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
7232#define GPIO_OTYPER_OT13_Pos (13U)
7233#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
7234#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
7235#define GPIO_OTYPER_OT14_Pos (14U)
7236#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
7237#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
7238#define GPIO_OTYPER_OT15_Pos (15U)
7239#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
7240#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
7241
7242/* Legacy defines */
7243#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
7244#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
7245#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
7246#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
7247#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
7248#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
7249#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
7250#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
7251#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
7252#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
7253#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
7254#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
7255#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
7256#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
7257#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
7258#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
7259
7260/****************** Bits definition for GPIO_OSPEEDR register ***************/
7261#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
7262#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
7263#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
7264#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
7265#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
7266#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
7267#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
7268#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
7269#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
7270#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
7271#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
7272#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
7273#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
7274#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
7275#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
7276#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
7277#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
7278#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
7279#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
7280#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
7281#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
7282#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
7283#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
7284#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
7285#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
7286#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
7287#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
7288#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
7289#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
7290#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
7291#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
7292#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
7293#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
7294#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
7295#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
7296#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
7297#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
7298#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
7299#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
7300#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
7301#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
7302#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
7303#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
7304#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
7305#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
7306#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
7307#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
7308#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
7309#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
7310#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
7311#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
7312#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
7313#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
7314#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
7315#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
7316#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
7317#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
7318#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
7319#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
7320#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
7321#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
7322#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
7323#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
7324#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
7325#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
7326#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
7327#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
7328#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
7329#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
7330#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
7331#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
7332#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
7333#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
7334#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
7335#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
7336#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
7337#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
7338#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
7339#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
7340#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
7341
7342/* Legacy defines */
7343#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
7344#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
7345#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
7346#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
7347#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
7348#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
7349#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
7350#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
7351#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
7352#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
7353#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
7354#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
7355#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
7356#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
7357#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
7358#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
7359#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
7360#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
7361#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
7362#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
7363#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
7364#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
7365#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
7366#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
7367#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
7368#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
7369#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
7370#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
7371#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
7372#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
7373#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
7374#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
7375#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
7376#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
7377#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
7378#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
7379#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
7380#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
7381#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
7382#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
7383#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
7384#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
7385#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
7386#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
7387#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
7388#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
7389#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
7390#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
7391
7392/****************** Bits definition for GPIO_PUPDR register *****************/
7393#define GPIO_PUPDR_PUPD0_Pos (0U)
7394#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
7395#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
7396#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
7397#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
7398#define GPIO_PUPDR_PUPD1_Pos (2U)
7399#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
7400#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
7401#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
7402#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
7403#define GPIO_PUPDR_PUPD2_Pos (4U)
7404#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
7405#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
7406#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
7407#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
7408#define GPIO_PUPDR_PUPD3_Pos (6U)
7409#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
7410#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
7411#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
7412#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
7413#define GPIO_PUPDR_PUPD4_Pos (8U)
7414#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
7415#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
7416#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
7417#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
7418#define GPIO_PUPDR_PUPD5_Pos (10U)
7419#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
7420#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
7421#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
7422#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
7423#define GPIO_PUPDR_PUPD6_Pos (12U)
7424#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
7425#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
7426#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
7427#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
7428#define GPIO_PUPDR_PUPD7_Pos (14U)
7429#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
7430#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
7431#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
7432#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
7433#define GPIO_PUPDR_PUPD8_Pos (16U)
7434#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
7435#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
7436#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
7437#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
7438#define GPIO_PUPDR_PUPD9_Pos (18U)
7439#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
7440#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
7441#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
7442#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
7443#define GPIO_PUPDR_PUPD10_Pos (20U)
7444#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
7445#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
7446#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
7447#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
7448#define GPIO_PUPDR_PUPD11_Pos (22U)
7449#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
7450#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
7451#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
7452#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
7453#define GPIO_PUPDR_PUPD12_Pos (24U)
7454#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
7455#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
7456#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
7457#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
7458#define GPIO_PUPDR_PUPD13_Pos (26U)
7459#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
7460#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
7461#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
7462#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
7463#define GPIO_PUPDR_PUPD14_Pos (28U)
7464#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
7465#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
7466#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
7467#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
7468#define GPIO_PUPDR_PUPD15_Pos (30U)
7469#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
7470#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
7471#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
7472#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
7473
7474/* Legacy defines */
7475#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
7476#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
7477#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
7478#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
7479#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
7480#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
7481#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
7482#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
7483#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
7484#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
7485#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
7486#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
7487#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
7488#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
7489#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
7490#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
7491#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
7492#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
7493#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
7494#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
7495#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
7496#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
7497#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
7498#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
7499#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
7500#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
7501#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
7502#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
7503#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
7504#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
7505#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
7506#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
7507#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
7508#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
7509#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
7510#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
7511#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
7512#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
7513#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
7514#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
7515#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
7516#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
7517#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
7518#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
7519#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
7520#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
7521#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
7522#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
7523
7524/****************** Bits definition for GPIO_IDR register *******************/
7525#define GPIO_IDR_ID0_Pos (0U)
7526#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
7527#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
7528#define GPIO_IDR_ID1_Pos (1U)
7529#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
7530#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
7531#define GPIO_IDR_ID2_Pos (2U)
7532#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
7533#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
7534#define GPIO_IDR_ID3_Pos (3U)
7535#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
7536#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
7537#define GPIO_IDR_ID4_Pos (4U)
7538#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
7539#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
7540#define GPIO_IDR_ID5_Pos (5U)
7541#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
7542#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
7543#define GPIO_IDR_ID6_Pos (6U)
7544#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
7545#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
7546#define GPIO_IDR_ID7_Pos (7U)
7547#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
7548#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
7549#define GPIO_IDR_ID8_Pos (8U)
7550#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
7551#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
7552#define GPIO_IDR_ID9_Pos (9U)
7553#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
7554#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
7555#define GPIO_IDR_ID10_Pos (10U)
7556#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
7557#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
7558#define GPIO_IDR_ID11_Pos (11U)
7559#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
7560#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
7561#define GPIO_IDR_ID12_Pos (12U)
7562#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
7563#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
7564#define GPIO_IDR_ID13_Pos (13U)
7565#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
7566#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
7567#define GPIO_IDR_ID14_Pos (14U)
7568#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
7569#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
7570#define GPIO_IDR_ID15_Pos (15U)
7571#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
7572#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
7573
7574/* Legacy defines */
7575#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
7576#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
7577#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
7578#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
7579#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
7580#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
7581#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
7582#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
7583#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
7584#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
7585#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
7586#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
7587#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
7588#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
7589#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
7590#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
7591
7592/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
7593#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
7594#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
7595#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
7596#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
7597#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
7598#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
7599#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
7600#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
7601#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
7602#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
7603#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
7604#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
7605#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
7606#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
7607#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
7608#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
7609
7610/****************** Bits definition for GPIO_ODR register *******************/
7611#define GPIO_ODR_OD0_Pos (0U)
7612#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
7613#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
7614#define GPIO_ODR_OD1_Pos (1U)
7615#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
7616#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
7617#define GPIO_ODR_OD2_Pos (2U)
7618#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
7619#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
7620#define GPIO_ODR_OD3_Pos (3U)
7621#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
7622#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
7623#define GPIO_ODR_OD4_Pos (4U)
7624#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
7625#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
7626#define GPIO_ODR_OD5_Pos (5U)
7627#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
7628#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
7629#define GPIO_ODR_OD6_Pos (6U)
7630#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
7631#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
7632#define GPIO_ODR_OD7_Pos (7U)
7633#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
7634#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
7635#define GPIO_ODR_OD8_Pos (8U)
7636#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
7637#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
7638#define GPIO_ODR_OD9_Pos (9U)
7639#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
7640#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
7641#define GPIO_ODR_OD10_Pos (10U)
7642#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
7643#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
7644#define GPIO_ODR_OD11_Pos (11U)
7645#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
7646#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
7647#define GPIO_ODR_OD12_Pos (12U)
7648#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
7649#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
7650#define GPIO_ODR_OD13_Pos (13U)
7651#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
7652#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
7653#define GPIO_ODR_OD14_Pos (14U)
7654#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
7655#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
7656#define GPIO_ODR_OD15_Pos (15U)
7657#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
7658#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
7659
7660/* Legacy defines */
7661#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
7662#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
7663#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
7664#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
7665#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
7666#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
7667#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
7668#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
7669#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
7670#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
7671#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
7672#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
7673#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
7674#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
7675#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
7676#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
7677
7678/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
7679#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
7680#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
7681#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
7682#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
7683#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
7684#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
7685#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
7686#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
7687#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
7688#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
7689#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
7690#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
7691#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
7692#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
7693#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
7694#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
7695
7696/****************** Bits definition for GPIO_BSRR register ******************/
7697#define GPIO_BSRR_BS0_Pos (0U)
7698#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
7699#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
7700#define GPIO_BSRR_BS1_Pos (1U)
7701#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
7702#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
7703#define GPIO_BSRR_BS2_Pos (2U)
7704#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
7705#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
7706#define GPIO_BSRR_BS3_Pos (3U)
7707#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
7708#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
7709#define GPIO_BSRR_BS4_Pos (4U)
7710#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
7711#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
7712#define GPIO_BSRR_BS5_Pos (5U)
7713#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
7714#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
7715#define GPIO_BSRR_BS6_Pos (6U)
7716#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
7717#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
7718#define GPIO_BSRR_BS7_Pos (7U)
7719#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
7720#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
7721#define GPIO_BSRR_BS8_Pos (8U)
7722#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
7723#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
7724#define GPIO_BSRR_BS9_Pos (9U)
7725#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
7726#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
7727#define GPIO_BSRR_BS10_Pos (10U)
7728#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
7729#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
7730#define GPIO_BSRR_BS11_Pos (11U)
7731#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
7732#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
7733#define GPIO_BSRR_BS12_Pos (12U)
7734#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
7735#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
7736#define GPIO_BSRR_BS13_Pos (13U)
7737#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
7738#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
7739#define GPIO_BSRR_BS14_Pos (14U)
7740#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
7741#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
7742#define GPIO_BSRR_BS15_Pos (15U)
7743#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
7744#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
7745#define GPIO_BSRR_BR0_Pos (16U)
7746#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
7747#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
7748#define GPIO_BSRR_BR1_Pos (17U)
7749#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
7750#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
7751#define GPIO_BSRR_BR2_Pos (18U)
7752#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
7753#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
7754#define GPIO_BSRR_BR3_Pos (19U)
7755#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
7756#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
7757#define GPIO_BSRR_BR4_Pos (20U)
7758#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
7759#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
7760#define GPIO_BSRR_BR5_Pos (21U)
7761#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
7762#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
7763#define GPIO_BSRR_BR6_Pos (22U)
7764#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
7765#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
7766#define GPIO_BSRR_BR7_Pos (23U)
7767#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
7768#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
7769#define GPIO_BSRR_BR8_Pos (24U)
7770#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
7771#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
7772#define GPIO_BSRR_BR9_Pos (25U)
7773#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
7774#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
7775#define GPIO_BSRR_BR10_Pos (26U)
7776#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
7777#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
7778#define GPIO_BSRR_BR11_Pos (27U)
7779#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
7780#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
7781#define GPIO_BSRR_BR12_Pos (28U)
7782#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
7783#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
7784#define GPIO_BSRR_BR13_Pos (29U)
7785#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
7786#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
7787#define GPIO_BSRR_BR14_Pos (30U)
7788#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
7789#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
7790#define GPIO_BSRR_BR15_Pos (31U)
7791#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
7792#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
7793
7794/* Legacy defines */
7795#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
7796#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
7797#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
7798#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
7799#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
7800#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
7801#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
7802#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
7803#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
7804#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
7805#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
7806#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
7807#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
7808#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
7809#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
7810#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
7811#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
7812#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
7813#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
7814#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
7815#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
7816#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
7817#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
7818#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
7819#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
7820#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
7821#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
7822#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
7823#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
7824#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
7825#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
7826#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
7827
7828/****************** Bit definition for GPIO_LCKR register *********************/
7829#define GPIO_LCKR_LCK0_Pos (0U)
7830#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
7831#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
7832#define GPIO_LCKR_LCK1_Pos (1U)
7833#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
7834#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
7835#define GPIO_LCKR_LCK2_Pos (2U)
7836#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
7837#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
7838#define GPIO_LCKR_LCK3_Pos (3U)
7839#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
7840#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
7841#define GPIO_LCKR_LCK4_Pos (4U)
7842#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
7843#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
7844#define GPIO_LCKR_LCK5_Pos (5U)
7845#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
7846#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
7847#define GPIO_LCKR_LCK6_Pos (6U)
7848#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
7849#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
7850#define GPIO_LCKR_LCK7_Pos (7U)
7851#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
7852#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
7853#define GPIO_LCKR_LCK8_Pos (8U)
7854#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
7855#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
7856#define GPIO_LCKR_LCK9_Pos (9U)
7857#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
7858#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
7859#define GPIO_LCKR_LCK10_Pos (10U)
7860#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
7861#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
7862#define GPIO_LCKR_LCK11_Pos (11U)
7863#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
7864#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
7865#define GPIO_LCKR_LCK12_Pos (12U)
7866#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
7867#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
7868#define GPIO_LCKR_LCK13_Pos (13U)
7869#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
7870#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
7871#define GPIO_LCKR_LCK14_Pos (14U)
7872#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
7873#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
7874#define GPIO_LCKR_LCK15_Pos (15U)
7875#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
7876#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
7877#define GPIO_LCKR_LCKK_Pos (16U)
7878#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
7879#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
7880
7881/****************** Bit definition for GPIO_AFRL register *********************/
7882#define GPIO_AFRL_AFSEL0_Pos (0U)
7883#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
7884#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
7885#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
7886#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
7887#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
7888#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
7889#define GPIO_AFRL_AFSEL1_Pos (4U)
7890#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
7891#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
7892#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
7893#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
7894#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
7895#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
7896#define GPIO_AFRL_AFSEL2_Pos (8U)
7897#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
7898#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
7899#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
7900#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
7901#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
7902#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
7903#define GPIO_AFRL_AFSEL3_Pos (12U)
7904#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
7905#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
7906#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
7907#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
7908#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
7909#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
7910#define GPIO_AFRL_AFSEL4_Pos (16U)
7911#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
7912#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
7913#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
7914#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
7915#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
7916#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
7917#define GPIO_AFRL_AFSEL5_Pos (20U)
7918#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
7919#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
7920#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
7921#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
7922#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
7923#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
7924#define GPIO_AFRL_AFSEL6_Pos (24U)
7925#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
7926#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
7927#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
7928#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
7929#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
7930#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
7931#define GPIO_AFRL_AFSEL7_Pos (28U)
7932#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
7933#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
7934#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
7935#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
7936#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
7937#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
7938
7939/* Legacy defines */
7940#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
7941#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
7942#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
7943#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
7944#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
7945#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
7946#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
7947#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
7948
7949/****************** Bit definition for GPIO_AFRH register *********************/
7950#define GPIO_AFRH_AFSEL8_Pos (0U)
7951#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
7952#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
7953#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
7954#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
7955#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
7956#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
7957#define GPIO_AFRH_AFSEL9_Pos (4U)
7958#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
7959#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
7960#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
7961#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
7962#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
7963#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
7964#define GPIO_AFRH_AFSEL10_Pos (8U)
7965#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
7966#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
7967#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
7968#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
7969#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
7970#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
7971#define GPIO_AFRH_AFSEL11_Pos (12U)
7972#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
7973#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
7974#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
7975#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
7976#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
7977#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
7978#define GPIO_AFRH_AFSEL12_Pos (16U)
7979#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
7980#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
7981#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
7982#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
7983#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
7984#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
7985#define GPIO_AFRH_AFSEL13_Pos (20U)
7986#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
7987#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
7988#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
7989#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
7990#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
7991#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
7992#define GPIO_AFRH_AFSEL14_Pos (24U)
7993#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
7994#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
7995#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
7996#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
7997#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
7998#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
7999#define GPIO_AFRH_AFSEL15_Pos (28U)
8000#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
8001#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
8002#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
8003#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
8004#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
8005#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
8006
8007/* Legacy defines */
8008#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
8009#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
8010#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
8011#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
8012#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
8013#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
8014#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
8015#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
8016
8017/****************** Bits definition for GPIO_BRR register ******************/
8018#define GPIO_BRR_BR0_Pos (0U)
8019#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
8020#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
8021#define GPIO_BRR_BR1_Pos (1U)
8022#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
8023#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
8024#define GPIO_BRR_BR2_Pos (2U)
8025#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
8026#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
8027#define GPIO_BRR_BR3_Pos (3U)
8028#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
8029#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
8030#define GPIO_BRR_BR4_Pos (4U)
8031#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
8032#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
8033#define GPIO_BRR_BR5_Pos (5U)
8034#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
8035#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
8036#define GPIO_BRR_BR6_Pos (6U)
8037#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
8038#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
8039#define GPIO_BRR_BR7_Pos (7U)
8040#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
8041#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
8042#define GPIO_BRR_BR8_Pos (8U)
8043#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
8044#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
8045#define GPIO_BRR_BR9_Pos (9U)
8046#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
8047#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
8048#define GPIO_BRR_BR10_Pos (10U)
8049#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
8050#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
8051#define GPIO_BRR_BR11_Pos (11U)
8052#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
8053#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
8054#define GPIO_BRR_BR12_Pos (12U)
8055#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
8056#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
8057#define GPIO_BRR_BR13_Pos (13U)
8058#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
8059#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
8060#define GPIO_BRR_BR14_Pos (14U)
8061#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
8062#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
8063#define GPIO_BRR_BR15_Pos (15U)
8064#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
8065#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
8066
8067/* Legacy defines */
8068#define GPIO_BRR_BR_0 GPIO_BRR_BR0
8069#define GPIO_BRR_BR_1 GPIO_BRR_BR1
8070#define GPIO_BRR_BR_2 GPIO_BRR_BR2
8071#define GPIO_BRR_BR_3 GPIO_BRR_BR3
8072#define GPIO_BRR_BR_4 GPIO_BRR_BR4
8073#define GPIO_BRR_BR_5 GPIO_BRR_BR5
8074#define GPIO_BRR_BR_6 GPIO_BRR_BR6
8075#define GPIO_BRR_BR_7 GPIO_BRR_BR7
8076#define GPIO_BRR_BR_8 GPIO_BRR_BR8
8077#define GPIO_BRR_BR_9 GPIO_BRR_BR9
8078#define GPIO_BRR_BR_10 GPIO_BRR_BR10
8079#define GPIO_BRR_BR_11 GPIO_BRR_BR11
8080#define GPIO_BRR_BR_12 GPIO_BRR_BR12
8081#define GPIO_BRR_BR_13 GPIO_BRR_BR13
8082#define GPIO_BRR_BR_14 GPIO_BRR_BR14
8083#define GPIO_BRR_BR_15 GPIO_BRR_BR15
8084
8085
8086
8087/******************************************************************************/
8088/* */
8089/* Inter-integrated Circuit Interface (I2C) */
8090/* */
8091/******************************************************************************/
8092/******************* Bit definition for I2C_CR1 register *******************/
8093#define I2C_CR1_PE_Pos (0U)
8094#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
8095#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
8096#define I2C_CR1_TXIE_Pos (1U)
8097#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
8098#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
8099#define I2C_CR1_RXIE_Pos (2U)
8100#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
8101#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
8102#define I2C_CR1_ADDRIE_Pos (3U)
8103#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
8104#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
8105#define I2C_CR1_NACKIE_Pos (4U)
8106#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
8107#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
8108#define I2C_CR1_STOPIE_Pos (5U)
8109#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
8110#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
8111#define I2C_CR1_TCIE_Pos (6U)
8112#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
8113#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
8114#define I2C_CR1_ERRIE_Pos (7U)
8115#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
8116#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
8117#define I2C_CR1_DNF_Pos (8U)
8118#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
8119#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
8120#define I2C_CR1_ANFOFF_Pos (12U)
8121#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
8122#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
8123#define I2C_CR1_SWRST_Pos (13U)
8124#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
8125#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
8126#define I2C_CR1_TXDMAEN_Pos (14U)
8127#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
8128#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
8129#define I2C_CR1_RXDMAEN_Pos (15U)
8130#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
8131#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
8132#define I2C_CR1_SBC_Pos (16U)
8133#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
8134#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
8135#define I2C_CR1_NOSTRETCH_Pos (17U)
8136#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
8137#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
8138#define I2C_CR1_WUPEN_Pos (18U)
8139#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
8140#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
8141#define I2C_CR1_GCEN_Pos (19U)
8142#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
8143#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
8144#define I2C_CR1_SMBHEN_Pos (20U)
8145#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
8146#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
8147#define I2C_CR1_SMBDEN_Pos (21U)
8148#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
8149#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
8150#define I2C_CR1_ALERTEN_Pos (22U)
8151#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
8152#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
8153#define I2C_CR1_PECEN_Pos (23U)
8154#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
8155#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
8156
8157/****************** Bit definition for I2C_CR2 register ********************/
8158#define I2C_CR2_SADD_Pos (0U)
8159#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
8160#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
8161#define I2C_CR2_RD_WRN_Pos (10U)
8162#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
8163#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
8164#define I2C_CR2_ADD10_Pos (11U)
8165#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
8166#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
8167#define I2C_CR2_HEAD10R_Pos (12U)
8168#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
8169#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
8170#define I2C_CR2_START_Pos (13U)
8171#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
8172#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
8173#define I2C_CR2_STOP_Pos (14U)
8174#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
8175#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
8176#define I2C_CR2_NACK_Pos (15U)
8177#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
8178#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
8179#define I2C_CR2_NBYTES_Pos (16U)
8180#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
8181#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
8182#define I2C_CR2_RELOAD_Pos (24U)
8183#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
8184#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
8185#define I2C_CR2_AUTOEND_Pos (25U)
8186#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
8187#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
8188#define I2C_CR2_PECBYTE_Pos (26U)
8189#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
8190#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
8191
8192/******************* Bit definition for I2C_OAR1 register ******************/
8193#define I2C_OAR1_OA1_Pos (0U)
8194#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
8195#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
8196#define I2C_OAR1_OA1MODE_Pos (10U)
8197#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
8198#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
8199#define I2C_OAR1_OA1EN_Pos (15U)
8200#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
8201#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
8202
8203/******************* Bit definition for I2C_OAR2 register ******************/
8204#define I2C_OAR2_OA2_Pos (1U)
8205#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
8206#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
8207#define I2C_OAR2_OA2MSK_Pos (8U)
8208#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
8209#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
8210#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
8211#define I2C_OAR2_OA2MASK01_Pos (8U)
8212#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
8213#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
8214#define I2C_OAR2_OA2MASK02_Pos (9U)
8215#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
8216#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
8217#define I2C_OAR2_OA2MASK03_Pos (8U)
8218#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
8219#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
8220#define I2C_OAR2_OA2MASK04_Pos (10U)
8221#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
8222#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
8223#define I2C_OAR2_OA2MASK05_Pos (8U)
8224#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
8225#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
8226#define I2C_OAR2_OA2MASK06_Pos (9U)
8227#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
8228#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
8229#define I2C_OAR2_OA2MASK07_Pos (8U)
8230#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
8231#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
8232#define I2C_OAR2_OA2EN_Pos (15U)
8233#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
8234#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
8235
8236/******************* Bit definition for I2C_TIMINGR register *******************/
8237#define I2C_TIMINGR_SCLL_Pos (0U)
8238#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
8239#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
8240#define I2C_TIMINGR_SCLH_Pos (8U)
8241#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
8242#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
8243#define I2C_TIMINGR_SDADEL_Pos (16U)
8244#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
8245#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
8246#define I2C_TIMINGR_SCLDEL_Pos (20U)
8247#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
8248#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
8249#define I2C_TIMINGR_PRESC_Pos (28U)
8250#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
8251#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
8252
8253/******************* Bit definition for I2C_TIMEOUTR register *******************/
8254#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
8255#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
8256#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
8257#define I2C_TIMEOUTR_TIDLE_Pos (12U)
8258#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
8259#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
8260#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
8261#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
8262#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
8263#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
8264#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
8265#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
8266#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
8267#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
8268#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
8269
8270/****************** Bit definition for I2C_ISR register *********************/
8271#define I2C_ISR_TXE_Pos (0U)
8272#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
8273#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
8274#define I2C_ISR_TXIS_Pos (1U)
8275#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
8276#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
8277#define I2C_ISR_RXNE_Pos (2U)
8278#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
8279#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
8280#define I2C_ISR_ADDR_Pos (3U)
8281#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
8282#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
8283#define I2C_ISR_NACKF_Pos (4U)
8284#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
8285#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
8286#define I2C_ISR_STOPF_Pos (5U)
8287#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
8288#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
8289#define I2C_ISR_TC_Pos (6U)
8290#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
8291#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
8292#define I2C_ISR_TCR_Pos (7U)
8293#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
8294#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
8295#define I2C_ISR_BERR_Pos (8U)
8296#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
8297#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
8298#define I2C_ISR_ARLO_Pos (9U)
8299#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
8300#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
8301#define I2C_ISR_OVR_Pos (10U)
8302#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
8303#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
8304#define I2C_ISR_PECERR_Pos (11U)
8305#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
8306#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
8307#define I2C_ISR_TIMEOUT_Pos (12U)
8308#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
8309#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
8310#define I2C_ISR_ALERT_Pos (13U)
8311#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
8312#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
8313#define I2C_ISR_BUSY_Pos (15U)
8314#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
8315#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
8316#define I2C_ISR_DIR_Pos (16U)
8317#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
8318#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
8319#define I2C_ISR_ADDCODE_Pos (17U)
8320#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
8321#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
8322
8323/****************** Bit definition for I2C_ICR register *********************/
8324#define I2C_ICR_ADDRCF_Pos (3U)
8325#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
8326#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
8327#define I2C_ICR_NACKCF_Pos (4U)
8328#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
8329#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
8330#define I2C_ICR_STOPCF_Pos (5U)
8331#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
8332#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
8333#define I2C_ICR_BERRCF_Pos (8U)
8334#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
8335#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
8336#define I2C_ICR_ARLOCF_Pos (9U)
8337#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
8338#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
8339#define I2C_ICR_OVRCF_Pos (10U)
8340#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
8341#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
8342#define I2C_ICR_PECCF_Pos (11U)
8343#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
8344#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
8345#define I2C_ICR_TIMOUTCF_Pos (12U)
8346#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
8347#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
8348#define I2C_ICR_ALERTCF_Pos (13U)
8349#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
8350#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
8351
8352/****************** Bit definition for I2C_PECR register *********************/
8353#define I2C_PECR_PEC_Pos (0U)
8354#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
8355#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
8356
8357/****************** Bit definition for I2C_RXDR register *********************/
8358#define I2C_RXDR_RXDATA_Pos (0U)
8359#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
8360#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
8361
8362/****************** Bit definition for I2C_TXDR register *********************/
8363#define I2C_TXDR_TXDATA_Pos (0U)
8364#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
8365#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
8366
8367/******************************************************************************/
8368/* */
8369/* Independent WATCHDOG */
8370/* */
8371/******************************************************************************/
8372/******************* Bit definition for IWDG_KR register ********************/
8373#define IWDG_KR_KEY_Pos (0U)
8374#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
8375#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
8376
8377/******************* Bit definition for IWDG_PR register ********************/
8378#define IWDG_PR_PR_Pos (0U)
8379#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
8380#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
8381#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
8382#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
8383#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
8384
8385/******************* Bit definition for IWDG_RLR register *******************/
8386#define IWDG_RLR_RL_Pos (0U)
8387#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
8388#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
8389
8390/******************* Bit definition for IWDG_SR register ********************/
8391#define IWDG_SR_PVU_Pos (0U)
8392#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
8393#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
8394#define IWDG_SR_RVU_Pos (1U)
8395#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
8396#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
8397#define IWDG_SR_WVU_Pos (2U)
8398#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
8399#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
8400
8401/******************* Bit definition for IWDG_KR register ********************/
8402#define IWDG_WINR_WIN_Pos (0U)
8403#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
8404#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
8405
8406/******************************************************************************/
8407/* */
8408/* Firewall */
8409/* */
8410/******************************************************************************/
8411
8412/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
8413#define FW_CSSA_ADD_Pos (8U)
8414#define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
8415#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
8416#define FW_CSL_LENG_Pos (8U)
8417#define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
8418#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
8419#define FW_NVDSSA_ADD_Pos (8U)
8420#define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
8421#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
8422#define FW_NVDSL_LENG_Pos (8U)
8423#define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
8424#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
8425#define FW_VDSSA_ADD_Pos (6U)
8426#define FW_VDSSA_ADD_Msk (0x7FFU << FW_VDSSA_ADD_Pos) /*!< 0x0001FFC0 */
8427#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
8428#define FW_VDSL_LENG_Pos (6U)
8429#define FW_VDSL_LENG_Msk (0x7FFU << FW_VDSL_LENG_Pos) /*!< 0x0001FFC0 */
8430#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
8431
8432/**************************Bit definition for CR register *********************/
8433#define FW_CR_FPA_Pos (0U)
8434#define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
8435#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
8436#define FW_CR_VDS_Pos (1U)
8437#define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
8438#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
8439#define FW_CR_VDE_Pos (2U)
8440#define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
8441#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
8442
8443/******************************************************************************/
8444/* */
8445/* Power Control */
8446/* */
8447/******************************************************************************/
8448
8449/******************** Bit definition for PWR_CR1 register ********************/
8450
8451#define PWR_CR1_LPR_Pos (14U)
8452#define PWR_CR1_LPR_Msk (0x1U << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
8453#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
8454#define PWR_CR1_VOS_Pos (9U)
8455#define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
8456#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
8457#define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
8458#define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
8459#define PWR_CR1_DBP_Pos (8U)
8460#define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
8461#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
8462#define PWR_CR1_LPMS_Pos (0U)
8463#define PWR_CR1_LPMS_Msk (0x7U << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
8464#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
8465#define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
8466#define PWR_CR1_LPMS_STOP1_Pos (0U)
8467#define PWR_CR1_LPMS_STOP1_Msk (0x1U << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
8468#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
8469#define PWR_CR1_LPMS_STOP2_Pos (1U)
8470#define PWR_CR1_LPMS_STOP2_Msk (0x1U << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */
8471#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
8472#define PWR_CR1_LPMS_STANDBY_Pos (0U)
8473#define PWR_CR1_LPMS_STANDBY_Msk (0x3U << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
8474#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
8475#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
8476#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
8477#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
8478
8479
8480/******************** Bit definition for PWR_CR2 register ********************/
8481#define PWR_CR2_USV_Pos (10U)
8482#define PWR_CR2_USV_Msk (0x1U << PWR_CR2_USV_Pos) /*!< 0x00000400 */
8483#define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */
8484/*!< PVME Peripheral Voltage Monitor Enable */
8485#define PWR_CR2_PVME_Pos (6U)
8486#define PWR_CR2_PVME_Msk (0x3U << PWR_CR2_PVME_Pos) /*!< 0x000000C0 */
8487#define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
8488#define PWR_CR2_PVME4_Pos (7U)
8489#define PWR_CR2_PVME4_Msk (0x1U << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
8490#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
8491#define PWR_CR2_PVME3_Pos (6U)
8492#define PWR_CR2_PVME3_Msk (0x1U << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
8493#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
8494/*!< PVD level configuration */
8495#define PWR_CR2_PLS_Pos (1U)
8496#define PWR_CR2_PLS_Msk (0x7U << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
8497#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
8498#define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
8499#define PWR_CR2_PLS_LEV1_Pos (1U)
8500#define PWR_CR2_PLS_LEV1_Msk (0x1U << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
8501#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
8502#define PWR_CR2_PLS_LEV2_Pos (2U)
8503#define PWR_CR2_PLS_LEV2_Msk (0x1U << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
8504#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
8505#define PWR_CR2_PLS_LEV3_Pos (1U)
8506#define PWR_CR2_PLS_LEV3_Msk (0x3U << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
8507#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
8508#define PWR_CR2_PLS_LEV4_Pos (3U)
8509#define PWR_CR2_PLS_LEV4_Msk (0x1U << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
8510#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
8511#define PWR_CR2_PLS_LEV5_Pos (1U)
8512#define PWR_CR2_PLS_LEV5_Msk (0x5U << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
8513#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
8514#define PWR_CR2_PLS_LEV6_Pos (2U)
8515#define PWR_CR2_PLS_LEV6_Msk (0x3U << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
8516#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
8517#define PWR_CR2_PLS_LEV7_Pos (1U)
8518#define PWR_CR2_PLS_LEV7_Msk (0x7U << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
8519#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
8520#define PWR_CR2_PVDE_Pos (0U)
8521#define PWR_CR2_PVDE_Msk (0x1U << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
8522#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
8523
8524/******************** Bit definition for PWR_CR3 register ********************/
8525#define PWR_CR3_EIWUL_Pos (15U)
8526#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
8527#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
8528#define PWR_CR3_APC_Pos (10U)
8529#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
8530#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
8531#define PWR_CR3_RRS_Pos (8U)
8532#define PWR_CR3_RRS_Msk (0x1U << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
8533#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
8534#define PWR_CR3_EWUP5_Pos (4U)
8535#define PWR_CR3_EWUP5_Msk (0x1U << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
8536#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
8537#define PWR_CR3_EWUP4_Pos (3U)
8538#define PWR_CR3_EWUP4_Msk (0x1U << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
8539#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
8540#define PWR_CR3_EWUP3_Pos (2U)
8541#define PWR_CR3_EWUP3_Msk (0x1U << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
8542#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
8543#define PWR_CR3_EWUP2_Pos (1U)
8544#define PWR_CR3_EWUP2_Msk (0x1U << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
8545#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
8546#define PWR_CR3_EWUP1_Pos (0U)
8547#define PWR_CR3_EWUP1_Msk (0x1U << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
8548#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
8549#define PWR_CR3_EWUP_Pos (0U)
8550#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
8551#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
8552
8553/* Legacy defines */
8554#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
8555#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
8556#define PWR_CR3_EIWF PWR_CR3_EIWUL
8557
8558
8559/******************** Bit definition for PWR_CR4 register ********************/
8560#define PWR_CR4_VBRS_Pos (9U)
8561#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
8562#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
8563#define PWR_CR4_VBE_Pos (8U)
8564#define PWR_CR4_VBE_Msk (0x1U << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
8565#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
8566#define PWR_CR4_WP5_Pos (4U)
8567#define PWR_CR4_WP5_Msk (0x1U << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
8568#define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
8569#define PWR_CR4_WP4_Pos (3U)
8570#define PWR_CR4_WP4_Msk (0x1U << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
8571#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
8572#define PWR_CR4_WP3_Pos (2U)
8573#define PWR_CR4_WP3_Msk (0x1U << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
8574#define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
8575#define PWR_CR4_WP2_Pos (1U)
8576#define PWR_CR4_WP2_Msk (0x1U << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
8577#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
8578#define PWR_CR4_WP1_Pos (0U)
8579#define PWR_CR4_WP1_Msk (0x1U << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
8580#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
8581
8582/******************** Bit definition for PWR_SR1 register ********************/
8583#define PWR_SR1_WUFI_Pos (15U)
8584#define PWR_SR1_WUFI_Msk (0x1U << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
8585#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
8586#define PWR_SR1_SBF_Pos (8U)
8587#define PWR_SR1_SBF_Msk (0x1U << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
8588#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
8589#define PWR_SR1_WUF_Pos (0U)
8590#define PWR_SR1_WUF_Msk (0x1FU << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
8591#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
8592#define PWR_SR1_WUF5_Pos (4U)
8593#define PWR_SR1_WUF5_Msk (0x1U << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
8594#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
8595#define PWR_SR1_WUF4_Pos (3U)
8596#define PWR_SR1_WUF4_Msk (0x1U << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
8597#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
8598#define PWR_SR1_WUF3_Pos (2U)
8599#define PWR_SR1_WUF3_Msk (0x1U << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
8600#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
8601#define PWR_SR1_WUF2_Pos (1U)
8602#define PWR_SR1_WUF2_Msk (0x1U << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
8603#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
8604#define PWR_SR1_WUF1_Pos (0U)
8605#define PWR_SR1_WUF1_Msk (0x1U << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
8606#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
8607
8608/******************** Bit definition for PWR_SR2 register ********************/
8609#define PWR_SR2_PVMO4_Pos (15U)
8610#define PWR_SR2_PVMO4_Msk (0x1U << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
8611#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
8612#define PWR_SR2_PVMO3_Pos (14U)
8613#define PWR_SR2_PVMO3_Msk (0x1U << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
8614#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
8615#define PWR_SR2_PVDO_Pos (11U)
8616#define PWR_SR2_PVDO_Msk (0x1U << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
8617#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
8618#define PWR_SR2_VOSF_Pos (10U)
8619#define PWR_SR2_VOSF_Msk (0x1U << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
8620#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
8621#define PWR_SR2_REGLPF_Pos (9U)
8622#define PWR_SR2_REGLPF_Msk (0x1U << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
8623#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
8624#define PWR_SR2_REGLPS_Pos (8U)
8625#define PWR_SR2_REGLPS_Msk (0x1U << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
8626#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
8627
8628/******************** Bit definition for PWR_SCR register ********************/
8629#define PWR_SCR_CSBF_Pos (8U)
8630#define PWR_SCR_CSBF_Msk (0x1U << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
8631#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
8632#define PWR_SCR_CWUF_Pos (0U)
8633#define PWR_SCR_CWUF_Msk (0x1FU << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
8634#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
8635#define PWR_SCR_CWUF5_Pos (4U)
8636#define PWR_SCR_CWUF5_Msk (0x1U << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
8637#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
8638#define PWR_SCR_CWUF4_Pos (3U)
8639#define PWR_SCR_CWUF4_Msk (0x1U << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
8640#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
8641#define PWR_SCR_CWUF3_Pos (2U)
8642#define PWR_SCR_CWUF3_Msk (0x1U << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
8643#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
8644#define PWR_SCR_CWUF2_Pos (1U)
8645#define PWR_SCR_CWUF2_Msk (0x1U << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
8646#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
8647#define PWR_SCR_CWUF1_Pos (0U)
8648#define PWR_SCR_CWUF1_Msk (0x1U << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
8649#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
8650
8651/******************** Bit definition for PWR_PUCRA register ********************/
8652#define PWR_PUCRA_PA15_Pos (15U)
8653#define PWR_PUCRA_PA15_Msk (0x1U << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
8654#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
8655#define PWR_PUCRA_PA13_Pos (13U)
8656#define PWR_PUCRA_PA13_Msk (0x1U << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
8657#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
8658#define PWR_PUCRA_PA12_Pos (12U)
8659#define PWR_PUCRA_PA12_Msk (0x1U << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
8660#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
8661#define PWR_PUCRA_PA11_Pos (11U)
8662#define PWR_PUCRA_PA11_Msk (0x1U << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
8663#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
8664#define PWR_PUCRA_PA10_Pos (10U)
8665#define PWR_PUCRA_PA10_Msk (0x1U << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
8666#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
8667#define PWR_PUCRA_PA9_Pos (9U)
8668#define PWR_PUCRA_PA9_Msk (0x1U << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
8669#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
8670#define PWR_PUCRA_PA8_Pos (8U)
8671#define PWR_PUCRA_PA8_Msk (0x1U << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
8672#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
8673#define PWR_PUCRA_PA7_Pos (7U)
8674#define PWR_PUCRA_PA7_Msk (0x1U << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
8675#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
8676#define PWR_PUCRA_PA6_Pos (6U)
8677#define PWR_PUCRA_PA6_Msk (0x1U << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
8678#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
8679#define PWR_PUCRA_PA5_Pos (5U)
8680#define PWR_PUCRA_PA5_Msk (0x1U << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
8681#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
8682#define PWR_PUCRA_PA4_Pos (4U)
8683#define PWR_PUCRA_PA4_Msk (0x1U << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
8684#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
8685#define PWR_PUCRA_PA3_Pos (3U)
8686#define PWR_PUCRA_PA3_Msk (0x1U << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
8687#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
8688#define PWR_PUCRA_PA2_Pos (2U)
8689#define PWR_PUCRA_PA2_Msk (0x1U << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
8690#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
8691#define PWR_PUCRA_PA1_Pos (1U)
8692#define PWR_PUCRA_PA1_Msk (0x1U << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
8693#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
8694#define PWR_PUCRA_PA0_Pos (0U)
8695#define PWR_PUCRA_PA0_Msk (0x1U << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
8696#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
8697
8698/******************** Bit definition for PWR_PDCRA register ********************/
8699#define PWR_PDCRA_PA14_Pos (14U)
8700#define PWR_PDCRA_PA14_Msk (0x1U << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
8701#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
8702#define PWR_PDCRA_PA12_Pos (12U)
8703#define PWR_PDCRA_PA12_Msk (0x1U << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
8704#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
8705#define PWR_PDCRA_PA11_Pos (11U)
8706#define PWR_PDCRA_PA11_Msk (0x1U << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
8707#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
8708#define PWR_PDCRA_PA10_Pos (10U)
8709#define PWR_PDCRA_PA10_Msk (0x1U << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
8710#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
8711#define PWR_PDCRA_PA9_Pos (9U)
8712#define PWR_PDCRA_PA9_Msk (0x1U << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
8713#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
8714#define PWR_PDCRA_PA8_Pos (8U)
8715#define PWR_PDCRA_PA8_Msk (0x1U << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
8716#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
8717#define PWR_PDCRA_PA7_Pos (7U)
8718#define PWR_PDCRA_PA7_Msk (0x1U << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
8719#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
8720#define PWR_PDCRA_PA6_Pos (6U)
8721#define PWR_PDCRA_PA6_Msk (0x1U << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
8722#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
8723#define PWR_PDCRA_PA5_Pos (5U)
8724#define PWR_PDCRA_PA5_Msk (0x1U << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
8725#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
8726#define PWR_PDCRA_PA4_Pos (4U)
8727#define PWR_PDCRA_PA4_Msk (0x1U << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
8728#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
8729#define PWR_PDCRA_PA3_Pos (3U)
8730#define PWR_PDCRA_PA3_Msk (0x1U << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
8731#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
8732#define PWR_PDCRA_PA2_Pos (2U)
8733#define PWR_PDCRA_PA2_Msk (0x1U << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
8734#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
8735#define PWR_PDCRA_PA1_Pos (1U)
8736#define PWR_PDCRA_PA1_Msk (0x1U << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
8737#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
8738#define PWR_PDCRA_PA0_Pos (0U)
8739#define PWR_PDCRA_PA0_Msk (0x1U << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
8740#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
8741
8742/******************** Bit definition for PWR_PUCRB register ********************/
8743#define PWR_PUCRB_PB7_Pos (7U)
8744#define PWR_PUCRB_PB7_Msk (0x1U << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
8745#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
8746#define PWR_PUCRB_PB6_Pos (6U)
8747#define PWR_PUCRB_PB6_Msk (0x1U << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
8748#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
8749#define PWR_PUCRB_PB5_Pos (5U)
8750#define PWR_PUCRB_PB5_Msk (0x1U << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
8751#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
8752#define PWR_PUCRB_PB4_Pos (4U)
8753#define PWR_PUCRB_PB4_Msk (0x1U << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
8754#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
8755#define PWR_PUCRB_PB3_Pos (3U)
8756#define PWR_PUCRB_PB3_Msk (0x1U << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
8757#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
8758#define PWR_PUCRB_PB1_Pos (1U)
8759#define PWR_PUCRB_PB1_Msk (0x1U << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
8760#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
8761#define PWR_PUCRB_PB0_Pos (0U)
8762#define PWR_PUCRB_PB0_Msk (0x1U << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
8763#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
8764
8765/******************** Bit definition for PWR_PDCRB register ********************/
8766#define PWR_PDCRB_PB7_Pos (7U)
8767#define PWR_PDCRB_PB7_Msk (0x1U << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
8768#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
8769#define PWR_PDCRB_PB6_Pos (6U)
8770#define PWR_PDCRB_PB6_Msk (0x1U << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
8771#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
8772#define PWR_PDCRB_PB5_Pos (5U)
8773#define PWR_PDCRB_PB5_Msk (0x1U << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
8774#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
8775#define PWR_PDCRB_PB3_Pos (3U)
8776#define PWR_PDCRB_PB3_Msk (0x1U << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
8777#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
8778#define PWR_PDCRB_PB1_Pos (1U)
8779#define PWR_PDCRB_PB1_Msk (0x1U << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
8780#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
8781#define PWR_PDCRB_PB0_Pos (0U)
8782#define PWR_PDCRB_PB0_Msk (0x1U << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
8783#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
8784
8785/******************** Bit definition for PWR_PUCRC register ********************/
8786#define PWR_PUCRC_PC15_Pos (15U)
8787#define PWR_PUCRC_PC15_Msk (0x1U << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
8788#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
8789#define PWR_PUCRC_PC14_Pos (14U)
8790#define PWR_PUCRC_PC14_Msk (0x1U << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
8791#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
8792
8793/******************** Bit definition for PWR_PDCRC register ********************/
8794#define PWR_PDCRC_PC15_Pos (15U)
8795#define PWR_PDCRC_PC15_Msk (0x1U << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
8796#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
8797#define PWR_PDCRC_PC14_Pos (14U)
8798#define PWR_PDCRC_PC14_Msk (0x1U << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
8799#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
8800
8801
8802
8803
8804/******************** Bit definition for PWR_PUCRH register ********************/
8805#define PWR_PUCRH_PH3_Pos (3U)
8806#define PWR_PUCRH_PH3_Msk (0x1U << PWR_PUCRH_PH3_Pos) /*!< 0x00000008 */
8807#define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Port PH3 Pull-Up set */
8808
8809/******************** Bit definition for PWR_PDCRH register ********************/
8810#define PWR_PDCRH_PH3_Pos (3U)
8811#define PWR_PDCRH_PH3_Msk (0x1U << PWR_PDCRH_PH3_Pos) /*!< 0x00000008 */
8812#define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Port PH3 Pull-Down set */
8813
8814
8815/******************************************************************************/
8816/* */
8817/* Reset and Clock Control */
8818/* */
8819/******************************************************************************/
8820/*
8821* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
8822*/
8823#define RCC_HSI48_SUPPORT
8824#define RCC_PLLP_DIV_2_31_SUPPORT
8825#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
8826
8827/******************** Bit definition for RCC_CR register ********************/
8828#define RCC_CR_MSION_Pos (0U)
8829#define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000001 */
8830#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */
8831#define RCC_CR_MSIRDY_Pos (1U)
8832#define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */
8833#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
8834#define RCC_CR_MSIPLLEN_Pos (2U)
8835#define RCC_CR_MSIPLLEN_Msk (0x1U << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */
8836#define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */
8837#define RCC_CR_MSIRGSEL_Pos (3U)
8838#define RCC_CR_MSIRGSEL_Msk (0x1U << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */
8839#define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */
8840
8841/*!< MSIRANGE configuration : 12 frequency ranges available */
8842#define RCC_CR_MSIRANGE_Pos (4U)
8843#define RCC_CR_MSIRANGE_Msk (0xFU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */
8844#define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */
8845#define RCC_CR_MSIRANGE_0 (0x0U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */
8846#define RCC_CR_MSIRANGE_1 (0x1U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */
8847#define RCC_CR_MSIRANGE_2 (0x2U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */
8848#define RCC_CR_MSIRANGE_3 (0x3U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */
8849#define RCC_CR_MSIRANGE_4 (0x4U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */
8850#define RCC_CR_MSIRANGE_5 (0x5U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */
8851#define RCC_CR_MSIRANGE_6 (0x6U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */
8852#define RCC_CR_MSIRANGE_7 (0x7U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */
8853#define RCC_CR_MSIRANGE_8 (0x8U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */
8854#define RCC_CR_MSIRANGE_9 (0x9U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */
8855#define RCC_CR_MSIRANGE_10 (0xAU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */
8856#define RCC_CR_MSIRANGE_11 (0xBU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */
8857
8858#define RCC_CR_HSION_Pos (8U)
8859#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000100 */
8860#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
8861#define RCC_CR_HSIKERON_Pos (9U)
8862#define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
8863#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
8864#define RCC_CR_HSIRDY_Pos (10U)
8865#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
8866#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
8867#define RCC_CR_HSIASFS_Pos (11U)
8868#define RCC_CR_HSIASFS_Msk (0x1U << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */
8869#define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */
8870
8871#define RCC_CR_HSEON_Pos (16U)
8872#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
8873#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
8874#define RCC_CR_HSERDY_Pos (17U)
8875#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
8876#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
8877#define RCC_CR_HSEBYP_Pos (18U)
8878#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
8879#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
8880#define RCC_CR_CSSON_Pos (19U)
8881#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
8882#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
8883
8884#define RCC_CR_PLLON_Pos (24U)
8885#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
8886#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
8887#define RCC_CR_PLLRDY_Pos (25U)
8888#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
8889#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
8890#define RCC_CR_PLLSAI1ON_Pos (26U)
8891#define RCC_CR_PLLSAI1ON_Msk (0x1U << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
8892#define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
8893#define RCC_CR_PLLSAI1RDY_Pos (27U)
8894#define RCC_CR_PLLSAI1RDY_Msk (0x1U << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */
8895#define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */
8896
8897/******************** Bit definition for RCC_ICSCR register ***************/
8898/*!< MSICAL configuration */
8899#define RCC_ICSCR_MSICAL_Pos (0U)
8900#define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */
8901#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */
8902#define RCC_ICSCR_MSICAL_0 (0x01U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */
8903#define RCC_ICSCR_MSICAL_1 (0x02U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */
8904#define RCC_ICSCR_MSICAL_2 (0x04U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */
8905#define RCC_ICSCR_MSICAL_3 (0x08U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */
8906#define RCC_ICSCR_MSICAL_4 (0x10U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */
8907#define RCC_ICSCR_MSICAL_5 (0x20U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */
8908#define RCC_ICSCR_MSICAL_6 (0x40U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */
8909#define RCC_ICSCR_MSICAL_7 (0x80U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */
8910
8911/*!< MSITRIM configuration */
8912#define RCC_ICSCR_MSITRIM_Pos (8U)
8913#define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
8914#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */
8915#define RCC_ICSCR_MSITRIM_0 (0x01U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
8916#define RCC_ICSCR_MSITRIM_1 (0x02U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
8917#define RCC_ICSCR_MSITRIM_2 (0x04U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
8918#define RCC_ICSCR_MSITRIM_3 (0x08U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
8919#define RCC_ICSCR_MSITRIM_4 (0x10U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
8920#define RCC_ICSCR_MSITRIM_5 (0x20U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
8921#define RCC_ICSCR_MSITRIM_6 (0x40U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
8922#define RCC_ICSCR_MSITRIM_7 (0x80U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
8923
8924/*!< HSICAL configuration */
8925#define RCC_ICSCR_HSICAL_Pos (16U)
8926#define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
8927#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
8928#define RCC_ICSCR_HSICAL_0 (0x01U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
8929#define RCC_ICSCR_HSICAL_1 (0x02U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
8930#define RCC_ICSCR_HSICAL_2 (0x04U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
8931#define RCC_ICSCR_HSICAL_3 (0x08U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
8932#define RCC_ICSCR_HSICAL_4 (0x10U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
8933#define RCC_ICSCR_HSICAL_5 (0x20U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
8934#define RCC_ICSCR_HSICAL_6 (0x40U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
8935#define RCC_ICSCR_HSICAL_7 (0x80U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
8936
8937/*!< HSITRIM configuration */
8938#define RCC_ICSCR_HSITRIM_Pos (24U)
8939#define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
8940#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
8941#define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
8942#define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
8943#define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
8944#define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
8945#define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
8946
8947/******************** Bit definition for RCC_CFGR register ******************/
8948/*!< SW configuration */
8949#define RCC_CFGR_SW_Pos (0U)
8950#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
8951#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
8952#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
8953#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
8954
8955#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI oscillator selection as system clock */
8956#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
8957#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
8958#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
8959
8960/*!< SWS configuration */
8961#define RCC_CFGR_SWS_Pos (2U)
8962#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
8963#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
8964#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
8965#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
8966
8967#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
8968#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
8969#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
8970#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
8971
8972/*!< HPRE configuration */
8973#define RCC_CFGR_HPRE_Pos (4U)
8974#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
8975#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
8976#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
8977#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
8978#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
8979#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
8980
8981#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
8982#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
8983#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
8984#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
8985#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
8986#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
8987#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
8988#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
8989#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
8990
8991/*!< PPRE1 configuration */
8992#define RCC_CFGR_PPRE1_Pos (8U)
8993#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
8994#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
8995#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
8996#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
8997#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
8998
8999#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
9000#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
9001#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
9002#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
9003#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
9004
9005/*!< PPRE2 configuration */
9006#define RCC_CFGR_PPRE2_Pos (11U)
9007#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
9008#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
9009#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
9010#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
9011#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
9012
9013#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
9014#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
9015#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
9016#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
9017#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
9018
9019#define RCC_CFGR_STOPWUCK_Pos (15U)
9020#define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
9021#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
9022
9023/*!< MCOSEL configuration */
9024#define RCC_CFGR_MCOSEL_Pos (24U)
9025#define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
9026#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
9027#define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
9028#define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
9029#define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
9030#define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
9031
9032#define RCC_CFGR_MCOPRE_Pos (28U)
9033#define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
9034#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
9035#define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
9036#define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
9037#define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
9038
9039#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
9040#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
9041#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
9042#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
9043#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
9044
9045/* Legacy aliases */
9046#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
9047#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
9048#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
9049#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
9050#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
9051#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
9052
9053/******************** Bit definition for RCC_PLLCFGR register ***************/
9054#define RCC_PLLCFGR_PLLSRC_Pos (0U)
9055#define RCC_PLLCFGR_PLLSRC_Msk (0x3U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
9056#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9057
9058#define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
9059#define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
9060#define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */
9061#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
9062#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
9063#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
9064#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
9065#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
9066#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
9067
9068#define RCC_PLLCFGR_PLLM_Pos (4U)
9069#define RCC_PLLCFGR_PLLM_Msk (0x7U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
9070#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9071#define RCC_PLLCFGR_PLLM_0 (0x1U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
9072#define RCC_PLLCFGR_PLLM_1 (0x2U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
9073#define RCC_PLLCFGR_PLLM_2 (0x4U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
9074
9075#define RCC_PLLCFGR_PLLN_Pos (8U)
9076#define RCC_PLLCFGR_PLLN_Msk (0x7FU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
9077#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9078#define RCC_PLLCFGR_PLLN_0 (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
9079#define RCC_PLLCFGR_PLLN_1 (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
9080#define RCC_PLLCFGR_PLLN_2 (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
9081#define RCC_PLLCFGR_PLLN_3 (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
9082#define RCC_PLLCFGR_PLLN_4 (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
9083#define RCC_PLLCFGR_PLLN_5 (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
9084#define RCC_PLLCFGR_PLLN_6 (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
9085
9086#define RCC_PLLCFGR_PLLPEN_Pos (16U)
9087#define RCC_PLLCFGR_PLLPEN_Msk (0x1U << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
9088#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
9089#define RCC_PLLCFGR_PLLP_Pos (17U)
9090#define RCC_PLLCFGR_PLLP_Msk (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
9091#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9092#define RCC_PLLCFGR_PLLQEN_Pos (20U)
9093#define RCC_PLLCFGR_PLLQEN_Msk (0x1U << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
9094#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
9095
9096#define RCC_PLLCFGR_PLLQ_Pos (21U)
9097#define RCC_PLLCFGR_PLLQ_Msk (0x3U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
9098#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9099#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
9100#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
9101
9102#define RCC_PLLCFGR_PLLREN_Pos (24U)
9103#define RCC_PLLCFGR_PLLREN_Msk (0x1U << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
9104#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
9105#define RCC_PLLCFGR_PLLR_Pos (25U)
9106#define RCC_PLLCFGR_PLLR_Msk (0x3U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
9107#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
9108#define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
9109#define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
9110
9111#define RCC_PLLCFGR_PLLPDIV_Pos (27U)
9112#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FU << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */
9113#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
9114#define RCC_PLLCFGR_PLLPDIV_0 (0x01U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */
9115#define RCC_PLLCFGR_PLLPDIV_1 (0x02U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */
9116#define RCC_PLLCFGR_PLLPDIV_2 (0x04U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */
9117#define RCC_PLLCFGR_PLLPDIV_3 (0x08U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */
9118#define RCC_PLLCFGR_PLLPDIV_4 (0x10U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */
9119
9120/******************** Bit definition for RCC_PLLSAI1CFGR register ************/
9121#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
9122#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
9123#define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
9124#define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
9125#define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
9126#define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
9127#define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
9128#define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
9129#define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
9130#define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
9131
9132#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
9133#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
9134#define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
9135#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
9136#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
9137#define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
9138
9139#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
9140#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
9141#define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
9142#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
9143#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
9144#define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
9145#define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
9146#define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
9147
9148#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
9149#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
9150#define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
9151#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
9152#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
9153#define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
9154#define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
9155#define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
9156
9157#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos (27U)
9158#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk (0x1FU << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */
9159#define RCC_PLLSAI1CFGR_PLLSAI1PDIV RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk
9160#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */
9161#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */
9162#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */
9163#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */
9164#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */
9165
9166/******************** Bit definition for RCC_CIER register ******************/
9167#define RCC_CIER_LSIRDYIE_Pos (0U)
9168#define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
9169#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
9170#define RCC_CIER_LSERDYIE_Pos (1U)
9171#define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
9172#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
9173#define RCC_CIER_MSIRDYIE_Pos (2U)
9174#define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */
9175#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
9176#define RCC_CIER_HSIRDYIE_Pos (3U)
9177#define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
9178#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
9179#define RCC_CIER_HSERDYIE_Pos (4U)
9180#define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
9181#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
9182#define RCC_CIER_PLLRDYIE_Pos (5U)
9183#define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
9184#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
9185#define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
9186#define RCC_CIER_PLLSAI1RDYIE_Msk (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
9187#define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
9188#define RCC_CIER_LSECSSIE_Pos (9U)
9189#define RCC_CIER_LSECSSIE_Msk (0x1U << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
9190#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
9191#define RCC_CIER_HSI48RDYIE_Pos (10U)
9192#define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */
9193#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
9194
9195/******************** Bit definition for RCC_CIFR register ******************/
9196#define RCC_CIFR_LSIRDYF_Pos (0U)
9197#define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
9198#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
9199#define RCC_CIFR_LSERDYF_Pos (1U)
9200#define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
9201#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
9202#define RCC_CIFR_MSIRDYF_Pos (2U)
9203#define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */
9204#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
9205#define RCC_CIFR_HSIRDYF_Pos (3U)
9206#define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
9207#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
9208#define RCC_CIFR_HSERDYF_Pos (4U)
9209#define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
9210#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
9211#define RCC_CIFR_PLLRDYF_Pos (5U)
9212#define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
9213#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
9214#define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
9215#define RCC_CIFR_PLLSAI1RDYF_Msk (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
9216#define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
9217#define RCC_CIFR_CSSF_Pos (8U)
9218#define RCC_CIFR_CSSF_Msk (0x1U << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
9219#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
9220#define RCC_CIFR_LSECSSF_Pos (9U)
9221#define RCC_CIFR_LSECSSF_Msk (0x1U << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
9222#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
9223#define RCC_CIFR_HSI48RDYF_Pos (10U)
9224#define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
9225#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
9226
9227/******************** Bit definition for RCC_CICR register ******************/
9228#define RCC_CICR_LSIRDYC_Pos (0U)
9229#define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
9230#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
9231#define RCC_CICR_LSERDYC_Pos (1U)
9232#define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
9233#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
9234#define RCC_CICR_MSIRDYC_Pos (2U)
9235#define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */
9236#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
9237#define RCC_CICR_HSIRDYC_Pos (3U)
9238#define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
9239#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
9240#define RCC_CICR_HSERDYC_Pos (4U)
9241#define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
9242#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
9243#define RCC_CICR_PLLRDYC_Pos (5U)
9244#define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
9245#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
9246#define RCC_CICR_PLLSAI1RDYC_Pos (6U)
9247#define RCC_CICR_PLLSAI1RDYC_Msk (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
9248#define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
9249#define RCC_CICR_CSSC_Pos (8U)
9250#define RCC_CICR_CSSC_Msk (0x1U << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
9251#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
9252#define RCC_CICR_LSECSSC_Pos (9U)
9253#define RCC_CICR_LSECSSC_Msk (0x1U << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
9254#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
9255#define RCC_CICR_HSI48RDYC_Pos (10U)
9256#define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
9257#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
9258
9259/******************** Bit definition for RCC_AHB1RSTR register **************/
9260#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
9261#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
9262#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
9263#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
9264#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
9265#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
9266#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
9267#define RCC_AHB1RSTR_FLASHRST_Msk (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
9268#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
9269#define RCC_AHB1RSTR_CRCRST_Pos (12U)
9270#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
9271#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
9272#define RCC_AHB1RSTR_TSCRST_Pos (16U)
9273#define RCC_AHB1RSTR_TSCRST_Msk (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
9274#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
9275
9276/******************** Bit definition for RCC_AHB2RSTR register **************/
9277#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
9278#define RCC_AHB2RSTR_GPIOARST_Msk (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
9279#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
9280#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
9281#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
9282#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
9283#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
9284#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
9285#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
9286#define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
9287#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
9288#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
9289#define RCC_AHB2RSTR_ADCRST_Pos (13U)
9290#define RCC_AHB2RSTR_ADCRST_Msk (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
9291#define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
9292#define RCC_AHB2RSTR_RNGRST_Pos (18U)
9293#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
9294#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
9295
9296/******************** Bit definition for RCC_AHB3RSTR register **************/
9297#define RCC_AHB3RSTR_QSPIRST_Pos (8U)
9298#define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
9299#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
9300
9301/******************** Bit definition for RCC_APB1RSTR1 register **************/
9302#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
9303#define RCC_APB1RSTR1_TIM2RST_Msk (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
9304#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
9305#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
9306#define RCC_APB1RSTR1_TIM6RST_Msk (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
9307#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
9308#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
9309#define RCC_APB1RSTR1_TIM7RST_Msk (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
9310#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
9311#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
9312#define RCC_APB1RSTR1_SPI3RST_Msk (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
9313#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
9314#define RCC_APB1RSTR1_USART2RST_Pos (17U)
9315#define RCC_APB1RSTR1_USART2RST_Msk (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
9316#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
9317#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
9318#define RCC_APB1RSTR1_I2C1RST_Msk (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
9319#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
9320#define RCC_APB1RSTR1_I2C3RST_Pos (23U)
9321#define RCC_APB1RSTR1_I2C3RST_Msk (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
9322#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
9323#define RCC_APB1RSTR1_CRSRST_Pos (24U)
9324#define RCC_APB1RSTR1_CRSRST_Msk (0x1U << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */
9325#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
9326#define RCC_APB1RSTR1_CAN1RST_Pos (25U)
9327#define RCC_APB1RSTR1_CAN1RST_Msk (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
9328#define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
9329#define RCC_APB1RSTR1_USBFSRST_Pos (26U)
9330#define RCC_APB1RSTR1_USBFSRST_Msk (0x1U << RCC_APB1RSTR1_USBFSRST_Pos) /*!< 0x04000000 */
9331#define RCC_APB1RSTR1_USBFSRST RCC_APB1RSTR1_USBFSRST_Msk
9332#define RCC_APB1RSTR1_PWRRST_Pos (28U)
9333#define RCC_APB1RSTR1_PWRRST_Msk (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
9334#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
9335#define RCC_APB1RSTR1_DAC1RST_Pos (29U)
9336#define RCC_APB1RSTR1_DAC1RST_Msk (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
9337#define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
9338#define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
9339#define RCC_APB1RSTR1_OPAMPRST_Msk (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
9340#define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
9341#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
9342#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
9343#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
9344
9345/******************** Bit definition for RCC_APB1RSTR2 register **************/
9346#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
9347#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
9348#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
9349#define RCC_APB1RSTR2_SWPMI1RST_Pos (2U)
9350#define RCC_APB1RSTR2_SWPMI1RST_Msk (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
9351#define RCC_APB1RSTR2_SWPMI1RST RCC_APB1RSTR2_SWPMI1RST_Msk
9352#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
9353#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
9354#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
9355
9356/******************** Bit definition for RCC_APB2RSTR register **************/
9357#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
9358#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
9359#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
9360#define RCC_APB2RSTR_TIM1RST_Pos (11U)
9361#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
9362#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
9363#define RCC_APB2RSTR_SPI1RST_Pos (12U)
9364#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
9365#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
9366#define RCC_APB2RSTR_USART1RST_Pos (14U)
9367#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
9368#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
9369#define RCC_APB2RSTR_TIM15RST_Pos (16U)
9370#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
9371#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
9372#define RCC_APB2RSTR_TIM16RST_Pos (17U)
9373#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
9374#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
9375#define RCC_APB2RSTR_SAI1RST_Pos (21U)
9376#define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
9377#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
9378
9379/******************** Bit definition for RCC_AHB1ENR register ***************/
9380#define RCC_AHB1ENR_DMA1EN_Pos (0U)
9381#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
9382#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
9383#define RCC_AHB1ENR_DMA2EN_Pos (1U)
9384#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
9385#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
9386#define RCC_AHB1ENR_FLASHEN_Pos (8U)
9387#define RCC_AHB1ENR_FLASHEN_Msk (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
9388#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
9389#define RCC_AHB1ENR_CRCEN_Pos (12U)
9390#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
9391#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
9392#define RCC_AHB1ENR_TSCEN_Pos (16U)
9393#define RCC_AHB1ENR_TSCEN_Msk (0x1U << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
9394#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
9395
9396/******************** Bit definition for RCC_AHB2ENR register ***************/
9397#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
9398#define RCC_AHB2ENR_GPIOAEN_Msk (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
9399#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
9400#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
9401#define RCC_AHB2ENR_GPIOBEN_Msk (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
9402#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
9403#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
9404#define RCC_AHB2ENR_GPIOCEN_Msk (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
9405#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
9406#define RCC_AHB2ENR_GPIOHEN_Pos (7U)
9407#define RCC_AHB2ENR_GPIOHEN_Msk (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
9408#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
9409#define RCC_AHB2ENR_ADCEN_Pos (13U)
9410#define RCC_AHB2ENR_ADCEN_Msk (0x1U << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */
9411#define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
9412#define RCC_AHB2ENR_RNGEN_Pos (18U)
9413#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
9414#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
9415
9416/******************** Bit definition for RCC_AHB3ENR register ***************/
9417#define RCC_AHB3ENR_QSPIEN_Pos (8U)
9418#define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
9419#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
9420
9421/******************** Bit definition for RCC_APB1ENR1 register ***************/
9422#define RCC_APB1ENR1_TIM2EN_Pos (0U)
9423#define RCC_APB1ENR1_TIM2EN_Msk (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
9424#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
9425#define RCC_APB1ENR1_TIM6EN_Pos (4U)
9426#define RCC_APB1ENR1_TIM6EN_Msk (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
9427#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
9428#define RCC_APB1ENR1_TIM7EN_Pos (5U)
9429#define RCC_APB1ENR1_TIM7EN_Msk (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
9430#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
9431#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
9432#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1U << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
9433#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
9434#define RCC_APB1ENR1_WWDGEN_Pos (11U)
9435#define RCC_APB1ENR1_WWDGEN_Msk (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
9436#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
9437#define RCC_APB1ENR1_SPI3EN_Pos (15U)
9438#define RCC_APB1ENR1_SPI3EN_Msk (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
9439#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
9440#define RCC_APB1ENR1_USART2EN_Pos (17U)
9441#define RCC_APB1ENR1_USART2EN_Msk (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
9442#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
9443#define RCC_APB1ENR1_I2C1EN_Pos (21U)
9444#define RCC_APB1ENR1_I2C1EN_Msk (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
9445#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
9446#define RCC_APB1ENR1_I2C3EN_Pos (23U)
9447#define RCC_APB1ENR1_I2C3EN_Msk (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
9448#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
9449#define RCC_APB1ENR1_CRSEN_Pos (24U)
9450#define RCC_APB1ENR1_CRSEN_Msk (0x1U << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x01000000 */
9451#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
9452#define RCC_APB1ENR1_CAN1EN_Pos (25U)
9453#define RCC_APB1ENR1_CAN1EN_Msk (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
9454#define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
9455#define RCC_APB1ENR1_USBFSEN_Pos (26U)
9456#define RCC_APB1ENR1_USBFSEN_Msk (0x1U << RCC_APB1ENR1_USBFSEN_Pos) /*!< 0x04000000 */
9457#define RCC_APB1ENR1_USBFSEN RCC_APB1ENR1_USBFSEN_Msk
9458#define RCC_APB1ENR1_PWREN_Pos (28U)
9459#define RCC_APB1ENR1_PWREN_Msk (0x1U << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
9460#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
9461#define RCC_APB1ENR1_DAC1EN_Pos (29U)
9462#define RCC_APB1ENR1_DAC1EN_Msk (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
9463#define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
9464#define RCC_APB1ENR1_OPAMPEN_Pos (30U)
9465#define RCC_APB1ENR1_OPAMPEN_Msk (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
9466#define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
9467#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
9468#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
9469#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
9470
9471/******************** Bit definition for RCC_APB1RSTR2 register **************/
9472#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
9473#define RCC_APB1ENR2_LPUART1EN_Msk (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
9474#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
9475#define RCC_APB1ENR2_SWPMI1EN_Pos (2U)
9476#define RCC_APB1ENR2_SWPMI1EN_Msk (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
9477#define RCC_APB1ENR2_SWPMI1EN RCC_APB1ENR2_SWPMI1EN_Msk
9478#define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
9479#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
9480#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
9481
9482/******************** Bit definition for RCC_APB2ENR register ***************/
9483#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
9484#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
9485#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
9486#define RCC_APB2ENR_FWEN_Pos (7U)
9487#define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
9488#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
9489#define RCC_APB2ENR_TIM1EN_Pos (11U)
9490#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
9491#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
9492#define RCC_APB2ENR_SPI1EN_Pos (12U)
9493#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
9494#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
9495#define RCC_APB2ENR_USART1EN_Pos (14U)
9496#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
9497#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
9498#define RCC_APB2ENR_TIM15EN_Pos (16U)
9499#define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
9500#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
9501#define RCC_APB2ENR_TIM16EN_Pos (17U)
9502#define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
9503#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
9504#define RCC_APB2ENR_SAI1EN_Pos (21U)
9505#define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
9506#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
9507
9508/******************** Bit definition for RCC_AHB1SMENR register ***************/
9509#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
9510#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
9511#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
9512#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
9513#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
9514#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
9515#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
9516#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
9517#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
9518#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
9519#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
9520#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
9521#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
9522#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
9523#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
9524#define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
9525#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
9526#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
9527
9528/******************** Bit definition for RCC_AHB2SMENR register *************/
9529#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
9530#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
9531#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
9532#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
9533#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
9534#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
9535#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
9536#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
9537#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
9538#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
9539#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
9540#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
9541#define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
9542#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
9543#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
9544#define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
9545#define RCC_AHB2SMENR_ADCSMEN_Msk (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
9546#define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
9547#define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
9548#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
9549#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
9550
9551/******************** Bit definition for RCC_AHB3SMENR register *************/
9552#define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
9553#define RCC_AHB3SMENR_QSPISMEN_Msk (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
9554#define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
9555
9556/******************** Bit definition for RCC_APB1SMENR1 register *************/
9557#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
9558#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
9559#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
9560#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
9561#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
9562#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
9563#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
9564#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
9565#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
9566#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
9567#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1U << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
9568#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
9569#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
9570#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
9571#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
9572#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
9573#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
9574#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
9575#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
9576#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
9577#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
9578#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
9579#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
9580#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
9581#define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
9582#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
9583#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
9584#define RCC_APB1SMENR1_CRSSMEN_Pos (24U)
9585#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1U << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
9586#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
9587#define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
9588#define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
9589#define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
9590#define RCC_APB1SMENR1_USBFSSMEN_Pos (26U)
9591#define RCC_APB1SMENR1_USBFSSMEN_Msk (0x1U << RCC_APB1SMENR1_USBFSSMEN_Pos) /*!< 0x04000000 */
9592#define RCC_APB1SMENR1_USBFSSMEN RCC_APB1SMENR1_USBFSSMEN_Msk
9593#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
9594#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
9595#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
9596#define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
9597#define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
9598#define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
9599#define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
9600#define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
9601#define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
9602#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
9603#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
9604#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
9605
9606/******************** Bit definition for RCC_APB1SMENR2 register *************/
9607#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
9608#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
9609#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
9610#define RCC_APB1SMENR2_SWPMI1SMEN_Pos (2U)
9611#define RCC_APB1SMENR2_SWPMI1SMEN_Msk (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
9612#define RCC_APB1SMENR2_SWPMI1SMEN RCC_APB1SMENR2_SWPMI1SMEN_Msk
9613#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
9614#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
9615#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
9616
9617/******************** Bit definition for RCC_APB2SMENR register *************/
9618#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
9619#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
9620#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
9621#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
9622#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
9623#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
9624#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
9625#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
9626#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
9627#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
9628#define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
9629#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
9630#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
9631#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
9632#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
9633#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
9634#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
9635#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
9636#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
9637#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
9638#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
9639
9640/******************** Bit definition for RCC_CCIPR register ******************/
9641#define RCC_CCIPR_USART1SEL_Pos (0U)
9642#define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
9643#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
9644#define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
9645#define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
9646
9647#define RCC_CCIPR_USART2SEL_Pos (2U)
9648#define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
9649#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
9650#define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
9651#define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
9652
9653#define RCC_CCIPR_LPUART1SEL_Pos (10U)
9654#define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
9655#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
9656#define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
9657#define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
9658
9659#define RCC_CCIPR_I2C1SEL_Pos (12U)
9660#define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
9661#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
9662#define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
9663#define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
9664
9665#define RCC_CCIPR_I2C3SEL_Pos (16U)
9666#define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
9667#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
9668#define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
9669#define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
9670
9671#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
9672#define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
9673#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
9674#define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
9675#define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
9676
9677#define RCC_CCIPR_LPTIM2SEL_Pos (20U)
9678#define RCC_CCIPR_LPTIM2SEL_Msk (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
9679#define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
9680#define RCC_CCIPR_LPTIM2SEL_0 (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
9681#define RCC_CCIPR_LPTIM2SEL_1 (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
9682
9683#define RCC_CCIPR_SAI1SEL_Pos (22U)
9684#define RCC_CCIPR_SAI1SEL_Msk (0x3U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00C00000 */
9685#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
9686#define RCC_CCIPR_SAI1SEL_0 (0x1U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00400000 */
9687#define RCC_CCIPR_SAI1SEL_1 (0x2U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00800000 */
9688
9689#define RCC_CCIPR_CLK48SEL_Pos (26U)
9690#define RCC_CCIPR_CLK48SEL_Msk (0x3U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
9691#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
9692#define RCC_CCIPR_CLK48SEL_0 (0x1U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
9693#define RCC_CCIPR_CLK48SEL_1 (0x2U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
9694
9695#define RCC_CCIPR_ADCSEL_Pos (28U)
9696#define RCC_CCIPR_ADCSEL_Msk (0x3U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */
9697#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
9698#define RCC_CCIPR_ADCSEL_0 (0x1U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */
9699#define RCC_CCIPR_ADCSEL_1 (0x2U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */
9700
9701#define RCC_CCIPR_SWPMI1SEL_Pos (30U)
9702#define RCC_CCIPR_SWPMI1SEL_Msk (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
9703#define RCC_CCIPR_SWPMI1SEL RCC_CCIPR_SWPMI1SEL_Msk
9704
9705/******************** Bit definition for RCC_BDCR register ******************/
9706#define RCC_BDCR_LSEON_Pos (0U)
9707#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
9708#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
9709#define RCC_BDCR_LSERDY_Pos (1U)
9710#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
9711#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
9712#define RCC_BDCR_LSEBYP_Pos (2U)
9713#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
9714#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
9715
9716#define RCC_BDCR_LSEDRV_Pos (3U)
9717#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
9718#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
9719#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
9720#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
9721
9722#define RCC_BDCR_LSECSSON_Pos (5U)
9723#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
9724#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
9725#define RCC_BDCR_LSECSSD_Pos (6U)
9726#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
9727#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
9728
9729#define RCC_BDCR_RTCSEL_Pos (8U)
9730#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
9731#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
9732#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
9733#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
9734
9735#define RCC_BDCR_RTCEN_Pos (15U)
9736#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
9737#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
9738#define RCC_BDCR_BDRST_Pos (16U)
9739#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
9740#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
9741#define RCC_BDCR_LSCOEN_Pos (24U)
9742#define RCC_BDCR_LSCOEN_Msk (0x1U << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
9743#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
9744#define RCC_BDCR_LSCOSEL_Pos (25U)
9745#define RCC_BDCR_LSCOSEL_Msk (0x1U << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
9746#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
9747
9748/******************** Bit definition for RCC_CSR register *******************/
9749#define RCC_CSR_LSION_Pos (0U)
9750#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
9751#define RCC_CSR_LSION RCC_CSR_LSION_Msk
9752#define RCC_CSR_LSIRDY_Pos (1U)
9753#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
9754#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
9755
9756#define RCC_CSR_MSISRANGE_Pos (8U)
9757#define RCC_CSR_MSISRANGE_Msk (0xFU << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */
9758#define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
9759#define RCC_CSR_MSISRANGE_1 (0x4U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */
9760#define RCC_CSR_MSISRANGE_2 (0x5U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */
9761#define RCC_CSR_MSISRANGE_4 (0x6U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */
9762#define RCC_CSR_MSISRANGE_8 (0x7U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */
9763
9764#define RCC_CSR_RMVF_Pos (23U)
9765#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
9766#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
9767#define RCC_CSR_FWRSTF_Pos (24U)
9768#define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
9769#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
9770#define RCC_CSR_OBLRSTF_Pos (25U)
9771#define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
9772#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
9773#define RCC_CSR_PINRSTF_Pos (26U)
9774#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
9775#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
9776#define RCC_CSR_BORRSTF_Pos (27U)
9777#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
9778#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
9779#define RCC_CSR_SFTRSTF_Pos (28U)
9780#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
9781#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
9782#define RCC_CSR_IWDGRSTF_Pos (29U)
9783#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
9784#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
9785#define RCC_CSR_WWDGRSTF_Pos (30U)
9786#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
9787#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
9788#define RCC_CSR_LPWRRSTF_Pos (31U)
9789#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
9790#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
9791
9792/******************** Bit definition for RCC_CRRCR register *****************/
9793#define RCC_CRRCR_HSI48ON_Pos (0U)
9794#define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
9795#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
9796#define RCC_CRRCR_HSI48RDY_Pos (1U)
9797#define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
9798#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
9799
9800/*!< HSI48CAL configuration */
9801#define RCC_CRRCR_HSI48CAL_Pos (7U)
9802#define RCC_CRRCR_HSI48CAL_Msk (0x1FFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */
9803#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
9804#define RCC_CRRCR_HSI48CAL_0 (0x001U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
9805#define RCC_CRRCR_HSI48CAL_1 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
9806#define RCC_CRRCR_HSI48CAL_2 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
9807#define RCC_CRRCR_HSI48CAL_3 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */
9808#define RCC_CRRCR_HSI48CAL_4 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */
9809#define RCC_CRRCR_HSI48CAL_5 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */
9810#define RCC_CRRCR_HSI48CAL_6 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */
9811#define RCC_CRRCR_HSI48CAL_7 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */
9812#define RCC_CRRCR_HSI48CAL_8 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */
9813
9814/******************************************************************************/
9815/* */
9816/* RNG */
9817/* */
9818/******************************************************************************/
9819/******************** Bits definition for RNG_CR register *******************/
9820#define RNG_CR_RNGEN_Pos (2U)
9821#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
9822#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
9823#define RNG_CR_IE_Pos (3U)
9824#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
9825#define RNG_CR_IE RNG_CR_IE_Msk
9826
9827/******************** Bits definition for RNG_SR register *******************/
9828#define RNG_SR_DRDY_Pos (0U)
9829#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
9830#define RNG_SR_DRDY RNG_SR_DRDY_Msk
9831#define RNG_SR_CECS_Pos (1U)
9832#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
9833#define RNG_SR_CECS RNG_SR_CECS_Msk
9834#define RNG_SR_SECS_Pos (2U)
9835#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
9836#define RNG_SR_SECS RNG_SR_SECS_Msk
9837#define RNG_SR_CEIS_Pos (5U)
9838#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
9839#define RNG_SR_CEIS RNG_SR_CEIS_Msk
9840#define RNG_SR_SEIS_Pos (6U)
9841#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
9842#define RNG_SR_SEIS RNG_SR_SEIS_Msk
9843
9844/******************************************************************************/
9845/* */
9846/* Real-Time Clock (RTC) */
9847/* */
9848/******************************************************************************/
9849/*
9850* @brief Specific device feature definitions
9851*/
9852#define RTC_TAMPER2_SUPPORT
9853#define RTC_WAKEUP_SUPPORT
9854#define RTC_BACKUP_SUPPORT
9855
9856/******************** Bits definition for RTC_TR register *******************/
9857#define RTC_TR_PM_Pos (22U)
9858#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
9859#define RTC_TR_PM RTC_TR_PM_Msk
9860#define RTC_TR_HT_Pos (20U)
9861#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
9862#define RTC_TR_HT RTC_TR_HT_Msk
9863#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
9864#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
9865#define RTC_TR_HU_Pos (16U)
9866#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
9867#define RTC_TR_HU RTC_TR_HU_Msk
9868#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
9869#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
9870#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
9871#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
9872#define RTC_TR_MNT_Pos (12U)
9873#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
9874#define RTC_TR_MNT RTC_TR_MNT_Msk
9875#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
9876#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
9877#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
9878#define RTC_TR_MNU_Pos (8U)
9879#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
9880#define RTC_TR_MNU RTC_TR_MNU_Msk
9881#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
9882#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
9883#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
9884#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
9885#define RTC_TR_ST_Pos (4U)
9886#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
9887#define RTC_TR_ST RTC_TR_ST_Msk
9888#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
9889#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
9890#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
9891#define RTC_TR_SU_Pos (0U)
9892#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
9893#define RTC_TR_SU RTC_TR_SU_Msk
9894#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
9895#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
9896#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
9897#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
9898
9899/******************** Bits definition for RTC_DR register *******************/
9900#define RTC_DR_YT_Pos (20U)
9901#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
9902#define RTC_DR_YT RTC_DR_YT_Msk
9903#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
9904#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
9905#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
9906#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
9907#define RTC_DR_YU_Pos (16U)
9908#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
9909#define RTC_DR_YU RTC_DR_YU_Msk
9910#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
9911#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
9912#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
9913#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
9914#define RTC_DR_WDU_Pos (13U)
9915#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
9916#define RTC_DR_WDU RTC_DR_WDU_Msk
9917#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
9918#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
9919#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
9920#define RTC_DR_MT_Pos (12U)
9921#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
9922#define RTC_DR_MT RTC_DR_MT_Msk
9923#define RTC_DR_MU_Pos (8U)
9924#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
9925#define RTC_DR_MU RTC_DR_MU_Msk
9926#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
9927#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
9928#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
9929#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
9930#define RTC_DR_DT_Pos (4U)
9931#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
9932#define RTC_DR_DT RTC_DR_DT_Msk
9933#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
9934#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
9935#define RTC_DR_DU_Pos (0U)
9936#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
9937#define RTC_DR_DU RTC_DR_DU_Msk
9938#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
9939#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
9940#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
9941#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
9942
9943/******************** Bits definition for RTC_CR register *******************/
9944#define RTC_CR_ITSE_Pos (24U)
9945#define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
9946#define RTC_CR_ITSE RTC_CR_ITSE_Msk
9947#define RTC_CR_COE_Pos (23U)
9948#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
9949#define RTC_CR_COE RTC_CR_COE_Msk
9950#define RTC_CR_OSEL_Pos (21U)
9951#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
9952#define RTC_CR_OSEL RTC_CR_OSEL_Msk
9953#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
9954#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
9955#define RTC_CR_POL_Pos (20U)
9956#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
9957#define RTC_CR_POL RTC_CR_POL_Msk
9958#define RTC_CR_COSEL_Pos (19U)
9959#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
9960#define RTC_CR_COSEL RTC_CR_COSEL_Msk
9961#define RTC_CR_BKP_Pos (18U)
9962#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
9963#define RTC_CR_BKP RTC_CR_BKP_Msk
9964#define RTC_CR_SUB1H_Pos (17U)
9965#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
9966#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
9967#define RTC_CR_ADD1H_Pos (16U)
9968#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
9969#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
9970#define RTC_CR_TSIE_Pos (15U)
9971#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
9972#define RTC_CR_TSIE RTC_CR_TSIE_Msk
9973#define RTC_CR_WUTIE_Pos (14U)
9974#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
9975#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
9976#define RTC_CR_ALRBIE_Pos (13U)
9977#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
9978#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
9979#define RTC_CR_ALRAIE_Pos (12U)
9980#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
9981#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
9982#define RTC_CR_TSE_Pos (11U)
9983#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
9984#define RTC_CR_TSE RTC_CR_TSE_Msk
9985#define RTC_CR_WUTE_Pos (10U)
9986#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
9987#define RTC_CR_WUTE RTC_CR_WUTE_Msk
9988#define RTC_CR_ALRBE_Pos (9U)
9989#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
9990#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
9991#define RTC_CR_ALRAE_Pos (8U)
9992#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
9993#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
9994#define RTC_CR_FMT_Pos (6U)
9995#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
9996#define RTC_CR_FMT RTC_CR_FMT_Msk
9997#define RTC_CR_BYPSHAD_Pos (5U)
9998#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
9999#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
10000#define RTC_CR_REFCKON_Pos (4U)
10001#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
10002#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
10003#define RTC_CR_TSEDGE_Pos (3U)
10004#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
10005#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
10006#define RTC_CR_WUCKSEL_Pos (0U)
10007#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
10008#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
10009#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
10010#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
10011#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
10012
10013/* Legacy defines */
10014#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
10015#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
10016#define RTC_CR_BCK RTC_CR_BKP
10017
10018/******************** Bits definition for RTC_ISR register ******************/
10019#define RTC_ISR_ITSF_Pos (17U)
10020#define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
10021#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
10022#define RTC_ISR_RECALPF_Pos (16U)
10023#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
10024#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
10025#define RTC_ISR_TAMP2F_Pos (14U)
10026#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
10027#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
10028#define RTC_ISR_TSOVF_Pos (12U)
10029#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
10030#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
10031#define RTC_ISR_TSF_Pos (11U)
10032#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
10033#define RTC_ISR_TSF RTC_ISR_TSF_Msk
10034#define RTC_ISR_WUTF_Pos (10U)
10035#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
10036#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
10037#define RTC_ISR_ALRBF_Pos (9U)
10038#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
10039#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
10040#define RTC_ISR_ALRAF_Pos (8U)
10041#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
10042#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
10043#define RTC_ISR_INIT_Pos (7U)
10044#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
10045#define RTC_ISR_INIT RTC_ISR_INIT_Msk
10046#define RTC_ISR_INITF_Pos (6U)
10047#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
10048#define RTC_ISR_INITF RTC_ISR_INITF_Msk
10049#define RTC_ISR_RSF_Pos (5U)
10050#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
10051#define RTC_ISR_RSF RTC_ISR_RSF_Msk
10052#define RTC_ISR_INITS_Pos (4U)
10053#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
10054#define RTC_ISR_INITS RTC_ISR_INITS_Msk
10055#define RTC_ISR_SHPF_Pos (3U)
10056#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
10057#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
10058#define RTC_ISR_WUTWF_Pos (2U)
10059#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
10060#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
10061#define RTC_ISR_ALRBWF_Pos (1U)
10062#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
10063#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
10064#define RTC_ISR_ALRAWF_Pos (0U)
10065#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
10066#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
10067
10068/******************** Bits definition for RTC_PRER register *****************/
10069#define RTC_PRER_PREDIV_A_Pos (16U)
10070#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
10071#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
10072#define RTC_PRER_PREDIV_S_Pos (0U)
10073#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
10074#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
10075
10076/******************** Bits definition for RTC_WUTR register *****************/
10077#define RTC_WUTR_WUT_Pos (0U)
10078#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
10079#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
10080
10081/******************** Bits definition for RTC_ALRMAR register ***************/
10082#define RTC_ALRMAR_MSK4_Pos (31U)
10083#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
10084#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
10085#define RTC_ALRMAR_WDSEL_Pos (30U)
10086#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
10087#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
10088#define RTC_ALRMAR_DT_Pos (28U)
10089#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
10090#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
10091#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
10092#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
10093#define RTC_ALRMAR_DU_Pos (24U)
10094#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
10095#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
10096#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
10097#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
10098#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
10099#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
10100#define RTC_ALRMAR_MSK3_Pos (23U)
10101#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
10102#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
10103#define RTC_ALRMAR_PM_Pos (22U)
10104#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
10105#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
10106#define RTC_ALRMAR_HT_Pos (20U)
10107#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
10108#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
10109#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
10110#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
10111#define RTC_ALRMAR_HU_Pos (16U)
10112#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
10113#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
10114#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
10115#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
10116#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
10117#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
10118#define RTC_ALRMAR_MSK2_Pos (15U)
10119#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
10120#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
10121#define RTC_ALRMAR_MNT_Pos (12U)
10122#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
10123#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
10124#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
10125#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
10126#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
10127#define RTC_ALRMAR_MNU_Pos (8U)
10128#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
10129#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
10130#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
10131#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
10132#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
10133#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
10134#define RTC_ALRMAR_MSK1_Pos (7U)
10135#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
10136#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
10137#define RTC_ALRMAR_ST_Pos (4U)
10138#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
10139#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
10140#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
10141#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
10142#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
10143#define RTC_ALRMAR_SU_Pos (0U)
10144#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
10145#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
10146#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
10147#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
10148#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
10149#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
10150
10151/******************** Bits definition for RTC_ALRMBR register ***************/
10152#define RTC_ALRMBR_MSK4_Pos (31U)
10153#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
10154#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
10155#define RTC_ALRMBR_WDSEL_Pos (30U)
10156#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
10157#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
10158#define RTC_ALRMBR_DT_Pos (28U)
10159#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
10160#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
10161#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
10162#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
10163#define RTC_ALRMBR_DU_Pos (24U)
10164#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
10165#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
10166#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
10167#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
10168#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
10169#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
10170#define RTC_ALRMBR_MSK3_Pos (23U)
10171#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
10172#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
10173#define RTC_ALRMBR_PM_Pos (22U)
10174#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
10175#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
10176#define RTC_ALRMBR_HT_Pos (20U)
10177#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
10178#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
10179#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
10180#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
10181#define RTC_ALRMBR_HU_Pos (16U)
10182#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
10183#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
10184#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
10185#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
10186#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
10187#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
10188#define RTC_ALRMBR_MSK2_Pos (15U)
10189#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
10190#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
10191#define RTC_ALRMBR_MNT_Pos (12U)
10192#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
10193#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
10194#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
10195#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
10196#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
10197#define RTC_ALRMBR_MNU_Pos (8U)
10198#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
10199#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
10200#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
10201#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
10202#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
10203#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
10204#define RTC_ALRMBR_MSK1_Pos (7U)
10205#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
10206#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
10207#define RTC_ALRMBR_ST_Pos (4U)
10208#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
10209#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
10210#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
10211#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
10212#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
10213#define RTC_ALRMBR_SU_Pos (0U)
10214#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
10215#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
10216#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
10217#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
10218#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
10219#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
10220
10221/******************** Bits definition for RTC_WPR register ******************/
10222#define RTC_WPR_KEY_Pos (0U)
10223#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
10224#define RTC_WPR_KEY RTC_WPR_KEY_Msk
10225
10226/******************** Bits definition for RTC_SSR register ******************/
10227#define RTC_SSR_SS_Pos (0U)
10228#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
10229#define RTC_SSR_SS RTC_SSR_SS_Msk
10230
10231/******************** Bits definition for RTC_SHIFTR register ***************/
10232#define RTC_SHIFTR_SUBFS_Pos (0U)
10233#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
10234#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
10235#define RTC_SHIFTR_ADD1S_Pos (31U)
10236#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
10237#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
10238
10239/******************** Bits definition for RTC_TSTR register *****************/
10240#define RTC_TSTR_PM_Pos (22U)
10241#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
10242#define RTC_TSTR_PM RTC_TSTR_PM_Msk
10243#define RTC_TSTR_HT_Pos (20U)
10244#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
10245#define RTC_TSTR_HT RTC_TSTR_HT_Msk
10246#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
10247#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
10248#define RTC_TSTR_HU_Pos (16U)
10249#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
10250#define RTC_TSTR_HU RTC_TSTR_HU_Msk
10251#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
10252#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
10253#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
10254#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
10255#define RTC_TSTR_MNT_Pos (12U)
10256#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
10257#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
10258#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
10259#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
10260#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
10261#define RTC_TSTR_MNU_Pos (8U)
10262#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
10263#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
10264#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
10265#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
10266#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
10267#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
10268#define RTC_TSTR_ST_Pos (4U)
10269#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
10270#define RTC_TSTR_ST RTC_TSTR_ST_Msk
10271#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
10272#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
10273#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
10274#define RTC_TSTR_SU_Pos (0U)
10275#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
10276#define RTC_TSTR_SU RTC_TSTR_SU_Msk
10277#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
10278#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
10279#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
10280#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
10281
10282/******************** Bits definition for RTC_TSDR register *****************/
10283#define RTC_TSDR_WDU_Pos (13U)
10284#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
10285#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
10286#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
10287#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
10288#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
10289#define RTC_TSDR_MT_Pos (12U)
10290#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
10291#define RTC_TSDR_MT RTC_TSDR_MT_Msk
10292#define RTC_TSDR_MU_Pos (8U)
10293#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
10294#define RTC_TSDR_MU RTC_TSDR_MU_Msk
10295#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
10296#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
10297#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
10298#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
10299#define RTC_TSDR_DT_Pos (4U)
10300#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
10301#define RTC_TSDR_DT RTC_TSDR_DT_Msk
10302#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
10303#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
10304#define RTC_TSDR_DU_Pos (0U)
10305#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
10306#define RTC_TSDR_DU RTC_TSDR_DU_Msk
10307#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
10308#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
10309#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
10310#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
10311
10312/******************** Bits definition for RTC_TSSSR register ****************/
10313#define RTC_TSSSR_SS_Pos (0U)
10314#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
10315#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
10316
10317/******************** Bits definition for RTC_CAL register *****************/
10318#define RTC_CALR_CALP_Pos (15U)
10319#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
10320#define RTC_CALR_CALP RTC_CALR_CALP_Msk
10321#define RTC_CALR_CALW8_Pos (14U)
10322#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
10323#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
10324#define RTC_CALR_CALW16_Pos (13U)
10325#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
10326#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
10327#define RTC_CALR_CALM_Pos (0U)
10328#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
10329#define RTC_CALR_CALM RTC_CALR_CALM_Msk
10330#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
10331#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
10332#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
10333#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
10334#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
10335#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
10336#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
10337#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
10338#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
10339
10340/******************** Bits definition for RTC_TAMPCR register ***************/
10341#define RTC_TAMPCR_TAMP2MF_Pos (21U)
10342#define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
10343#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
10344#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
10345#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
10346#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
10347#define RTC_TAMPCR_TAMP2IE_Pos (19U)
10348#define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
10349#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
10350#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
10351#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
10352#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
10353#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
10354#define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
10355#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
10356#define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
10357#define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
10358#define RTC_TAMPCR_TAMPFLT_Pos (11U)
10359#define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
10360#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
10361#define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
10362#define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
10363#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
10364#define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
10365#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
10366#define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
10367#define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
10368#define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
10369#define RTC_TAMPCR_TAMPTS_Pos (7U)
10370#define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
10371#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
10372#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
10373#define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
10374#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
10375#define RTC_TAMPCR_TAMP2E_Pos (3U)
10376#define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
10377#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
10378#define RTC_TAMPCR_TAMPIE_Pos (2U)
10379#define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
10380#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
10381
10382/******************** Bits definition for RTC_ALRMASSR register *************/
10383#define RTC_ALRMASSR_MASKSS_Pos (24U)
10384#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
10385#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
10386#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
10387#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
10388#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
10389#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
10390#define RTC_ALRMASSR_SS_Pos (0U)
10391#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
10392#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
10393
10394/******************** Bits definition for RTC_ALRMBSSR register *************/
10395#define RTC_ALRMBSSR_MASKSS_Pos (24U)
10396#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
10397#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
10398#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
10399#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
10400#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
10401#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
10402#define RTC_ALRMBSSR_SS_Pos (0U)
10403#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
10404#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
10405
10406/******************** Bits definition for RTC_0R register *******************/
10407#define RTC_OR_OUT_RMP_Pos (1U)
10408#define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
10409#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
10410#define RTC_OR_ALARMOUTTYPE_Pos (0U)
10411#define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
10412#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
10413
10414
10415/******************** Bits definition for RTC_BKP0R register ****************/
10416#define RTC_BKP0R_Pos (0U)
10417#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
10418#define RTC_BKP0R RTC_BKP0R_Msk
10419
10420/******************** Bits definition for RTC_BKP1R register ****************/
10421#define RTC_BKP1R_Pos (0U)
10422#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
10423#define RTC_BKP1R RTC_BKP1R_Msk
10424
10425/******************** Bits definition for RTC_BKP2R register ****************/
10426#define RTC_BKP2R_Pos (0U)
10427#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
10428#define RTC_BKP2R RTC_BKP2R_Msk
10429
10430/******************** Bits definition for RTC_BKP3R register ****************/
10431#define RTC_BKP3R_Pos (0U)
10432#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
10433#define RTC_BKP3R RTC_BKP3R_Msk
10434
10435/******************** Bits definition for RTC_BKP4R register ****************/
10436#define RTC_BKP4R_Pos (0U)
10437#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
10438#define RTC_BKP4R RTC_BKP4R_Msk
10439
10440/******************** Bits definition for RTC_BKP5R register ****************/
10441#define RTC_BKP5R_Pos (0U)
10442#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
10443#define RTC_BKP5R RTC_BKP5R_Msk
10444
10445/******************** Bits definition for RTC_BKP6R register ****************/
10446#define RTC_BKP6R_Pos (0U)
10447#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
10448#define RTC_BKP6R RTC_BKP6R_Msk
10449
10450/******************** Bits definition for RTC_BKP7R register ****************/
10451#define RTC_BKP7R_Pos (0U)
10452#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
10453#define RTC_BKP7R RTC_BKP7R_Msk
10454
10455/******************** Bits definition for RTC_BKP8R register ****************/
10456#define RTC_BKP8R_Pos (0U)
10457#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
10458#define RTC_BKP8R RTC_BKP8R_Msk
10459
10460/******************** Bits definition for RTC_BKP9R register ****************/
10461#define RTC_BKP9R_Pos (0U)
10462#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
10463#define RTC_BKP9R RTC_BKP9R_Msk
10464
10465/******************** Bits definition for RTC_BKP10R register ***************/
10466#define RTC_BKP10R_Pos (0U)
10467#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
10468#define RTC_BKP10R RTC_BKP10R_Msk
10469
10470/******************** Bits definition for RTC_BKP11R register ***************/
10471#define RTC_BKP11R_Pos (0U)
10472#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
10473#define RTC_BKP11R RTC_BKP11R_Msk
10474
10475/******************** Bits definition for RTC_BKP12R register ***************/
10476#define RTC_BKP12R_Pos (0U)
10477#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
10478#define RTC_BKP12R RTC_BKP12R_Msk
10479
10480/******************** Bits definition for RTC_BKP13R register ***************/
10481#define RTC_BKP13R_Pos (0U)
10482#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
10483#define RTC_BKP13R RTC_BKP13R_Msk
10484
10485/******************** Bits definition for RTC_BKP14R register ***************/
10486#define RTC_BKP14R_Pos (0U)
10487#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
10488#define RTC_BKP14R RTC_BKP14R_Msk
10489
10490/******************** Bits definition for RTC_BKP15R register ***************/
10491#define RTC_BKP15R_Pos (0U)
10492#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
10493#define RTC_BKP15R RTC_BKP15R_Msk
10494
10495/******************** Bits definition for RTC_BKP16R register ***************/
10496#define RTC_BKP16R_Pos (0U)
10497#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
10498#define RTC_BKP16R RTC_BKP16R_Msk
10499
10500/******************** Bits definition for RTC_BKP17R register ***************/
10501#define RTC_BKP17R_Pos (0U)
10502#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
10503#define RTC_BKP17R RTC_BKP17R_Msk
10504
10505/******************** Bits definition for RTC_BKP18R register ***************/
10506#define RTC_BKP18R_Pos (0U)
10507#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
10508#define RTC_BKP18R RTC_BKP18R_Msk
10509
10510/******************** Bits definition for RTC_BKP19R register ***************/
10511#define RTC_BKP19R_Pos (0U)
10512#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
10513#define RTC_BKP19R RTC_BKP19R_Msk
10514
10515/******************** Bits definition for RTC_BKP20R register ***************/
10516#define RTC_BKP20R_Pos (0U)
10517#define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
10518#define RTC_BKP20R RTC_BKP20R_Msk
10519
10520/******************** Bits definition for RTC_BKP21R register ***************/
10521#define RTC_BKP21R_Pos (0U)
10522#define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
10523#define RTC_BKP21R RTC_BKP21R_Msk
10524
10525/******************** Bits definition for RTC_BKP22R register ***************/
10526#define RTC_BKP22R_Pos (0U)
10527#define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
10528#define RTC_BKP22R RTC_BKP22R_Msk
10529
10530/******************** Bits definition for RTC_BKP23R register ***************/
10531#define RTC_BKP23R_Pos (0U)
10532#define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
10533#define RTC_BKP23R RTC_BKP23R_Msk
10534
10535/******************** Bits definition for RTC_BKP24R register ***************/
10536#define RTC_BKP24R_Pos (0U)
10537#define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
10538#define RTC_BKP24R RTC_BKP24R_Msk
10539
10540/******************** Bits definition for RTC_BKP25R register ***************/
10541#define RTC_BKP25R_Pos (0U)
10542#define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
10543#define RTC_BKP25R RTC_BKP25R_Msk
10544
10545/******************** Bits definition for RTC_BKP26R register ***************/
10546#define RTC_BKP26R_Pos (0U)
10547#define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
10548#define RTC_BKP26R RTC_BKP26R_Msk
10549
10550/******************** Bits definition for RTC_BKP27R register ***************/
10551#define RTC_BKP27R_Pos (0U)
10552#define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
10553#define RTC_BKP27R RTC_BKP27R_Msk
10554
10555/******************** Bits definition for RTC_BKP28R register ***************/
10556#define RTC_BKP28R_Pos (0U)
10557#define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
10558#define RTC_BKP28R RTC_BKP28R_Msk
10559
10560/******************** Bits definition for RTC_BKP29R register ***************/
10561#define RTC_BKP29R_Pos (0U)
10562#define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
10563#define RTC_BKP29R RTC_BKP29R_Msk
10564
10565/******************** Bits definition for RTC_BKP30R register ***************/
10566#define RTC_BKP30R_Pos (0U)
10567#define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
10568#define RTC_BKP30R RTC_BKP30R_Msk
10569
10570/******************** Bits definition for RTC_BKP31R register ***************/
10571#define RTC_BKP31R_Pos (0U)
10572#define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
10573#define RTC_BKP31R RTC_BKP31R_Msk
10574
10575/******************** Number of backup registers ******************************/
10576#define RTC_BKP_NUMBER 32U
10577
10578/******************************************************************************/
10579/* */
10580/* Serial Audio Interface */
10581/* */
10582/******************************************************************************/
10583/******************** Bit definition for SAI_GCR register *******************/
10584#define SAI_GCR_SYNCIN_Pos (0U)
10585#define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
10586#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
10587#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
10588#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
10589
10590#define SAI_GCR_SYNCOUT_Pos (4U)
10591#define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
10592#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
10593#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
10594#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
10595
10596/******************* Bit definition for SAI_xCR1 register *******************/
10597#define SAI_xCR1_MODE_Pos (0U)
10598#define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
10599#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
10600#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
10601#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
10602
10603#define SAI_xCR1_PRTCFG_Pos (2U)
10604#define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
10605#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
10606#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
10607#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
10608
10609#define SAI_xCR1_DS_Pos (5U)
10610#define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
10611#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
10612#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
10613#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
10614#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
10615
10616#define SAI_xCR1_LSBFIRST_Pos (8U)
10617#define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
10618#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
10619#define SAI_xCR1_CKSTR_Pos (9U)
10620#define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
10621#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
10622
10623#define SAI_xCR1_SYNCEN_Pos (10U)
10624#define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
10625#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
10626#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
10627#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
10628
10629#define SAI_xCR1_MONO_Pos (12U)
10630#define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
10631#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
10632#define SAI_xCR1_OUTDRIV_Pos (13U)
10633#define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
10634#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
10635#define SAI_xCR1_SAIEN_Pos (16U)
10636#define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
10637#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
10638#define SAI_xCR1_DMAEN_Pos (17U)
10639#define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
10640#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
10641#define SAI_xCR1_NODIV_Pos (19U)
10642#define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
10643#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
10644
10645#define SAI_xCR1_MCKDIV_Pos (20U)
10646#define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
10647#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
10648#define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
10649#define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
10650#define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
10651#define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
10652
10653/******************* Bit definition for SAI_xCR2 register *******************/
10654#define SAI_xCR2_FTH_Pos (0U)
10655#define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
10656#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
10657#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
10658#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
10659#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
10660
10661#define SAI_xCR2_FFLUSH_Pos (3U)
10662#define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
10663#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
10664#define SAI_xCR2_TRIS_Pos (4U)
10665#define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
10666#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
10667#define SAI_xCR2_MUTE_Pos (5U)
10668#define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
10669#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
10670#define SAI_xCR2_MUTEVAL_Pos (6U)
10671#define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
10672#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
10673
10674
10675#define SAI_xCR2_MUTECNT_Pos (7U)
10676#define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
10677#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
10678#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
10679#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
10680#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
10681#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
10682#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
10683#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
10684
10685#define SAI_xCR2_CPL_Pos (13U)
10686#define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
10687#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
10688#define SAI_xCR2_COMP_Pos (14U)
10689#define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
10690#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
10691#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
10692#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
10693
10694
10695/****************** Bit definition for SAI_xFRCR register *******************/
10696#define SAI_xFRCR_FRL_Pos (0U)
10697#define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
10698#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
10699#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
10700#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
10701#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
10702#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
10703#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
10704#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
10705#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
10706#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
10707
10708#define SAI_xFRCR_FSALL_Pos (8U)
10709#define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
10710#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
10711#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
10712#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
10713#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
10714#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
10715#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
10716#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
10717#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
10718
10719#define SAI_xFRCR_FSDEF_Pos (16U)
10720#define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
10721#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
10722#define SAI_xFRCR_FSPOL_Pos (17U)
10723#define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
10724#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
10725#define SAI_xFRCR_FSOFF_Pos (18U)
10726#define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
10727#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
10728
10729/****************** Bit definition for SAI_xSLOTR register *******************/
10730#define SAI_xSLOTR_FBOFF_Pos (0U)
10731#define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
10732#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
10733#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
10734#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
10735#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
10736#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
10737#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
10738
10739#define SAI_xSLOTR_SLOTSZ_Pos (6U)
10740#define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
10741#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
10742#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
10743#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
10744
10745#define SAI_xSLOTR_NBSLOT_Pos (8U)
10746#define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
10747#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
10748#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
10749#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
10750#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
10751#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
10752
10753#define SAI_xSLOTR_SLOTEN_Pos (16U)
10754#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
10755#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
10756
10757/******************* Bit definition for SAI_xIMR register *******************/
10758#define SAI_xIMR_OVRUDRIE_Pos (0U)
10759#define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
10760#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
10761#define SAI_xIMR_MUTEDETIE_Pos (1U)
10762#define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
10763#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
10764#define SAI_xIMR_WCKCFGIE_Pos (2U)
10765#define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
10766#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
10767#define SAI_xIMR_FREQIE_Pos (3U)
10768#define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
10769#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
10770#define SAI_xIMR_CNRDYIE_Pos (4U)
10771#define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
10772#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
10773#define SAI_xIMR_AFSDETIE_Pos (5U)
10774#define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
10775#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
10776#define SAI_xIMR_LFSDETIE_Pos (6U)
10777#define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
10778#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
10779
10780/******************** Bit definition for SAI_xSR register *******************/
10781#define SAI_xSR_OVRUDR_Pos (0U)
10782#define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
10783#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
10784#define SAI_xSR_MUTEDET_Pos (1U)
10785#define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
10786#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
10787#define SAI_xSR_WCKCFG_Pos (2U)
10788#define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
10789#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
10790#define SAI_xSR_FREQ_Pos (3U)
10791#define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
10792#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
10793#define SAI_xSR_CNRDY_Pos (4U)
10794#define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
10795#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
10796#define SAI_xSR_AFSDET_Pos (5U)
10797#define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
10798#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
10799#define SAI_xSR_LFSDET_Pos (6U)
10800#define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
10801#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
10802
10803#define SAI_xSR_FLVL_Pos (16U)
10804#define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
10805#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
10806#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
10807#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
10808#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
10809
10810/****************** Bit definition for SAI_xCLRFR register ******************/
10811#define SAI_xCLRFR_COVRUDR_Pos (0U)
10812#define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
10813#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
10814#define SAI_xCLRFR_CMUTEDET_Pos (1U)
10815#define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
10816#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
10817#define SAI_xCLRFR_CWCKCFG_Pos (2U)
10818#define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
10819#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
10820#define SAI_xCLRFR_CFREQ_Pos (3U)
10821#define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
10822#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
10823#define SAI_xCLRFR_CCNRDY_Pos (4U)
10824#define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
10825#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
10826#define SAI_xCLRFR_CAFSDET_Pos (5U)
10827#define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
10828#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
10829#define SAI_xCLRFR_CLFSDET_Pos (6U)
10830#define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
10831#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
10832
10833/****************** Bit definition for SAI_xDR register ******************/
10834#define SAI_xDR_DATA_Pos (0U)
10835#define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
10836#define SAI_xDR_DATA SAI_xDR_DATA_Msk
10837
10838/******************************************************************************/
10839/* */
10840/* Serial Peripheral Interface (SPI) */
10841/* */
10842/******************************************************************************/
10843/******************* Bit definition for SPI_CR1 register ********************/
10844#define SPI_CR1_CPHA_Pos (0U)
10845#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
10846#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
10847#define SPI_CR1_CPOL_Pos (1U)
10848#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
10849#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
10850#define SPI_CR1_MSTR_Pos (2U)
10851#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
10852#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
10853
10854#define SPI_CR1_BR_Pos (3U)
10855#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
10856#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
10857#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
10858#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
10859#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
10860
10861#define SPI_CR1_SPE_Pos (6U)
10862#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
10863#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
10864#define SPI_CR1_LSBFIRST_Pos (7U)
10865#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
10866#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
10867#define SPI_CR1_SSI_Pos (8U)
10868#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
10869#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
10870#define SPI_CR1_SSM_Pos (9U)
10871#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
10872#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
10873#define SPI_CR1_RXONLY_Pos (10U)
10874#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
10875#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
10876#define SPI_CR1_CRCL_Pos (11U)
10877#define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
10878#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
10879#define SPI_CR1_CRCNEXT_Pos (12U)
10880#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
10881#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
10882#define SPI_CR1_CRCEN_Pos (13U)
10883#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
10884#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
10885#define SPI_CR1_BIDIOE_Pos (14U)
10886#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
10887#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
10888#define SPI_CR1_BIDIMODE_Pos (15U)
10889#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
10890#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
10891
10892/******************* Bit definition for SPI_CR2 register ********************/
10893#define SPI_CR2_RXDMAEN_Pos (0U)
10894#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
10895#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
10896#define SPI_CR2_TXDMAEN_Pos (1U)
10897#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
10898#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
10899#define SPI_CR2_SSOE_Pos (2U)
10900#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
10901#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
10902#define SPI_CR2_NSSP_Pos (3U)
10903#define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
10904#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
10905#define SPI_CR2_FRF_Pos (4U)
10906#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
10907#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
10908#define SPI_CR2_ERRIE_Pos (5U)
10909#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
10910#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
10911#define SPI_CR2_RXNEIE_Pos (6U)
10912#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
10913#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
10914#define SPI_CR2_TXEIE_Pos (7U)
10915#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
10916#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
10917#define SPI_CR2_DS_Pos (8U)
10918#define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
10919#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
10920#define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
10921#define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
10922#define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
10923#define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
10924#define SPI_CR2_FRXTH_Pos (12U)
10925#define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
10926#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
10927#define SPI_CR2_LDMARX_Pos (13U)
10928#define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
10929#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
10930#define SPI_CR2_LDMATX_Pos (14U)
10931#define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
10932#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
10933
10934/******************** Bit definition for SPI_SR register ********************/
10935#define SPI_SR_RXNE_Pos (0U)
10936#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
10937#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
10938#define SPI_SR_TXE_Pos (1U)
10939#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
10940#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
10941#define SPI_SR_CHSIDE_Pos (2U)
10942#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
10943#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
10944#define SPI_SR_UDR_Pos (3U)
10945#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
10946#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
10947#define SPI_SR_CRCERR_Pos (4U)
10948#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
10949#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
10950#define SPI_SR_MODF_Pos (5U)
10951#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
10952#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
10953#define SPI_SR_OVR_Pos (6U)
10954#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
10955#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
10956#define SPI_SR_BSY_Pos (7U)
10957#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
10958#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
10959#define SPI_SR_FRE_Pos (8U)
10960#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
10961#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
10962#define SPI_SR_FRLVL_Pos (9U)
10963#define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
10964#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
10965#define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
10966#define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
10967#define SPI_SR_FTLVL_Pos (11U)
10968#define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
10969#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
10970#define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
10971#define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
10972
10973/******************** Bit definition for SPI_DR register ********************/
10974#define SPI_DR_DR_Pos (0U)
10975#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
10976#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
10977
10978/******************* Bit definition for SPI_CRCPR register ******************/
10979#define SPI_CRCPR_CRCPOLY_Pos (0U)
10980#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
10981#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
10982
10983/****************** Bit definition for SPI_RXCRCR register ******************/
10984#define SPI_RXCRCR_RXCRC_Pos (0U)
10985#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
10986#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
10987
10988/****************** Bit definition for SPI_TXCRCR register ******************/
10989#define SPI_TXCRCR_TXCRC_Pos (0U)
10990#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
10991#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
10992
10993/******************************************************************************/
10994/* */
10995/* QUADSPI */
10996/* */
10997/******************************************************************************/
10998/***************** Bit definition for QUADSPI_CR register *******************/
10999#define QUADSPI_CR_EN_Pos (0U)
11000#define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
11001#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
11002#define QUADSPI_CR_ABORT_Pos (1U)
11003#define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
11004#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
11005#define QUADSPI_CR_DMAEN_Pos (2U)
11006#define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
11007#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
11008#define QUADSPI_CR_TCEN_Pos (3U)
11009#define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
11010#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
11011#define QUADSPI_CR_SSHIFT_Pos (4U)
11012#define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
11013#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
11014#define QUADSPI_CR_DFM_Pos (6U)
11015#define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
11016#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */
11017#define QUADSPI_CR_FSEL_Pos (7U)
11018#define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
11019#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */
11020#define QUADSPI_CR_FTHRES_Pos (8U)
11021#define QUADSPI_CR_FTHRES_Msk (0xFU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
11022#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
11023#define QUADSPI_CR_TEIE_Pos (16U)
11024#define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
11025#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
11026#define QUADSPI_CR_TCIE_Pos (17U)
11027#define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
11028#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
11029#define QUADSPI_CR_FTIE_Pos (18U)
11030#define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
11031#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
11032#define QUADSPI_CR_SMIE_Pos (19U)
11033#define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
11034#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
11035#define QUADSPI_CR_TOIE_Pos (20U)
11036#define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
11037#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
11038#define QUADSPI_CR_APMS_Pos (22U)
11039#define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
11040#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
11041#define QUADSPI_CR_PMM_Pos (23U)
11042#define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
11043#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
11044#define QUADSPI_CR_PRESCALER_Pos (24U)
11045#define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
11046#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
11047
11048/***************** Bit definition for QUADSPI_DCR register ******************/
11049#define QUADSPI_DCR_CKMODE_Pos (0U)
11050#define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
11051#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
11052#define QUADSPI_DCR_CSHT_Pos (8U)
11053#define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
11054#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
11055#define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
11056#define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
11057#define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
11058#define QUADSPI_DCR_FSIZE_Pos (16U)
11059#define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
11060#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
11061
11062/****************** Bit definition for QUADSPI_SR register *******************/
11063#define QUADSPI_SR_TEF_Pos (0U)
11064#define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
11065#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
11066#define QUADSPI_SR_TCF_Pos (1U)
11067#define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
11068#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
11069#define QUADSPI_SR_FTF_Pos (2U)
11070#define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
11071#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
11072#define QUADSPI_SR_SMF_Pos (3U)
11073#define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
11074#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
11075#define QUADSPI_SR_TOF_Pos (4U)
11076#define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
11077#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
11078#define QUADSPI_SR_BUSY_Pos (5U)
11079#define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
11080#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
11081#define QUADSPI_SR_FLEVEL_Pos (8U)
11082#define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
11083#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
11084
11085/****************** Bit definition for QUADSPI_FCR register ******************/
11086#define QUADSPI_FCR_CTEF_Pos (0U)
11087#define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
11088#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
11089#define QUADSPI_FCR_CTCF_Pos (1U)
11090#define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
11091#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
11092#define QUADSPI_FCR_CSMF_Pos (3U)
11093#define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
11094#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
11095#define QUADSPI_FCR_CTOF_Pos (4U)
11096#define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
11097#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
11098
11099/****************** Bit definition for QUADSPI_DLR register ******************/
11100#define QUADSPI_DLR_DL_Pos (0U)
11101#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
11102#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
11103
11104/****************** Bit definition for QUADSPI_CCR register ******************/
11105#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
11106#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
11107#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
11108#define QUADSPI_CCR_IMODE_Pos (8U)
11109#define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
11110#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
11111#define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
11112#define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
11113#define QUADSPI_CCR_ADMODE_Pos (10U)
11114#define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
11115#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
11116#define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
11117#define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
11118#define QUADSPI_CCR_ADSIZE_Pos (12U)
11119#define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
11120#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
11121#define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
11122#define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
11123#define QUADSPI_CCR_ABMODE_Pos (14U)
11124#define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
11125#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
11126#define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
11127#define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
11128#define QUADSPI_CCR_ABSIZE_Pos (16U)
11129#define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
11130#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
11131#define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
11132#define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
11133#define QUADSPI_CCR_DCYC_Pos (18U)
11134#define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
11135#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
11136#define QUADSPI_CCR_DMODE_Pos (24U)
11137#define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
11138#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
11139#define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
11140#define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
11141#define QUADSPI_CCR_FMODE_Pos (26U)
11142#define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
11143#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
11144#define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
11145#define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
11146#define QUADSPI_CCR_SIOO_Pos (28U)
11147#define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
11148#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
11149#define QUADSPI_CCR_DHHC_Pos (30U)
11150#define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
11151#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */
11152#define QUADSPI_CCR_DDRM_Pos (31U)
11153#define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
11154#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
11155
11156/****************** Bit definition for QUADSPI_AR register *******************/
11157#define QUADSPI_AR_ADDRESS_Pos (0U)
11158#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
11159#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
11160
11161/****************** Bit definition for QUADSPI_ABR register ******************/
11162#define QUADSPI_ABR_ALTERNATE_Pos (0U)
11163#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
11164#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
11165
11166/****************** Bit definition for QUADSPI_DR register *******************/
11167#define QUADSPI_DR_DATA_Pos (0U)
11168#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
11169#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
11170
11171/****************** Bit definition for QUADSPI_PSMKR register ****************/
11172#define QUADSPI_PSMKR_MASK_Pos (0U)
11173#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
11174#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
11175
11176/****************** Bit definition for QUADSPI_PSMAR register ****************/
11177#define QUADSPI_PSMAR_MATCH_Pos (0U)
11178#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
11179#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
11180
11181/****************** Bit definition for QUADSPI_PIR register *****************/
11182#define QUADSPI_PIR_INTERVAL_Pos (0U)
11183#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
11184#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
11185
11186/****************** Bit definition for QUADSPI_LPTR register *****************/
11187#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
11188#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
11189#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
11190
11191/******************************************************************************/
11192/* */
11193/* SYSCFG */
11194/* */
11195/******************************************************************************/
11196/****************** Bit definition for SYSCFG_MEMRMP register ***************/
11197#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
11198#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
11199#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
11200#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
11201#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
11202#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
11203
11204/****************** Bit definition for SYSCFG_CFGR1 register ******************/
11205#define SYSCFG_CFGR1_FWDIS_Pos (0U)
11206#define SYSCFG_CFGR1_FWDIS_Msk (0x1U << SYSCFG_CFGR1_FWDIS_Pos) /*!< 0x00000001 */
11207#define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk /*!< FIREWALL access enable*/
11208#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
11209#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
11210#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
11211#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
11212#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
11213#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
11214#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
11215#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
11216#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
11217#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
11218#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
11219#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
11220#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
11221#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
11222#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
11223#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
11224#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
11225#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
11226#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
11227#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
11228#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
11229
11230/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
11231#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
11232#define SYSCFG_EXTICR1_EXTI0_Msk (0x7U << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
11233#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
11234#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
11235#define SYSCFG_EXTICR1_EXTI1_Msk (0x7U << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x00000070 */
11236#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
11237#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
11238#define SYSCFG_EXTICR1_EXTI2_Msk (0x7U << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000700 */
11239#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
11240#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
11241#define SYSCFG_EXTICR1_EXTI3_Msk (0x7U << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x00007000 */
11242#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
11243
11244/**
11245 * @brief EXTI0 configuration
11246 */
11247#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
11248#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
11249#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
11250
11251/**
11252 * @brief EXTI1 configuration
11253 */
11254#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
11255#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
11256#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
11257
11258/**
11259 * @brief EXTI2 configuration
11260 */
11261#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
11262
11263/**
11264 * @brief EXTI3 configuration
11265 */
11266#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
11267#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
11268#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
11269
11270/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
11271#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
11272#define SYSCFG_EXTICR2_EXTI4_Msk (0x7U << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
11273#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
11274#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
11275#define SYSCFG_EXTICR2_EXTI5_Msk (0x7U << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x00000070 */
11276#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
11277#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
11278#define SYSCFG_EXTICR2_EXTI6_Msk (0x7U << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000700 */
11279#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
11280#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
11281#define SYSCFG_EXTICR2_EXTI7_Msk (0x7U << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x00007000 */
11282#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
11283/**
11284 * @brief EXTI4 configuration
11285 */
11286#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
11287#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
11288
11289/**
11290 * @brief EXTI5 configuration
11291 */
11292#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
11293#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
11294
11295/**
11296 * @brief EXTI6 configuration
11297 */
11298#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
11299#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
11300
11301/**
11302 * @brief EXTI7 configuration
11303 */
11304#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
11305#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
11306
11307/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
11308#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
11309#define SYSCFG_EXTICR3_EXTI8_Msk (0x7U << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
11310#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
11311#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
11312#define SYSCFG_EXTICR3_EXTI9_Msk (0x7U << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x00000070 */
11313#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
11314#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
11315#define SYSCFG_EXTICR3_EXTI10_Msk (0x7U << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000700 */
11316#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
11317#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
11318#define SYSCFG_EXTICR3_EXTI11_Msk (0x7U << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x00007000 */
11319#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
11320
11321/**
11322 * @brief EXTI8 configuration
11323 */
11324#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
11325
11326/**
11327 * @brief EXTI9 configuration
11328 */
11329#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
11330
11331/**
11332 * @brief EXTI10 configuration
11333 */
11334#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
11335
11336/**
11337 * @brief EXTI11 configuration
11338 */
11339#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
11340
11341/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
11342#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
11343#define SYSCFG_EXTICR4_EXTI12_Msk (0x7U << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
11344#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
11345#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
11346#define SYSCFG_EXTICR4_EXTI13_Msk (0x7U << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
11347#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
11348#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
11349#define SYSCFG_EXTICR4_EXTI14_Msk (0x7U << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
11350#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
11351#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
11352#define SYSCFG_EXTICR4_EXTI15_Msk (0x7U << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
11353#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
11354
11355/**
11356 * @brief EXTI12 configuration
11357 */
11358#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
11359
11360/**
11361 * @brief EXTI13 configuration
11362 */
11363#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
11364
11365/**
11366 * @brief EXTI14 configuration
11367 */
11368#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
11369#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
11370
11371/**
11372 * @brief EXTI15 configuration
11373 */
11374#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
11375#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
11376
11377/****************** Bit definition for SYSCFG_SCSR register ****************/
11378#define SYSCFG_SCSR_SRAM2ER_Pos (0U)
11379#define SYSCFG_SCSR_SRAM2ER_Msk (0x1U << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */
11380#define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */
11381#define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
11382#define SYSCFG_SCSR_SRAM2BSY_Msk (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */
11383#define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */
11384
11385/****************** Bit definition for SYSCFG_CFGR2 register ****************/
11386#define SYSCFG_CFGR2_CLL_Pos (0U)
11387#define SYSCFG_CFGR2_CLL_Msk (0x1U << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
11388#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
11389#define SYSCFG_CFGR2_SPL_Pos (1U)
11390#define SYSCFG_CFGR2_SPL_Msk (0x1U << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
11391#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
11392#define SYSCFG_CFGR2_PVDL_Pos (2U)
11393#define SYSCFG_CFGR2_PVDL_Msk (0x1U << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
11394#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
11395#define SYSCFG_CFGR2_ECCL_Pos (3U)
11396#define SYSCFG_CFGR2_ECCL_Msk (0x1U << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
11397#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
11398#define SYSCFG_CFGR2_SPF_Pos (8U)
11399#define SYSCFG_CFGR2_SPF_Msk (0x1U << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
11400#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
11401
11402/****************** Bit definition for SYSCFG_SWPR register ****************/
11403#define SYSCFG_SWPR_PAGE0_Pos (0U)
11404#define SYSCFG_SWPR_PAGE0_Msk (0x1U << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
11405#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 */
11406#define SYSCFG_SWPR_PAGE1_Pos (1U)
11407#define SYSCFG_SWPR_PAGE1_Msk (0x1U << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
11408#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 */
11409#define SYSCFG_SWPR_PAGE2_Pos (2U)
11410#define SYSCFG_SWPR_PAGE2_Msk (0x1U << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
11411#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 */
11412#define SYSCFG_SWPR_PAGE3_Pos (3U)
11413#define SYSCFG_SWPR_PAGE3_Msk (0x1U << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
11414#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 */
11415#define SYSCFG_SWPR_PAGE4_Pos (4U)
11416#define SYSCFG_SWPR_PAGE4_Msk (0x1U << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
11417#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 */
11418#define SYSCFG_SWPR_PAGE5_Pos (5U)
11419#define SYSCFG_SWPR_PAGE5_Msk (0x1U << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
11420#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 */
11421#define SYSCFG_SWPR_PAGE6_Pos (6U)
11422#define SYSCFG_SWPR_PAGE6_Msk (0x1U << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
11423#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 */
11424#define SYSCFG_SWPR_PAGE7_Pos (7U)
11425#define SYSCFG_SWPR_PAGE7_Msk (0x1U << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
11426#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 */
11427#define SYSCFG_SWPR_PAGE8_Pos (8U)
11428#define SYSCFG_SWPR_PAGE8_Msk (0x1U << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
11429#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 */
11430#define SYSCFG_SWPR_PAGE9_Pos (9U)
11431#define SYSCFG_SWPR_PAGE9_Msk (0x1U << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
11432#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 */
11433#define SYSCFG_SWPR_PAGE10_Pos (10U)
11434#define SYSCFG_SWPR_PAGE10_Msk (0x1U << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
11435#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10*/
11436#define SYSCFG_SWPR_PAGE11_Pos (11U)
11437#define SYSCFG_SWPR_PAGE11_Msk (0x1U << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
11438#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11*/
11439#define SYSCFG_SWPR_PAGE12_Pos (12U)
11440#define SYSCFG_SWPR_PAGE12_Msk (0x1U << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
11441#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12*/
11442#define SYSCFG_SWPR_PAGE13_Pos (13U)
11443#define SYSCFG_SWPR_PAGE13_Msk (0x1U << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
11444#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13*/
11445#define SYSCFG_SWPR_PAGE14_Pos (14U)
11446#define SYSCFG_SWPR_PAGE14_Msk (0x1U << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
11447#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14*/
11448#define SYSCFG_SWPR_PAGE15_Pos (15U)
11449#define SYSCFG_SWPR_PAGE15_Msk (0x1U << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
11450#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15*/
11451
11452/****************** Bit definition for SYSCFG_SKR register ****************/
11453#define SYSCFG_SKR_KEY_Pos (0U)
11454#define SYSCFG_SKR_KEY_Msk (0xFFU << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
11455#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */
11456
11457
11458
11459
11460/******************************************************************************/
11461/* */
11462/* TIM */
11463/* */
11464/******************************************************************************/
11465/******************* Bit definition for TIM_CR1 register ********************/
11466#define TIM_CR1_CEN_Pos (0U)
11467#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
11468#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
11469#define TIM_CR1_UDIS_Pos (1U)
11470#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
11471#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
11472#define TIM_CR1_URS_Pos (2U)
11473#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
11474#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
11475#define TIM_CR1_OPM_Pos (3U)
11476#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
11477#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
11478#define TIM_CR1_DIR_Pos (4U)
11479#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
11480#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
11481
11482#define TIM_CR1_CMS_Pos (5U)
11483#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
11484#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
11485#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
11486#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
11487
11488#define TIM_CR1_ARPE_Pos (7U)
11489#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
11490#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
11491
11492#define TIM_CR1_CKD_Pos (8U)
11493#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
11494#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
11495#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
11496#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
11497
11498#define TIM_CR1_UIFREMAP_Pos (11U)
11499#define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
11500#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
11501
11502/******************* Bit definition for TIM_CR2 register ********************/
11503#define TIM_CR2_CCPC_Pos (0U)
11504#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
11505#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
11506#define TIM_CR2_CCUS_Pos (2U)
11507#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
11508#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
11509#define TIM_CR2_CCDS_Pos (3U)
11510#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
11511#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
11512
11513#define TIM_CR2_MMS_Pos (4U)
11514#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
11515#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
11516#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
11517#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
11518#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
11519
11520#define TIM_CR2_TI1S_Pos (7U)
11521#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
11522#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
11523#define TIM_CR2_OIS1_Pos (8U)
11524#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
11525#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
11526#define TIM_CR2_OIS1N_Pos (9U)
11527#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
11528#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
11529#define TIM_CR2_OIS2_Pos (10U)
11530#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
11531#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
11532#define TIM_CR2_OIS2N_Pos (11U)
11533#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
11534#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
11535#define TIM_CR2_OIS3_Pos (12U)
11536#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
11537#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
11538#define TIM_CR2_OIS3N_Pos (13U)
11539#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
11540#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
11541#define TIM_CR2_OIS4_Pos (14U)
11542#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
11543#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
11544#define TIM_CR2_OIS5_Pos (16U)
11545#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
11546#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
11547#define TIM_CR2_OIS6_Pos (18U)
11548#define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
11549#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
11550
11551#define TIM_CR2_MMS2_Pos (20U)
11552#define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
11553#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
11554#define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
11555#define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
11556#define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
11557#define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
11558
11559/******************* Bit definition for TIM_SMCR register *******************/
11560#define TIM_SMCR_SMS_Pos (0U)
11561#define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
11562#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
11563#define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
11564#define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
11565#define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
11566#define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
11567
11568#define TIM_SMCR_OCCS_Pos (3U)
11569#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
11570#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
11571
11572#define TIM_SMCR_TS_Pos (4U)
11573#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
11574#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
11575#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
11576#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
11577#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
11578
11579#define TIM_SMCR_MSM_Pos (7U)
11580#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
11581#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
11582
11583#define TIM_SMCR_ETF_Pos (8U)
11584#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
11585#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
11586#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
11587#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
11588#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
11589#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
11590
11591#define TIM_SMCR_ETPS_Pos (12U)
11592#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
11593#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
11594#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
11595#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
11596
11597#define TIM_SMCR_ECE_Pos (14U)
11598#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
11599#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
11600#define TIM_SMCR_ETP_Pos (15U)
11601#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
11602#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
11603
11604/******************* Bit definition for TIM_DIER register *******************/
11605#define TIM_DIER_UIE_Pos (0U)
11606#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
11607#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
11608#define TIM_DIER_CC1IE_Pos (1U)
11609#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
11610#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
11611#define TIM_DIER_CC2IE_Pos (2U)
11612#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
11613#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
11614#define TIM_DIER_CC3IE_Pos (3U)
11615#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
11616#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
11617#define TIM_DIER_CC4IE_Pos (4U)
11618#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
11619#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
11620#define TIM_DIER_COMIE_Pos (5U)
11621#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
11622#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
11623#define TIM_DIER_TIE_Pos (6U)
11624#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
11625#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
11626#define TIM_DIER_BIE_Pos (7U)
11627#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
11628#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
11629#define TIM_DIER_UDE_Pos (8U)
11630#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
11631#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
11632#define TIM_DIER_CC1DE_Pos (9U)
11633#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
11634#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
11635#define TIM_DIER_CC2DE_Pos (10U)
11636#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
11637#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
11638#define TIM_DIER_CC3DE_Pos (11U)
11639#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
11640#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
11641#define TIM_DIER_CC4DE_Pos (12U)
11642#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
11643#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
11644#define TIM_DIER_COMDE_Pos (13U)
11645#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
11646#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
11647#define TIM_DIER_TDE_Pos (14U)
11648#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
11649#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
11650
11651/******************** Bit definition for TIM_SR register ********************/
11652#define TIM_SR_UIF_Pos (0U)
11653#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
11654#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
11655#define TIM_SR_CC1IF_Pos (1U)
11656#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
11657#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
11658#define TIM_SR_CC2IF_Pos (2U)
11659#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
11660#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
11661#define TIM_SR_CC3IF_Pos (3U)
11662#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
11663#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
11664#define TIM_SR_CC4IF_Pos (4U)
11665#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
11666#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
11667#define TIM_SR_COMIF_Pos (5U)
11668#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
11669#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
11670#define TIM_SR_TIF_Pos (6U)
11671#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
11672#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
11673#define TIM_SR_BIF_Pos (7U)
11674#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
11675#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
11676#define TIM_SR_B2IF_Pos (8U)
11677#define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
11678#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
11679#define TIM_SR_CC1OF_Pos (9U)
11680#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
11681#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
11682#define TIM_SR_CC2OF_Pos (10U)
11683#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
11684#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
11685#define TIM_SR_CC3OF_Pos (11U)
11686#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
11687#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
11688#define TIM_SR_CC4OF_Pos (12U)
11689#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
11690#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
11691#define TIM_SR_SBIF_Pos (13U)
11692#define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
11693#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
11694#define TIM_SR_CC5IF_Pos (16U)
11695#define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
11696#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
11697#define TIM_SR_CC6IF_Pos (17U)
11698#define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
11699#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
11700
11701
11702/******************* Bit definition for TIM_EGR register ********************/
11703#define TIM_EGR_UG_Pos (0U)
11704#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
11705#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
11706#define TIM_EGR_CC1G_Pos (1U)
11707#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
11708#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
11709#define TIM_EGR_CC2G_Pos (2U)
11710#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
11711#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
11712#define TIM_EGR_CC3G_Pos (3U)
11713#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
11714#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
11715#define TIM_EGR_CC4G_Pos (4U)
11716#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
11717#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
11718#define TIM_EGR_COMG_Pos (5U)
11719#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
11720#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
11721#define TIM_EGR_TG_Pos (6U)
11722#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
11723#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
11724#define TIM_EGR_BG_Pos (7U)
11725#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
11726#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
11727#define TIM_EGR_B2G_Pos (8U)
11728#define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
11729#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
11730
11731
11732/****************** Bit definition for TIM_CCMR1 register *******************/
11733#define TIM_CCMR1_CC1S_Pos (0U)
11734#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
11735#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
11736#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
11737#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
11738
11739#define TIM_CCMR1_OC1FE_Pos (2U)
11740#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
11741#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
11742#define TIM_CCMR1_OC1PE_Pos (3U)
11743#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
11744#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
11745
11746#define TIM_CCMR1_OC1M_Pos (4U)
11747#define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
11748#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
11749#define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
11750#define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
11751#define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
11752#define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
11753
11754#define TIM_CCMR1_OC1CE_Pos (7U)
11755#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
11756#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
11757
11758#define TIM_CCMR1_CC2S_Pos (8U)
11759#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
11760#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
11761#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
11762#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
11763
11764#define TIM_CCMR1_OC2FE_Pos (10U)
11765#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
11766#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
11767#define TIM_CCMR1_OC2PE_Pos (11U)
11768#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
11769#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
11770
11771#define TIM_CCMR1_OC2M_Pos (12U)
11772#define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
11773#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
11774#define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
11775#define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
11776#define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
11777#define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
11778
11779#define TIM_CCMR1_OC2CE_Pos (15U)
11780#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
11781#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
11782
11783/*----------------------------------------------------------------------------*/
11784#define TIM_CCMR1_IC1PSC_Pos (2U)
11785#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
11786#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
11787#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
11788#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
11789
11790#define TIM_CCMR1_IC1F_Pos (4U)
11791#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
11792#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
11793#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
11794#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
11795#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
11796#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
11797
11798#define TIM_CCMR1_IC2PSC_Pos (10U)
11799#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
11800#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
11801#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
11802#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
11803
11804#define TIM_CCMR1_IC2F_Pos (12U)
11805#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
11806#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
11807#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
11808#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
11809#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
11810#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
11811
11812/****************** Bit definition for TIM_CCMR2 register *******************/
11813#define TIM_CCMR2_CC3S_Pos (0U)
11814#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
11815#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
11816#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
11817#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
11818
11819#define TIM_CCMR2_OC3FE_Pos (2U)
11820#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
11821#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
11822#define TIM_CCMR2_OC3PE_Pos (3U)
11823#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
11824#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
11825
11826#define TIM_CCMR2_OC3M_Pos (4U)
11827#define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
11828#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
11829#define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
11830#define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
11831#define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
11832#define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
11833
11834#define TIM_CCMR2_OC3CE_Pos (7U)
11835#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
11836#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
11837
11838#define TIM_CCMR2_CC4S_Pos (8U)
11839#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
11840#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
11841#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
11842#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
11843
11844#define TIM_CCMR2_OC4FE_Pos (10U)
11845#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
11846#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
11847#define TIM_CCMR2_OC4PE_Pos (11U)
11848#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
11849#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
11850
11851#define TIM_CCMR2_OC4M_Pos (12U)
11852#define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
11853#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
11854#define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
11855#define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
11856#define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
11857#define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
11858
11859#define TIM_CCMR2_OC4CE_Pos (15U)
11860#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
11861#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
11862
11863/*----------------------------------------------------------------------------*/
11864#define TIM_CCMR2_IC3PSC_Pos (2U)
11865#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
11866#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
11867#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
11868#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
11869
11870#define TIM_CCMR2_IC3F_Pos (4U)
11871#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
11872#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
11873#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
11874#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
11875#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
11876#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
11877
11878#define TIM_CCMR2_IC4PSC_Pos (10U)
11879#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
11880#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
11881#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
11882#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
11883
11884#define TIM_CCMR2_IC4F_Pos (12U)
11885#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
11886#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
11887#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
11888#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
11889#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
11890#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
11891
11892/****************** Bit definition for TIM_CCMR3 register *******************/
11893#define TIM_CCMR3_OC5FE_Pos (2U)
11894#define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
11895#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
11896#define TIM_CCMR3_OC5PE_Pos (3U)
11897#define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
11898#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
11899
11900#define TIM_CCMR3_OC5M_Pos (4U)
11901#define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
11902#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
11903#define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
11904#define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
11905#define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
11906#define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
11907
11908#define TIM_CCMR3_OC5CE_Pos (7U)
11909#define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
11910#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
11911
11912#define TIM_CCMR3_OC6FE_Pos (10U)
11913#define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
11914#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
11915#define TIM_CCMR3_OC6PE_Pos (11U)
11916#define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
11917#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
11918
11919#define TIM_CCMR3_OC6M_Pos (12U)
11920#define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
11921#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
11922#define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
11923#define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
11924#define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
11925#define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
11926
11927#define TIM_CCMR3_OC6CE_Pos (15U)
11928#define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
11929#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
11930
11931/******************* Bit definition for TIM_CCER register *******************/
11932#define TIM_CCER_CC1E_Pos (0U)
11933#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
11934#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
11935#define TIM_CCER_CC1P_Pos (1U)
11936#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
11937#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
11938#define TIM_CCER_CC1NE_Pos (2U)
11939#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
11940#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
11941#define TIM_CCER_CC1NP_Pos (3U)
11942#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
11943#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
11944#define TIM_CCER_CC2E_Pos (4U)
11945#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
11946#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
11947#define TIM_CCER_CC2P_Pos (5U)
11948#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
11949#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
11950#define TIM_CCER_CC2NE_Pos (6U)
11951#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
11952#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
11953#define TIM_CCER_CC2NP_Pos (7U)
11954#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
11955#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
11956#define TIM_CCER_CC3E_Pos (8U)
11957#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
11958#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
11959#define TIM_CCER_CC3P_Pos (9U)
11960#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
11961#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
11962#define TIM_CCER_CC3NE_Pos (10U)
11963#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
11964#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
11965#define TIM_CCER_CC3NP_Pos (11U)
11966#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
11967#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
11968#define TIM_CCER_CC4E_Pos (12U)
11969#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
11970#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
11971#define TIM_CCER_CC4P_Pos (13U)
11972#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
11973#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
11974#define TIM_CCER_CC4NP_Pos (15U)
11975#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
11976#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
11977#define TIM_CCER_CC5E_Pos (16U)
11978#define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
11979#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
11980#define TIM_CCER_CC5P_Pos (17U)
11981#define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
11982#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
11983#define TIM_CCER_CC6E_Pos (20U)
11984#define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
11985#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
11986#define TIM_CCER_CC6P_Pos (21U)
11987#define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
11988#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
11989
11990/******************* Bit definition for TIM_CNT register ********************/
11991#define TIM_CNT_CNT_Pos (0U)
11992#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
11993#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
11994#define TIM_CNT_UIFCPY_Pos (31U)
11995#define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
11996#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
11997
11998/******************* Bit definition for TIM_PSC register ********************/
11999#define TIM_PSC_PSC_Pos (0U)
12000#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
12001#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
12002
12003/******************* Bit definition for TIM_ARR register ********************/
12004#define TIM_ARR_ARR_Pos (0U)
12005#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
12006#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
12007
12008/******************* Bit definition for TIM_RCR register ********************/
12009#define TIM_RCR_REP_Pos (0U)
12010#define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
12011#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
12012
12013/******************* Bit definition for TIM_CCR1 register *******************/
12014#define TIM_CCR1_CCR1_Pos (0U)
12015#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
12016#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
12017
12018/******************* Bit definition for TIM_CCR2 register *******************/
12019#define TIM_CCR2_CCR2_Pos (0U)
12020#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
12021#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
12022
12023/******************* Bit definition for TIM_CCR3 register *******************/
12024#define TIM_CCR3_CCR3_Pos (0U)
12025#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
12026#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
12027
12028/******************* Bit definition for TIM_CCR4 register *******************/
12029#define TIM_CCR4_CCR4_Pos (0U)
12030#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
12031#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
12032
12033/******************* Bit definition for TIM_CCR5 register *******************/
12034#define TIM_CCR5_CCR5_Pos (0U)
12035#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
12036#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
12037#define TIM_CCR5_GC5C1_Pos (29U)
12038#define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
12039#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
12040#define TIM_CCR5_GC5C2_Pos (30U)
12041#define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
12042#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
12043#define TIM_CCR5_GC5C3_Pos (31U)
12044#define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
12045#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
12046
12047/******************* Bit definition for TIM_CCR6 register *******************/
12048#define TIM_CCR6_CCR6_Pos (0U)
12049#define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
12050#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
12051
12052/******************* Bit definition for TIM_BDTR register *******************/
12053#define TIM_BDTR_DTG_Pos (0U)
12054#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
12055#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
12056#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
12057#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
12058#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
12059#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
12060#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
12061#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
12062#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
12063#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
12064
12065#define TIM_BDTR_LOCK_Pos (8U)
12066#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
12067#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
12068#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
12069#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
12070
12071#define TIM_BDTR_OSSI_Pos (10U)
12072#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
12073#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
12074#define TIM_BDTR_OSSR_Pos (11U)
12075#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
12076#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
12077#define TIM_BDTR_BKE_Pos (12U)
12078#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
12079#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
12080#define TIM_BDTR_BKP_Pos (13U)
12081#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
12082#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
12083#define TIM_BDTR_AOE_Pos (14U)
12084#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
12085#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
12086#define TIM_BDTR_MOE_Pos (15U)
12087#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
12088#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
12089
12090#define TIM_BDTR_BKF_Pos (16U)
12091#define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
12092#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
12093#define TIM_BDTR_BK2F_Pos (20U)
12094#define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
12095#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
12096
12097#define TIM_BDTR_BK2E_Pos (24U)
12098#define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
12099#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
12100#define TIM_BDTR_BK2P_Pos (25U)
12101#define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
12102#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
12103
12104/******************* Bit definition for TIM_DCR register ********************/
12105#define TIM_DCR_DBA_Pos (0U)
12106#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
12107#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
12108#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
12109#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
12110#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
12111#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
12112#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
12113
12114#define TIM_DCR_DBL_Pos (8U)
12115#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
12116#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
12117#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
12118#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
12119#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
12120#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
12121#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
12122
12123/******************* Bit definition for TIM_DMAR register *******************/
12124#define TIM_DMAR_DMAB_Pos (0U)
12125#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
12126#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
12127
12128/******************* Bit definition for TIM1_OR1 register *******************/
12129#define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
12130#define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
12131#define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
12132#define TIM1_OR1_ETR_ADC1_RMP_0 (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
12133#define TIM1_OR1_ETR_ADC1_RMP_1 (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
12134
12135#define TIM1_OR1_TI1_RMP_Pos (4U)
12136#define TIM1_OR1_TI1_RMP_Msk (0x1U << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
12137#define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */
12138
12139/******************* Bit definition for TIM1_OR2 register *******************/
12140#define TIM1_OR2_BKINE_Pos (0U)
12141#define TIM1_OR2_BKINE_Msk (0x1U << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */
12142#define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */
12143#define TIM1_OR2_BKCMP1E_Pos (1U)
12144#define TIM1_OR2_BKCMP1E_Msk (0x1U << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
12145#define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
12146#define TIM1_OR2_BKCMP2E_Pos (2U)
12147#define TIM1_OR2_BKCMP2E_Msk (0x1U << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
12148#define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
12149#define TIM1_OR2_BKINP_Pos (9U)
12150#define TIM1_OR2_BKINP_Msk (0x1U << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */
12151#define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
12152#define TIM1_OR2_BKCMP1P_Pos (10U)
12153#define TIM1_OR2_BKCMP1P_Msk (0x1U << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
12154#define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
12155#define TIM1_OR2_BKCMP2P_Pos (11U)
12156#define TIM1_OR2_BKCMP2P_Msk (0x1U << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
12157#define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
12158
12159#define TIM1_OR2_ETRSEL_Pos (14U)
12160#define TIM1_OR2_ETRSEL_Msk (0x7U << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
12161#define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
12162#define TIM1_OR2_ETRSEL_0 (0x1U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */
12163#define TIM1_OR2_ETRSEL_1 (0x2U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */
12164#define TIM1_OR2_ETRSEL_2 (0x4U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */
12165
12166/******************* Bit definition for TIM1_OR3 register *******************/
12167#define TIM1_OR3_BK2INE_Pos (0U)
12168#define TIM1_OR3_BK2INE_Msk (0x1U << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */
12169#define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
12170#define TIM1_OR3_BK2CMP1E_Pos (1U)
12171#define TIM1_OR3_BK2CMP1E_Msk (0x1U << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
12172#define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
12173#define TIM1_OR3_BK2CMP2E_Pos (2U)
12174#define TIM1_OR3_BK2CMP2E_Msk (0x1U << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
12175#define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
12176#define TIM1_OR3_BK2INP_Pos (9U)
12177#define TIM1_OR3_BK2INP_Msk (0x1U << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */
12178#define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
12179#define TIM1_OR3_BK2CMP1P_Pos (10U)
12180#define TIM1_OR3_BK2CMP1P_Msk (0x1U << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
12181#define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
12182#define TIM1_OR3_BK2CMP2P_Pos (11U)
12183#define TIM1_OR3_BK2CMP2P_Msk (0x1U << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
12184#define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
12185
12186
12187/******************* Bit definition for TIM2_OR1 register *******************/
12188#define TIM2_OR1_ITR1_RMP_Pos (0U)
12189#define TIM2_OR1_ITR1_RMP_Msk (0x1U << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */
12190#define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
12191#define TIM2_OR1_ETR1_RMP_Pos (1U)
12192#define TIM2_OR1_ETR1_RMP_Msk (0x1U << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */
12193#define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */
12194
12195#define TIM2_OR1_TI4_RMP_Pos (2U)
12196#define TIM2_OR1_TI4_RMP_Msk (0x3U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */
12197#define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
12198#define TIM2_OR1_TI4_RMP_0 (0x1U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */
12199#define TIM2_OR1_TI4_RMP_1 (0x2U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */
12200
12201/******************* Bit definition for TIM2_OR2 register *******************/
12202#define TIM2_OR2_ETRSEL_Pos (14U)
12203#define TIM2_OR2_ETRSEL_Msk (0x7U << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
12204#define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
12205#define TIM2_OR2_ETRSEL_0 (0x1U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */
12206#define TIM2_OR2_ETRSEL_1 (0x2U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */
12207#define TIM2_OR2_ETRSEL_2 (0x4U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */
12208
12209
12210/******************* Bit definition for TIM15_OR1 register ******************/
12211#define TIM15_OR1_TI1_RMP_Pos (0U)
12212#define TIM15_OR1_TI1_RMP_Msk (0x1U << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
12213#define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */
12214
12215#define TIM15_OR1_ENCODER_MODE_Pos (1U)
12216#define TIM15_OR1_ENCODER_MODE_Msk (0x3U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */
12217#define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
12218#define TIM15_OR1_ENCODER_MODE_0 (0x1U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */
12219#define TIM15_OR1_ENCODER_MODE_1 (0x2U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */
12220
12221/******************* Bit definition for TIM15_OR2 register ******************/
12222#define TIM15_OR2_BKINE_Pos (0U)
12223#define TIM15_OR2_BKINE_Msk (0x1U << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */
12224#define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */
12225#define TIM15_OR2_BKCMP1E_Pos (1U)
12226#define TIM15_OR2_BKCMP1E_Msk (0x1U << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
12227#define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
12228#define TIM15_OR2_BKCMP2E_Pos (2U)
12229#define TIM15_OR2_BKCMP2E_Msk (0x1U << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
12230#define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
12231#define TIM15_OR2_BKINP_Pos (9U)
12232#define TIM15_OR2_BKINP_Msk (0x1U << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */
12233#define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
12234#define TIM15_OR2_BKCMP1P_Pos (10U)
12235#define TIM15_OR2_BKCMP1P_Msk (0x1U << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
12236#define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
12237#define TIM15_OR2_BKCMP2P_Pos (11U)
12238#define TIM15_OR2_BKCMP2P_Msk (0x1U << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
12239#define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
12240
12241/******************* Bit definition for TIM16_OR1 register ******************/
12242#define TIM16_OR1_TI1_RMP_Pos (0U)
12243#define TIM16_OR1_TI1_RMP_Msk (0x7U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
12244#define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM16 Input Capture 1 remap) */
12245#define TIM16_OR1_TI1_RMP_0 (0x1U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
12246#define TIM16_OR1_TI1_RMP_1 (0x2U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
12247#define TIM16_OR1_TI1_RMP_2 (0x4U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
12248
12249/******************* Bit definition for TIM16_OR2 register ******************/
12250#define TIM16_OR2_BKINE_Pos (0U)
12251#define TIM16_OR2_BKINE_Msk (0x1U << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */
12252#define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */
12253#define TIM16_OR2_BKCMP1E_Pos (1U)
12254#define TIM16_OR2_BKCMP1E_Msk (0x1U << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
12255#define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
12256#define TIM16_OR2_BKCMP2E_Pos (2U)
12257#define TIM16_OR2_BKCMP2E_Msk (0x1U << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
12258#define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
12259#define TIM16_OR2_BKINP_Pos (9U)
12260#define TIM16_OR2_BKINP_Msk (0x1U << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */
12261#define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
12262#define TIM16_OR2_BKCMP1P_Pos (10U)
12263#define TIM16_OR2_BKCMP1P_Msk (0x1U << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
12264#define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
12265#define TIM16_OR2_BKCMP2P_Pos (11U)
12266#define TIM16_OR2_BKCMP2P_Msk (0x1U << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
12267#define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
12268
12269
12270/******************************************************************************/
12271/* */
12272/* Low Power Timer (LPTTIM) */
12273/* */
12274/******************************************************************************/
12275/****************** Bit definition for LPTIM_ISR register *******************/
12276#define LPTIM_ISR_CMPM_Pos (0U)
12277#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
12278#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
12279#define LPTIM_ISR_ARRM_Pos (1U)
12280#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
12281#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
12282#define LPTIM_ISR_EXTTRIG_Pos (2U)
12283#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
12284#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
12285#define LPTIM_ISR_CMPOK_Pos (3U)
12286#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
12287#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
12288#define LPTIM_ISR_ARROK_Pos (4U)
12289#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
12290#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
12291#define LPTIM_ISR_UP_Pos (5U)
122