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1/**
2 ******************************************************************************
3 * @file stm32l485xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32L485xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral�s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42/** @addtogroup CMSIS_Device
43 * @{
44 */
45
46/** @addtogroup stm32l485xx
47 * @{
48 */
49
50#ifndef __STM32L485xx_H
51#define __STM32L485xx_H
52
53#ifdef __cplusplus
54 extern "C" {
55#endif /* __cplusplus */
56
57/** @addtogroup Configuration_section_for_CMSIS
58 * @{
59 */
60
61/**
62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63 */
64#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
65#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
66#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
67#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
68#define __FPU_PRESENT 1 /*!< FPU present */
69
70/**
71 * @}
72 */
73
74/** @addtogroup Peripheral_interrupt_number_definition
75 * @{
76 */
77
78/**
79 * @brief STM32L4XX Interrupt Number Definition, according to the selected device
80 * in @ref Library_configuration_section
81 */
82typedef enum
83{
84/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
86 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
87 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
88 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
89 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
90 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
91 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
92 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
93 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
94/****** STM32 specific Interrupt Numbers **********************************************************************/
95 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
96 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
97 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
98 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
99 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
100 RCC_IRQn = 5, /*!< RCC global Interrupt */
101 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
102 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
103 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
104 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
105 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
106 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
107 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
108 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
109 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
110 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
111 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
112 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
113 ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */
114 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
115 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
116 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
117 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
118 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
119 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
120 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
121 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
122 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
123 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
124 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
125 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
128 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
129 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
130 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
131 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
132 USART1_IRQn = 37, /*!< USART1 global Interrupt */
133 USART2_IRQn = 38, /*!< USART2 global Interrupt */
134 USART3_IRQn = 39, /*!< USART3 global Interrupt */
135 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
136 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
137 DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */
138 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
139 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
140 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
141 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
142 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
143 FMC_IRQn = 48, /*!< FMC global Interrupt */
144 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
145 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
146 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
147 UART4_IRQn = 52, /*!< UART4 global Interrupt */
148 UART5_IRQn = 53, /*!< UART5 global Interrupt */
149 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
150 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
151 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
152 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
153 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
154 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
155 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
156 DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
157 DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
158 DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */
159 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
160 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
161 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
162 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
163 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
164 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
165 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
166 QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
167 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
168 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
169 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
170 SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */
171 SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */
172 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
173 AES_IRQn = 79, /*!< AES global interrupt */
174 RNG_IRQn = 80, /*!< RNG global interrupt */
175 FPU_IRQn = 81 /*!< FPU global interrupt */
176} IRQn_Type;
177
178/**
179 * @}
180 */
181
182#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
183#include "system_stm32l4xx.h"
184#include <stdint.h>
185
186/** @addtogroup Peripheral_registers_structures
187 * @{
188 */
189
190/**
191 * @brief Analog to Digital Converter
192 */
193
194typedef struct
195{
196 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
197 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
198 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
199 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
200 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
201 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
202 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
203 uint32_t RESERVED1; /*!< Reserved, 0x1C */
204 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
205 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
206 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
207 uint32_t RESERVED2; /*!< Reserved, 0x2C */
208 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
209 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
210 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
211 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
212 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
213 uint32_t RESERVED3; /*!< Reserved, 0x44 */
214 uint32_t RESERVED4; /*!< Reserved, 0x48 */
215 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
216 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
217 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
218 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
219 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
220 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
221 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
222 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
223 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
224 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
225 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
226 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
227 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
228 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
229 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
230 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
231 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
232 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
233
234} ADC_TypeDef;
235
236typedef struct
237{
238 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
239 uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
240 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
241 __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */
242} ADC_Common_TypeDef;
243
244
245/**
246 * @brief Controller Area Network TxMailBox
247 */
248
249typedef struct
250{
251 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
252 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
253 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
254 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
255} CAN_TxMailBox_TypeDef;
256
257/**
258 * @brief Controller Area Network FIFOMailBox
259 */
260
261typedef struct
262{
263 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
264 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
265 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
266 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
267} CAN_FIFOMailBox_TypeDef;
268
269/**
270 * @brief Controller Area Network FilterRegister
271 */
272
273typedef struct
274{
275 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
276 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
277} CAN_FilterRegister_TypeDef;
278
279/**
280 * @brief Controller Area Network
281 */
282
283typedef struct
284{
285 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
286 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
287 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
288 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
289 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
290 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
291 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
292 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
293 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
294 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
295 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
296 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
297 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
298 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
299 uint32_t RESERVED2; /*!< Reserved, 0x208 */
300 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
301 uint32_t RESERVED3; /*!< Reserved, 0x210 */
302 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
303 uint32_t RESERVED4; /*!< Reserved, 0x218 */
304 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
305 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
306 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
307} CAN_TypeDef;
308
309
310/**
311 * @brief Comparator
312 */
313
314typedef struct
315{
316 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
317} COMP_TypeDef;
318
319typedef struct
320{
321 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
322} COMP_Common_TypeDef;
323
324/**
325 * @brief CRC calculation unit
326 */
327
328typedef struct
329{
330 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
331 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
332 uint8_t RESERVED0; /*!< Reserved, 0x05 */
333 uint16_t RESERVED1; /*!< Reserved, 0x06 */
334 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
335 uint32_t RESERVED2; /*!< Reserved, 0x0C */
336 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
337 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
338} CRC_TypeDef;
339
340/**
341 * @brief Digital to Analog Converter
342 */
343
344typedef struct
345{
346 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
347 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
348 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
349 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
350 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
351 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
352 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
353 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
354 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
355 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
356 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
357 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
358 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
359 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
360 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
361 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
362 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
363 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
364 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
365 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
366} DAC_TypeDef;
367
368/**
369 * @brief DFSDM module registers
370 */
371typedef struct
372{
373 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
374 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
375 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
376 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
377 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
378 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
379 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
380 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
381 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
382 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
383 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
384 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
385 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
386 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
387 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
388} DFSDM_Filter_TypeDef;
389
390/**
391 * @brief DFSDM channel configuration registers
392 */
393typedef struct
394{
395 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
396 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
397 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
398 short circuit detector register, Address offset: 0x08 */
399 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
400 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
401} DFSDM_Channel_TypeDef;
402
403/**
404 * @brief Debug MCU
405 */
406
407typedef struct
408{
409 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
410 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
411 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
412 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
413 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
414} DBGMCU_TypeDef;
415
416
417/**
418 * @brief DMA Controller
419 */
420
421typedef struct
422{
423 __IO uint32_t CCR; /*!< DMA channel x configuration register */
424 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
425 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
426 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
427} DMA_Channel_TypeDef;
428
429typedef struct
430{
431 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
432 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
433} DMA_TypeDef;
434
435typedef struct
436{
437 __IO uint32_t CSELR; /*!< DMA channel selection register */
438} DMA_Request_TypeDef;
439
440/* Legacy define */
441#define DMA_request_TypeDef DMA_Request_TypeDef
442
443
444/**
445 * @brief External Interrupt/Event Controller
446 */
447
448typedef struct
449{
450 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
451 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
452 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
453 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
454 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
455 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
456 uint32_t RESERVED1; /*!< Reserved, 0x18 */
457 uint32_t RESERVED2; /*!< Reserved, 0x1C */
458 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
459 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
460 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
461 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
462 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
463 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
464} EXTI_TypeDef;
465
466
467/**
468 * @brief Firewall
469 */
470
471typedef struct
472{
473 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
474 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
475 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
476 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
477 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
478 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
479 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
480 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
481 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
482} FIREWALL_TypeDef;
483
484
485/**
486 * @brief FLASH Registers
487 */
488
489typedef struct
490{
491 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
492 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
493 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
494 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
495 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
496 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
497 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
498 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
499 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
500 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
501 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
502 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
503 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
504 uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */
505 __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
506 __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
507 __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
508 __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
509} FLASH_TypeDef;
510
511
512/**
513 * @brief Flexible Memory Controller
514 */
515
516typedef struct
517{
518 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
519} FMC_Bank1_TypeDef;
520
521/**
522 * @brief Flexible Memory Controller Bank1E
523 */
524
525typedef struct
526{
527 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
528} FMC_Bank1E_TypeDef;
529
530/**
531 * @brief Flexible Memory Controller Bank3
532 */
533
534typedef struct
535{
536 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
537 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
538 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
539 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
540 uint32_t RESERVED0; /*!< Reserved, 0x90 */
541 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
542} FMC_Bank3_TypeDef;
543
544/**
545 * @brief General Purpose I/O
546 */
547
548typedef struct
549{
550 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
551 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
552 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
553 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
554 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
555 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
556 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
557 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
558 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
559 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
560 __IO uint32_t ASCR; /*!< GPIO analog switch control register, Address offset: 0x2C */
561
562} GPIO_TypeDef;
563
564
565/**
566 * @brief Inter-integrated Circuit Interface
567 */
568
569typedef struct
570{
571 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
572 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
573 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
574 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
575 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
576 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
577 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
578 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
579 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
580 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
581 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
582} I2C_TypeDef;
583
584/**
585 * @brief Independent WATCHDOG
586 */
587
588typedef struct
589{
590 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
591 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
592 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
593 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
594 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
595} IWDG_TypeDef;
596
597/**
598 * @brief LPTIMER
599 */
600typedef struct
601{
602 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
603 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
604 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
605 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
606 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
607 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
608 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
609 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
610 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
611} LPTIM_TypeDef;
612
613/**
614 * @brief Operational Amplifier (OPAMP)
615 */
616
617typedef struct
618{
619 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
620 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
621 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
622} OPAMP_TypeDef;
623
624typedef struct
625{
626 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
627} OPAMP_Common_TypeDef;
628
629/**
630 * @brief Power Control
631 */
632
633typedef struct
634{
635 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
636 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
637 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
638 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
639 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
640 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
641 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
642 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
643 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
644 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
645 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
646 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
647 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
648 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
649 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
650 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
651 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
652 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
653 __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
654 __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
655 __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
656 __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
657 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
658 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
659} PWR_TypeDef;
660
661
662/**
663 * @brief QUAD Serial Peripheral Interface
664 */
665
666typedef struct
667{
668 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
669 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
670 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
671 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
672 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
673 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
674 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
675 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
676 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
677 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
678 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
679 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
680 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
681} QUADSPI_TypeDef;
682
683
684/**
685 * @brief Reset and Clock Control
686 */
687
688typedef struct
689{
690 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
691 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
692 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
693 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
694 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
695 __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */
696 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
697 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
698 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
699 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
700 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
701 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
702 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
703 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
704 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
705 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
706 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
707 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
708 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
709 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
710 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
711 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
712 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
713 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
714 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
715 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
716 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
717 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
718 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
719 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
720 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
721 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
722 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
723 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
724 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
725 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
726 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
727 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
728} RCC_TypeDef;
729
730/**
731 * @brief Real-Time Clock
732 */
733
734typedef struct
735{
736 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
737 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
738 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
739 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
740 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
741 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
742 uint32_t reserved; /*!< Reserved */
743 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
744 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
745 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
746 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
747 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
748 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
749 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
750 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
751 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
752 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
753 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
754 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
755 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
756 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
757 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
758 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
759 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
760 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
761 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
762 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
763 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
764 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
765 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
766 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
767 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
768 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
769 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
770 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
771 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
772 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
773 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
774 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
775 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
776 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
777 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
778 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
779 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
780 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
781 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
782 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
783 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
784 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
785 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
786 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
787 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
788} RTC_TypeDef;
789
790
791/**
792 * @brief Serial Audio Interface
793 */
794
795typedef struct
796{
797 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
798} SAI_TypeDef;
799
800typedef struct
801{
802 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
803 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
804 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
805 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
806 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
807 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
808 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
809 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
810} SAI_Block_TypeDef;
811
812
813/**
814 * @brief Secure digital input/output Interface
815 */
816
817typedef struct
818{
819 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
820 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
821 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
822 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
823 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
824 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
825 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
826 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
827 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
828 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
829 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
830 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
831 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
832 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
833 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
834 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
835 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
836 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
837 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
838 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
839} SDMMC_TypeDef;
840
841
842/**
843 * @brief Serial Peripheral Interface
844 */
845
846typedef struct
847{
848 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
849 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
850 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
851 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
852 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
853 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
854 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
855} SPI_TypeDef;
856
857
858/**
859 * @brief Single Wire Protocol Master Interface SPWMI
860 */
861
862typedef struct
863{
864 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
865 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
866 uint32_t RESERVED1; /*!< Reserved, 0x08 */
867 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
868 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
869 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
870 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
871 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
872 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
873 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
874} SWPMI_TypeDef;
875
876
877/**
878 * @brief System configuration controller
879 */
880
881typedef struct
882{
883 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
884 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
885 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
886 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
887 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
888 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
889 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
890} SYSCFG_TypeDef;
891
892
893/**
894 * @brief TIM
895 */
896
897typedef struct
898{
899 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
900 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
901 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
902 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
903 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
904 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
905 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
906 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
907 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
908 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
909 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
910 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
911 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
912 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
913 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
914 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
915 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
916 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
917 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
918 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
919 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
920 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
921 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
922 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
923 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
924 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
925} TIM_TypeDef;
926
927
928/**
929 * @brief Touch Sensing Controller (TSC)
930 */
931
932typedef struct
933{
934 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
935 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
936 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
937 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
938 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
939 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
940 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
941 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
942 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
943 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
944 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
945 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
946 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
947 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
948} TSC_TypeDef;
949
950/**
951 * @brief Universal Synchronous Asynchronous Receiver Transmitter
952 */
953
954typedef struct
955{
956 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
957 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
958 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
959 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
960 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
961 uint16_t RESERVED2; /*!< Reserved, 0x12 */
962 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
963 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
964 uint16_t RESERVED3; /*!< Reserved, 0x1A */
965 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
966 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
967 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
968 uint16_t RESERVED4; /*!< Reserved, 0x26 */
969 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
970 uint16_t RESERVED5; /*!< Reserved, 0x2A */
971} USART_TypeDef;
972
973/**
974 * @brief VREFBUF
975 */
976
977typedef struct
978{
979 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
980 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
981} VREFBUF_TypeDef;
982
983/**
984 * @brief Window WATCHDOG
985 */
986
987typedef struct
988{
989 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
990 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
991 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
992} WWDG_TypeDef;
993
994/**
995 * @brief AES hardware accelerator
996 */
997
998typedef struct
999{
1000 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
1001 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
1002 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
1003 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
1004 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
1005 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
1006 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
1007 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
1008 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
1009 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
1010 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
1011 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
1012 __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */
1013 __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */
1014 __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */
1015 __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */
1016 __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */
1017 __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */
1018 __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */
1019 __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */
1020 __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */
1021 __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */
1022 __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */
1023 __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */
1024} AES_TypeDef;
1025
1026/**
1027 * @brief RNG
1028 */
1029
1030typedef struct
1031{
1032 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1033 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1034 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1035} RNG_TypeDef;
1036
1037/**
1038 * @brief USB_OTG_Core_register
1039 */
1040typedef struct
1041{
1042 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
1043 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
1044 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
1045 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
1046 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
1047 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
1048 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
1049 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
1050 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
1051 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
1052 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
1053 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
1054 uint32_t Reserved30[2]; /* Reserved 030h*/
1055 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
1056 __IO uint32_t CID; /* User ID Register 03Ch*/
1057 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1058 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1059 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1060 __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/
1061 uint32_t Reserved6; /* Reserved 050h*/
1062 __IO uint32_t GLPMCFG; /* LPM Register 054h*/
1063 __IO uint32_t GPWRDN; /* Power Down Register 058h*/
1064 __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/
1065 __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/
1066 uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/
1067 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
1068 __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */
1069} USB_OTG_GlobalTypeDef;
1070
1071/**
1072 * @brief USB_OTG_device_Registers
1073 */
1074typedef struct
1075{
1076 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
1077 __IO uint32_t DCTL; /* dev Control Register 804h*/
1078 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
1079 uint32_t Reserved0C; /* Reserved 80Ch*/
1080 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
1081 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
1082 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
1083 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
1084 uint32_t Reserved20; /* Reserved 820h*/
1085 uint32_t Reserved9; /* Reserved 824h*/
1086 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
1087 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
1088 __IO uint32_t DTHRCTL; /* dev thr 830h*/
1089 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
1090 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
1091 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
1092 uint32_t Reserved40; /* dedicated EP mask 840h*/
1093 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
1094 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
1095 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
1096} USB_OTG_DeviceTypeDef;
1097
1098/**
1099 * @brief USB_OTG_IN_Endpoint-Specific_Register
1100 */
1101typedef struct
1102{
1103 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
1104 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
1105 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
1106 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
1107 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
1108 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
1109 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
1110 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
1111} USB_OTG_INEndpointTypeDef;
1112
1113/**
1114 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1115 */
1116typedef struct
1117{
1118 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
1119 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
1120 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
1121 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
1122 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
1123 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
1124 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
1125} USB_OTG_OUTEndpointTypeDef;
1126
1127/**
1128 * @brief USB_OTG_Host_Mode_Register_Structures
1129 */
1130typedef struct
1131{
1132 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
1133 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
1134 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
1135 uint32_t Reserved40C; /* Reserved 40Ch*/
1136 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
1137 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
1138 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
1139} USB_OTG_HostTypeDef;
1140
1141/**
1142 * @brief USB_OTG_Host_Channel_Specific_Registers
1143 */
1144typedef struct
1145{
1146 __IO uint32_t HCCHAR;
1147 __IO uint32_t HCSPLT;
1148 __IO uint32_t HCINT;
1149 __IO uint32_t HCINTMSK;
1150 __IO uint32_t HCTSIZ;
1151 __IO uint32_t HCDMA;
1152 uint32_t Reserved[2];
1153} USB_OTG_HostChannelTypeDef;
1154
1155/**
1156 * @}
1157 */
1158
1159/** @addtogroup Peripheral_memory_map
1160 * @{
1161 */
1162#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
1163#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address */
1164#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */
1165#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
1166#define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */
1167#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */
1168
1169#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
1170#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
1171#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
1172#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
1173
1174/* Legacy defines */
1175#define SRAM_BASE SRAM1_BASE
1176#define SRAM_BB_BASE SRAM1_BB_BASE
1177
1178#define SRAM1_SIZE_MAX ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */
1179#define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */
1180
1181/*!< Peripheral memory map */
1182#define APB1PERIPH_BASE PERIPH_BASE
1183#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1184#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1185#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
1186
1187#define FMC_BANK1 FMC_BASE
1188#define FMC_BANK1_1 FMC_BANK1
1189#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U)
1190#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U)
1191#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U)
1192#define FMC_BANK3 (FMC_BASE + 0x20000000U)
1193
1194/*!< APB1 peripherals */
1195#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1196#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1197#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1198#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1199#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1200#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1201#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1202#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1203#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1204#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1205#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1206#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1207#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1208#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1209#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1210#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1211#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1212#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1213#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1214#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1215#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1216#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
1217#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
1218#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
1219#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U)
1220#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
1221#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
1222#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U)
1223#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
1224
1225
1226/*!< APB2 peripherals */
1227#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
1228#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U)
1229#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
1230#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
1231#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
1232#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
1233#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U)
1234#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
1235#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1236#define TIM8_BASE (APB2PERIPH_BASE + 0x3400U)
1237#define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
1238#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
1239#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
1240#define TIM17_BASE (APB2PERIPH_BASE + 0x4800U)
1241#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
1242#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
1243#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
1244#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
1245#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
1246#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
1247#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
1248#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
1249#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
1250#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
1251#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
1252#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)
1253#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)
1254#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)
1255#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)
1256#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
1257#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
1258#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200)
1259#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280)
1260
1261/*!< AHB1 peripherals */
1262#define DMA1_BASE (AHB1PERIPH_BASE)
1263#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
1264#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
1265#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
1266#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1267#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
1268
1269
1270#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
1271#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
1272#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
1273#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
1274#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
1275#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
1276#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
1277#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U)
1278
1279
1280#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
1281#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
1282#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
1283#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
1284#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
1285#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
1286#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
1287#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U)
1288
1289
1290/*!< AHB2 peripherals */
1291#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
1292#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
1293#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
1294#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U)
1295#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U)
1296#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U)
1297#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U)
1298#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
1299
1300#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U)
1301
1302#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
1303#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U)
1304#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U)
1305#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
1306
1307
1308#define AES_BASE (AHB2PERIPH_BASE + 0x08060000U)
1309#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
1310
1311
1312/*!< FMC Banks registers base address */
1313#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1314#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1315#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1316
1317/* Debug MCU registers base address */
1318#define DBGMCU_BASE ((uint32_t)0xE0042000U)
1319
1320/*!< USB registers base address */
1321#define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U)
1322
1323#define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U)
1324#define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U)
1325#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U)
1326#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U)
1327#define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U)
1328#define USB_OTG_HOST_BASE ((uint32_t)0x00000400U)
1329#define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U)
1330#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U)
1331#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U)
1332#define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U)
1333#define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U)
1334#define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U)
1335
1336
1337#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
1338#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
1339#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
1340/**
1341 * @}
1342 */
1343
1344/** @addtogroup Peripheral_declaration
1345 * @{
1346 */
1347#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1348#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1349#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1350#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1351#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1352#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1353#define RTC ((RTC_TypeDef *) RTC_BASE)
1354#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1355#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1356#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1357#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1358#define USART2 ((USART_TypeDef *) USART2_BASE)
1359#define USART3 ((USART_TypeDef *) USART3_BASE)
1360#define UART4 ((USART_TypeDef *) UART4_BASE)
1361#define UART5 ((USART_TypeDef *) UART5_BASE)
1362#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1363#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1364#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1365#define CAN ((CAN_TypeDef *) CAN1_BASE)
1366#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1367#define PWR ((PWR_TypeDef *) PWR_BASE)
1368#define DAC ((DAC_TypeDef *) DAC1_BASE)
1369#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1370#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1371#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1372#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
1373#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1374#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1375#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1376#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
1377#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
1378
1379#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1380#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
1381#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1382#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1383#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
1384#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1385#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
1386#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1387#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1388#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1389#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1390#define USART1 ((USART_TypeDef *) USART1_BASE)
1391#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1392#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1393#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1394#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1395#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1396#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1397#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1398#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1399#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1400#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1401#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1402#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1403#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1404#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
1405#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
1406#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
1407#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
1408#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1409#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1410#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
1411#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
1412/* Aliases to keep compatibility after DFSDM renaming */
1413#define DFSDM_Channel0 DFSDM1_Channel0
1414#define DFSDM_Channel1 DFSDM1_Channel1
1415#define DFSDM_Channel2 DFSDM1_Channel2
1416#define DFSDM_Channel3 DFSDM1_Channel3
1417#define DFSDM_Channel4 DFSDM1_Channel4
1418#define DFSDM_Channel5 DFSDM1_Channel5
1419#define DFSDM_Channel6 DFSDM1_Channel6
1420#define DFSDM_Channel7 DFSDM1_Channel7
1421#define DFSDM_Filter0 DFSDM1_Filter0
1422#define DFSDM_Filter1 DFSDM1_Filter1
1423#define DFSDM_Filter2 DFSDM1_Filter2
1424#define DFSDM_Filter3 DFSDM1_Filter3
1425#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1426#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1427#define RCC ((RCC_TypeDef *) RCC_BASE)
1428#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1429#define CRC ((CRC_TypeDef *) CRC_BASE)
1430#define TSC ((TSC_TypeDef *) TSC_BASE)
1431
1432#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1433#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1434#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1435#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1436#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1437#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1438#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1439#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1440#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1441#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1442#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1443#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1444#define AES ((AES_TypeDef *) AES_BASE)
1445#define RNG ((RNG_TypeDef *) RNG_BASE)
1446
1447
1448#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1449#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1450#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1451#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1452#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1453#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1454#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1455#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
1456
1457
1458#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1459#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1460#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1461#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1462#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1463#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1464#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1465#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
1466
1467
1468#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1469#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1470#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1471
1472#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1473
1474#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1475
1476#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1477/**
1478 * @}
1479 */
1480
1481/** @addtogroup Exported_constants
1482 * @{
1483 */
1484
1485/** @addtogroup Peripheral_Registers_Bits_Definition
1486 * @{
1487 */
1488
1489/******************************************************************************/
1490/* Peripheral Registers_Bits_Definition */
1491/******************************************************************************/
1492
1493/******************************************************************************/
1494/* */
1495/* Analog to Digital Converter */
1496/* */
1497/******************************************************************************/
1498
1499/*
1500 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
1501 */
1502#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1503
1504/******************** Bit definition for ADC_ISR register *******************/
1505#define ADC_ISR_ADRDY_Pos (0U)
1506#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
1507#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
1508#define ADC_ISR_EOSMP_Pos (1U)
1509#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
1510#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
1511#define ADC_ISR_EOC_Pos (2U)
1512#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
1513#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
1514#define ADC_ISR_EOS_Pos (3U)
1515#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
1516#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
1517#define ADC_ISR_OVR_Pos (4U)
1518#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
1519#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
1520#define ADC_ISR_JEOC_Pos (5U)
1521#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
1522#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
1523#define ADC_ISR_JEOS_Pos (6U)
1524#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
1525#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
1526#define ADC_ISR_AWD1_Pos (7U)
1527#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
1528#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
1529#define ADC_ISR_AWD2_Pos (8U)
1530#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
1531#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
1532#define ADC_ISR_AWD3_Pos (9U)
1533#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
1534#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
1535#define ADC_ISR_JQOVF_Pos (10U)
1536#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
1537#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
1538
1539/******************** Bit definition for ADC_IER register *******************/
1540#define ADC_IER_ADRDYIE_Pos (0U)
1541#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
1542#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
1543#define ADC_IER_EOSMPIE_Pos (1U)
1544#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
1545#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
1546#define ADC_IER_EOCIE_Pos (2U)
1547#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
1548#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
1549#define ADC_IER_EOSIE_Pos (3U)
1550#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
1551#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
1552#define ADC_IER_OVRIE_Pos (4U)
1553#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
1554#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
1555#define ADC_IER_JEOCIE_Pos (5U)
1556#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
1557#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
1558#define ADC_IER_JEOSIE_Pos (6U)
1559#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
1560#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
1561#define ADC_IER_AWD1IE_Pos (7U)
1562#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
1563#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
1564#define ADC_IER_AWD2IE_Pos (8U)
1565#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
1566#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
1567#define ADC_IER_AWD3IE_Pos (9U)
1568#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
1569#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
1570#define ADC_IER_JQOVFIE_Pos (10U)
1571#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
1572#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
1573
1574/* Legacy defines */
1575#define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
1576#define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
1577#define ADC_IER_EOC (ADC_IER_EOCIE)
1578#define ADC_IER_EOS (ADC_IER_EOSIE)
1579#define ADC_IER_OVR (ADC_IER_OVRIE)
1580#define ADC_IER_JEOC (ADC_IER_JEOCIE)
1581#define ADC_IER_JEOS (ADC_IER_JEOSIE)
1582#define ADC_IER_AWD1 (ADC_IER_AWD1IE)
1583#define ADC_IER_AWD2 (ADC_IER_AWD2IE)
1584#define ADC_IER_AWD3 (ADC_IER_AWD3IE)
1585#define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
1586
1587/******************** Bit definition for ADC_CR register ********************/
1588#define ADC_CR_ADEN_Pos (0U)
1589#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
1590#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
1591#define ADC_CR_ADDIS_Pos (1U)
1592#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
1593#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
1594#define ADC_CR_ADSTART_Pos (2U)
1595#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
1596#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
1597#define ADC_CR_JADSTART_Pos (3U)
1598#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
1599#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
1600#define ADC_CR_ADSTP_Pos (4U)
1601#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
1602#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
1603#define ADC_CR_JADSTP_Pos (5U)
1604#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
1605#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
1606#define ADC_CR_ADVREGEN_Pos (28U)
1607#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
1608#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
1609#define ADC_CR_DEEPPWD_Pos (29U)
1610#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
1611#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
1612#define ADC_CR_ADCALDIF_Pos (30U)
1613#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
1614#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
1615#define ADC_CR_ADCAL_Pos (31U)
1616#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
1617#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
1618
1619/******************** Bit definition for ADC_CFGR register ******************/
1620#define ADC_CFGR_DMAEN_Pos (0U)
1621#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
1622#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
1623#define ADC_CFGR_DMACFG_Pos (1U)
1624#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
1625#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
1626
1627#define ADC_CFGR_RES_Pos (3U)
1628#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
1629#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
1630#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
1631#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
1632
1633#define ADC_CFGR_ALIGN_Pos (5U)
1634#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
1635#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1636
1637#define ADC_CFGR_EXTSEL_Pos (6U)
1638#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
1639#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
1640#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
1641#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
1642#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
1643#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
1644
1645#define ADC_CFGR_EXTEN_Pos (10U)
1646#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
1647#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
1648#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
1649#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
1650
1651#define ADC_CFGR_OVRMOD_Pos (12U)
1652#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
1653#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
1654#define ADC_CFGR_CONT_Pos (13U)
1655#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
1656#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
1657#define ADC_CFGR_AUTDLY_Pos (14U)
1658#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
1659#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
1660
1661#define ADC_CFGR_DISCEN_Pos (16U)
1662#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
1663#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
1664
1665#define ADC_CFGR_DISCNUM_Pos (17U)
1666#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
1667#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
1668#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
1669#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
1670#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
1671
1672#define ADC_CFGR_JDISCEN_Pos (20U)
1673#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
1674#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
1675#define ADC_CFGR_JQM_Pos (21U)
1676#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
1677#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
1678#define ADC_CFGR_AWD1SGL_Pos (22U)
1679#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
1680#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1681#define ADC_CFGR_AWD1EN_Pos (23U)
1682#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
1683#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1684#define ADC_CFGR_JAWD1EN_Pos (24U)
1685#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
1686#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1687#define ADC_CFGR_JAUTO_Pos (25U)
1688#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
1689#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
1690
1691#define ADC_CFGR_AWD1CH_Pos (26U)
1692#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
1693#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
1694#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
1695#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
1696#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
1697#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
1698#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
1699
1700#define ADC_CFGR_JQDIS_Pos (31U)
1701#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
1702#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
1703
1704/******************** Bit definition for ADC_CFGR2 register *****************/
1705#define ADC_CFGR2_ROVSE_Pos (0U)
1706#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
1707#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
1708#define ADC_CFGR2_JOVSE_Pos (1U)
1709#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
1710#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
1711
1712#define ADC_CFGR2_OVSR_Pos (2U)
1713#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
1714#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
1715#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
1716#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
1717#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
1718
1719#define ADC_CFGR2_OVSS_Pos (5U)
1720#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
1721#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
1722#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
1723#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
1724#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
1725#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
1726
1727#define ADC_CFGR2_TROVS_Pos (9U)
1728#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
1729#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1730#define ADC_CFGR2_ROVSM_Pos (10U)
1731#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
1732#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1733
1734/******************** Bit definition for ADC_SMPR1 register *****************/
1735#define ADC_SMPR1_SMP0_Pos (0U)
1736#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
1737#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
1738#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
1739#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
1740#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
1741
1742#define ADC_SMPR1_SMP1_Pos (3U)
1743#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
1744#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
1745#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
1746#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
1747#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
1748
1749#define ADC_SMPR1_SMP2_Pos (6U)
1750#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
1751#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
1752#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
1753#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
1754#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
1755
1756#define ADC_SMPR1_SMP3_Pos (9U)
1757#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
1758#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
1759#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
1760#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
1761#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
1762
1763#define ADC_SMPR1_SMP4_Pos (12U)
1764#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
1765#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
1766#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
1767#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
1768#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
1769
1770#define ADC_SMPR1_SMP5_Pos (15U)
1771#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
1772#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
1773#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
1774#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
1775#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
1776
1777#define ADC_SMPR1_SMP6_Pos (18U)
1778#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
1779#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
1780#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
1781#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
1782#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
1783
1784#define ADC_SMPR1_SMP7_Pos (21U)
1785#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
1786#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
1787#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
1788#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
1789#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
1790
1791#define ADC_SMPR1_SMP8_Pos (24U)
1792#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
1793#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
1794#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
1795#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
1796#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
1797
1798#define ADC_SMPR1_SMP9_Pos (27U)
1799#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
1800#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
1801#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
1802#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
1803#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
1804
1805/******************** Bit definition for ADC_SMPR2 register *****************/
1806#define ADC_SMPR2_SMP10_Pos (0U)
1807#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
1808#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
1809#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
1810#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
1811#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
1812
1813#define ADC_SMPR2_SMP11_Pos (3U)
1814#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
1815#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
1816#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
1817#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
1818#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
1819
1820#define ADC_SMPR2_SMP12_Pos (6U)
1821#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
1822#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
1823#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
1824#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
1825#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
1826
1827#define ADC_SMPR2_SMP13_Pos (9U)
1828#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
1829#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
1830#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
1831#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
1832#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
1833
1834#define ADC_SMPR2_SMP14_Pos (12U)
1835#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
1836#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
1837#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
1838#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
1839#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
1840
1841#define ADC_SMPR2_SMP15_Pos (15U)
1842#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
1843#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
1844#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
1845#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
1846#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
1847
1848#define ADC_SMPR2_SMP16_Pos (18U)
1849#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
1850#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
1851#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
1852#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
1853#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
1854
1855#define ADC_SMPR2_SMP17_Pos (21U)
1856#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
1857#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
1858#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
1859#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
1860#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
1861
1862#define ADC_SMPR2_SMP18_Pos (24U)
1863#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
1864#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
1865#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
1866#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
1867#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
1868
1869/******************** Bit definition for ADC_TR1 register *******************/
1870#define ADC_TR1_LT1_Pos (0U)
1871#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
1872#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
1873#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
1874#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
1875#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
1876#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
1877#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
1878#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
1879#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
1880#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
1881#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
1882#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
1883#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
1884#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
1885
1886#define ADC_TR1_HT1_Pos (16U)
1887#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
1888#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
1889#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
1890#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
1891#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
1892#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
1893#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
1894#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
1895#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
1896#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
1897#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
1898#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
1899#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
1900#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
1901
1902/******************** Bit definition for ADC_TR2 register *******************/
1903#define ADC_TR2_LT2_Pos (0U)
1904#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
1905#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
1906#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
1907#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
1908#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
1909#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
1910#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
1911#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
1912#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
1913#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
1914
1915#define ADC_TR2_HT2_Pos (16U)
1916#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
1917#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
1918#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
1919#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
1920#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
1921#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
1922#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
1923#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
1924#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
1925#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
1926
1927/******************** Bit definition for ADC_TR3 register *******************/
1928#define ADC_TR3_LT3_Pos (0U)
1929#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
1930#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
1931#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
1932#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
1933#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
1934#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
1935#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
1936#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
1937#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
1938#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
1939
1940#define ADC_TR3_HT3_Pos (16U)
1941#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
1942#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
1943#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
1944#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
1945#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
1946#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
1947#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
1948#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
1949#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
1950#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
1951
1952/******************** Bit definition for ADC_SQR1 register ******************/
1953#define ADC_SQR1_L_Pos (0U)
1954#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
1955#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
1956#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
1957#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
1958#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
1959#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
1960
1961#define ADC_SQR1_SQ1_Pos (6U)
1962#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
1963#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
1964#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
1965#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
1966#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
1967#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
1968#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
1969
1970#define ADC_SQR1_SQ2_Pos (12U)
1971#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
1972#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
1973#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
1974#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
1975#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
1976#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
1977#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
1978
1979#define ADC_SQR1_SQ3_Pos (18U)
1980#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
1981#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
1982#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
1983#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
1984#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
1985#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
1986#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
1987
1988#define ADC_SQR1_SQ4_Pos (24U)
1989#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
1990#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
1991#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
1992#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
1993#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
1994#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
1995#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
1996
1997/******************** Bit definition for ADC_SQR2 register ******************/
1998#define ADC_SQR2_SQ5_Pos (0U)
1999#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
2000#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
2001#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
2002#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
2003#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
2004#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
2005#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
2006
2007#define ADC_SQR2_SQ6_Pos (6U)
2008#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
2009#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
2010#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
2011#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
2012#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
2013#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
2014#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
2015
2016#define ADC_SQR2_SQ7_Pos (12U)
2017#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
2018#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
2019#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
2020#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
2021#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
2022#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
2023#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
2024
2025#define ADC_SQR2_SQ8_Pos (18U)
2026#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
2027#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
2028#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
2029#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
2030#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
2031#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
2032#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
2033
2034#define ADC_SQR2_SQ9_Pos (24U)
2035#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
2036#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
2037#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
2038#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
2039#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
2040#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
2041#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
2042
2043/******************** Bit definition for ADC_SQR3 register ******************/
2044#define ADC_SQR3_SQ10_Pos (0U)
2045#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
2046#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
2047#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
2048#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
2049#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
2050#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
2051#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
2052
2053#define ADC_SQR3_SQ11_Pos (6U)
2054#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
2055#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
2056#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
2057#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
2058#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
2059#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
2060#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
2061
2062#define ADC_SQR3_SQ12_Pos (12U)
2063#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
2064#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
2065#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
2066#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
2067#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
2068#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
2069#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
2070
2071#define ADC_SQR3_SQ13_Pos (18U)
2072#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
2073#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
2074#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
2075#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
2076#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
2077#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
2078#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
2079
2080#define ADC_SQR3_SQ14_Pos (24U)
2081#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
2082#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
2083#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
2084#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
2085#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
2086#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
2087#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
2088
2089/******************** Bit definition for ADC_SQR4 register ******************/
2090#define ADC_SQR4_SQ15_Pos (0U)
2091#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
2092#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
2093#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
2094#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
2095#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
2096#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
2097#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
2098
2099#define ADC_SQR4_SQ16_Pos (6U)
2100#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
2101#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
2102#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
2103#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
2104#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
2105#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
2106#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
2107
2108/******************** Bit definition for ADC_DR register ********************/
2109#define ADC_DR_RDATA_Pos (0U)
2110#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
2111#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
2112#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
2113#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
2114#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
2115#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
2116#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
2117#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
2118#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
2119#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
2120#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
2121#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
2122#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
2123#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
2124#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
2125#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
2126#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
2127#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
2128
2129/******************** Bit definition for ADC_JSQR register ******************/
2130#define ADC_JSQR_JL_Pos (0U)
2131#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
2132#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
2133#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
2134#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
2135
2136#define ADC_JSQR_JEXTSEL_Pos (2U)
2137#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
2138#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
2139#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
2140#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
2141#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
2142#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
2143
2144#define ADC_JSQR_JEXTEN_Pos (6U)
2145#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
2146#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
2147#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
2148#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
2149
2150#define ADC_JSQR_JSQ1_Pos (8U)
2151#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
2152#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
2153#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
2154#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
2155#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
2156#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
2157#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
2158
2159#define ADC_JSQR_JSQ2_Pos (14U)
2160#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
2161#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
2162#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
2163#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
2164#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
2165#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
2166#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
2167
2168#define ADC_JSQR_JSQ3_Pos (20U)
2169#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
2170#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
2171#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
2172#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
2173#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
2174#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
2175#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
2176
2177#define ADC_JSQR_JSQ4_Pos (26U)
2178#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
2179#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
2180#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
2181#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
2182#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
2183#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
2184#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
2185
2186/******************** Bit definition for ADC_OFR1 register ******************/
2187#define ADC_OFR1_OFFSET1_Pos (0U)
2188#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
2189#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
2190#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
2191#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
2192#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
2193#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
2194#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
2195#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
2196#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
2197#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
2198#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
2199#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
2200#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
2201#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
2202
2203#define ADC_OFR1_OFFSET1_CH_Pos (26U)
2204#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
2205#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
2206#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
2207#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
2208#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
2209#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
2210#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
2211
2212#define ADC_OFR1_OFFSET1_EN_Pos (31U)
2213#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
2214#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
2215
2216/******************** Bit definition for ADC_OFR2 register ******************/
2217#define ADC_OFR2_OFFSET2_Pos (0U)
2218#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
2219#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
2220#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
2221#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
2222#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
2223#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
2224#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
2225#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
2226#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
2227#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
2228#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
2229#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
2230#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
2231#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
2232
2233#define ADC_OFR2_OFFSET2_CH_Pos (26U)
2234#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
2235#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
2236#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
2237#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
2238#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
2239#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
2240#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
2241
2242#define ADC_OFR2_OFFSET2_EN_Pos (31U)
2243#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
2244#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
2245
2246/******************** Bit definition for ADC_OFR3 register ******************/
2247#define ADC_OFR3_OFFSET3_Pos (0U)
2248#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
2249#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
2250#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
2251#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
2252#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
2253#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
2254#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
2255#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
2256#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
2257#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
2258#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
2259#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
2260#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
2261#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
2262
2263#define ADC_OFR3_OFFSET3_CH_Pos (26U)
2264#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
2265#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
2266#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
2267#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
2268#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
2269#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
2270#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
2271
2272#define ADC_OFR3_OFFSET3_EN_Pos (31U)
2273#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
2274#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
2275
2276/******************** Bit definition for ADC_OFR4 register ******************/
2277#define ADC_OFR4_OFFSET4_Pos (0U)
2278#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
2279#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
2280#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
2281#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
2282#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
2283#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
2284#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
2285#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
2286#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
2287#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
2288#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
2289#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
2290#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
2291#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
2292
2293#define ADC_OFR4_OFFSET4_CH_Pos (26U)
2294#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
2295#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
2296#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
2297#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
2298#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
2299#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
2300#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
2301
2302#define ADC_OFR4_OFFSET4_EN_Pos (31U)
2303#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
2304#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
2305
2306/******************** Bit definition for ADC_JDR1 register ******************/
2307#define ADC_JDR1_JDATA_Pos (0U)
2308#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
2309#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
2310#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
2311#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
2312#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
2313#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
2314#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
2315#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
2316#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
2317#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
2318#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
2319#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
2320#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
2321#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
2322#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
2323#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
2324#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
2325#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
2326
2327/******************** Bit definition for ADC_JDR2 register ******************/
2328#define ADC_JDR2_JDATA_Pos (0U)
2329#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
2330#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
2331#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
2332#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
2333#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
2334#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
2335#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
2336#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
2337#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
2338#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
2339#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
2340#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
2341#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
2342#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
2343#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
2344#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
2345#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
2346#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
2347
2348/******************** Bit definition for ADC_JDR3 register ******************/
2349#define ADC_JDR3_JDATA_Pos (0U)
2350#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
2351#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
2352#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
2353#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
2354#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
2355#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
2356#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
2357#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
2358#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
2359#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
2360#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
2361#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
2362#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
2363#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
2364#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
2365#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
2366#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
2367#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
2368
2369/******************** Bit definition for ADC_JDR4 register ******************/
2370#define ADC_JDR4_JDATA_Pos (0U)
2371#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
2372#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
2373#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
2374#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
2375#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
2376#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
2377#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
2378#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
2379#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
2380#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
2381#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
2382#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
2383#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
2384#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
2385#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
2386#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
2387#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
2388#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
2389
2390/******************** Bit definition for ADC_AWD2CR register ****************/
2391#define ADC_AWD2CR_AWD2CH_Pos (0U)
2392#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
2393#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
2394#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
2395#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
2396#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
2397#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
2398#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
2399#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
2400#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
2401#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
2402#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
2403#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
2404#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
2405#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
2406#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
2407#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
2408#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
2409#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
2410#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
2411#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
2412#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
2413
2414/******************** Bit definition for ADC_AWD3CR register ****************/
2415#define ADC_AWD3CR_AWD3CH_Pos (0U)
2416#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
2417#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
2418#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
2419#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
2420#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
2421#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
2422#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
2423#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
2424#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
2425#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
2426#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
2427#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
2428#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
2429#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
2430#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
2431#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
2432#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
2433#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
2434#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
2435#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
2436#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
2437
2438/******************** Bit definition for ADC_DIFSEL register ****************/
2439#define ADC_DIFSEL_DIFSEL_Pos (0U)
2440#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
2441#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
2442#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
2443#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
2444#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
2445#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
2446#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
2447#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
2448#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
2449#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
2450#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
2451#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
2452#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
2453#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
2454#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
2455#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
2456#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
2457#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
2458#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
2459#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
2460#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
2461
2462/******************** Bit definition for ADC_CALFACT register ***************/
2463#define ADC_CALFACT_CALFACT_S_Pos (0U)
2464#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
2465#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
2466#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
2467#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
2468#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
2469#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
2470#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
2471#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
2472#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
2473
2474#define ADC_CALFACT_CALFACT_D_Pos (16U)
2475#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
2476#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
2477#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
2478#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
2479#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
2480#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
2481#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
2482#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
2483#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
2484
2485/************************* ADC Common registers *****************************/
2486/******************** Bit definition for ADC_CSR register *******************/
2487#define ADC_CSR_ADRDY_MST_Pos (0U)
2488#define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
2489#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
2490#define ADC_CSR_EOSMP_MST_Pos (1U)
2491#define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
2492#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
2493#define ADC_CSR_EOC_MST_Pos (2U)
2494#define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
2495#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
2496#define ADC_CSR_EOS_MST_Pos (3U)
2497#define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
2498#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
2499#define ADC_CSR_OVR_MST_Pos (4U)
2500#define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
2501#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
2502#define ADC_CSR_JEOC_MST_Pos (5U)
2503#define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
2504#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
2505#define ADC_CSR_JEOS_MST_Pos (6U)
2506#define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
2507#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
2508#define ADC_CSR_AWD1_MST_Pos (7U)
2509#define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
2510#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
2511#define ADC_CSR_AWD2_MST_Pos (8U)
2512#define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
2513#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
2514#define ADC_CSR_AWD3_MST_Pos (9U)
2515#define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
2516#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
2517#define ADC_CSR_JQOVF_MST_Pos (10U)
2518#define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
2519#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
2520
2521#define ADC_CSR_ADRDY_SLV_Pos (16U)
2522#define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
2523#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
2524#define ADC_CSR_EOSMP_SLV_Pos (17U)
2525#define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
2526#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
2527#define ADC_CSR_EOC_SLV_Pos (18U)
2528#define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
2529#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
2530#define ADC_CSR_EOS_SLV_Pos (19U)
2531#define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
2532#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
2533#define ADC_CSR_OVR_SLV_Pos (20U)
2534#define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
2535#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
2536#define ADC_CSR_JEOC_SLV_Pos (21U)
2537#define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
2538#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
2539#define ADC_CSR_JEOS_SLV_Pos (22U)
2540#define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
2541#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
2542#define ADC_CSR_AWD1_SLV_Pos (23U)
2543#define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
2544#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
2545#define ADC_CSR_AWD2_SLV_Pos (24U)
2546#define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
2547#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
2548#define ADC_CSR_AWD3_SLV_Pos (25U)
2549#define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
2550#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
2551#define ADC_CSR_JQOVF_SLV_Pos (26U)
2552#define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
2553#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
2554
2555/******************** Bit definition for ADC_CCR register *******************/
2556#define ADC_CCR_DUAL_Pos (0U)
2557#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
2558#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
2559#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
2560#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
2561#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
2562#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
2563#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
2564
2565#define ADC_CCR_DELAY_Pos (8U)
2566#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
2567#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
2568#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
2569#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
2570#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
2571#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
2572
2573#define ADC_CCR_DMACFG_Pos (13U)
2574#define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
2575#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
2576
2577#define ADC_CCR_MDMA_Pos (14U)
2578#define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
2579#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
2580#define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
2581#define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
2582
2583#define ADC_CCR_CKMODE_Pos (16U)
2584#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
2585#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2586#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
2587#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
2588
2589#define ADC_CCR_PRESC_Pos (18U)
2590#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
2591#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
2592#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
2593#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
2594#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
2595#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
2596
2597#define ADC_CCR_VREFEN_Pos (22U)
2598#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
2599#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
2600#define ADC_CCR_TSEN_Pos (23U)
2601#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
2602#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
2603#define ADC_CCR_VBATEN_Pos (24U)
2604#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
2605#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
2606
2607/******************** Bit definition for ADC_CDR register *******************/
2608#define ADC_CDR_RDATA_MST_Pos (0U)
2609#define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
2610#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
2611#define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
2612#define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
2613#define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
2614#define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
2615#define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
2616#define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
2617#define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
2618#define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
2619#define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
2620#define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
2621#define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
2622#define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
2623#define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
2624#define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
2625#define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
2626#define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
2627
2628#define ADC_CDR_RDATA_SLV_Pos (16U)
2629#define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
2630#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
2631#define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
2632#define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
2633#define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
2634#define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
2635#define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
2636#define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
2637#define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
2638#define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
2639#define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
2640#define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
2641#define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
2642#define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
2643#define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
2644#define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
2645#define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
2646#define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
2647
2648/******************************************************************************/
2649/* */
2650/* Controller Area Network */
2651/* */
2652/******************************************************************************/
2653/*!<CAN control and status registers */
2654/******************* Bit definition for CAN_MCR register ********************/
2655#define CAN_MCR_INRQ_Pos (0U)
2656#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
2657#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
2658#define CAN_MCR_SLEEP_Pos (1U)
2659#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
2660#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
2661#define CAN_MCR_TXFP_Pos (2U)
2662#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
2663#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
2664#define CAN_MCR_RFLM_Pos (3U)
2665#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
2666#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
2667#define CAN_MCR_NART_Pos (4U)
2668#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
2669#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
2670#define CAN_MCR_AWUM_Pos (5U)
2671#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
2672#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
2673#define CAN_MCR_ABOM_Pos (6U)
2674#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
2675#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
2676#define CAN_MCR_TTCM_Pos (7U)
2677#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
2678#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
2679#define CAN_MCR_RESET_Pos (15U)
2680#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
2681#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
2682
2683/******************* Bit definition for CAN_MSR register ********************/
2684#define CAN_MSR_INAK_Pos (0U)
2685#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
2686#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
2687#define CAN_MSR_SLAK_Pos (1U)
2688#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
2689#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
2690#define CAN_MSR_ERRI_Pos (2U)
2691#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
2692#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
2693#define CAN_MSR_WKUI_Pos (3U)
2694#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
2695#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
2696#define CAN_MSR_SLAKI_Pos (4U)
2697#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
2698#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
2699#define CAN_MSR_TXM_Pos (8U)
2700#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
2701#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
2702#define CAN_MSR_RXM_Pos (9U)
2703#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
2704#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
2705#define CAN_MSR_SAMP_Pos (10U)
2706#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
2707#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
2708#define CAN_MSR_RX_Pos (11U)
2709#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
2710#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
2711
2712/******************* Bit definition for CAN_TSR register ********************/
2713#define CAN_TSR_RQCP0_Pos (0U)
2714#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
2715#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
2716#define CAN_TSR_TXOK0_Pos (1U)
2717#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
2718#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
2719#define CAN_TSR_ALST0_Pos (2U)
2720#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
2721#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
2722#define CAN_TSR_TERR0_Pos (3U)
2723#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
2724#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
2725#define CAN_TSR_ABRQ0_Pos (7U)
2726#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
2727#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
2728#define CAN_TSR_RQCP1_Pos (8U)
2729#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
2730#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
2731#define CAN_TSR_TXOK1_Pos (9U)
2732#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
2733#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
2734#define CAN_TSR_ALST1_Pos (10U)
2735#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
2736#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
2737#define CAN_TSR_TERR1_Pos (11U)
2738#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
2739#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
2740#define CAN_TSR_ABRQ1_Pos (15U)
2741#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
2742#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
2743#define CAN_TSR_RQCP2_Pos (16U)
2744#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
2745#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
2746#define CAN_TSR_TXOK2_Pos (17U)
2747#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
2748#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
2749#define CAN_TSR_ALST2_Pos (18U)
2750#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
2751#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
2752#define CAN_TSR_TERR2_Pos (19U)
2753#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
2754#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
2755#define CAN_TSR_ABRQ2_Pos (23U)
2756#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
2757#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
2758#define CAN_TSR_CODE_Pos (24U)
2759#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
2760#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
2761
2762#define CAN_TSR_TME_Pos (26U)
2763#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
2764#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
2765#define CAN_TSR_TME0_Pos (26U)
2766#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
2767#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
2768#define CAN_TSR_TME1_Pos (27U)
2769#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
2770#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
2771#define CAN_TSR_TME2_Pos (28U)
2772#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
2773#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
2774
2775#define CAN_TSR_LOW_Pos (29U)
2776#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
2777#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
2778#define CAN_TSR_LOW0_Pos (29U)
2779#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
2780#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
2781#define CAN_TSR_LOW1_Pos (30U)
2782#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
2783#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
2784#define CAN_TSR_LOW2_Pos (31U)
2785#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
2786#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
2787
2788/******************* Bit definition for CAN_RF0R register *******************/
2789#define CAN_RF0R_FMP0_Pos (0U)
2790#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
2791#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
2792#define CAN_RF0R_FULL0_Pos (3U)
2793#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
2794#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
2795#define CAN_RF0R_FOVR0_Pos (4U)
2796#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
2797#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
2798#define CAN_RF0R_RFOM0_Pos (5U)
2799#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
2800#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
2801
2802/******************* Bit definition for CAN_RF1R register *******************/
2803#define CAN_RF1R_FMP1_Pos (0U)
2804#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
2805#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
2806#define CAN_RF1R_FULL1_Pos (3U)
2807#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
2808#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
2809#define CAN_RF1R_FOVR1_Pos (4U)
2810#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
2811#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
2812#define CAN_RF1R_RFOM1_Pos (5U)
2813#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
2814#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
2815
2816/******************** Bit definition for CAN_IER register *******************/
2817#define CAN_IER_TMEIE_Pos (0U)
2818#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
2819#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
2820#define CAN_IER_FMPIE0_Pos (1U)
2821#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
2822#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
2823#define CAN_IER_FFIE0_Pos (2U)
2824#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
2825#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
2826#define CAN_IER_FOVIE0_Pos (3U)
2827#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
2828#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2829#define CAN_IER_FMPIE1_Pos (4U)
2830#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2831#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2832#define CAN_IER_FFIE1_Pos (5U)
2833#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2834#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2835#define CAN_IER_FOVIE1_Pos (6U)
2836#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2837#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2838#define CAN_IER_EWGIE_Pos (8U)
2839#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2840#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2841#define CAN_IER_EPVIE_Pos (9U)
2842#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2843#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2844#define CAN_IER_BOFIE_Pos (10U)
2845#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2846#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2847#define CAN_IER_LECIE_Pos (11U)
2848#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
2849#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
2850#define CAN_IER_ERRIE_Pos (15U)
2851#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2852#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2853#define CAN_IER_WKUIE_Pos (16U)
2854#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2855#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2856#define CAN_IER_SLKIE_Pos (17U)
2857#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2858#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2859
2860/******************** Bit definition for CAN_ESR register *******************/
2861#define CAN_ESR_EWGF_Pos (0U)
2862#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2863#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2864#define CAN_ESR_EPVF_Pos (1U)
2865#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2866#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2867#define CAN_ESR_BOFF_Pos (2U)
2868#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2869#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2870
2871#define CAN_ESR_LEC_Pos (4U)
2872#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2873#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2874#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2875#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2876#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2877
2878#define CAN_ESR_TEC_Pos (16U)
2879#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2880#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2881#define CAN_ESR_REC_Pos (24U)
2882#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2883#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2884
2885/******************* Bit definition for CAN_BTR register ********************/
2886#define CAN_BTR_BRP_Pos (0U)
2887#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2888#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2889#define CAN_BTR_TS1_Pos (16U)
2890#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2891#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2892#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2893#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2894#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2895#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2896#define CAN_BTR_TS2_Pos (20U)
2897#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2898#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2899#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2900#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2901#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2902#define CAN_BTR_SJW_Pos (24U)
2903#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2904#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2905#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2906#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2907#define CAN_BTR_LBKM_Pos (30U)
2908#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2909#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2910#define CAN_BTR_SILM_Pos (31U)
2911#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2912#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2913
2914/*!<Mailbox registers */
2915/****************** Bit definition for CAN_TI0R register ********************/
2916#define CAN_TI0R_TXRQ_Pos (0U)
2917#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2918#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2919#define CAN_TI0R_RTR_Pos (1U)
2920#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2921#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2922#define CAN_TI0R_IDE_Pos (2U)
2923#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2924#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2925#define CAN_TI0R_EXID_Pos (3U)
2926#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2927#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2928#define CAN_TI0R_STID_Pos (21U)
2929#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2930#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2931
2932/****************** Bit definition for CAN_TDT0R register *******************/
2933#define CAN_TDT0R_DLC_Pos (0U)
2934#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2935#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2936#define CAN_TDT0R_TGT_Pos (8U)
2937#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2938#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2939#define CAN_TDT0R_TIME_Pos (16U)
2940#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2941#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2942
2943/****************** Bit definition for CAN_TDL0R register *******************/
2944#define CAN_TDL0R_DATA0_Pos (0U)
2945#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2946#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2947#define CAN_TDL0R_DATA1_Pos (8U)
2948#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2949#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2950#define CAN_TDL0R_DATA2_Pos (16U)
2951#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2952#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2953#define CAN_TDL0R_DATA3_Pos (24U)
2954#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2955#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2956
2957/****************** Bit definition for CAN_TDH0R register *******************/
2958#define CAN_TDH0R_DATA4_Pos (0U)
2959#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2960#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2961#define CAN_TDH0R_DATA5_Pos (8U)
2962#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2963#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2964#define CAN_TDH0R_DATA6_Pos (16U)
2965#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2966#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2967#define CAN_TDH0R_DATA7_Pos (24U)
2968#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2969#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2970
2971/******************* Bit definition for CAN_TI1R register *******************/
2972#define CAN_TI1R_TXRQ_Pos (0U)
2973#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2974#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2975#define CAN_TI1R_RTR_Pos (1U)
2976#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2977#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2978#define CAN_TI1R_IDE_Pos (2U)
2979#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2980#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2981#define CAN_TI1R_EXID_Pos (3U)
2982#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2983#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2984#define CAN_TI1R_STID_Pos (21U)
2985#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2986#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2987
2988/******************* Bit definition for CAN_TDT1R register ******************/
2989#define CAN_TDT1R_DLC_Pos (0U)
2990#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2991#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2992#define CAN_TDT1R_TGT_Pos (8U)
2993#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2994#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2995#define CAN_TDT1R_TIME_Pos (16U)
2996#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2997#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2998
2999/******************* Bit definition for CAN_TDL1R register ******************/
3000#define CAN_TDL1R_DATA0_Pos (0U)
3001#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
3002#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
3003#define CAN_TDL1R_DATA1_Pos (8U)
3004#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
3005#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
3006#define CAN_TDL1R_DATA2_Pos (16U)
3007#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
3008#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
3009#define CAN_TDL1R_DATA3_Pos (24U)
3010#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
3011#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
3012
3013/******************* Bit definition for CAN_TDH1R register ******************/
3014#define CAN_TDH1R_DATA4_Pos (0U)
3015#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
3016#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
3017#define CAN_TDH1R_DATA5_Pos (8U)
3018#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
3019#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
3020#define CAN_TDH1R_DATA6_Pos (16U)
3021#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
3022#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
3023#define CAN_TDH1R_DATA7_Pos (24U)
3024#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
3025#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
3026
3027/******************* Bit definition for CAN_TI2R register *******************/
3028#define CAN_TI2R_TXRQ_Pos (0U)
3029#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
3030#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
3031#define CAN_TI2R_RTR_Pos (1U)
3032#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
3033#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
3034#define CAN_TI2R_IDE_Pos (2U)
3035#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
3036#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
3037#define CAN_TI2R_EXID_Pos (3U)
3038#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
3039#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
3040#define CAN_TI2R_STID_Pos (21U)
3041#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
3042#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3043
3044/******************* Bit definition for CAN_TDT2R register ******************/
3045#define CAN_TDT2R_DLC_Pos (0U)
3046#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
3047#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
3048#define CAN_TDT2R_TGT_Pos (8U)
3049#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
3050#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
3051#define CAN_TDT2R_TIME_Pos (16U)
3052#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
3053#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
3054
3055/******************* Bit definition for CAN_TDL2R register ******************/
3056#define CAN_TDL2R_DATA0_Pos (0U)
3057#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
3058#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
3059#define CAN_TDL2R_DATA1_Pos (8U)
3060#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
3061#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
3062#define CAN_TDL2R_DATA2_Pos (16U)
3063#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
3064#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
3065#define CAN_TDL2R_DATA3_Pos (24U)
3066#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
3067#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
3068
3069/******************* Bit definition for CAN_TDH2R register ******************/
3070#define CAN_TDH2R_DATA4_Pos (0U)
3071#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
3072#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
3073#define CAN_TDH2R_DATA5_Pos (8U)
3074#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
3075#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
3076#define CAN_TDH2R_DATA6_Pos (16U)
3077#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
3078#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
3079#define CAN_TDH2R_DATA7_Pos (24U)
3080#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
3081#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
3082
3083/******************* Bit definition for CAN_RI0R register *******************/
3084#define CAN_RI0R_RTR_Pos (1U)
3085#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
3086#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
3087#define CAN_RI0R_IDE_Pos (2U)
3088#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
3089#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
3090#define CAN_RI0R_EXID_Pos (3U)
3091#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
3092#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
3093#define CAN_RI0R_STID_Pos (21U)
3094#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
3095#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3096
3097/******************* Bit definition for CAN_RDT0R register ******************/
3098#define CAN_RDT0R_DLC_Pos (0U)
3099#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
3100#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
3101#define CAN_RDT0R_FMI_Pos (8U)
3102#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
3103#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
3104#define CAN_RDT0R_TIME_Pos (16U)
3105#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
3106#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
3107
3108/******************* Bit definition for CAN_RDL0R register ******************/
3109#define CAN_RDL0R_DATA0_Pos (0U)
3110#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
3111#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
3112#define CAN_RDL0R_DATA1_Pos (8U)
3113#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
3114#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
3115#define CAN_RDL0R_DATA2_Pos (16U)
3116#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
3117#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
3118#define CAN_RDL0R_DATA3_Pos (24U)
3119#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
3120#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
3121
3122/******************* Bit definition for CAN_RDH0R register ******************/
3123#define CAN_RDH0R_DATA4_Pos (0U)
3124#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
3125#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
3126#define CAN_RDH0R_DATA5_Pos (8U)
3127#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
3128#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
3129#define CAN_RDH0R_DATA6_Pos (16U)
3130#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
3131#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
3132#define CAN_RDH0R_DATA7_Pos (24U)
3133#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
3134#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
3135
3136/******************* Bit definition for CAN_RI1R register *******************/
3137#define CAN_RI1R_RTR_Pos (1U)
3138#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
3139#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
3140#define CAN_RI1R_IDE_Pos (2U)
3141#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
3142#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
3143#define CAN_RI1R_EXID_Pos (3U)
3144#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
3145#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
3146#define CAN_RI1R_STID_Pos (21U)
3147#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
3148#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3149
3150/******************* Bit definition for CAN_RDT1R register ******************/
3151#define CAN_RDT1R_DLC_Pos (0U)
3152#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
3153#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
3154#define CAN_RDT1R_FMI_Pos (8U)
3155#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
3156#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
3157#define CAN_RDT1R_TIME_Pos (16U)
3158#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
3159#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
3160
3161/******************* Bit definition for CAN_RDL1R register ******************/
3162#define CAN_RDL1R_DATA0_Pos (0U)
3163#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
3164#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
3165#define CAN_RDL1R_DATA1_Pos (8U)
3166#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
3167#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
3168#define CAN_RDL1R_DATA2_Pos (16U)
3169#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
3170#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
3171#define CAN_RDL1R_DATA3_Pos (24U)
3172#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
3173#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
3174
3175/******************* Bit definition for CAN_RDH1R register ******************/
3176#define CAN_RDH1R_DATA4_Pos (0U)
3177#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
3178#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
3179#define CAN_RDH1R_DATA5_Pos (8U)
3180#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
3181#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
3182#define CAN_RDH1R_DATA6_Pos (16U)
3183#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
3184#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
3185#define CAN_RDH1R_DATA7_Pos (24U)
3186#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
3187#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
3188
3189/*!<CAN filter registers */
3190/******************* Bit definition for CAN_FMR register ********************/
3191#define CAN_FMR_FINIT_Pos (0U)
3192#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
3193#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
3194
3195/******************* Bit definition for CAN_FM1R register *******************/
3196#define CAN_FM1R_FBM_Pos (0U)
3197#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
3198#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
3199#define CAN_FM1R_FBM0_Pos (0U)
3200#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
3201#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
3202#define CAN_FM1R_FBM1_Pos (1U)
3203#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
3204#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
3205#define CAN_FM1R_FBM2_Pos (2U)
3206#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
3207#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
3208#define CAN_FM1R_FBM3_Pos (3U)
3209#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
3210#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
3211#define CAN_FM1R_FBM4_Pos (4U)
3212#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
3213#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
3214#define CAN_FM1R_FBM5_Pos (5U)
3215#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
3216#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
3217#define CAN_FM1R_FBM6_Pos (6U)
3218#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
3219#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
3220#define CAN_FM1R_FBM7_Pos (7U)
3221#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
3222#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
3223#define CAN_FM1R_FBM8_Pos (8U)
3224#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
3225#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
3226#define CAN_FM1R_FBM9_Pos (9U)
3227#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
3228#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
3229#define CAN_FM1R_FBM10_Pos (10U)
3230#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
3231#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
3232#define CAN_FM1R_FBM11_Pos (11U)
3233#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
3234#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
3235#define CAN_FM1R_FBM12_Pos (12U)
3236#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
3237#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
3238#define CAN_FM1R_FBM13_Pos (13U)
3239#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
3240#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
3241
3242/******************* Bit definition for CAN_FS1R register *******************/
3243#define CAN_FS1R_FSC_Pos (0U)
3244#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
3245#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
3246#define CAN_FS1R_FSC0_Pos (0U)
3247#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
3248#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
3249#define CAN_FS1R_FSC1_Pos (1U)
3250#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
3251#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
3252#define CAN_FS1R_FSC2_Pos (2U)
3253#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
3254#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
3255#define CAN_FS1R_FSC3_Pos (3U)
3256#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
3257#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
3258#define CAN_FS1R_FSC4_Pos (4U)
3259#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
3260#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
3261#define CAN_FS1R_FSC5_Pos (5U)
3262#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
3263#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
3264#define CAN_FS1R_FSC6_Pos (6U)
3265#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
3266#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
3267#define CAN_FS1R_FSC7_Pos (7U)
3268#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
3269#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
3270#define CAN_FS1R_FSC8_Pos (8U)
3271#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
3272#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
3273#define CAN_FS1R_FSC9_Pos (9U)
3274#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
3275#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
3276#define CAN_FS1R_FSC10_Pos (10U)
3277#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
3278#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
3279#define CAN_FS1R_FSC11_Pos (11U)
3280#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
3281#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
3282#define CAN_FS1R_FSC12_Pos (12U)
3283#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
3284#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
3285#define CAN_FS1R_FSC13_Pos (13U)
3286#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
3287#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
3288
3289/****************** Bit definition for CAN_FFA1R register *******************/
3290#define CAN_FFA1R_FFA_Pos (0U)
3291#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
3292#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
3293#define CAN_FFA1R_FFA0_Pos (0U)
3294#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
3295#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
3296#define CAN_FFA1R_FFA1_Pos (1U)
3297#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
3298#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
3299#define CAN_FFA1R_FFA2_Pos (2U)
3300#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
3301#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
3302#define CAN_FFA1R_FFA3_Pos (3U)
3303#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
3304#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
3305#define CAN_FFA1R_FFA4_Pos (4U)
3306#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
3307#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
3308#define CAN_FFA1R_FFA5_Pos (5U)
3309#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
3310#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
3311#define CAN_FFA1R_FFA6_Pos (6U)
3312#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
3313#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
3314#define CAN_FFA1R_FFA7_Pos (7U)
3315#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
3316#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
3317#define CAN_FFA1R_FFA8_Pos (8U)
3318#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
3319#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
3320#define CAN_FFA1R_FFA9_Pos (9U)
3321#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
3322#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
3323#define CAN_FFA1R_FFA10_Pos (10U)
3324#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
3325#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
3326#define CAN_FFA1R_FFA11_Pos (11U)
3327#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
3328#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
3329#define CAN_FFA1R_FFA12_Pos (12U)
3330#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
3331#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
3332#define CAN_FFA1R_FFA13_Pos (13U)
3333#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
3334#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
3335
3336/******************* Bit definition for CAN_FA1R register *******************/
3337#define CAN_FA1R_FACT_Pos (0U)
3338#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
3339#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
3340#define CAN_FA1R_FACT0_Pos (0U)
3341#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
3342#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
3343#define CAN_FA1R_FACT1_Pos (1U)
3344#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
3345#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
3346#define CAN_FA1R_FACT2_Pos (2U)
3347#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
3348#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
3349#define CAN_FA1R_FACT3_Pos (3U)
3350#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
3351#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
3352#define CAN_FA1R_FACT4_Pos (4U)
3353#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
3354#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
3355#define CAN_FA1R_FACT5_Pos (5U)
3356#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
3357#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
3358#define CAN_FA1R_FACT6_Pos (6U)
3359#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
3360#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
3361#define CAN_FA1R_FACT7_Pos (7U)
3362#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
3363#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
3364#define CAN_FA1R_FACT8_Pos (8U)
3365#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
3366#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
3367#define CAN_FA1R_FACT9_Pos (9U)
3368#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
3369#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
3370#define CAN_FA1R_FACT10_Pos (10U)
3371#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
3372#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
3373#define CAN_FA1R_FACT11_Pos (11U)
3374#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
3375#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
3376#define CAN_FA1R_FACT12_Pos (12U)
3377#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
3378#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
3379#define CAN_FA1R_FACT13_Pos (13U)
3380#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
3381#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
3382
3383/******************* Bit definition for CAN_F0R1 register *******************/
3384#define CAN_F0R1_FB0_Pos (0U)
3385#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
3386#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
3387#define CAN_F0R1_FB1_Pos (1U)
3388#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
3389#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
3390#define CAN_F0R1_FB2_Pos (2U)
3391#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
3392#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
3393#define CAN_F0R1_FB3_Pos (3U)
3394#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
3395#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
3396#define CAN_F0R1_FB4_Pos (4U)
3397#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
3398#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
3399#define CAN_F0R1_FB5_Pos (5U)
3400#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
3401#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
3402#define CAN_F0R1_FB6_Pos (6U)
3403#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
3404#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
3405#define CAN_F0R1_FB7_Pos (7U)
3406#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
3407#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
3408#define CAN_F0R1_FB8_Pos (8U)
3409#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
3410#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
3411#define CAN_F0R1_FB9_Pos (9U)
3412#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
3413#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
3414#define CAN_F0R1_FB10_Pos (10U)
3415#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
3416#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
3417#define CAN_F0R1_FB11_Pos (11U)
3418#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
3419#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
3420#define CAN_F0R1_FB12_Pos (12U)
3421#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
3422#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
3423#define CAN_F0R1_FB13_Pos (13U)
3424#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
3425#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
3426#define CAN_F0R1_FB14_Pos (14U)
3427#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
3428#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
3429#define CAN_F0R1_FB15_Pos (15U)
3430#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
3431#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
3432#define CAN_F0R1_FB16_Pos (16U)
3433#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
3434#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
3435#define CAN_F0R1_FB17_Pos (17U)
3436#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
3437#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
3438#define CAN_F0R1_FB18_Pos (18U)
3439#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
3440#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
3441#define CAN_F0R1_FB19_Pos (19U)
3442#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
3443#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
3444#define CAN_F0R1_FB20_Pos (20U)
3445#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
3446#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
3447#define CAN_F0R1_FB21_Pos (21U)
3448#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
3449#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
3450#define CAN_F0R1_FB22_Pos (22U)
3451#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
3452#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
3453#define CAN_F0R1_FB23_Pos (23U)
3454#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
3455#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
3456#define CAN_F0R1_FB24_Pos (24U)
3457#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
3458#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
3459#define CAN_F0R1_FB25_Pos (25U)
3460#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
3461#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
3462#define CAN_F0R1_FB26_Pos (26U)
3463#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
3464#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
3465#define CAN_F0R1_FB27_Pos (27U)
3466#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
3467#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
3468#define CAN_F0R1_FB28_Pos (28U)
3469#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
3470#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
3471#define CAN_F0R1_FB29_Pos (29U)
3472#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
3473#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
3474#define CAN_F0R1_FB30_Pos (30U)
3475#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
3476#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
3477#define CAN_F0R1_FB31_Pos (31U)
3478#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
3479#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
3480
3481/******************* Bit definition for CAN_F1R1 register *******************/
3482#define CAN_F1R1_FB0_Pos (0U)
3483#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
3484#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
3485#define CAN_F1R1_FB1_Pos (1U)
3486#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
3487#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
3488#define CAN_F1R1_FB2_Pos (2U)
3489#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
3490#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
3491#define CAN_F1R1_FB3_Pos (3U)
3492#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
3493#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
3494#define CAN_F1R1_FB4_Pos (4U)
3495#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
3496#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
3497#define CAN_F1R1_FB5_Pos (5U)
3498#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
3499#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
3500#define CAN_F1R1_FB6_Pos (6U)
3501#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
3502#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
3503#define CAN_F1R1_FB7_Pos (7U)
3504#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
3505#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
3506#define CAN_F1R1_FB8_Pos (8U)
3507#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
3508#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
3509#define CAN_F1R1_FB9_Pos (9U)
3510#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
3511#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
3512#define CAN_F1R1_FB10_Pos (10U)
3513#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
3514#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
3515#define CAN_F1R1_FB11_Pos (11U)
3516#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
3517#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
3518#define CAN_F1R1_FB12_Pos (12U)
3519#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
3520#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
3521#define CAN_F1R1_FB13_Pos (13U)
3522#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
3523#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
3524#define CAN_F1R1_FB14_Pos (14U)
3525#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
3526#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
3527#define CAN_F1R1_FB15_Pos (15U)
3528#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
3529#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
3530#define CAN_F1R1_FB16_Pos (16U)
3531#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
3532#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
3533#define CAN_F1R1_FB17_Pos (17U)
3534#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
3535#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
3536#define CAN_F1R1_FB18_Pos (18U)
3537#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
3538#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
3539#define CAN_F1R1_FB19_Pos (19U)
3540#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
3541#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
3542#define CAN_F1R1_FB20_Pos (20U)
3543#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
3544#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
3545#define CAN_F1R1_FB21_Pos (21U)
3546#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
3547#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
3548#define CAN_F1R1_FB22_Pos (22U)
3549#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
3550#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
3551#define CAN_F1R1_FB23_Pos (23U)
3552#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
3553#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
3554#define CAN_F1R1_FB24_Pos (24U)
3555#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
3556#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
3557#define CAN_F1R1_FB25_Pos (25U)
3558#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
3559#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
3560#define CAN_F1R1_FB26_Pos (26U)
3561#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
3562#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
3563#define CAN_F1R1_FB27_Pos (27U)
3564#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
3565#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
3566#define CAN_F1R1_FB28_Pos (28U)
3567#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
3568#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
3569#define CAN_F1R1_FB29_Pos (29U)
3570#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
3571#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
3572#define CAN_F1R1_FB30_Pos (30U)
3573#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
3574#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
3575#define CAN_F1R1_FB31_Pos (31U)
3576#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
3577#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
3578
3579/******************* Bit definition for CAN_F2R1 register *******************/
3580#define CAN_F2R1_FB0_Pos (0U)
3581#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
3582#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
3583#define CAN_F2R1_FB1_Pos (1U)
3584#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
3585#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
3586#define CAN_F2R1_FB2_Pos (2U)
3587#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
3588#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
3589#define CAN_F2R1_FB3_Pos (3U)
3590#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
3591#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
3592#define CAN_F2R1_FB4_Pos (4U)
3593#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
3594#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
3595#define CAN_F2R1_FB5_Pos (5U)
3596#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
3597#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
3598#define CAN_F2R1_FB6_Pos (6U)
3599#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
3600#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
3601#define CAN_F2R1_FB7_Pos (7U)
3602#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
3603#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
3604#define CAN_F2R1_FB8_Pos (8U)
3605#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
3606#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
3607#define CAN_F2R1_FB9_Pos (9U)
3608#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
3609#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
3610#define CAN_F2R1_FB10_Pos (10U)
3611#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
3612#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
3613#define CAN_F2R1_FB11_Pos (11U)
3614#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
3615#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
3616#define CAN_F2R1_FB12_Pos (12U)
3617#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
3618#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
3619#define CAN_F2R1_FB13_Pos (13U)
3620#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
3621#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
3622#define CAN_F2R1_FB14_Pos (14U)
3623#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
3624#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
3625#define CAN_F2R1_FB15_Pos (15U)
3626#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
3627#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
3628#define CAN_F2R1_FB16_Pos (16U)
3629#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
3630#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
3631#define CAN_F2R1_FB17_Pos (17U)
3632#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
3633#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
3634#define CAN_F2R1_FB18_Pos (18U)
3635#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
3636#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
3637#define CAN_F2R1_FB19_Pos (19U)
3638#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
3639#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
3640#define CAN_F2R1_FB20_Pos (20U)
3641#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
3642#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
3643#define CAN_F2R1_FB21_Pos (21U)
3644#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
3645#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
3646#define CAN_F2R1_FB22_Pos (22U)
3647#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
3648#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
3649#define CAN_F2R1_FB23_Pos (23U)
3650#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
3651#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
3652#define CAN_F2R1_FB24_Pos (24U)
3653#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
3654#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
3655#define CAN_F2R1_FB25_Pos (25U)
3656#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
3657#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
3658#define CAN_F2R1_FB26_Pos (26U)
3659#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
3660#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
3661#define CAN_F2R1_FB27_Pos (27U)
3662#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
3663#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
3664#define CAN_F2R1_FB28_Pos (28U)
3665#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
3666#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
3667#define CAN_F2R1_FB29_Pos (29U)
3668#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
3669#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
3670#define CAN_F2R1_FB30_Pos (30U)
3671#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
3672#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
3673#define CAN_F2R1_FB31_Pos (31U)
3674#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
3675#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
3676
3677/******************* Bit definition for CAN_F3R1 register *******************/
3678#define CAN_F3R1_FB0_Pos (0U)
3679#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
3680#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3681#define CAN_F3R1_FB1_Pos (1U)
3682#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3683#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3684#define CAN_F3R1_FB2_Pos (2U)
3685#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3686#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3687#define CAN_F3R1_FB3_Pos (3U)
3688#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3689#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3690#define CAN_F3R1_FB4_Pos (4U)
3691#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3692#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3693#define CAN_F3R1_FB5_Pos (5U)
3694#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3695#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3696#define CAN_F3R1_FB6_Pos (6U)
3697#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3698#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3699#define CAN_F3R1_FB7_Pos (7U)
3700#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3701#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3702#define CAN_F3R1_FB8_Pos (8U)
3703#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3704#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3705#define CAN_F3R1_FB9_Pos (9U)
3706#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3707#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3708#define CAN_F3R1_FB10_Pos (10U)
3709#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3710#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3711#define CAN_F3R1_FB11_Pos (11U)
3712#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3713#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3714#define CAN_F3R1_FB12_Pos (12U)
3715#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3716#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3717#define CAN_F3R1_FB13_Pos (13U)
3718#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3719#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3720#define CAN_F3R1_FB14_Pos (14U)
3721#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3722#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3723#define CAN_F3R1_FB15_Pos (15U)
3724#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3725#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3726#define CAN_F3R1_FB16_Pos (16U)
3727#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3728#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3729#define CAN_F3R1_FB17_Pos (17U)
3730#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3731#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3732#define CAN_F3R1_FB18_Pos (18U)
3733#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3734#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3735#define CAN_F3R1_FB19_Pos (19U)
3736#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3737#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3738#define CAN_F3R1_FB20_Pos (20U)
3739#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3740#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3741#define CAN_F3R1_FB21_Pos (21U)
3742#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3743#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3744#define CAN_F3R1_FB22_Pos (22U)
3745#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3746#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3747#define CAN_F3R1_FB23_Pos (23U)
3748#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3749#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3750#define CAN_F3R1_FB24_Pos (24U)
3751#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3752#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3753#define CAN_F3R1_FB25_Pos (25U)
3754#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3755#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3756#define CAN_F3R1_FB26_Pos (26U)
3757#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3758#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3759#define CAN_F3R1_FB27_Pos (27U)
3760#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3761#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3762#define CAN_F3R1_FB28_Pos (28U)
3763#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3764#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3765#define CAN_F3R1_FB29_Pos (29U)
3766#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3767#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3768#define CAN_F3R1_FB30_Pos (30U)
3769#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3770#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3771#define CAN_F3R1_FB31_Pos (31U)
3772#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3773#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3774
3775/******************* Bit definition for CAN_F4R1 register *******************/
3776#define CAN_F4R1_FB0_Pos (0U)
3777#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3778#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3779#define CAN_F4R1_FB1_Pos (1U)
3780#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3781#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3782#define CAN_F4R1_FB2_Pos (2U)
3783#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3784#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3785#define CAN_F4R1_FB3_Pos (3U)
3786#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3787#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3788#define CAN_F4R1_FB4_Pos (4U)
3789#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3790#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3791#define CAN_F4R1_FB5_Pos (5U)
3792#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3793#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3794#define CAN_F4R1_FB6_Pos (6U)
3795#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3796#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3797#define CAN_F4R1_FB7_Pos (7U)
3798#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3799#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3800#define CAN_F4R1_FB8_Pos (8U)
3801#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3802#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3803#define CAN_F4R1_FB9_Pos (9U)
3804#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3805#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3806#define CAN_F4R1_FB10_Pos (10U)
3807#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3808#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3809#define CAN_F4R1_FB11_Pos (11U)
3810#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3811#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3812#define CAN_F4R1_FB12_Pos (12U)
3813#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3814#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3815#define CAN_F4R1_FB13_Pos (13U)
3816#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3817#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3818#define CAN_F4R1_FB14_Pos (14U)
3819#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3820#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3821#define CAN_F4R1_FB15_Pos (15U)
3822#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3823#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3824#define CAN_F4R1_FB16_Pos (16U)
3825#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3826#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3827#define CAN_F4R1_FB17_Pos (17U)
3828#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3829#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3830#define CAN_F4R1_FB18_Pos (18U)
3831#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3832#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3833#define CAN_F4R1_FB19_Pos (19U)
3834#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3835#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3836#define CAN_F4R1_FB20_Pos (20U)
3837#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3838#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3839#define CAN_F4R1_FB21_Pos (21U)
3840#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3841#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3842#define CAN_F4R1_FB22_Pos (22U)
3843#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3844#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3845#define CAN_F4R1_FB23_Pos (23U)
3846#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3847#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3848#define CAN_F4R1_FB24_Pos (24U)
3849#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3850#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3851#define CAN_F4R1_FB25_Pos (25U)
3852#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3853#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3854#define CAN_F4R1_FB26_Pos (26U)
3855#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3856#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3857#define CAN_F4R1_FB27_Pos (27U)
3858#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3859#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3860#define CAN_F4R1_FB28_Pos (28U)
3861#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3862#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3863#define CAN_F4R1_FB29_Pos (29U)
3864#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3865#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3866#define CAN_F4R1_FB30_Pos (30U)
3867#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3868#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3869#define CAN_F4R1_FB31_Pos (31U)
3870#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3871#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3872
3873/******************* Bit definition for CAN_F5R1 register *******************/
3874#define CAN_F5R1_FB0_Pos (0U)
3875#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3876#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3877#define CAN_F5R1_FB1_Pos (1U)
3878#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3879#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3880#define CAN_F5R1_FB2_Pos (2U)
3881#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3882#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3883#define CAN_F5R1_FB3_Pos (3U)
3884#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3885#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3886#define CAN_F5R1_FB4_Pos (4U)
3887#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3888#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3889#define CAN_F5R1_FB5_Pos (5U)
3890#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3891#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3892#define CAN_F5R1_FB6_Pos (6U)
3893#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3894#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3895#define CAN_F5R1_FB7_Pos (7U)
3896#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3897#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3898#define CAN_F5R1_FB8_Pos (8U)
3899#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3900#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3901#define CAN_F5R1_FB9_Pos (9U)
3902#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3903#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3904#define CAN_F5R1_FB10_Pos (10U)
3905#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3906#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3907#define CAN_F5R1_FB11_Pos (11U)
3908#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3909#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3910#define CAN_F5R1_FB12_Pos (12U)
3911#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3912#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3913#define CAN_F5R1_FB13_Pos (13U)
3914#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3915#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3916#define CAN_F5R1_FB14_Pos (14U)
3917#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3918#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3919#define CAN_F5R1_FB15_Pos (15U)
3920#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3921#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3922#define CAN_F5R1_FB16_Pos (16U)
3923#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3924#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3925#define CAN_F5R1_FB17_Pos (17U)
3926#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3927#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3928#define CAN_F5R1_FB18_Pos (18U)
3929#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3930#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3931#define CAN_F5R1_FB19_Pos (19U)
3932#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3933#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3934#define CAN_F5R1_FB20_Pos (20U)
3935#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3936#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3937#define CAN_F5R1_FB21_Pos (21U)
3938#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3939#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3940#define CAN_F5R1_FB22_Pos (22U)
3941#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3942#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3943#define CAN_F5R1_FB23_Pos (23U)
3944#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3945#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3946#define CAN_F5R1_FB24_Pos (24U)
3947#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3948#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3949#define CAN_F5R1_FB25_Pos (25U)
3950#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3951#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3952#define CAN_F5R1_FB26_Pos (26U)
3953#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3954#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3955#define CAN_F5R1_FB27_Pos (27U)
3956#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3957#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3958#define CAN_F5R1_FB28_Pos (28U)
3959#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3960#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3961#define CAN_F5R1_FB29_Pos (29U)
3962#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3963#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3964#define CAN_F5R1_FB30_Pos (30U)
3965#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3966#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3967#define CAN_F5R1_FB31_Pos (31U)
3968#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3969#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3970
3971/******************* Bit definition for CAN_F6R1 register *******************/
3972#define CAN_F6R1_FB0_Pos (0U)
3973#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3974#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3975#define CAN_F6R1_FB1_Pos (1U)
3976#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3977#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3978#define CAN_F6R1_FB2_Pos (2U)
3979#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3980#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3981#define CAN_F6R1_FB3_Pos (3U)
3982#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3983#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3984#define CAN_F6R1_FB4_Pos (4U)
3985#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3986#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3987#define CAN_F6R1_FB5_Pos (5U)
3988#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3989#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3990#define CAN_F6R1_FB6_Pos (6U)
3991#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3992#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3993#define CAN_F6R1_FB7_Pos (7U)
3994#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3995#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3996#define CAN_F6R1_FB8_Pos (8U)
3997#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3998#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3999#define CAN_F6R1_FB9_Pos (9U)
4000#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
4001#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
4002#define CAN_F6R1_FB10_Pos (10U)
4003#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
4004#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
4005#define CAN_F6R1_FB11_Pos (11U)
4006#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
4007#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
4008#define CAN_F6R1_FB12_Pos (12U)
4009#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
4010#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
4011#define CAN_F6R1_FB13_Pos (13U)
4012#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
4013#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
4014#define CAN_F6R1_FB14_Pos (14U)
4015#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
4016#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
4017#define CAN_F6R1_FB15_Pos (15U)
4018#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
4019#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
4020#define CAN_F6R1_FB16_Pos (16U)
4021#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
4022#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
4023#define CAN_F6R1_FB17_Pos (17U)
4024#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
4025#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
4026#define CAN_F6R1_FB18_Pos (18U)
4027#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
4028#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
4029#define CAN_F6R1_FB19_Pos (19U)
4030#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
4031#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
4032#define CAN_F6R1_FB20_Pos (20U)
4033#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
4034#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
4035#define CAN_F6R1_FB21_Pos (21U)
4036#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
4037#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
4038#define CAN_F6R1_FB22_Pos (22U)
4039#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
4040#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
4041#define CAN_F6R1_FB23_Pos (23U)
4042#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
4043#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
4044#define CAN_F6R1_FB24_Pos (24U)
4045#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
4046#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
4047#define CAN_F6R1_FB25_Pos (25U)
4048#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
4049#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
4050#define CAN_F6R1_FB26_Pos (26U)
4051#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
4052#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
4053#define CAN_F6R1_FB27_Pos (27U)
4054#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
4055#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
4056#define CAN_F6R1_FB28_Pos (28U)
4057#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
4058#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
4059#define CAN_F6R1_FB29_Pos (29U)
4060#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
4061#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
4062#define CAN_F6R1_FB30_Pos (30U)
4063#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
4064#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
4065#define CAN_F6R1_FB31_Pos (31U)
4066#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
4067#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
4068
4069/******************* Bit definition for CAN_F7R1 register *******************/
4070#define CAN_F7R1_FB0_Pos (0U)
4071#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
4072#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
4073#define CAN_F7R1_FB1_Pos (1U)
4074#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
4075#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
4076#define CAN_F7R1_FB2_Pos (2U)
4077#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
4078#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
4079#define CAN_F7R1_FB3_Pos (3U)
4080#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
4081#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
4082#define CAN_F7R1_FB4_Pos (4U)
4083#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
4084#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
4085#define CAN_F7R1_FB5_Pos (5U)
4086#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
4087#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
4088#define CAN_F7R1_FB6_Pos (6U)
4089#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
4090#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
4091#define CAN_F7R1_FB7_Pos (7U)
4092#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
4093#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
4094#define CAN_F7R1_FB8_Pos (8U)
4095#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
4096#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
4097#define CAN_F7R1_FB9_Pos (9U)
4098#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
4099#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
4100#define CAN_F7R1_FB10_Pos (10U)
4101#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
4102#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
4103#define CAN_F7R1_FB11_Pos (11U)
4104#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
4105#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
4106#define CAN_F7R1_FB12_Pos (12U)
4107#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
4108#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
4109#define CAN_F7R1_FB13_Pos (13U)
4110#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
4111#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
4112#define CAN_F7R1_FB14_Pos (14U)
4113#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
4114#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
4115#define CAN_F7R1_FB15_Pos (15U)
4116#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
4117#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
4118#define CAN_F7R1_FB16_Pos (16U)
4119#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
4120#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
4121#define CAN_F7R1_FB17_Pos (17U)
4122#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
4123#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
4124#define CAN_F7R1_FB18_Pos (18U)
4125#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
4126#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
4127#define CAN_F7R1_FB19_Pos (19U)
4128#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
4129#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
4130#define CAN_F7R1_FB20_Pos (20U)
4131#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
4132#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
4133#define CAN_F7R1_FB21_Pos (21U)
4134#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
4135#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
4136#define CAN_F7R1_FB22_Pos (22U)
4137#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
4138#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
4139#define CAN_F7R1_FB23_Pos (23U)
4140#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
4141#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
4142#define CAN_F7R1_FB24_Pos (24U)
4143#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
4144#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
4145#define CAN_F7R1_FB25_Pos (25U)
4146#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
4147#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
4148#define CAN_F7R1_FB26_Pos (26U)
4149#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
4150#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
4151#define CAN_F7R1_FB27_Pos (27U)
4152#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
4153#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
4154#define CAN_F7R1_FB28_Pos (28U)
4155#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
4156#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
4157#define CAN_F7R1_FB29_Pos (29U)
4158#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
4159#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
4160#define CAN_F7R1_FB30_Pos (30U)
4161#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
4162#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
4163#define CAN_F7R1_FB31_Pos (31U)
4164#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
4165#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
4166
4167/******************* Bit definition for CAN_F8R1 register *******************/
4168#define CAN_F8R1_FB0_Pos (0U)
4169#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
4170#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
4171#define CAN_F8R1_FB1_Pos (1U)
4172#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
4173#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
4174#define CAN_F8R1_FB2_Pos (2U)
4175#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
4176#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
4177#define CAN_F8R1_FB3_Pos (3U)
4178#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
4179#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
4180#define CAN_F8R1_FB4_Pos (4U)
4181#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
4182#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
4183#define CAN_F8R1_FB5_Pos (5U)
4184#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
4185#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
4186#define CAN_F8R1_FB6_Pos (6U)
4187#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
4188#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
4189#define CAN_F8R1_FB7_Pos (7U)
4190#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
4191#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
4192#define CAN_F8R1_FB8_Pos (8U)
4193#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
4194#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
4195#define CAN_F8R1_FB9_Pos (9U)
4196#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
4197#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
4198#define CAN_F8R1_FB10_Pos (10U)
4199#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
4200#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
4201#define CAN_F8R1_FB11_Pos (11U)
4202#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
4203#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
4204#define CAN_F8R1_FB12_Pos (12U)
4205#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
4206#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
4207#define CAN_F8R1_FB13_Pos (13U)
4208#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
4209#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
4210#define CAN_F8R1_FB14_Pos (14U)
4211#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
4212#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
4213#define CAN_F8R1_FB15_Pos (15U)
4214#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
4215#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
4216#define CAN_F8R1_FB16_Pos (16U)
4217#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
4218#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
4219#define CAN_F8R1_FB17_Pos (17U)
4220#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
4221#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
4222#define CAN_F8R1_FB18_Pos (18U)
4223#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
4224#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
4225#define CAN_F8R1_FB19_Pos (19U)
4226#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
4227#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
4228#define CAN_F8R1_FB20_Pos (20U)
4229#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
4230#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
4231#define CAN_F8R1_FB21_Pos (21U)
4232#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
4233#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
4234#define CAN_F8R1_FB22_Pos (22U)
4235#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
4236#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
4237#define CAN_F8R1_FB23_Pos (23U)
4238#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
4239#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
4240#define CAN_F8R1_FB24_Pos (24U)
4241#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
4242#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
4243#define CAN_F8R1_FB25_Pos (25U)
4244#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
4245#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
4246#define CAN_F8R1_FB26_Pos (26U)
4247#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
4248#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
4249#define CAN_F8R1_FB27_Pos (27U)
4250#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
4251#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
4252#define CAN_F8R1_FB28_Pos (28U)
4253#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
4254#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
4255#define CAN_F8R1_FB29_Pos (29U)
4256#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
4257#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
4258#define CAN_F8R1_FB30_Pos (30U)
4259#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
4260#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
4261#define CAN_F8R1_FB31_Pos (31U)
4262#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
4263#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
4264
4265/******************* Bit definition for CAN_F9R1 register *******************/
4266#define CAN_F9R1_FB0_Pos (0U)
4267#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
4268#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
4269#define CAN_F9R1_FB1_Pos (1U)
4270#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
4271#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
4272#define CAN_F9R1_FB2_Pos (2U)
4273#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
4274#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
4275#define CAN_F9R1_FB3_Pos (3U)
4276#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
4277#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
4278#define CAN_F9R1_FB4_Pos (4U)
4279#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
4280#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
4281#define CAN_F9R1_FB5_Pos (5U)
4282#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
4283#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
4284#define CAN_F9R1_FB6_Pos (6U)
4285#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
4286#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
4287#define CAN_F9R1_FB7_Pos (7U)
4288#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
4289#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
4290#define CAN_F9R1_FB8_Pos (8U)
4291#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
4292#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
4293#define CAN_F9R1_FB9_Pos (9U)
4294#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
4295#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
4296#define CAN_F9R1_FB10_Pos (10U)
4297#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
4298#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
4299#define CAN_F9R1_FB11_Pos (11U)
4300#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
4301#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
4302#define CAN_F9R1_FB12_Pos (12U)
4303#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
4304#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
4305#define CAN_F9R1_FB13_Pos (13U)
4306#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
4307#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
4308#define CAN_F9R1_FB14_Pos (14U)
4309#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
4310#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
4311#define CAN_F9R1_FB15_Pos (15U)
4312#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
4313#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
4314#define CAN_F9R1_FB16_Pos (16U)
4315#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
4316#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
4317#define CAN_F9R1_FB17_Pos (17U)
4318#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
4319#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
4320#define CAN_F9R1_FB18_Pos (18U)
4321#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
4322#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
4323#define CAN_F9R1_FB19_Pos (19U)
4324#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
4325#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
4326#define CAN_F9R1_FB20_Pos (20U)
4327#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
4328#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
4329#define CAN_F9R1_FB21_Pos (21U)
4330#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
4331#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
4332#define CAN_F9R1_FB22_Pos (22U)
4333#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
4334#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
4335#define CAN_F9R1_FB23_Pos (23U)
4336#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
4337#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
4338#define CAN_F9R1_FB24_Pos (24U)
4339#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
4340#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
4341#define CAN_F9R1_FB25_Pos (25U)
4342#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
4343#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
4344#define CAN_F9R1_FB26_Pos (26U)
4345#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
4346#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
4347#define CAN_F9R1_FB27_Pos (27U)
4348#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
4349#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
4350#define CAN_F9R1_FB28_Pos (28U)
4351#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
4352#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
4353#define CAN_F9R1_FB29_Pos (29U)
4354#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
4355#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
4356#define CAN_F9R1_FB30_Pos (30U)
4357#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
4358#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
4359#define CAN_F9R1_FB31_Pos (31U)
4360#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
4361#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
4362
4363/******************* Bit definition for CAN_F10R1 register ******************/
4364#define CAN_F10R1_FB0_Pos (0U)
4365#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
4366#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
4367#define CAN_F10R1_FB1_Pos (1U)
4368#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
4369#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
4370#define CAN_F10R1_FB2_Pos (2U)
4371#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
4372#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
4373#define CAN_F10R1_FB3_Pos (3U)
4374#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
4375#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
4376#define CAN_F10R1_FB4_Pos (4U)
4377#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
4378#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
4379#define CAN_F10R1_FB5_Pos (5U)
4380#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
4381#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
4382#define CAN_F10R1_FB6_Pos (6U)
4383#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
4384#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
4385#define CAN_F10R1_FB7_Pos (7U)
4386#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
4387#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
4388#define CAN_F10R1_FB8_Pos (8U)
4389#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
4390#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
4391#define CAN_F10R1_FB9_Pos (9U)
4392#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
4393#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
4394#define CAN_F10R1_FB10_Pos (10U)
4395#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
4396#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
4397#define CAN_F10R1_FB11_Pos (11U)
4398#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
4399#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
4400#define CAN_F10R1_FB12_Pos (12U)
4401#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
4402#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
4403#define CAN_F10R1_FB13_Pos (13U)
4404#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
4405#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
4406#define CAN_F10R1_FB14_Pos (14U)
4407#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
4408#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
4409#define CAN_F10R1_FB15_Pos (15U)
4410#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
4411#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
4412#define CAN_F10R1_FB16_Pos (16U)
4413#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
4414#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
4415#define CAN_F10R1_FB17_Pos (17U)
4416#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
4417#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
4418#define CAN_F10R1_FB18_Pos (18U)
4419#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
4420#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
4421#define CAN_F10R1_FB19_Pos (19U)
4422#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
4423#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
4424#define CAN_F10R1_FB20_Pos (20U)
4425#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
4426#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
4427#define CAN_F10R1_FB21_Pos (21U)
4428#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
4429#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
4430#define CAN_F10R1_FB22_Pos (22U)
4431#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
4432#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
4433#define CAN_F10R1_FB23_Pos (23U)
4434#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
4435#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
4436#define CAN_F10R1_FB24_Pos (24U)
4437#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
4438#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
4439#define CAN_F10R1_FB25_Pos (25U)
4440#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
4441#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
4442#define CAN_F10R1_FB26_Pos (26U)
4443#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
4444#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
4445#define CAN_F10R1_FB27_Pos (27U)
4446#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
4447#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
4448#define CAN_F10R1_FB28_Pos (28U)
4449#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
4450#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
4451#define CAN_F10R1_FB29_Pos (29U)
4452#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
4453#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
4454#define CAN_F10R1_FB30_Pos (30U)
4455#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
4456#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
4457#define CAN_F10R1_FB31_Pos (31U)
4458#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
4459#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
4460
4461/******************* Bit definition for CAN_F11R1 register ******************/
4462#define CAN_F11R1_FB0_Pos (0U)
4463#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
4464#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
4465#define CAN_F11R1_FB1_Pos (1U)
4466#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
4467#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
4468#define CAN_F11R1_FB2_Pos (2U)
4469#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
4470#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
4471#define CAN_F11R1_FB3_Pos (3U)
4472#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
4473#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
4474#define CAN_F11R1_FB4_Pos (4U)
4475#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
4476#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
4477#define CAN_F11R1_FB5_Pos (5U)
4478#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
4479#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
4480#define CAN_F11R1_FB6_Pos (6U)
4481#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
4482#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
4483#define CAN_F11R1_FB7_Pos (7U)
4484#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
4485#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
4486#define CAN_F11R1_FB8_Pos (8U)
4487#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
4488#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
4489#define CAN_F11R1_FB9_Pos (9U)
4490#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
4491#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
4492#define CAN_F11R1_FB10_Pos (10U)
4493#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
4494#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
4495#define CAN_F11R1_FB11_Pos (11U)
4496#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
4497#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
4498#define CAN_F11R1_FB12_Pos (12U)
4499#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
4500#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
4501#define CAN_F11R1_FB13_Pos (13U)
4502#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
4503#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
4504#define CAN_F11R1_FB14_Pos (14U)
4505#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
4506#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
4507#define CAN_F11R1_FB15_Pos (15U)
4508#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
4509#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
4510#define CAN_F11R1_FB16_Pos (16U)
4511#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
4512#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
4513#define CAN_F11R1_FB17_Pos (17U)
4514#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
4515#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
4516#define CAN_F11R1_FB18_Pos (18U)
4517#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
4518#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
4519#define CAN_F11R1_FB19_Pos (19U)
4520#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
4521#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
4522#define CAN_F11R1_FB20_Pos (20U)
4523#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
4524#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
4525#define CAN_F11R1_FB21_Pos (21U)
4526#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
4527#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
4528#define CAN_F11R1_FB22_Pos (22U)
4529#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
4530#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
4531#define CAN_F11R1_FB23_Pos (23U)
4532#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
4533#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
4534#define CAN_F11R1_FB24_Pos (24U)
4535#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
4536#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
4537#define CAN_F11R1_FB25_Pos (25U)
4538#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
4539#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
4540#define CAN_F11R1_FB26_Pos (26U)
4541#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
4542#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
4543#define CAN_F11R1_FB27_Pos (27U)
4544#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
4545#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
4546#define CAN_F11R1_FB28_Pos (28U)
4547#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
4548#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
4549#define CAN_F11R1_FB29_Pos (29U)
4550#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
4551#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
4552#define CAN_F11R1_FB30_Pos (30U)
4553#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
4554#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
4555#define CAN_F11R1_FB31_Pos (31U)
4556#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
4557#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
4558
4559/******************* Bit definition for CAN_F12R1 register ******************/
4560#define CAN_F12R1_FB0_Pos (0U)
4561#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
4562#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
4563#define CAN_F12R1_FB1_Pos (1U)
4564#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
4565#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
4566#define CAN_F12R1_FB2_Pos (2U)
4567#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
4568#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
4569#define CAN_F12R1_FB3_Pos (3U)
4570#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
4571#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
4572#define CAN_F12R1_FB4_Pos (4U)
4573#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
4574#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
4575#define CAN_F12R1_FB5_Pos (5U)
4576#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
4577#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
4578#define CAN_F12R1_FB6_Pos (6U)
4579#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
4580#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
4581#define CAN_F12R1_FB7_Pos (7U)
4582#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
4583#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
4584#define CAN_F12R1_FB8_Pos (8U)
4585#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
4586#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
4587#define CAN_F12R1_FB9_Pos (9U)
4588#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
4589#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
4590#define CAN_F12R1_FB10_Pos (10U)
4591#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
4592#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
4593#define CAN_F12R1_FB11_Pos (11U)
4594#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
4595#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
4596#define CAN_F12R1_FB12_Pos (12U)
4597#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
4598#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
4599#define CAN_F12R1_FB13_Pos (13U)
4600#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
4601#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
4602#define CAN_F12R1_FB14_Pos (14U)
4603#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
4604#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
4605#define CAN_F12R1_FB15_Pos (15U)
4606#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
4607#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
4608#define CAN_F12R1_FB16_Pos (16U)
4609#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
4610#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
4611#define CAN_F12R1_FB17_Pos (17U)
4612#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
4613#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
4614#define CAN_F12R1_FB18_Pos (18U)
4615#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
4616#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
4617#define CAN_F12R1_FB19_Pos (19U)
4618#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
4619#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
4620#define CAN_F12R1_FB20_Pos (20U)
4621#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
4622#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
4623#define CAN_F12R1_FB21_Pos (21U)
4624#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
4625#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
4626#define CAN_F12R1_FB22_Pos (22U)
4627#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
4628#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
4629#define CAN_F12R1_FB23_Pos (23U)
4630#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
4631#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
4632#define CAN_F12R1_FB24_Pos (24U)
4633#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
4634#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
4635#define CAN_F12R1_FB25_Pos (25U)
4636#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
4637#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
4638#define CAN_F12R1_FB26_Pos (26U)
4639#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
4640#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
4641#define CAN_F12R1_FB27_Pos (27U)
4642#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
4643#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
4644#define CAN_F12R1_FB28_Pos (28U)
4645#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
4646#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
4647#define CAN_F12R1_FB29_Pos (29U)
4648#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
4649#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
4650#define CAN_F12R1_FB30_Pos (30U)
4651#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
4652#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
4653#define CAN_F12R1_FB31_Pos (31U)
4654#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
4655#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
4656
4657/******************* Bit definition for CAN_F13R1 register ******************/
4658#define CAN_F13R1_FB0_Pos (0U)
4659#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
4660#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
4661#define CAN_F13R1_FB1_Pos (1U)
4662#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
4663#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
4664#define CAN_F13R1_FB2_Pos (2U)
4665#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
4666#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
4667#define CAN_F13R1_FB3_Pos (3U)
4668#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
4669#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
4670#define CAN_F13R1_FB4_Pos (4U)
4671#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
4672#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
4673#define CAN_F13R1_FB5_Pos (5U)
4674#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
4675#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
4676#define CAN_F13R1_FB6_Pos (6U)
4677#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
4678#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
4679#define CAN_F13R1_FB7_Pos (7U)
4680#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
4681#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
4682#define CAN_F13R1_FB8_Pos (8U)
4683#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
4684#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
4685#define CAN_F13R1_FB9_Pos (9U)
4686#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
4687#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
4688#define CAN_F13R1_FB10_Pos (10U)
4689#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
4690#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
4691#define CAN_F13R1_FB11_Pos (11U)
4692#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
4693#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
4694#define CAN_F13R1_FB12_Pos (12U)
4695#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4696#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4697#define CAN_F13R1_FB13_Pos (13U)
4698#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4699#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4700#define CAN_F13R1_FB14_Pos (14U)
4701#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4702#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4703#define CAN_F13R1_FB15_Pos (15U)
4704#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4705#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4706#define CAN_F13R1_FB16_Pos (16U)
4707#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4708#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4709#define CAN_F13R1_FB17_Pos (17U)
4710#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4711#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4712#define CAN_F13R1_FB18_Pos (18U)
4713#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4714#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4715#define CAN_F13R1_FB19_Pos (19U)
4716#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4717#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4718#define CAN_F13R1_FB20_Pos (20U)
4719#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4720#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4721#define CAN_F13R1_FB21_Pos (21U)
4722#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4723#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4724#define CAN_F13R1_FB22_Pos (22U)
4725#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4726#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4727#define CAN_F13R1_FB23_Pos (23U)
4728#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4729#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4730#define CAN_F13R1_FB24_Pos (24U)
4731#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4732#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4733#define CAN_F13R1_FB25_Pos (25U)
4734#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4735#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4736#define CAN_F13R1_FB26_Pos (26U)
4737#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4738#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4739#define CAN_F13R1_FB27_Pos (27U)
4740#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4741#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4742#define CAN_F13R1_FB28_Pos (28U)
4743#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4744#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4745#define CAN_F13R1_FB29_Pos (29U)
4746#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4747#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4748#define CAN_F13R1_FB30_Pos (30U)
4749#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4750#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4751#define CAN_F13R1_FB31_Pos (31U)
4752#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4753#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4754
4755/******************* Bit definition for CAN_F0R2 register *******************/
4756#define CAN_F0R2_FB0_Pos (0U)
4757#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4758#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4759#define CAN_F0R2_FB1_Pos (1U)
4760#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4761#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4762#define CAN_F0R2_FB2_Pos (2U)
4763#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4764#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4765#define CAN_F0R2_FB3_Pos (3U)
4766#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4767#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4768#define CAN_F0R2_FB4_Pos (4U)
4769#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4770#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4771#define CAN_F0R2_FB5_Pos (5U)
4772#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4773#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4774#define CAN_F0R2_FB6_Pos (6U)
4775#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4776#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4777#define CAN_F0R2_FB7_Pos (7U)
4778#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4779#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4780#define CAN_F0R2_FB8_Pos (8U)
4781#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4782#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4783#define CAN_F0R2_FB9_Pos (9U)
4784#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4785#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4786#define CAN_F0R2_FB10_Pos (10U)
4787#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4788#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4789#define CAN_F0R2_FB11_Pos (11U)
4790#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4791#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4792#define CAN_F0R2_FB12_Pos (12U)
4793#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4794#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4795#define CAN_F0R2_FB13_Pos (13U)
4796#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4797#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4798#define CAN_F0R2_FB14_Pos (14U)
4799#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4800#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4801#define CAN_F0R2_FB15_Pos (15U)
4802#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4803#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4804#define CAN_F0R2_FB16_Pos (16U)
4805#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4806#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4807#define CAN_F0R2_FB17_Pos (17U)
4808#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4809#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4810#define CAN_F0R2_FB18_Pos (18U)
4811#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4812#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4813#define CAN_F0R2_FB19_Pos (19U)
4814#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4815#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4816#define CAN_F0R2_FB20_Pos (20U)
4817#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4818#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4819#define CAN_F0R2_FB21_Pos (21U)
4820#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4821#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4822#define CAN_F0R2_FB22_Pos (22U)
4823#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4824#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4825#define CAN_F0R2_FB23_Pos (23U)
4826#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4827#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4828#define CAN_F0R2_FB24_Pos (24U)
4829#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4830#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4831#define CAN_F0R2_FB25_Pos (25U)
4832#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4833#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4834#define CAN_F0R2_FB26_Pos (26U)
4835#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4836#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4837#define CAN_F0R2_FB27_Pos (27U)
4838#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4839#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4840#define CAN_F0R2_FB28_Pos (28U)
4841#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4842#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4843#define CAN_F0R2_FB29_Pos (29U)
4844#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4845#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4846#define CAN_F0R2_FB30_Pos (30U)
4847#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4848#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4849#define CAN_F0R2_FB31_Pos (31U)
4850#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4851#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4852
4853/******************* Bit definition for CAN_F1R2 register *******************/
4854#define CAN_F1R2_FB0_Pos (0U)
4855#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4856#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4857#define CAN_F1R2_FB1_Pos (1U)
4858#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4859#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4860#define CAN_F1R2_FB2_Pos (2U)
4861#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4862#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4863#define CAN_F1R2_FB3_Pos (3U)
4864#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4865#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4866#define CAN_F1R2_FB4_Pos (4U)
4867#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4868#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4869#define CAN_F1R2_FB5_Pos (5U)
4870#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4871#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4872#define CAN_F1R2_FB6_Pos (6U)
4873#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4874#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4875#define CAN_F1R2_FB7_Pos (7U)
4876#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4877#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4878#define CAN_F1R2_FB8_Pos (8U)
4879#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4880#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4881#define CAN_F1R2_FB9_Pos (9U)
4882#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4883#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4884#define CAN_F1R2_FB10_Pos (10U)
4885#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4886#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4887#define CAN_F1R2_FB11_Pos (11U)
4888#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4889#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4890#define CAN_F1R2_FB12_Pos (12U)
4891#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4892#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4893#define CAN_F1R2_FB13_Pos (13U)
4894#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4895#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4896#define CAN_F1R2_FB14_Pos (14U)
4897#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4898#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4899#define CAN_F1R2_FB15_Pos (15U)
4900#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4901#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4902#define CAN_F1R2_FB16_Pos (16U)
4903#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4904#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4905#define CAN_F1R2_FB17_Pos (17U)
4906#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4907#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4908#define CAN_F1R2_FB18_Pos (18U)
4909#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4910#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4911#define CAN_F1R2_FB19_Pos (19U)
4912#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4913#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4914#define CAN_F1R2_FB20_Pos (20U)
4915#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4916#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4917#define CAN_F1R2_FB21_Pos (21U)
4918#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4919#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4920#define CAN_F1R2_FB22_Pos (22U)
4921#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4922#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4923#define CAN_F1R2_FB23_Pos (23U)
4924#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4925#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4926#define CAN_F1R2_FB24_Pos (24U)
4927#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4928#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4929#define CAN_F1R2_FB25_Pos (25U)
4930#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4931#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4932#define CAN_F1R2_FB26_Pos (26U)
4933#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4934#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4935#define CAN_F1R2_FB27_Pos (27U)
4936#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4937#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4938#define CAN_F1R2_FB28_Pos (28U)
4939#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4940#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4941#define CAN_F1R2_FB29_Pos (29U)
4942#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4943#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4944#define CAN_F1R2_FB30_Pos (30U)
4945#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4946#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4947#define CAN_F1R2_FB31_Pos (31U)
4948#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4949#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4950
4951/******************* Bit definition for CAN_F2R2 register *******************/
4952#define CAN_F2R2_FB0_Pos (0U)
4953#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4954#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4955#define CAN_F2R2_FB1_Pos (1U)
4956#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4957#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4958#define CAN_F2R2_FB2_Pos (2U)
4959#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4960#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4961#define CAN_F2R2_FB3_Pos (3U)
4962#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4963#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4964#define CAN_F2R2_FB4_Pos (4U)
4965#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4966#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4967#define CAN_F2R2_FB5_Pos (5U)
4968#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4969#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4970#define CAN_F2R2_FB6_Pos (6U)
4971#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4972#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4973#define CAN_F2R2_FB7_Pos (7U)
4974#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4975#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4976#define CAN_F2R2_FB8_Pos (8U)
4977#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4978#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4979#define CAN_F2R2_FB9_Pos (9U)
4980#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4981#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4982#define CAN_F2R2_FB10_Pos (10U)
4983#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4984#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4985#define CAN_F2R2_FB11_Pos (11U)
4986#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4987#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4988#define CAN_F2R2_FB12_Pos (12U)
4989#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4990#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4991#define CAN_F2R2_FB13_Pos (13U)
4992#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4993#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4994#define CAN_F2R2_FB14_Pos (14U)
4995#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4996#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4997#define CAN_F2R2_FB15_Pos (15U)
4998#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4999#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
5000#define CAN_F2R2_FB16_Pos (16U)
5001#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
5002#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
5003#define CAN_F2R2_FB17_Pos (17U)
5004#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
5005#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
5006#define CAN_F2R2_FB18_Pos (18U)
5007#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
5008#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
5009#define CAN_F2R2_FB19_Pos (19U)
5010#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
5011#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
5012#define CAN_F2R2_FB20_Pos (20U)
5013#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
5014#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
5015#define CAN_F2R2_FB21_Pos (21U)
5016#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
5017#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
5018#define CAN_F2R2_FB22_Pos (22U)
5019#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
5020#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
5021#define CAN_F2R2_FB23_Pos (23U)
5022#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
5023#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
5024#define CAN_F2R2_FB24_Pos (24U)
5025#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
5026#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
5027#define CAN_F2R2_FB25_Pos (25U)
5028#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
5029#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
5030#define CAN_F2R2_FB26_Pos (26U)
5031#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
5032#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
5033#define CAN_F2R2_FB27_Pos (27U)
5034#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
5035#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
5036#define CAN_F2R2_FB28_Pos (28U)
5037#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
5038#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
5039#define CAN_F2R2_FB29_Pos (29U)
5040#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
5041#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
5042#define CAN_F2R2_FB30_Pos (30U)
5043#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
5044#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
5045#define CAN_F2R2_FB31_Pos (31U)
5046#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
5047#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
5048
5049/******************* Bit definition for CAN_F3R2 register *******************/
5050#define CAN_F3R2_FB0_Pos (0U)
5051#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
5052#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
5053#define CAN_F3R2_FB1_Pos (1U)
5054#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
5055#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
5056#define CAN_F3R2_FB2_Pos (2U)
5057#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
5058#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
5059#define CAN_F3R2_FB3_Pos (3U)
5060#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
5061#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
5062#define CAN_F3R2_FB4_Pos (4U)
5063#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
5064#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
5065#define CAN_F3R2_FB5_Pos (5U)
5066#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
5067#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
5068#define CAN_F3R2_FB6_Pos (6U)
5069#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
5070#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
5071#define CAN_F3R2_FB7_Pos (7U)
5072#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
5073#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
5074#define CAN_F3R2_FB8_Pos (8U)
5075#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
5076#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
5077#define CAN_F3R2_FB9_Pos (9U)
5078#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
5079#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
5080#define CAN_F3R2_FB10_Pos (10U)
5081#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
5082#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
5083#define CAN_F3R2_FB11_Pos (11U)
5084#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
5085#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
5086#define CAN_F3R2_FB12_Pos (12U)
5087#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
5088#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
5089#define CAN_F3R2_FB13_Pos (13U)
5090#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
5091#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
5092#define CAN_F3R2_FB14_Pos (14U)
5093#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
5094#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
5095#define CAN_F3R2_FB15_Pos (15U)
5096#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
5097#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
5098#define CAN_F3R2_FB16_Pos (16U)
5099#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
5100#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
5101#define CAN_F3R2_FB17_Pos (17U)
5102#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
5103#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
5104#define CAN_F3R2_FB18_Pos (18U)
5105#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
5106#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
5107#define CAN_F3R2_FB19_Pos (19U)
5108#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
5109#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
5110#define CAN_F3R2_FB20_Pos (20U)
5111#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
5112#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
5113#define CAN_F3R2_FB21_Pos (21U)
5114#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
5115#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
5116#define CAN_F3R2_FB22_Pos (22U)
5117#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
5118#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
5119#define CAN_F3R2_FB23_Pos (23U)
5120#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
5121#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
5122#define CAN_F3R2_FB24_Pos (24U)
5123#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
5124#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
5125#define CAN_F3R2_FB25_Pos (25U)
5126#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
5127#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
5128#define CAN_F3R2_FB26_Pos (26U)
5129#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
5130#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
5131#define CAN_F3R2_FB27_Pos (27U)
5132#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
5133#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
5134#define CAN_F3R2_FB28_Pos (28U)
5135#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
5136#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
5137#define CAN_F3R2_FB29_Pos (29U)
5138#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
5139#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
5140#define CAN_F3R2_FB30_Pos (30U)
5141#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
5142#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
5143#define CAN_F3R2_FB31_Pos (31U)
5144#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
5145#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
5146
5147/******************* Bit definition for CAN_F4R2 register *******************/
5148#define CAN_F4R2_FB0_Pos (0U)
5149#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
5150#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
5151#define CAN_F4R2_FB1_Pos (1U)
5152#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
5153#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
5154#define CAN_F4R2_FB2_Pos (2U)
5155#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
5156#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
5157#define CAN_F4R2_FB3_Pos (3U)
5158#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
5159#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
5160#define CAN_F4R2_FB4_Pos (4U)
5161#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
5162#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
5163#define CAN_F4R2_FB5_Pos (5U)
5164#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
5165#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
5166#define CAN_F4R2_FB6_Pos (6U)
5167#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
5168#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
5169#define CAN_F4R2_FB7_Pos (7U)
5170#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
5171#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
5172#define CAN_F4R2_FB8_Pos (8U)
5173#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
5174#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
5175#define CAN_F4R2_FB9_Pos (9U)
5176#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
5177#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
5178#define CAN_F4R2_FB10_Pos (10U)
5179#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
5180#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
5181#define CAN_F4R2_FB11_Pos (11U)
5182#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
5183#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
5184#define CAN_F4R2_FB12_Pos (12U)
5185#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
5186#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
5187#define CAN_F4R2_FB13_Pos (13U)
5188#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
5189#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
5190#define CAN_F4R2_FB14_Pos (14U)
5191#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
5192#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
5193#define CAN_F4R2_FB15_Pos (15U)
5194#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
5195#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
5196#define CAN_F4R2_FB16_Pos (16U)
5197#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
5198#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
5199#define CAN_F4R2_FB17_Pos (17U)
5200#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
5201#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
5202#define CAN_F4R2_FB18_Pos (18U)
5203#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
5204#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
5205#define CAN_F4R2_FB19_Pos (19U)
5206#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
5207#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
5208#define CAN_F4R2_FB20_Pos (20U)
5209#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
5210#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
5211#define CAN_F4R2_FB21_Pos (21U)
5212#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
5213#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
5214#define CAN_F4R2_FB22_Pos (22U)
5215#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
5216#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
5217#define CAN_F4R2_FB23_Pos (23U)
5218#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
5219#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
5220#define CAN_F4R2_FB24_Pos (24U)
5221#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
5222#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
5223#define CAN_F4R2_FB25_Pos (25U)
5224#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
5225#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
5226#define CAN_F4R2_FB26_Pos (26U)
5227#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
5228#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
5229#define CAN_F4R2_FB27_Pos (27U)
5230#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
5231#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
5232#define CAN_F4R2_FB28_Pos (28U)
5233#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
5234#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
5235#define CAN_F4R2_FB29_Pos (29U)
5236#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
5237#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
5238#define CAN_F4R2_FB30_Pos (30U)
5239#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
5240#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
5241#define CAN_F4R2_FB31_Pos (31U)
5242#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
5243#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
5244
5245/******************* Bit definition for CAN_F5R2 register *******************/
5246#define CAN_F5R2_FB0_Pos (0U)
5247#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
5248#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
5249#define CAN_F5R2_FB1_Pos (1U)
5250#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
5251#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
5252#define CAN_F5R2_FB2_Pos (2U)
5253#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
5254#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
5255#define CAN_F5R2_FB3_Pos (3U)
5256#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
5257#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
5258#define CAN_F5R2_FB4_Pos (4U)
5259#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
5260#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
5261#define CAN_F5R2_FB5_Pos (5U)
5262#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
5263#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
5264#define CAN_F5R2_FB6_Pos (6U)
5265#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
5266#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
5267#define CAN_F5R2_FB7_Pos (7U)
5268#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
5269#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
5270#define CAN_F5R2_FB8_Pos (8U)
5271#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
5272#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
5273#define CAN_F5R2_FB9_Pos (9U)
5274#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
5275#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
5276#define CAN_F5R2_FB10_Pos (10U)
5277#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
5278#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
5279#define CAN_F5R2_FB11_Pos (11U)
5280#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
5281#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
5282#define CAN_F5R2_FB12_Pos (12U)
5283#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
5284#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
5285#define CAN_F5R2_FB13_Pos (13U)
5286#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
5287#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
5288#define CAN_F5R2_FB14_Pos (14U)
5289#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
5290#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
5291#define CAN_F5R2_FB15_Pos (15U)
5292#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
5293#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
5294#define CAN_F5R2_FB16_Pos (16U)
5295#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
5296#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
5297#define CAN_F5R2_FB17_Pos (17U)
5298#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
5299#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
5300#define CAN_F5R2_FB18_Pos (18U)
5301#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
5302#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
5303#define CAN_F5R2_FB19_Pos (19U)
5304#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
5305#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
5306#define CAN_F5R2_FB20_Pos (20U)
5307#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
5308#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
5309#define CAN_F5R2_FB21_Pos (21U)
5310#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
5311#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
5312#define CAN_F5R2_FB22_Pos (22U)
5313#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
5314#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
5315#define CAN_F5R2_FB23_Pos (23U)
5316#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
5317#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
5318#define CAN_F5R2_FB24_Pos (24U)
5319#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
5320#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
5321#define CAN_F5R2_FB25_Pos (25U)
5322#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
5323#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
5324#define CAN_F5R2_FB26_Pos (26U)
5325#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
5326#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
5327#define CAN_F5R2_FB27_Pos (27U)
5328#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
5329#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
5330#define CAN_F5R2_FB28_Pos (28U)
5331#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
5332#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
5333#define CAN_F5R2_FB29_Pos (29U)
5334#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
5335#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
5336#define CAN_F5R2_FB30_Pos (30U)
5337#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
5338#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
5339#define CAN_F5R2_FB31_Pos (31U)
5340#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
5341#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
5342
5343/******************* Bit definition for CAN_F6R2 register *******************/
5344#define CAN_F6R2_FB0_Pos (0U)
5345#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
5346#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
5347#define CAN_F6R2_FB1_Pos (1U)
5348#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
5349#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
5350#define CAN_F6R2_FB2_Pos (2U)
5351#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
5352#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
5353#define CAN_F6R2_FB3_Pos (3U)
5354#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
5355#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
5356#define CAN_F6R2_FB4_Pos (4U)
5357#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
5358#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
5359#define CAN_F6R2_FB5_Pos (5U)
5360#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
5361#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
5362#define CAN_F6R2_FB6_Pos (6U)
5363#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
5364#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
5365#define CAN_F6R2_FB7_Pos (7U)
5366#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
5367#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
5368#define CAN_F6R2_FB8_Pos (8U)
5369#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
5370#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
5371#define CAN_F6R2_FB9_Pos (9U)
5372#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
5373#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
5374#define CAN_F6R2_FB10_Pos (10U)
5375#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
5376#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
5377#define CAN_F6R2_FB11_Pos (11U)
5378#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
5379#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
5380#define CAN_F6R2_FB12_Pos (12U)
5381#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
5382#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
5383#define CAN_F6R2_FB13_Pos (13U)
5384#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
5385#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
5386#define CAN_F6R2_FB14_Pos (14U)
5387#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
5388#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
5389#define CAN_F6R2_FB15_Pos (15U)
5390#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
5391#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
5392#define CAN_F6R2_FB16_Pos (16U)
5393#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
5394#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
5395#define CAN_F6R2_FB17_Pos (17U)
5396#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
5397#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
5398#define CAN_F6R2_FB18_Pos (18U)
5399#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
5400#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
5401#define CAN_F6R2_FB19_Pos (19U)
5402#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
5403#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
5404#define CAN_F6R2_FB20_Pos (20U)
5405#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
5406#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
5407#define CAN_F6R2_FB21_Pos (21U)
5408#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
5409#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
5410#define CAN_F6R2_FB22_Pos (22U)
5411#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
5412#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
5413#define CAN_F6R2_FB23_Pos (23U)
5414#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
5415#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
5416#define CAN_F6R2_FB24_Pos (24U)
5417#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
5418#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
5419#define CAN_F6R2_FB25_Pos (25U)
5420#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
5421#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
5422#define CAN_F6R2_FB26_Pos (26U)
5423#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
5424#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
5425#define CAN_F6R2_FB27_Pos (27U)
5426#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
5427#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
5428#define CAN_F6R2_FB28_Pos (28U)
5429#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
5430#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
5431#define CAN_F6R2_FB29_Pos (29U)
5432#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
5433#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
5434#define CAN_F6R2_FB30_Pos (30U)
5435#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
5436#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
5437#define CAN_F6R2_FB31_Pos (31U)
5438#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
5439#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
5440
5441/******************* Bit definition for CAN_F7R2 register *******************/
5442#define CAN_F7R2_FB0_Pos (0U)
5443#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
5444#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
5445#define CAN_F7R2_FB1_Pos (1U)
5446#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
5447#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
5448#define CAN_F7R2_FB2_Pos (2U)
5449#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
5450#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
5451#define CAN_F7R2_FB3_Pos (3U)
5452#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
5453#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
5454#define CAN_F7R2_FB4_Pos (4U)
5455#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
5456#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
5457#define CAN_F7R2_FB5_Pos (5U)
5458#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
5459#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
5460#define CAN_F7R2_FB6_Pos (6U)
5461#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
5462#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
5463#define CAN_F7R2_FB7_Pos (7U)
5464#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
5465#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
5466#define CAN_F7R2_FB8_Pos (8U)
5467#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
5468#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
5469#define CAN_F7R2_FB9_Pos (9U)
5470#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
5471#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
5472#define CAN_F7R2_FB10_Pos (10U)
5473#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
5474#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
5475#define CAN_F7R2_FB11_Pos (11U)
5476#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
5477#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
5478#define CAN_F7R2_FB12_Pos (12U)
5479#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
5480#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
5481#define CAN_F7R2_FB13_Pos (13U)
5482#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
5483#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
5484#define CAN_F7R2_FB14_Pos (14U)
5485#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
5486#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
5487#define CAN_F7R2_FB15_Pos (15U)
5488#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
5489#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
5490#define CAN_F7R2_FB16_Pos (16U)
5491#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
5492#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
5493#define CAN_F7R2_FB17_Pos (17U)
5494#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
5495#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
5496#define CAN_F7R2_FB18_Pos (18U)
5497#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
5498#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
5499#define CAN_F7R2_FB19_Pos (19U)
5500#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
5501#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
5502#define CAN_F7R2_FB20_Pos (20U)
5503#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
5504#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
5505#define CAN_F7R2_FB21_Pos (21U)
5506#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
5507#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
5508#define CAN_F7R2_FB22_Pos (22U)
5509#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
5510#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
5511#define CAN_F7R2_FB23_Pos (23U)
5512#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
5513#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
5514#define CAN_F7R2_FB24_Pos (24U)
5515#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
5516#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
5517#define CAN_F7R2_FB25_Pos (25U)
5518#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
5519#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
5520#define CAN_F7R2_FB26_Pos (26U)
5521#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
5522#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
5523#define CAN_F7R2_FB27_Pos (27U)
5524#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
5525#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
5526#define CAN_F7R2_FB28_Pos (28U)
5527#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
5528#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
5529#define CAN_F7R2_FB29_Pos (29U)
5530#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
5531#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
5532#define CAN_F7R2_FB30_Pos (30U)
5533#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
5534#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
5535#define CAN_F7R2_FB31_Pos (31U)
5536#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
5537#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
5538
5539/******************* Bit definition for CAN_F8R2 register *******************/
5540#define CAN_F8R2_FB0_Pos (0U)
5541#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
5542#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
5543#define CAN_F8R2_FB1_Pos (1U)
5544#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
5545#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
5546#define CAN_F8R2_FB2_Pos (2U)
5547#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
5548#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
5549#define CAN_F8R2_FB3_Pos (3U)
5550#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
5551#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
5552#define CAN_F8R2_FB4_Pos (4U)
5553#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
5554#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
5555#define CAN_F8R2_FB5_Pos (5U)
5556#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
5557#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
5558#define CAN_F8R2_FB6_Pos (6U)
5559#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
5560#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
5561#define CAN_F8R2_FB7_Pos (7U)
5562#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
5563#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
5564#define CAN_F8R2_FB8_Pos (8U)
5565#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
5566#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
5567#define CAN_F8R2_FB9_Pos (9U)
5568#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
5569#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
5570#define CAN_F8R2_FB10_Pos (10U)
5571#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
5572#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
5573#define CAN_F8R2_FB11_Pos (11U)
5574#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
5575#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
5576#define CAN_F8R2_FB12_Pos (12U)
5577#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
5578#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
5579#define CAN_F8R2_FB13_Pos (13U)
5580#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
5581#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
5582#define CAN_F8R2_FB14_Pos (14U)
5583#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
5584#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
5585#define CAN_F8R2_FB15_Pos (15U)
5586#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
5587#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
5588#define CAN_F8R2_FB16_Pos (16U)
5589#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
5590#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
5591#define CAN_F8R2_FB17_Pos (17U)
5592#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
5593#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
5594#define CAN_F8R2_FB18_Pos (18U)
5595#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
5596#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
5597#define CAN_F8R2_FB19_Pos (19U)
5598#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
5599#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
5600#define CAN_F8R2_FB20_Pos (20U)
5601#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
5602#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
5603#define CAN_F8R2_FB21_Pos (21U)
5604#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
5605#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
5606#define CAN_F8R2_FB22_Pos (22U)
5607#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
5608#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
5609#define CAN_F8R2_FB23_Pos (23U)
5610#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
5611#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
5612#define CAN_F8R2_FB24_Pos (24U)
5613#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
5614#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
5615#define CAN_F8R2_FB25_Pos (25U)
5616#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
5617#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
5618#define CAN_F8R2_FB26_Pos (26U)
5619#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
5620#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
5621#define CAN_F8R2_FB27_Pos (27U)
5622#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
5623#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
5624#define CAN_F8R2_FB28_Pos (28U)
5625#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
5626#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
5627#define CAN_F8R2_FB29_Pos (29U)
5628#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
5629#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
5630#define CAN_F8R2_FB30_Pos (30U)
5631#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
5632#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
5633#define CAN_F8R2_FB31_Pos (31U)
5634#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
5635#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
5636
5637/******************* Bit definition for CAN_F9R2 register *******************/
5638#define CAN_F9R2_FB0_Pos (0U)
5639#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
5640#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
5641#define CAN_F9R2_FB1_Pos (1U)
5642#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
5643#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
5644#define CAN_F9R2_FB2_Pos (2U)
5645#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
5646#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
5647#define CAN_F9R2_FB3_Pos (3U)
5648#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
5649#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
5650#define CAN_F9R2_FB4_Pos (4U)
5651#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
5652#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
5653#define CAN_F9R2_FB5_Pos (5U)
5654#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
5655#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
5656#define CAN_F9R2_FB6_Pos (6U)
5657#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
5658#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
5659#define CAN_F9R2_FB7_Pos (7U)
5660#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
5661#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
5662#define CAN_F9R2_FB8_Pos (8U)
5663#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
5664#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
5665#define CAN_F9R2_FB9_Pos (9U)
5666#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
5667#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
5668#define CAN_F9R2_FB10_Pos (10U)
5669#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
5670#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
5671#define CAN_F9R2_FB11_Pos (11U)
5672#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
5673#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
5674#define CAN_F9R2_FB12_Pos (12U)
5675#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
5676#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
5677#define CAN_F9R2_FB13_Pos (13U)
5678#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
5679#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
5680#define CAN_F9R2_FB14_Pos (14U)
5681#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
5682#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
5683#define CAN_F9R2_FB15_Pos (15U)
5684#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
5685#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
5686#define CAN_F9R2_FB16_Pos (16U)
5687#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
5688#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
5689#define CAN_F9R2_FB17_Pos (17U)
5690#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
5691#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
5692#define CAN_F9R2_FB18_Pos (18U)
5693#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
5694#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
5695#define CAN_F9R2_FB19_Pos (19U)
5696#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5697#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5698#define CAN_F9R2_FB20_Pos (20U)
5699#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5700#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5701#define CAN_F9R2_FB21_Pos (21U)
5702#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5703#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5704#define CAN_F9R2_FB22_Pos (22U)
5705#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5706#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5707#define CAN_F9R2_FB23_Pos (23U)
5708#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5709#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5710#define CAN_F9R2_FB24_Pos (24U)
5711#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5712#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5713#define CAN_F9R2_FB25_Pos (25U)
5714#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5715#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5716#define CAN_F9R2_FB26_Pos (26U)
5717#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5718#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5719#define CAN_F9R2_FB27_Pos (27U)
5720#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5721#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5722#define CAN_F9R2_FB28_Pos (28U)
5723#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5724#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5725#define CAN_F9R2_FB29_Pos (29U)
5726#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5727#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5728#define CAN_F9R2_FB30_Pos (30U)
5729#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5730#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5731#define CAN_F9R2_FB31_Pos (31U)
5732#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5733#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5734
5735/******************* Bit definition for CAN_F10R2 register ******************/
5736#define CAN_F10R2_FB0_Pos (0U)
5737#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5738#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5739#define CAN_F10R2_FB1_Pos (1U)
5740#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5741#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5742#define CAN_F10R2_FB2_Pos (2U)
5743#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5744#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5745#define CAN_F10R2_FB3_Pos (3U)
5746#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5747#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5748#define CAN_F10R2_FB4_Pos (4U)
5749#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5750#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5751#define CAN_F10R2_FB5_Pos (5U)
5752#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5753#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5754#define CAN_F10R2_FB6_Pos (6U)
5755#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5756#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5757#define CAN_F10R2_FB7_Pos (7U)
5758#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5759#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5760#define CAN_F10R2_FB8_Pos (8U)
5761#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5762#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5763#define CAN_F10R2_FB9_Pos (9U)
5764#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5765#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5766#define CAN_F10R2_FB10_Pos (10U)
5767#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5768#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5769#define CAN_F10R2_FB11_Pos (11U)
5770#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5771#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5772#define CAN_F10R2_FB12_Pos (12U)
5773#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5774#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5775#define CAN_F10R2_FB13_Pos (13U)
5776#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5777#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5778#define CAN_F10R2_FB14_Pos (14U)
5779#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5780#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5781#define CAN_F10R2_FB15_Pos (15U)
5782#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5783#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5784#define CAN_F10R2_FB16_Pos (16U)
5785#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5786#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5787#define CAN_F10R2_FB17_Pos (17U)
5788#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5789#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5790#define CAN_F10R2_FB18_Pos (18U)
5791#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5792#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5793#define CAN_F10R2_FB19_Pos (19U)
5794#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5795#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5796#define CAN_F10R2_FB20_Pos (20U)
5797#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5798#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5799#define CAN_F10R2_FB21_Pos (21U)
5800#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5801#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5802#define CAN_F10R2_FB22_Pos (22U)
5803#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5804#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5805#define CAN_F10R2_FB23_Pos (23U)
5806#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5807#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5808#define CAN_F10R2_FB24_Pos (24U)
5809#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5810#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5811#define CAN_F10R2_FB25_Pos (25U)
5812#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5813#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5814#define CAN_F10R2_FB26_Pos (26U)
5815#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5816#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5817#define CAN_F10R2_FB27_Pos (27U)
5818#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5819#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5820#define CAN_F10R2_FB28_Pos (28U)
5821#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5822#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5823#define CAN_F10R2_FB29_Pos (29U)
5824#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5825#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5826#define CAN_F10R2_FB30_Pos (30U)
5827#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5828#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5829#define CAN_F10R2_FB31_Pos (31U)
5830#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5831#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5832
5833/******************* Bit definition for CAN_F11R2 register ******************/
5834#define CAN_F11R2_FB0_Pos (0U)
5835#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5836#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5837#define CAN_F11R2_FB1_Pos (1U)
5838#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5839#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5840#define CAN_F11R2_FB2_Pos (2U)
5841#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5842#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5843#define CAN_F11R2_FB3_Pos (3U)
5844#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5845#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5846#define CAN_F11R2_FB4_Pos (4U)
5847#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5848#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5849#define CAN_F11R2_FB5_Pos (5U)
5850#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5851#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5852#define CAN_F11R2_FB6_Pos (6U)
5853#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5854#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5855#define CAN_F11R2_FB7_Pos (7U)
5856#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5857#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5858#define CAN_F11R2_FB8_Pos (8U)
5859#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5860#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5861#define CAN_F11R2_FB9_Pos (9U)
5862#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5863#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5864#define CAN_F11R2_FB10_Pos (10U)
5865#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5866#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5867#define CAN_F11R2_FB11_Pos (11U)
5868#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5869#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5870#define CAN_F11R2_FB12_Pos (12U)
5871#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5872#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5873#define CAN_F11R2_FB13_Pos (13U)
5874#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5875#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5876#define CAN_F11R2_FB14_Pos (14U)
5877#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5878#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5879#define CAN_F11R2_FB15_Pos (15U)
5880#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5881#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5882#define CAN_F11R2_FB16_Pos (16U)
5883#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5884#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5885#define CAN_F11R2_FB17_Pos (17U)
5886#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5887#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5888#define CAN_F11R2_FB18_Pos (18U)
5889#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5890#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5891#define CAN_F11R2_FB19_Pos (19U)
5892#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5893#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5894#define CAN_F11R2_FB20_Pos (20U)
5895#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5896#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5897#define CAN_F11R2_FB21_Pos (21U)
5898#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5899#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5900#define CAN_F11R2_FB22_Pos (22U)
5901#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5902#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5903#define CAN_F11R2_FB23_Pos (23U)
5904#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5905#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5906#define CAN_F11R2_FB24_Pos (24U)
5907#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5908#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5909#define CAN_F11R2_FB25_Pos (25U)
5910#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5911#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5912#define CAN_F11R2_FB26_Pos (26U)
5913#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5914#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5915#define CAN_F11R2_FB27_Pos (27U)
5916#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5917#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5918#define CAN_F11R2_FB28_Pos (28U)
5919#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5920#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5921#define CAN_F11R2_FB29_Pos (29U)
5922#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5923#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5924#define CAN_F11R2_FB30_Pos (30U)
5925#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5926#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5927#define CAN_F11R2_FB31_Pos (31U)
5928#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5929#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5930
5931/******************* Bit definition for CAN_F12R2 register ******************/
5932#define CAN_F12R2_FB0_Pos (0U)
5933#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5934#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5935#define CAN_F12R2_FB1_Pos (1U)
5936#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5937#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5938#define CAN_F12R2_FB2_Pos (2U)
5939#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5940#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5941#define CAN_F12R2_FB3_Pos (3U)
5942#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5943#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5944#define CAN_F12R2_FB4_Pos (4U)
5945#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5946#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5947#define CAN_F12R2_FB5_Pos (5U)
5948#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5949#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5950#define CAN_F12R2_FB6_Pos (6U)
5951#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5952#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5953#define CAN_F12R2_FB7_Pos (7U)
5954#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5955#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5956#define CAN_F12R2_FB8_Pos (8U)
5957#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5958#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5959#define CAN_F12R2_FB9_Pos (9U)
5960#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5961#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5962#define CAN_F12R2_FB10_Pos (10U)
5963#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5964#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5965#define CAN_F12R2_FB11_Pos (11U)
5966#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5967#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5968#define CAN_F12R2_FB12_Pos (12U)
5969#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5970#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5971#define CAN_F12R2_FB13_Pos (13U)
5972#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5973#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5974#define CAN_F12R2_FB14_Pos (14U)
5975#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5976#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5977#define CAN_F12R2_FB15_Pos (15U)
5978#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5979#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5980#define CAN_F12R2_FB16_Pos (16U)
5981#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5982#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5983#define CAN_F12R2_FB17_Pos (17U)
5984#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5985#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5986#define CAN_F12R2_FB18_Pos (18U)
5987#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5988#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5989#define CAN_F12R2_FB19_Pos (19U)
5990#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5991#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5992#define CAN_F12R2_FB20_Pos (20U)
5993#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5994#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5995#define CAN_F12R2_FB21_Pos (21U)
5996#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5997#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5998#define CAN_F12R2_FB22_Pos (22U)
5999#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
6000#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
6001#define CAN_F12R2_FB23_Pos (23U)
6002#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
6003#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
6004#define CAN_F12R2_FB24_Pos (24U)
6005#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
6006#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
6007#define CAN_F12R2_FB25_Pos (25U)
6008#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
6009#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
6010#define CAN_F12R2_FB26_Pos (26U)
6011#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
6012#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
6013#define CAN_F12R2_FB27_Pos (27U)
6014#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
6015#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
6016#define CAN_F12R2_FB28_Pos (28U)
6017#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
6018#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
6019#define CAN_F12R2_FB29_Pos (29U)
6020#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
6021#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
6022#define CAN_F12R2_FB30_Pos (30U)
6023#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
6024#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
6025#define CAN_F12R2_FB31_Pos (31U)
6026#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
6027#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
6028
6029/******************* Bit definition for CAN_F13R2 register ******************/
6030#define CAN_F13R2_FB0_Pos (0U)
6031#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
6032#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
6033#define CAN_F13R2_FB1_Pos (1U)
6034#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
6035#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
6036#define CAN_F13R2_FB2_Pos (2U)
6037#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
6038#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
6039#define CAN_F13R2_FB3_Pos (3U)
6040#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
6041#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
6042#define CAN_F13R2_FB4_Pos (4U)
6043#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
6044#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
6045#define CAN_F13R2_FB5_Pos (5U)
6046#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
6047#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
6048#define CAN_F13R2_FB6_Pos (6U)
6049#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
6050#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
6051#define CAN_F13R2_FB7_Pos (7U)
6052#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
6053#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
6054#define CAN_F13R2_FB8_Pos (8U)
6055#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
6056#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
6057#define CAN_F13R2_FB9_Pos (9U)
6058#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
6059#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
6060#define CAN_F13R2_FB10_Pos (10U)
6061#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
6062#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
6063#define CAN_F13R2_FB11_Pos (11U)
6064#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
6065#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
6066#define CAN_F13R2_FB12_Pos (12U)
6067#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
6068#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
6069#define CAN_F13R2_FB13_Pos (13U)
6070#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
6071#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
6072#define CAN_F13R2_FB14_Pos (14U)
6073#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
6074#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
6075#define CAN_F13R2_FB15_Pos (15U)
6076#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
6077#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
6078#define CAN_F13R2_FB16_Pos (16U)
6079#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
6080#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
6081#define CAN_F13R2_FB17_Pos (17U)
6082#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
6083#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
6084#define CAN_F13R2_FB18_Pos (18U)
6085#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
6086#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
6087#define CAN_F13R2_FB19_Pos (19U)
6088#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
6089#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
6090#define CAN_F13R2_FB20_Pos (20U)
6091#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
6092#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
6093#define CAN_F13R2_FB21_Pos (21U)
6094#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
6095#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
6096#define CAN_F13R2_FB22_Pos (22U)
6097#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
6098#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
6099#define CAN_F13R2_FB23_Pos (23U)
6100#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
6101#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
6102#define CAN_F13R2_FB24_Pos (24U)
6103#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
6104#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
6105#define CAN_F13R2_FB25_Pos (25U)
6106#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
6107#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
6108#define CAN_F13R2_FB26_Pos (26U)
6109#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
6110#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
6111#define CAN_F13R2_FB27_Pos (27U)
6112#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
6113#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
6114#define CAN_F13R2_FB28_Pos (28U)
6115#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
6116#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
6117#define CAN_F13R2_FB29_Pos (29U)
6118#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
6119#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
6120#define CAN_F13R2_FB30_Pos (30U)
6121#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
6122#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
6123#define CAN_F13R2_FB31_Pos (31U)
6124#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
6125#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
6126
6127/******************************************************************************/
6128/* */
6129/* CRC calculation unit */
6130/* */
6131/******************************************************************************/
6132/******************* Bit definition for CRC_DR register *********************/
6133#define CRC_DR_DR_Pos (0U)
6134#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
6135#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
6136
6137/******************* Bit definition for CRC_IDR register ********************/
6138#define CRC_IDR_IDR_Pos (0U)
6139#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
6140#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
6141
6142/******************** Bit definition for CRC_CR register ********************/
6143#define CRC_CR_RESET_Pos (0U)
6144#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
6145#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
6146#define CRC_CR_POLYSIZE_Pos (3U)
6147#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
6148#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
6149#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
6150#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
6151#define CRC_CR_REV_IN_Pos (5U)
6152#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
6153#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
6154#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
6155#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
6156#define CRC_CR_REV_OUT_Pos (7U)
6157#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
6158#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
6159
6160/******************* Bit definition for CRC_INIT register *******************/
6161#define CRC_INIT_INIT_Pos (0U)
6162#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
6163#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
6164
6165/******************* Bit definition for CRC_POL register ********************/
6166#define CRC_POL_POL_Pos (0U)
6167#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
6168#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
6169
6170/******************************************************************************/
6171/* */
6172/* Advanced Encryption Standard (AES) */
6173/* */
6174/******************************************************************************/
6175/******************* Bit definition for AES_CR register *********************/
6176#define AES_CR_EN_Pos (0U)
6177#define AES_CR_EN_Msk (0x1U << AES_CR_EN_Pos) /*!< 0x00000001 */
6178#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
6179#define AES_CR_DATATYPE_Pos (1U)
6180#define AES_CR_DATATYPE_Msk (0x3U << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
6181#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
6182#define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
6183#define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
6184
6185#define AES_CR_MODE_Pos (3U)
6186#define AES_CR_MODE_Msk (0x3U << AES_CR_MODE_Pos) /*!< 0x00000018 */
6187#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
6188#define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */
6189#define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */
6190
6191#define AES_CR_CHMOD_Pos (5U)
6192#define AES_CR_CHMOD_Msk (0x803U << AES_CR_CHMOD_Pos) /*!< 0x00010060 */
6193#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
6194#define AES_CR_CHMOD_0 (0x001U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
6195#define AES_CR_CHMOD_1 (0x002U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
6196#define AES_CR_CHMOD_2 (0x800U << AES_CR_CHMOD_Pos) /*!< 0x00010000 */
6197
6198#define AES_CR_CCFC_Pos (7U)
6199#define AES_CR_CCFC_Msk (0x1U << AES_CR_CCFC_Pos) /*!< 0x00000080 */
6200#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
6201#define AES_CR_ERRC_Pos (8U)
6202#define AES_CR_ERRC_Msk (0x1U << AES_CR_ERRC_Pos) /*!< 0x00000100 */
6203#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
6204#define AES_CR_CCFIE_Pos (9U)
6205#define AES_CR_CCFIE_Msk (0x1U << AES_CR_CCFIE_Pos) /*!< 0x00000200 */
6206#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */
6207#define AES_CR_ERRIE_Pos (10U)
6208#define AES_CR_ERRIE_Msk (0x1U << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
6209#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
6210#define AES_CR_DMAINEN_Pos (11U)
6211#define AES_CR_DMAINEN_Msk (0x1U << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
6212#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */
6213#define AES_CR_DMAOUTEN_Pos (12U)
6214#define AES_CR_DMAOUTEN_Msk (0x1U << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
6215#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */
6216
6217#define AES_CR_GCMPH_Pos (13U)
6218#define AES_CR_GCMPH_Msk (0x3U << AES_CR_GCMPH_Pos) /*!< 0x00006000 */
6219#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */
6220#define AES_CR_GCMPH_0 (0x1U << AES_CR_GCMPH_Pos) /*!< 0x00002000 */
6221#define AES_CR_GCMPH_1 (0x2U << AES_CR_GCMPH_Pos) /*!< 0x00004000 */
6222
6223#define AES_CR_KEYSIZE_Pos (18U)
6224#define AES_CR_KEYSIZE_Msk (0x1U << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */
6225#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */
6226
6227/******************* Bit definition for AES_SR register *********************/
6228#define AES_SR_CCF_Pos (0U)
6229#define AES_SR_CCF_Msk (0x1U << AES_SR_CCF_Pos) /*!< 0x00000001 */
6230#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
6231#define AES_SR_RDERR_Pos (1U)
6232#define AES_SR_RDERR_Msk (0x1U << AES_SR_RDERR_Pos) /*!< 0x00000002 */
6233#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
6234#define AES_SR_WRERR_Pos (2U)
6235#define AES_SR_WRERR_Msk (0x1U << AES_SR_WRERR_Pos) /*!< 0x00000004 */
6236#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
6237#define AES_SR_BUSY_Pos (3U)
6238#define AES_SR_BUSY_Msk (0x1U << AES_SR_BUSY_Pos) /*!< 0x00000008 */
6239#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */
6240
6241/******************* Bit definition for AES_DINR register *******************/
6242#define AES_DINR_Pos (0U)
6243#define AES_DINR_Msk (0xFFFFFFFFU << AES_DINR_Pos) /*!< 0xFFFFFFFF */
6244#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
6245
6246/******************* Bit definition for AES_DOUTR register ******************/
6247#define AES_DOUTR_Pos (0U)
6248#define AES_DOUTR_Msk (0xFFFFFFFFU << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */
6249#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
6250
6251/******************* Bit definition for AES_KEYR0 register ******************/
6252#define AES_KEYR0_Pos (0U)
6253#define AES_KEYR0_Msk (0xFFFFFFFFU << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */
6254#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
6255
6256/******************* Bit definition for AES_KEYR1 register ******************/
6257#define AES_KEYR1_Pos (0U)
6258#define AES_KEYR1_Msk (0xFFFFFFFFU << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */
6259#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
6260
6261/******************* Bit definition for AES_KEYR2 register ******************/
6262#define AES_KEYR2_Pos (0U)
6263#define AES_KEYR2_Msk (0xFFFFFFFFU << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */
6264#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
6265
6266/******************* Bit definition for AES_KEYR3 register ******************/
6267#define AES_KEYR3_Pos (0U)
6268#define AES_KEYR3_Msk (0xFFFFFFFFU << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */
6269#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
6270
6271/******************* Bit definition for AES_KEYR4 register ******************/
6272#define AES_KEYR4_Pos (0U)
6273#define AES_KEYR4_Msk (0xFFFFFFFFU << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */
6274#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */
6275
6276/******************* Bit definition for AES_KEYR5 register ******************/
6277#define AES_KEYR5_Pos (0U)
6278#define AES_KEYR5_Msk (0xFFFFFFFFU << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */
6279#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */
6280
6281/******************* Bit definition for AES_KEYR6 register ******************/
6282#define AES_KEYR6_Pos (0U)
6283#define AES_KEYR6_Msk (0xFFFFFFFFU << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */
6284#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */
6285
6286/******************* Bit definition for AES_KEYR7 register ******************/
6287#define AES_KEYR7_Pos (0U)
6288#define AES_KEYR7_Msk (0xFFFFFFFFU << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */
6289#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */
6290
6291/******************* Bit definition for AES_IVR0 register ******************/
6292#define AES_IVR0_Pos (0U)
6293#define AES_IVR0_Msk (0xFFFFFFFFU << AES_IVR0_Pos) /*!< 0xFFFFFFFF */
6294#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
6295
6296/******************* Bit definition for AES_IVR1 register ******************/
6297#define AES_IVR1_Pos (0U)
6298#define AES_IVR1_Msk (0xFFFFFFFFU << AES_IVR1_Pos) /*!< 0xFFFFFFFF */
6299#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
6300
6301/******************* Bit definition for AES_IVR2 register ******************/
6302#define AES_IVR2_Pos (0U)
6303#define AES_IVR2_Msk (0xFFFFFFFFU << AES_IVR2_Pos) /*!< 0xFFFFFFFF */
6304#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
6305
6306/******************* Bit definition for AES_IVR3 register ******************/
6307#define AES_IVR3_Pos (0U)
6308#define AES_IVR3_Msk (0xFFFFFFFFU << AES_IVR3_Pos) /*!< 0xFFFFFFFF */
6309#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
6310
6311/******************* Bit definition for AES_SUSP0R register ******************/
6312#define AES_SUSP0R_Pos (0U)
6313#define AES_SUSP0R_Msk (0xFFFFFFFFU << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */
6314#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */
6315
6316/******************* Bit definition for AES_SUSP1R register ******************/
6317#define AES_SUSP1R_Pos (0U)
6318#define AES_SUSP1R_Msk (0xFFFFFFFFU << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */
6319#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */
6320
6321/******************* Bit definition for AES_SUSP2R register ******************/
6322#define AES_SUSP2R_Pos (0U)
6323#define AES_SUSP2R_Msk (0xFFFFFFFFU << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */
6324#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */
6325
6326/******************* Bit definition for AES_SUSP3R register ******************/
6327#define AES_SUSP3R_Pos (0U)
6328#define AES_SUSP3R_Msk (0xFFFFFFFFU << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */
6329#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */
6330
6331/******************* Bit definition for AES_SUSP4R register ******************/
6332#define AES_SUSP4R_Pos (0U)
6333#define AES_SUSP4R_Msk (0xFFFFFFFFU << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */
6334#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */
6335
6336/******************* Bit definition for AES_SUSP5R register ******************/
6337#define AES_SUSP5R_Pos (0U)
6338#define AES_SUSP5R_Msk (0xFFFFFFFFU << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */
6339#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */
6340
6341/******************* Bit definition for AES_SUSP6R register ******************/
6342#define AES_SUSP6R_Pos (0U)
6343#define AES_SUSP6R_Msk (0xFFFFFFFFU << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */
6344#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */
6345
6346/******************* Bit definition for AES_SUSP7R register ******************/
6347#define AES_SUSP7R_Pos (0U)
6348#define AES_SUSP7R_Msk (0xFFFFFFFFU << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */
6349#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */
6350
6351/******************************************************************************/
6352/* */
6353/* Digital to Analog Converter */
6354/* */
6355/******************************************************************************/
6356/*
6357 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
6358 */
6359#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
6360
6361/******************** Bit definition for DAC_CR register ********************/
6362#define DAC_CR_EN1_Pos (0U)
6363#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
6364#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
6365#define DAC_CR_TEN1_Pos (2U)
6366#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
6367#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
6368
6369#define DAC_CR_TSEL1_Pos (3U)
6370#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
6371#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
6372#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
6373#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
6374#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
6375
6376#define DAC_CR_WAVE1_Pos (6U)
6377#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
6378#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
6379#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
6380#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
6381
6382#define DAC_CR_MAMP1_Pos (8U)
6383#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
6384#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
6385#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
6386#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
6387#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
6388#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
6389
6390#define DAC_CR_DMAEN1_Pos (12U)
6391#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
6392#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
6393#define DAC_CR_DMAUDRIE1_Pos (13U)
6394#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
6395#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
6396#define DAC_CR_CEN1_Pos (14U)
6397#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
6398#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
6399
6400#define DAC_CR_EN2_Pos (16U)
6401#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
6402#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
6403#define DAC_CR_TEN2_Pos (18U)
6404#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
6405#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
6406
6407#define DAC_CR_TSEL2_Pos (19U)
6408#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
6409#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
6410#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
6411#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
6412#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
6413
6414#define DAC_CR_WAVE2_Pos (22U)
6415#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
6416#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
6417#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
6418#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
6419
6420#define DAC_CR_MAMP2_Pos (24U)
6421#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
6422#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
6423#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
6424#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
6425#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
6426#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
6427
6428#define DAC_CR_DMAEN2_Pos (28U)
6429#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
6430#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
6431#define DAC_CR_DMAUDRIE2_Pos (29U)
6432#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
6433#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
6434#define DAC_CR_CEN2_Pos (30U)
6435#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
6436#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
6437
6438/***************** Bit definition for DAC_SWTRIGR register ******************/
6439#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
6440#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
6441#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
6442#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
6443#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
6444#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
6445
6446/***************** Bit definition for DAC_DHR12R1 register ******************/
6447#define DAC_DHR12R1_DACC1DHR_Pos (0U)
6448#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
6449#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
6450
6451/***************** Bit definition for DAC_DHR12L1 register ******************/
6452#define DAC_DHR12L1_DACC1DHR_Pos (4U)
6453#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
6454#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
6455
6456/****************** Bit definition for DAC_DHR8R1 register ******************/
6457#define DAC_DHR8R1_DACC1DHR_Pos (0U)
6458#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
6459#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
6460
6461/***************** Bit definition for DAC_DHR12R2 register ******************/
6462#define DAC_DHR12R2_DACC2DHR_Pos (0U)
6463#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
6464#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
6465
6466/***************** Bit definition for DAC_DHR12L2 register ******************/
6467#define DAC_DHR12L2_DACC2DHR_Pos (4U)
6468#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
6469#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
6470
6471/****************** Bit definition for DAC_DHR8R2 register ******************/
6472#define DAC_DHR8R2_DACC2DHR_Pos (0U)
6473#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
6474#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
6475
6476/***************** Bit definition for DAC_DHR12RD register ******************/
6477#define DAC_DHR12RD_DACC1DHR_Pos (0U)
6478#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
6479#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
6480#define DAC_DHR12RD_DACC2DHR_Pos (16U)
6481#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
6482#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
6483
6484/***************** Bit definition for DAC_DHR12LD register ******************/
6485#define DAC_DHR12LD_DACC1DHR_Pos (4U)
6486#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
6487#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
6488#define DAC_DHR12LD_DACC2DHR_Pos (20U)
6489#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
6490#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
6491
6492/****************** Bit definition for DAC_DHR8RD register ******************/
6493#define DAC_DHR8RD_DACC1DHR_Pos (0U)
6494#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
6495#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
6496#define DAC_DHR8RD_DACC2DHR_Pos (8U)
6497#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
6498#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
6499
6500/******************* Bit definition for DAC_DOR1 register *******************/
6501#define DAC_DOR1_DACC1DOR_Pos (0U)
6502#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
6503#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
6504
6505/******************* Bit definition for DAC_DOR2 register *******************/
6506#define DAC_DOR2_DACC2DOR_Pos (0U)
6507#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
6508#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
6509
6510/******************** Bit definition for DAC_SR register ********************/
6511#define DAC_SR_DMAUDR1_Pos (13U)
6512#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
6513#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
6514#define DAC_SR_CAL_FLAG1_Pos (14U)
6515#define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
6516#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
6517#define DAC_SR_BWST1_Pos (15U)
6518#define DAC_SR_BWST1_Msk (0x1U << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
6519#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
6520
6521#define DAC_SR_DMAUDR2_Pos (29U)
6522#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
6523#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
6524#define DAC_SR_CAL_FLAG2_Pos (30U)
6525#define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
6526#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
6527#define DAC_SR_BWST2_Pos (31U)
6528#define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
6529#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
6530
6531/******************* Bit definition for DAC_CCR register ********************/
6532#define DAC_CCR_OTRIM1_Pos (0U)
6533#define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
6534#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
6535#define DAC_CCR_OTRIM2_Pos (16U)
6536#define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
6537#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
6538
6539/******************* Bit definition for DAC_MCR register *******************/
6540#define DAC_MCR_MODE1_Pos (0U)
6541#define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
6542#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
6543#define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
6544#define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
6545#define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
6546
6547#define DAC_MCR_MODE2_Pos (16U)
6548#define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
6549#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
6550#define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
6551#define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
6552#define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
6553
6554/****************** Bit definition for DAC_SHSR1 register ******************/
6555#define DAC_SHSR1_TSAMPLE1_Pos (0U)
6556#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
6557#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
6558
6559/****************** Bit definition for DAC_SHSR2 register ******************/
6560#define DAC_SHSR2_TSAMPLE2_Pos (0U)
6561#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
6562#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
6563
6564/****************** Bit definition for DAC_SHHR register ******************/
6565#define DAC_SHHR_THOLD1_Pos (0U)
6566#define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
6567#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
6568#define DAC_SHHR_THOLD2_Pos (16U)
6569#define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
6570#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
6571
6572/****************** Bit definition for DAC_SHRR register ******************/
6573#define DAC_SHRR_TREFRESH1_Pos (0U)
6574#define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
6575#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
6576#define DAC_SHRR_TREFRESH2_Pos (16U)
6577#define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
6578#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
6579
6580/******************************************************************************/
6581/* */
6582/* Digital Filter for Sigma Delta Modulators */
6583/* */
6584/******************************************************************************/
6585
6586/**************** DFSDM channel configuration registers ********************/
6587
6588/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6589#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6590#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
6591#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
6592#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6593#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
6594#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
6595#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6596#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
6597#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
6598#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6599#define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
6600#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
6601#define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
6602#define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
6603#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6604#define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
6605#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
6606#define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
6607#define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
6608#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6609#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
6610#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
6611#define DFSDM_CHCFGR1_CHEN_Pos (7U)
6612#define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
6613#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
6614#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6615#define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
6616#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
6617#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6618#define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
6619#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
6620#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6621#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
6622#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
6623#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
6624#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
6625#define DFSDM_CHCFGR1_SITP_Pos (0U)
6626#define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
6627#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
6628#define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
6629#define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
6630
6631/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6632#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6633#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
6634#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
6635#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6636#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
6637#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
6638
6639/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
6640#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6641#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
6642#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
6643#define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
6644#define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
6645#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6646#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
6647#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
6648#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6649#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
6650#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
6651#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6652#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
6653#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
6654
6655/**************** Bit definition for DFSDM_CHWDATR register *******************/
6656#define DFSDM_CHWDATR_WDATA_Pos (0U)
6657#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
6658#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
6659
6660/**************** Bit definition for DFSDM_CHDATINR register *****************/
6661#define DFSDM_CHDATINR_INDAT0_Pos (0U)
6662#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
6663#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
6664#define DFSDM_CHDATINR_INDAT1_Pos (16U)
6665#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
6666#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
6667
6668/************************ DFSDM module registers ****************************/
6669
6670/***************** Bit definition for DFSDM_FLTCR1 register *******************/
6671#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6672#define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
6673#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
6674#define DFSDM_FLTCR1_FAST_Pos (29U)
6675#define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
6676#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
6677#define DFSDM_FLTCR1_RCH_Pos (24U)
6678#define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
6679#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
6680#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6681#define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
6682#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
6683#define DFSDM_FLTCR1_RSYNC_Pos (19U)
6684#define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
6685#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
6686#define DFSDM_FLTCR1_RCONT_Pos (18U)
6687#define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
6688#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
6689#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6690#define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
6691#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
6692#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6693#define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
6694#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
6695#define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
6696#define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
6697#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6698#define DFSDM_FLTCR1_JEXTSEL_Msk (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000700 */
6699#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
6700#define DFSDM_FLTCR1_JEXTSEL_2 (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
6701#define DFSDM_FLTCR1_JEXTSEL_1 (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
6702#define DFSDM_FLTCR1_JEXTSEL_0 (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
6703#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6704#define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
6705#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
6706#define DFSDM_FLTCR1_JSCAN_Pos (4U)
6707#define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
6708#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
6709#define DFSDM_FLTCR1_JSYNC_Pos (3U)
6710#define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
6711#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
6712#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6713#define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
6714#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
6715#define DFSDM_FLTCR1_DFEN_Pos (0U)
6716#define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
6717#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
6718
6719/***************** Bit definition for DFSDM_FLTCR2 register *******************/
6720#define DFSDM_FLTCR2_AWDCH_Pos (16U)
6721#define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
6722#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
6723#define DFSDM_FLTCR2_EXCH_Pos (8U)
6724#define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
6725#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
6726#define DFSDM_FLTCR2_CKABIE_Pos (6U)
6727#define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
6728#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
6729#define DFSDM_FLTCR2_SCDIE_Pos (5U)
6730#define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
6731#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
6732#define DFSDM_FLTCR2_AWDIE_Pos (4U)
6733#define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
6734#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
6735#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6736#define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
6737#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
6738#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6739#define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
6740#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
6741#define DFSDM_FLTCR2_REOCIE_Pos (1U)
6742#define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
6743#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
6744#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6745#define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
6746#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
6747
6748/***************** Bit definition for DFSDM_FLTISR register *******************/
6749#define DFSDM_FLTISR_SCDF_Pos (24U)
6750#define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
6751#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
6752#define DFSDM_FLTISR_CKABF_Pos (16U)
6753#define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
6754#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
6755#define DFSDM_FLTISR_RCIP_Pos (14U)
6756#define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
6757#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
6758#define DFSDM_FLTISR_JCIP_Pos (13U)
6759#define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
6760#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
6761#define DFSDM_FLTISR_AWDF_Pos (4U)
6762#define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
6763#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
6764#define DFSDM_FLTISR_ROVRF_Pos (3U)
6765#define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
6766#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
6767#define DFSDM_FLTISR_JOVRF_Pos (2U)
6768#define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
6769#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
6770#define DFSDM_FLTISR_REOCF_Pos (1U)
6771#define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
6772#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
6773#define DFSDM_FLTISR_JEOCF_Pos (0U)
6774#define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
6775#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
6776
6777/***************** Bit definition for DFSDM_FLTICR register *******************/
6778#define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
6779#define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
6780#define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
6781#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6782#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
6783#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
6784#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6785#define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
6786#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
6787#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6788#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
6789#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
6790
6791/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
6792#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6793#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
6794#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
6795
6796/***************** Bit definition for DFSDM_FLTFCR register *******************/
6797#define DFSDM_FLTFCR_FORD_Pos (29U)
6798#define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
6799#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
6800#define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
6801#define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
6802#define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
6803#define DFSDM_FLTFCR_FOSR_Pos (16U)
6804#define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
6805#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
6806#define DFSDM_FLTFCR_IOSR_Pos (0U)
6807#define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
6808#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
6809
6810/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
6811#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6812#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
6813#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
6814#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6815#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
6816#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
6817
6818/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
6819#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6820#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
6821#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
6822#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6823#define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
6824#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
6825#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6826#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
6827#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
6828
6829/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
6830#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6831#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
6832#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
6833#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6834#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
6835#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
6836
6837/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
6838#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6839#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
6840#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
6841#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6842#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
6843#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
6844
6845/*************** Bit definition for DFSDM_FLTAWSR register *******************/
6846#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6847#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
6848#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
6849#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6850#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
6851#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
6852
6853/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
6854#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6855#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
6856#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
6857#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6858#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
6859#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
6860
6861/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
6862#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6863#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
6864#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
6865#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6866#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
6867#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
6868
6869/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
6870#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6871#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
6872#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
6873#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6874#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
6875#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
6876
6877/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
6878#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6879#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
6880#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
6881
6882/******************************************************************************/
6883/* */
6884/* DMA Controller (DMA) */
6885/* */
6886/******************************************************************************/
6887
6888/******************* Bit definition for DMA_ISR register ********************/
6889#define DMA_ISR_GIF1_Pos (0U)
6890#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
6891#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
6892#define DMA_ISR_TCIF1_Pos (1U)
6893#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
6894#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
6895#define DMA_ISR_HTIF1_Pos (2U)
6896#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
6897#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
6898#define DMA_ISR_TEIF1_Pos (3U)
6899#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
6900#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
6901#define DMA_ISR_GIF2_Pos (4U)
6902#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
6903#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
6904#define DMA_ISR_TCIF2_Pos (5U)
6905#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
6906#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
6907#define DMA_ISR_HTIF2_Pos (6U)
6908#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
6909#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
6910#define DMA_ISR_TEIF2_Pos (7U)
6911#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
6912#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
6913#define DMA_ISR_GIF3_Pos (8U)
6914#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
6915#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
6916#define DMA_ISR_TCIF3_Pos (9U)
6917#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
6918#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
6919#define DMA_ISR_HTIF3_Pos (10U)
6920#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
6921#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
6922#define DMA_ISR_TEIF3_Pos (11U)
6923#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
6924#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
6925#define DMA_ISR_GIF4_Pos (12U)
6926#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
6927#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
6928#define DMA_ISR_TCIF4_Pos (13U)
6929#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
6930#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
6931#define DMA_ISR_HTIF4_Pos (14U)
6932#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
6933#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
6934#define DMA_ISR_TEIF4_Pos (15U)
6935#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
6936#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
6937#define DMA_ISR_GIF5_Pos (16U)
6938#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
6939#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
6940#define DMA_ISR_TCIF5_Pos (17U)
6941#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
6942#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
6943#define DMA_ISR_HTIF5_Pos (18U)
6944#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
6945#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
6946#define DMA_ISR_TEIF5_Pos (19U)
6947#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
6948#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
6949#define DMA_ISR_GIF6_Pos (20U)
6950#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
6951#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
6952#define DMA_ISR_TCIF6_Pos (21U)
6953#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
6954#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
6955#define DMA_ISR_HTIF6_Pos (22U)
6956#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
6957#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
6958#define DMA_ISR_TEIF6_Pos (23U)
6959#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
6960#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
6961#define DMA_ISR_GIF7_Pos (24U)
6962#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
6963#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
6964#define DMA_ISR_TCIF7_Pos (25U)
6965#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
6966#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
6967#define DMA_ISR_HTIF7_Pos (26U)
6968#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
6969#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
6970#define DMA_ISR_TEIF7_Pos (27U)
6971#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
6972#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
6973
6974/******************* Bit definition for DMA_IFCR register *******************/
6975#define DMA_IFCR_CGIF1_Pos (0U)
6976#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
6977#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
6978#define DMA_IFCR_CTCIF1_Pos (1U)
6979#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
6980#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
6981#define DMA_IFCR_CHTIF1_Pos (2U)
6982#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
6983#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
6984#define DMA_IFCR_CTEIF1_Pos (3U)
6985#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
6986#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
6987#define DMA_IFCR_CGIF2_Pos (4U)
6988#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
6989#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
6990#define DMA_IFCR_CTCIF2_Pos (5U)
6991#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
6992#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
6993#define DMA_IFCR_CHTIF2_Pos (6U)
6994#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
6995#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
6996#define DMA_IFCR_CTEIF2_Pos (7U)
6997#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
6998#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
6999#define DMA_IFCR_CGIF3_Pos (8U)
7000#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
7001#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
7002#define DMA_IFCR_CTCIF3_Pos (9U)
7003#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
7004#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
7005#define DMA_IFCR_CHTIF3_Pos (10U)
7006#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
7007#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
7008#define DMA_IFCR_CTEIF3_Pos (11U)
7009#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
7010#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
7011#define DMA_IFCR_CGIF4_Pos (12U)
7012#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
7013#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
7014#define DMA_IFCR_CTCIF4_Pos (13U)
7015#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
7016#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
7017#define DMA_IFCR_CHTIF4_Pos (14U)
7018#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
7019#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
7020#define DMA_IFCR_CTEIF4_Pos (15U)
7021#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
7022#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
7023#define DMA_IFCR_CGIF5_Pos (16U)
7024#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
7025#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
7026#define DMA_IFCR_CTCIF5_Pos (17U)
7027#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
7028#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
7029#define DMA_IFCR_CHTIF5_Pos (18U)
7030#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
7031#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
7032#define DMA_IFCR_CTEIF5_Pos (19U)
7033#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
7034#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
7035#define DMA_IFCR_CGIF6_Pos (20U)
7036#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
7037#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
7038#define DMA_IFCR_CTCIF6_Pos (21U)
7039#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
7040#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
7041#define DMA_IFCR_CHTIF6_Pos (22U)
7042#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
7043#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
7044#define DMA_IFCR_CTEIF6_Pos (23U)
7045#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
7046#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
7047#define DMA_IFCR_CGIF7_Pos (24U)
7048#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
7049#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
7050#define DMA_IFCR_CTCIF7_Pos (25U)
7051#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
7052#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
7053#define DMA_IFCR_CHTIF7_Pos (26U)
7054#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
7055#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
7056#define DMA_IFCR_CTEIF7_Pos (27U)
7057#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
7058#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
7059
7060/******************* Bit definition for DMA_CCR register ********************/
7061#define DMA_CCR_EN_Pos (0U)
7062#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
7063#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
7064#define DMA_CCR_TCIE_Pos (1U)
7065#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
7066#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
7067#define DMA_CCR_HTIE_Pos (2U)
7068#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
7069#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
7070#define DMA_CCR_TEIE_Pos (3U)
7071#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
7072#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
7073#define DMA_CCR_DIR_Pos (4U)
7074#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
7075#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
7076#define DMA_CCR_CIRC_Pos (5U)
7077#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
7078#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
7079#define DMA_CCR_PINC_Pos (6U)
7080#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
7081#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
7082#define DMA_CCR_MINC_Pos (7U)
7083#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
7084#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
7085
7086#define DMA_CCR_PSIZE_Pos (8U)
7087#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
7088#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
7089#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
7090#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
7091
7092#define DMA_CCR_MSIZE_Pos (10U)
7093#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
7094#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
7095#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
7096#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
7097
7098#define DMA_CCR_PL_Pos (12U)
7099#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
7100#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
7101#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
7102#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
7103
7104#define DMA_CCR_MEM2MEM_Pos (14U)
7105#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
7106#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
7107
7108/****************** Bit definition for DMA_CNDTR register *******************/
7109#define DMA_CNDTR_NDT_Pos (0U)
7110#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
7111#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
7112
7113/****************** Bit definition for DMA_CPAR register ********************/
7114#define DMA_CPAR_PA_Pos (0U)
7115#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
7116#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
7117
7118/****************** Bit definition for DMA_CMAR register ********************/
7119#define DMA_CMAR_MA_Pos (0U)
7120#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
7121#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
7122
7123
7124/******************* Bit definition for DMA_CSELR register *******************/
7125#define DMA_CSELR_C1S_Pos (0U)
7126#define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
7127#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
7128#define DMA_CSELR_C2S_Pos (4U)
7129#define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
7130#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
7131#define DMA_CSELR_C3S_Pos (8U)
7132#define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
7133#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
7134#define DMA_CSELR_C4S_Pos (12U)
7135#define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
7136#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
7137#define DMA_CSELR_C5S_Pos (16U)
7138#define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
7139#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
7140#define DMA_CSELR_C6S_Pos (20U)
7141#define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
7142#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
7143#define DMA_CSELR_C7S_Pos (24U)
7144#define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
7145#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
7146
7147/******************************************************************************/
7148/* */
7149/* External Interrupt/Event Controller */
7150/* */
7151/******************************************************************************/
7152/******************* Bit definition for EXTI_IMR1 register ******************/
7153#define EXTI_IMR1_IM0_Pos (0U)
7154#define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
7155#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
7156#define EXTI_IMR1_IM1_Pos (1U)
7157#define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
7158#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
7159#define EXTI_IMR1_IM2_Pos (2U)
7160#define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
7161#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
7162#define EXTI_IMR1_IM3_Pos (3U)
7163#define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
7164#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
7165#define EXTI_IMR1_IM4_Pos (4U)
7166#define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
7167#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
7168#define EXTI_IMR1_IM5_Pos (5U)
7169#define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
7170#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
7171#define EXTI_IMR1_IM6_Pos (6U)
7172#define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
7173#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
7174#define EXTI_IMR1_IM7_Pos (7U)
7175#define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
7176#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
7177#define EXTI_IMR1_IM8_Pos (8U)
7178#define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
7179#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
7180#define EXTI_IMR1_IM9_Pos (9U)
7181#define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
7182#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
7183#define EXTI_IMR1_IM10_Pos (10U)
7184#define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
7185#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
7186#define EXTI_IMR1_IM11_Pos (11U)
7187#define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
7188#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
7189#define EXTI_IMR1_IM12_Pos (12U)
7190#define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
7191#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
7192#define EXTI_IMR1_IM13_Pos (13U)
7193#define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
7194#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
7195#define EXTI_IMR1_IM14_Pos (14U)
7196#define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
7197#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
7198#define EXTI_IMR1_IM15_Pos (15U)
7199#define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
7200#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
7201#define EXTI_IMR1_IM16_Pos (16U)
7202#define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
7203#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
7204#define EXTI_IMR1_IM17_Pos (17U)
7205#define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
7206#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
7207#define EXTI_IMR1_IM18_Pos (18U)
7208#define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
7209#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
7210#define EXTI_IMR1_IM19_Pos (19U)
7211#define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
7212#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
7213#define EXTI_IMR1_IM20_Pos (20U)
7214#define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
7215#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
7216#define EXTI_IMR1_IM21_Pos (21U)
7217#define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
7218#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
7219#define EXTI_IMR1_IM22_Pos (22U)
7220#define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
7221#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
7222#define EXTI_IMR1_IM23_Pos (23U)
7223#define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
7224#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
7225#define EXTI_IMR1_IM24_Pos (24U)
7226#define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
7227#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
7228#define EXTI_IMR1_IM25_Pos (25U)
7229#define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
7230#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
7231#define EXTI_IMR1_IM26_Pos (26U)
7232#define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
7233#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
7234#define EXTI_IMR1_IM27_Pos (27U)
7235#define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
7236#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
7237#define EXTI_IMR1_IM28_Pos (28U)
7238#define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
7239#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
7240#define EXTI_IMR1_IM29_Pos (29U)
7241#define EXTI_IMR1_IM29_Msk (0x1U << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
7242#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
7243#define EXTI_IMR1_IM30_Pos (30U)
7244#define EXTI_IMR1_IM30_Msk (0x1U << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
7245#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
7246#define EXTI_IMR1_IM31_Pos (31U)
7247#define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
7248#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
7249#define EXTI_IMR1_IM_Pos (0U)
7250#define EXTI_IMR1_IM_Msk (0xFFFFFFFFU << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
7251#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
7252
7253/******************* Bit definition for EXTI_EMR1 register ******************/
7254#define EXTI_EMR1_EM0_Pos (0U)
7255#define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
7256#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
7257#define EXTI_EMR1_EM1_Pos (1U)
7258#define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
7259#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
7260#define EXTI_EMR1_EM2_Pos (2U)
7261#define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
7262#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
7263#define EXTI_EMR1_EM3_Pos (3U)
7264#define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
7265#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
7266#define EXTI_EMR1_EM4_Pos (4U)
7267#define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
7268#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
7269#define EXTI_EMR1_EM5_Pos (5U)
7270#define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
7271#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
7272#define EXTI_EMR1_EM6_Pos (6U)
7273#define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
7274#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
7275#define EXTI_EMR1_EM7_Pos (7U)
7276#define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
7277#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
7278#define EXTI_EMR1_EM8_Pos (8U)
7279#define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
7280#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
7281#define EXTI_EMR1_EM9_Pos (9U)
7282#define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
7283#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
7284#define EXTI_EMR1_EM10_Pos (10U)
7285#define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
7286#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
7287#define EXTI_EMR1_EM11_Pos (11U)
7288#define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
7289#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
7290#define EXTI_EMR1_EM12_Pos (12U)
7291#define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
7292#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
7293#define EXTI_EMR1_EM13_Pos (13U)
7294#define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
7295#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
7296#define EXTI_EMR1_EM14_Pos (14U)
7297#define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
7298#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
7299#define EXTI_EMR1_EM15_Pos (15U)
7300#define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
7301#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
7302#define EXTI_EMR1_EM16_Pos (16U)
7303#define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
7304#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
7305#define EXTI_EMR1_EM17_Pos (17U)
7306#define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
7307#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
7308#define EXTI_EMR1_EM18_Pos (18U)
7309#define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
7310#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
7311#define EXTI_EMR1_EM19_Pos (19U)
7312#define EXTI_EMR1_EM19_Msk (0x1U << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
7313#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
7314#define EXTI_EMR1_EM20_Pos (20U)
7315#define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
7316#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
7317#define EXTI_EMR1_EM21_Pos (21U)
7318#define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
7319#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
7320#define EXTI_EMR1_EM22_Pos (22U)
7321#define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
7322#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
7323#define EXTI_EMR1_EM23_Pos (23U)
7324#define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
7325#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
7326#define EXTI_EMR1_EM24_Pos (24U)
7327#define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
7328#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
7329#define EXTI_EMR1_EM25_Pos (25U)
7330#define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
7331#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
7332#define EXTI_EMR1_EM26_Pos (26U)
7333#define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
7334#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
7335#define EXTI_EMR1_EM27_Pos (27U)
7336#define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
7337#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
7338#define EXTI_EMR1_EM28_Pos (28U)
7339#define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
7340#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
7341#define EXTI_EMR1_EM29_Pos (29U)
7342#define EXTI_EMR1_EM29_Msk (0x1U << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
7343#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
7344#define EXTI_EMR1_EM30_Pos (30U)
7345#define EXTI_EMR1_EM30_Msk (0x1U << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
7346#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
7347#define EXTI_EMR1_EM31_Pos (31U)
7348#define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
7349#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
7350
7351/****************** Bit definition for EXTI_RTSR1 register ******************/
7352#define EXTI_RTSR1_RT0_Pos (0U)
7353#define EXTI_RTSR1_RT0_Msk (0x1U << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
7354#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
7355#define EXTI_RTSR1_RT1_Pos (1U)
7356#define EXTI_RTSR1_RT1_Msk (0x1U << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
7357#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
7358#define EXTI_RTSR1_RT2_Pos (2U)
7359#define EXTI_RTSR1_RT2_Msk (0x1U << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
7360#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
7361#define EXTI_RTSR1_RT3_Pos (3U)
7362#define EXTI_RTSR1_RT3_Msk (0x1U << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
7363#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
7364#define EXTI_RTSR1_RT4_Pos (4U)
7365#define EXTI_RTSR1_RT4_Msk (0x1U << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
7366#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
7367#define EXTI_RTSR1_RT5_Pos (5U)
7368#define EXTI_RTSR1_RT5_Msk (0x1U << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
7369#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
7370#define EXTI_RTSR1_RT6_Pos (6U)
7371#define EXTI_RTSR1_RT6_Msk (0x1U << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
7372#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
7373#define EXTI_RTSR1_RT7_Pos (7U)
7374#define EXTI_RTSR1_RT7_Msk (0x1U << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
7375#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
7376#define EXTI_RTSR1_RT8_Pos (8U)
7377#define EXTI_RTSR1_RT8_Msk (0x1U << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
7378#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
7379#define EXTI_RTSR1_RT9_Pos (9U)
7380#define EXTI_RTSR1_RT9_Msk (0x1U << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
7381#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
7382#define EXTI_RTSR1_RT10_Pos (10U)
7383#define EXTI_RTSR1_RT10_Msk (0x1U << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
7384#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
7385#define EXTI_RTSR1_RT11_Pos (11U)
7386#define EXTI_RTSR1_RT11_Msk (0x1U << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
7387#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
7388#define EXTI_RTSR1_RT12_Pos (12U)
7389#define EXTI_RTSR1_RT12_Msk (0x1U << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
7390#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
7391#define EXTI_RTSR1_RT13_Pos (13U)
7392#define EXTI_RTSR1_RT13_Msk (0x1U << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
7393#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
7394#define EXTI_RTSR1_RT14_Pos (14U)
7395#define EXTI_RTSR1_RT14_Msk (0x1U << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
7396#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
7397#define EXTI_RTSR1_RT15_Pos (15U)
7398#define EXTI_RTSR1_RT15_Msk (0x1U << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
7399#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
7400#define EXTI_RTSR1_RT16_Pos (16U)
7401#define EXTI_RTSR1_RT16_Msk (0x1U << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
7402#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
7403#define EXTI_RTSR1_RT18_Pos (18U)
7404#define EXTI_RTSR1_RT18_Msk (0x1U << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
7405#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
7406#define EXTI_RTSR1_RT19_Pos (19U)
7407#define EXTI_RTSR1_RT19_Msk (0x1U << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
7408#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
7409#define EXTI_RTSR1_RT20_Pos (20U)
7410#define EXTI_RTSR1_RT20_Msk (0x1U << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
7411#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
7412#define EXTI_RTSR1_RT21_Pos (21U)
7413#define EXTI_RTSR1_RT21_Msk (0x1U << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
7414#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
7415#define EXTI_RTSR1_RT22_Pos (22U)
7416#define EXTI_RTSR1_RT22_Msk (0x1U << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
7417#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
7418
7419/****************** Bit definition for EXTI_FTSR1 register ******************/
7420#define EXTI_FTSR1_FT0_Pos (0U)
7421#define EXTI_FTSR1_FT0_Msk (0x1U << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
7422#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
7423#define EXTI_FTSR1_FT1_Pos (1U)
7424#define EXTI_FTSR1_FT1_Msk (0x1U << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
7425#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
7426#define EXTI_FTSR1_FT2_Pos (2U)
7427#define EXTI_FTSR1_FT2_Msk (0x1U << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
7428#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
7429#define EXTI_FTSR1_FT3_Pos (3U)
7430#define EXTI_FTSR1_FT3_Msk (0x1U << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
7431#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
7432#define EXTI_FTSR1_FT4_Pos (4U)
7433#define EXTI_FTSR1_FT4_Msk (0x1U << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
7434#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
7435#define EXTI_FTSR1_FT5_Pos (5U)
7436#define EXTI_FTSR1_FT5_Msk (0x1U << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
7437#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
7438#define EXTI_FTSR1_FT6_Pos (6U)
7439#define EXTI_FTSR1_FT6_Msk (0x1U << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
7440#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
7441#define EXTI_FTSR1_FT7_Pos (7U)
7442#define EXTI_FTSR1_FT7_Msk (0x1U << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
7443#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
7444#define EXTI_FTSR1_FT8_Pos (8U)
7445#define EXTI_FTSR1_FT8_Msk (0x1U << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
7446#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
7447#define EXTI_FTSR1_FT9_Pos (9U)
7448#define EXTI_FTSR1_FT9_Msk (0x1U << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
7449#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
7450#define EXTI_FTSR1_FT10_Pos (10U)
7451#define EXTI_FTSR1_FT10_Msk (0x1U << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
7452#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
7453#define EXTI_FTSR1_FT11_Pos (11U)
7454#define EXTI_FTSR1_FT11_Msk (0x1U << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
7455#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
7456#define EXTI_FTSR1_FT12_Pos (12U)
7457#define EXTI_FTSR1_FT12_Msk (0x1U << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
7458#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
7459#define EXTI_FTSR1_FT13_Pos (13U)
7460#define EXTI_FTSR1_FT13_Msk (0x1U << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
7461#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
7462#define EXTI_FTSR1_FT14_Pos (14U)
7463#define EXTI_FTSR1_FT14_Msk (0x1U << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
7464#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
7465#define EXTI_FTSR1_FT15_Pos (15U)
7466#define EXTI_FTSR1_FT15_Msk (0x1U << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
7467#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
7468#define EXTI_FTSR1_FT16_Pos (16U)
7469#define EXTI_FTSR1_FT16_Msk (0x1U << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
7470#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
7471#define EXTI_FTSR1_FT18_Pos (18U)
7472#define EXTI_FTSR1_FT18_Msk (0x1U << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
7473#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */
7474#define EXTI_FTSR1_FT19_Pos (19U)
7475#define EXTI_FTSR1_FT19_Msk (0x1U << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
7476#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
7477#define EXTI_FTSR1_FT20_Pos (20U)
7478#define EXTI_FTSR1_FT20_Msk (0x1U << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
7479#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
7480#define EXTI_FTSR1_FT21_Pos (21U)
7481#define EXTI_FTSR1_FT21_Msk (0x1U << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
7482#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
7483#define EXTI_FTSR1_FT22_Pos (22U)
7484#define EXTI_FTSR1_FT22_Msk (0x1U << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
7485#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
7486
7487/****************** Bit definition for EXTI_SWIER1 register *****************/
7488#define EXTI_SWIER1_SWI0_Pos (0U)
7489#define EXTI_SWIER1_SWI0_Msk (0x1U << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
7490#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
7491#define EXTI_SWIER1_SWI1_Pos (1U)
7492#define EXTI_SWIER1_SWI1_Msk (0x1U << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
7493#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
7494#define EXTI_SWIER1_SWI2_Pos (2U)
7495#define EXTI_SWIER1_SWI2_Msk (0x1U << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
7496#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
7497#define EXTI_SWIER1_SWI3_Pos (3U)
7498#define EXTI_SWIER1_SWI3_Msk (0x1U << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
7499#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
7500#define EXTI_SWIER1_SWI4_Pos (4U)
7501#define EXTI_SWIER1_SWI4_Msk (0x1U << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
7502#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
7503#define EXTI_SWIER1_SWI5_Pos (5U)
7504#define EXTI_SWIER1_SWI5_Msk (0x1U << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
7505#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
7506#define EXTI_SWIER1_SWI6_Pos (6U)
7507#define EXTI_SWIER1_SWI6_Msk (0x1U << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
7508#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
7509#define EXTI_SWIER1_SWI7_Pos (7U)
7510#define EXTI_SWIER1_SWI7_Msk (0x1U << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
7511#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
7512#define EXTI_SWIER1_SWI8_Pos (8U)
7513#define EXTI_SWIER1_SWI8_Msk (0x1U << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
7514#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
7515#define EXTI_SWIER1_SWI9_Pos (9U)
7516#define EXTI_SWIER1_SWI9_Msk (0x1U << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
7517#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
7518#define EXTI_SWIER1_SWI10_Pos (10U)
7519#define EXTI_SWIER1_SWI10_Msk (0x1U << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
7520#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
7521#define EXTI_SWIER1_SWI11_Pos (11U)
7522#define EXTI_SWIER1_SWI11_Msk (0x1U << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
7523#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
7524#define EXTI_SWIER1_SWI12_Pos (12U)
7525#define EXTI_SWIER1_SWI12_Msk (0x1U << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
7526#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
7527#define EXTI_SWIER1_SWI13_Pos (13U)
7528#define EXTI_SWIER1_SWI13_Msk (0x1U << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
7529#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
7530#define EXTI_SWIER1_SWI14_Pos (14U)
7531#define EXTI_SWIER1_SWI14_Msk (0x1U << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
7532#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
7533#define EXTI_SWIER1_SWI15_Pos (15U)
7534#define EXTI_SWIER1_SWI15_Msk (0x1U << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
7535#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
7536#define EXTI_SWIER1_SWI16_Pos (16U)
7537#define EXTI_SWIER1_SWI16_Msk (0x1U << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
7538#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
7539#define EXTI_SWIER1_SWI18_Pos (18U)
7540#define EXTI_SWIER1_SWI18_Msk (0x1U << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
7541#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
7542#define EXTI_SWIER1_SWI19_Pos (19U)
7543#define EXTI_SWIER1_SWI19_Msk (0x1U << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
7544#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
7545#define EXTI_SWIER1_SWI20_Pos (20U)
7546#define EXTI_SWIER1_SWI20_Msk (0x1U << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
7547#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
7548#define EXTI_SWIER1_SWI21_Pos (21U)
7549#define EXTI_SWIER1_SWI21_Msk (0x1U << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
7550#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
7551#define EXTI_SWIER1_SWI22_Pos (22U)
7552#define EXTI_SWIER1_SWI22_Msk (0x1U << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
7553#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
7554
7555/******************* Bit definition for EXTI_PR1 register *******************/
7556#define EXTI_PR1_PIF0_Pos (0U)
7557#define EXTI_PR1_PIF0_Msk (0x1U << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
7558#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
7559#define EXTI_PR1_PIF1_Pos (1U)
7560#define EXTI_PR1_PIF1_Msk (0x1U << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
7561#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
7562#define EXTI_PR1_PIF2_Pos (2U)
7563#define EXTI_PR1_PIF2_Msk (0x1U << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
7564#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
7565#define EXTI_PR1_PIF3_Pos (3U)
7566#define EXTI_PR1_PIF3_Msk (0x1U << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
7567#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
7568#define EXTI_PR1_PIF4_Pos (4U)
7569#define EXTI_PR1_PIF4_Msk (0x1U << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
7570#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
7571#define EXTI_PR1_PIF5_Pos (5U)
7572#define EXTI_PR1_PIF5_Msk (0x1U << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
7573#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
7574#define EXTI_PR1_PIF6_Pos (6U)
7575#define EXTI_PR1_PIF6_Msk (0x1U << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
7576#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
7577#define EXTI_PR1_PIF7_Pos (7U)
7578#define EXTI_PR1_PIF7_Msk (0x1U << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
7579#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
7580#define EXTI_PR1_PIF8_Pos (8U)
7581#define EXTI_PR1_PIF8_Msk (0x1U << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
7582#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
7583#define EXTI_PR1_PIF9_Pos (9U)
7584#define EXTI_PR1_PIF9_Msk (0x1U << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
7585#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
7586#define EXTI_PR1_PIF10_Pos (10U)
7587#define EXTI_PR1_PIF10_Msk (0x1U << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
7588#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
7589#define EXTI_PR1_PIF11_Pos (11U)
7590#define EXTI_PR1_PIF11_Msk (0x1U << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
7591#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
7592#define EXTI_PR1_PIF12_Pos (12U)
7593#define EXTI_PR1_PIF12_Msk (0x1U << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
7594#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
7595#define EXTI_PR1_PIF13_Pos (13U)
7596#define EXTI_PR1_PIF13_Msk (0x1U << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
7597#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
7598#define EXTI_PR1_PIF14_Pos (14U)
7599#define EXTI_PR1_PIF14_Msk (0x1U << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
7600#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
7601#define EXTI_PR1_PIF15_Pos (15U)
7602#define EXTI_PR1_PIF15_Msk (0x1U << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
7603#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
7604#define EXTI_PR1_PIF16_Pos (16U)
7605#define EXTI_PR1_PIF16_Msk (0x1U << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
7606#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
7607#define EXTI_PR1_PIF18_Pos (18U)
7608#define EXTI_PR1_PIF18_Msk (0x1U << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */
7609#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */
7610#define EXTI_PR1_PIF19_Pos (19U)
7611#define EXTI_PR1_PIF19_Msk (0x1U << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
7612#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
7613#define EXTI_PR1_PIF20_Pos (20U)
7614#define EXTI_PR1_PIF20_Msk (0x1U << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
7615#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
7616#define EXTI_PR1_PIF21_Pos (21U)
7617#define EXTI_PR1_PIF21_Msk (0x1U << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
7618#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
7619#define EXTI_PR1_PIF22_Pos (22U)
7620#define EXTI_PR1_PIF22_Msk (0x1U << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
7621#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
7622
7623/******************* Bit definition for EXTI_IMR2 register ******************/
7624#define EXTI_IMR2_IM32_Pos (0U)
7625#define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
7626#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
7627#define EXTI_IMR2_IM33_Pos (1U)
7628#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
7629#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
7630#define EXTI_IMR2_IM34_Pos (2U)
7631#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
7632#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
7633#define EXTI_IMR2_IM35_Pos (3U)
7634#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
7635#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
7636#define EXTI_IMR2_IM36_Pos (4U)
7637#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
7638#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
7639#define EXTI_IMR2_IM37_Pos (5U)
7640#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
7641#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
7642#define EXTI_IMR2_IM38_Pos (6U)
7643#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
7644#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
7645#define EXTI_IMR2_IM_Pos (0U)
7646#define EXTI_IMR2_IM_Msk (0x7FU << EXTI_IMR2_IM_Pos) /*!< 0x0000007F */
7647#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
7648
7649/******************* Bit definition for EXTI_EMR2 register ******************/
7650#define EXTI_EMR2_EM32_Pos (0U)
7651#define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
7652#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
7653#define EXTI_EMR2_EM33_Pos (1U)
7654#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
7655#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
7656#define EXTI_EMR2_EM34_Pos (2U)
7657#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
7658#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
7659#define EXTI_EMR2_EM35_Pos (3U)
7660#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
7661#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
7662#define EXTI_EMR2_EM36_Pos (4U)
7663#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
7664#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
7665#define EXTI_EMR2_EM37_Pos (5U)
7666#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
7667#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
7668#define EXTI_EMR2_EM38_Pos (6U)
7669#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
7670#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
7671#define EXTI_EMR2_EM_Pos (0U)
7672#define EXTI_EMR2_EM_Msk (0x7FU << EXTI_EMR2_EM_Pos) /*!< 0x0000007F */
7673#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
7674
7675/****************** Bit definition for EXTI_RTSR2 register ******************/
7676#define EXTI_RTSR2_RT35_Pos (3U)
7677#define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
7678#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
7679#define EXTI_RTSR2_RT36_Pos (4U)
7680#define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
7681#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
7682#define EXTI_RTSR2_RT37_Pos (5U)
7683#define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
7684#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
7685#define EXTI_RTSR2_RT38_Pos (6U)
7686#define EXTI_RTSR2_RT38_Msk (0x1U << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
7687#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
7688
7689/****************** Bit definition for EXTI_FTSR2 register ******************/
7690#define EXTI_FTSR2_FT35_Pos (3U)
7691#define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
7692#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
7693#define EXTI_FTSR2_FT36_Pos (4U)
7694#define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
7695#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
7696#define EXTI_FTSR2_FT37_Pos (5U)
7697#define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
7698#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
7699#define EXTI_FTSR2_FT38_Pos (6U)
7700#define EXTI_FTSR2_FT38_Msk (0x1U << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
7701#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
7702
7703/****************** Bit definition for EXTI_SWIER2 register *****************/
7704#define EXTI_SWIER2_SWI35_Pos (3U)
7705#define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
7706#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
7707#define EXTI_SWIER2_SWI36_Pos (4U)
7708#define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
7709#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
7710#define EXTI_SWIER2_SWI37_Pos (5U)
7711#define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
7712#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
7713#define EXTI_SWIER2_SWI38_Pos (6U)
7714#define EXTI_SWIER2_SWI38_Msk (0x1U << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
7715#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
7716
7717/******************* Bit definition for EXTI_PR2 register *******************/
7718#define EXTI_PR2_PIF35_Pos (3U)
7719#define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
7720#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
7721#define EXTI_PR2_PIF36_Pos (4U)
7722#define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
7723#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
7724#define EXTI_PR2_PIF37_Pos (5U)
7725#define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
7726#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
7727#define EXTI_PR2_PIF38_Pos (6U)
7728#define EXTI_PR2_PIF38_Msk (0x1U << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
7729#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
7730
7731
7732/******************************************************************************/
7733/* */
7734/* FLASH */
7735/* */
7736/******************************************************************************/
7737/******************* Bits definition for FLASH_ACR register *****************/
7738#define FLASH_ACR_LATENCY_Pos (0U)
7739#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
7740#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
7741#define FLASH_ACR_LATENCY_0WS (0x00000000U)
7742#define FLASH_ACR_LATENCY_1WS (0x00000001U)
7743#define FLASH_ACR_LATENCY_2WS (0x00000002U)
7744#define FLASH_ACR_LATENCY_3WS (0x00000003U)
7745#define FLASH_ACR_LATENCY_4WS (0x00000004U)
7746#define FLASH_ACR_PRFTEN_Pos (8U)
7747#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
7748#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
7749#define FLASH_ACR_ICEN_Pos (9U)
7750#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
7751#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
7752#define FLASH_ACR_DCEN_Pos (10U)
7753#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
7754#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
7755#define FLASH_ACR_ICRST_Pos (11U)
7756#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
7757#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
7758#define FLASH_ACR_DCRST_Pos (12U)
7759#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
7760#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
7761#define FLASH_ACR_RUN_PD_Pos (13U)
7762#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
7763#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
7764#define FLASH_ACR_SLEEP_PD_Pos (14U)
7765#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
7766#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
7767
7768/******************* Bits definition for FLASH_SR register ******************/
7769#define FLASH_SR_EOP_Pos (0U)
7770#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
7771#define FLASH_SR_EOP FLASH_SR_EOP_Msk
7772#define FLASH_SR_OPERR_Pos (1U)
7773#define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
7774#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
7775#define FLASH_SR_PROGERR_Pos (3U)
7776#define FLASH_SR_PROGERR_Msk (0x1U << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
7777#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
7778#define FLASH_SR_WRPERR_Pos (4U)
7779#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
7780#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
7781#define FLASH_SR_PGAERR_Pos (5U)
7782#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
7783#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
7784#define FLASH_SR_SIZERR_Pos (6U)
7785#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
7786#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
7787#define FLASH_SR_PGSERR_Pos (7U)
7788#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
7789#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
7790#define FLASH_SR_MISERR_Pos (8U)
7791#define FLASH_SR_MISERR_Msk (0x1U << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
7792#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
7793#define FLASH_SR_FASTERR_Pos (9U)
7794#define FLASH_SR_FASTERR_Msk (0x1U << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
7795#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
7796#define FLASH_SR_RDERR_Pos (14U)
7797#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
7798#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
7799#define FLASH_SR_OPTVERR_Pos (15U)
7800#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
7801#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
7802#define FLASH_SR_BSY_Pos (16U)
7803#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
7804#define FLASH_SR_BSY FLASH_SR_BSY_Msk
7805
7806/******************* Bits definition for FLASH_CR register ******************/
7807#define FLASH_CR_PG_Pos (0U)
7808#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
7809#define FLASH_CR_PG FLASH_CR_PG_Msk
7810#define FLASH_CR_PER_Pos (1U)
7811#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
7812#define FLASH_CR_PER FLASH_CR_PER_Msk
7813#define FLASH_CR_MER1_Pos (2U)
7814#define FLASH_CR_MER1_Msk (0x1U << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
7815#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
7816#define FLASH_CR_PNB_Pos (3U)
7817#define FLASH_CR_PNB_Msk (0xFFU << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
7818#define FLASH_CR_PNB FLASH_CR_PNB_Msk
7819#define FLASH_CR_BKER_Pos (11U)
7820#define FLASH_CR_BKER_Msk (0x1U << FLASH_CR_BKER_Pos) /*!< 0x00000800 */
7821#define FLASH_CR_BKER FLASH_CR_BKER_Msk
7822#define FLASH_CR_MER2_Pos (15U)
7823#define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
7824#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
7825#define FLASH_CR_STRT_Pos (16U)
7826#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
7827#define FLASH_CR_STRT FLASH_CR_STRT_Msk
7828#define FLASH_CR_OPTSTRT_Pos (17U)
7829#define FLASH_CR_OPTSTRT_Msk (0x1U << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
7830#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
7831#define FLASH_CR_FSTPG_Pos (18U)
7832#define FLASH_CR_FSTPG_Msk (0x1U << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
7833#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
7834#define FLASH_CR_EOPIE_Pos (24U)
7835#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
7836#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
7837#define FLASH_CR_ERRIE_Pos (25U)
7838#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
7839#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
7840#define FLASH_CR_RDERRIE_Pos (26U)
7841#define FLASH_CR_RDERRIE_Msk (0x1U << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
7842#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
7843#define FLASH_CR_OBL_LAUNCH_Pos (27U)
7844#define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
7845#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
7846#define FLASH_CR_OPTLOCK_Pos (30U)
7847#define FLASH_CR_OPTLOCK_Msk (0x1U << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
7848#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
7849#define FLASH_CR_LOCK_Pos (31U)
7850#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
7851#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
7852
7853/******************* Bits definition for FLASH_ECCR register ***************/
7854#define FLASH_ECCR_ADDR_ECC_Pos (0U)
7855#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
7856#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
7857#define FLASH_ECCR_BK_ECC_Pos (19U)
7858#define FLASH_ECCR_BK_ECC_Msk (0x1U << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00080000 */
7859#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
7860#define FLASH_ECCR_SYSF_ECC_Pos (20U)
7861#define FLASH_ECCR_SYSF_ECC_Msk (0x1U << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
7862#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
7863#define FLASH_ECCR_ECCIE_Pos (24U)
7864#define FLASH_ECCR_ECCIE_Msk (0x1U << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
7865#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
7866#define FLASH_ECCR_ECCC_Pos (30U)
7867#define FLASH_ECCR_ECCC_Msk (0x1U << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
7868#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
7869#define FLASH_ECCR_ECCD_Pos (31U)
7870#define FLASH_ECCR_ECCD_Msk (0x1U << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
7871#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
7872
7873/******************* Bits definition for FLASH_OPTR register ***************/
7874#define FLASH_OPTR_RDP_Pos (0U)
7875#define FLASH_OPTR_RDP_Msk (0xFFU << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
7876#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
7877#define FLASH_OPTR_BOR_LEV_Pos (8U)
7878#define FLASH_OPTR_BOR_LEV_Msk (0x7U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
7879#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
7880#define FLASH_OPTR_BOR_LEV_0 (0x0U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
7881#define FLASH_OPTR_BOR_LEV_1 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
7882#define FLASH_OPTR_BOR_LEV_2 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
7883#define FLASH_OPTR_BOR_LEV_3 (0x3U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
7884#define FLASH_OPTR_BOR_LEV_4 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
7885#define FLASH_OPTR_nRST_STOP_Pos (12U)
7886#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
7887#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
7888#define FLASH_OPTR_nRST_STDBY_Pos (13U)
7889#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
7890#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
7891#define FLASH_OPTR_nRST_SHDW_Pos (14U)
7892#define FLASH_OPTR_nRST_SHDW_Msk (0x1U << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
7893#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
7894#define FLASH_OPTR_IWDG_SW_Pos (16U)
7895#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
7896#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
7897#define FLASH_OPTR_IWDG_STOP_Pos (17U)
7898#define FLASH_OPTR_IWDG_STOP_Msk (0x1U << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
7899#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
7900#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
7901#define FLASH_OPTR_IWDG_STDBY_Msk (0x1U << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
7902#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
7903#define FLASH_OPTR_WWDG_SW_Pos (19U)
7904#define FLASH_OPTR_WWDG_SW_Msk (0x1U << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
7905#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
7906#define FLASH_OPTR_BFB2_Pos (20U)
7907#define FLASH_OPTR_BFB2_Msk (0x1U << FLASH_OPTR_BFB2_Pos) /*!< 0x00100000 */
7908#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
7909#define FLASH_OPTR_DUALBANK_Pos (21U)
7910#define FLASH_OPTR_DUALBANK_Msk (0x1U << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */
7911#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk
7912#define FLASH_OPTR_nBOOT1_Pos (23U)
7913#define FLASH_OPTR_nBOOT1_Msk (0x1U << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
7914#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
7915#define FLASH_OPTR_SRAM2_PE_Pos (24U)
7916#define FLASH_OPTR_SRAM2_PE_Msk (0x1U << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
7917#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
7918#define FLASH_OPTR_SRAM2_RST_Pos (25U)
7919#define FLASH_OPTR_SRAM2_RST_Msk (0x1U << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
7920#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
7921
7922/****************** Bits definition for FLASH_PCROP1SR register **********/
7923#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
7924#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
7925#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
7926
7927/****************** Bits definition for FLASH_PCROP1ER register ***********/
7928#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
7929#define FLASH_PCROP1ER_PCROP1_END_Msk (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
7930#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
7931#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
7932#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
7933#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
7934
7935/****************** Bits definition for FLASH_WRP1AR register ***************/
7936#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
7937#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
7938#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
7939#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
7940#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
7941#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
7942
7943/****************** Bits definition for FLASH_WRPB1R register ***************/
7944#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
7945#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
7946#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
7947#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
7948#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
7949#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
7950
7951/****************** Bits definition for FLASH_PCROP2SR register **********/
7952#define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
7953#define FLASH_PCROP2SR_PCROP2_STRT_Msk (0xFFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0000FFFF */
7954#define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
7955
7956/****************** Bits definition for FLASH_PCROP2ER register ***********/
7957#define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
7958#define FLASH_PCROP2ER_PCROP2_END_Msk (0xFFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0000FFFF */
7959#define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
7960
7961/****************** Bits definition for FLASH_WRP2AR register ***************/
7962#define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
7963#define FLASH_WRP2AR_WRP2A_STRT_Msk (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */
7964#define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
7965#define FLASH_WRP2AR_WRP2A_END_Pos (16U)
7966#define FLASH_WRP2AR_WRP2A_END_Msk (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */
7967#define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
7968
7969/****************** Bits definition for FLASH_WRP2BR register ***************/
7970#define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
7971#define FLASH_WRP2BR_WRP2B_STRT_Msk (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */
7972#define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
7973#define FLASH_WRP2BR_WRP2B_END_Pos (16U)
7974#define FLASH_WRP2BR_WRP2B_END_Msk (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */
7975#define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
7976
7977
7978/******************************************************************************/
7979/* */
7980/* Flexible Memory Controller */
7981/* */
7982/******************************************************************************/
7983/****************** Bit definition for FMC_BCR1 register *******************/
7984#define FMC_BCR1_CCLKEN_Pos (20U)
7985#define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
7986#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
7987
7988/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
7989#define FMC_BCRx_MBKEN_Pos (0U)
7990#define FMC_BCRx_MBKEN_Msk (0x1U << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
7991#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
7992#define FMC_BCRx_MUXEN_Pos (1U)
7993#define FMC_BCRx_MUXEN_Msk (0x1U << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
7994#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7995
7996#define FMC_BCRx_MTYP_Pos (2U)
7997#define FMC_BCRx_MTYP_Msk (0x3U << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
7998#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7999#define FMC_BCRx_MTYP_0 (0x1U << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
8000#define FMC_BCRx_MTYP_1 (0x2U << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
8001
8002#define FMC_BCRx_MWID_Pos (4U)
8003#define FMC_BCRx_MWID_Msk (0x3U << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
8004#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
8005#define FMC_BCRx_MWID_0 (0x1U << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
8006#define FMC_BCRx_MWID_1 (0x2U << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
8007
8008#define FMC_BCRx_FACCEN_Pos (6U)
8009#define FMC_BCRx_FACCEN_Msk (0x1U << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
8010#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
8011#define FMC_BCRx_BURSTEN_Pos (8U)
8012#define FMC_BCRx_BURSTEN_Msk (0x1U << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
8013#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
8014#define FMC_BCRx_WAITPOL_Pos (9U)
8015#define FMC_BCRx_WAITPOL_Msk (0x1U << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
8016#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
8017#define FMC_BCRx_WAITCFG_Pos (11U)
8018#define FMC_BCRx_WAITCFG_Msk (0x1U << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
8019#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
8020#define FMC_BCRx_WREN_Pos (12U)
8021#define FMC_BCRx_WREN_Msk (0x1U << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
8022#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
8023#define FMC_BCRx_WAITEN_Pos (13U)
8024#define FMC_BCRx_WAITEN_Msk (0x1U << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
8025#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
8026#define FMC_BCRx_EXTMOD_Pos (14U)
8027#define FMC_BCRx_EXTMOD_Msk (0x1U << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
8028#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
8029#define FMC_BCRx_ASYNCWAIT_Pos (15U)
8030#define FMC_BCRx_ASYNCWAIT_Msk (0x1U << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
8031#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
8032
8033#define FMC_BCRx_CPSIZE_Pos (16U)
8034#define FMC_BCRx_CPSIZE_Msk (0x7U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
8035#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<CRAM page size */
8036#define FMC_BCRx_CPSIZE_0 (0x1U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
8037#define FMC_BCRx_CPSIZE_1 (0x2U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
8038#define FMC_BCRx_CPSIZE_2 (0x4U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
8039
8040#define FMC_BCRx_CBURSTRW_Pos (19U)
8041#define FMC_BCRx_CBURSTRW_Msk (0x1U << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
8042#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
8043
8044/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
8045#define FMC_BTRx_ADDSET_Pos (0U)
8046#define FMC_BTRx_ADDSET_Msk (0xFU << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
8047#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8048#define FMC_BTRx_ADDSET_0 (0x1U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
8049#define FMC_BTRx_ADDSET_1 (0x2U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
8050#define FMC_BTRx_ADDSET_2 (0x4U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
8051#define FMC_BTRx_ADDSET_3 (0x8U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
8052
8053#define FMC_BTRx_ADDHLD_Pos (4U)
8054#define FMC_BTRx_ADDHLD_Msk (0xFU << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
8055#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8056#define FMC_BTRx_ADDHLD_0 (0x1U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
8057#define FMC_BTRx_ADDHLD_1 (0x2U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
8058#define FMC_BTRx_ADDHLD_2 (0x4U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
8059#define FMC_BTRx_ADDHLD_3 (0x8U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
8060
8061#define FMC_BTRx_DATAST_Pos (8U)
8062#define FMC_BTRx_DATAST_Msk (0xFFU << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
8063#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8064#define FMC_BTRx_DATAST_0 (0x01U << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
8065#define FMC_BTRx_DATAST_1 (0x02U << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
8066#define FMC_BTRx_DATAST_2 (0x04U << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
8067#define FMC_BTRx_DATAST_3 (0x08U << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
8068#define FMC_BTRx_DATAST_4 (0x10U << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
8069#define FMC_BTRx_DATAST_5 (0x20U << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
8070#define FMC_BTRx_DATAST_6 (0x40U << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
8071#define FMC_BTRx_DATAST_7 (0x80U << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
8072
8073#define FMC_BTRx_BUSTURN_Pos (16U)
8074#define FMC_BTRx_BUSTURN_Msk (0xFU << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
8075#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8076#define FMC_BTRx_BUSTURN_0 (0x1U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
8077#define FMC_BTRx_BUSTURN_1 (0x2U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
8078#define FMC_BTRx_BUSTURN_2 (0x4U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
8079#define FMC_BTRx_BUSTURN_3 (0x8U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
8080
8081#define FMC_BTRx_CLKDIV_Pos (20U)
8082#define FMC_BTRx_CLKDIV_Msk (0xFU << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
8083#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8084#define FMC_BTRx_CLKDIV_0 (0x1U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
8085#define FMC_BTRx_CLKDIV_1 (0x2U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
8086#define FMC_BTRx_CLKDIV_2 (0x4U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
8087#define FMC_BTRx_CLKDIV_3 (0x8U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
8088
8089#define FMC_BTRx_DATLAT_Pos (24U)
8090#define FMC_BTRx_DATLAT_Msk (0xFU << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
8091#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLAT[3:0] bits (Data latency) */
8092#define FMC_BTRx_DATLAT_0 (0x1U << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
8093#define FMC_BTRx_DATLAT_1 (0x2U << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
8094#define FMC_BTRx_DATLAT_2 (0x4U << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
8095#define FMC_BTRx_DATLAT_3 (0x8U << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
8096
8097#define FMC_BTRx_ACCMOD_Pos (28U)
8098#define FMC_BTRx_ACCMOD_Msk (0x3U << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
8099#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8100#define FMC_BTRx_ACCMOD_0 (0x1U << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
8101#define FMC_BTRx_ACCMOD_1 (0x2U << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
8102
8103/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
8104#define FMC_BWTRx_ADDSET_Pos (0U)
8105#define FMC_BWTRx_ADDSET_Msk (0xFU << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
8106#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8107#define FMC_BWTRx_ADDSET_0 (0x1U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
8108#define FMC_BWTRx_ADDSET_1 (0x2U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
8109#define FMC_BWTRx_ADDSET_2 (0x4U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
8110#define FMC_BWTRx_ADDSET_3 (0x8U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
8111
8112#define FMC_BWTRx_ADDHLD_Pos (4U)
8113#define FMC_BWTRx_ADDHLD_Msk (0xFU << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
8114#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8115#define FMC_BWTRx_ADDHLD_0 (0x1U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
8116#define FMC_BWTRx_ADDHLD_1 (0x2U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
8117#define FMC_BWTRx_ADDHLD_2 (0x4U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
8118#define FMC_BWTRx_ADDHLD_3 (0x8U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
8119
8120#define FMC_BWTRx_DATAST_Pos (8U)
8121#define FMC_BWTRx_DATAST_Msk (0xFFU << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
8122#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8123#define FMC_BWTRx_DATAST_0 (0x01U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
8124#define FMC_BWTRx_DATAST_1 (0x02U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
8125#define FMC_BWTRx_DATAST_2 (0x04U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
8126#define FMC_BWTRx_DATAST_3 (0x08U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
8127#define FMC_BWTRx_DATAST_4 (0x10U << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
8128#define FMC_BWTRx_DATAST_5 (0x20U << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
8129#define FMC_BWTRx_DATAST_6 (0x40U << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
8130#define FMC_BWTRx_DATAST_7 (0x80U << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
8131
8132#define FMC_BWTRx_BUSTURN_Pos (16U)
8133#define FMC_BWTRx_BUSTURN_Msk (0xFU << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
8134#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8135#define FMC_BWTRx_BUSTURN_0 (0x1U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
8136#define FMC_BWTRx_BUSTURN_1 (0x2U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
8137#define FMC_BWTRx_BUSTURN_2 (0x4U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
8138#define FMC_BWTRx_BUSTURN_3 (0x8U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
8139
8140#define FMC_BWTRx_ACCMOD_Pos (28U)
8141#define FMC_BWTRx_ACCMOD_Msk (0x3U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
8142#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8143#define FMC_BWTRx_ACCMOD_0 (0x1U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
8144#define FMC_BWTRx_ACCMOD_1 (0x2U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
8145
8146/****************** Bit definition for FMC_PCR register ********************/
8147#define FMC_PCR_PWAITEN_Pos (1U)
8148#define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
8149#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
8150#define FMC_PCR_PBKEN_Pos (2U)
8151#define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
8152#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
8153#define FMC_PCR_PTYP_Pos (3U)
8154#define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
8155#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
8156
8157#define FMC_PCR_PWID_Pos (4U)
8158#define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
8159#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
8160#define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
8161#define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
8162
8163#define FMC_PCR_ECCEN_Pos (6U)
8164#define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
8165#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
8166
8167#define FMC_PCR_TCLR_Pos (9U)
8168#define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
8169#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
8170#define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
8171#define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
8172#define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
8173#define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
8174
8175#define FMC_PCR_TAR_Pos (13U)
8176#define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
8177#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
8178#define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
8179#define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
8180#define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
8181#define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
8182
8183#define FMC_PCR_ECCPS_Pos (17U)
8184#define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
8185#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
8186#define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
8187#define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
8188#define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
8189
8190/******************* Bit definition for FMC_SR register ********************/
8191#define FMC_SR_IRS_Pos (0U)
8192#define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
8193#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
8194#define FMC_SR_ILS_Pos (1U)
8195#define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
8196#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
8197#define FMC_SR_IFS_Pos (2U)
8198#define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
8199#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
8200#define FMC_SR_IREN_Pos (3U)
8201#define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
8202#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
8203#define FMC_SR_ILEN_Pos (4U)
8204#define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
8205#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
8206#define FMC_SR_IFEN_Pos (5U)
8207#define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
8208#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
8209#define FMC_SR_FEMPT_Pos (6U)
8210#define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
8211#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
8212
8213/****************** Bit definition for FMC_PMEM register ******************/
8214#define FMC_PMEM_MEMSET_Pos (0U)
8215#define FMC_PMEM_MEMSET_Msk (0xFFU << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
8216#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
8217#define FMC_PMEM_MEMSET_0 (0x01U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
8218#define FMC_PMEM_MEMSET_1 (0x02U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
8219#define FMC_PMEM_MEMSET_2 (0x04U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
8220#define FMC_PMEM_MEMSET_3 (0x08U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
8221#define FMC_PMEM_MEMSET_4 (0x10U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
8222#define FMC_PMEM_MEMSET_5 (0x20U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
8223#define FMC_PMEM_MEMSET_6 (0x40U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
8224#define FMC_PMEM_MEMSET_7 (0x80U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
8225
8226#define FMC_PMEM_MEMWAIT_Pos (8U)
8227#define FMC_PMEM_MEMWAIT_Msk (0xFFU << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
8228#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
8229#define FMC_PMEM_MEMWAIT_0 (0x01U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
8230#define FMC_PMEM_MEMWAIT_1 (0x02U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
8231#define FMC_PMEM_MEMWAIT_2 (0x04U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
8232#define FMC_PMEM_MEMWAIT_3 (0x08U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
8233#define FMC_PMEM_MEMWAIT_4 (0x10U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
8234#define FMC_PMEM_MEMWAIT_5 (0x20U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
8235#define FMC_PMEM_MEMWAIT_6 (0x40U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
8236#define FMC_PMEM_MEMWAIT_7 (0x80U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
8237
8238#define FMC_PMEM_MEMHOLD_Pos (16U)
8239#define FMC_PMEM_MEMHOLD_Msk (0xFFU << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
8240#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
8241#define FMC_PMEM_MEMHOLD_0 (0x01U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
8242#define FMC_PMEM_MEMHOLD_1 (0x02U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
8243#define FMC_PMEM_MEMHOLD_2 (0x04U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
8244#define FMC_PMEM_MEMHOLD_3 (0x08U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
8245#define FMC_PMEM_MEMHOLD_4 (0x10U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
8246#define FMC_PMEM_MEMHOLD_5 (0x20U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
8247#define FMC_PMEM_MEMHOLD_6 (0x40U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
8248#define FMC_PMEM_MEMHOLD_7 (0x80U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
8249
8250#define FMC_PMEM_MEMHIZ_Pos (24U)
8251#define FMC_PMEM_MEMHIZ_Msk (0xFFU << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
8252#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
8253#define FMC_PMEM_MEMHIZ_0 (0x01U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
8254#define FMC_PMEM_MEMHIZ_1 (0x02U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
8255#define FMC_PMEM_MEMHIZ_2 (0x04U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
8256#define FMC_PMEM_MEMHIZ_3 (0x08U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
8257#define FMC_PMEM_MEMHIZ_4 (0x10U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
8258#define FMC_PMEM_MEMHIZ_5 (0x20U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
8259#define FMC_PMEM_MEMHIZ_6 (0x40U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
8260#define FMC_PMEM_MEMHIZ_7 (0x80U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
8261
8262/****************** Bit definition for FMC_PATT register *******************/
8263#define FMC_PATT_ATTSET_Pos (0U)
8264#define FMC_PATT_ATTSET_Msk (0xFFU << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
8265#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
8266#define FMC_PATT_ATTSET_0 (0x01U << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
8267#define FMC_PATT_ATTSET_1 (0x02U << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
8268#define FMC_PATT_ATTSET_2 (0x04U << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
8269#define FMC_PATT_ATTSET_3 (0x08U << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
8270#define FMC_PATT_ATTSET_4 (0x10U << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
8271#define FMC_PATT_ATTSET_5 (0x20U << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
8272#define FMC_PATT_ATTSET_6 (0x40U << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
8273#define FMC_PATT_ATTSET_7 (0x80U << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
8274
8275#define FMC_PATT_ATTWAIT_Pos (8U)
8276#define FMC_PATT_ATTWAIT_Msk (0xFFU << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
8277#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
8278#define FMC_PATT_ATTWAIT_0 (0x01U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
8279#define FMC_PATT_ATTWAIT_1 (0x02U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
8280#define FMC_PATT_ATTWAIT_2 (0x04U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
8281#define FMC_PATT_ATTWAIT_3 (0x08U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
8282#define FMC_PATT_ATTWAIT_4 (0x10U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
8283#define FMC_PATT_ATTWAIT_5 (0x20U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
8284#define FMC_PATT_ATTWAIT_6 (0x40U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
8285#define FMC_PATT_ATTWAIT_7 (0x80U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
8286
8287#define FMC_PATT_ATTHOLD_Pos (16U)
8288#define FMC_PATT_ATTHOLD_Msk (0xFFU << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
8289#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
8290#define FMC_PATT_ATTHOLD_0 (0x01U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
8291#define FMC_PATT_ATTHOLD_1 (0x02U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
8292#define FMC_PATT_ATTHOLD_2 (0x04U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
8293#define FMC_PATT_ATTHOLD_3 (0x08U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
8294#define FMC_PATT_ATTHOLD_4 (0x10U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
8295#define FMC_PATT_ATTHOLD_5 (0x20U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
8296#define FMC_PATT_ATTHOLD_6 (0x40U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
8297#define FMC_PATT_ATTHOLD_7 (0x80U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
8298
8299#define FMC_PATT_ATTHIZ_Pos (24U)
8300#define FMC_PATT_ATTHIZ_Msk (0xFFU << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
8301#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
8302#define FMC_PATT_ATTHIZ_0 (0x01U << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
8303#define FMC_PATT_ATTHIZ_1 (0x02U << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
8304#define FMC_PATT_ATTHIZ_2 (0x04U << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
8305#define FMC_PATT_ATTHIZ_3 (0x08U << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
8306#define FMC_PATT_ATTHIZ_4 (0x10U << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
8307#define FMC_PATT_ATTHIZ_5 (0x20U << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
8308#define FMC_PATT_ATTHIZ_6 (0x40U << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
8309#define FMC_PATT_ATTHIZ_7 (0x80U << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
8310
8311/****************** Bit definition for FMC_ECCR register *******************/
8312#define FMC_ECCR_ECC_Pos (0U)
8313#define FMC_ECCR_ECC_Msk (0xFFFFFFFFU << FMC_ECCR_ECC_Pos) /*!< 0xFFFFFFFF */
8314#define FMC_ECCR_ECC FMC_ECCR_ECC_Msk /*!<ECC result */
8315
8316/******************************************************************************/
8317/* */
8318/* General Purpose IOs (GPIO) */
8319/* */
8320/******************************************************************************/
8321/****************** Bits definition for GPIO_MODER register *****************/
8322#define GPIO_MODER_MODE0_Pos (0U)
8323#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
8324#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
8325#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
8326#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
8327#define GPIO_MODER_MODE1_Pos (2U)
8328#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
8329#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
8330#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
8331#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
8332#define GPIO_MODER_MODE2_Pos (4U)
8333#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
8334#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
8335#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
8336#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
8337#define GPIO_MODER_MODE3_Pos (6U)
8338#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
8339#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
8340#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
8341#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
8342#define GPIO_MODER_MODE4_Pos (8U)
8343#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
8344#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
8345#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
8346#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
8347#define GPIO_MODER_MODE5_Pos (10U)
8348#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
8349#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
8350#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
8351#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
8352#define GPIO_MODER_MODE6_Pos (12U)
8353#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
8354#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
8355#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
8356#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
8357#define GPIO_MODER_MODE7_Pos (14U)
8358#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
8359#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
8360#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
8361#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
8362#define GPIO_MODER_MODE8_Pos (16U)
8363#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
8364#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
8365#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
8366#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
8367#define GPIO_MODER_MODE9_Pos (18U)
8368#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
8369#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
8370#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
8371#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
8372#define GPIO_MODER_MODE10_Pos (20U)
8373#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
8374#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
8375#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
8376#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
8377#define GPIO_MODER_MODE11_Pos (22U)
8378#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
8379#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
8380#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
8381#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
8382#define GPIO_MODER_MODE12_Pos (24U)
8383#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
8384#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
8385#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
8386#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
8387#define GPIO_MODER_MODE13_Pos (26U)
8388#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
8389#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
8390#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
8391#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
8392#define GPIO_MODER_MODE14_Pos (28U)
8393#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
8394#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
8395#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
8396#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
8397#define GPIO_MODER_MODE15_Pos (30U)
8398#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
8399#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
8400#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
8401#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
8402
8403/* Legacy defines */
8404#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
8405#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
8406#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
8407#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
8408#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
8409#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
8410#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
8411#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
8412#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
8413#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
8414#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
8415#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
8416#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
8417#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
8418#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
8419#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
8420#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
8421#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
8422#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
8423#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
8424#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
8425#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
8426#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
8427#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
8428#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
8429#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
8430#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
8431#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
8432#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
8433#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
8434#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
8435#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
8436#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
8437#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
8438#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
8439#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
8440#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
8441#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
8442#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
8443#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
8444#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
8445#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
8446#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
8447#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
8448#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
8449#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
8450#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
8451#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
8452
8453/****************** Bits definition for GPIO_OTYPER register ****************/
8454#define GPIO_OTYPER_OT0_Pos (0U)
8455#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
8456#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8457#define GPIO_OTYPER_OT1_Pos (1U)
8458#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
8459#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8460#define GPIO_OTYPER_OT2_Pos (2U)
8461#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
8462#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8463#define GPIO_OTYPER_OT3_Pos (3U)
8464#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
8465#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8466#define GPIO_OTYPER_OT4_Pos (4U)
8467#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
8468#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8469#define GPIO_OTYPER_OT5_Pos (5U)
8470#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
8471#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8472#define GPIO_OTYPER_OT6_Pos (6U)
8473#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
8474#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8475#define GPIO_OTYPER_OT7_Pos (7U)
8476#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
8477#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8478#define GPIO_OTYPER_OT8_Pos (8U)
8479#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
8480#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8481#define GPIO_OTYPER_OT9_Pos (9U)
8482#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
8483#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8484#define GPIO_OTYPER_OT10_Pos (10U)
8485#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
8486#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8487#define GPIO_OTYPER_OT11_Pos (11U)
8488#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
8489#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8490#define GPIO_OTYPER_OT12_Pos (12U)
8491#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
8492#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8493#define GPIO_OTYPER_OT13_Pos (13U)
8494#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
8495#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8496#define GPIO_OTYPER_OT14_Pos (14U)
8497#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
8498#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8499#define GPIO_OTYPER_OT15_Pos (15U)
8500#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
8501#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8502
8503/* Legacy defines */
8504#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8505#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8506#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8507#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8508#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8509#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8510#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8511#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8512#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8513#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8514#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8515#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
8516#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
8517#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
8518#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
8519#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
8520
8521/****************** Bits definition for GPIO_OSPEEDR register ***************/
8522#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
8523#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
8524#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
8525#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
8526#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
8527#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
8528#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
8529#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
8530#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
8531#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
8532#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
8533#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
8534#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
8535#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
8536#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
8537#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
8538#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
8539#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
8540#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
8541#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
8542#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
8543#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
8544#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
8545#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
8546#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
8547#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
8548#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
8549#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
8550#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
8551#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
8552#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
8553#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
8554#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
8555#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
8556#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
8557#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
8558#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
8559#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
8560#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
8561#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
8562#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
8563#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
8564#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
8565#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
8566#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
8567#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
8568#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
8569#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
8570#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
8571#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
8572#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
8573#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
8574#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
8575#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
8576#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
8577#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
8578#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
8579#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
8580#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
8581#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
8582#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
8583#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
8584#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
8585#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
8586#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
8587#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
8588#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
8589#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
8590#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
8591#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
8592#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
8593#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
8594#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
8595#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
8596#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
8597#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
8598#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
8599#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
8600#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
8601#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
8602
8603/* Legacy defines */
8604#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
8605#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
8606#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
8607#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
8608#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
8609#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
8610#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
8611#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
8612#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
8613#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
8614#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
8615#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
8616#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
8617#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
8618#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
8619#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
8620#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
8621#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
8622#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
8623#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
8624#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
8625#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
8626#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
8627#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
8628#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
8629#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
8630#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
8631#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
8632#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
8633#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
8634#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
8635#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
8636#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
8637#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
8638#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
8639#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
8640#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
8641#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
8642#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
8643#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
8644#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
8645#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
8646#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
8647#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
8648#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
8649#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
8650#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
8651#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
8652
8653/****************** Bits definition for GPIO_PUPDR register *****************/
8654#define GPIO_PUPDR_PUPD0_Pos (0U)
8655#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
8656#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
8657#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
8658#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
8659#define GPIO_PUPDR_PUPD1_Pos (2U)
8660#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
8661#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
8662#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
8663#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
8664#define GPIO_PUPDR_PUPD2_Pos (4U)
8665#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
8666#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
8667#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
8668#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
8669#define GPIO_PUPDR_PUPD3_Pos (6U)
8670#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
8671#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
8672#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
8673#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
8674#define GPIO_PUPDR_PUPD4_Pos (8U)
8675#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
8676#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
8677#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
8678#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
8679#define GPIO_PUPDR_PUPD5_Pos (10U)
8680#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
8681#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
8682#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
8683#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
8684#define GPIO_PUPDR_PUPD6_Pos (12U)
8685#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
8686#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
8687#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
8688#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
8689#define GPIO_PUPDR_PUPD7_Pos (14U)
8690#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
8691#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
8692#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
8693#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
8694#define GPIO_PUPDR_PUPD8_Pos (16U)
8695#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
8696#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
8697#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
8698#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
8699#define GPIO_PUPDR_PUPD9_Pos (18U)
8700#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
8701#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
8702#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
8703#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
8704#define GPIO_PUPDR_PUPD10_Pos (20U)
8705#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
8706#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
8707#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
8708#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
8709#define GPIO_PUPDR_PUPD11_Pos (22U)
8710#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
8711#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
8712#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
8713#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
8714#define GPIO_PUPDR_PUPD12_Pos (24U)
8715#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
8716#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
8717#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
8718#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
8719#define GPIO_PUPDR_PUPD13_Pos (26U)
8720#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
8721#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
8722#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
8723#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
8724#define GPIO_PUPDR_PUPD14_Pos (28U)
8725#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
8726#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
8727#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
8728#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
8729#define GPIO_PUPDR_PUPD15_Pos (30U)
8730#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
8731#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
8732#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
8733#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
8734
8735/* Legacy defines */
8736#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
8737#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
8738#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
8739#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
8740#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
8741#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
8742#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
8743#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
8744#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
8745#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
8746#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
8747#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
8748#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
8749#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
8750#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
8751#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
8752#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
8753#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
8754#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
8755#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
8756#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
8757#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
8758#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
8759#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
8760#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
8761#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
8762#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
8763#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
8764#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
8765#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
8766#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
8767#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
8768#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
8769#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
8770#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
8771#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
8772#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
8773#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
8774#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
8775#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
8776#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
8777#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
8778#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
8779#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
8780#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
8781#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
8782#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
8783#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
8784
8785/****************** Bits definition for GPIO_IDR register *******************/
8786#define GPIO_IDR_ID0_Pos (0U)
8787#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
8788#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8789#define GPIO_IDR_ID1_Pos (1U)
8790#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
8791#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8792#define GPIO_IDR_ID2_Pos (2U)
8793#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
8794#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8795#define GPIO_IDR_ID3_Pos (3U)
8796#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
8797#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8798#define GPIO_IDR_ID4_Pos (4U)
8799#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
8800#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8801#define GPIO_IDR_ID5_Pos (5U)
8802#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
8803#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8804#define GPIO_IDR_ID6_Pos (6U)
8805#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
8806#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8807#define GPIO_IDR_ID7_Pos (7U)
8808#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
8809#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8810#define GPIO_IDR_ID8_Pos (8U)
8811#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
8812#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8813#define GPIO_IDR_ID9_Pos (9U)
8814#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
8815#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8816#define GPIO_IDR_ID10_Pos (10U)
8817#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
8818#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8819#define GPIO_IDR_ID11_Pos (11U)
8820#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
8821#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8822#define GPIO_IDR_ID12_Pos (12U)
8823#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
8824#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8825#define GPIO_IDR_ID13_Pos (13U)
8826#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
8827#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8828#define GPIO_IDR_ID14_Pos (14U)
8829#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
8830#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8831#define GPIO_IDR_ID15_Pos (15U)
8832#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
8833#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8834
8835/* Legacy defines */
8836#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8837#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8838#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8839#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8840#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8841#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8842#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8843#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8844#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8845#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8846#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8847#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8848#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8849#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8850#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8851#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8852
8853/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
8854#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
8855#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
8856#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
8857#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
8858#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
8859#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
8860#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
8861#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
8862#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
8863#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
8864#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
8865#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
8866#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
8867#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
8868#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
8869#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
8870
8871/****************** Bits definition for GPIO_ODR register *******************/
8872#define GPIO_ODR_OD0_Pos (0U)
8873#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
8874#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8875#define GPIO_ODR_OD1_Pos (1U)
8876#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
8877#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8878#define GPIO_ODR_OD2_Pos (2U)
8879#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
8880#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8881#define GPIO_ODR_OD3_Pos (3U)
8882#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
8883#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8884#define GPIO_ODR_OD4_Pos (4U)
8885#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
8886#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8887#define GPIO_ODR_OD5_Pos (5U)
8888#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
8889#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8890#define GPIO_ODR_OD6_Pos (6U)
8891#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
8892#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8893#define GPIO_ODR_OD7_Pos (7U)
8894#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
8895#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8896#define GPIO_ODR_OD8_Pos (8U)
8897#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
8898#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8899#define GPIO_ODR_OD9_Pos (9U)
8900#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
8901#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8902#define GPIO_ODR_OD10_Pos (10U)
8903#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
8904#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8905#define GPIO_ODR_OD11_Pos (11U)
8906#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
8907#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8908#define GPIO_ODR_OD12_Pos (12U)
8909#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
8910#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8911#define GPIO_ODR_OD13_Pos (13U)
8912#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
8913#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8914#define GPIO_ODR_OD14_Pos (14U)
8915#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
8916#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8917#define GPIO_ODR_OD15_Pos (15U)
8918#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
8919#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8920
8921/* Legacy defines */
8922#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8923#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8924#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8925#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8926#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8927#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8928#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8929#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8930#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8931#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8932#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8933#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8934#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8935#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8936#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8937#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8938
8939/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
8940#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
8941#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
8942#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
8943#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
8944#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
8945#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
8946#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
8947#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
8948#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
8949#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
8950#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
8951#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
8952#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
8953#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
8954#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
8955#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
8956
8957/****************** Bits definition for GPIO_BSRR register ******************/
8958#define GPIO_BSRR_BS0_Pos (0U)
8959#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
8960#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8961#define GPIO_BSRR_BS1_Pos (1U)
8962#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
8963#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8964#define GPIO_BSRR_BS2_Pos (2U)
8965#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
8966#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8967#define GPIO_BSRR_BS3_Pos (3U)
8968#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
8969#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8970#define GPIO_BSRR_BS4_Pos (4U)
8971#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
8972#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8973#define GPIO_BSRR_BS5_Pos (5U)
8974#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
8975#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8976#define GPIO_BSRR_BS6_Pos (6U)
8977#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
8978#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8979#define GPIO_BSRR_BS7_Pos (7U)
8980#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
8981#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8982#define GPIO_BSRR_BS8_Pos (8U)
8983#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
8984#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8985#define GPIO_BSRR_BS9_Pos (9U)
8986#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
8987#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8988#define GPIO_BSRR_BS10_Pos (10U)
8989#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
8990#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8991#define GPIO_BSRR_BS11_Pos (11U)
8992#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
8993#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8994#define GPIO_BSRR_BS12_Pos (12U)
8995#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
8996#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8997#define GPIO_BSRR_BS13_Pos (13U)
8998#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
8999#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
9000#define GPIO_BSRR_BS14_Pos (14U)
9001#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
9002#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
9003#define GPIO_BSRR_BS15_Pos (15U)
9004#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
9005#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
9006#define GPIO_BSRR_BR0_Pos (16U)
9007#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
9008#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
9009#define GPIO_BSRR_BR1_Pos (17U)
9010#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
9011#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
9012#define GPIO_BSRR_BR2_Pos (18U)
9013#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
9014#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
9015#define GPIO_BSRR_BR3_Pos (19U)
9016#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
9017#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
9018#define GPIO_BSRR_BR4_Pos (20U)
9019#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
9020#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
9021#define GPIO_BSRR_BR5_Pos (21U)
9022#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
9023#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
9024#define GPIO_BSRR_BR6_Pos (22U)
9025#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
9026#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
9027#define GPIO_BSRR_BR7_Pos (23U)
9028#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
9029#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
9030#define GPIO_BSRR_BR8_Pos (24U)
9031#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
9032#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
9033#define GPIO_BSRR_BR9_Pos (25U)
9034#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
9035#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
9036#define GPIO_BSRR_BR10_Pos (26U)
9037#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
9038#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
9039#define GPIO_BSRR_BR11_Pos (27U)
9040#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
9041#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
9042#define GPIO_BSRR_BR12_Pos (28U)
9043#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
9044#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
9045#define GPIO_BSRR_BR13_Pos (29U)
9046#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
9047#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
9048#define GPIO_BSRR_BR14_Pos (30U)
9049#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
9050#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
9051#define GPIO_BSRR_BR15_Pos (31U)
9052#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
9053#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
9054
9055/* Legacy defines */
9056#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
9057#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
9058#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
9059#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
9060#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
9061#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
9062#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
9063#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
9064#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
9065#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
9066#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
9067#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
9068#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
9069#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
9070#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
9071#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
9072#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
9073#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
9074#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
9075#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
9076#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
9077#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
9078#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
9079#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
9080#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
9081#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
9082#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
9083#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
9084#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
9085#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
9086#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
9087#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
9088
9089/****************** Bit definition for GPIO_LCKR register *********************/
9090#define GPIO_LCKR_LCK0_Pos (0U)
9091#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
9092#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
9093#define GPIO_LCKR_LCK1_Pos (1U)
9094#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
9095#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
9096#define GPIO_LCKR_LCK2_Pos (2U)
9097#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
9098#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
9099#define GPIO_LCKR_LCK3_Pos (3U)
9100#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
9101#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
9102#define GPIO_LCKR_LCK4_Pos (4U)
9103#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
9104#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
9105#define GPIO_LCKR_LCK5_Pos (5U)
9106#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
9107#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
9108#define GPIO_LCKR_LCK6_Pos (6U)
9109#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
9110#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
9111#define GPIO_LCKR_LCK7_Pos (7U)
9112#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
9113#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
9114#define GPIO_LCKR_LCK8_Pos (8U)
9115#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
9116#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
9117#define GPIO_LCKR_LCK9_Pos (9U)
9118#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
9119#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
9120#define GPIO_LCKR_LCK10_Pos (10U)
9121#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
9122#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
9123#define GPIO_LCKR_LCK11_Pos (11U)
9124#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
9125#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
9126#define GPIO_LCKR_LCK12_Pos (12U)
9127#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
9128#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
9129#define GPIO_LCKR_LCK13_Pos (13U)
9130#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
9131#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
9132#define GPIO_LCKR_LCK14_Pos (14U)
9133#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
9134#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
9135#define GPIO_LCKR_LCK15_Pos (15U)
9136#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
9137#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
9138#define GPIO_LCKR_LCKK_Pos (16U)
9139#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
9140#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
9141
9142/****************** Bit definition for GPIO_AFRL register *********************/
9143#define GPIO_AFRL_AFSEL0_Pos (0U)
9144#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
9145#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
9146#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
9147#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
9148#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
9149#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
9150#define GPIO_AFRL_AFSEL1_Pos (4U)
9151#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
9152#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
9153#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
9154#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
9155#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
9156#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
9157#define GPIO_AFRL_AFSEL2_Pos (8U)
9158#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
9159#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
9160#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
9161#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
9162#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
9163#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
9164#define GPIO_AFRL_AFSEL3_Pos (12U)
9165#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
9166#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
9167#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
9168#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
9169#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
9170#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
9171#define GPIO_AFRL_AFSEL4_Pos (16U)
9172#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
9173#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
9174#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
9175#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
9176#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
9177#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
9178#define GPIO_AFRL_AFSEL5_Pos (20U)
9179#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
9180#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
9181#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
9182#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
9183#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
9184#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
9185#define GPIO_AFRL_AFSEL6_Pos (24U)
9186#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
9187#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
9188#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
9189#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
9190#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
9191#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
9192#define GPIO_AFRL_AFSEL7_Pos (28U)
9193#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
9194#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
9195#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
9196#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
9197#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
9198#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
9199
9200/* Legacy defines */
9201#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
9202#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
9203#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
9204#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
9205#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
9206#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
9207#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
9208#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
9209
9210/****************** Bit definition for GPIO_AFRH register *********************/
9211#define GPIO_AFRH_AFSEL8_Pos (0U)
9212#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
9213#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
9214#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
9215#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
9216#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
9217#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
9218#define GPIO_AFRH_AFSEL9_Pos (4U)
9219#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
9220#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
9221#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
9222#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
9223#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
9224#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
9225#define GPIO_AFRH_AFSEL10_Pos (8U)
9226#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
9227#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
9228#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
9229#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
9230#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
9231#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
9232#define GPIO_AFRH_AFSEL11_Pos (12U)
9233#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
9234#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
9235#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
9236#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
9237#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
9238#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
9239#define GPIO_AFRH_AFSEL12_Pos (16U)
9240#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
9241#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
9242#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
9243#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
9244#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
9245#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
9246#define GPIO_AFRH_AFSEL13_Pos (20U)
9247#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
9248#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
9249#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
9250#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
9251#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
9252#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
9253#define GPIO_AFRH_AFSEL14_Pos (24U)
9254#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
9255#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
9256#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
9257#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
9258#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
9259#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
9260#define GPIO_AFRH_AFSEL15_Pos (28U)
9261#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
9262#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
9263#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
9264#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
9265#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
9266#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
9267
9268/* Legacy defines */
9269#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
9270#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
9271#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
9272#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
9273#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
9274#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
9275#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
9276#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
9277
9278/****************** Bits definition for GPIO_BRR register ******************/
9279#define GPIO_BRR_BR0_Pos (0U)
9280#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
9281#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
9282#define GPIO_BRR_BR1_Pos (1U)
9283#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
9284#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
9285#define GPIO_BRR_BR2_Pos (2U)
9286#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
9287#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
9288#define GPIO_BRR_BR3_Pos (3U)
9289#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
9290#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
9291#define GPIO_BRR_BR4_Pos (4U)
9292#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
9293#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
9294#define GPIO_BRR_BR5_Pos (5U)
9295#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
9296#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
9297#define GPIO_BRR_BR6_Pos (6U)
9298#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
9299#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
9300#define GPIO_BRR_BR7_Pos (7U)
9301#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
9302#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
9303#define GPIO_BRR_BR8_Pos (8U)
9304#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
9305#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
9306#define GPIO_BRR_BR9_Pos (9U)
9307#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
9308#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
9309#define GPIO_BRR_BR10_Pos (10U)
9310#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
9311#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
9312#define GPIO_BRR_BR11_Pos (11U)
9313#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
9314#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
9315#define GPIO_BRR_BR12_Pos (12U)
9316#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
9317#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
9318#define GPIO_BRR_BR13_Pos (13U)
9319#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
9320#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
9321#define GPIO_BRR_BR14_Pos (14U)
9322#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
9323#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
9324#define GPIO_BRR_BR15_Pos (15U)
9325#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
9326#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
9327
9328/* Legacy defines */
9329#define GPIO_BRR_BR_0 GPIO_BRR_BR0
9330#define GPIO_BRR_BR_1 GPIO_BRR_BR1
9331#define GPIO_BRR_BR_2 GPIO_BRR_BR2
9332#define GPIO_BRR_BR_3 GPIO_BRR_BR3
9333#define GPIO_BRR_BR_4 GPIO_BRR_BR4
9334#define GPIO_BRR_BR_5 GPIO_BRR_BR5
9335#define GPIO_BRR_BR_6 GPIO_BRR_BR6
9336#define GPIO_BRR_BR_7 GPIO_BRR_BR7
9337#define GPIO_BRR_BR_8 GPIO_BRR_BR8
9338#define GPIO_BRR_BR_9 GPIO_BRR_BR9
9339#define GPIO_BRR_BR_10 GPIO_BRR_BR10
9340#define GPIO_BRR_BR_11 GPIO_BRR_BR11
9341#define GPIO_BRR_BR_12 GPIO_BRR_BR12
9342#define GPIO_BRR_BR_13 GPIO_BRR_BR13
9343#define GPIO_BRR_BR_14 GPIO_BRR_BR14
9344#define GPIO_BRR_BR_15 GPIO_BRR_BR15
9345
9346
9347/****************** Bits definition for GPIO_ASCR register *******************/
9348#define GPIO_ASCR_ASC0_Pos (0U)
9349#define GPIO_ASCR_ASC0_Msk (0x1U << GPIO_ASCR_ASC0_Pos) /*!< 0x00000001 */
9350#define GPIO_ASCR_ASC0 GPIO_ASCR_ASC0_Msk
9351#define GPIO_ASCR_ASC1_Pos (1U)
9352#define GPIO_ASCR_ASC1_Msk (0x1U << GPIO_ASCR_ASC1_Pos) /*!< 0x00000002 */
9353#define GPIO_ASCR_ASC1 GPIO_ASCR_ASC1_Msk
9354#define GPIO_ASCR_ASC2_Pos (2U)
9355#define GPIO_ASCR_ASC2_Msk (0x1U << GPIO_ASCR_ASC2_Pos) /*!< 0x00000004 */
9356#define GPIO_ASCR_ASC2 GPIO_ASCR_ASC2_Msk
9357#define GPIO_ASCR_ASC3_Pos (3U)
9358#define GPIO_ASCR_ASC3_Msk (0x1U << GPIO_ASCR_ASC3_Pos) /*!< 0x00000008 */
9359#define GPIO_ASCR_ASC3 GPIO_ASCR_ASC3_Msk
9360#define GPIO_ASCR_ASC4_Pos (4U)
9361#define GPIO_ASCR_ASC4_Msk (0x1U << GPIO_ASCR_ASC4_Pos) /*!< 0x00000010 */
9362#define GPIO_ASCR_ASC4 GPIO_ASCR_ASC4_Msk
9363#define GPIO_ASCR_ASC5_Pos (5U)
9364#define GPIO_ASCR_ASC5_Msk (0x1U << GPIO_ASCR_ASC5_Pos) /*!< 0x00000020 */
9365#define GPIO_ASCR_ASC5 GPIO_ASCR_ASC5_Msk
9366#define GPIO_ASCR_ASC6_Pos (6U)
9367#define GPIO_ASCR_ASC6_Msk (0x1U << GPIO_ASCR_ASC6_Pos) /*!< 0x00000040 */
9368#define GPIO_ASCR_ASC6 GPIO_ASCR_ASC6_Msk
9369#define GPIO_ASCR_ASC7_Pos (7U)
9370#define GPIO_ASCR_ASC7_Msk (0x1U << GPIO_ASCR_ASC7_Pos) /*!< 0x00000080 */
9371#define GPIO_ASCR_ASC7 GPIO_ASCR_ASC7_Msk
9372#define GPIO_ASCR_ASC8_Pos (8U)
9373#define GPIO_ASCR_ASC8_Msk (0x1U << GPIO_ASCR_ASC8_Pos) /*!< 0x00000100 */
9374#define GPIO_ASCR_ASC8 GPIO_ASCR_ASC8_Msk
9375#define GPIO_ASCR_ASC9_Pos (9U)
9376#define GPIO_ASCR_ASC9_Msk (0x1U << GPIO_ASCR_ASC9_Pos) /*!< 0x00000200 */
9377#define GPIO_ASCR_ASC9 GPIO_ASCR_ASC9_Msk
9378#define GPIO_ASCR_ASC10_Pos (10U)
9379#define GPIO_ASCR_ASC10_Msk (0x1U << GPIO_ASCR_ASC10_Pos) /*!< 0x00000400 */
9380#define GPIO_ASCR_ASC10 GPIO_ASCR_ASC10_Msk
9381#define GPIO_ASCR_ASC11_Pos (11U)
9382#define GPIO_ASCR_ASC11_Msk (0x1U << GPIO_ASCR_ASC11_Pos) /*!< 0x00000800 */
9383#define GPIO_ASCR_ASC11 GPIO_ASCR_ASC11_Msk
9384#define GPIO_ASCR_ASC12_Pos (12U)
9385#define GPIO_ASCR_ASC12_Msk (0x1U << GPIO_ASCR_ASC12_Pos) /*!< 0x00001000 */
9386#define GPIO_ASCR_ASC12 GPIO_ASCR_ASC12_Msk
9387#define GPIO_ASCR_ASC13_Pos (13U)
9388#define GPIO_ASCR_ASC13_Msk (0x1U << GPIO_ASCR_ASC13_Pos) /*!< 0x00002000 */
9389#define GPIO_ASCR_ASC13 GPIO_ASCR_ASC13_Msk
9390#define GPIO_ASCR_ASC14_Pos (14U)
9391#define GPIO_ASCR_ASC14_Msk (0x1U << GPIO_ASCR_ASC14_Pos) /*!< 0x00004000 */
9392#define GPIO_ASCR_ASC14 GPIO_ASCR_ASC14_Msk
9393#define GPIO_ASCR_ASC15_Pos (15U)
9394#define GPIO_ASCR_ASC15_Msk (0x1U << GPIO_ASCR_ASC15_Pos) /*!< 0x00008000 */
9395#define GPIO_ASCR_ASC15 GPIO_ASCR_ASC15_Msk
9396
9397/* Legacy defines */
9398#define GPIO_ASCR_EN_0 GPIO_ASCR_ASC0
9399#define GPIO_ASCR_EN_1 GPIO_ASCR_ASC1
9400#define GPIO_ASCR_EN_2 GPIO_ASCR_ASC2
9401#define GPIO_ASCR_EN_3 GPIO_ASCR_ASC3
9402#define GPIO_ASCR_EN_4 GPIO_ASCR_ASC4
9403#define GPIO_ASCR_EN_5 GPIO_ASCR_ASC5
9404#define GPIO_ASCR_EN_6 GPIO_ASCR_ASC6
9405#define GPIO_ASCR_EN_7 GPIO_ASCR_ASC7
9406#define GPIO_ASCR_EN_8 GPIO_ASCR_ASC8
9407#define GPIO_ASCR_EN_9 GPIO_ASCR_ASC9
9408#define GPIO_ASCR_EN_10 GPIO_ASCR_ASC10
9409#define GPIO_ASCR_EN_11 GPIO_ASCR_ASC11
9410#define GPIO_ASCR_EN_12 GPIO_ASCR_ASC12
9411#define GPIO_ASCR_EN_13 GPIO_ASCR_ASC13
9412#define GPIO_ASCR_EN_14 GPIO_ASCR_ASC14
9413#define GPIO_ASCR_EN_15 GPIO_ASCR_ASC15
9414
9415/******************************************************************************/
9416/* */
9417/* Inter-integrated Circuit Interface (I2C) */
9418/* */
9419/******************************************************************************/
9420/******************* Bit definition for I2C_CR1 register *******************/
9421#define I2C_CR1_PE_Pos (0U)
9422#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
9423#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
9424#define I2C_CR1_TXIE_Pos (1U)
9425#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
9426#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
9427#define I2C_CR1_RXIE_Pos (2U)
9428#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
9429#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
9430#define I2C_CR1_ADDRIE_Pos (3U)
9431#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
9432#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
9433#define I2C_CR1_NACKIE_Pos (4U)
9434#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
9435#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
9436#define I2C_CR1_STOPIE_Pos (5U)
9437#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
9438#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
9439#define I2C_CR1_TCIE_Pos (6U)
9440#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
9441#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
9442#define I2C_CR1_ERRIE_Pos (7U)
9443#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
9444#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
9445#define I2C_CR1_DNF_Pos (8U)
9446#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
9447#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
9448#define I2C_CR1_ANFOFF_Pos (12U)
9449#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
9450#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
9451#define I2C_CR1_SWRST_Pos (13U)
9452#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
9453#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
9454#define I2C_CR1_TXDMAEN_Pos (14U)
9455#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
9456#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
9457#define I2C_CR1_RXDMAEN_Pos (15U)
9458#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
9459#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
9460#define I2C_CR1_SBC_Pos (16U)
9461#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
9462#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
9463#define I2C_CR1_NOSTRETCH_Pos (17U)
9464#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
9465#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
9466#define I2C_CR1_WUPEN_Pos (18U)
9467#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
9468#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
9469#define I2C_CR1_GCEN_Pos (19U)
9470#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
9471#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
9472#define I2C_CR1_SMBHEN_Pos (20U)
9473#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
9474#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
9475#define I2C_CR1_SMBDEN_Pos (21U)
9476#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
9477#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
9478#define I2C_CR1_ALERTEN_Pos (22U)
9479#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
9480#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
9481#define I2C_CR1_PECEN_Pos (23U)
9482#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
9483#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
9484
9485/****************** Bit definition for I2C_CR2 register ********************/
9486#define I2C_CR2_SADD_Pos (0U)
9487#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
9488#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
9489#define I2C_CR2_RD_WRN_Pos (10U)
9490#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
9491#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
9492#define I2C_CR2_ADD10_Pos (11U)
9493#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
9494#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
9495#define I2C_CR2_HEAD10R_Pos (12U)
9496#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
9497#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
9498#define I2C_CR2_START_Pos (13U)
9499#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
9500#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
9501#define I2C_CR2_STOP_Pos (14U)
9502#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
9503#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
9504#define I2C_CR2_NACK_Pos (15U)
9505#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
9506#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
9507#define I2C_CR2_NBYTES_Pos (16U)
9508#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
9509#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
9510#define I2C_CR2_RELOAD_Pos (24U)
9511#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
9512#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
9513#define I2C_CR2_AUTOEND_Pos (25U)
9514#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
9515#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
9516#define I2C_CR2_PECBYTE_Pos (26U)
9517#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
9518#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
9519
9520/******************* Bit definition for I2C_OAR1 register ******************/
9521#define I2C_OAR1_OA1_Pos (0U)
9522#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
9523#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
9524#define I2C_OAR1_OA1MODE_Pos (10U)
9525#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
9526#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
9527#define I2C_OAR1_OA1EN_Pos (15U)
9528#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
9529#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
9530
9531/******************* Bit definition for I2C_OAR2 register ******************/
9532#define I2C_OAR2_OA2_Pos (1U)
9533#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
9534#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
9535#define I2C_OAR2_OA2MSK_Pos (8U)
9536#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
9537#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
9538#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
9539#define I2C_OAR2_OA2MASK01_Pos (8U)
9540#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
9541#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
9542#define I2C_OAR2_OA2MASK02_Pos (9U)
9543#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
9544#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
9545#define I2C_OAR2_OA2MASK03_Pos (8U)
9546#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
9547#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
9548#define I2C_OAR2_OA2MASK04_Pos (10U)
9549#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
9550#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
9551#define I2C_OAR2_OA2MASK05_Pos (8U)
9552#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
9553#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
9554#define I2C_OAR2_OA2MASK06_Pos (9U)
9555#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
9556#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
9557#define I2C_OAR2_OA2MASK07_Pos (8U)
9558#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
9559#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
9560#define I2C_OAR2_OA2EN_Pos (15U)
9561#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
9562#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
9563
9564/******************* Bit definition for I2C_TIMINGR register *******************/
9565#define I2C_TIMINGR_SCLL_Pos (0U)
9566#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
9567#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
9568#define I2C_TIMINGR_SCLH_Pos (8U)
9569#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
9570#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
9571#define I2C_TIMINGR_SDADEL_Pos (16U)
9572#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
9573#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
9574#define I2C_TIMINGR_SCLDEL_Pos (20U)
9575#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
9576#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
9577#define I2C_TIMINGR_PRESC_Pos (28U)
9578#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
9579#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
9580
9581/******************* Bit definition for I2C_TIMEOUTR register *******************/
9582#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
9583#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
9584#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
9585#define I2C_TIMEOUTR_TIDLE_Pos (12U)
9586#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
9587#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
9588#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
9589#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
9590#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
9591#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
9592#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
9593#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
9594#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
9595#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
9596#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
9597
9598/****************** Bit definition for I2C_ISR register *********************/
9599#define I2C_ISR_TXE_Pos (0U)
9600#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
9601#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
9602#define I2C_ISR_TXIS_Pos (1U)
9603#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
9604#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
9605#define I2C_ISR_RXNE_Pos (2U)
9606#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
9607#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
9608#define I2C_ISR_ADDR_Pos (3U)
9609#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
9610#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
9611#define I2C_ISR_NACKF_Pos (4U)
9612#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
9613#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
9614#define I2C_ISR_STOPF_Pos (5U)
9615#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
9616#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
9617#define I2C_ISR_TC_Pos (6U)
9618#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
9619#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
9620#define I2C_ISR_TCR_Pos (7U)
9621#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
9622#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
9623#define I2C_ISR_BERR_Pos (8U)
9624#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
9625#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
9626#define I2C_ISR_ARLO_Pos (9U)
9627#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
9628#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
9629#define I2C_ISR_OVR_Pos (10U)
9630#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
9631#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
9632#define I2C_ISR_PECERR_Pos (11U)
9633#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
9634#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
9635#define I2C_ISR_TIMEOUT_Pos (12U)
9636#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
9637#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
9638#define I2C_ISR_ALERT_Pos (13U)
9639#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
9640#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
9641#define I2C_ISR_BUSY_Pos (15U)
9642#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
9643#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
9644#define I2C_ISR_DIR_Pos (16U)
9645#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
9646#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
9647#define I2C_ISR_ADDCODE_Pos (17U)
9648#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
9649#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
9650
9651/****************** Bit definition for I2C_ICR register *********************/
9652#define I2C_ICR_ADDRCF_Pos (3U)
9653#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
9654#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
9655#define I2C_ICR_NACKCF_Pos (4U)
9656#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
9657#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
9658#define I2C_ICR_STOPCF_Pos (5U)
9659#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
9660#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
9661#define I2C_ICR_BERRCF_Pos (8U)
9662#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
9663#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
9664#define I2C_ICR_ARLOCF_Pos (9U)
9665#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
9666#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
9667#define I2C_ICR_OVRCF_Pos (10U)
9668#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
9669#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
9670#define I2C_ICR_PECCF_Pos (11U)
9671#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
9672#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
9673#define I2C_ICR_TIMOUTCF_Pos (12U)
9674#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
9675#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
9676#define I2C_ICR_ALERTCF_Pos (13U)
9677#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
9678#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
9679
9680/****************** Bit definition for I2C_PECR register *********************/
9681#define I2C_PECR_PEC_Pos (0U)
9682#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
9683#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
9684
9685/****************** Bit definition for I2C_RXDR register *********************/
9686#define I2C_RXDR_RXDATA_Pos (0U)
9687#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
9688#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
9689
9690/****************** Bit definition for I2C_TXDR register *********************/
9691#define I2C_TXDR_TXDATA_Pos (0U)
9692#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
9693#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
9694
9695/******************************************************************************/
9696/* */
9697/* Independent WATCHDOG */
9698/* */
9699/******************************************************************************/
9700/******************* Bit definition for IWDG_KR register ********************/
9701#define IWDG_KR_KEY_Pos (0U)
9702#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
9703#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
9704
9705/******************* Bit definition for IWDG_PR register ********************/
9706#define IWDG_PR_PR_Pos (0U)
9707#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
9708#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
9709#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
9710#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
9711#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
9712
9713/******************* Bit definition for IWDG_RLR register *******************/
9714#define IWDG_RLR_RL_Pos (0U)
9715#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
9716#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
9717
9718/******************* Bit definition for IWDG_SR register ********************/
9719#define IWDG_SR_PVU_Pos (0U)
9720#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
9721#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
9722#define IWDG_SR_RVU_Pos (1U)
9723#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
9724#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
9725#define IWDG_SR_WVU_Pos (2U)
9726#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
9727#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
9728
9729/******************* Bit definition for IWDG_KR register ********************/
9730#define IWDG_WINR_WIN_Pos (0U)
9731#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
9732#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
9733
9734/******************************************************************************/
9735/* */
9736/* Firewall */
9737/* */
9738/******************************************************************************/
9739
9740/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
9741#define FW_CSSA_ADD_Pos (8U)
9742#define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
9743#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
9744#define FW_CSL_LENG_Pos (8U)
9745#define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
9746#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
9747#define FW_NVDSSA_ADD_Pos (8U)
9748#define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
9749#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
9750#define FW_NVDSL_LENG_Pos (8U)
9751#define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
9752#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
9753#define FW_VDSSA_ADD_Pos (6U)
9754#define FW_VDSSA_ADD_Msk (0x7FFU << FW_VDSSA_ADD_Pos) /*!< 0x0001FFC0 */
9755#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
9756#define FW_VDSL_LENG_Pos (6U)
9757#define FW_VDSL_LENG_Msk (0x7FFU << FW_VDSL_LENG_Pos) /*!< 0x0001FFC0 */
9758#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
9759
9760/**************************Bit definition for CR register *********************/
9761#define FW_CR_FPA_Pos (0U)
9762#define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
9763#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
9764#define FW_CR_VDS_Pos (1U)
9765#define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
9766#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
9767#define FW_CR_VDE_Pos (2U)
9768#define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
9769#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
9770
9771/******************************************************************************/
9772/* */
9773/* Power Control */
9774/* */
9775/******************************************************************************/
9776
9777/******************** Bit definition for PWR_CR1 register ********************/
9778
9779#define PWR_CR1_LPR_Pos (14U)
9780#define PWR_CR1_LPR_Msk (0x1U << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
9781#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
9782#define PWR_CR1_VOS_Pos (9U)
9783#define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
9784#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
9785#define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
9786#define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
9787#define PWR_CR1_DBP_Pos (8U)
9788#define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
9789#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
9790#define PWR_CR1_LPMS_Pos (0U)
9791#define PWR_CR1_LPMS_Msk (0x7U << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
9792#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
9793#define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
9794#define PWR_CR1_LPMS_STOP1_Pos (0U)
9795#define PWR_CR1_LPMS_STOP1_Msk (0x1U << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
9796#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
9797#define PWR_CR1_LPMS_STOP2_Pos (1U)
9798#define PWR_CR1_LPMS_STOP2_Msk (0x1U << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */
9799#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
9800#define PWR_CR1_LPMS_STANDBY_Pos (0U)
9801#define PWR_CR1_LPMS_STANDBY_Msk (0x3U << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
9802#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
9803#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
9804#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
9805#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
9806
9807
9808/******************** Bit definition for PWR_CR2 register ********************/
9809#define PWR_CR2_USV_Pos (10U)
9810#define PWR_CR2_USV_Msk (0x1U << PWR_CR2_USV_Pos) /*!< 0x00000400 */
9811#define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */
9812#define PWR_CR2_IOSV_Pos (9U)
9813#define PWR_CR2_IOSV_Msk (0x1U << PWR_CR2_IOSV_Pos) /*!< 0x00000200 */
9814#define PWR_CR2_IOSV PWR_CR2_IOSV_Msk /*!< VDD IO2 independent I/Os Supply Valid */
9815/*!< PVME Peripheral Voltage Monitor Enable */
9816#define PWR_CR2_PVME_Pos (4U)
9817#define PWR_CR2_PVME_Msk (0xFU << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
9818#define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
9819#define PWR_CR2_PVME4_Pos (7U)
9820#define PWR_CR2_PVME4_Msk (0x1U << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
9821#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
9822#define PWR_CR2_PVME3_Pos (6U)
9823#define PWR_CR2_PVME3_Msk (0x1U << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
9824#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
9825#define PWR_CR2_PVME2_Pos (5U)
9826#define PWR_CR2_PVME2_Msk (0x1U << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
9827#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
9828#define PWR_CR2_PVME1_Pos (4U)
9829#define PWR_CR2_PVME1_Msk (0x1U << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
9830#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
9831/*!< PVD level configuration */
9832#define PWR_CR2_PLS_Pos (1U)
9833#define PWR_CR2_PLS_Msk (0x7U << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
9834#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
9835#define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
9836#define PWR_CR2_PLS_LEV1_Pos (1U)
9837#define PWR_CR2_PLS_LEV1_Msk (0x1U << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
9838#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
9839#define PWR_CR2_PLS_LEV2_Pos (2U)
9840#define PWR_CR2_PLS_LEV2_Msk (0x1U << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
9841#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
9842#define PWR_CR2_PLS_LEV3_Pos (1U)
9843#define PWR_CR2_PLS_LEV3_Msk (0x3U << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
9844#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
9845#define PWR_CR2_PLS_LEV4_Pos (3U)
9846#define PWR_CR2_PLS_LEV4_Msk (0x1U << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
9847#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
9848#define PWR_CR2_PLS_LEV5_Pos (1U)
9849#define PWR_CR2_PLS_LEV5_Msk (0x5U << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
9850#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
9851#define PWR_CR2_PLS_LEV6_Pos (2U)
9852#define PWR_CR2_PLS_LEV6_Msk (0x3U << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
9853#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
9854#define PWR_CR2_PLS_LEV7_Pos (1U)
9855#define PWR_CR2_PLS_LEV7_Msk (0x7U << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
9856#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
9857#define PWR_CR2_PVDE_Pos (0U)
9858#define PWR_CR2_PVDE_Msk (0x1U << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
9859#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
9860
9861/******************** Bit definition for PWR_CR3 register ********************/
9862#define PWR_CR3_EIWUL_Pos (15U)
9863#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
9864#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
9865#define PWR_CR3_APC_Pos (10U)
9866#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
9867#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
9868#define PWR_CR3_RRS_Pos (8U)
9869#define PWR_CR3_RRS_Msk (0x1U << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
9870#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
9871#define PWR_CR3_EWUP5_Pos (4U)
9872#define PWR_CR3_EWUP5_Msk (0x1U << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
9873#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
9874#define PWR_CR3_EWUP4_Pos (3U)
9875#define PWR_CR3_EWUP4_Msk (0x1U << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
9876#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
9877#define PWR_CR3_EWUP3_Pos (2U)
9878#define PWR_CR3_EWUP3_Msk (0x1U << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
9879#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
9880#define PWR_CR3_EWUP2_Pos (1U)
9881#define PWR_CR3_EWUP2_Msk (0x1U << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
9882#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
9883#define PWR_CR3_EWUP1_Pos (0U)
9884#define PWR_CR3_EWUP1_Msk (0x1U << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
9885#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
9886#define PWR_CR3_EWUP_Pos (0U)
9887#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
9888#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
9889
9890/* Legacy defines */
9891#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
9892#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
9893#define PWR_CR3_EIWF PWR_CR3_EIWUL
9894
9895
9896/******************** Bit definition for PWR_CR4 register ********************/
9897#define PWR_CR4_VBRS_Pos (9U)
9898#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
9899#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
9900#define PWR_CR4_VBE_Pos (8U)
9901#define PWR_CR4_VBE_Msk (0x1U << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
9902#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
9903#define PWR_CR4_WP5_Pos (4U)
9904#define PWR_CR4_WP5_Msk (0x1U << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
9905#define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
9906#define PWR_CR4_WP4_Pos (3U)
9907#define PWR_CR4_WP4_Msk (0x1U << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
9908#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
9909#define PWR_CR4_WP3_Pos (2U)
9910#define PWR_CR4_WP3_Msk (0x1U << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
9911#define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
9912#define PWR_CR4_WP2_Pos (1U)
9913#define PWR_CR4_WP2_Msk (0x1U << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
9914#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
9915#define PWR_CR4_WP1_Pos (0U)
9916#define PWR_CR4_WP1_Msk (0x1U << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
9917#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
9918
9919/******************** Bit definition for PWR_SR1 register ********************/
9920#define PWR_SR1_WUFI_Pos (15U)
9921#define PWR_SR1_WUFI_Msk (0x1U << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
9922#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
9923#define PWR_SR1_SBF_Pos (8U)
9924#define PWR_SR1_SBF_Msk (0x1U << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
9925#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
9926#define PWR_SR1_WUF_Pos (0U)
9927#define PWR_SR1_WUF_Msk (0x1FU << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
9928#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
9929#define PWR_SR1_WUF5_Pos (4U)
9930#define PWR_SR1_WUF5_Msk (0x1U << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
9931#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
9932#define PWR_SR1_WUF4_Pos (3U)
9933#define PWR_SR1_WUF4_Msk (0x1U << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
9934#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
9935#define PWR_SR1_WUF3_Pos (2U)
9936#define PWR_SR1_WUF3_Msk (0x1U << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
9937#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
9938#define PWR_SR1_WUF2_Pos (1U)
9939#define PWR_SR1_WUF2_Msk (0x1U << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
9940#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
9941#define PWR_SR1_WUF1_Pos (0U)
9942#define PWR_SR1_WUF1_Msk (0x1U << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
9943#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
9944
9945/******************** Bit definition for PWR_SR2 register ********************/
9946#define PWR_SR2_PVMO4_Pos (15U)
9947#define PWR_SR2_PVMO4_Msk (0x1U << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
9948#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
9949#define PWR_SR2_PVMO3_Pos (14U)
9950#define PWR_SR2_PVMO3_Msk (0x1U << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
9951#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
9952#define PWR_SR2_PVMO2_Pos (13U)
9953#define PWR_SR2_PVMO2_Msk (0x1U << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
9954#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
9955#define PWR_SR2_PVMO1_Pos (12U)
9956#define PWR_SR2_PVMO1_Msk (0x1U << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
9957#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
9958#define PWR_SR2_PVDO_Pos (11U)
9959#define PWR_SR2_PVDO_Msk (0x1U << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
9960#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
9961#define PWR_SR2_VOSF_Pos (10U)
9962#define PWR_SR2_VOSF_Msk (0x1U << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
9963#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
9964#define PWR_SR2_REGLPF_Pos (9U)
9965#define PWR_SR2_REGLPF_Msk (0x1U << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
9966#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
9967#define PWR_SR2_REGLPS_Pos (8U)
9968#define PWR_SR2_REGLPS_Msk (0x1U << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
9969#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
9970
9971/******************** Bit definition for PWR_SCR register ********************/
9972#define PWR_SCR_CSBF_Pos (8U)
9973#define PWR_SCR_CSBF_Msk (0x1U << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
9974#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
9975#define PWR_SCR_CWUF_Pos (0U)
9976#define PWR_SCR_CWUF_Msk (0x1FU << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
9977#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
9978#define PWR_SCR_CWUF5_Pos (4U)
9979#define PWR_SCR_CWUF5_Msk (0x1U << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
9980#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
9981#define PWR_SCR_CWUF4_Pos (3U)
9982#define PWR_SCR_CWUF4_Msk (0x1U << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
9983#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
9984#define PWR_SCR_CWUF3_Pos (2U)
9985#define PWR_SCR_CWUF3_Msk (0x1U << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
9986#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
9987#define PWR_SCR_CWUF2_Pos (1U)
9988#define PWR_SCR_CWUF2_Msk (0x1U << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
9989#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
9990#define PWR_SCR_CWUF1_Pos (0U)
9991#define PWR_SCR_CWUF1_Msk (0x1U << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
9992#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
9993
9994/******************** Bit definition for PWR_PUCRA register ********************/
9995#define PWR_PUCRA_PA15_Pos (15U)
9996#define PWR_PUCRA_PA15_Msk (0x1U << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
9997#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
9998#define PWR_PUCRA_PA13_Pos (13U)
9999#define PWR_PUCRA_PA13_Msk (0x1U << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
10000#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
10001#define PWR_PUCRA_PA12_Pos (12U)
10002#define PWR_PUCRA_PA12_Msk (0x1U << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
10003#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
10004#define PWR_PUCRA_PA11_Pos (11U)
10005#define PWR_PUCRA_PA11_Msk (0x1U << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
10006#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
10007#define PWR_PUCRA_PA10_Pos (10U)
10008#define PWR_PUCRA_PA10_Msk (0x1U << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
10009#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
10010#define PWR_PUCRA_PA9_Pos (9U)
10011#define PWR_PUCRA_PA9_Msk (0x1U << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
10012#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
10013#define PWR_PUCRA_PA8_Pos (8U)
10014#define PWR_PUCRA_PA8_Msk (0x1U << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
10015#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
10016#define PWR_PUCRA_PA7_Pos (7U)
10017#define PWR_PUCRA_PA7_Msk (0x1U << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
10018#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
10019#define PWR_PUCRA_PA6_Pos (6U)
10020#define PWR_PUCRA_PA6_Msk (0x1U << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
10021#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
10022#define PWR_PUCRA_PA5_Pos (5U)
10023#define PWR_PUCRA_PA5_Msk (0x1U << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
10024#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
10025#define PWR_PUCRA_PA4_Pos (4U)
10026#define PWR_PUCRA_PA4_Msk (0x1U << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
10027#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
10028#define PWR_PUCRA_PA3_Pos (3U)
10029#define PWR_PUCRA_PA3_Msk (0x1U << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
10030#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
10031#define PWR_PUCRA_PA2_Pos (2U)
10032#define PWR_PUCRA_PA2_Msk (0x1U << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
10033#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
10034#define PWR_PUCRA_PA1_Pos (1U)
10035#define PWR_PUCRA_PA1_Msk (0x1U << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
10036#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
10037#define PWR_PUCRA_PA0_Pos (0U)
10038#define PWR_PUCRA_PA0_Msk (0x1U << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
10039#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
10040
10041/******************** Bit definition for PWR_PDCRA register ********************/
10042#define PWR_PDCRA_PA14_Pos (14U)
10043#define PWR_PDCRA_PA14_Msk (0x1U << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
10044#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
10045#define PWR_PDCRA_PA12_Pos (12U)
10046#define PWR_PDCRA_PA12_Msk (0x1U << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
10047#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
10048#define PWR_PDCRA_PA11_Pos (11U)
10049#define PWR_PDCRA_PA11_Msk (0x1U << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
10050#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
10051#define PWR_PDCRA_PA10_Pos (10U)
10052#define PWR_PDCRA_PA10_Msk (0x1U << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
10053#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
10054#define PWR_PDCRA_PA9_Pos (9U)
10055#define PWR_PDCRA_PA9_Msk (0x1U << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
10056#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
10057#define PWR_PDCRA_PA8_Pos (8U)
10058#define PWR_PDCRA_PA8_Msk (0x1U << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
10059#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
10060#define PWR_PDCRA_PA7_Pos (7U)
10061#define PWR_PDCRA_PA7_Msk (0x1U << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
10062#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
10063#define PWR_PDCRA_PA6_Pos (6U)
10064#define PWR_PDCRA_PA6_Msk (0x1U << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
10065#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
10066#define PWR_PDCRA_PA5_Pos (5U)
10067#define PWR_PDCRA_PA5_Msk (0x1U << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
10068#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
10069#define PWR_PDCRA_PA4_Pos (4U)
10070#define PWR_PDCRA_PA4_Msk (0x1U << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
10071#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
10072#define PWR_PDCRA_PA3_Pos (3U)
10073#define PWR_PDCRA_PA3_Msk (0x1U << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
10074#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
10075#define PWR_PDCRA_PA2_Pos (2U)
10076#define PWR_PDCRA_PA2_Msk (0x1U << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
10077#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
10078#define PWR_PDCRA_PA1_Pos (1U)
10079#define PWR_PDCRA_PA1_Msk (0x1U << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
10080#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
10081#define PWR_PDCRA_PA0_Pos (0U)
10082#define PWR_PDCRA_PA0_Msk (0x1U << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
10083#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
10084
10085/******************** Bit definition for PWR_PUCRB register ********************/
10086#define PWR_PUCRB_PB15_Pos (15U)
10087#define PWR_PUCRB_PB15_Msk (0x1U << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
10088#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
10089#define PWR_PUCRB_PB14_Pos (14U)
10090#define PWR_PUCRB_PB14_Msk (0x1U << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
10091#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
10092#define PWR_PUCRB_PB13_Pos (13U)
10093#define PWR_PUCRB_PB13_Msk (0x1U << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
10094#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
10095#define PWR_PUCRB_PB12_Pos (12U)
10096#define PWR_PUCRB_PB12_Msk (0x1U << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
10097#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
10098#define PWR_PUCRB_PB11_Pos (11U)
10099#define PWR_PUCRB_PB11_Msk (0x1U << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
10100#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
10101#define PWR_PUCRB_PB10_Pos (10U)
10102#define PWR_PUCRB_PB10_Msk (0x1U << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
10103#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
10104#define PWR_PUCRB_PB9_Pos (9U)
10105#define PWR_PUCRB_PB9_Msk (0x1U << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
10106#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
10107#define PWR_PUCRB_PB8_Pos (8U)
10108#define PWR_PUCRB_PB8_Msk (0x1U << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
10109#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
10110#define PWR_PUCRB_PB7_Pos (7U)
10111#define PWR_PUCRB_PB7_Msk (0x1U << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
10112#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
10113#define PWR_PUCRB_PB6_Pos (6U)
10114#define PWR_PUCRB_PB6_Msk (0x1U << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
10115#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
10116#define PWR_PUCRB_PB5_Pos (5U)
10117#define PWR_PUCRB_PB5_Msk (0x1U << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
10118#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
10119#define PWR_PUCRB_PB4_Pos (4U)
10120#define PWR_PUCRB_PB4_Msk (0x1U << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
10121#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
10122#define PWR_PUCRB_PB3_Pos (3U)
10123#define PWR_PUCRB_PB3_Msk (0x1U << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
10124#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
10125#define PWR_PUCRB_PB2_Pos (2U)
10126#define PWR_PUCRB_PB2_Msk (0x1U << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
10127#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
10128#define PWR_PUCRB_PB1_Pos (1U)
10129#define PWR_PUCRB_PB1_Msk (0x1U << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
10130#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
10131#define PWR_PUCRB_PB0_Pos (0U)
10132#define PWR_PUCRB_PB0_Msk (0x1U << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
10133#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
10134
10135/******************** Bit definition for PWR_PDCRB register ********************/
10136#define PWR_PDCRB_PB15_Pos (15U)
10137#define PWR_PDCRB_PB15_Msk (0x1U << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
10138#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
10139#define PWR_PDCRB_PB14_Pos (14U)
10140#define PWR_PDCRB_PB14_Msk (0x1U << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
10141#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
10142#define PWR_PDCRB_PB13_Pos (13U)
10143#define PWR_PDCRB_PB13_Msk (0x1U << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
10144#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
10145#define PWR_PDCRB_PB12_Pos (12U)
10146#define PWR_PDCRB_PB12_Msk (0x1U << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
10147#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
10148#define PWR_PDCRB_PB11_Pos (11U)
10149#define PWR_PDCRB_PB11_Msk (0x1U << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
10150#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
10151#define PWR_PDCRB_PB10_Pos (10U)
10152#define PWR_PDCRB_PB10_Msk (0x1U << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
10153#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
10154#define PWR_PDCRB_PB9_Pos (9U)
10155#define PWR_PDCRB_PB9_Msk (0x1U << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
10156#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
10157#define PWR_PDCRB_PB8_Pos (8U)
10158#define PWR_PDCRB_PB8_Msk (0x1U << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
10159#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
10160#define PWR_PDCRB_PB7_Pos (7U)
10161#define PWR_PDCRB_PB7_Msk (0x1U << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
10162#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
10163#define PWR_PDCRB_PB6_Pos (6U)
10164#define PWR_PDCRB_PB6_Msk (0x1U << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
10165#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
10166#define PWR_PDCRB_PB5_Pos (5U)
10167#define PWR_PDCRB_PB5_Msk (0x1U << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
10168#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
10169#define PWR_PDCRB_PB3_Pos (3U)
10170#define PWR_PDCRB_PB3_Msk (0x1U << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
10171#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
10172#define PWR_PDCRB_PB2_Pos (2U)
10173#define PWR_PDCRB_PB2_Msk (0x1U << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
10174#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
10175#define PWR_PDCRB_PB1_Pos (1U)
10176#define PWR_PDCRB_PB1_Msk (0x1U << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
10177#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
10178#define PWR_PDCRB_PB0_Pos (0U)
10179#define PWR_PDCRB_PB0_Msk (0x1U << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
10180#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
10181
10182/******************** Bit definition for PWR_PUCRC register ********************/
10183#define PWR_PUCRC_PC15_Pos (15U)
10184#define PWR_PUCRC_PC15_Msk (0x1U << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
10185#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
10186#define PWR_PUCRC_PC14_Pos (14U)
10187#define PWR_PUCRC_PC14_Msk (0x1U << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
10188#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
10189#define PWR_PUCRC_PC13_Pos (13U)
10190#define PWR_PUCRC_PC13_Msk (0x1U << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
10191#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
10192#define PWR_PUCRC_PC12_Pos (12U)
10193#define PWR_PUCRC_PC12_Msk (0x1U << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
10194#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
10195#define PWR_PUCRC_PC11_Pos (11U)
10196#define PWR_PUCRC_PC11_Msk (0x1U << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
10197#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
10198#define PWR_PUCRC_PC10_Pos (10U)
10199#define PWR_PUCRC_PC10_Msk (0x1U << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
10200#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
10201#define PWR_PUCRC_PC9_Pos (9U)
10202#define PWR_PUCRC_PC9_Msk (0x1U << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
10203#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
10204#define PWR_PUCRC_PC8_Pos (8U)
10205#define PWR_PUCRC_PC8_Msk (0x1U << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
10206#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
10207#define PWR_PUCRC_PC7_Pos (7U)
10208#define PWR_PUCRC_PC7_Msk (0x1U << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
10209#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
10210#define PWR_PUCRC_PC6_Pos (6U)
10211#define PWR_PUCRC_PC6_Msk (0x1U << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
10212#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
10213#define PWR_PUCRC_PC5_Pos (5U)
10214#define PWR_PUCRC_PC5_Msk (0x1U << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
10215#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
10216#define PWR_PUCRC_PC4_Pos (4U)
10217#define PWR_PUCRC_PC4_Msk (0x1U << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
10218#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
10219#define PWR_PUCRC_PC3_Pos (3U)
10220#define PWR_PUCRC_PC3_Msk (0x1U << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
10221#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
10222#define PWR_PUCRC_PC2_Pos (2U)
10223#define PWR_PUCRC_PC2_Msk (0x1U << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
10224#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
10225#define PWR_PUCRC_PC1_Pos (1U)
10226#define PWR_PUCRC_PC1_Msk (0x1U << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
10227#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
10228#define PWR_PUCRC_PC0_Pos (0U)
10229#define PWR_PUCRC_PC0_Msk (0x1U << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
10230#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
10231
10232/******************** Bit definition for PWR_PDCRC register ********************/
10233#define PWR_PDCRC_PC15_Pos (15U)
10234#define PWR_PDCRC_PC15_Msk (0x1U << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
10235#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
10236#define PWR_PDCRC_PC14_Pos (14U)
10237#define PWR_PDCRC_PC14_Msk (0x1U << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
10238#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
10239#define PWR_PDCRC_PC13_Pos (13U)
10240#define PWR_PDCRC_PC13_Msk (0x1U << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
10241#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
10242#define PWR_PDCRC_PC12_Pos (12U)
10243#define PWR_PDCRC_PC12_Msk (0x1U << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
10244#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
10245#define PWR_PDCRC_PC11_Pos (11U)
10246#define PWR_PDCRC_PC11_Msk (0x1U << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
10247#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
10248#define PWR_PDCRC_PC10_Pos (10U)
10249#define PWR_PDCRC_PC10_Msk (0x1U << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
10250#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
10251#define PWR_PDCRC_PC9_Pos (9U)
10252#define PWR_PDCRC_PC9_Msk (0x1U << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
10253#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
10254#define PWR_PDCRC_PC8_Pos (8U)
10255#define PWR_PDCRC_PC8_Msk (0x1U << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
10256#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
10257#define PWR_PDCRC_PC7_Pos (7U)
10258#define PWR_PDCRC_PC7_Msk (0x1U << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
10259#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
10260#define PWR_PDCRC_PC6_Pos (6U)
10261#define PWR_PDCRC_PC6_Msk (0x1U << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
10262#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
10263#define PWR_PDCRC_PC5_Pos (5U)
10264#define PWR_PDCRC_PC5_Msk (0x1U << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
10265#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
10266#define PWR_PDCRC_PC4_Pos (4U)
10267#define PWR_PDCRC_PC4_Msk (0x1U << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
10268#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
10269#define PWR_PDCRC_PC3_Pos (3U)
10270#define PWR_PDCRC_PC3_Msk (0x1U << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
10271#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
10272#define PWR_PDCRC_PC2_Pos (2U)
10273#define PWR_PDCRC_PC2_Msk (0x1U << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
10274#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
10275#define PWR_PDCRC_PC1_Pos (1U)
10276#define PWR_PDCRC_PC1_Msk (0x1U << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
10277#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
10278#define PWR_PDCRC_PC0_Pos (0U)
10279#define PWR_PDCRC_PC0_Msk (0x1U << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
10280#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
10281
10282/******************** Bit definition for PWR_PUCRD register ********************/
10283#define PWR_PUCRD_PD15_Pos (15U)
10284#define PWR_PUCRD_PD15_Msk (0x1U << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
10285#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
10286#define PWR_PUCRD_PD14_Pos (14U)
10287#define PWR_PUCRD_PD14_Msk (0x1U << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
10288#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
10289#define PWR_PUCRD_PD13_Pos (13U)
10290#define PWR_PUCRD_PD13_Msk (0x1U << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
10291#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
10292#define PWR_PUCRD_PD12_Pos (12U)
10293#define PWR_PUCRD_PD12_Msk (0x1U << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
10294#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
10295#define PWR_PUCRD_PD11_Pos (11U)
10296#define PWR_PUCRD_PD11_Msk (0x1U << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
10297#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
10298#define PWR_PUCRD_PD10_Pos (10U)
10299#define PWR_PUCRD_PD10_Msk (0x1U << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
10300#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
10301#define PWR_PUCRD_PD9_Pos (9U)
10302#define PWR_PUCRD_PD9_Msk (0x1U << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
10303#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
10304#define PWR_PUCRD_PD8_Pos (8U)
10305#define PWR_PUCRD_PD8_Msk (0x1U << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
10306#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
10307#define PWR_PUCRD_PD7_Pos (7U)
10308#define PWR_PUCRD_PD7_Msk (0x1U << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
10309#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
10310#define PWR_PUCRD_PD6_Pos (6U)
10311#define PWR_PUCRD_PD6_Msk (0x1U << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
10312#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
10313#define PWR_PUCRD_PD5_Pos (5U)
10314#define PWR_PUCRD_PD5_Msk (0x1U << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
10315#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
10316#define PWR_PUCRD_PD4_Pos (4U)
10317#define PWR_PUCRD_PD4_Msk (0x1U << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
10318#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
10319#define PWR_PUCRD_PD3_Pos (3U)
10320#define PWR_PUCRD_PD3_Msk (0x1U << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
10321#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
10322#define PWR_PUCRD_PD2_Pos (2U)
10323#define PWR_PUCRD_PD2_Msk (0x1U << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
10324#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
10325#define PWR_PUCRD_PD1_Pos (1U)
10326#define PWR_PUCRD_PD1_Msk (0x1U << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
10327#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
10328#define PWR_PUCRD_PD0_Pos (0U)
10329#define PWR_PUCRD_PD0_Msk (0x1U << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
10330#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
10331
10332/******************** Bit definition for PWR_PDCRD register ********************/
10333#define PWR_PDCRD_PD15_Pos (15U)
10334#define PWR_PDCRD_PD15_Msk (0x1U << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
10335#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
10336#define PWR_PDCRD_PD14_Pos (14U)
10337#define PWR_PDCRD_PD14_Msk (0x1U << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
10338#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
10339#define PWR_PDCRD_PD13_Pos (13U)
10340#define PWR_PDCRD_PD13_Msk (0x1U << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
10341#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
10342#define PWR_PDCRD_PD12_Pos (12U)
10343#define PWR_PDCRD_PD12_Msk (0x1U << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
10344#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
10345#define PWR_PDCRD_PD11_Pos (11U)
10346#define PWR_PDCRD_PD11_Msk (0x1U << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
10347#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
10348#define PWR_PDCRD_PD10_Pos (10U)
10349#define PWR_PDCRD_PD10_Msk (0x1U << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
10350#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
10351#define PWR_PDCRD_PD9_Pos (9U)
10352#define PWR_PDCRD_PD9_Msk (0x1U << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
10353#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
10354#define PWR_PDCRD_PD8_Pos (8U)
10355#define PWR_PDCRD_PD8_Msk (0x1U << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
10356#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
10357#define PWR_PDCRD_PD7_Pos (7U)
10358#define PWR_PDCRD_PD7_Msk (0x1U << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
10359#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
10360#define PWR_PDCRD_PD6_Pos (6U)
10361#define PWR_PDCRD_PD6_Msk (0x1U << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
10362#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
10363#define PWR_PDCRD_PD5_Pos (5U)
10364#define PWR_PDCRD_PD5_Msk (0x1U << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
10365#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
10366#define PWR_PDCRD_PD4_Pos (4U)
10367#define PWR_PDCRD_PD4_Msk (0x1U << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
10368#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
10369#define PWR_PDCRD_PD3_Pos (3U)
10370#define PWR_PDCRD_PD3_Msk (0x1U << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
10371#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
10372#define PWR_PDCRD_PD2_Pos (2U)
10373#define PWR_PDCRD_PD2_Msk (0x1U << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
10374#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
10375#define PWR_PDCRD_PD1_Pos (1U)
10376#define PWR_PDCRD_PD1_Msk (0x1U << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
10377#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
10378#define PWR_PDCRD_PD0_Pos (0U)
10379#define PWR_PDCRD_PD0_Msk (0x1U << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
10380#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
10381
10382/******************** Bit definition for PWR_PUCRE register ********************/
10383#define PWR_PUCRE_PE15_Pos (15U)
10384#define PWR_PUCRE_PE15_Msk (0x1U << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
10385#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
10386#define PWR_PUCRE_PE14_Pos (14U)
10387#define PWR_PUCRE_PE14_Msk (0x1U << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
10388#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
10389#define PWR_PUCRE_PE13_Pos (13U)
10390#define PWR_PUCRE_PE13_Msk (0x1U << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
10391#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
10392#define PWR_PUCRE_PE12_Pos (12U)
10393#define PWR_PUCRE_PE12_Msk (0x1U << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
10394#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
10395#define PWR_PUCRE_PE11_Pos (11U)
10396#define PWR_PUCRE_PE11_Msk (0x1U << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
10397#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
10398#define PWR_PUCRE_PE10_Pos (10U)
10399#define PWR_PUCRE_PE10_Msk (0x1U << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
10400#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
10401#define PWR_PUCRE_PE9_Pos (9U)
10402#define PWR_PUCRE_PE9_Msk (0x1U << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
10403#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
10404#define PWR_PUCRE_PE8_Pos (8U)
10405#define PWR_PUCRE_PE8_Msk (0x1U << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
10406#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
10407#define PWR_PUCRE_PE7_Pos (7U)
10408#define PWR_PUCRE_PE7_Msk (0x1U << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
10409#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
10410#define PWR_PUCRE_PE6_Pos (6U)
10411#define PWR_PUCRE_PE6_Msk (0x1U << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
10412#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
10413#define PWR_PUCRE_PE5_Pos (5U)
10414#define PWR_PUCRE_PE5_Msk (0x1U << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
10415#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
10416#define PWR_PUCRE_PE4_Pos (4U)
10417#define PWR_PUCRE_PE4_Msk (0x1U << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
10418#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
10419#define PWR_PUCRE_PE3_Pos (3U)
10420#define PWR_PUCRE_PE3_Msk (0x1U << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
10421#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
10422#define PWR_PUCRE_PE2_Pos (2U)
10423#define PWR_PUCRE_PE2_Msk (0x1U << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
10424#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
10425#define PWR_PUCRE_PE1_Pos (1U)
10426#define PWR_PUCRE_PE1_Msk (0x1U << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
10427#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
10428#define PWR_PUCRE_PE0_Pos (0U)
10429#define PWR_PUCRE_PE0_Msk (0x1U << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
10430#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
10431
10432/******************** Bit definition for PWR_PDCRE register ********************/
10433#define PWR_PDCRE_PE15_Pos (15U)
10434#define PWR_PDCRE_PE15_Msk (0x1U << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
10435#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
10436#define PWR_PDCRE_PE14_Pos (14U)
10437#define PWR_PDCRE_PE14_Msk (0x1U << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
10438#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
10439#define PWR_PDCRE_PE13_Pos (13U)
10440#define PWR_PDCRE_PE13_Msk (0x1U << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
10441#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
10442#define PWR_PDCRE_PE12_Pos (12U)
10443#define PWR_PDCRE_PE12_Msk (0x1U << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
10444#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
10445#define PWR_PDCRE_PE11_Pos (11U)
10446#define PWR_PDCRE_PE11_Msk (0x1U << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
10447#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
10448#define PWR_PDCRE_PE10_Pos (10U)
10449#define PWR_PDCRE_PE10_Msk (0x1U << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
10450#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
10451#define PWR_PDCRE_PE9_Pos (9U)
10452#define PWR_PDCRE_PE9_Msk (0x1U << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
10453#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
10454#define PWR_PDCRE_PE8_Pos (8U)
10455#define PWR_PDCRE_PE8_Msk (0x1U << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
10456#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
10457#define PWR_PDCRE_PE7_Pos (7U)
10458#define PWR_PDCRE_PE7_Msk (0x1U << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
10459#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
10460#define PWR_PDCRE_PE6_Pos (6U)
10461#define PWR_PDCRE_PE6_Msk (0x1U << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
10462#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
10463#define PWR_PDCRE_PE5_Pos (5U)
10464#define PWR_PDCRE_PE5_Msk (0x1U << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
10465#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
10466#define PWR_PDCRE_PE4_Pos (4U)
10467#define PWR_PDCRE_PE4_Msk (0x1U << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
10468#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
10469#define PWR_PDCRE_PE3_Pos (3U)
10470#define PWR_PDCRE_PE3_Msk (0x1U << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
10471#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
10472#define PWR_PDCRE_PE2_Pos (2U)
10473#define PWR_PDCRE_PE2_Msk (0x1U << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
10474#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
10475#define PWR_PDCRE_PE1_Pos (1U)
10476#define PWR_PDCRE_PE1_Msk (0x1U << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
10477#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
10478#define PWR_PDCRE_PE0_Pos (0U)
10479#define PWR_PDCRE_PE0_Msk (0x1U << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
10480#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
10481
10482/******************** Bit definition for PWR_PUCRF register ********************/
10483#define PWR_PUCRF_PF15_Pos (15U)
10484#define PWR_PUCRF_PF15_Msk (0x1U << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
10485#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
10486#define PWR_PUCRF_PF14_Pos (14U)
10487#define PWR_PUCRF_PF14_Msk (0x1U << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
10488#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
10489#define PWR_PUCRF_PF13_Pos (13U)
10490#define PWR_PUCRF_PF13_Msk (0x1U << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
10491#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
10492#define PWR_PUCRF_PF12_Pos (12U)
10493#define PWR_PUCRF_PF12_Msk (0x1U << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
10494#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
10495#define PWR_PUCRF_PF11_Pos (11U)
10496#define PWR_PUCRF_PF11_Msk (0x1U << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
10497#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
10498#define PWR_PUCRF_PF10_Pos (10U)
10499#define PWR_PUCRF_PF10_Msk (0x1U << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
10500#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
10501#define PWR_PUCRF_PF9_Pos (9U)
10502#define PWR_PUCRF_PF9_Msk (0x1U << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
10503#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
10504#define PWR_PUCRF_PF8_Pos (8U)
10505#define PWR_PUCRF_PF8_Msk (0x1U << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
10506#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
10507#define PWR_PUCRF_PF7_Pos (7U)
10508#define PWR_PUCRF_PF7_Msk (0x1U << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
10509#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
10510#define PWR_PUCRF_PF6_Pos (6U)
10511#define PWR_PUCRF_PF6_Msk (0x1U << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
10512#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
10513#define PWR_PUCRF_PF5_Pos (5U)
10514#define PWR_PUCRF_PF5_Msk (0x1U << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
10515#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
10516#define PWR_PUCRF_PF4_Pos (4U)
10517#define PWR_PUCRF_PF4_Msk (0x1U << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
10518#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
10519#define PWR_PUCRF_PF3_Pos (3U)
10520#define PWR_PUCRF_PF3_Msk (0x1U << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
10521#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
10522#define PWR_PUCRF_PF2_Pos (2U)
10523#define PWR_PUCRF_PF2_Msk (0x1U << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
10524#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
10525#define PWR_PUCRF_PF1_Pos (1U)
10526#define PWR_PUCRF_PF1_Msk (0x1U << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
10527#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
10528#define PWR_PUCRF_PF0_Pos (0U)
10529#define PWR_PUCRF_PF0_Msk (0x1U << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
10530#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
10531
10532/******************** Bit definition for PWR_PDCRF register ********************/
10533#define PWR_PDCRF_PF15_Pos (15U)
10534#define PWR_PDCRF_PF15_Msk (0x1U << PWR_PDCRF_PF15_Pos) /*!< 0x00008000 */
10535#define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk /*!< Port PF15 Pull-Down set */
10536#define PWR_PDCRF_PF14_Pos (14U)
10537#define PWR_PDCRF_PF14_Msk (0x1U << PWR_PDCRF_PF14_Pos) /*!< 0x00004000 */
10538#define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk /*!< Port PF14 Pull-Down set */
10539#define PWR_PDCRF_PF13_Pos (13U)
10540#define PWR_PDCRF_PF13_Msk (0x1U << PWR_PDCRF_PF13_Pos) /*!< 0x00002000 */
10541#define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk /*!< Port PF13 Pull-Down set */
10542#define PWR_PDCRF_PF12_Pos (12U)
10543#define PWR_PDCRF_PF12_Msk (0x1U << PWR_PDCRF_PF12_Pos) /*!< 0x00001000 */
10544#define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk /*!< Port PF12 Pull-Down set */
10545#define PWR_PDCRF_PF11_Pos (11U)
10546#define PWR_PDCRF_PF11_Msk (0x1U << PWR_PDCRF_PF11_Pos) /*!< 0x00000800 */
10547#define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk /*!< Port PF11 Pull-Down set */
10548#define PWR_PDCRF_PF10_Pos (10U)
10549#define PWR_PDCRF_PF10_Msk (0x1U << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
10550#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
10551#define PWR_PDCRF_PF9_Pos (9U)
10552#define PWR_PDCRF_PF9_Msk (0x1U << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
10553#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
10554#define PWR_PDCRF_PF8_Pos (8U)
10555#define PWR_PDCRF_PF8_Msk (0x1U << PWR_PDCRF_PF8_Pos) /*!< 0x00000100 */
10556#define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk /*!< Port PF8 Pull-Down set */
10557#define PWR_PDCRF_PF7_Pos (7U)
10558#define PWR_PDCRF_PF7_Msk (0x1U << PWR_PDCRF_PF7_Pos) /*!< 0x00000080 */
10559#define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk /*!< Port PF7 Pull-Down set */
10560#define PWR_PDCRF_PF6_Pos (6U)
10561#define PWR_PDCRF_PF6_Msk (0x1U << PWR_PDCRF_PF6_Pos) /*!< 0x00000040 */
10562#define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk /*!< Port PF6 Pull-Down set */
10563#define PWR_PDCRF_PF5_Pos (5U)
10564#define PWR_PDCRF_PF5_Msk (0x1U << PWR_PDCRF_PF5_Pos) /*!< 0x00000020 */
10565#define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk /*!< Port PF5 Pull-Down set */
10566#define PWR_PDCRF_PF4_Pos (4U)
10567#define PWR_PDCRF_PF4_Msk (0x1U << PWR_PDCRF_PF4_Pos) /*!< 0x00000010 */
10568#define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk /*!< Port PF4 Pull-Down set */
10569#define PWR_PDCRF_PF3_Pos (3U)
10570#define PWR_PDCRF_PF3_Msk (0x1U << PWR_PDCRF_PF3_Pos) /*!< 0x00000008 */
10571#define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk /*!< Port PF3 Pull-Down set */
10572#define PWR_PDCRF_PF2_Pos (2U)
10573#define PWR_PDCRF_PF2_Msk (0x1U << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
10574#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
10575#define PWR_PDCRF_PF1_Pos (1U)
10576#define PWR_PDCRF_PF1_Msk (0x1U << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
10577#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
10578#define PWR_PDCRF_PF0_Pos (0U)
10579#define PWR_PDCRF_PF0_Msk (0x1U << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
10580#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
10581
10582/******************** Bit definition for PWR_PUCRG register ********************/
10583#define PWR_PUCRG_PG15_Pos (15U)
10584#define PWR_PUCRG_PG15_Msk (0x1U << PWR_PUCRG_PG15_Pos) /*!< 0x00008000 */
10585#define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk /*!< Port PG15 Pull-Up set */
10586#define PWR_PUCRG_PG14_Pos (14U)
10587#define PWR_PUCRG_PG14_Msk (0x1U << PWR_PUCRG_PG14_Pos) /*!< 0x00004000 */
10588#define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk /*!< Port PG14 Pull-Up set */
10589#define PWR_PUCRG_PG13_Pos (13U)
10590#define PWR_PUCRG_PG13_Msk (0x1U << PWR_PUCRG_PG13_Pos) /*!< 0x00002000 */
10591#define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk /*!< Port PG13 Pull-Up set */
10592#define PWR_PUCRG_PG12_Pos (12U)
10593#define PWR_PUCRG_PG12_Msk (0x1U << PWR_PUCRG_PG12_Pos) /*!< 0x00001000 */
10594#define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk /*!< Port PG12 Pull-Up set */
10595#define PWR_PUCRG_PG11_Pos (11U)
10596#define PWR_PUCRG_PG11_Msk (0x1U << PWR_PUCRG_PG11_Pos) /*!< 0x00000800 */
10597#define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk /*!< Port PG11 Pull-Up set */
10598#define PWR_PUCRG_PG10_Pos (10U)
10599#define PWR_PUCRG_PG10_Msk (0x1U << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
10600#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
10601#define PWR_PUCRG_PG9_Pos (9U)
10602#define PWR_PUCRG_PG9_Msk (0x1U << PWR_PUCRG_PG9_Pos) /*!< 0x00000200 */
10603#define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk /*!< Port PG9 Pull-Up set */
10604#define PWR_PUCRG_PG8_Pos (8U)
10605#define PWR_PUCRG_PG8_Msk (0x1U << PWR_PUCRG_PG8_Pos) /*!< 0x00000100 */
10606#define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk /*!< Port PG8 Pull-Up set */
10607#define PWR_PUCRG_PG7_Pos (7U)
10608#define PWR_PUCRG_PG7_Msk (0x1U << PWR_PUCRG_PG7_Pos) /*!< 0x00000080 */
10609#define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk /*!< Port PG7 Pull-Up set */
10610#define PWR_PUCRG_PG6_Pos (6U)
10611#define PWR_PUCRG_PG6_Msk (0x1U << PWR_PUCRG_PG6_Pos) /*!< 0x00000040 */
10612#define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk /*!< Port PG6 Pull-Up set */
10613#define PWR_PUCRG_PG5_Pos (5U)
10614#define PWR_PUCRG_PG5_Msk (0x1U << PWR_PUCRG_PG5_Pos) /*!< 0x00000020 */
10615#define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk /*!< Port PG5 Pull-Up set */
10616#define PWR_PUCRG_PG4_Pos (4U)
10617#define PWR_PUCRG_PG4_Msk (0x1U << PWR_PUCRG_PG4_Pos) /*!< 0x00000010 */
10618#define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk /*!< Port PG4 Pull-Up set */
10619#define PWR_PUCRG_PG3_Pos (3U)
10620#define PWR_PUCRG_PG3_Msk (0x1U << PWR_PUCRG_PG3_Pos) /*!< 0x00000008 */
10621#define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk /*!< Port PG3 Pull-Up set */
10622#define PWR_PUCRG_PG2_Pos (2U)
10623#define PWR_PUCRG_PG2_Msk (0x1U << PWR_PUCRG_PG2_Pos) /*!< 0x00000004 */
10624#define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk /*!< Port PG2 Pull-Up set */
10625#define PWR_PUCRG_PG1_Pos (1U)
10626#define PWR_PUCRG_PG1_Msk (0x1U << PWR_PUCRG_PG1_Pos) /*!< 0x00000002 */
10627#define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk /*!< Port PG1 Pull-Up set */
10628#define PWR_PUCRG_PG0_Pos (0U)
10629#define PWR_PUCRG_PG0_Msk (0x1U << PWR_PUCRG_PG0_Pos) /*!< 0x00000001 */
10630#define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk /*!< Port PG0 Pull-Up set */
10631
10632/******************** Bit definition for PWR_PDCRG register ********************/
10633#define PWR_PDCRG_PG15_Pos (15U)
10634#define PWR_PDCRG_PG15_Msk (0x1U << PWR_PDCRG_PG15_Pos) /*!< 0x00008000 */
10635#define PWR_PDCRG_PG15 PWR_PDCRG_PG15_Msk /*!< Port PG15 Pull-Down set */
10636#define PWR_PDCRG_PG14_Pos (14U)
10637#define PWR_PDCRG_PG14_Msk (0x1U << PWR_PDCRG_PG14_Pos) /*!< 0x00004000 */
10638#define PWR_PDCRG_PG14 PWR_PDCRG_PG14_Msk /*!< Port PG14 Pull-Down set */
10639#define PWR_PDCRG_PG13_Pos (13U)
10640#define PWR_PDCRG_PG13_Msk (0x1U << PWR_PDCRG_PG13_Pos) /*!< 0x00002000 */
10641#define PWR_PDCRG_PG13 PWR_PDCRG_PG13_Msk /*!< Port PG13 Pull-Down set */
10642#define PWR_PDCRG_PG12_Pos (12U)
10643#define PWR_PDCRG_PG12_Msk (0x1U << PWR_PDCRG_PG12_Pos) /*!< 0x00001000 */
10644#define PWR_PDCRG_PG12 PWR_PDCRG_PG12_Msk /*!< Port PG12 Pull-Down set */
10645#define PWR_PDCRG_PG11_Pos (11U)
10646#define PWR_PDCRG_PG11_Msk (0x1U << PWR_PDCRG_PG11_Pos) /*!< 0x00000800 */
10647#define PWR_PDCRG_PG11 PWR_PDCRG_PG11_Msk /*!< Port PG11 Pull-Down set */
10648#define PWR_PDCRG_PG10_Pos (10U)
10649#define PWR_PDCRG_PG10_Msk (0x1U << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
10650#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
10651#define PWR_PDCRG_PG9_Pos (9U)
10652#define PWR_PDCRG_PG9_Msk (0x1U << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
10653#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
10654#define PWR_PDCRG_PG8_Pos (8U)
10655#define PWR_PDCRG_PG8_Msk (0x1U << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
10656#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
10657#define PWR_PDCRG_PG7_Pos (7U)
10658#define PWR_PDCRG_PG7_Msk (0x1U << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
10659#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
10660#define PWR_PDCRG_PG6_Pos (6U)
10661#define PWR_PDCRG_PG6_Msk (0x1U << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
10662#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
10663#define PWR_PDCRG_PG5_Pos (5U)
10664#define PWR_PDCRG_PG5_Msk (0x1U << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
10665#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
10666#define PWR_PDCRG_PG4_Pos (4U)
10667#define PWR_PDCRG_PG4_Msk (0x1U << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
10668#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
10669#define PWR_PDCRG_PG3_Pos (3U)
10670#define PWR_PDCRG_PG3_Msk (0x1U << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
10671#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
10672#define PWR_PDCRG_PG2_Pos (2U)
10673#define PWR_PDCRG_PG2_Msk (0x1U << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
10674#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
10675#define PWR_PDCRG_PG1_Pos (1U)
10676#define PWR_PDCRG_PG1_Msk (0x1U << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
10677#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
10678#define PWR_PDCRG_PG0_Pos (0U)
10679#define PWR_PDCRG_PG0_Msk (0x1U << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
10680#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
10681
10682/******************** Bit definition for PWR_PUCRH register ********************/
10683#define PWR_PUCRH_PH1_Pos (1U)
10684#define PWR_PUCRH_PH1_Msk (0x1U << PWR_PUCRH_PH1_Pos) /*!< 0x00000002 */
10685#define PWR_PUCRH_PH1 PWR_PUCRH_PH1_Msk /*!< Port PH1 Pull-Up set */
10686#define PWR_PUCRH_PH0_Pos (0U)
10687#define PWR_PUCRH_PH0_Msk (0x1U << PWR_PUCRH_PH0_Pos) /*!< 0x00000001 */
10688#define PWR_PUCRH_PH0 PWR_PUCRH_PH0_Msk /*!< Port PH0 Pull-Up set */
10689
10690/******************** Bit definition for PWR_PDCRH register ********************/
10691#define PWR_PDCRH_PH1_Pos (1U)
10692#define PWR_PDCRH_PH1_Msk (0x1U << PWR_PDCRH_PH1_Pos) /*!< 0x00000002 */
10693#define PWR_PDCRH_PH1 PWR_PDCRH_PH1_Msk /*!< Port PH1 Pull-Down set */
10694#define PWR_PDCRH_PH0_Pos (0U)
10695#define PWR_PDCRH_PH0_Msk (0x1U << PWR_PDCRH_PH0_Pos) /*!< 0x00000001 */
10696#define PWR_PDCRH_PH0 PWR_PDCRH_PH0_Msk /*!< Port PH0 Pull-Down set */
10697
10698
10699/******************************************************************************/
10700/* */
10701/* Reset and Clock Control */
10702/* */
10703/******************************************************************************/
10704/*
10705* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
10706*/
10707#define RCC_PLLSAI2_SUPPORT
10708
10709/******************** Bit definition for RCC_CR register ********************/
10710#define RCC_CR_MSION_Pos (0U)
10711#define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000001 */
10712#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */
10713#define RCC_CR_MSIRDY_Pos (1U)
10714#define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */
10715#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
10716#define RCC_CR_MSIPLLEN_Pos (2U)
10717#define RCC_CR_MSIPLLEN_Msk (0x1U << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */
10718#define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */
10719#define RCC_CR_MSIRGSEL_Pos (3U)
10720#define RCC_CR_MSIRGSEL_Msk (0x1U << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */
10721#define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */
10722
10723/*!< MSIRANGE configuration : 12 frequency ranges available */
10724#define RCC_CR_MSIRANGE_Pos (4U)
10725#define RCC_CR_MSIRANGE_Msk (0xFU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */
10726#define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */
10727#define RCC_CR_MSIRANGE_0 (0x0U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */
10728#define RCC_CR_MSIRANGE_1 (0x1U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */
10729#define RCC_CR_MSIRANGE_2 (0x2U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */
10730#define RCC_CR_MSIRANGE_3 (0x3U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */
10731#define RCC_CR_MSIRANGE_4 (0x4U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */
10732#define RCC_CR_MSIRANGE_5 (0x5U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */
10733#define RCC_CR_MSIRANGE_6 (0x6U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */
10734#define RCC_CR_MSIRANGE_7 (0x7U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */
10735#define RCC_CR_MSIRANGE_8 (0x8U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */
10736#define RCC_CR_MSIRANGE_9 (0x9U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */
10737#define RCC_CR_MSIRANGE_10 (0xAU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */
10738#define RCC_CR_MSIRANGE_11 (0xBU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */
10739
10740#define RCC_CR_HSION_Pos (8U)
10741#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000100 */
10742#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
10743#define RCC_CR_HSIKERON_Pos (9U)
10744#define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
10745#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
10746#define RCC_CR_HSIRDY_Pos (10U)
10747#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
10748#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
10749#define RCC_CR_HSIASFS_Pos (11U)
10750#define RCC_CR_HSIASFS_Msk (0x1U << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */
10751#define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */
10752
10753#define RCC_CR_HSEON_Pos (16U)
10754#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
10755#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
10756#define RCC_CR_HSERDY_Pos (17U)
10757#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
10758#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
10759#define RCC_CR_HSEBYP_Pos (18U)
10760#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
10761#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
10762#define RCC_CR_CSSON_Pos (19U)
10763#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
10764#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
10765
10766#define RCC_CR_PLLON_Pos (24U)
10767#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
10768#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
10769#define RCC_CR_PLLRDY_Pos (25U)
10770#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
10771#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
10772#define RCC_CR_PLLSAI1ON_Pos (26U)
10773#define RCC_CR_PLLSAI1ON_Msk (0x1U << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
10774#define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
10775#define RCC_CR_PLLSAI1RDY_Pos (27U)
10776#define RCC_CR_PLLSAI1RDY_Msk (0x1U << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */
10777#define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */
10778#define RCC_CR_PLLSAI2ON_Pos (28U)
10779#define RCC_CR_PLLSAI2ON_Msk (0x1U << RCC_CR_PLLSAI2ON_Pos) /*!< 0x10000000 */
10780#define RCC_CR_PLLSAI2ON RCC_CR_PLLSAI2ON_Msk /*!< SAI2 PLL enable */
10781#define RCC_CR_PLLSAI2RDY_Pos (29U)
10782#define RCC_CR_PLLSAI2RDY_Msk (0x1U << RCC_CR_PLLSAI2RDY_Pos) /*!< 0x20000000 */
10783#define RCC_CR_PLLSAI2RDY RCC_CR_PLLSAI2RDY_Msk /*!< SAI2 PLL ready */
10784
10785/******************** Bit definition for RCC_ICSCR register ***************/
10786/*!< MSICAL configuration */
10787#define RCC_ICSCR_MSICAL_Pos (0U)
10788#define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */
10789#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */
10790#define RCC_ICSCR_MSICAL_0 (0x01U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */
10791#define RCC_ICSCR_MSICAL_1 (0x02U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */
10792#define RCC_ICSCR_MSICAL_2 (0x04U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */
10793#define RCC_ICSCR_MSICAL_3 (0x08U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */
10794#define RCC_ICSCR_MSICAL_4 (0x10U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */
10795#define RCC_ICSCR_MSICAL_5 (0x20U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */
10796#define RCC_ICSCR_MSICAL_6 (0x40U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */
10797#define RCC_ICSCR_MSICAL_7 (0x80U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */
10798
10799/*!< MSITRIM configuration */
10800#define RCC_ICSCR_MSITRIM_Pos (8U)
10801#define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
10802#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */
10803#define RCC_ICSCR_MSITRIM_0 (0x01U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
10804#define RCC_ICSCR_MSITRIM_1 (0x02U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
10805#define RCC_ICSCR_MSITRIM_2 (0x04U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
10806#define RCC_ICSCR_MSITRIM_3 (0x08U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
10807#define RCC_ICSCR_MSITRIM_4 (0x10U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
10808#define RCC_ICSCR_MSITRIM_5 (0x20U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
10809#define RCC_ICSCR_MSITRIM_6 (0x40U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
10810#define RCC_ICSCR_MSITRIM_7 (0x80U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
10811
10812/*!< HSICAL configuration */
10813#define RCC_ICSCR_HSICAL_Pos (16U)
10814#define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
10815#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
10816#define RCC_ICSCR_HSICAL_0 (0x01U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
10817#define RCC_ICSCR_HSICAL_1 (0x02U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
10818#define RCC_ICSCR_HSICAL_2 (0x04U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
10819#define RCC_ICSCR_HSICAL_3 (0x08U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
10820#define RCC_ICSCR_HSICAL_4 (0x10U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
10821#define RCC_ICSCR_HSICAL_5 (0x20U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
10822#define RCC_ICSCR_HSICAL_6 (0x40U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
10823#define RCC_ICSCR_HSICAL_7 (0x80U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
10824
10825/*!< HSITRIM configuration */
10826#define RCC_ICSCR_HSITRIM_Pos (24U)
10827#define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
10828#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
10829#define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
10830#define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
10831#define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
10832#define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
10833#define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
10834
10835/******************** Bit definition for RCC_CFGR register ******************/
10836/*!< SW configuration */
10837#define RCC_CFGR_SW_Pos (0U)
10838#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
10839#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
10840#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
10841#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
10842
10843#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI oscillator selection as system clock */
10844#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
10845#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
10846#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
10847
10848/*!< SWS configuration */
10849#define RCC_CFGR_SWS_Pos (2U)
10850#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
10851#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
10852#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
10853#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
10854
10855#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
10856#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
10857#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
10858#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
10859
10860/*!< HPRE configuration */
10861#define RCC_CFGR_HPRE_Pos (4U)
10862#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
10863#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
10864#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
10865#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
10866#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
10867#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
10868
10869#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
10870#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
10871#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
10872#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
10873#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
10874#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
10875#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
10876#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
10877#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
10878
10879/*!< PPRE1 configuration */
10880#define RCC_CFGR_PPRE1_Pos (8U)
10881#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
10882#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
10883#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
10884#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
10885#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
10886
10887#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
10888#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
10889#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
10890#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
10891#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
10892
10893/*!< PPRE2 configuration */
10894#define RCC_CFGR_PPRE2_Pos (11U)
10895#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
10896#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
10897#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
10898#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
10899#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
10900
10901#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
10902#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
10903#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
10904#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
10905#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
10906
10907#define RCC_CFGR_STOPWUCK_Pos (15U)
10908#define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
10909#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
10910
10911/*!< MCOSEL configuration */
10912#define RCC_CFGR_MCOSEL_Pos (24U)
10913#define RCC_CFGR_MCOSEL_Msk (0x7U << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */
10914#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [2:0] bits (Clock output selection) */
10915#define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
10916#define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
10917#define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
10918
10919#define RCC_CFGR_MCOPRE_Pos (28U)
10920#define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
10921#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
10922#define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
10923#define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
10924#define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
10925
10926#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
10927#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
10928#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
10929#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
10930#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
10931
10932/* Legacy aliases */
10933#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
10934#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
10935#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
10936#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
10937#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
10938#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
10939
10940/******************** Bit definition for RCC_PLLCFGR register ***************/
10941#define RCC_PLLCFGR_PLLSRC_Pos (0U)
10942#define RCC_PLLCFGR_PLLSRC_Msk (0x3U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
10943#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
10944
10945#define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
10946#define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
10947#define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */
10948#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
10949#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
10950#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
10951#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
10952#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
10953#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
10954
10955#define RCC_PLLCFGR_PLLM_Pos (4U)
10956#define RCC_PLLCFGR_PLLM_Msk (0x7U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
10957#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
10958#define RCC_PLLCFGR_PLLM_0 (0x1U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
10959#define RCC_PLLCFGR_PLLM_1 (0x2U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
10960#define RCC_PLLCFGR_PLLM_2 (0x4U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
10961
10962#define RCC_PLLCFGR_PLLN_Pos (8U)
10963#define RCC_PLLCFGR_PLLN_Msk (0x7FU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
10964#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
10965#define RCC_PLLCFGR_PLLN_0 (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
10966#define RCC_PLLCFGR_PLLN_1 (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
10967#define RCC_PLLCFGR_PLLN_2 (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
10968#define RCC_PLLCFGR_PLLN_3 (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
10969#define RCC_PLLCFGR_PLLN_4 (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
10970#define RCC_PLLCFGR_PLLN_5 (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
10971#define RCC_PLLCFGR_PLLN_6 (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
10972
10973#define RCC_PLLCFGR_PLLPEN_Pos (16U)
10974#define RCC_PLLCFGR_PLLPEN_Msk (0x1U << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
10975#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
10976#define RCC_PLLCFGR_PLLP_Pos (17U)
10977#define RCC_PLLCFGR_PLLP_Msk (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
10978#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
10979#define RCC_PLLCFGR_PLLQEN_Pos (20U)
10980#define RCC_PLLCFGR_PLLQEN_Msk (0x1U << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
10981#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
10982
10983#define RCC_PLLCFGR_PLLQ_Pos (21U)
10984#define RCC_PLLCFGR_PLLQ_Msk (0x3U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
10985#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
10986#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
10987#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
10988
10989#define RCC_PLLCFGR_PLLREN_Pos (24U)
10990#define RCC_PLLCFGR_PLLREN_Msk (0x1U << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
10991#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
10992#define RCC_PLLCFGR_PLLR_Pos (25U)
10993#define RCC_PLLCFGR_PLLR_Msk (0x3U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
10994#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
10995#define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
10996#define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
10997
10998/******************** Bit definition for RCC_PLLSAI1CFGR register ************/
10999#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
11000#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
11001#define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
11002#define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
11003#define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
11004#define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
11005#define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
11006#define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
11007#define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
11008#define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
11009
11010#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
11011#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
11012#define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
11013#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
11014#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
11015#define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
11016
11017#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
11018#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
11019#define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
11020#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
11021#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
11022#define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
11023#define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
11024#define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
11025
11026#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
11027#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
11028#define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
11029#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
11030#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
11031#define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
11032#define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
11033#define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
11034
11035/******************** Bit definition for RCC_PLLSAI2CFGR register ************/
11036#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos (8U)
11037#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */
11038#define RCC_PLLSAI2CFGR_PLLSAI2N RCC_PLLSAI2CFGR_PLLSAI2N_Msk
11039#define RCC_PLLSAI2CFGR_PLLSAI2N_0 (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */
11040#define RCC_PLLSAI2CFGR_PLLSAI2N_1 (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */
11041#define RCC_PLLSAI2CFGR_PLLSAI2N_2 (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */
11042#define RCC_PLLSAI2CFGR_PLLSAI2N_3 (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */
11043#define RCC_PLLSAI2CFGR_PLLSAI2N_4 (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */
11044#define RCC_PLLSAI2CFGR_PLLSAI2N_5 (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */
11045#define RCC_PLLSAI2CFGR_PLLSAI2N_6 (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */
11046
11047#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos (16U)
11048#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */
11049#define RCC_PLLSAI2CFGR_PLLSAI2PEN RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk
11050#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos (17U)
11051#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */
11052#define RCC_PLLSAI2CFGR_PLLSAI2P RCC_PLLSAI2CFGR_PLLSAI2P_Msk
11053
11054#define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos (24U)
11055#define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */
11056#define RCC_PLLSAI2CFGR_PLLSAI2REN RCC_PLLSAI2CFGR_PLLSAI2REN_Msk
11057#define RCC_PLLSAI2CFGR_PLLSAI2R_Pos (25U)
11058#define RCC_PLLSAI2CFGR_PLLSAI2R_Msk (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */
11059#define RCC_PLLSAI2CFGR_PLLSAI2R RCC_PLLSAI2CFGR_PLLSAI2R_Msk
11060#define RCC_PLLSAI2CFGR_PLLSAI2R_0 (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */
11061#define RCC_PLLSAI2CFGR_PLLSAI2R_1 (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */
11062
11063/******************** Bit definition for RCC_CIER register ******************/
11064#define RCC_CIER_LSIRDYIE_Pos (0U)
11065#define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
11066#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
11067#define RCC_CIER_LSERDYIE_Pos (1U)
11068#define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
11069#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
11070#define RCC_CIER_MSIRDYIE_Pos (2U)
11071#define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */
11072#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
11073#define RCC_CIER_HSIRDYIE_Pos (3U)
11074#define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
11075#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
11076#define RCC_CIER_HSERDYIE_Pos (4U)
11077#define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
11078#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
11079#define RCC_CIER_PLLRDYIE_Pos (5U)
11080#define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
11081#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
11082#define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
11083#define RCC_CIER_PLLSAI1RDYIE_Msk (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
11084#define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
11085#define RCC_CIER_PLLSAI2RDYIE_Pos (7U)
11086#define RCC_CIER_PLLSAI2RDYIE_Msk (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */
11087#define RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE_Msk
11088#define RCC_CIER_LSECSSIE_Pos (9U)
11089#define RCC_CIER_LSECSSIE_Msk (0x1U << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
11090#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
11091
11092/******************** Bit definition for RCC_CIFR register ******************/
11093#define RCC_CIFR_LSIRDYF_Pos (0U)
11094#define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
11095#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
11096#define RCC_CIFR_LSERDYF_Pos (1U)
11097#define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
11098#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
11099#define RCC_CIFR_MSIRDYF_Pos (2U)
11100#define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */
11101#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
11102#define RCC_CIFR_HSIRDYF_Pos (3U)
11103#define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
11104#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
11105#define RCC_CIFR_HSERDYF_Pos (4U)
11106#define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
11107#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
11108#define RCC_CIFR_PLLRDYF_Pos (5U)
11109#define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
11110#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
11111#define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
11112#define RCC_CIFR_PLLSAI1RDYF_Msk (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
11113#define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
11114#define RCC_CIFR_PLLSAI2RDYF_Pos (7U)
11115#define RCC_CIFR_PLLSAI2RDYF_Msk (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */
11116#define RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF_Msk
11117#define RCC_CIFR_CSSF_Pos (8U)
11118#define RCC_CIFR_CSSF_Msk (0x1U << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
11119#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
11120#define RCC_CIFR_LSECSSF_Pos (9U)
11121#define RCC_CIFR_LSECSSF_Msk (0x1U << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
11122#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
11123
11124/******************** Bit definition for RCC_CICR register ******************/
11125#define RCC_CICR_LSIRDYC_Pos (0U)
11126#define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
11127#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
11128#define RCC_CICR_LSERDYC_Pos (1U)
11129#define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
11130#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
11131#define RCC_CICR_MSIRDYC_Pos (2U)
11132#define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */
11133#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
11134#define RCC_CICR_HSIRDYC_Pos (3U)
11135#define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
11136#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
11137#define RCC_CICR_HSERDYC_Pos (4U)
11138#define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
11139#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
11140#define RCC_CICR_PLLRDYC_Pos (5U)
11141#define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
11142#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
11143#define RCC_CICR_PLLSAI1RDYC_Pos (6U)
11144#define RCC_CICR_PLLSAI1RDYC_Msk (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
11145#define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
11146#define RCC_CICR_PLLSAI2RDYC_Pos (7U)
11147#define RCC_CICR_PLLSAI2RDYC_Msk (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */
11148#define RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC_Msk
11149#define RCC_CICR_CSSC_Pos (8U)
11150#define RCC_CICR_CSSC_Msk (0x1U << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
11151#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
11152#define RCC_CICR_LSECSSC_Pos (9U)
11153#define RCC_CICR_LSECSSC_Msk (0x1U << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
11154#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
11155
11156/******************** Bit definition for RCC_AHB1RSTR register **************/
11157#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
11158#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
11159#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
11160#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
11161#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
11162#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
11163#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
11164#define RCC_AHB1RSTR_FLASHRST_Msk (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
11165#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
11166#define RCC_AHB1RSTR_CRCRST_Pos (12U)
11167#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
11168#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
11169#define RCC_AHB1RSTR_TSCRST_Pos (16U)
11170#define RCC_AHB1RSTR_TSCRST_Msk (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
11171#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
11172
11173/******************** Bit definition for RCC_AHB2RSTR register **************/
11174#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
11175#define RCC_AHB2RSTR_GPIOARST_Msk (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
11176#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
11177#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
11178#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
11179#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
11180#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
11181#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
11182#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
11183#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
11184#define RCC_AHB2RSTR_GPIODRST_Msk (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
11185#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
11186#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
11187#define RCC_AHB2RSTR_GPIOERST_Msk (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
11188#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
11189#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
11190#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
11191#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
11192#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
11193#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
11194#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
11195#define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
11196#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
11197#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
11198#define RCC_AHB2RSTR_OTGFSRST_Pos (12U)
11199#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */
11200#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
11201#define RCC_AHB2RSTR_ADCRST_Pos (13U)
11202#define RCC_AHB2RSTR_ADCRST_Msk (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
11203#define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
11204#define RCC_AHB2RSTR_AESRST_Pos (16U)
11205#define RCC_AHB2RSTR_AESRST_Msk (0x1U << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */
11206#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk
11207#define RCC_AHB2RSTR_RNGRST_Pos (18U)
11208#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
11209#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
11210
11211/******************** Bit definition for RCC_AHB3RSTR register **************/
11212#define RCC_AHB3RSTR_FMCRST_Pos (0U)
11213#define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
11214#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
11215#define RCC_AHB3RSTR_QSPIRST_Pos (8U)
11216#define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
11217#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
11218
11219/******************** Bit definition for RCC_APB1RSTR1 register **************/
11220#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
11221#define RCC_APB1RSTR1_TIM2RST_Msk (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
11222#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
11223#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
11224#define RCC_APB1RSTR1_TIM3RST_Msk (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
11225#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
11226#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
11227#define RCC_APB1RSTR1_TIM4RST_Msk (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */
11228#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
11229#define RCC_APB1RSTR1_TIM5RST_Pos (3U)
11230#define RCC_APB1RSTR1_TIM5RST_Msk (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */
11231#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
11232#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
11233#define RCC_APB1RSTR1_TIM6RST_Msk (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
11234#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
11235#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
11236#define RCC_APB1RSTR1_TIM7RST_Msk (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
11237#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
11238#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
11239#define RCC_APB1RSTR1_SPI2RST_Msk (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
11240#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
11241#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
11242#define RCC_APB1RSTR1_SPI3RST_Msk (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
11243#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
11244#define RCC_APB1RSTR1_USART2RST_Pos (17U)
11245#define RCC_APB1RSTR1_USART2RST_Msk (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
11246#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
11247#define RCC_APB1RSTR1_USART3RST_Pos (18U)
11248#define RCC_APB1RSTR1_USART3RST_Msk (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
11249#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
11250#define RCC_APB1RSTR1_UART4RST_Pos (19U)
11251#define RCC_APB1RSTR1_UART4RST_Msk (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
11252#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
11253#define RCC_APB1RSTR1_UART5RST_Pos (20U)
11254#define RCC_APB1RSTR1_UART5RST_Msk (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
11255#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
11256#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
11257#define RCC_APB1RSTR1_I2C1RST_Msk (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
11258#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
11259#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
11260#define RCC_APB1RSTR1_I2C2RST_Msk (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
11261#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
11262#define RCC_APB1RSTR1_I2C3RST_Pos (23U)
11263#define RCC_APB1RSTR1_I2C3RST_Msk (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
11264#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
11265#define RCC_APB1RSTR1_CAN1RST_Pos (25U)
11266#define RCC_APB1RSTR1_CAN1RST_Msk (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
11267#define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
11268#define RCC_APB1RSTR1_PWRRST_Pos (28U)
11269#define RCC_APB1RSTR1_PWRRST_Msk (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
11270#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
11271#define RCC_APB1RSTR1_DAC1RST_Pos (29U)
11272#define RCC_APB1RSTR1_DAC1RST_Msk (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
11273#define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
11274#define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
11275#define RCC_APB1RSTR1_OPAMPRST_Msk (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
11276#define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
11277#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
11278#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
11279#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
11280
11281/******************** Bit definition for RCC_APB1RSTR2 register **************/
11282#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
11283#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
11284#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
11285#define RCC_APB1RSTR2_SWPMI1RST_Pos (2U)
11286#define RCC_APB1RSTR2_SWPMI1RST_Msk (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
11287#define RCC_APB1RSTR2_SWPMI1RST RCC_APB1RSTR2_SWPMI1RST_Msk
11288#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
11289#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
11290#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
11291
11292/******************** Bit definition for RCC_APB2RSTR register **************/
11293#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
11294#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
11295#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
11296#define RCC_APB2RSTR_SDMMC1RST_Pos (10U)
11297#define RCC_APB2RSTR_SDMMC1RST_Msk (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */
11298#define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
11299#define RCC_APB2RSTR_TIM1RST_Pos (11U)
11300#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
11301#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
11302#define RCC_APB2RSTR_SPI1RST_Pos (12U)
11303#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
11304#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
11305#define RCC_APB2RSTR_TIM8RST_Pos (13U)
11306#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
11307#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
11308#define RCC_APB2RSTR_USART1RST_Pos (14U)
11309#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
11310#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
11311#define RCC_APB2RSTR_TIM15RST_Pos (16U)
11312#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
11313#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
11314#define RCC_APB2RSTR_TIM16RST_Pos (17U)
11315#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
11316#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
11317#define RCC_APB2RSTR_TIM17RST_Pos (18U)
11318#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
11319#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
11320#define RCC_APB2RSTR_SAI1RST_Pos (21U)
11321#define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
11322#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
11323#define RCC_APB2RSTR_SAI2RST_Pos (22U)
11324#define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */
11325#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
11326#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
11327#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
11328#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
11329
11330/******************** Bit definition for RCC_AHB1ENR register ***************/
11331#define RCC_AHB1ENR_DMA1EN_Pos (0U)
11332#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
11333#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
11334#define RCC_AHB1ENR_DMA2EN_Pos (1U)
11335#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
11336#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
11337#define RCC_AHB1ENR_FLASHEN_Pos (8U)
11338#define RCC_AHB1ENR_FLASHEN_Msk (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
11339#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
11340#define RCC_AHB1ENR_CRCEN_Pos (12U)
11341#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
11342#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
11343#define RCC_AHB1ENR_TSCEN_Pos (16U)
11344#define RCC_AHB1ENR_TSCEN_Msk (0x1U << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
11345#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
11346
11347/******************** Bit definition for RCC_AHB2ENR register ***************/
11348#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
11349#define RCC_AHB2ENR_GPIOAEN_Msk (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
11350#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
11351#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
11352#define RCC_AHB2ENR_GPIOBEN_Msk (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
11353#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
11354#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
11355#define RCC_AHB2ENR_GPIOCEN_Msk (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
11356#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
11357#define RCC_AHB2ENR_GPIODEN_Pos (3U)
11358#define RCC_AHB2ENR_GPIODEN_Msk (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
11359#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
11360#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
11361#define RCC_AHB2ENR_GPIOEEN_Msk (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
11362#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
11363#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
11364#define RCC_AHB2ENR_GPIOFEN_Msk (0x1U << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */
11365#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
11366#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
11367#define RCC_AHB2ENR_GPIOGEN_Msk (0x1U << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */
11368#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
11369#define RCC_AHB2ENR_GPIOHEN_Pos (7U)
11370#define RCC_AHB2ENR_GPIOHEN_Msk (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
11371#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
11372#define RCC_AHB2ENR_OTGFSEN_Pos (12U)
11373#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */
11374#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
11375#define RCC_AHB2ENR_ADCEN_Pos (13U)
11376#define RCC_AHB2ENR_ADCEN_Msk (0x1U << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */
11377#define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
11378#define RCC_AHB2ENR_AESEN_Pos (16U)
11379#define RCC_AHB2ENR_AESEN_Msk (0x1U << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00010000 */
11380#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk
11381#define RCC_AHB2ENR_RNGEN_Pos (18U)
11382#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
11383#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
11384
11385/******************** Bit definition for RCC_AHB3ENR register ***************/
11386#define RCC_AHB3ENR_FMCEN_Pos (0U)
11387#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
11388#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
11389#define RCC_AHB3ENR_QSPIEN_Pos (8U)
11390#define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
11391#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
11392
11393/******************** Bit definition for RCC_APB1ENR1 register ***************/
11394#define RCC_APB1ENR1_TIM2EN_Pos (0U)
11395#define RCC_APB1ENR1_TIM2EN_Msk (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
11396#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
11397#define RCC_APB1ENR1_TIM3EN_Pos (1U)
11398#define RCC_APB1ENR1_TIM3EN_Msk (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */
11399#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
11400#define RCC_APB1ENR1_TIM4EN_Pos (2U)
11401#define RCC_APB1ENR1_TIM4EN_Msk (0x1U << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */
11402#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
11403#define RCC_APB1ENR1_TIM5EN_Pos (3U)
11404#define RCC_APB1ENR1_TIM5EN_Msk (0x1U << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */
11405#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
11406#define RCC_APB1ENR1_TIM6EN_Pos (4U)
11407#define RCC_APB1ENR1_TIM6EN_Msk (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
11408#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
11409#define RCC_APB1ENR1_TIM7EN_Pos (5U)
11410#define RCC_APB1ENR1_TIM7EN_Msk (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
11411#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
11412#define RCC_APB1ENR1_WWDGEN_Pos (11U)
11413#define RCC_APB1ENR1_WWDGEN_Msk (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
11414#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
11415#define RCC_APB1ENR1_SPI2EN_Pos (14U)
11416#define RCC_APB1ENR1_SPI2EN_Msk (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
11417#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
11418#define RCC_APB1ENR1_SPI3EN_Pos (15U)
11419#define RCC_APB1ENR1_SPI3EN_Msk (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
11420#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
11421#define RCC_APB1ENR1_USART2EN_Pos (17U)
11422#define RCC_APB1ENR1_USART2EN_Msk (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
11423#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
11424#define RCC_APB1ENR1_USART3EN_Pos (18U)
11425#define RCC_APB1ENR1_USART3EN_Msk (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
11426#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
11427#define RCC_APB1ENR1_UART4EN_Pos (19U)
11428#define RCC_APB1ENR1_UART4EN_Msk (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
11429#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
11430#define RCC_APB1ENR1_UART5EN_Pos (20U)
11431#define RCC_APB1ENR1_UART5EN_Msk (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */
11432#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
11433#define RCC_APB1ENR1_I2C1EN_Pos (21U)
11434#define RCC_APB1ENR1_I2C1EN_Msk (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
11435#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
11436#define RCC_APB1ENR1_I2C2EN_Pos (22U)
11437#define RCC_APB1ENR1_I2C2EN_Msk (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
11438#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
11439#define RCC_APB1ENR1_I2C3EN_Pos (23U)
11440#define RCC_APB1ENR1_I2C3EN_Msk (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
11441#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
11442#define RCC_APB1ENR1_CAN1EN_Pos (25U)
11443#define RCC_APB1ENR1_CAN1EN_Msk (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
11444#define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
11445#define RCC_APB1ENR1_PWREN_Pos (28U)
11446#define RCC_APB1ENR1_PWREN_Msk (0x1U << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
11447#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
11448#define RCC_APB1ENR1_DAC1EN_Pos (29U)
11449#define RCC_APB1ENR1_DAC1EN_Msk (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
11450#define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
11451#define RCC_APB1ENR1_OPAMPEN_Pos (30U)
11452#define RCC_APB1ENR1_OPAMPEN_Msk (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
11453#define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
11454#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
11455#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
11456#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
11457
11458/******************** Bit definition for RCC_APB1RSTR2 register **************/
11459#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
11460#define RCC_APB1ENR2_LPUART1EN_Msk (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
11461#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
11462#define RCC_APB1ENR2_SWPMI1EN_Pos (2U)
11463#define RCC_APB1ENR2_SWPMI1EN_Msk (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
11464#define RCC_APB1ENR2_SWPMI1EN RCC_APB1ENR2_SWPMI1EN_Msk
11465#define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
11466#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
11467#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
11468
11469/******************** Bit definition for RCC_APB2ENR register ***************/
11470#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
11471#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
11472#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
11473#define RCC_APB2ENR_FWEN_Pos (7U)
11474#define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
11475#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
11476#define RCC_APB2ENR_SDMMC1EN_Pos (10U)
11477#define RCC_APB2ENR_SDMMC1EN_Msk (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */
11478#define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
11479#define RCC_APB2ENR_TIM1EN_Pos (11U)
11480#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
11481#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
11482#define RCC_APB2ENR_SPI1EN_Pos (12U)
11483#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
11484#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
11485#define RCC_APB2ENR_TIM8EN_Pos (13U)
11486#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
11487#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
11488#define RCC_APB2ENR_USART1EN_Pos (14U)
11489#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
11490#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
11491#define RCC_APB2ENR_TIM15EN_Pos (16U)
11492#define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
11493#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
11494#define RCC_APB2ENR_TIM16EN_Pos (17U)
11495#define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
11496#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
11497#define RCC_APB2ENR_TIM17EN_Pos (18U)
11498#define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
11499#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
11500#define RCC_APB2ENR_SAI1EN_Pos (21U)
11501#define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
11502#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
11503#define RCC_APB2ENR_SAI2EN_Pos (22U)
11504#define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */
11505#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
11506#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
11507#define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
11508#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
11509
11510/******************** Bit definition for RCC_AHB1SMENR register ***************/
11511#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
11512#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
11513#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
11514#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
11515#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
11516#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
11517#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
11518#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
11519#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
11520#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
11521#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
11522#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
11523#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
11524#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
11525#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
11526#define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
11527#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
11528#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
11529
11530/******************** Bit definition for RCC_AHB2SMENR register *************/
11531#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
11532#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
11533#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
11534#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
11535#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
11536#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
11537#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
11538#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
11539#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
11540#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
11541#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
11542#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
11543#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
11544#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
11545#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
11546#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
11547#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
11548#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
11549#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
11550#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */
11551#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
11552#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
11553#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
11554#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
11555#define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
11556#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
11557#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
11558#define RCC_AHB2SMENR_OTGFSSMEN_Pos (12U)
11559#define RCC_AHB2SMENR_OTGFSSMEN_Msk (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */
11560#define RCC_AHB2SMENR_OTGFSSMEN RCC_AHB2SMENR_OTGFSSMEN_Msk
11561#define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
11562#define RCC_AHB2SMENR_ADCSMEN_Msk (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
11563#define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
11564#define RCC_AHB2SMENR_AESSMEN_Pos (16U)
11565#define RCC_AHB2SMENR_AESSMEN_Msk (0x1U << RCC_AHB2SMENR_AESSMEN_Pos) /*!< 0x00010000 */
11566#define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk
11567#define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
11568#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
11569#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
11570
11571/******************** Bit definition for RCC_AHB3SMENR register *************/
11572#define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
11573#define RCC_AHB3SMENR_FMCSMEN_Msk (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */
11574#define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
11575#define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
11576#define RCC_AHB3SMENR_QSPISMEN_Msk (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
11577#define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
11578
11579/******************** Bit definition for RCC_APB1SMENR1 register *************/
11580#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
11581#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
11582#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
11583#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
11584#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
11585#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
11586#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
11587#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
11588#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
11589#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
11590#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
11591#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
11592#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
11593#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
11594#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
11595#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
11596#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
11597#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
11598#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
11599#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
11600#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
11601#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
11602#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
11603#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
11604#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
11605#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
11606#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
11607#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
11608#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
11609#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
11610#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
11611#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
11612#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
11613#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
11614#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
11615#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
11616#define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
11617#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
11618#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
11619#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
11620#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
11621#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
11622#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
11623#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
11624#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
11625#define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
11626#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
11627#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
11628#define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
11629#define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
11630#define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
11631#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
11632#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
11633#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
11634#define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
11635#define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
11636#define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
11637#define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
11638#define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
11639#define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
11640#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
11641#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
11642#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
11643
11644/******************** Bit definition for RCC_APB1SMENR2 register *************/
11645#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
11646#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
11647#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
11648#define RCC_APB1SMENR2_SWPMI1SMEN_Pos (2U)
11649#define RCC_APB1SMENR2_SWPMI1SMEN_Msk (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
11650#define RCC_APB1SMENR2_SWPMI1SMEN RCC_APB1SMENR2_SWPMI1SMEN_Msk
11651#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
11652#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
11653#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
11654
11655/******************** Bit definition for RCC_APB2SMENR register *************/
11656#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
11657#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
11658#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
11659#define RCC_APB2SMENR_SDMMC1SMEN_Pos (10U)
11660#define RCC_APB2SMENR_SDMMC1SMEN_Msk (0x1U << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */
11661#define RCC_APB2SMENR_SDMMC1SMEN RCC_APB2SMENR_SDMMC1SMEN_Msk
11662#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
11663#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
11664#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
11665#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
11666#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
11667#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
11668#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
11669#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
11670#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
11671#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
11672#define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
11673#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
11674#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
11675#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
11676#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
11677#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
11678#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
11679#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
11680#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
11681#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
11682#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
11683#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
11684#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
11685#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
11686#define RCC_APB2SMENR_SAI2SMEN_Pos (22U)
11687#define RCC_APB2SMENR_SAI2SMEN_Msk (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
11688#define RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk
11689#define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
11690#define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
11691#define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
11692
11693/******************** Bit definition for RCC_CCIPR register ******************/
11694#define RCC_CCIPR_USART1SEL_Pos (0U)
11695#define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
11696#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
11697#define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
11698#define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
11699
11700#define RCC_CCIPR_USART2SEL_Pos (2U)
11701#define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
11702#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
11703#define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
11704#define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
11705
11706#define RCC_CCIPR_USART3SEL_Pos (4U)
11707#define RCC_CCIPR_USART3SEL_Msk (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
11708#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
11709#define RCC_CCIPR_USART3SEL_0 (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
11710#define RCC_CCIPR_USART3SEL_1 (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
11711
11712#define RCC_CCIPR_UART4SEL_Pos (6U)
11713#define RCC_CCIPR_UART4SEL_Msk (0x3U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
11714#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
11715#define RCC_CCIPR_UART4SEL_0 (0x1U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
11716#define RCC_CCIPR_UART4SEL_1 (0x2U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
11717
11718#define RCC_CCIPR_UART5SEL_Pos (8U)
11719#define RCC_CCIPR_UART5SEL_Msk (0x3U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
11720#define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
11721#define RCC_CCIPR_UART5SEL_0 (0x1U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
11722#define RCC_CCIPR_UART5SEL_1 (0x2U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
11723
11724#define RCC_CCIPR_LPUART1SEL_Pos (10U)
11725#define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
11726#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
11727#define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
11728#define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
11729
11730#define RCC_CCIPR_I2C1SEL_Pos (12U)
11731#define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
11732#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
11733#define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
11734#define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
11735
11736#define RCC_CCIPR_I2C2SEL_Pos (14U)
11737#define RCC_CCIPR_I2C2SEL_Msk (0x3U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
11738#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
11739#define RCC_CCIPR_I2C2SEL_0 (0x1U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
11740#define RCC_CCIPR_I2C2SEL_1 (0x2U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
11741
11742#define RCC_CCIPR_I2C3SEL_Pos (16U)
11743#define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
11744#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
11745#define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
11746#define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
11747
11748#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
11749#define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
11750#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
11751#define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
11752#define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
11753
11754#define RCC_CCIPR_LPTIM2SEL_Pos (20U)
11755#define RCC_CCIPR_LPTIM2SEL_Msk (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
11756#define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
11757#define RCC_CCIPR_LPTIM2SEL_0 (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
11758#define RCC_CCIPR_LPTIM2SEL_1 (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
11759
11760#define RCC_CCIPR_SAI1SEL_Pos (22U)
11761#define RCC_CCIPR_SAI1SEL_Msk (0x3U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00C00000 */
11762#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
11763#define RCC_CCIPR_SAI1SEL_0 (0x1U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00400000 */
11764#define RCC_CCIPR_SAI1SEL_1 (0x2U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00800000 */
11765
11766#define RCC_CCIPR_SAI2SEL_Pos (24U)
11767#define RCC_CCIPR_SAI2SEL_Msk (0x3U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x03000000 */
11768#define RCC_CCIPR_SAI2SEL RCC_CCIPR_SAI2SEL_Msk
11769#define RCC_CCIPR_SAI2SEL_0 (0x1U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x01000000 */
11770#define RCC_CCIPR_SAI2SEL_1 (0x2U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x02000000 */
11771
11772#define RCC_CCIPR_CLK48SEL_Pos (26U)
11773#define RCC_CCIPR_CLK48SEL_Msk (0x3U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
11774#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
11775#define RCC_CCIPR_CLK48SEL_0 (0x1U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
11776#define RCC_CCIPR_CLK48SEL_1 (0x2U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
11777
11778#define RCC_CCIPR_ADCSEL_Pos (28U)
11779#define RCC_CCIPR_ADCSEL_Msk (0x3U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */
11780#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
11781#define RCC_CCIPR_ADCSEL_0 (0x1U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */
11782#define RCC_CCIPR_ADCSEL_1 (0x2U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */
11783
11784#define RCC_CCIPR_SWPMI1SEL_Pos (30U)
11785#define RCC_CCIPR_SWPMI1SEL_Msk (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
11786#define RCC_CCIPR_SWPMI1SEL RCC_CCIPR_SWPMI1SEL_Msk
11787
11788#define RCC_CCIPR_DFSDM1SEL_Pos (31U)
11789#define RCC_CCIPR_DFSDM1SEL_Msk (0x1U << RCC_CCIPR_DFSDM1SEL_Pos) /*!< 0x80000000 */
11790#define RCC_CCIPR_DFSDM1SEL RCC_CCIPR_DFSDM1SEL_Msk
11791
11792/******************** Bit definition for RCC_BDCR register ******************/
11793#define RCC_BDCR_LSEON_Pos (0U)
11794#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
11795#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
11796#define RCC_BDCR_LSERDY_Pos (1U)
11797#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
11798#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
11799#define RCC_BDCR_LSEBYP_Pos (2U)
11800#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
11801#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
11802
11803#define RCC_BDCR_LSEDRV_Pos (3U)
11804#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
11805#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
11806#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
11807#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
11808
11809#define RCC_BDCR_LSECSSON_Pos (5U)
11810#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
11811#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
11812#define RCC_BDCR_LSECSSD_Pos (6U)
11813#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
11814#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
11815
11816#define RCC_BDCR_RTCSEL_Pos (8U)
11817#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
11818#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
11819#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
11820#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
11821
11822#define RCC_BDCR_RTCEN_Pos (15U)
11823#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
11824#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
11825#define RCC_BDCR_BDRST_Pos (16U)
11826#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
11827#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
11828#define RCC_BDCR_LSCOEN_Pos (24U)
11829#define RCC_BDCR_LSCOEN_Msk (0x1U << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
11830#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
11831#define RCC_BDCR_LSCOSEL_Pos (25U)
11832#define RCC_BDCR_LSCOSEL_Msk (0x1U << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
11833#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
11834
11835/******************** Bit definition for RCC_CSR register *******************/
11836#define RCC_CSR_LSION_Pos (0U)
11837#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
11838#define RCC_CSR_LSION RCC_CSR_LSION_Msk
11839#define RCC_CSR_LSIRDY_Pos (1U)
11840#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
11841#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
11842
11843#define RCC_CSR_MSISRANGE_Pos (8U)
11844#define RCC_CSR_MSISRANGE_Msk (0xFU << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */
11845#define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
11846#define RCC_CSR_MSISRANGE_1 (0x4U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */
11847#define RCC_CSR_MSISRANGE_2 (0x5U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */
11848#define RCC_CSR_MSISRANGE_4 (0x6U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */
11849#define RCC_CSR_MSISRANGE_8 (0x7U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */
11850
11851#define RCC_CSR_RMVF_Pos (23U)
11852#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
11853#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
11854#define RCC_CSR_FWRSTF_Pos (24U)
11855#define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
11856#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
11857#define RCC_CSR_OBLRSTF_Pos (25U)
11858#define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
11859#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
11860#define RCC_CSR_PINRSTF_Pos (26U)
11861#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
11862#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
11863#define RCC_CSR_BORRSTF_Pos (27U)
11864#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
11865#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
11866#define RCC_CSR_SFTRSTF_Pos (28U)
11867#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
11868#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
11869#define RCC_CSR_IWDGRSTF_Pos (29U)
11870#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
11871#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
11872#define RCC_CSR_WWDGRSTF_Pos (30U)
11873#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
11874#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
11875#define RCC_CSR_LPWRRSTF_Pos (31U)
11876#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
11877#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
11878
11879/******************************************************************************/
11880/* */
11881/* RNG */
11882/* */
11883/******************************************************************************/
11884/******************** Bits definition for RNG_CR register *******************/
11885#define RNG_CR_RNGEN_Pos (2U)
11886#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
11887#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
11888#define RNG_CR_IE_Pos (3U)
11889#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
11890#define RNG_CR_IE RNG_CR_IE_Msk
11891
11892/******************** Bits definition for RNG_SR register *******************/
11893#define RNG_SR_DRDY_Pos (0U)
11894#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
11895#define RNG_SR_DRDY RNG_SR_DRDY_Msk
11896#define RNG_SR_CECS_Pos (1U)
11897#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
11898#define RNG_SR_CECS RNG_SR_CECS_Msk
11899#define RNG_SR_SECS_Pos (2U)
11900#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
11901#define RNG_SR_SECS RNG_SR_SECS_Msk
11902#define RNG_SR_CEIS_Pos (5U)
11903#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
11904#define RNG_SR_CEIS RNG_SR_CEIS_Msk
11905#define RNG_SR_SEIS_Pos (6U)
11906#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
11907#define RNG_SR_SEIS RNG_SR_SEIS_Msk
11908
11909/******************************************************************************/
11910/* */
11911/* Real-Time Clock (RTC) */
11912/* */
11913/******************************************************************************/
11914/*
11915* @brief Specific device feature definitions
11916*/
11917#define RTC_TAMPER1_SUPPORT
11918#define RTC_TAMPER2_SUPPORT
11919#define RTC_TAMPER3_SUPPORT
11920#define RTC_WAKEUP_SUPPORT
11921#define RTC_BACKUP_SUPPORT
11922
11923/******************** Bits definition for RTC_TR register *******************/
11924#define RTC_TR_PM_Pos (22U)
11925#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
11926#define RTC_TR_PM RTC_TR_PM_Msk
11927#define RTC_TR_HT_Pos (20U)
11928#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
11929#define RTC_TR_HT RTC_TR_HT_Msk
11930#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
11931#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
11932#define RTC_TR_HU_Pos (16U)
11933#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
11934#define RTC_TR_HU RTC_TR_HU_Msk
11935#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
11936#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
11937#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
11938#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
11939#define RTC_TR_MNT_Pos (12U)
11940#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
11941#define RTC_TR_MNT RTC_TR_MNT_Msk
11942#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
11943#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
11944#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
11945#define RTC_TR_MNU_Pos (8U)
11946#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
11947#define RTC_TR_MNU RTC_TR_MNU_Msk
11948#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
11949#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
11950#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
11951#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
11952#define RTC_TR_ST_Pos (4U)
11953#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
11954#define RTC_TR_ST RTC_TR_ST_Msk
11955#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
11956#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
11957#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
11958#define RTC_TR_SU_Pos (0U)
11959#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
11960#define RTC_TR_SU RTC_TR_SU_Msk
11961#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
11962#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
11963#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
11964#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
11965
11966/******************** Bits definition for RTC_DR register *******************/
11967#define RTC_DR_YT_Pos (20U)
11968#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
11969#define RTC_DR_YT RTC_DR_YT_Msk
11970#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
11971#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
11972#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
11973#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
11974#define RTC_DR_YU_Pos (16U)
11975#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
11976#define RTC_DR_YU RTC_DR_YU_Msk
11977#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
11978#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
11979#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
11980#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
11981#define RTC_DR_WDU_Pos (13U)
11982#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
11983#define RTC_DR_WDU RTC_DR_WDU_Msk
11984#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
11985#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
11986#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
11987#define RTC_DR_MT_Pos (12U)
11988#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
11989#define RTC_DR_MT RTC_DR_MT_Msk
11990#define RTC_DR_MU_Pos (8U)
11991#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
11992#define RTC_DR_MU RTC_DR_MU_Msk
11993#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
11994#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
11995#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
11996#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
11997#define RTC_DR_DT_Pos (4U)
11998#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
11999#define RTC_DR_DT RTC_DR_DT_Msk
12000#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
12001#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
12002#define RTC_DR_DU_Pos (0U)
12003#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
12004#define RTC_DR_DU RTC_DR_DU_Msk
12005#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
12006#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
12007#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
12008#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
12009
12010/******************** Bits definition for RTC_CR register *******************/
12011#define RTC_CR_ITSE_Pos (24U)
12012#define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
12013#define RTC_CR_ITSE RTC_CR_ITSE_Msk
12014#define RTC_CR_COE_Pos (23U)
12015#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
12016#define RTC_CR_COE RTC_CR_COE_Msk
12017#define RTC_CR_OSEL_Pos (21U)
12018#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
12019#define RTC_CR_OSEL RTC_CR_OSEL_Msk
12020#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
12021#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
12022#define RTC_CR_POL_Pos (20U)
12023#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
12024#define RTC_CR_POL RTC_CR_POL_Msk
12025#define RTC_CR_COSEL_Pos (19U)
12026#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
12027#define RTC_CR_COSEL RTC_CR_COSEL_Msk
12028#define RTC_CR_BKP_Pos (18U)
12029#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
12030#define RTC_CR_BKP RTC_CR_BKP_Msk
12031#define RTC_CR_SUB1H_Pos (17U)
12032#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
12033#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
12034#define RTC_CR_ADD1H_Pos (16U)
12035#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
12036#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
12037#define RTC_CR_TSIE_Pos (15U)
12038#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
12039#define RTC_CR_TSIE RTC_CR_TSIE_Msk
12040#define RTC_CR_WUTIE_Pos (14U)
12041#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
12042#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
12043#define RTC_CR_ALRBIE_Pos (13U)
12044#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
12045#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
12046#define RTC_CR_ALRAIE_Pos (12U)
12047#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
12048#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
12049#define RTC_CR_TSE_Pos (11U)
12050#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
12051#define RTC_CR_TSE RTC_CR_TSE_Msk
12052#define RTC_CR_WUTE_Pos (10U)
12053#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
12054#define RTC_CR_WUTE RTC_CR_WUTE_Msk
12055#define RTC_CR_ALRBE_Pos (9U)
12056#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
12057#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
12058#define RTC_CR_ALRAE_Pos (8U)
12059#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
12060#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
12061#define RTC_CR_FMT_Pos (6U)
12062#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
12063#define RTC_CR_FMT RTC_CR_FMT_Msk
12064#define RTC_CR_BYPSHAD_Pos (5U)
12065#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
12066#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
12067#define RTC_CR_REFCKON_Pos (4U)
12068#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
12069#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
12070#define RTC_CR_TSEDGE_Pos (3U)
12071#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
12072#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
12073#define RTC_CR_WUCKSEL_Pos (0U)
12074#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
12075#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
12076#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
12077#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
12078#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
12079
12080/* Legacy defines */
12081#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
12082#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
12083#define RTC_CR_BCK RTC_CR_BKP
12084
12085/******************** Bits definition for RTC_ISR register ******************/
12086#define RTC_ISR_ITSF_Pos (17U)
12087#define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
12088#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
12089#define RTC_ISR_RECALPF_Pos (16U)
12090#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
12091#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
12092#define RTC_ISR_TAMP3F_Pos (15U)
12093#define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
12094#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
12095#define RTC_ISR_TAMP2F_Pos (14U)
12096#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
12097#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
12098#define RTC_ISR_TAMP1F_Pos (13U)
12099#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
12100#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
12101#define RTC_ISR_TSOVF_Pos (12U)
12102#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
12103#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
12104#define RTC_ISR_TSF_Pos (11U)
12105#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
12106#define RTC_ISR_TSF RTC_ISR_TSF_Msk
12107#define RTC_ISR_WUTF_Pos (10U)
12108#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
12109#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
12110#define RTC_ISR_ALRBF_Pos (9U)
12111#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
12112#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
12113#define RTC_ISR_ALRAF_Pos (8U)
12114#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
12115#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
12116#define RTC_ISR_INIT_Pos (7U)
12117#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
12118#define RTC_ISR_INIT RTC_ISR_INIT_Msk
12119#define RTC_ISR_INITF_Pos (6U)
12120#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
12121#define RTC_ISR_INITF RTC_ISR_INITF_Msk
12122#define RTC_ISR_RSF_Pos (5U)
12123#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
12124#define RTC_ISR_RSF RTC_ISR_RSF_Msk
12125#define RTC_ISR_INITS_Pos (4U)
12126#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
12127#define RTC_ISR_INITS RTC_ISR_INITS_Msk
12128#define RTC_ISR_SHPF_Pos (3U)
12129#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
12130#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
12131#define RTC_ISR_WUTWF_Pos (2U)
12132#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
12133#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
12134#define RTC_ISR_ALRBWF_Pos (1U)
12135#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
12136#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
12137#define RTC_ISR_ALRAWF_Pos (0U)
12138#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
12139#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
12140
12141/******************** Bits definition for RTC_PRER register *****************/
12142#define RTC_PRER_PREDIV_A_Pos (16U)
12143#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
12144#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
12145#define RTC_PRER_PREDIV_S_Pos (0U)
12146#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
12147#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
12148
12149/******************** Bits definition for RTC_WUTR register *****************/
12150#define RTC_WUTR_WUT_Pos (0U)
12151#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
12152#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
12153
12154/******************** Bits definition for RTC_ALRMAR register ***************/
12155#define RTC_ALRMAR_MSK4_Pos (31U)
12156#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
12157#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
12158#define RTC_ALRMAR_WDSEL_Pos (30U)
12159#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
12160#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
12161#define RTC_ALRMAR_DT_Pos (28U)
12162#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
12163#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
12164#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
12165#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
12166#define RTC_ALRMAR_DU_Pos (24U)
12167#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
12168#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
12169#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
12170#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
12171#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
12172#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
12173#define RTC_ALRMAR_MSK3_Pos (23U)
12174#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
12175#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
12176#define RTC_ALRMAR_PM_Pos (22U)
12177#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
12178#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
12179#define RTC_ALRMAR_HT_Pos (20U)
12180#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
12181#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
12182#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
12183#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
12184#define RTC_ALRMAR_HU_Pos (16U)
12185#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
12186#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
12187#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
12188#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
12189#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
12190#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
12191#define RTC_ALRMAR_MSK2_Pos (15U)
12192#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
12193#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
12194#define RTC_ALRMAR_MNT_Pos (12U)
12195#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
12196#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
12197#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
12198#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
12199#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
12200#define RTC_ALRMAR_MNU_Pos (8U)
12201#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
12202#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
12203#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
12204#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
12205#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
12206#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
12207#define RTC_ALRMAR_MSK1_Pos (7U)
12208#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
12209#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
12210#define RTC_ALRMAR_ST_Pos (4U)
12211#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
12212#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
12213#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
12214#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
12215#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
12216#define RTC_ALRMAR_SU_Pos (0U)
12217#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
12218#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
12219#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
12220#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
12221#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
12222#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
12223
12224/******************** Bits definition for RTC_ALRMBR register ***************/
12225#define RTC_ALRMBR_MSK4_Pos (31U)
12226#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
12227#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
12228#define RTC_ALRMBR_WDSEL_Pos (30U)
12229#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
12230#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
12231#define RTC_ALRMBR_DT_Pos (28U)
12232#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
12233#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
12234#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
12235#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
12236#define RTC_ALRMBR_DU_Pos (24U)
12237#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
12238#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
12239#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
12240#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
12241#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
12242#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
12243#define RTC_ALRMBR_MSK3_Pos (23U)
12244#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
12245#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
12246#define RTC_ALRMBR_PM_Pos (22U)
12247#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
12248#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
12249#define RTC_ALRMBR_HT_Pos (20U)
12250#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
12251#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
12252#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
12253#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
12254#define RTC_ALRMBR_HU_Pos (16U)
12255#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
12256#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
12257#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
12258#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
12259#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
12260#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
12261#define RTC_ALRMBR_MSK2_Pos (15U)
12262#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
12263#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
12264#define RTC_ALRMBR_MNT_Pos (12U)
12265#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
12266#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
12267#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
12268#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
12269#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
12270#define RTC_ALRMBR_MNU_Pos (8U)
12271#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
12272#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
12273#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
12274#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
12275#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
12276#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
12277#define RTC_ALRMBR_MSK1_Pos (7U)
12278#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
12279#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
12280#define RTC_ALRMBR_ST_Pos (4U)
12281#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
12282#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
12283#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
12284#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
12285#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
12286#define RTC_ALRMBR_SU_Pos (0U)
12287#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
12288#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
12289#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
12290#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
12291#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
12292#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
12293
12294/******************** Bits definition for RTC_WPR register ******************/
12295#define RTC_WPR_KEY_Pos (0U)
12296#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
12297#define RTC_WPR_KEY RTC_WPR_KEY_Msk
12298
12299/******************** Bits definition for RTC_SSR register ******************/
12300#define RTC_SSR_SS_Pos (0U)
12301#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
12302#define RTC_SSR_SS RTC_SSR_SS_Msk
12303
12304/******************** Bits definition for RTC_SHIFTR register ***************/
12305#define RTC_SHIFTR_SUBFS_Pos (0U)
12306#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
12307#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
12308#define RTC_SHIFTR_ADD1S_Pos (31U)
12309#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
12310#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
12311
12312/******************** Bits definition for RTC_TSTR register *****************/
12313#define RTC_TSTR_PM_Pos (22U)
12314#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
12315#define RTC_TSTR_PM RTC_TSTR_PM_Msk
12316#define RTC_TSTR_HT_Pos (20U)
12317#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
12318#define RTC_TSTR_HT RTC_TSTR_HT_Msk
12319#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
12320#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
12321#define RTC_TSTR_HU_Pos (16U)
12322#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
12323#define RTC_TSTR_HU RTC_TSTR_HU_Msk
12324#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
12325#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
12326#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
12327#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
12328#define RTC_TSTR_MNT_Pos (12U)
12329#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
12330#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
12331#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
12332#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
12333#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
12334#define RTC_TSTR_MNU_Pos (8U)
12335#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
12336#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
12337#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
12338#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
12339#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
12340#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
12341#define RTC_TSTR_ST_Pos (4U)
12342#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
12343#define RTC_TSTR_ST RTC_TSTR_ST_Msk
12344#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
12345#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
12346#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
12347#define RTC_TSTR_SU_Pos (0U)
12348#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
12349#define RTC_TSTR_SU RTC_TSTR_SU_Msk
12350#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
12351#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
12352#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
12353#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
12354
12355/******************** Bits definition for RTC_TSDR register *****************/
12356#define RTC_TSDR_WDU_Pos (13U)
12357#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
12358#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
12359#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
12360#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
12361#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
12362#define RTC_TSDR_MT_Pos (12U)
12363#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
12364#define RTC_TSDR_MT RTC_TSDR_MT_Msk
12365#define RTC_TSDR_MU_Pos (8U)
12366#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
12367#define RTC_TSDR_MU RTC_TSDR_MU_Msk
12368#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
12369#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
12370#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
12371#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
12372#define RTC_TSDR_DT_Pos (4U)
12373#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
12374#define RTC_TSDR_DT RTC_TSDR_DT_Msk
12375#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
12376#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
12377#define RTC_TSDR_DU_Pos (0U)
12378#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
12379#define RTC_TSDR_DU RTC_TSDR_DU_Msk
12380#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
12381#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
12382#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
12383#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
12384
12385/******************** Bits definition for RTC_TSSSR register ****************/
12386#define RTC_TSSSR_SS_Pos (0U)
12387#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
12388#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
12389
12390/******************** Bits definition for RTC_CAL register *****************/
12391#define RTC_CALR_CALP_Pos (15U)
12392#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
12393#define RTC_CALR_CALP RTC_CALR_CALP_Msk
12394#define RTC_CALR_CALW8_Pos (14U)
12395#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
12396#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
12397#define RTC_CALR_CALW16_Pos (13U)
12398#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
12399#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
12400#define RTC_CALR_CALM_Pos (0U)
12401#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
12402#define RTC_CALR_CALM RTC_CALR_CALM_Msk
12403#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
12404#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
12405#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
12406#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
12407#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
12408#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
12409#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
12410#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
12411#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
12412
12413/******************** Bits definition for RTC_TAMPCR register ***************/
12414#define RTC_TAMPCR_TAMP3MF_Pos (24U)
12415#define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
12416#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
12417#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
12418#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
12419#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
12420#define RTC_TAMPCR_TAMP3IE_Pos (22U)
12421#define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
12422#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
12423#define RTC_TAMPCR_TAMP2MF_Pos (21U)
12424#define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
12425#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
12426#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
12427#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
12428#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
12429#define RTC_TAMPCR_TAMP2IE_Pos (19U)
12430#define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
12431#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
12432#define RTC_TAMPCR_TAMP1MF_Pos (18U)
12433#define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
12434#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
12435#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
12436#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
12437#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
12438#define RTC_TAMPCR_TAMP1IE_Pos (16U)
12439#define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
12440#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
12441#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
12442#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
12443#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
12444#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
12445#define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
12446#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
12447#define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
12448#define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
12449#define RTC_TAMPCR_TAMPFLT_Pos (11U)
12450#define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
12451#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
12452#define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
12453#define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
12454#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
12455#define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
12456#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
12457#define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
12458#define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
12459#define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
12460#define RTC_TAMPCR_TAMPTS_Pos (7U)
12461#define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
12462#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
12463#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
12464#define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
12465#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
12466#define RTC_TAMPCR_TAMP3E_Pos (5U)
12467#define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
12468#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
12469#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
12470#define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
12471#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
12472#define RTC_TAMPCR_TAMP2E_Pos (3U)
12473#define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
12474#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
12475#define RTC_TAMPCR_TAMPIE_Pos (2U)
12476#define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
12477#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
12478#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
12479#define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
12480#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
12481#define RTC_TAMPCR_TAMP1E_Pos (0U)
12482#define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
12483#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
12484
12485/******************** Bits definition for RTC_ALRMASSR register *************/
12486#define RTC_ALRMASSR_MASKSS_Pos (24U)
12487#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
12488#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
12489#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
12490#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
12491#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
12492#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
12493#define RTC_ALRMASSR_SS_Pos (0U)
12494#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
12495#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
12496
12497/******************** Bits definition for RTC_ALRMBSSR register *************/
12498#define RTC_ALRMBSSR_MASKSS_Pos (24U)
12499#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
12500#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
12501#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
12502#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
12503#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
12504#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
12505#define RTC_ALRMBSSR_SS_Pos (0U)
12506#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
12507#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
12508
12509/******************** Bits definition for RTC_0R register *******************/
12510#define RTC_OR_OUT_RMP_Pos (1U)
12511#define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
12512#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
12513#define RTC_OR_ALARMOUTTYPE_Pos (0U)
12514#define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
12515#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
12516
12517
12518/******************** Bits definition for RTC_BKP0R register ****************/
12519#define RTC_BKP0R_Pos (0U)
12520#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
12521#define RTC_BKP0R RTC_BKP0R_Msk
12522
12523/******************** Bits definition for RTC_BKP1R register ****************/
12524#define RTC_BKP1R_Pos (0U)
12525#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
12526#define RTC_BKP1R RTC_BKP1R_Msk
12527
12528/******************** Bits definition for RTC_BKP2R register ****************/
12529#define RTC_BKP2R_Pos (0U)
12530#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
12531#define RTC_BKP2R RTC_BKP2R_Msk
12532
12533/******************** Bits definition for RTC_BKP3R register ****************/
12534#define RTC_BKP3R_Pos (0U)
12535#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
12536#define RTC_BKP3R RTC_BKP3R_Msk
12537
12538/******************** Bits definition for RTC_BKP4R register ****************/
12539#define RTC_BKP4R_Pos (0U)
12540#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
12541#define RTC_BKP4R RTC_BKP4R_Msk
12542
12543/******************** Bits definition for RTC_BKP5R register ****************/
12544#define RTC_BKP5R_Pos (0U)
12545#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
12546#define RTC_BKP5R RTC_BKP5R_Msk
12547
12548/******************** Bits definition for RTC_BKP6R register ****************/
12549#define RTC_BKP6R_Pos (0U)
12550#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
12551#define RTC_BKP6R RTC_BKP6R_Msk
12552
12553/******************** Bits definition for RTC_BKP7R register ****************/
12554#define RTC_BKP7R_Pos (0U)
12555#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
12556#define RTC_BKP7R RTC_BKP7R_Msk
12557
12558/******************** Bits definition for RTC_BKP8R register ****************/
12559#define RTC_BKP8R_Pos (0U)
12560#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
12561#define RTC_BKP8R RTC_BKP8R_Msk
12562
12563/******************** Bits definition for RTC_BKP9R register ****************/
12564#define RTC_BKP9R_Pos (0U)
12565#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
12566#define RTC_BKP9R RTC_BKP9R_Msk
12567
12568/******************** Bits definition for RTC_BKP10R register ***************/
12569#define RTC_BKP10R_Pos (0U)
12570#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
12571#define RTC_BKP10R RTC_BKP10R_Msk
12572
12573/******************** Bits definition for RTC_BKP11R register ***************/
12574#define RTC_BKP11R_Pos (0U)
12575#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
12576#define RTC_BKP11R RTC_BKP11R_Msk
12577
12578/******************** Bits definition for RTC_BKP12R register ***************/
12579#define RTC_BKP12R_Pos (0U)
12580#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
12581#define RTC_BKP12R RTC_BKP12R_Msk
12582
12583/******************** Bits definition for RTC_BKP13R register ***************/
12584#define RTC_BKP13R_Pos (0U)
12585#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
12586#define RTC_BKP13R RTC_BKP13R_Msk
12587
12588/******************** Bits definition for RTC_BKP14R register ***************/
12589#define RTC_BKP14R_Pos (0U)
12590#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
12591#define RTC_BKP14R RTC_BKP14R_Msk
12592
12593/******************** Bits definition for RTC_BKP15R register ***************/
12594#define RTC_BKP15R_Pos (0U)
12595#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
12596#define RTC_BKP15R RTC_BKP15R_Msk
12597
12598/******************** Bits definition for RTC_BKP16R register ***************/
12599#define RTC_BKP16R_Pos (0U)
12600#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
12601#define RTC_BKP16R RTC_BKP16R_Msk
12602
12603/******************** Bits definition for RTC_BKP17R register ***************/
12604#define RTC_BKP17R_Pos (0U)
12605#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
12606#define RTC_BKP17R RTC_BKP17R_Msk
12607
12608/******************** Bits definition for RTC_BKP18R register ***************/
12609#define RTC_BKP18R_Pos (0U)
12610#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
12611#define RTC_BKP18R RTC_BKP18R_Msk
12612
12613/******************** Bits definition for RTC_BKP19R register ***************/
12614#define RTC_BKP19R_Pos (0U)
12615#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
12616#define RTC_BKP19R RTC_BKP19R_Msk
12617
12618/******************** Bits definition for RTC_BKP20R register ***************/
12619#define RTC_BKP20R_Pos (0U)
12620#define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
12621#define RTC_BKP20R RTC_BKP20R_Msk
12622
12623/******************** Bits definition for RTC_BKP21R register ***************/
12624#define RTC_BKP21R_Pos (0U)
12625#define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
12626#define RTC_BKP21R RTC_BKP21R_Msk
12627
12628/******************** Bits definition for RTC_BKP22R register ***************/
12629#define RTC_BKP22R_Pos (0U)
12630#define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
12631#define RTC_BKP22R RTC_BKP22R_Msk
12632
12633/******************** Bits definition for RTC_BKP23R register ***************/
12634#define RTC_BKP23R_Pos (0U)
12635#define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
12636#define RTC_BKP23R RTC_BKP23R_Msk
12637
12638/******************** Bits definition for RTC_BKP24R register ***************/
12639#define RTC_BKP24R_Pos (0U)
12640#define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
12641#define RTC_BKP24R RTC_BKP24R_Msk
12642
12643/******************** Bits definition for RTC_BKP25R register ***************/
12644#define RTC_BKP25R_Pos (0U)
12645#define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
12646#define RTC_BKP25R RTC_BKP25R_Msk
12647
12648/******************** Bits definition for RTC_BKP26R register ***************/
12649#define RTC_BKP26R_Pos (0U)
12650#define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
12651#define RTC_BKP26R RTC_BKP26R_Msk
12652
12653/******************** Bits definition for RTC_BKP27R register ***************/
12654#define RTC_BKP27R_Pos (0U)
12655#define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
12656#define RTC_BKP27R RTC_BKP27R_Msk
12657
12658/******************** Bits definition for RTC_BKP28R register ***************/
12659#define RTC_BKP28R_Pos (0U)
12660#define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
12661#define RTC_BKP28R RTC_BKP28R_Msk
12662
12663/******************** Bits definition for RTC_BKP29R register ***************/
12664#define RTC_BKP29R_Pos (0U)
12665#define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
12666#define RTC_BKP29R RTC_BKP29R_Msk
12667
12668/******************** Bits definition for RTC_BKP30R register ***************/
12669#define RTC_BKP30R_Pos (0U)
12670#define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
12671#define RTC_BKP30R RTC_BKP30R_Msk
12672
12673/******************** Bits definition for RTC_BKP31R register ***************/
12674#define RTC_BKP31R_Pos (0U)
12675#define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
12676#define RTC_BKP31R RTC_BKP31R_Msk
12677
12678/******************** Number of backup registers ******************************/
12679#define RTC_BKP_NUMBER 32U
12680
12681/******************************************************************************/
12682/* */
12683/* Serial Audio Interface */
12684/* */
12685/******************************************************************************/
12686/******************** Bit definition for SAI_GCR register *******************/
12687#define SAI_GCR_SYNCIN_Pos (0U)
12688#define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
12689#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
12690#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
12691#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
12692
12693#define SAI_GCR_SYNCOUT_Pos (4U)
12694#define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
12695#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
12696#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
12697#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
12698
12699/******************* Bit definition for SAI_xCR1 register *******************/
12700#define SAI_xCR1_MODE_Pos (0U)
12701#define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
12702#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
12703#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
12704#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
12705
12706#define SAI_xCR1_PRTCFG_Pos (2U)
12707#define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
12708#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
12709#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
12710#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
12711
12712#define SAI_xCR1_DS_Pos (5U)
12713#define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
12714#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
12715#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
12716#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
12717#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
12718
12719#define SAI_xCR1_LSBFIRST_Pos (8U)
12720#define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
12721#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
12722#define SAI_xCR1_CKSTR_Pos (9U)
12723#define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
12724#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
12725
12726#define SAI_xCR1_SYNCEN_Pos (10U)
12727#define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
12728#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
12729#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
12730#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
12731
12732#define SAI_xCR1_MONO_Pos (12U)
12733#define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
12734#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
12735#define SAI_xCR1_OUTDRIV_Pos (13U)
12736#define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
12737#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
12738#define SAI_xCR1_SAIEN_Pos (16U)
12739#define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
12740#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
12741#define SAI_xCR1_DMAEN_Pos (17U)
12742#define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
12743#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
12744#define SAI_xCR1_NODIV_Pos (19U)
12745#define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
12746#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
12747
12748#define SAI_xCR1_MCKDIV_Pos (20U)
12749#define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
12750#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
12751#define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
12752#define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
12753#define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
12754#define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
12755
12756/******************* Bit definition for SAI_xCR2 register *******************/
12757#define SAI_xCR2_FTH_Pos (0U)
12758#define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
12759#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
12760#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
12761#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
12762#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
12763
12764#define SAI_xCR2_FFLUSH_Pos (3U)
12765#define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
12766#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
12767#define SAI_xCR2_TRIS_Pos (4U)
12768#define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
12769#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
12770#define SAI_xCR2_MUTE_Pos (5U)
12771#define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
12772#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
12773#define SAI_xCR2_MUTEVAL_Pos (6U)
12774#define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
12775#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
12776
12777
12778#define SAI_xCR2_MUTECNT_Pos (7U)
12779#define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
12780#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
12781#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
12782#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
12783#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
12784#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
12785#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
12786#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
12787
12788#define SAI_xCR2_CPL_Pos (13U)
12789#define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
12790#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
12791#define SAI_xCR2_COMP_Pos (14U)
12792#define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
12793#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
12794#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
12795#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
12796
12797
12798/****************** Bit definition for SAI_xFRCR register *******************/
12799#define SAI_xFRCR_FRL_Pos (0U)
12800#define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
12801#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
12802#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
12803#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
12804#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
12805#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
12806#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
12807#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
12808#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
12809#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
12810
12811#define SAI_xFRCR_FSALL_Pos (8U)
12812#define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
12813#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
12814#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
12815#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
12816#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
12817#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
12818#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
12819#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
12820#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
12821
12822#define SAI_xFRCR_FSDEF_Pos (16U)
12823#define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
12824#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
12825#define SAI_xFRCR_FSPOL_Pos (17U)
12826#define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
12827#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
12828#define SAI_xFRCR_FSOFF_Pos (18U)
12829#define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
12830#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
12831
12832/****************** Bit definition for SAI_xSLOTR register *******************/
12833#define SAI_xSLOTR_FBOFF_Pos (0U)
12834#define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
12835#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
12836#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
12837#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
12838#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
12839#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
12840#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
12841
12842#define SAI_xSLOTR_SLOTSZ_Pos (6U)
12843#define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
12844#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
12845#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
12846#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
12847
12848#define SAI_xSLOTR_NBSLOT_Pos (8U)
12849#define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
12850#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
12851#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
12852#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
12853#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
12854#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
12855
12856#define SAI_xSLOTR_SLOTEN_Pos (16U)
12857#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
12858#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
12859
12860/******************* Bit definition for SAI_xIMR register *******************/
12861#define SAI_xIMR_OVRUDRIE_Pos (0U)
12862#define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
12863#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
12864#define SAI_xIMR_MUTEDETIE_Pos (1U)
12865#define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
12866#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
12867#define SAI_xIMR_WCKCFGIE_Pos (2U)
12868#define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
12869#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
12870#define SAI_xIMR_FREQIE_Pos (3U)
12871#define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
12872#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
12873#define SAI_xIMR_CNRDYIE_Pos (4U)
12874#define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
12875#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
12876#define SAI_xIMR_AFSDETIE_Pos (5U)
12877#define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
12878#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
12879#define SAI_xIMR_LFSDETIE_Pos (6U)
12880#define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
12881#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
12882
12883/******************** Bit definition for SAI_xSR register *******************/
12884#define SAI_xSR_OVRUDR_Pos (0U)
12885#define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
12886#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
12887#define SAI_xSR_MUTEDET_Pos (1U)
12888#define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
12889#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
12890#define SAI_xSR_WCKCFG_Pos (2U)
12891#define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
12892#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
12893#define SAI_xSR_FREQ_Pos (3U)
12894#define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
12895#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
12896#define SAI_xSR_CNRDY_Pos (4U)
12897#define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
12898#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
12899#define SAI_xSR_AFSDET_Pos (5U)
12900#define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
12901#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
12902#define SAI_xSR_LFSDET_Pos (6U)
12903#define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
12904#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
12905
12906#define SAI_xSR_FLVL_Pos (16U)
12907#define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
12908#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
12909#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
12910#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
12911#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
12912
12913/****************** Bit definition for SAI_xCLRFR register ******************/
12914#define SAI_xCLRFR_COVRUDR_Pos (0U)
12915#define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
12916#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
12917#define SAI_xCLRFR_CMUTEDET_Pos (1U)
12918#define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
12919#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
12920#define SAI_xCLRFR_CWCKCFG_Pos (2U)
12921#define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
12922#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
12923#define SAI_xCLRFR_CFREQ_Pos (3U)
12924#define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
12925#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
12926#define SAI_xCLRFR_CCNRDY_Pos (4U)
12927#define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
12928#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
12929#define SAI_xCLRFR_CAFSDET_Pos (5U)
12930#define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
12931#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
12932#define SAI_xCLRFR_CLFSDET_Pos (6U)
12933#define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
12934#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
12935
12936/****************** Bit definition for SAI_xDR register ******************/
12937#define SAI_xDR_DATA_Pos (0U)
12938#define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
12939#define SAI_xDR_DATA SAI_xDR_DATA_Msk
12940
12941/******************************************************************************/
12942/* */
12943/* SDMMC Interface */
12944/* */
12945/******************************************************************************/
12946/****************** Bit definition for SDMMC_POWER register ******************/
12947#define SDMMC_POWER_PWRCTRL_Pos (0U)
12948#define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
12949#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
12950#define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
12951#define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
12952
12953/****************** Bit definition for SDMMC_CLKCR register ******************/
12954#define SDMMC_CLKCR_CLKDIV_Pos (0U)
12955#define SDMMC_CLKCR_CLKDIV_Msk (0xFFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
12956#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
12957#define SDMMC_CLKCR_CLKEN_Pos (8U)
12958#define SDMMC_CLKCR_CLKEN_Msk (0x1U << SDMMC_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
12959#define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk /*!<Clock enable bit */
12960#define SDMMC_CLKCR_PWRSAV_Pos (9U)
12961#define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
12962#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
12963#define SDMMC_CLKCR_BYPASS_Pos (10U)
12964#define SDMMC_CLKCR_BYPASS_Msk (0x1U << SDMMC_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
12965#define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
12966
12967#define SDMMC_CLKCR_WIDBUS_Pos (11U)
12968#define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
12969#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
12970#define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00000800 */
12971#define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001000 */
12972
12973#define SDMMC_CLKCR_NEGEDGE_Pos (13U)
12974#define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
12975#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
12976#define SDMMC_CLKCR_HWFC_EN_Pos (14U)
12977#define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
12978#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
12979
12980/******************* Bit definition for SDMMC_ARG register *******************/
12981#define SDMMC_ARG_CMDARG_Pos (0U)
12982#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
12983#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
12984
12985/******************* Bit definition for SDMMC_CMD register *******************/
12986#define SDMMC_CMD_CMDINDEX_Pos (0U)
12987#define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
12988#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
12989
12990#define SDMMC_CMD_WAITRESP_Pos (6U)
12991#define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
12992#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
12993#define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000040 */
12994#define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000080 */
12995
12996#define SDMMC_CMD_WAITINT_Pos (8U)
12997#define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000100 */
12998#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
12999#define SDMMC_CMD_WAITPEND_Pos (9U)
13000#define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000200 */
13001#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
13002#define SDMMC_CMD_CPSMEN_Pos (10U)
13003#define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00000400 */
13004#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
13005#define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
13006#define SDMMC_CMD_SDIOSUSPEND_Msk (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
13007#define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
13008
13009/***************** Bit definition for SDMMC_RESPCMD register *****************/
13010#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
13011#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
13012#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
13013
13014/****************** Bit definition for SDMMC_RESP1 register ******************/
13015#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
13016#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
13017#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
13018
13019/****************** Bit definition for SDMMC_RESP2 register ******************/
13020#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
13021#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
13022#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
13023
13024/****************** Bit definition for SDMMC_RESP3 register ******************/
13025#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
13026#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
13027#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
13028
13029/****************** Bit definition for SDMMC_RESP4 register ******************/
13030#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
13031#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
13032#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
13033
13034/****************** Bit definition for SDMMC_DTIMER register *****************/
13035#define SDMMC_DTIMER_DATATIME_Pos (0U)
13036#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
13037#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
13038
13039/****************** Bit definition for SDMMC_DLEN register *******************/
13040#define SDMMC_DLEN_DATALENGTH_Pos (0U)
13041#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
13042#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
13043
13044/****************** Bit definition for SDMMC_DCTRL register ******************/
13045#define SDMMC_DCTRL_DTEN_Pos (0U)
13046#define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
13047#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
13048#define SDMMC_DCTRL_DTDIR_Pos (1U)
13049#define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
13050#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
13051#define SDMMC_DCTRL_DTMODE_Pos (2U)
13052#define SDMMC_DCTRL_DTMODE_Msk (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
13053#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
13054#define SDMMC_DCTRL_DMAEN_Pos (3U)
13055#define SDMMC_DCTRL_DMAEN_Msk (0x1U << SDMMC_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
13056#define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
13057
13058#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
13059#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
13060#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
13061#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
13062#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
13063#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
13064#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
13065
13066#define SDMMC_DCTRL_RWSTART_Pos (8U)
13067#define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
13068#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
13069#define SDMMC_DCTRL_RWSTOP_Pos (9U)
13070#define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
13071#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
13072#define SDMMC_DCTRL_RWMOD_Pos (10U)
13073#define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
13074#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
13075#define SDMMC_DCTRL_SDIOEN_Pos (11U)
13076#define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
13077#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
13078
13079/****************** Bit definition for SDMMC_DCOUNT register *****************/
13080#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
13081#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
13082#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
13083
13084/****************** Bit definition for SDMMC_STA register ********************/
13085#define SDMMC_STA_CCRCFAIL_Pos (0U)
13086#define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
13087#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
13088#define SDMMC_STA_DCRCFAIL_Pos (1U)
13089#define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
13090#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
13091#define SDMMC_STA_CTIMEOUT_Pos (2U)
13092#define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
13093#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
13094#define SDMMC_STA_DTIMEOUT_Pos (3U)
13095#define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
13096#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
13097#define SDMMC_STA_TXUNDERR_Pos (4U)
13098#define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
13099#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
13100#define SDMMC_STA_RXOVERR_Pos (5U)
13101#define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
13102#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
13103#define SDMMC_STA_CMDREND_Pos (6U)
13104#define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
13105#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
13106#define SDMMC_STA_CMDSENT_Pos (7U)
13107#define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
13108#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
13109#define SDMMC_STA_DATAEND_Pos (8U)
13110#define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
13111#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
13112#define SDMMC_STA_STBITERR_Pos (9U)
13113#define SDMMC_STA_STBITERR_Msk (0x1U << SDMMC_STA_STBITERR_Pos) /*!< 0x00000200 */
13114#define SDMMC_STA_STBITERR SDMMC_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
13115#define SDMMC_STA_DBCKEND_Pos (10U)
13116#define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
13117#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
13118#define SDMMC_STA_CMDACT_Pos (11U)
13119#define SDMMC_STA_CMDACT_Msk (0x1U << SDMMC_STA_CMDACT_Pos) /*!< 0x00000800 */
13120#define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk /*!<Command transfer in progress */
13121#define SDMMC_STA_TXACT_Pos (12U)
13122#define SDMMC_STA_TXACT_Msk (0x1U << SDMMC_STA_TXACT_Pos) /*!< 0x00001000 */
13123#define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk /*!<Data transmit in progress */
13124#define SDMMC_STA_RXACT_Pos (13U)
13125#define SDMMC_STA_RXACT_Msk (0x1U << SDMMC_STA_RXACT_Pos) /*!< 0x00002000 */
13126#define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk /*!<Data receive in progress */
13127#define SDMMC_STA_TXFIFOHE_Pos (14U)
13128#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
13129#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
13130#define SDMMC_STA_RXFIFOHF_Pos (15U)
13131#define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
13132#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
13133#define SDMMC_STA_TXFIFOF_Pos (16U)
13134#define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
13135#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
13136#define SDMMC_STA_RXFIFOF_Pos (17U)
13137#define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
13138#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
13139#define SDMMC_STA_TXFIFOE_Pos (18U)
13140#define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
13141#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
13142#define SDMMC_STA_RXFIFOE_Pos (19U)
13143#define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
13144#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
13145#define SDMMC_STA_TXDAVL_Pos (20U)
13146#define SDMMC_STA_TXDAVL_Msk (0x1U << SDMMC_STA_TXDAVL_Pos) /*!< 0x00100000 */
13147#define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
13148#define SDMMC_STA_RXDAVL_Pos (21U)
13149#define SDMMC_STA_RXDAVL_Msk (0x1U << SDMMC_STA_RXDAVL_Pos) /*!< 0x00200000 */
13150#define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
13151#define SDMMC_STA_SDIOIT_Pos (22U)
13152#define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
13153#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
13154
13155/******************* Bit definition for SDMMC_ICR register *******************/
13156#define SDMMC_ICR_CCRCFAILC_Pos (0U)
13157#define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
13158#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
13159#define SDMMC_ICR_DCRCFAILC_Pos (1U)
13160#define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
13161#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
13162#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
13163#define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
13164#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
13165#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
13166#define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
13167#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
13168#define SDMMC_ICR_TXUNDERRC_Pos (4U)
13169#define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
13170#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
13171#define SDMMC_ICR_RXOVERRC_Pos (5U)
13172#define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
13173#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
13174#define SDMMC_ICR_CMDRENDC_Pos (6U)
13175#define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
13176#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
13177#define SDMMC_ICR_CMDSENTC_Pos (7U)
13178#define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
13179#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
13180#define SDMMC_ICR_DATAENDC_Pos (8U)
13181#define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
13182#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
13183#define SDMMC_ICR_STBITERRC_Pos (9U)
13184#define SDMMC_ICR_STBITERRC_Msk (0x1U << SDMMC_ICR_STBITERRC_Pos) /*!< 0x00000200 */
13185#define SDMMC_ICR_STBITERRC SDMMC_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
13186#define SDMMC_ICR_DBCKENDC_Pos (10U)
13187#define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
13188#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
13189#define SDMMC_ICR_SDIOITC_Pos (22U)
13190#define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
13191#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
13192
13193/****************** Bit definition for SDMMC_MASK register *******************/
13194#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
13195#define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
13196#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
13197#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
13198#define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
13199#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
13200#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
13201#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
13202#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
13203#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
13204#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
13205#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
13206#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
13207#define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
13208#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
13209#define SDMMC_MASK_RXOVERRIE_Pos (5U)
13210#define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
13211#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
13212#define SDMMC_MASK_CMDRENDIE_Pos (6U)
13213#define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
13214#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
13215#define SDMMC_MASK_CMDSENTIE_Pos (7U)
13216#define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
13217#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
13218#define SDMMC_MASK_DATAENDIE_Pos (8U)
13219#define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
13220#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
13221#define SDMMC_MASK_DBCKENDIE_Pos (10U)
13222#define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
13223#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
13224#define SDMMC_MASK_CMDACTIE_Pos (11U)
13225#define SDMMC_MASK_CMDACTIE_Msk (0x1U << SDMMC_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
13226#define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
13227#define SDMMC_MASK_TXACTIE_Pos (12U)
13228#define SDMMC_MASK_TXACTIE_Msk (0x1U << SDMMC_MASK_TXACTIE_Pos) /*!< 0x00001000 */
13229#define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
13230#define SDMMC_MASK_RXACTIE_Pos (13U)
13231#define SDMMC_MASK_RXACTIE_Msk (0x1U << SDMMC_MASK_RXACTIE_Pos) /*!< 0x00002000 */
13232#define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
13233#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
13234#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
13235#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
13236#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
13237#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
13238#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
13239#define SDMMC_MASK_TXFIFOFIE_Pos (16U)
13240#define SDMMC_MASK_TXFIFOFIE_Msk (0x1U << SDMMC_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
13241#define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
13242#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
13243#define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
13244#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
13245#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
13246#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
13247#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
13248#define SDMMC_MASK_RXFIFOEIE_Pos (19U)
13249#define SDMMC_MASK_RXFIFOEIE_Msk (0x1U << SDMMC_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
13250#define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
13251#define SDMMC_MASK_TXDAVLIE_Pos (20U)
13252#define SDMMC_MASK_TXDAVLIE_Msk (0x1U << SDMMC_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
13253#define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
13254#define SDMMC_MASK_RXDAVLIE_Pos (21U)
13255#define SDMMC_MASK_RXDAVLIE_Msk (0x1U << SDMMC_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
13256#define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
13257#define SDMMC_MASK_SDIOITIE_Pos (22U)
13258#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
13259#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
13260
13261/***************** Bit definition for SDMMC_FIFOCNT register *****************/
13262#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
13263#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
13264#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
13265
13266/****************** Bit definition for SDMMC_FIFO register *******************/
13267#define SDMMC_FIFO_FIFODATA_Pos (0U)
13268#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
13269#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
13270
13271/******************************************************************************/
13272/* */
13273/* Serial Peripheral Interface (SPI) */
13274/* */
13275/******************************************************************************/
13276/******************* Bit definition for SPI_CR1 register ********************/
13277#define SPI_CR1_CPHA_Pos (0U)
13278#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
13279#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
13280#define SPI_CR1_CPOL_Pos (1U)
13281#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
13282#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
13283#define SPI_CR1_MSTR_Pos (2U)
13284#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
13285#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
13286
13287#define SPI_CR1_BR_Pos (3U)
13288#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
13289#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
13290#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
13291#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
13292#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
13293
13294#define SPI_CR1_SPE_Pos (6U)
13295#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
13296#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
13297#define SPI_CR1_LSBFIRST_Pos (7U)
13298#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
13299#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
13300#define SPI_CR1_SSI_Pos (8U)
13301#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
13302#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
13303#define SPI_CR1_SSM_Pos (9U)
13304#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
13305#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
13306#define SPI_CR1_RXONLY_Pos (10U)
13307#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
13308#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
13309#define SPI_CR1_CRCL_Pos (11U)
13310#define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
13311#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
13312#define SPI_CR1_CRCNEXT_Pos (12U)
13313#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
13314#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
13315#define SPI_CR1_CRCEN_Pos (13U)
13316#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
13317#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
13318#define SPI_CR1_BIDIOE_Pos (14U)
13319#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
13320#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
13321#define SPI_CR1_BIDIMODE_Pos (15U)
13322#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
13323#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
13324
13325/******************* Bit definition for SPI_CR2 register ********************/
13326#define SPI_CR2_RXDMAEN_Pos (0U)
13327#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
13328#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
13329#define SPI_CR2_TXDMAEN_Pos (1U)
13330#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
13331#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
13332#define SPI_CR2_SSOE_Pos (2U)
13333#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
13334#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
13335#define SPI_CR2_NSSP_Pos (3U)
13336#define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
13337#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
13338#define SPI_CR2_FRF_Pos (4U)
13339#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
13340#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
13341#define SPI_CR2_ERRIE_Pos (5U)
13342#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
13343#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
13344#define SPI_CR2_RXNEIE_Pos (6U)
13345#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
13346#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
13347#define SPI_CR2_TXEIE_Pos (7U)
13348#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
13349#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
13350#define SPI_CR2_DS_Pos (8U)
13351#define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
13352#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
13353#define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
13354#define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
13355#define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
13356#define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
13357#define SPI_CR2_FRXTH_Pos (12U)
13358#define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
13359#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
13360#define SPI_CR2_LDMARX_Pos (13U)
13361#define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
13362#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
13363#define SPI_CR2_LDMATX_Pos (14U)
13364#define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
13365#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
13366
13367/******************** Bit definition for SPI_SR register ********************/
13368#define SPI_SR_RXNE_Pos (0U)
13369#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
13370#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
13371#define SPI_SR_TXE_Pos (1U)
13372#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
13373#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
13374#define SPI_SR_CHSIDE_Pos (2U)
13375#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
13376#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
13377#define SPI_SR_UDR_Pos (3U)
13378#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
13379#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
13380#define SPI_SR_CRCERR_Pos (4U)
13381#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
13382#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
13383#define SPI_SR_MODF_Pos (5U)
13384#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
13385#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
13386#define SPI_SR_OVR_Pos (6U)
13387#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
13388#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
13389#define SPI_SR_BSY_Pos (7U)
13390#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
13391#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
13392#define SPI_SR_FRE_Pos (8U)
13393#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
13394#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
13395#define SPI_SR_FRLVL_Pos (9U)
13396#define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
13397#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
13398#define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
13399#define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
13400#define SPI_SR_FTLVL_Pos (11U)
13401#define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
13402#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
13403#define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
13404#define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
13405
13406/******************** Bit definition for SPI_DR register ********************/
13407#define SPI_DR_DR_Pos (0U)
13408#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
13409#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
13410
13411/******************* Bit definition for SPI_CRCPR register ******************/
13412#define SPI_CRCPR_CRCPOLY_Pos (0U)
13413#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
13414#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
13415
13416/****************** Bit definition for SPI_RXCRCR register ******************/
13417#define SPI_RXCRCR_RXCRC_Pos (0U)
13418#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
13419#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
13420
13421/****************** Bit definition for SPI_TXCRCR register ******************/
13422#define SPI_TXCRCR_TXCRC_Pos (0U)
13423#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
13424#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
13425
13426/******************************************************************************/
13427/* */
13428/* QUADSPI */
13429/* */
13430/******************************************************************************/
13431/***************** Bit definition for QUADSPI_CR register *******************/
13432#define QUADSPI_CR_EN_Pos (0U)
13433#define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
13434#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
13435#define QUADSPI_CR_ABORT_Pos (1U)
13436#define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
13437#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
13438#define QUADSPI_CR_DMAEN_Pos (2U)
13439#define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
13440#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
13441#define QUADSPI_CR_TCEN_Pos (3U)
13442#define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
13443#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
13444#define QUADSPI_CR_SSHIFT_Pos (4U)
13445#define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
13446#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
13447#define QUADSPI_CR_FTHRES_Pos (8U)
13448#define QUADSPI_CR_FTHRES_Msk (0xFU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
13449#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
13450#define QUADSPI_CR_TEIE_Pos (16U)
13451#define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
13452#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
13453#define QUADSPI_CR_TCIE_Pos (17U)
13454#define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
13455#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
13456#define QUADSPI_CR_FTIE_Pos (18U)
13457#define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
13458#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
13459#define QUADSPI_CR_SMIE_Pos (19U)
13460#define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
13461#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
13462#define QUADSPI_CR_TOIE_Pos (20U)
13463#define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
13464#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
13465#define QUADSPI_CR_APMS_Pos (22U)
13466#define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
13467#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
13468#define QUADSPI_CR_PMM_Pos (23U)
13469#define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
13470#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
13471#define QUADSPI_CR_PRESCALER_Pos (24U)
13472#define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
13473#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
13474
13475/***************** Bit definition for QUADSPI_DCR register ******************/
13476#define QUADSPI_DCR_CKMODE_Pos (0U)
13477#define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
13478#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
13479#define QUADSPI_DCR_CSHT_Pos (8U)
13480#define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
13481#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
13482#define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
13483#define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
13484#define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
13485#define QUADSPI_DCR_FSIZE_Pos (16U)
13486#define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
13487#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
13488
13489/****************** Bit definition for QUADSPI_SR register *******************/
13490#define QUADSPI_SR_TEF_Pos (0U)
13491#define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
13492#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
13493#define QUADSPI_SR_TCF_Pos (1U)
13494#define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
13495#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
13496#define QUADSPI_SR_FTF_Pos (2U)
13497#define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
13498#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
13499#define QUADSPI_SR_SMF_Pos (3U)
13500#define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
13501#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
13502#define QUADSPI_SR_TOF_Pos (4U)
13503#define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
13504#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
13505#define QUADSPI_SR_BUSY_Pos (5U)
13506#define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
13507#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
13508#define QUADSPI_SR_FLEVEL_Pos (8U)
13509#define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
13510#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
13511
13512/****************** Bit definition for QUADSPI_FCR register ******************/
13513#define QUADSPI_FCR_CTEF_Pos (0U)
13514#define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
13515#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
13516#define QUADSPI_FCR_CTCF_Pos (1U)
13517#define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
13518#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
13519#define QUADSPI_FCR_CSMF_Pos (3U)
13520#define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
13521#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
13522#define QUADSPI_FCR_CTOF_Pos (4U)
13523#define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
13524#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
13525
13526/****************** Bit definition for QUADSPI_DLR register ******************/
13527#define QUADSPI_DLR_DL_Pos (0U)
13528#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
13529#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
13530
13531/****************** Bit definition for QUADSPI_CCR register ******************/
13532#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
13533#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
13534#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
13535#define QUADSPI_CCR_IMODE_Pos (8U)
13536#define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
13537#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
13538#define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
13539#define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
13540#define QUADSPI_CCR_ADMODE_Pos (10U)
13541#define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
13542#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
13543#define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
13544#define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
13545#define QUADSPI_CCR_ADSIZE_Pos (12U)
13546#define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
13547#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
13548#define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
13549#define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
13550#define QUADSPI_CCR_ABMODE_Pos (14U)
13551#define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
13552#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
13553#define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
13554#define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
13555#define QUADSPI_CCR_ABSIZE_Pos (16U)
13556#define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
13557#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
13558#define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
13559#define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
13560#define QUADSPI_CCR_DCYC_Pos (18U)
13561#define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
13562#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
13563#define QUADSPI_CCR_DMODE_Pos (24U)
13564#define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
13565#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
13566#define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
13567#define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
13568#define QUADSPI_CCR_FMODE_Pos (26U)
13569#define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
13570#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
13571#define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
13572#define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
13573#define QUADSPI_CCR_SIOO_Pos (28U)
13574#define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
13575#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
13576#define QUADSPI_CCR_DDRM_Pos (31U)
13577#define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
13578#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
13579
13580/****************** Bit definition for QUADSPI_AR register *******************/
13581#define QUADSPI_AR_ADDRESS_Pos (0U)
13582#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
13583#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
13584
13585/****************** Bit definition for QUADSPI_ABR register ******************/
13586#define QUADSPI_ABR_ALTERNATE_Pos (0U)
13587#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
13588#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
13589
13590/****************** Bit definition for QUADSPI_DR register *******************/
13591#define QUADSPI_DR_DATA_Pos (0U)
13592#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
13593#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
13594
13595/****************** Bit definition for QUADSPI_PSMKR register ****************/
13596#define QUADSPI_PSMKR_MASK_Pos (0U)
13597#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
13598#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
13599
13600/****************** Bit definition for QUADSPI_PSMAR register ****************/
13601#define QUADSPI_PSMAR_MATCH_Pos (0U)
13602#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
13603#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
13604
13605/****************** Bit definition for QUADSPI_PIR register *****************/
13606#define QUADSPI_PIR_INTERVAL_Pos (0U)
13607#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
13608#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
13609
13610/****************** Bit definition for QUADSPI_LPTR register *****************/
13611#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
13612#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
13613#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
13614
13615/******************************************************************************/
13616/* */
13617/* SYSCFG */
13618/* */
13619/******************************************************************************/
13620/****************** Bit definition for SYSCFG_MEMRMP register ***************/
13621#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
13622#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
13623#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
13624#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
13625#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
13626#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
13627
13628#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
13629#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
13630#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< Flash Bank mode selection */
13631
13632/****************** Bit definition for SYSCFG_CFGR1 register ******************/
13633#define SYSCFG_CFGR1_FWDIS_Pos (0U)
13634#define SYSCFG_CFGR1_FWDIS_Msk (0x1U << SYSCFG_CFGR1_FWDIS_Pos) /*!< 0x00000001 */
13635#define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk /*!< FIREWALL access enable*/
13636#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
13637#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
13638#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
13639#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
13640#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
13641#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
13642#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
13643#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
13644#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
13645#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
13646#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
13647#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
13648#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
13649#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
13650#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
13651#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
13652#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
13653#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
13654#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
13655#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
13656#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
13657#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
13658#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
13659#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
13660#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
13661#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
13662#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
13663#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
13664#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
13665#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
13666
13667/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
13668#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
13669#define SYSCFG_EXTICR1_EXTI0_Msk (0x7U << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
13670#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
13671#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
13672#define SYSCFG_EXTICR1_EXTI1_Msk (0x7U << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x00000070 */
13673#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
13674#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
13675#define SYSCFG_EXTICR1_EXTI2_Msk (0x7U << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000700 */
13676#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
13677#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
13678#define SYSCFG_EXTICR1_EXTI3_Msk (0x7U << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x00007000 */
13679#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
13680
13681/**
13682 * @brief EXTI0 configuration
13683 */
13684#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
13685#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
13686#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
13687#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
13688#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
13689#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
13690#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
13691#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
13692
13693/**
13694 * @brief EXTI1 configuration
13695 */
13696#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
13697#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
13698#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
13699#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
13700#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
13701#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
13702#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
13703#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
13704
13705/**
13706 * @brief EXTI2 configuration
13707 */
13708#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
13709#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
13710#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
13711#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
13712#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
13713#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
13714#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
13715
13716/**
13717 * @brief EXTI3 configuration
13718 */
13719#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
13720#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
13721#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
13722#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
13723#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
13724#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
13725#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
13726
13727/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
13728#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
13729#define SYSCFG_EXTICR2_EXTI4_Msk (0x7U << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
13730#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
13731#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
13732#define SYSCFG_EXTICR2_EXTI5_Msk (0x7U << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x00000070 */
13733#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
13734#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
13735#define SYSCFG_EXTICR2_EXTI6_Msk (0x7U << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000700 */
13736#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
13737#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
13738#define SYSCFG_EXTICR2_EXTI7_Msk (0x7U << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x00007000 */
13739#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
13740/**
13741 * @brief EXTI4 configuration
13742 */
13743#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
13744#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
13745#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
13746#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
13747#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
13748#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
13749#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
13750
13751/**
13752 * @brief EXTI5 configuration
13753 */
13754#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
13755#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
13756#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
13757#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
13758#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
13759#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
13760#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
13761
13762/**
13763 * @brief EXTI6 configuration
13764 */
13765#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
13766#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
13767#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
13768#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
13769#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
13770#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
13771#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
13772
13773/**
13774 * @brief EXTI7 configuration
13775 */
13776#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
13777#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
13778#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
13779#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
13780#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
13781#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
13782#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
13783
13784/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
13785#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
13786#define SYSCFG_EXTICR3_EXTI8_Msk (0x7U << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
13787#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
13788#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
13789#define SYSCFG_EXTICR3_EXTI9_Msk (0x7U << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x00000070 */
13790#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
13791#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
13792#define SYSCFG_EXTICR3_EXTI10_Msk (0x7U << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000700 */
13793#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
13794#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
13795#define SYSCFG_EXTICR3_EXTI11_Msk (0x7U << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x00007000 */
13796#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
13797
13798/**
13799 * @brief EXTI8 configuration
13800 */
13801#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
13802#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
13803#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
13804#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
13805#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
13806#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
13807#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
13808
13809/**
13810 * @brief EXTI9 configuration
13811 */
13812#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
13813#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
13814#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
13815#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
13816#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
13817#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
13818#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
13819
13820/**
13821 * @brief EXTI10 configuration
13822 */
13823#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
13824#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
13825#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
13826#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
13827#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
13828#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
13829#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
13830
13831/**
13832 * @brief EXTI11 configuration
13833 */
13834#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
13835#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
13836#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
13837#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
13838#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
13839#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
13840#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
13841
13842/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
13843#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
13844#define SYSCFG_EXTICR4_EXTI12_Msk (0x7U << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
13845#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
13846#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
13847#define SYSCFG_EXTICR4_EXTI13_Msk (0x7U << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
13848#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
13849#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
13850#define SYSCFG_EXTICR4_EXTI14_Msk (0x7U << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
13851#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
13852#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
13853#define SYSCFG_EXTICR4_EXTI15_Msk (0x7U << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
13854#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
13855
13856/**
13857 * @brief EXTI12 configuration
13858 */
13859#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
13860#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
13861#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
13862#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
13863#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
13864#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
13865#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
13866
13867/**
13868 * @brief EXTI13 configuration
13869 */
13870#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
13871#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
13872#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
13873#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
13874#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
13875#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
13876#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
13877
13878/**
13879 * @brief EXTI14 configuration
13880 */
13881#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
13882#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
13883#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
13884#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
13885#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
13886#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
13887#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
13888
13889/**
13890 * @brief EXTI15 configuration
13891 */
13892#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
13893#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
13894#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
13895#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
13896#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
13897#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
13898#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
13899
13900/****************** Bit definition for SYSCFG_SCSR register ****************/
13901#define SYSCFG_SCSR_SRAM2ER_Pos (0U)
13902#define SYSCFG_SCSR_SRAM2ER_Msk (0x1U << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */
13903#define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */
13904#define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
13905#define SYSCFG_SCSR_SRAM2BSY_Msk (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */
13906#define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */
13907
13908/****************** Bit definition for SYSCFG_CFGR2 register ****************/
13909#define SYSCFG_CFGR2_CLL_Pos (0U)
13910#define SYSCFG_CFGR2_CLL_Msk (0x1U << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
13911#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
13912#define SYSCFG_CFGR2_SPL_Pos (1U)
13913#define SYSCFG_CFGR2_SPL_Msk (0x1U << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
13914#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
13915#define SYSCFG_CFGR2_PVDL_Pos (2U)
13916#define SYSCFG_CFGR2_PVDL_Msk (0x1U << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
13917#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
13918#define SYSCFG_CFGR2_ECCL_Pos (3U)
13919#define SYSCFG_CFGR2_ECCL_Msk (0x1U << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
13920#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
13921#define SYSCFG_CFGR2_SPF_Pos (8U)
13922#define SYSCFG_CFGR2_SPF_Msk (0x1U << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
13923#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
13924
13925/****************** Bit definition for SYSCFG_SWPR register ****************/
13926#define SYSCFG_SWPR_PAGE0_Pos (0U)
13927#define SYSCFG_SWPR_PAGE0_Msk (0x1U << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
13928#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 */
13929#define SYSCFG_SWPR_PAGE1_Pos (1U)
13930#define SYSCFG_SWPR_PAGE1_Msk (0x1U << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
13931#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 */
13932#define SYSCFG_SWPR_PAGE2_Pos (2U)
13933#define SYSCFG_SWPR_PAGE2_Msk (0x1U << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
13934#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 */
13935#define SYSCFG_SWPR_PAGE3_Pos (3U)
13936#define SYSCFG_SWPR_PAGE3_Msk (0x1U << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
13937#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 */
13938#define SYSCFG_SWPR_PAGE4_Pos (4U)
13939#define SYSCFG_SWPR_PAGE4_Msk (0x1U << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
13940#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 */
13941#define SYSCFG_SWPR_PAGE5_Pos (5U)
13942#define SYSCFG_SWPR_PAGE5_Msk (0x1U << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
13943#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 */
13944#define SYSCFG_SWPR_PAGE6_Pos (6U)
13945#define SYSCFG_SWPR_PAGE6_Msk (0x1U << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
13946#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 */
13947#define SYSCFG_SWPR_PAGE7_Pos (7U)
13948#define SYSCFG_SWPR_PAGE7_Msk (0x1U << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
13949#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 */
13950#define SYSCFG_SWPR_PAGE8_Pos (8U)
13951#define SYSCFG_SWPR_PAGE8_Msk (0x1U << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
13952#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 */
13953#define SYSCFG_SWPR_PAGE9_Pos (9U)
13954#define SYSCFG_SWPR_PAGE9_Msk (0x1U << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
13955#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 */
13956#define SYSCFG_SWPR_PAGE10_Pos (10U)
13957#define SYSCFG_SWPR_PAGE10_Msk (0x1U << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
13958#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10*/
13959#define SYSCFG_SWPR_PAGE11_Pos (11U)
13960#define SYSCFG_SWPR_PAGE11_Msk (0x1U << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
13961#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11*/
13962#define SYSCFG_SWPR_PAGE12_Pos (12U)
13963#define SYSCFG_SWPR_PAGE12_Msk (0x1U << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
13964#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12*/
13965#define SYSCFG_SWPR_PAGE13_Pos (13U)
13966#define SYSCFG_SWPR_PAGE13_Msk (0x1U << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
13967#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13*/
13968#define SYSCFG_SWPR_PAGE14_Pos (14U)
13969#define SYSCFG_SWPR_PAGE14_Msk (0x1U << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
13970#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14*/
13971#define SYSCFG_SWPR_PAGE15_Pos (15U)
13972#define SYSCFG_SWPR_PAGE15_Msk (0x1U << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
13973#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15*/
13974#define SYSCFG_SWPR_PAGE16_Pos (16U)
13975#define SYSCFG_SWPR_PAGE16_Msk (0x1U << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
13976#define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16*/
13977#define SYSCFG_SWPR_PAGE17_Pos (17U)
13978#define SYSCFG_SWPR_PAGE17_Msk (0x1U << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
13979#define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17*/
13980#define SYSCFG_SWPR_PAGE18_Pos (18U)
13981#define SYSCFG_SWPR_PAGE18_Msk (0x1U << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
13982#define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18*/
13983#define SYSCFG_SWPR_PAGE19_Pos (19U)
13984#define SYSCFG_SWPR_PAGE19_Msk (0x1U << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
13985#define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19*/
13986#define SYSCFG_SWPR_PAGE20_Pos (20U)
13987#define SYSCFG_SWPR_PAGE20_Msk (0x1U << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
13988#define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20*/
13989#define SYSCFG_SWPR_PAGE21_Pos (21U)
13990#define SYSCFG_SWPR_PAGE21_Msk (0x1U << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
13991#define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21*/
13992#define SYSCFG_SWPR_PAGE22_Pos (22U)
13993#define SYSCFG_SWPR_PAGE22_Msk (0x1U << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
13994#define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22*/
13995#define SYSCFG_SWPR_PAGE23_Pos (23U)
13996#define SYSCFG_SWPR_PAGE23_Msk (0x1U << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
13997#define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23*/
13998#define SYSCFG_SWPR_PAGE24_Pos (24U)
13999#define SYSCFG_SWPR_PAGE24_Msk (0x1U << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
14000#define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24*/
14001#define SYSCFG_SWPR_PAGE25_Pos (25U)
14002#define SYSCFG_SWPR_PAGE25_Msk (0x1U << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
14003#define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25*/
14004#define SYSCFG_SWPR_PAGE26_Pos (26U)
14005#define SYSCFG_SWPR_PAGE26_Msk (0x1U << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
14006#define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26*/
14007#define SYSCFG_SWPR_PAGE27_Pos (27U)
14008#define SYSCFG_SWPR_PAGE27_Msk (0x1U << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
14009#define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27*/
14010#define SYSCFG_SWPR_PAGE28_Pos (28U)
14011#define SYSCFG_SWPR_PAGE28_Msk (0x1U << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
14012#define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28*/
14013#define SYSCFG_SWPR_PAGE29_Pos (29U)
14014#define SYSCFG_SWPR_PAGE29_Msk (0x1U << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
14015#define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29*/
14016#define SYSCFG_SWPR_PAGE30_Pos (30U)
14017#define SYSCFG_SWPR_PAGE30_Msk (0x1U << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
14018#define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30*/
14019#define SYSCFG_SWPR_PAGE31_Pos (31U)
14020#define SYSCFG_SWPR_PAGE31_Msk (0x1U << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
14021#define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31*/
14022
14023/****************** Bit definition for SYSCFG_SKR register ****************/
14024#define SYSCFG_SKR_KEY_Pos (0U)
14025#define SYSCFG_SKR_KEY_Msk (0xFFU << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
14026#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */
14027
14028
14029
14030
14031/******************************************************************************/
14032/* */
14033/* TIM */
14034/* */
14035/******************************************************************************/
14036/******************* Bit definition for TIM_CR1 register ********************/
14037#define TIM_CR1_CEN_Pos (0U)
14038#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
14039#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
14040#define TIM_CR1_UDIS_Pos (1U)
14041#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
14042#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
14043#define TIM_CR1_URS_Pos (2U)
14044#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
14045#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
14046#define TIM_CR1_OPM_Pos (3U)
14047#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
14048#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
14049#define TIM_CR1_DIR_Pos (4U)
14050#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
14051#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
14052
14053#define TIM_CR1_CMS_Pos (5U)
14054#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
14055#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
14056#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
14057#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
14058
14059#define TIM_CR1_ARPE_Pos (7U)
14060#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
14061#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
14062
14063#define TIM_CR1_CKD_Pos (8U)
14064#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
14065#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
14066#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
14067#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
14068
14069#define TIM_CR1_UIFREMAP_Pos (11U)
14070#define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
14071#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
14072
14073/******************* Bit definition for TIM_CR2 register ********************/
14074#define TIM_CR2_CCPC_Pos (0U)
14075#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
14076#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
14077#define TIM_CR2_CCUS_Pos (2U)
14078#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
14079#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
14080#define TIM_CR2_CCDS_Pos (3U)
14081#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
14082#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
14083
14084#define TIM_CR2_MMS_Pos (4U)
14085#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
14086#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
14087#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
14088#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
14089#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
14090
14091#define TIM_CR2_TI1S_Pos (7U)
14092#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
14093#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
14094#define TIM_CR2_OIS1_Pos (8U)
14095#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
14096#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
14097#define TIM_CR2_OIS1N_Pos (9U)
14098#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
14099#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
14100#define TIM_CR2_OIS2_Pos (10U)
14101#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
14102#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
14103#define TIM_CR2_OIS2N_Pos (11U)
14104#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
14105#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
14106#define TIM_CR2_OIS3_Pos (12U)
14107#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
14108#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
14109#define TIM_CR2_OIS3N_Pos (13U)
14110#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
14111#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
14112#define TIM_CR2_OIS4_Pos (14U)
14113#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
14114#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
14115#define TIM_CR2_OIS5_Pos (16U)
14116#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
14117#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
14118#define TIM_CR2_OIS6_Pos (18U)
14119#define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
14120#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
14121
14122#define TIM_CR2_MMS2_Pos (20U)
14123#define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
14124#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
14125#define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
14126#define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
14127#define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
14128#define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
14129
14130/******************* Bit definition for TIM_SMCR register *******************/
14131#define TIM_SMCR_SMS_Pos (0U)
14132#define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
14133#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
14134#define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
14135#define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
14136#define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
14137#define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
14138
14139#define TIM_SMCR_OCCS_Pos (3U)
14140#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
14141#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
14142
14143#define TIM_SMCR_TS_Pos (4U)
14144#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
14145#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
14146#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
14147#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
14148#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
14149
14150#define TIM_SMCR_MSM_Pos (7U)
14151#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
14152#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
14153
14154#define TIM_SMCR_ETF_Pos (8U)
14155#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
14156#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
14157#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
14158#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
14159#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
14160#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
14161
14162#define TIM_SMCR_ETPS_Pos (12U)
14163#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
14164#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
14165#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
14166#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
14167
14168#define TIM_SMCR_ECE_Pos (14U)
14169#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
14170#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
14171#define TIM_SMCR_ETP_Pos (15U)
14172#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
14173#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
14174
14175/******************* Bit definition for TIM_DIER register *******************/
14176#define TIM_DIER_UIE_Pos (0U)
14177#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
14178#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
14179#define TIM_DIER_CC1IE_Pos (1U)
14180#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
14181#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
14182#define TIM_DIER_CC2IE_Pos (2U)
14183#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
14184#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
14185#define TIM_DIER_CC3IE_Pos (3U)
14186#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
14187#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
14188#define TIM_DIER_CC4IE_Pos (4U)
14189#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
14190#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
14191#define TIM_DIER_COMIE_Pos (5U)
14192#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
14193#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
14194#define TIM_DIER_TIE_Pos (6U)
14195#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
14196#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
14197#define TIM_DIER_BIE_Pos (7U)
14198#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
14199#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
14200#define TIM_DIER_UDE_Pos (8U)
14201#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
14202#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
14203#define TIM_DIER_CC1DE_Pos (9U)
14204#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
14205#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
14206#define TIM_DIER_CC2DE_Pos (10U)
14207#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
14208#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
14209#define TIM_DIER_CC3DE_Pos (11U)
14210#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
14211#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
14212#define TIM_DIER_CC4DE_Pos (12U)
14213#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
14214#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
14215#define TIM_DIER_COMDE_Pos (13U)
14216#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
14217#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
14218#define TIM_DIER_TDE_Pos (14U)
14219#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
14220#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
14221
14222/******************** Bit definition for TIM_SR register ********************/
14223#define TIM_SR_UIF_Pos (0U)
14224#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
14225#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
14226#define TIM_SR_CC1IF_Pos (1U)
14227#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
14228#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
14229#define TIM_SR_CC2IF_Pos (2U)
14230#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
14231#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
14232#define TIM_SR_CC3IF_Pos (3U)
14233#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
14234#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
14235#define TIM_SR_CC4IF_Pos (4U)
14236#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
14237#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
14238#define TIM_SR_COMIF_Pos (5U)
14239#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
14240#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
14241#define TIM_SR_TIF_Pos (6U)
14242#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
14243#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
14244#define TIM_SR_BIF_Pos (7U)
14245#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
14246#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
14247#define TIM_SR_B2IF_Pos (8U)
14248#define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
14249#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
14250#define TIM_SR_CC1OF_Pos (9U)
14251#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
14252#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
14253#define TIM_SR_CC2OF_Pos (10U)
14254#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
14255#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
14256#define TIM_SR_CC3OF_Pos (11U)
14257#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
14258#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
14259#define TIM_SR_CC4OF_Pos (12U)
14260#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
14261#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
14262#define TIM_SR_SBIF_Pos (13U)
14263#define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
14264#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
14265#define TIM_SR_CC5IF_Pos (16U)
14266#define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
14267#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
14268#define TIM_SR_CC6IF_Pos (17U)
14269#define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
14270#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
14271
14272
14273/******************* Bit definition for TIM_EGR register ********************/
14274#define TIM_EGR_UG_Pos (0U)
14275#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
14276#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
14277#define TIM_EGR_CC1G_Pos (1U)
14278#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
14279#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
14280#define TIM_EGR_CC2G_Pos (2U)
14281#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
14282#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
14283#define TIM_EGR_CC3G_Pos (3U)
14284#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
14285#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
14286#define TIM_EGR_CC4G_Pos (4U)
14287#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
14288#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
14289#define TIM_EGR_COMG_Pos (5U)
14290#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
14291#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
14292#define TIM_EGR_TG_Pos (6U)
14293#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
14294#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
14295#define TIM_EGR_BG_Pos (7U)
14296#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
14297#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
14298#define TIM_EGR_B2G_Pos (8U)
14299#define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
14300#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
14301
14302
14303/****************** Bit definition for TIM_CCMR1 register *******************/
14304#define TIM_CCMR1_CC1S_Pos (0U)
14305#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
14306#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
14307#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
14308#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
14309
14310#define TIM_CCMR1_OC1FE_Pos (2U)
14311#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
14312#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
14313#define TIM_CCMR1_OC1PE_Pos (3U)
14314#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
14315#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
14316
14317#define TIM_CCMR1_OC1M_Pos (4U)
14318#define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
14319#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
14320#define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
14321#define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
14322#define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
14323#define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
14324
14325#define TIM_CCMR1_OC1CE_Pos (7U)
14326#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
14327#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
14328
14329#define TIM_CCMR1_CC2S_Pos (8U)
14330#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
14331#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
14332#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
14333#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
14334
14335#define TIM_CCMR1_OC2FE_Pos (10U)
14336#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
14337#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
14338#define TIM_CCMR1_OC2PE_Pos (11U)
14339#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
14340#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
14341
14342#define TIM_CCMR1_OC2M_Pos (12U)
14343#define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
14344#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
14345#define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
14346#define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
14347#define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
14348#define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
14349
14350#define TIM_CCMR1_OC2CE_Pos (15U)
14351#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
14352#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
14353
14354/*----------------------------------------------------------------------------*/
14355#define TIM_CCMR1_IC1PSC_Pos (2U)
14356#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
14357#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
14358#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
14359#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
14360
14361#define TIM_CCMR1_IC1F_Pos (4U)
14362#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
14363#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
14364#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
14365#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
14366#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
14367#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
14368
14369#define TIM_CCMR1_IC2PSC_Pos (10U)
14370#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
14371#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
14372#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
14373#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
14374
14375#define TIM_CCMR1_IC2F_Pos (12U)
14376#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
14377#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
14378#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
14379#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
14380#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
14381#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
14382
14383/****************** Bit definition for TIM_CCMR2 register *******************/
14384#define TIM_CCMR2_CC3S_Pos (0U)
14385#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
14386#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
14387#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
14388#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
14389
14390#define TIM_CCMR2_OC3FE_Pos (2U)
14391#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
14392#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
14393#define TIM_CCMR2_OC3PE_Pos (3U)
14394#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
14395#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
14396
14397#define TIM_CCMR2_OC3M_Pos (4U)
14398#define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
14399#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
14400#define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
14401#define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
14402#define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
14403#define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
14404
14405#define TIM_CCMR2_OC3CE_Pos (7U)
14406#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
14407#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
14408
14409#define TIM_CCMR2_CC4S_Pos (8U)
14410#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
14411#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
14412#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
14413#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
14414
14415#define TIM_CCMR2_OC4FE_Pos (10U)
14416#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
14417#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
14418#define TIM_CCMR2_OC4PE_Pos (11U)
14419#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
14420#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
14421
14422#define TIM_CCMR2_OC4M_Pos (12U)
14423#define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
14424#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
14425#define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
14426#define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
14427#define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
14428#define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
14429
14430#define TIM_CCMR2_OC4CE_Pos (15U)
14431#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
14432#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
14433
14434/*----------------------------------------------------------------------------*/
14435#define TIM_CCMR2_IC3PSC_Pos (2U)
14436#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
14437#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
14438#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
14439#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
14440
14441#define TIM_CCMR2_IC3F_Pos (4U)
14442#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
14443#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
14444#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
14445#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
14446#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
14447#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
14448
14449#define TIM_CCMR2_IC4PSC_Pos (10U)
14450#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
14451#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
14452#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
14453#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
14454
14455#define TIM_CCMR2_IC4F_Pos (12U)
14456#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
14457#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
14458#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
14459#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
14460#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
14461#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
14462
14463/****************** Bit definition for TIM_CCMR3 register *******************/
14464#define TIM_CCMR3_OC5FE_Pos (2U)
14465#define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
14466#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
14467#define TIM_CCMR3_OC5PE_Pos (3U)
14468#define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
14469#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
14470
14471#define TIM_CCMR3_OC5M_Pos (4U)
14472#define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
14473#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
14474#define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
14475#define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
14476#define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
14477#define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
14478
14479#define TIM_CCMR3_OC5CE_Pos (7U)
14480#define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
14481#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
14482
14483#define TIM_CCMR3_OC6FE_Pos (10U)
14484#define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
14485#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
14486#define TIM_CCMR3_OC6PE_Pos (11U)
14487#define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
14488#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
14489
14490#define TIM_CCMR3_OC6M_Pos (12U)
14491#define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
14492#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
14493#define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
14494#define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
14495#define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
14496#define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
14497
14498#define TIM_CCMR3_OC6CE_Pos (15U)
14499#define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
14500#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
14501
14502/******************* Bit definition for TIM_CCER register *******************/
14503#define TIM_CCER_CC1E_Pos (0U)
14504#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
14505#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
14506#define TIM_CCER_CC1P_Pos (1U)
14507#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
14508#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
14509#define TIM_CCER_CC1NE_Pos (2U)
14510#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
14511#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
14512#define TIM_CCER_CC1NP_Pos (3U)
14513#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
14514#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
14515#define TIM_CCER_CC2E_Pos (4U)
14516#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
14517#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
14518#define TIM_CCER_CC2P_Pos (5U)
14519#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
14520#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
14521#define TIM_CCER_CC2NE_Pos (6U)
14522#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
14523#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
14524#define TIM_CCER_CC2NP_Pos (7U)
14525#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
14526#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
14527#define TIM_CCER_CC3E_Pos (8U)
14528#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
14529#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
14530#define TIM_CCER_CC3P_Pos (9U)
14531#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
14532#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
14533#define TIM_CCER_CC3NE_Pos (10U)
14534#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
14535#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
14536#define TIM_CCER_CC3NP_Pos (11U)
14537#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
14538#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
14539#define TIM_CCER_CC4E_Pos (12U)
14540#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
14541#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
14542#define TIM_CCER_CC4P_Pos (13U)
14543#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
14544#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
14545#define TIM_CCER_CC4NP_Pos (15U)
14546#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
14547#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
14548#define TIM_CCER_CC5E_Pos (16U)
14549#define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
14550#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
14551#define TIM_CCER_CC5P_Pos (17U)
14552#define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
14553#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
14554#define TIM_CCER_CC6E_Pos (20U)
14555#define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
14556#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
14557#define TIM_CCER_CC6P_Pos (21U)
14558#define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
14559#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
14560
14561/******************* Bit definition for TIM_CNT register ********************/
14562#define TIM_CNT_CNT_Pos (0U)
14563#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
14564#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
14565#define TIM_CNT_UIFCPY_Pos (31U)
14566#define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
14567#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
14568
14569/******************* Bit definition for TIM_PSC register ********************/
14570#define TIM_PSC_PSC_Pos (0U)
14571#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
14572#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
14573
14574/******************* Bit definition for TIM_ARR register ********************/
14575#define TIM_ARR_ARR_Pos (0U)
14576#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
14577#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
14578
14579/******************* Bit definition for TIM_RCR register ********************/
14580#define TIM_RCR_REP_Pos (0U)
14581#define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
14582#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
14583
14584/******************* Bit definition for TIM_CCR1 register *******************/
14585#define TIM_CCR1_CCR1_Pos (0U)
14586#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
14587#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
14588
14589/******************* Bit definition for TIM_CCR2 register *******************/
14590#define TIM_CCR2_CCR2_Pos (0U)
14591#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
14592#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
14593
14594/******************* Bit definition for TIM_CCR3 register *******************/
14595#define TIM_CCR3_CCR3_Pos (0U)
14596#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
14597#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
14598
14599/******************* Bit definition for TIM_CCR4 register *******************/
14600#define TIM_CCR4_CCR4_Pos (0U)
14601#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
14602#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
14603
14604/******************* Bit definition for TIM_CCR5 register *******************/
14605#define TIM_CCR5_CCR5_Pos (0U)
14606#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
14607#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
14608#define TIM_CCR5_GC5C1_Pos (29U)
14609#define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
14610#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
14611#define TIM_CCR5_GC5C2_Pos (30U)
14612#define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
14613#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
14614#define TIM_CCR5_GC5C3_Pos (31U)
14615#define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
14616#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
14617
14618/******************* Bit definition for TIM_CCR6 register *******************/
14619#define TIM_CCR6_CCR6_Pos (0U)
14620#define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
14621#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
14622
14623/******************* Bit definition for TIM_BDTR register *******************/
14624#define TIM_BDTR_DTG_Pos (0U)
14625#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
14626#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
14627#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
14628#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
14629#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
14630#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
14631#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
14632#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
14633#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
14634#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
14635
14636#define TIM_BDTR_LOCK_Pos (8U)
14637#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
14638#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
14639#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
14640#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
14641
14642#define TIM_BDTR_OSSI_Pos (10U)
14643#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
14644#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
14645#define TIM_BDTR_OSSR_Pos (11U)
14646#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
14647#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
14648#define TIM_BDTR_BKE_Pos (12U)
14649#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
14650#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
14651#define TIM_BDTR_BKP_Pos (13U)
14652#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
14653#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
14654#define TIM_BDTR_AOE_Pos (14U)
14655#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
14656#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
14657#define TIM_BDTR_MOE_Pos (15U)
14658#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
14659#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
14660
14661#define TIM_BDTR_BKF_Pos (16U)
14662#define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
14663#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
14664#define TIM_BDTR_BK2F_Pos (20U)
14665#define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
14666#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
14667
14668#define TIM_BDTR_BK2E_Pos (24U)
14669#define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
14670#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
14671#define TIM_BDTR_BK2P_Pos (25U)
14672#define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
14673#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
14674
14675/******************* Bit definition for TIM_DCR register ********************/
14676#define TIM_DCR_DBA_Pos (0U)
14677#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
14678#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
14679#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
14680#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
14681#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
14682#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
14683#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
14684
14685#define TIM_DCR_DBL_Pos (8U)
14686#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
14687#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
14688#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
14689#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
14690#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
14691#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
14692#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
14693
14694/******************* Bit definition for TIM_DMAR register *******************/
14695#define TIM_DMAR_DMAB_Pos (0U)
14696#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
14697#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
14698
14699/******************* Bit definition for TIM1_OR1 register *******************/
14700#define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
14701#define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
14702#define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
14703#define TIM1_OR1_ETR_ADC1_RMP_0 (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
14704#define TIM1_OR1_ETR_ADC1_RMP_1 (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
14705
14706#define TIM1_OR1_ETR_ADC3_RMP_Pos (2U)
14707#define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */
14708#define TIM1_OR1_ETR_ADC3_RMP TIM1_OR1_ETR_ADC3_RMP_Msk /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
14709#define TIM1_OR1_ETR_ADC3_RMP_0 (0x1U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */
14710#define TIM1_OR1_ETR_ADC3_RMP_1 (0x2U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
14711
14712#define TIM1_OR1_TI1_RMP_Pos (4U)
14713#define TIM1_OR1_TI1_RMP_Msk (0x1U << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
14714#define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */
14715
14716/******************* Bit definition for TIM1_OR2 register *******************/
14717#define TIM1_OR2_BKINE_Pos (0U)
14718#define TIM1_OR2_BKINE_Msk (0x1U << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */
14719#define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */
14720#define TIM1_OR2_BKCMP1E_Pos (1U)
14721#define TIM1_OR2_BKCMP1E_Msk (0x1U << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
14722#define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
14723#define TIM1_OR2_BKCMP2E_Pos (2U)
14724#define TIM1_OR2_BKCMP2E_Msk (0x1U << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
14725#define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
14726#define TIM1_OR2_BKDF1BK0E_Pos (8U)
14727#define TIM1_OR2_BKDF1BK0E_Msk (0x1U << TIM1_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
14728#define TIM1_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
14729#define TIM1_OR2_BKINP_Pos (9U)
14730#define TIM1_OR2_BKINP_Msk (0x1U << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */
14731#define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
14732#define TIM1_OR2_BKCMP1P_Pos (10U)
14733#define TIM1_OR2_BKCMP1P_Msk (0x1U << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
14734#define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
14735#define TIM1_OR2_BKCMP2P_Pos (11U)
14736#define TIM1_OR2_BKCMP2P_Msk (0x1U << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
14737#define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
14738
14739#define TIM1_OR2_ETRSEL_Pos (14U)
14740#define TIM1_OR2_ETRSEL_Msk (0x7U << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
14741#define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
14742#define TIM1_OR2_ETRSEL_0 (0x1U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */
14743#define TIM1_OR2_ETRSEL_1 (0x2U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */
14744#define TIM1_OR2_ETRSEL_2 (0x4U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */
14745
14746/******************* Bit definition for TIM1_OR3 register *******************/
14747#define TIM1_OR3_BK2INE_Pos (0U)
14748#define TIM1_OR3_BK2INE_Msk (0x1U << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */
14749#define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
14750#define TIM1_OR3_BK2CMP1E_Pos (1U)
14751#define TIM1_OR3_BK2CMP1E_Msk (0x1U << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
14752#define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
14753#define TIM1_OR3_BK2CMP2E_Pos (2U)
14754#define TIM1_OR3_BK2CMP2E_Msk (0x1U << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
14755#define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
14756#define TIM1_OR3_BK2DF1BK1E_Pos (8U)
14757#define TIM1_OR3_BK2DF1BK1E_Msk (0x1U << TIM1_OR3_BK2DF1BK1E_Pos) /*!< 0x00000100 */
14758#define TIM1_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E_Msk /*!<BRK2 DFSDM1_BREAK[1] enable */
14759#define TIM1_OR3_BK2INP_Pos (9U)
14760#define TIM1_OR3_BK2INP_Msk (0x1U << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */
14761#define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
14762#define TIM1_OR3_BK2CMP1P_Pos (10U)
14763#define TIM1_OR3_BK2CMP1P_Msk (0x1U << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
14764#define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
14765#define TIM1_OR3_BK2CMP2P_Pos (11U)
14766#define TIM1_OR3_BK2CMP2P_Msk (0x1U << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
14767#define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
14768
14769/******************* Bit definition for TIM8_OR1 register *******************/
14770#define TIM8_OR1_ETR_ADC2_RMP_Pos (0U)
14771#define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000003 */
14772#define TIM8_OR1_ETR_ADC2_RMP TIM8_OR1_ETR_ADC2_RMP_Msk /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
14773#define TIM8_OR1_ETR_ADC2_RMP_0 (0x1U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000001 */
14774#define TIM8_OR1_ETR_ADC2_RMP_1 (0x2U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000002 */
14775
14776#define TIM8_OR1_ETR_ADC3_RMP_Pos (2U)
14777#define TIM8_OR1_ETR_ADC3_RMP_Msk (0x3U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */
14778#define TIM8_OR1_ETR_ADC3_RMP TIM8_OR1_ETR_ADC3_RMP_Msk /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
14779#define TIM8_OR1_ETR_ADC3_RMP_0 (0x1U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */
14780#define TIM8_OR1_ETR_ADC3_RMP_1 (0x2U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
14781
14782#define TIM8_OR1_TI1_RMP_Pos (4U)
14783#define TIM8_OR1_TI1_RMP_Msk (0x1U << TIM8_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
14784#define TIM8_OR1_TI1_RMP TIM8_OR1_TI1_RMP_Msk /*!<TIM8 Input Capture 1 remap */
14785
14786/******************* Bit definition for TIM8_OR2 register *******************/
14787#define TIM8_OR2_BKINE_Pos (0U)
14788#define TIM8_OR2_BKINE_Msk (0x1U << TIM8_OR2_BKINE_Pos) /*!< 0x00000001 */
14789#define TIM8_OR2_BKINE TIM8_OR2_BKINE_Msk /*!<BRK BKIN input enable */
14790#define TIM8_OR2_BKCMP1E_Pos (1U)
14791#define TIM8_OR2_BKCMP1E_Msk (0x1U << TIM8_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
14792#define TIM8_OR2_BKCMP1E TIM8_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
14793#define TIM8_OR2_BKCMP2E_Pos (2U)
14794#define TIM8_OR2_BKCMP2E_Msk (0x1U << TIM8_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
14795#define TIM8_OR2_BKCMP2E TIM8_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
14796#define TIM8_OR2_BKDF1BK2E_Pos (8U)
14797#define TIM8_OR2_BKDF1BK2E_Msk (0x1U << TIM8_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
14798#define TIM8_OR2_BKDF1BK2E TIM8_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
14799#define TIM8_OR2_BKINP_Pos (9U)
14800#define TIM8_OR2_BKINP_Msk (0x1U << TIM8_OR2_BKINP_Pos) /*!< 0x00000200 */
14801#define TIM8_OR2_BKINP TIM8_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
14802#define TIM8_OR2_BKCMP1P_Pos (10U)
14803#define TIM8_OR2_BKCMP1P_Msk (0x1U << TIM8_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
14804#define TIM8_OR2_BKCMP1P TIM8_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
14805#define TIM8_OR2_BKCMP2P_Pos (11U)
14806#define TIM8_OR2_BKCMP2P_Msk (0x1U << TIM8_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
14807#define TIM8_OR2_BKCMP2P TIM8_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
14808
14809#define TIM8_OR2_ETRSEL_Pos (14U)
14810#define TIM8_OR2_ETRSEL_Msk (0x7U << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
14811#define TIM8_OR2_ETRSEL TIM8_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
14812#define TIM8_OR2_ETRSEL_0 (0x1U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */
14813#define TIM8_OR2_ETRSEL_1 (0x2U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */
14814#define TIM8_OR2_ETRSEL_2 (0x4U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
14815
14816/******************* Bit definition for TIM8_OR3 register *******************/
14817#define TIM8_OR3_BK2INE_Pos (0U)
14818#define TIM8_OR3_BK2INE_Msk (0x1U << TIM8_OR3_BK2INE_Pos) /*!< 0x00000001 */
14819#define TIM8_OR3_BK2INE TIM8_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
14820#define TIM8_OR3_BK2CMP1E_Pos (1U)
14821#define TIM8_OR3_BK2CMP1E_Msk (0x1U << TIM8_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
14822#define TIM8_OR3_BK2CMP1E TIM8_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
14823#define TIM8_OR3_BK2CMP2E_Pos (2U)
14824#define TIM8_OR3_BK2CMP2E_Msk (0x1U << TIM8_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
14825#define TIM8_OR3_BK2CMP2E TIM8_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
14826#define TIM8_OR3_BK2DF1BK3E_Pos (8U)
14827#define TIM8_OR3_BK2DF1BK3E_Msk (0x1U << TIM8_OR3_BK2DF1BK3E_Pos) /*!< 0x00000100 */
14828#define TIM8_OR3_BK2DF1BK3E TIM8_OR3_BK2DF1BK3E_Msk /*!<BRK2 DFSDM1_BREAK[3] enable */
14829#define TIM8_OR3_BK2INP_Pos (9U)
14830#define TIM8_OR3_BK2INP_Msk (0x1U << TIM8_OR3_BK2INP_Pos) /*!< 0x00000200 */
14831#define TIM8_OR3_BK2INP TIM8_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
14832#define TIM8_OR3_BK2CMP1P_Pos (10U)
14833#define TIM8_OR3_BK2CMP1P_Msk (0x1U << TIM8_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
14834#define TIM8_OR3_BK2CMP1P TIM8_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
14835#define TIM8_OR3_BK2CMP2P_Pos (11U)
14836#define TIM8_OR3_BK2CMP2P_Msk (0x1U << TIM8_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
14837#define TIM8_OR3_BK2CMP2P TIM8_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
14838
14839/******************* Bit definition for TIM2_OR1 register *******************/
14840#define TIM2_OR1_ITR1_RMP_Pos (0U)
14841#define TIM2_OR1_ITR1_RMP_Msk (0x1U << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */
14842#define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
14843#define TIM2_OR1_ETR1_RMP_Pos (1U)
14844#define TIM2_OR1_ETR1_RMP_Msk (0x1U << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */
14845#define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */
14846
14847#define TIM2_OR1_TI4_RMP_Pos (2U)
14848#define TIM2_OR1_TI4_RMP_Msk (0x3U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */
14849#define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
14850#define TIM2_OR1_TI4_RMP_0 (0x1U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */
14851#define TIM2_OR1_TI4_RMP_1 (0x2U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */
14852
14853/******************* Bit definition for TIM2_OR2 register *******************/
14854#define TIM2_OR2_ETRSEL_Pos (14U)
14855#define TIM2_OR2_ETRSEL_Msk (0x7U << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
14856#define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
14857#define TIM2_OR2_ETRSEL_0 (0x1U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */
14858#define TIM2_OR2_ETRSEL_1 (0x2U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */
14859#define TIM2_OR2_ETRSEL_2 (0x4U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */
14860
14861/******************* Bit definition for TIM3_OR1 register *******************/
14862#define TIM3_OR1_TI1_RMP_Pos (0U)
14863#define TIM3_OR1_TI1_RMP_Msk (0x3U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
14864#define TIM3_OR1_TI1_RMP TIM3_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
14865#define TIM3_OR1_TI1_RMP_0 (0x1U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14866#define TIM3_OR1_TI1_RMP_1 (0x2U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
14867
14868/******************* Bit definition for TIM3_OR2 register *******************/
14869#define TIM3_OR2_ETRSEL_Pos (14U)
14870#define TIM3_OR2_ETRSEL_Msk (0x7U << TIM3_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
14871#define TIM3_OR2_ETRSEL TIM3_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
14872#define TIM3_OR2_ETRSEL_0 (0x1U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00004000 */
14873#define TIM3_OR2_ETRSEL_1 (0x2U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00008000 */
14874#define TIM3_OR2_ETRSEL_2 (0x4U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00010000 */
14875
14876/******************* Bit definition for TIM15_OR1 register ******************/
14877#define TIM15_OR1_TI1_RMP_Pos (0U)
14878#define TIM15_OR1_TI1_RMP_Msk (0x1U << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14879#define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */
14880
14881#define TIM15_OR1_ENCODER_MODE_Pos (1U)
14882#define TIM15_OR1_ENCODER_MODE_Msk (0x3U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */
14883#define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
14884#define TIM15_OR1_ENCODER_MODE_0 (0x1U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */
14885#define TIM15_OR1_ENCODER_MODE_1 (0x2U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */
14886
14887/******************* Bit definition for TIM15_OR2 register ******************/
14888#define TIM15_OR2_BKINE_Pos (0U)
14889#define TIM15_OR2_BKINE_Msk (0x1U << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */
14890#define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */
14891#define TIM15_OR2_BKCMP1E_Pos (1U)
14892#define TIM15_OR2_BKCMP1E_Msk (0x1U << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
14893#define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
14894#define TIM15_OR2_BKCMP2E_Pos (2U)
14895#define TIM15_OR2_BKCMP2E_Msk (0x1U << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
14896#define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
14897#define TIM15_OR2_BKDF1BK0E_Pos (8U)
14898#define TIM15_OR2_BKDF1BK0E_Msk (0x1U << TIM15_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
14899#define TIM15_OR2_BKDF1BK0E TIM15_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
14900#define TIM15_OR2_BKINP_Pos (9U)
14901#define TIM15_OR2_BKINP_Msk (0x1U << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */
14902#define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
14903#define TIM15_OR2_BKCMP1P_Pos (10U)
14904#define TIM15_OR2_BKCMP1P_Msk (0x1U << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
14905#define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
14906#define TIM15_OR2_BKCMP2P_Pos (11U)
14907#define TIM15_OR2_BKCMP2P_Msk (0x1U << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
14908#define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
14909
14910/******************* Bit definition for TIM16_OR1 register ******************/
14911#define TIM16_OR1_TI1_RMP_Pos (0U)
14912#define TIM16_OR1_TI1_RMP_Msk (0x3U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
14913#define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
14914#define TIM16_OR1_TI1_RMP_0 (0x1U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14915#define TIM16_OR1_TI1_RMP_1 (0x2U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
14916
14917/******************* Bit definition for TIM16_OR2 register ******************/
14918#define TIM16_OR2_BKINE_Pos (0U)
14919#define TIM16_OR2_BKINE_Msk (0x1U << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */
14920#define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */
14921#define TIM16_OR2_BKCMP1E_Pos (1U)
14922#define TIM16_OR2_BKCMP1E_Msk (0x1U << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
14923#define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
14924#define TIM16_OR2_BKCMP2E_Pos (2U)
14925#define TIM16_OR2_BKCMP2E_Msk (0x1U << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
14926#define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
14927#define TIM16_OR2_BKDF1BK1E_Pos (8U)
14928#define TIM16_OR2_BKDF1BK1E_Msk (0x1U << TIM16_OR2_BKDF1BK1E_Pos) /*!< 0x00000100 */
14929#define TIM16_OR2_BKDF1BK1E TIM16_OR2_BKDF1BK1E_Msk /*!<BRK DFSDM1_BREAK[1] enable */
14930#define TIM16_OR2_BKINP_Pos (9U)
14931#define TIM16_OR2_BKINP_Msk (0x1U << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */
14932#define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
14933#define TIM16_OR2_BKCMP1P_Pos (10U)
14934#define TIM16_OR2_BKCMP1P_Msk (0x1U << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
14935#define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
14936#define TIM16_OR2_BKCMP2P_Pos (11U)
14937#define TIM16_OR2_BKCMP2P_Msk (0x1U << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
14938#define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
14939
14940/******************* Bit definition for TIM17_OR1 register ******************/
14941#define TIM17_OR1_TI1_RMP_Pos (0U)
14942#define TIM17_OR1_TI1_RMP_Msk (0x3U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
14943#define TIM17_OR1_TI1_RMP TIM17_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
14944#define TIM17_OR1_TI1_RMP_0 (0x1U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14945#define TIM17_OR1_TI1_RMP_1 (0x2U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
14946
14947/******************* Bit definition for TIM17_OR2 register ******************/
14948#define TIM17_OR2_BKINE_Pos (0U)
14949#define TIM17_OR2_BKINE_Msk (0x1U << TIM17_OR2_BKINE_Pos) /*!< 0x00000001 */
14950#define TIM17_OR2_BKINE TIM17_OR2_BKINE_Msk /*!<BRK BKIN input enable */
14951#define TIM17_OR2_BKCMP1E_Pos (1U)
14952#define TIM17_OR2_BKCMP1E_Msk (0x1U << TIM17_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
14953#define TIM17_OR2_BKCMP1E TIM17_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
14954#define TIM17_OR2_BKCMP2E_Pos (2U)
14955#define TIM17_OR2_BKCMP2E_Msk (0x1U << TIM17_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
14956#define TIM17_OR2_BKCMP2E TIM17_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
14957#define TIM17_OR2_BKDF1BK2E_Pos (8U)
14958#define TIM17_OR2_BKDF1BK2E_Msk (0x1U << TIM17_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
14959#define TIM17_OR2_BKDF1BK2E TIM17_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
14960#define TIM17_OR2_BKINP_Pos (9U)
14961#define TIM17_OR2_BKINP_Msk (0x1U << TIM17_OR2_BKINP_Pos) /*!< 0x00000200 */
14962#define TIM17_OR2_BKINP TIM17_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
14963#define TIM17_OR2_BKCMP1P_Pos (10U)
14964#define TIM17_OR2_BKCMP1P_Msk (0x1U << TIM17_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
14965#define TIM17_OR2_BKCMP1P TIM17_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
14966#define TIM17_OR2_BKCMP2P_Pos (11U)
14967#define TIM17_OR2_BKCMP2P_Msk (0x1U << TIM17_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
14968#define TIM17_OR2_BKCMP2P TIM17_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
14969
14970/******************************************************************************/
14971/* */
14972/* Low Power Timer (LPTTIM) */
14973/* */
14974/******************************************************************************/
14975/****************** Bit definition for LPTIM_ISR register *******************/
14976#define LPTIM_ISR_CMPM_Pos (0U)
14977#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
14978#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
14979#define LPTIM_ISR_ARRM_Pos (1U)
14980#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
14981#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
14982#define LPTIM_ISR_EXTTRIG_Pos (2U)
14983#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
14984#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
14985#define LPTIM_ISR_CMPOK_Pos (3U)
14986#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
14987#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
14988#define LPTIM_ISR_ARROK_Pos (4U)
14989#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
14990#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
14991#define LPTIM_ISR_UP_Pos (5U)
14992#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
14993#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
14994#define LPTIM_ISR_DOWN_Pos (6U)
14995#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
14996#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
14997
14998/****************** Bit definition for LPTIM_ICR register *******************/
14999#define LPTIM_ICR_CMPMCF_Pos (0U)
15000#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
15001#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
15002#define LPTIM_ICR_ARRMCF_Pos (1U)
15003#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
15004#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
15005#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
15006#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
15007#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
15008#define LPTIM_ICR_CMPOKCF_Pos (3U)
15009#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
15010#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
15011#define LPTIM_ICR_ARROKCF_Pos (4U)
15012#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
15013#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
15014#define LPTIM_ICR_UPCF_Pos (5U)
15015#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
15016#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
15017#define LPTIM_ICR_DOWNCF_Pos (6U)
15018#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
15019#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
15020
15021/****************** Bit definition for LPTIM_IER register ********************/
15022#define LPTIM_IER_CMPMIE_Pos (0U)
15023#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
15024#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
15025#define LPTIM_IER_ARRMIE_Pos (1U)
15026#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
15027#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
15028#define LPTIM_IER_EXTTRIGIE_Pos (2U)
15029#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
15030#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
15031#define LPTIM_IER_CMPOKIE_Pos (3U)
15032#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
15033#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
15034#define LPTIM_IER_ARROKIE_Pos (4U)
15035#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
15036#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
15037#define LPTIM_IER_UPIE_Pos (5U)
15038#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
15039#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
15040#define LPTIM_IER_DOWNIE_Pos (6U)
15041#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
15042#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
15043
15044/****************** Bit definition for LPTIM_CFGR register *******************/
15045#define LPTIM_CFGR_CKSEL_Pos (0U)
15046#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
15047#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
15048
15049#define LPTIM_CFGR_CKPOL_Pos (1U)
15050#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
15051#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
15052#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
15053#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
15054
15055#define LPTIM_CFGR_CKFLT_Pos (3U)
15056#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
15057#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
15058#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
15059#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
15060
15061#define LPTIM_CFGR_TRGFLT_Pos (6U)
15062#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
15063#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
15064#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
15065#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
15066
15067#define LPTIM_CFGR_PRESC_Pos (9U)
15068#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
15069#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
15070#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
15071#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
15072#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
15073
15074#define LPTIM_CFGR_TRIGSEL_Pos (13U)
15075#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
15076#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
15077#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
15078#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
15079#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
15080
15081#define LPTIM_CFGR_TRIGEN_Pos (17U)
15082#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
15083#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
15084#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
15085#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
15086
15087#define LPTIM_CFGR_TIMOUT_Pos (19U)
15088#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
15089#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
15090#define LPTIM_CFGR_WAVE_Pos (20U)
15091#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
15092#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
15093#define LPTIM_CFGR_WAVPOL_Pos (21U)
15094#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
15095#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
15096#define LPTIM_CFGR_PRELOAD_Pos (22U)
15097#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
15098#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
15099#define LPTIM_CFGR_COUNTMODE_Pos (23U)
15100#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
15101#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
15102#define LPTIM_CFGR_ENC_Pos (24U)
15103#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
15104#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
15105
15106/****************** Bit definition for LPTIM_CR register ********************/
15107#define LPTIM_CR_ENABLE_Pos (0U)
15108#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
15109#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
15110#define LPTIM_CR_SNGSTRT_Pos (1U)
15111#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
15112#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
15113#define LPTIM_CR_CNTSTRT_Pos (2U)
15114#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
15115#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
15116
15117/****************** Bit definition for LPTIM_CMP register *******************/
15118#define LPTIM_CMP_CMP_Pos (0U)
15119#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
15120#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
15121
15122/****************** Bit definition for LPTIM_ARR register *******************/
15123#define LPTIM_ARR_ARR_Pos (0U)
15124#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
15125#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
15126
15127/****************** Bit definition for LPTIM_CNT register *******************/
15128#define LPTIM_CNT_CNT_Pos (0U)
15129#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
15130#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
15131
15132/****************** Bit definition for LPTIM_OR register ********************/
15133#define LPTIM_OR_OR_Pos (0U)
15134#define LPTIM_OR_OR_Msk (0x3U << LPTIM_OR_OR_Pos) /*!< 0x00000003 */
15135#define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */
15136#define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */
15137#define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */
15138
15139/******************************************************************************/
15140/* */
15141/* Analog Comparators (COMP) */
15142/* */
15143/******************************************************************************/
15144/********************** Bit definition for COMP_CSR register ****************/
15145#define COMP_CSR_EN_Pos (0U)
15146#define COMP_CSR_EN_Msk (0x1U << COMP_CSR_EN_Pos) /*!< 0x00000001 */
15147#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
15148
15149#define COMP_CSR_PWRMODE_Pos (2U)
15150#define COMP_CSR_PWRMODE_Msk (0x3U << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */
15151#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
15152#define COMP_CSR_PWRMODE_0 (0x1U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */
15153#define COMP_CSR_PWRMODE_1 (0x2U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */
15154
15155#define COMP_CSR_INMSEL_Pos (4U)
15156#define COMP_CSR_INMSEL_Msk (0x7U << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
15157#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
15158#define COMP_CSR_INMSEL_0 (0x1U << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
15159#define COMP_CSR_INMSEL_1 (0x2U << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
15160#define COMP_CSR_INMSEL_2 (0x4U << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
15161
15162#define COMP_CSR_INPSEL_Pos (7U)
15163#define COMP_CSR_INPSEL_Msk (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
15164#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
15165#define COMP_CSR_INPSEL_0 (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
15166
15167#define COMP_CSR_WINMODE_Pos (9U)
15168#define COMP_CSR_WINMODE_Msk (0x1U << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */
15169#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
15170
15171#define COMP_CSR_POLARITY_Pos (15U)
15172#define COMP_CSR_POLARITY_Msk (0x1U << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
15173#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
15174
15175#define COMP_CSR_HYST_Pos (16U)
15176#define COMP_CSR_HYST_Msk (0x3U << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
15177#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
15178#define COMP_CSR_HYST_0 (0x1U << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
15179#define COMP_CSR_HYST_1 (0x2U << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
15180
15181#define COMP_CSR_BLANKING_Pos (18U)
15182#define COMP_CSR_BLANKING_Msk (0x7U << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
15183#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
15184#define COMP_CSR_BLANKING_0 (0x1U << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
15185#define COMP_CSR_BLANKING_1 (0x2U << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
15186#define COMP_CSR_BLANKING_2 (0x4U << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
15187
15188#define COMP_CSR_BRGEN_Pos (22U)
15189#define COMP_CSR_BRGEN_Msk (0x1U << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
15190#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
15191#define COMP_CSR_SCALEN_Pos (23U)
15192#define COMP_CSR_SCALEN_Msk (0x1U << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
15193#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
15194
15195#define COMP_CSR_VALUE_Pos (30U)
15196#define COMP_CSR_VALUE_Msk (0x1U << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
15197#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
15198
15199#define COMP_CSR_LOCK_Pos (31U)
15200#define COMP_CSR_LOCK_Msk (0x1U << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
15201#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
15202
15203/******************************************************************************/
15204/* */
15205/* Operational Amplifier (OPAMP) */
15206/* */
15207/******************************************************************************/
15208/********************* Bit definition for OPAMPx_CSR register ***************/
15209#define OPAMP_CSR_OPAMPxEN_Pos (0U)
15210#define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
15211#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
15212#define OPAMP_CSR_OPALPM_Pos (1U)
15213#define OPAMP_CSR_OPALPM_Msk (0x1U << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */
15214#define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */
15215
15216#define OPAMP_CSR_OPAMODE_Pos (2U)
15217#define OPAMP_CSR_OPAMODE_Msk (0x3U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */
15218#define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */
15219#define OPAMP_CSR_OPAMODE_0 (0x1U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */
15220#define OPAMP_CSR_OPAMODE_1 (0x2U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */
15221
15222#define OPAMP_CSR_PGGAIN_Pos (4U)
15223#define OPAMP_CSR_PGGAIN_Msk (0x3U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000030 */
15224#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
15225#define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000010 */
15226#define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000020 */
15227
15228#define OPAMP_CSR_VMSEL_Pos (8U)
15229#define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000300 */
15230#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
15231#define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000100 */
15232#define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000200 */
15233
15234#define OPAMP_CSR_VPSEL_Pos (10U)
15235#define OPAMP_CSR_VPSEL_Msk (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000400 */
15236#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
15237#define OPAMP_CSR_CALON_Pos (12U)
15238#define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */
15239#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
15240#define OPAMP_CSR_CALSEL_Pos (13U)
15241#define OPAMP_CSR_CALSEL_Msk (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
15242#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
15243#define OPAMP_CSR_USERTRIM_Pos (14U)
15244#define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */
15245#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
15246#define OPAMP_CSR_CALOUT_Pos (15U)
15247#define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */
15248#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
15249
15250/********************* Bit definition for OPAMP1_CSR register ***************/
15251#define OPAMP1_CSR_OPAEN_Pos (0U)
15252#define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
15253#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
15254#define OPAMP1_CSR_OPALPM_Pos (1U)
15255#define OPAMP1_CSR_OPALPM_Msk (0x1U << OPAMP1_CSR_OPALPM_Pos) /*!< 0x00000002 */
15256#define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk /*!< Operational amplifier1 Low Power Mode */
15257
15258#define OPAMP1_CSR_OPAMODE_Pos (2U)
15259#define OPAMP1_CSR_OPAMODE_Msk (0x3U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x0000000C */
15260#define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk /*!< Operational amplifier1 PGA mode */
15261#define OPAMP1_CSR_OPAMODE_0 (0x1U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000004 */
15262#define OPAMP1_CSR_OPAMODE_1 (0x2U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000008 */
15263
15264#define OPAMP1_CSR_PGAGAIN_Pos (4U)
15265#define OPAMP1_CSR_PGAGAIN_Msk (0x3U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
15266#define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
15267#define OPAMP1_CSR_PGAGAIN_0 (0x1U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
15268#define OPAMP1_CSR_PGAGAIN_1 (0x2U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
15269
15270#define OPAMP1_CSR_VMSEL_Pos (8U)
15271#define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000300 */
15272#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
15273#define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000100 */
15274#define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000200 */
15275
15276#define OPAMP1_CSR_VPSEL_Pos (10U)
15277#define OPAMP1_CSR_VPSEL_Msk (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */
15278#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
15279#define OPAMP1_CSR_CALON_Pos (12U)
15280#define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00001000 */
15281#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
15282#define OPAMP1_CSR_CALSEL_Pos (13U)
15283#define OPAMP1_CSR_CALSEL_Msk (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
15284#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
15285#define OPAMP1_CSR_USERTRIM_Pos (14U)
15286#define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00004000 */
15287#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
15288#define OPAMP1_CSR_CALOUT_Pos (15U)
15289#define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x00008000 */
15290#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
15291
15292#define OPAMP1_CSR_OPARANGE_Pos (31U)
15293#define OPAMP1_CSR_OPARANGE_Msk (0x1U << OPAMP1_CSR_OPARANGE_Pos) /*!< 0x80000000 */
15294#define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
15295
15296/********************* Bit definition for OPAMP2_CSR register ***************/
15297#define OPAMP2_CSR_OPAEN_Pos (0U)
15298#define OPAMP2_CSR_OPAEN_Msk (0x1U << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
15299#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
15300#define OPAMP2_CSR_OPALPM_Pos (1U)
15301#define OPAMP2_CSR_OPALPM_Msk (0x1U << OPAMP2_CSR_OPALPM_Pos) /*!< 0x00000002 */
15302#define OPAMP2_CSR_OPALPM OPAMP2_CSR_OPALPM_Msk /*!< Operational amplifier2 Low Power Mode */
15303
15304#define OPAMP2_CSR_OPAMODE_Pos (2U)
15305#define OPAMP2_CSR_OPAMODE_Msk (0x3U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x0000000C */
15306#define OPAMP2_CSR_OPAMODE OPAMP2_CSR_OPAMODE_Msk /*!< Operational amplifier2 PGA mode */
15307#define OPAMP2_CSR_OPAMODE_0 (0x1U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000004 */
15308#define OPAMP2_CSR_OPAMODE_1 (0x2U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000008 */
15309
15310#define OPAMP2_CSR_PGAGAIN_Pos (4U)
15311#define OPAMP2_CSR_PGAGAIN_Msk (0x3U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
15312#define OPAMP2_CSR_PGAGAIN OPAMP2_CSR_PGAGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
15313#define OPAMP2_CSR_PGAGAIN_0 (0x1U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
15314#define OPAMP2_CSR_PGAGAIN_1 (0x2U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
15315
15316#define OPAMP2_CSR_VMSEL_Pos (8U)
15317#define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000300 */
15318#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
15319#define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000100 */
15320#define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000200 */
15321
15322#define OPAMP2_CSR_VPSEL_Pos (10U)
15323#define OPAMP2_CSR_VPSEL_Msk (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000400 */
15324#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
15325#define OPAMP2_CSR_CALON_Pos (12U)
15326#define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00001000 */
15327#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
15328#define OPAMP2_CSR_CALSEL_Pos (13U)
15329#define OPAMP2_CSR_CALSEL_Msk (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
15330#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
15331#define OPAMP2_CSR_USERTRIM_Pos (14U)
15332#define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00004000 */
15333#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
15334#define OPAMP2_CSR_CALOUT_Pos (15U)
15335#define OPAMP2_CSR_CALOUT_Msk (0x1U << OPAMP2_CSR_CALOUT_Pos) /*!< 0x00008000 */
15336#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
15337
15338/******************* Bit definition for OPAMP_OTR register ******************/
15339#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
15340#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
15341#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
15342#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
15343#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
15344#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
15345
15346/******************* Bit definition for OPAMP1_OTR register ******************/
15347#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
15348#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
15349#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
15350#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
15351#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
15352#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
15353
15354/******************* Bit definition for OPAMP2_OTR register ******************/
15355#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
15356#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
15357#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
15358#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
15359#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
15360#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
15361
15362/******************* Bit definition for OPAMP_LPOTR register ****************/
15363#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
15364#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
15365#define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
15366#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
15367#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
15368#define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
15369
15370/******************* Bit definition for OPAMP1_LPOTR register ****************/
15371#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
15372#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
15373#define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
15374#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
15375#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
15376#define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
15377
15378/******************* Bit definition for OPAMP2_LPOTR register ****************/
15379#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos (0U)
15380#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
15381#define OPAMP2_LPOTR_TRIMLPOFFSETN OPAMP2_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
15382#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos (8U)
15383#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
15384#define OPAMP2_LPOTR_TRIMLPOFFSETP OPAMP2_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
15385
15386/******************************************************************************/
15387/* */
15388/* Touch Sensing Controller (TSC) */
15389/* */
15390/******************************************************************************/
15391/******************* Bit definition for TSC_CR register *********************/
15392#define TSC_CR_TSCE_Pos (0U)
15393#define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
15394#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
15395#define TSC_CR_START_Pos (1U)
15396#define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
15397#define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
15398#define TSC_CR_AM_Pos (2U)
15399#define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
15400#define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
15401#define TSC_CR_SYNCPOL_Pos (3U)
15402#define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
15403#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
15404#define TSC_CR_IODEF_Pos (4U)
15405#define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
15406#define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
15407
15408#define TSC_CR_MCV_Pos (5U)
15409#define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
15410#define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
15411#define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
15412#define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
15413#define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
15414
15415#define TSC_CR_PGPSC_Pos (12U)
15416#define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
15417#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
15418#define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
15419#define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
15420#define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
15421
15422#define TSC_CR_SSPSC_Pos (15U)
15423#define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
15424#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
15425#define TSC_CR_SSE_Pos (16U)
15426#define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
15427#define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
15428
15429#define TSC_CR_SSD_Pos (17U)
15430#define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
15431#define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
15432#define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
15433#define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
15434#define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
15435#define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
15436#define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
15437#define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
15438#define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
15439
15440#define TSC_CR_CTPL_Pos (24U)
15441#define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
15442#define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
15443#define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
15444#define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
15445#define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
15446#define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
15447
15448#define TSC_CR_CTPH_Pos (28U)
15449#define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
15450#define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
15451#define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
15452#define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
15453#define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
15454#define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
15455
15456/******************* Bit definition for TSC_IER register ********************/
15457#define TSC_IER_EOAIE_Pos (0U)
15458#define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
15459#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
15460#define TSC_IER_MCEIE_Pos (1U)
15461#define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
15462#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
15463
15464/******************* Bit definition for TSC_ICR register ********************/
15465#define TSC_ICR_EOAIC_Pos (0U)
15466#define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
15467#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
15468#define TSC_ICR_MCEIC_Pos (1U)
15469#define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
15470#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
15471
15472/******************* Bit definition for TSC_ISR register ********************/
15473#define TSC_ISR_EOAF_Pos (0U)
15474#define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
15475#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
15476#define TSC_ISR_MCEF_Pos (1U)
15477#define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
15478#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
15479
15480/******************* Bit definition for TSC_IOHCR register ******************/
15481#define TSC_IOHCR_G1_IO1_Pos (0U)
15482#define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
15483#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
15484#define TSC_IOHCR_G1_IO2_Pos (1U)
15485#define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
15486#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
15487#define TSC_IOHCR_G1_IO3_Pos (2U)
15488#define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
15489#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
15490#define TSC_IOHCR_G1_IO4_Pos (3U)
15491#define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
15492#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
15493#define TSC_IOHCR_G2_IO1_Pos (4U)
15494#define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
15495#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
15496#define TSC_IOHCR_G2_IO2_Pos (5U)
15497#define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
15498#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
15499#define TSC_IOHCR_G2_IO3_Pos (6U)
15500#define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
15501#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
15502#define TSC_IOHCR_G2_IO4_Pos (7U)
15503#define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
15504#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
15505#define TSC_IOHCR_G3_IO1_Pos (8U)
15506#define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
15507#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
15508#define TSC_IOHCR_G3_IO2_Pos (9U)
15509#define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
15510#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
15511#define TSC_IOHCR_G3_IO3_Pos (10U)
15512#define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
15513#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
15514#define TSC_IOHCR_G3_IO4_Pos (11U)
15515#define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
15516#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
15517#define TSC_IOHCR_G4_IO1_Pos (12U)
15518#define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
15519#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
15520#define TSC_IOHCR_G4_IO2_Pos (13U)
15521#define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
15522#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
15523#define TSC_IOHCR_G4_IO3_Pos (14U)
15524#define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
15525#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
15526#define TSC_IOHCR_G4_IO4_Pos (15U)
15527#define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
15528#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
15529#define TSC_IOHCR_G5_IO1_Pos (16U)
15530#define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
15531#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
15532#define TSC_IOHCR_G5_IO2_Pos (17U)
15533#define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
15534#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
15535#define TSC_IOHCR_G5_IO3_Pos (18U)
15536#define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
15537#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
15538#define TSC_IOHCR_G5_IO4_Pos (19U)
15539#define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
15540#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
15541#define TSC_IOHCR_G6_IO1_Pos (20U)
15542#define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
15543#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
15544#define TSC_IOHCR_G6_IO2_Pos (21U)
15545#define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
15546#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
15547#define TSC_IOHCR_G6_IO3_Pos (22U)
15548#define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
15549#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
15550#define TSC_IOHCR_G6_IO4_Pos (23U)
15551#define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
15552#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
15553#define TSC_IOHCR_G7_IO1_Pos (24U)
15554#define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
15555#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
15556#define TSC_IOHCR_G7_IO2_Pos (25U)
15557#define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
15558#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
15559#define TSC_IOHCR_G7_IO3_Pos (26U)
15560#define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
15561#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
15562#define TSC_IOHCR_G7_IO4_Pos (27U)
15563#define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
15564#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
15565#define TSC_IOHCR_G8_IO1_Pos (28U)
15566#define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
15567#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
15568#define TSC_IOHCR_G8_IO2_Pos (29U)
15569#define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
15570#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
15571#define TSC_IOHCR_G8_IO3_Pos (30U)
15572#define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
15573#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
15574#define TSC_IOHCR_G8_IO4_Pos (31U)
15575#define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
15576#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
15577
15578/******************* Bit definition for TSC_IOASCR register *****************/
15579#define TSC_IOASCR_G1_IO1_Pos (0U)
15580#define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
15581#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
15582#define TSC_IOASCR_G1_IO2_Pos (1U)
15583#define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
15584#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
15585#define TSC_IOASCR_G1_IO3_Pos (2U)
15586#define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
15587#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
15588#define TSC_IOASCR_G1_IO4_Pos (3U)
15589#define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
15590#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
15591#define TSC_IOASCR_G2_IO1_Pos (4U)
15592#define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
15593#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
15594#define TSC_IOASCR_G2_IO2_Pos (5U)
15595#define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
15596#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
15597#define TSC_IOASCR_G2_IO3_Pos (6U)
15598#define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
15599#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
15600#define TSC_IOASCR_G2_IO4_Pos (7U)
15601#define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
15602#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
15603#define TSC_IOASCR_G3_IO1_Pos (8U)
15604#define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
15605#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
15606#define TSC_IOASCR_G3_IO2_Pos (9U)
15607#define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
15608#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
15609#define TSC_IOASCR_G3_IO3_Pos (10U)
15610#define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
15611#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
15612#define TSC_IOASCR_G3_IO4_Pos (11U)
15613#define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
15614#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
15615#define TSC_IOASCR_G4_IO1_Pos (12U)
15616#define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
15617#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
15618#define TSC_IOASCR_G4_IO2_Pos (13U)
15619#define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
15620#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
15621#define TSC_IOASCR_G4_IO3_Pos (14U)
15622#define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
15623#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
15624#define TSC_IOASCR_G4_IO4_Pos (15U)
15625#define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
15626#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
15627#define TSC_IOASCR_G5_IO1_Pos (16U)
15628#define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
15629#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
15630#define TSC_IOASCR_G5_IO2_Pos (17U)
15631#define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
15632#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
15633#define TSC_IOASCR_G5_IO3_Pos (18U)
15634#define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
15635#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
15636#define TSC_IOASCR_G5_IO4_Pos (19U)
15637#define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
15638#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
15639#define TSC_IOASCR_G6_IO1_Pos (20U)
15640#define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
15641#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
15642#define TSC_IOASCR_G6_IO2_Pos (21U)
15643#define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
15644#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
15645#define TSC_IOASCR_G6_IO3_Pos (22U)
15646#define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
15647#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
15648#define TSC_IOASCR_G6_IO4_Pos (23U)
15649#define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
15650#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
15651#define TSC_IOASCR_G7_IO1_Pos (24U)
15652#define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
15653#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
15654#define TSC_IOASCR_G7_IO2_Pos (25U)
15655#define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
15656#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
15657#define TSC_IOASCR_G7_IO3_Pos (26U)
15658#define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
15659#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
15660#define TSC_IOASCR_G7_IO4_Pos (27U)
15661#define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
15662#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
15663#define TSC_IOASCR_G8_IO1_Pos (28U)
15664#define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
15665#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
15666#define TSC_IOASCR_G8_IO2_Pos (29U)
15667#define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
15668#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
15669#define TSC_IOASCR_G8_IO3_Pos (30U)
15670#define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
15671#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
15672#define TSC_IOASCR_G8_IO4_Pos (31U)
15673#define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
15674#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
15675
15676/******************* Bit definition for TSC_IOSCR register ******************/
15677#define TSC_IOSCR_G1_IO1_Pos (0U)
15678#define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
15679#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
15680#define TSC_IOSCR_G1_IO2_Pos (1U)
15681#define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
15682#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
15683#define TSC_IOSCR_G1_IO3_Pos (2U)
15684#define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
15685#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
15686#define TSC_IOSCR_G1_IO4_Pos (3U)
15687#define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
15688#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
15689#define TSC_IOSCR_G2_IO1_Pos (4U)
15690#define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
15691#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
15692#define TSC_IOSCR_G2_IO2_Pos (5U)
15693#define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
15694#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
15695#define TSC_IOSCR_G2_IO3_Pos (6U)
15696#define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
15697#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
15698#define TSC_IOSCR_G2_IO4_Pos (7U)
15699#define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
15700#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
15701#define TSC_IOSCR_G3_IO1_Pos (8U)
15702#define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
15703#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
15704#define TSC_IOSCR_G3_IO2_Pos (9U)
15705#define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
15706#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
15707#define TSC_IOSCR_G3_IO3_Pos (10U)
15708#define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
15709#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
15710#define TSC_IOSCR_G3_IO4_Pos (11U)
15711#define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
15712#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
15713#define TSC_IOSCR_G4_IO1_Pos (12U)
15714#define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
15715#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
15716#define TSC_IOSCR_G4_IO2_Pos (13U)
15717#define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
15718#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
15719#define TSC_IOSCR_G4_IO3_Pos (14U)
15720#define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
15721#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
15722#define TSC_IOSCR_G4_IO4_Pos (15U)
15723#define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
15724#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
15725#define TSC_IOSCR_G5_IO1_Pos (16U)
15726#define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
15727#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
15728#define TSC_IOSCR_G5_IO2_Pos (17U)
15729#define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
15730#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
15731#define TSC_IOSCR_G5_IO3_Pos (18U)
15732#define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
15733#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
15734#define TSC_IOSCR_G5_IO4_Pos (19U)
15735#define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
15736#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
15737#define TSC_IOSCR_G6_IO1_Pos (20U)
15738#define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
15739#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
15740#define TSC_IOSCR_G6_IO2_Pos (21U)
15741#define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
15742#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
15743#define TSC_IOSCR_G6_IO3_Pos (22U)
15744#define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
15745#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
15746#define TSC_IOSCR_G6_IO4_Pos (23U)
15747#define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
15748#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
15749#define TSC_IOSCR_G7_IO1_Pos (24U)
15750#define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
15751#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
15752#define TSC_IOSCR_G7_IO2_Pos (25U)
15753#define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
15754#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
15755#define TSC_IOSCR_G7_IO3_Pos (26U)
15756#define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
15757#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
15758#define TSC_IOSCR_G7_IO4_Pos (27U)
15759#define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
15760#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
15761#define TSC_IOSCR_G8_IO1_Pos (28U)
15762#define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
15763#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
15764#define TSC_IOSCR_G8_IO2_Pos (29U)
15765#define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
15766#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
15767#define TSC_IOSCR_G8_IO3_Pos (30U)
15768#define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
15769#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
15770#define TSC_IOSCR_G8_IO4_Pos (31U)
15771#define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
15772#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
15773
15774/******************* Bit definition for TSC_IOCCR register ******************/
15775#define TSC_IOCCR_G1_IO1_Pos (0U)
15776#define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
15777#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
15778#define TSC_IOCCR_G1_IO2_Pos (1U)
15779#define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
15780#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
15781#define TSC_IOCCR_G1_IO3_Pos (2U)
15782#define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
15783#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
15784#define TSC_IOCCR_G1_IO4_Pos (3U)
15785#define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
15786#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
15787#define TSC_IOCCR_G2_IO1_Pos (4U)
15788#define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
15789#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
15790#define TSC_IOCCR_G2_IO2_Pos (5U)
15791#define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
15792#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
15793#define TSC_IOCCR_G2_IO3_Pos (6U)
15794#define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
15795#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
15796#define TSC_IOCCR_G2_IO4_Pos (7U)
15797#define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
15798#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
15799#define TSC_IOCCR_G3_IO1_Pos (8U)
15800#define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
15801#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
15802#define TSC_IOCCR_G3_IO2_Pos (9U)
15803#define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
15804#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
15805#define TSC_IOCCR_G3_IO3_Pos (10U)
15806#define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
15807#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
15808#define TSC_IOCCR_G3_IO4_Pos (11U)
15809#define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
15810#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
15811#define TSC_IOCCR_G4_IO1_Pos (12U)
15812#define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
15813#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
15814#define TSC_IOCCR_G4_IO2_Pos (13U)
15815#define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
15816#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
15817#define TSC_IOCCR_G4_IO3_Pos (14U)
15818#define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
15819#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
15820#define TSC_IOCCR_G4_IO4_Pos (15U)
15821#define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
15822#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
15823#define TSC_IOCCR_G5_IO1_Pos (16U)
15824#define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
15825#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
15826#define TSC_IOCCR_G5_IO2_Pos (17U)
15827#define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
15828#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
15829#define TSC_IOCCR_G5_IO3_Pos (18U)
15830#define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
15831#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
15832#define TSC_IOCCR_G5_IO4_Pos (19U)
15833#define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
15834#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
15835#define TSC_IOCCR_G6_IO1_Pos (20U)
15836#define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
15837#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
15838#define TSC_IOCCR_G6_IO2_Pos (21U)
15839#define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
15840#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
15841#define TSC_IOCCR_G6_IO3_Pos (22U)
15842#define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
15843#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
15844#define TSC_IOCCR_G6_IO4_Pos (23U)
15845#define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
15846#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
15847#define TSC_IOCCR_G7_IO1_Pos (24U)
15848#define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
15849#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
15850#define TSC_IOCCR_G7_IO2_Pos (25U)
15851#define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
15852#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
15853#define TSC_IOCCR_G7_IO3_Pos (26U)
15854#define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
15855#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
15856#define TSC_IOCCR_G7_IO4_Pos (27U)
15857#define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
15858#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
15859#define TSC_IOCCR_G8_IO1_Pos (28U)
15860#define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
15861#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
15862#define TSC_IOCCR_G8_IO2_Pos (29U)
15863#define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
15864#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
15865#define TSC_IOCCR_G8_IO3_Pos (30U)
15866#define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
15867#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
15868#define TSC_IOCCR_G8_IO4_Pos (31U)
15869#define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
15870#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
15871
15872/******************* Bit definition for TSC_IOGCSR register *****************/
15873#define TSC_IOGCSR_G1E_Pos (0U)
15874#define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
15875#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
15876#define TSC_IOGCSR_G2E_Pos (1U)
15877#define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
15878#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
15879#define TSC_IOGCSR_G3E_Pos (2U)
15880#define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
15881#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
15882#define TSC_IOGCSR_G4E_Pos (3U)
15883#define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
15884#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
15885#define TSC_IOGCSR_G5E_Pos (4U)
15886#define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
15887#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
15888#define TSC_IOGCSR_G6E_Pos (5U)
15889#define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
15890#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
15891#define TSC_IOGCSR_G7E_Pos (6U)
15892#define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
15893#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
15894#define TSC_IOGCSR_G8E_Pos (7U)
15895#define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
15896#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
15897#define TSC_IOGCSR_G1S_Pos (16U)
15898#define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
15899#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
15900#define TSC_IOGCSR_G2S_Pos (17U)
15901#define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
15902#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
15903#define TSC_IOGCSR_G3S_Pos (18U)
15904#define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
15905#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
15906#define TSC_IOGCSR_G4S_Pos (19U)
15907#define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
15908#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
15909#define TSC_IOGCSR_G5S_Pos (20U)
15910#define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
15911#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
15912#define TSC_IOGCSR_G6S_Pos (21U)
15913#define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
15914#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
15915#define TSC_IOGCSR_G7S_Pos (22U)
15916#define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
15917#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
15918#define TSC_IOGCSR_G8S_Pos (23U)
15919#define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
15920#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
15921
15922/******************* Bit definition for TSC_IOGXCR register *****************/
15923#define TSC_IOGXCR_CNT_Pos (0U)
15924#define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
15925#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
15926
15927/******************************************************************************/
15928/* */
15929/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
15930/* */
15931/******************************************************************************/
15932/****************** Bit definition for USART_CR1 register *******************/
15933#define USART_CR1_UE_Pos (0U)
15934#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
15935#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
15936#define USART_CR1_UESM_Pos (1U)
15937#define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
15938#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
15939#define USART_CR1_RE_Pos (2U)
15940#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
15941#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
15942#define USART_CR1_TE_Pos (3U)
15943#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
15944#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
15945#define USART_CR1_IDLEIE_Pos (4U)
15946#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
15947#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
15948#define USART_CR1_RXNEIE_Pos (5U)
15949#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
15950#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
15951#define USART_CR1_TCIE_Pos (6U)
15952#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
15953#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
15954#define USART_CR1_TXEIE_Pos (7U)
15955#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
15956#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
15957#define USART_CR1_PEIE_Pos (8U)
15958#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
15959#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
15960#define USART_CR1_PS_Pos (9U)
15961#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
15962#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
15963#define USART_CR1_PCE_Pos (10U)
15964#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
15965#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
15966#define USART_CR1_WAKE_Pos (11U)
15967#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
15968#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
15969#define USART_CR1_M_Pos (12U)
15970#define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
15971#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
15972#define USART_CR1_M0_Pos (12U)
15973#define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
15974#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
15975#define USART_CR1_MME_Pos (13U)
15976#define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
15977#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
15978#define USART_CR1_CMIE_Pos (14U)
15979#define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
15980#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
15981#define USART_CR1_OVER8_Pos (15U)
15982#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
15983#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
15984#define USART_CR1_DEDT_Pos (16U)
15985#define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
15986#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
15987#define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
15988#define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
15989#define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
15990#define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
15991#define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
15992#define USART_CR1_DEAT_Pos (21U)
15993#define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
15994#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
15995#define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
15996#define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
15997#define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
15998#define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
15999#define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
16000#define USART_CR1_RTOIE_Pos (26U)
16001#define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
16002#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
16003#define USART_CR1_EOBIE_Pos (27U)
16004#define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
16005#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
16006#define USART_CR1_M1_Pos (28U)
16007#define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
16008#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
16009
16010/****************** Bit definition for USART_CR2 register *******************/
16011#define USART_CR2_ADDM7_Pos (4U)
16012#define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
16013#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
16014#define USART_CR2_LBDL_Pos (5U)
16015#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
16016#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
16017#define USART_CR2_LBDIE_Pos (6U)
16018#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
16019#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
16020#define USART_CR2_LBCL_Pos (8U)
16021#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
16022#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
16023#define USART_CR2_CPHA_Pos (9U)
16024#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
16025#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
16026#define USART_CR2_CPOL_Pos (10U)
16027#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
16028#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
16029#define USART_CR2_CLKEN_Pos (11U)
16030#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
16031#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
16032#define USART_CR2_STOP_Pos (12U)
16033#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
16034#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
16035#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
16036#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
16037#define USART_CR2_LINEN_Pos (14U)
16038#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
16039#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
16040#define USART_CR2_SWAP_Pos (15U)
16041#define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
16042#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
16043#define USART_CR2_RXINV_Pos (16U)
16044#define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
16045#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
16046#define USART_CR2_TXINV_Pos (17U)
16047#define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
16048#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
16049#define USART_CR2_DATAINV_Pos (18U)
16050#define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
16051#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
16052#define USART_CR2_MSBFIRST_Pos (19U)
16053#define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
16054#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
16055#define USART_CR2_ABREN_Pos (20U)
16056#define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
16057#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
16058#define USART_CR2_ABRMODE_Pos (21U)
16059#define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
16060#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
16061#define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
16062#define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
16063#define USART_CR2_RTOEN_Pos (23U)
16064#define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
16065#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
16066#define USART_CR2_ADD_Pos (24U)
16067#define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
16068#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
16069
16070/****************** Bit definition for USART_CR3 register *******************/
16071#define USART_CR3_EIE_Pos (0U)
16072#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
16073#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
16074#define USART_CR3_IREN_Pos (1U)
16075#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
16076#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
16077#define USART_CR3_IRLP_Pos (2U)
16078#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
16079#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
16080#define USART_CR3_HDSEL_Pos (3U)
16081#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
16082#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
16083#define USART_CR3_NACK_Pos (4U)
16084#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
16085#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
16086#define USART_CR3_SCEN_Pos (5U)
16087#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
16088#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
16089#define USART_CR3_DMAR_Pos (6U)
16090#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
16091#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
16092#define USART_CR3_DMAT_Pos (7U)
16093#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
16094#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
16095#define USART_CR3_RTSE_Pos (8U)
16096#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
16097#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
16098#define USART_CR3_CTSE_Pos (9U)
16099#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
16100#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
16101#define USART_CR3_CTSIE_Pos (10U)
16102#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
16103#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
16104#define USART_CR3_ONEBIT_Pos (11U)
16105#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
16106#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
16107#define USART_CR3_OVRDIS_Pos (12U)
16108#define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
16109#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
16110#define USART_CR3_DDRE_Pos (13U)
16111#define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
16112#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
16113#define USART_CR3_DEM_Pos (14U)
16114#define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
16115#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
16116#define USART_CR3_DEP_Pos (15U)
16117#define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
16118#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
16119#define USART_CR3_SCARCNT_Pos (17U)
16120#define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
16121#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
16122#define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
16123#define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
16124#define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
16125#define USART_CR3_WUS_Pos (20U)
16126#define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
16127#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
16128#define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
16129#define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
16130#define USART_CR3_WUFIE_Pos (22U)
16131#define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
16132#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
16133
16134/****************** Bit definition for USART_BRR register *******************/
16135#define USART_BRR_DIV_FRACTION_Pos (0U)
16136#define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
16137#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
16138#define USART_BRR_DIV_MANTISSA_Pos (4U)
16139#define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
16140#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
16141
16142/****************** Bit definition for USART_GTPR register ******************/
16143#define USART_GTPR_PSC_Pos (0U)
16144#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
16145#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
16146#define USART_GTPR_GT_Pos (8U)
16147#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
16148#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
16149
16150/******************* Bit definition for USART_RTOR register *****************/
16151#define USART_RTOR_RTO_Pos (0U)
16152#define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
16153#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
16154#define USART_RTOR_BLEN_Pos (24U)
16155#define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
16156#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
16157
16158/******************* Bit definition for USART_RQR register ******************/
16159#define USART_RQR_ABRRQ_Pos (0U)
16160#define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
16161#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
16162#define USART_RQR_SBKRQ_Pos (1U)
16163#define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
16164#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
16165#define USART_RQR_MMRQ_Pos (2U)
16166#define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
16167#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
16168#define USART_RQR_RXFRQ_Pos (3U)
16169#define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
16170#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
16171#define USART_RQR_TXFRQ_Pos (4U)
16172#define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
16173#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
16174
16175/******************* Bit definition for USART_ISR register ******************/
16176#define USART_ISR_PE_Pos (0U)
16177#define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
16178#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
16179#define USART_ISR_FE_Pos (1U)
16180#define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
16181#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
16182#define USART_ISR_NE_Pos (2U)
16183#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
16184#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
16185#define USART_ISR_ORE_Pos (3U)
16186#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
16187#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
16188#define USART_ISR_IDLE_Pos (4U)
16189#define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
16190#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
16191#define USART_ISR_RXNE_Pos (5U)
16192#define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
16193#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
16194#define USART_ISR_TC_Pos (6U)
16195#define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
16196#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
16197#define USART_ISR_TXE_Pos (7U)
16198#define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
16199#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
16200#define USART_ISR_LBDF_Pos (8U)
16201#define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
16202#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
16203#define USART_ISR_CTSIF_Pos (9U)
16204#define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
16205#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
16206#define USART_ISR_CTS_Pos (10U)
16207#define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
16208#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
16209#define USART_ISR_RTOF_Pos (11U)
16210#define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
16211#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
16212#define USART_ISR_EOBF_Pos (12U)
16213#define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
16214#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
16215#define USART_ISR_ABRE_Pos (14U)
16216#define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
16217#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
16218#define USART_ISR_ABRF_Pos (15U)
16219#define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
16220#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
16221#define USART_ISR_BUSY_Pos (16U)
16222#define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
16223#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
16224#define USART_ISR_CMF_Pos (17U)
16225#define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
16226#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
16227#define USART_ISR_SBKF_Pos (18U)
16228#define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
16229#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
16230#define USART_ISR_RWU_Pos (19U)
16231#define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
16232#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
16233#define USART_ISR_WUF_Pos (20U)
16234#define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
16235#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
16236#define USART_ISR_TEACK_Pos (21U)
16237#define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
16238#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
16239#define USART_ISR_REACK_Pos (22U)
16240#define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
16241#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
16242
16243/******************* Bit definition for USART_ICR register ******************/
16244#define USART_ICR_PECF_Pos (0U)
16245#define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
16246#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
16247#define USART_ICR_FECF_Pos (1U)
16248#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
16249#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
16250#define USART_ICR_NECF_Pos (2U)
16251#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
16252#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
16253#define USART_ICR_ORECF_Pos (3U)
16254#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
16255#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
16256#define USART_ICR_IDLECF_Pos (4U)
16257#define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
16258#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
16259#define USART_ICR_TCCF_Pos (6U)
16260#define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
16261#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
16262#define USART_ICR_LBDCF_Pos (8U)
16263#define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
16264#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
16265#define USART_ICR_CTSCF_Pos (9U)
16266#define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
16267#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
16268#define USART_ICR_RTOCF_Pos (11U)
16269#define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
16270#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
16271#define USART_ICR_EOBCF_Pos (12U)
16272#define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
16273#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
16274#define USART_ICR_CMCF_Pos (17U)
16275#define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
16276#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
16277#define USART_ICR_WUCF_Pos (20U)
16278#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
16279#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
16280
16281/* Legacy defines */
16282#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
16283#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
16284#define USART_ICR_NCF USART_ICR_NECF
16285
16286/******************* Bit definition for USART_RDR register ******************/
16287#define USART_RDR_RDR_Pos (0U)
16288#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
16289#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
16290
16291/******************* Bit definition for USART_TDR register ******************/
16292#define USART_TDR_TDR_Pos (0U)
16293#define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
16294#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
16295
16296/******************************************************************************/
16297/* */
16298/* Single Wire Protocol Master Interface (SWPMI) */
16299/* */
16300/******************************************************************************/
16301
16302/******************* Bit definition for SWPMI_CR register ********************/
16303#define SWPMI_CR_RXDMA_Pos (0U)
16304#define SWPMI_CR_RXDMA_Msk (0x1U << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
16305#define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
16306#define SWPMI_CR_TXDMA_Pos (1U)
16307#define SWPMI_CR_TXDMA_Msk (0x1U << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
16308#define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
16309#define SWPMI_CR_RXMODE_Pos (2U)
16310#define SWPMI_CR_RXMODE_Msk (0x1U << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
16311#define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
16312#define SWPMI_CR_TXMODE_Pos (3U)
16313#define SWPMI_CR_TXMODE_Msk (0x1U << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
16314#define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
16315#define SWPMI_CR_LPBK_Pos (4U)
16316#define SWPMI_CR_LPBK_Msk (0x1U << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
16317#define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
16318#define SWPMI_CR_SWPACT_Pos (5U)
16319#define SWPMI_CR_SWPACT_Msk (0x1U << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
16320#define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
16321#define SWPMI_CR_DEACT_Pos (10U)
16322#define SWPMI_CR_DEACT_Msk (0x1U << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
16323#define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
16324
16325/******************* Bit definition for SWPMI_BRR register ********************/
16326#define SWPMI_BRR_BR_Pos (0U)
16327#define SWPMI_BRR_BR_Msk (0x3FU << SWPMI_BRR_BR_Pos) /*!< 0x0000003F */
16328#define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[5:0] bits (Bitrate prescaler) */
16329
16330/******************* Bit definition for SWPMI_ISR register ********************/
16331#define SWPMI_ISR_RXBFF_Pos (0U)
16332#define SWPMI_ISR_RXBFF_Msk (0x1U << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
16333#define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
16334#define SWPMI_ISR_TXBEF_Pos (1U)
16335#define SWPMI_ISR_TXBEF_Msk (0x1U << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
16336#define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
16337#define SWPMI_ISR_RXBERF_Pos (2U)
16338#define SWPMI_ISR_RXBERF_Msk (0x1U << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
16339#define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
16340#define SWPMI_ISR_RXOVRF_Pos (3U)
16341#define SWPMI_ISR_RXOVRF_Msk (0x1U << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
16342#define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
16343#define SWPMI_ISR_TXUNRF_Pos (4U)
16344#define SWPMI_ISR_TXUNRF_Msk (0x1U << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
16345#define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
16346#define SWPMI_ISR_RXNE_Pos (5U)
16347#define SWPMI_ISR_RXNE_Msk (0x1U << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
16348#define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
16349#define SWPMI_ISR_TXE_Pos (6U)
16350#define SWPMI_ISR_TXE_Msk (0x1U << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
16351#define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
16352#define SWPMI_ISR_TCF_Pos (7U)
16353#define SWPMI_ISR_TCF_Msk (0x1U << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
16354#define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
16355#define SWPMI_ISR_SRF_Pos (8U)
16356#define SWPMI_ISR_SRF_Msk (0x1U << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
16357#define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
16358#define SWPMI_ISR_SUSP_Pos (9U)
16359#define SWPMI_ISR_SUSP_Msk (0x1U << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
16360#define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
16361#define SWPMI_ISR_DEACTF_Pos (10U)
16362#define SWPMI_ISR_DEACTF_Msk (0x1U << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
16363#define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
16364
16365/******************* Bit definition for SWPMI_ICR register ********************/
16366#define SWPMI_ICR_CRXBFF_Pos (0U)
16367#define SWPMI_ICR_CRXBFF_Msk (0x1U << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
16368#define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
16369#define SWPMI_ICR_CTXBEF_Pos (1U)
16370#define SWPMI_ICR_CTXBEF_Msk (0x1U << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
16371#define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
16372#define SWPMI_ICR_CRXBERF_Pos (2U)
16373#define SWPMI_ICR_CRXBERF_Msk (0x1U << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
16374#define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
16375#define SWPMI_ICR_CRXOVRF_Pos (3U)
16376#define SWPMI_ICR_CRXOVRF_Msk (0x1U << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
16377#define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
16378#define SWPMI_ICR_CTXUNRF_Pos (4U)
16379#define SWPMI_ICR_CTXUNRF_Msk (0x1U << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
16380#define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
16381#define SWPMI_ICR_CTCF_Pos (7U)
16382#define SWPMI_ICR_CTCF_Msk (0x1U << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
16383#define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
16384#define SWPMI_ICR_CSRF_Pos (8U)
16385#define SWPMI_ICR_CSRF_Msk (0x1U << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
16386#define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
16387
16388/******************* Bit definition for SWPMI_IER register ********************/
16389#define SWPMI_IER_SRIE_Pos (8U)
16390#define SWPMI_IER_SRIE_Msk (0x1U << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
16391#define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
16392#define SWPMI_IER_TCIE_Pos (7U)
16393#define SWPMI_IER_TCIE_Msk (0x1U << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
16394#define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
16395#define SWPMI_IER_TIE_Pos (6U)
16396#define SWPMI_IER_TIE_Msk (0x1U << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
16397#define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
16398#define SWPMI_IER_RIE_Pos (5U)
16399#define SWPMI_IER_RIE_Msk (0x1U << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
16400#define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
16401#define SWPMI_IER_TXUNRIE_Pos (4U)
16402#define SWPMI_IER_TXUNRIE_Msk (0x1U << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
16403#define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
16404#define SWPMI_IER_RXOVRIE_Pos (3U)
16405#define SWPMI_IER_RXOVRIE_Msk (0x1U << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
16406#define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
16407#define SWPMI_IER_RXBERIE_Pos (2U)
16408#define SWPMI_IER_RXBERIE_Msk (0x1U << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
16409#define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
16410#define SWPMI_IER_TXBEIE_Pos (1U)
16411#define SWPMI_IER_TXBEIE_Msk (0x1U << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
16412#define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
16413#define SWPMI_IER_RXBFIE_Pos (0U)
16414#define SWPMI_IER_RXBFIE_Msk (0x1U << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
16415#define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
16416
16417/******************* Bit definition for SWPMI_RFL register ********************/
16418#define SWPMI_RFL_RFL_Pos (0U)
16419#define SWPMI_RFL_RFL_Msk (0x1FU << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
16420#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
16421#define SWPMI_RFL_RFL_0_1_Pos (0U)
16422#define SWPMI_RFL_RFL_0_1_Msk (0x3U << SWPMI_RFL_RFL_0_1_Pos) /*!< 0x00000003 */
16423#define SWPMI_RFL_RFL_0_1 SWPMI_RFL_RFL_0_1_Msk /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
16424
16425/******************* Bit definition for SWPMI_TDR register ********************/
16426#define SWPMI_TDR_TD_Pos (0U)
16427#define SWPMI_TDR_TD_Msk (0xFFFFFFFFU << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
16428#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
16429
16430/******************* Bit definition for SWPMI_RDR register ********************/
16431#define SWPMI_RDR_RD_Pos (0U)
16432#define SWPMI_RDR_RD_Msk (0xFFFFFFFFU << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
16433#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
16434
16435/******************* Bit definition for SWPMI_OR register ********************/
16436#define SWPMI_OR_TBYP_Pos (0U)
16437#define SWPMI_OR_TBYP_Msk (0x1U << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
16438#define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
16439#define SWPMI_OR_CLASS_Pos (1U)
16440#define SWPMI_OR_CLASS_Msk (0x1U << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
16441#define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP Voltage Class selection */
16442
16443/******************************************************************************/
16444/* */
16445/* VREFBUF */
16446/* */
16447/******************************************************************************/
16448/******************* Bit definition for VREFBUF_CSR register ****************/
16449#define VREFBUF_CSR_ENVR_Pos (0U)
16450#define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
16451#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
16452#define VREFBUF_CSR_HIZ_Pos (1U)
16453#define VREFBUF_CSR_HIZ_Msk (0x1U << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
16454#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
16455#define VREFBUF_CSR_VRS_Pos (2U)
16456#define VREFBUF_CSR_VRS_Msk (0x1U << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */
16457#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
16458#define VREFBUF_CSR_VRR_Pos (3U)
16459#define VREFBUF_CSR_VRR_Msk (0x1U << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
16460#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
16461
16462/******************* Bit definition for VREFBUF_CCR register ******************/
16463#define VREFBUF_CCR_TRIM_Pos (0U)
16464#define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
16465#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
16466
16467/******************************************************************************/
16468/* */
16469/* Window WATCHDOG */
16470/* */
16471/******************************************************************************/
16472/******************* Bit definition for WWDG_CR register ********************/
16473#define WWDG_CR_T_Pos (0U)
16474#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
16475#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
16476#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
16477#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
16478#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
16479#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
16480#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
16481#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
16482#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
16483
16484#define WWDG_CR_WDGA_Pos (7U)
16485#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
16486#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
16487
16488/******************* Bit definition for WWDG_CFR register *******************/
16489#define WWDG_CFR_W_Pos (0U)
16490#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
16491#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
16492#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
16493#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
16494#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
16495#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
16496#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
16497#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
16498#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
16499
16500#define WWDG_CFR_WDGTB_Pos (7U)
16501#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
16502#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
16503#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
16504#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
16505
16506#define WWDG_CFR_EWI_Pos (9U)
16507#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
16508#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
16509
16510/******************* Bit definition for WWDG_SR register ********************/
16511#define WWDG_SR_EWIF_Pos (0U)
16512#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
16513#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
16514
16515
16516/******************************************************************************/
16517/* */
16518/* Debug MCU */
16519/* */
16520/******************************************************************************/
16521/******************** Bit definition for DBGMCU_IDCODE register *************/
16522#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
16523#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
16524#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
16525#define DBGMCU_IDCODE_REV_ID_Pos (16U)
16526#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
16527#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
16528
16529/******************** Bit definition for DBGMCU_CR register *****************/
16530#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
16531#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
16532#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
16533#define DBGMCU_CR_DBG_STOP_Pos (1U)
16534#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
16535#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
16536#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
16537#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
16538#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
16539#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
16540#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
16541#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
16542
16543#define DBGMCU_CR_TRACE_MODE_Pos (6U)
16544#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
16545#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
16546#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
16547#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
16548
16549/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
16550#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
16551#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
16552#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
16553#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
16554#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
16555#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
16556#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
16557#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
16558#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
16559#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
16560#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
16561#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
16562#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
16563#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
16564#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
16565#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
16566#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
16567#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
16568#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
16569#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
16570#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
16571#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
16572#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
16573#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
16574#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
16575#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
16576#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
16577#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
16578#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
16579#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
16580#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
16581#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
16582#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
16583#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
16584#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
16585#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
16586#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
16587#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
16588#define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
16589#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
16590#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
16591#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
16592
16593/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
16594#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
16595#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
16596#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
16597
16598/******************** Bit definition for DBGMCU_APB2FZ register ************/
16599#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
16600#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
16601#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
16602#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
16603#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */
16604#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
16605#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
16606#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
16607#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
16608#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
16609#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
16610#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
16611#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
16612#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
16613#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
16614
16615/******************************************************************************/
16616/* */
16617/* USB_OTG */
16618/* */
16619/******************************************************************************/
16620/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
16621#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
16622#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
16623#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
16624#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
16625#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
16626#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
16627#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
16628#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
16629#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
16630#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
16631#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
16632#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
16633#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
16634#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
16635#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
16636#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
16637#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
16638#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
16639#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
16640#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
16641#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
16642#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
16643#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
16644#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
16645#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
16646#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
16647#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/
16648
16649/******************** Bit definition for USB_OTG_HCFG register ********************/
16650
16651#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
16652#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
16653#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
16654#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
16655#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
16656#define USB_OTG_HCFG_FSLSS_Pos (2U)
16657#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
16658#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
16659
16660/******************** Bit definition for USB_OTG_DCFG register ********************/
16661
16662#define USB_OTG_DCFG_DSPD_Pos (0U)
16663#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
16664#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
16665#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
16666#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
16667#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
16668#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
16669#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
16670#define USB_OTG_DCFG_DAD_Pos (4U)
16671#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
16672#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
16673#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
16674#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
16675#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
16676#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
16677#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
16678#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
16679#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
16680#define USB_OTG_DCFG_PFIVL_Pos (11U)
16681#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
16682#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
16683#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
16684#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
16685#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
16686#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
16687#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
16688#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
16689#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
16690
16691/******************** Bit definition for USB_OTG_PCGCR register ********************/
16692#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
16693#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
16694#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
16695#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
16696#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
16697#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
16698#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
16699#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
16700#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
16701
16702/******************** Bit definition for USB_OTG_GOTGINT register ********************/
16703#define USB_OTG_GOTGINT_SEDET_Pos (2U)
16704#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
16705#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
16706#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
16707#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
16708#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
16709#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
16710#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
16711#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
16712#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
16713#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
16714#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
16715#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
16716#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
16717#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
16718#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
16719#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
16720#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
16721
16722/******************** Bit definition for USB_OTG_DCTL register ********************/
16723#define USB_OTG_DCTL_RWUSIG_Pos (0U)
16724#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
16725#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
16726#define USB_OTG_DCTL_SDIS_Pos (1U)
16727#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
16728#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
16729#define USB_OTG_DCTL_GINSTS_Pos (2U)
16730#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
16731#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
16732#define USB_OTG_DCTL_GONSTS_Pos (3U)
16733#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
16734#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
16735
16736#define USB_OTG_DCTL_TCTL_Pos (4U)
16737#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
16738#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
16739#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
16740#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
16741#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
16742#define USB_OTG_DCTL_SGINAK_Pos (7U)
16743#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
16744#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
16745#define USB_OTG_DCTL_CGINAK_Pos (8U)
16746#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
16747#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
16748#define USB_OTG_DCTL_SGONAK_Pos (9U)
16749#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
16750#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
16751#define USB_OTG_DCTL_CGONAK_Pos (10U)
16752#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
16753#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
16754#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
16755#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
16756#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
16757
16758/******************** Bit definition for USB_OTG_HFIR register ********************/
16759#define USB_OTG_HFIR_FRIVL_Pos (0U)
16760#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
16761#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
16762
16763/******************** Bit definition for USB_OTG_HFNUM register ********************/
16764#define USB_OTG_HFNUM_FRNUM_Pos (0U)
16765#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
16766#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
16767#define USB_OTG_HFNUM_FTREM_Pos (16U)
16768#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
16769#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
16770
16771/******************** Bit definition for USB_OTG_DSTS register ********************/
16772#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
16773#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
16774#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
16775
16776#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
16777#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
16778#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
16779#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
16780#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
16781#define USB_OTG_DSTS_EERR_Pos (3U)
16782#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
16783#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
16784#define USB_OTG_DSTS_FNSOF_Pos (8U)
16785#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
16786#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
16787
16788/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
16789#define USB_OTG_GAHBCFG_GINT_Pos (0U)
16790#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
16791#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
16792#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
16793#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
16794#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
16795#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
16796#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
16797#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
16798#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
16799#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
16800#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
16801#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
16802#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
16803#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
16804#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
16805#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
16806#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
16807#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
16808
16809/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
16810
16811#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
16812#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
16813#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
16814#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
16815#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
16816#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
16817#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
16818#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
16819#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
16820#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
16821#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
16822#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
16823#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
16824#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
16825#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
16826#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
16827#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
16828#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
16829#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
16830#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
16831#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
16832#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
16833#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
16834#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
16835#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
16836#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
16837#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
16838#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
16839#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
16840#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
16841#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
16842#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
16843#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
16844#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
16845#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
16846#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
16847#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
16848#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
16849#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
16850#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
16851#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
16852#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
16853#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
16854#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
16855#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
16856#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
16857#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
16858#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
16859#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
16860#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
16861#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
16862#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
16863#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
16864#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
16865#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
16866#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
16867#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
16868#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
16869#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
16870#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
16871#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
16872
16873/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
16874#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
16875#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
16876#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
16877#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
16878#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
16879#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
16880#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
16881#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
16882#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
16883#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
16884#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
16885#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
16886#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
16887#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
16888#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
16889#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
16890#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
16891#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
16892#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
16893#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
16894#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
16895#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
16896#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
16897#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
16898#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
16899#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
16900#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
16901#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
16902#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
16903
16904/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
16905#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
16906#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
16907#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
16908#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
16909#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
16910#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
16911#define USB_OTG_DIEPMSK_TOM_Pos (3U)
16912#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
16913#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
16914#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
16915#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
16916#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
16917#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
16918#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
16919#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
16920#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
16921#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
16922#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
16923#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
16924#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
16925#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
16926#define USB_OTG_DIEPMSK_BIM_Pos (9U)
16927#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
16928#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
16929
16930/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
16931#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
16932#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
16933#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
16934#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
16935#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
16936#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
16937#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
16938#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
16939#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
16940#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
16941#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
16942#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
16943#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
16944#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
16945
16946#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
16947#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
16948#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
16949#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
16950#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
16951#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
16952#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
16953#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
16954#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
16955#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
16956#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
16957
16958/******************** Bit definition for USB_OTG_HAINT register ********************/
16959#define USB_OTG_HAINT_HAINT_Pos (0U)
16960#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
16961#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
16962
16963/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
16964#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
16965#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
16966#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
16967#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
16968#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
16969#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
16970#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
16971#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
16972#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
16973#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
16974#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
16975#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
16976#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
16977#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
16978#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
16979#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
16980#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
16981#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
16982#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
16983#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
16984#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
16985
16986/******************** Bit definition for USB_OTG_GINTSTS register ********************/
16987#define USB_OTG_GINTSTS_CMOD_Pos (0U)
16988#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
16989#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
16990#define USB_OTG_GINTSTS_MMIS_Pos (1U)
16991#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
16992#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
16993#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
16994#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
16995#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
16996#define USB_OTG_GINTSTS_SOF_Pos (3U)
16997#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
16998#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
16999#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
17000#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
17001#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
17002#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
17003#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
17004#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
17005#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
17006#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
17007#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
17008#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
17009#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
17010#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
17011#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
17012#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
17013#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
17014#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
17015#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
17016#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
17017#define USB_OTG_GINTSTS_USBRST_Pos (12U)
17018#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
17019#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
17020#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
17021#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
17022#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
17023#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
17024#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
17025#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
17026#define USB_OTG_GINTSTS_EOPF_Pos (15U)
17027#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
17028#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
17029#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
17030#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
17031#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
17032#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
17033#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
17034#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
17035#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
17036#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
17037#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
17038#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
17039#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
17040#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
17041#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
17042#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
17043#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
17044#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
17045#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
17046#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
17047#define USB_OTG_GINTSTS_HCINT_Pos (25U)
17048#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
17049#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
17050#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
17051#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
17052#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
17053#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
17054#define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
17055#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
17056#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
17057#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
17058#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
17059#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
17060#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
17061#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
17062#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
17063#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
17064#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
17065#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
17066#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
17067#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
17068
17069/******************** Bit definition for USB_OTG_GINTMSK register ********************/
17070
17071#define USB_OTG_GINTMSK_MMISM_Pos (1U)
17072#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
17073#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
17074#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
17075#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
17076#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
17077#define USB_OTG_GINTMSK_SOFM_Pos (3U)
17078#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
17079#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
17080#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
17081#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
17082#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
17083#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
17084#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
17085#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
17086#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
17087#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
17088#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
17089#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
17090#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
17091#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
17092#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
17093#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
17094#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
17095#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
17096#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
17097#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
17098#define USB_OTG_GINTMSK_USBRST_Pos (12U)
17099#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
17100#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
17101#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
17102#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
17103#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
17104#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
17105#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
17106#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
17107#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
17108#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
17109#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
17110#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
17111#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
17112#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
17113#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
17114#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
17115#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
17116#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
17117#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
17118#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
17119#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
17120#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
17121#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
17122#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
17123#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
17124#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
17125#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
17126#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
17127#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
17128#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
17129#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
17130#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
17131#define USB_OTG_GINTMSK_HCIM_Pos (25U)
17132#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
17133#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
17134#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
17135#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
17136#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
17137#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
17138#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
17139#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
17140#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
17141#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
17142#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
17143#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
17144#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
17145#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
17146#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
17147#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
17148#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
17149#define USB_OTG_GINTMSK_WUIM_Pos (31U)
17150#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
17151#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
17152
17153/******************** Bit definition for USB_OTG_DAINT register ********************/
17154#define USB_OTG_DAINT_IEPINT_Pos (0U)
17155#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
17156#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
17157#define USB_OTG_DAINT_OEPINT_Pos (16U)
17158#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
17159#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
17160
17161/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
17162#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
17163#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
17164#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
17165
17166/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
17167#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
17168#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
17169#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
17170#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
17171#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
17172#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
17173#define USB_OTG_GRXSTSP_DPID_Pos (15U)
17174#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
17175#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
17176#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
17177#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
17178#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
17179
17180/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
17181#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
17182#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
17183#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
17184#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
17185#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
17186#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
17187
17188/******************** Bit definition for OTG register ********************/
17189
17190#define USB_OTG_CHNUM_Pos (0U)
17191#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
17192#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
17193#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
17194#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
17195#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
17196#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
17197#define USB_OTG_BCNT_Pos (4U)
17198#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
17199#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
17200#define USB_OTG_DPID_Pos (15U)
17201#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
17202#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
17203#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
17204#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
17205#define USB_OTG_PKTSTS_Pos (17U)
17206#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
17207#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
17208#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
17209#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
17210#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
17211#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
17212#define USB_OTG_EPNUM_Pos (0U)
17213#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
17214#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
17215#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
17216#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
17217#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
17218#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
17219#define USB_OTG_FRMNUM_Pos (21U)
17220#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
17221#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
17222#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
17223#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
17224#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
17225#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
17226
17227/******************** Bit definition for OTG register ********************/
17228
17229#define USB_OTG_CHNUM_Pos (0U)
17230#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
17231#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
17232#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
17233#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
17234#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
17235#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
17236#define USB_OTG_BCNT_Pos (4U)
17237#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
17238#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
17239#define USB_OTG_DPID_Pos (15U)
17240#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
17241#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
17242#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
17243#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
17244#define USB_OTG_PKTSTS_Pos (17U)
17245#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
17246#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
17247#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
17248#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
17249#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
17250#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
17251#define USB_OTG_EPNUM_Pos (0U)
17252#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
17253#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
17254#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
17255#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
17256#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
17257#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
17258#define USB_OTG_FRMNUM_Pos (21U)
17259#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
17260#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
17261#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
17262#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
17263#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
17264#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
17265
17266/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
17267#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
17268#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
17269#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
17270
17271/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
17272#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
17273#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
17274#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
17275
17276/******************** Bit definition for OTG register ********************/
17277#define USB_OTG_NPTXFSA_Pos (0U)
17278#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
17279#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
17280#define USB_OTG_NPTXFD_Pos (16U)
17281#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
17282#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
17283#define USB_OTG_TX0FSA_Pos (0U)
17284#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
17285#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
17286#define USB_OTG_TX0FD_Pos (16U)
17287#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
17288#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
17289
17290/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
17291#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
17292#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
17293#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
17294
17295/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
17296#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
17297#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
17298#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
17299
17300#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
17301#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
17302#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
17303#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
17304#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
17305#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
17306#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
17307#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
17308#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
17309#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
17310#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
17311
17312#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
17313#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
17314#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
17315#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
17316#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
17317#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
17318#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
17319#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
17320#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
17321#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
17322
17323/******************** Bit definition for USB_OTG_DTHRCTL register ***************/
17324#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
17325#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
17326#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
17327#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
17328#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
17329#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
17330
17331#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
17332#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
17333#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
17334#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
17335#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
17336#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
17337#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
17338#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
17339#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
17340#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
17341#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
17342#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
17343#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
17344#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
17345#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
17346
17347#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
17348#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
17349#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
17350#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
17351#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
17352#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
17353#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
17354#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
17355#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
17356#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
17357#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
17358#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
17359#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
17360#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
17361#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
17362
17363/******************** Bit definition for USB_OTG_DIEPEMPMSK register ***************/
17364#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
17365#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
17366#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
17367
17368/******************** Bit definition for USB_OTG_DEACHINT register ********************/
17369#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
17370#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
17371#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
17372#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
17373#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
17374#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
17375
17376/******************** Bit definition for USB_OTG_GCCFG register ********************/
17377#define USB_OTG_GCCFG_DCDET_Pos (0U)
17378#define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
17379#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
17380#define USB_OTG_GCCFG_PDET_Pos (1U)
17381#define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
17382#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
17383#define USB_OTG_GCCFG_SDET_Pos (2U)
17384#define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
17385#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
17386#define USB_OTG_GCCFG_PS2DET_Pos (3U)
17387#define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
17388#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
17389#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
17390#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
17391#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
17392#define USB_OTG_GCCFG_BCDEN_Pos (17U)
17393#define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
17394#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
17395#define USB_OTG_GCCFG_DCDEN_Pos (18U)
17396#define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
17397#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
17398#define USB_OTG_GCCFG_PDEN_Pos (19U)
17399#define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
17400#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
17401#define USB_OTG_GCCFG_SDEN_Pos (20U)
17402#define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
17403#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
17404#define USB_OTG_GCCFG_VBDEN_Pos (21U)
17405#define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
17406#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
17407
17408/******************** Bit definition for USB_OTG_GPWRDN) register ********************/
17409#define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U)
17410#define USB_OTG_GPWRDN_DISABLEVBUS_Msk (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */
17411#define USB_OTG_GPWRDN_DISABLEVBUS USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */
17412
17413/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
17414#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
17415#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
17416#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
17417#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
17418#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
17419#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
17420
17421/******************** Bit definition for USB_OTG_CID register ********************/
17422#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
17423#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
17424#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
17425
17426
17427/******************** Bit definition for USB_OTG_GHWCFG3 register ********************/
17428#define USB_OTG_GHWCFG3_LPMMode_Pos (14U)
17429#define USB_OTG_GHWCFG3_LPMMode_Msk (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */
17430#define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */
17431
17432/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
17433#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
17434#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
17435#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */
17436#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
17437#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
17438#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */
17439#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
17440#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
17441#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */
17442#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
17443#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
17444#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */
17445#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
17446#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
17447#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */
17448#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U)
17449#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */
17450#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */
17451#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
17452#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
17453#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */
17454#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
17455#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
17456#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */
17457#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
17458#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
17459#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */
17460#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
17461#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
17462#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */
17463#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
17464#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
17465#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */
17466#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
17467#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
17468#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */
17469#define USB_OTG_GLPMCFG_BESL_Pos (2U)
17470#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
17471#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */
17472#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
17473#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
17474#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/
17475#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
17476#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
17477#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */
17478
17479
17480/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
17481#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
17482#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
17483#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
17484#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
17485#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
17486#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
17487#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
17488#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
17489#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
17490#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
17491#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
17492#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
17493#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
17494#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
17495#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
17496#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
17497#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
17498#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
17499#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
17500#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
17501#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
17502#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
17503#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
17504#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
17505#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
17506#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
17507#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
17508
17509/******************** Bit definition for USB_OTG_HPRT register ********************/
17510#define USB_OTG_HPRT_PCSTS_Pos (0U)
17511#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
17512#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
17513#define USB_OTG_HPRT_PCDET_Pos (1U)
17514#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
17515#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
17516#define USB_OTG_HPRT_PENA_Pos (2U)
17517#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
17518#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
17519#define USB_OTG_HPRT_PENCHNG_Pos (3U)
17520#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
17521#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
17522#define USB_OTG_HPRT_POCA_Pos (4U)
17523#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
17524#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
17525#define USB_OTG_HPRT_POCCHNG_Pos (5U)
17526#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
17527#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
17528#define USB_OTG_HPRT_PRES_Pos (6U)
17529#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
17530#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
17531#define USB_OTG_HPRT_PSUSP_Pos (7U)
17532#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
17533#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
17534#define USB_OTG_HPRT_PRST_Pos (8U)
17535#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
17536#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
17537
17538#define USB_OTG_HPRT_PLSTS_Pos (10U)
17539#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
17540#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
17541#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
17542#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
17543#define USB_OTG_HPRT_PPWR_Pos (12U)
17544#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
17545#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
17546
17547#define USB_OTG_HPRT_PTCTL_Pos (13U)
17548#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
17549#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
17550#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
17551#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
17552#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
17553#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
17554
17555#define USB_OTG_HPRT_PSPD_Pos (17U)
17556#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
17557#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
17558#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
17559#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
17560
17561/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
17562#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
17563#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
17564#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
17565#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
17566#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
17567#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
17568#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
17569#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
17570#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
17571#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
17572#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
17573#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
17574#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
17575#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
17576#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
17577#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
17578#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
17579#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
17580#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
17581#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
17582#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
17583#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
17584#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
17585#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
17586#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
17587#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
17588#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
17589#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
17590#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
17591#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
17592#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
17593#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
17594#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
17595
17596/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
17597#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
17598#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
17599#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
17600#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
17601#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
17602#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
17603
17604/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
17605#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
17606#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
17607#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
17608#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
17609#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
17610#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
17611#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
17612#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
17613#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
17614#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
17615#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
17616#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
17617
17618#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
17619#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
17620#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
17621#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
17622#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
17623#define USB_OTG_DIEPCTL_STALL_Pos (21U)
17624#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
17625#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
17626
17627#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
17628#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
17629#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
17630#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
17631#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
17632#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
17633#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
17634#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
17635#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
17636#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
17637#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
17638#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
17639#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
17640#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
17641#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
17642#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
17643#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
17644#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
17645#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
17646#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
17647#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
17648#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
17649#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
17650#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
17651#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
17652
17653/******************** Bit definition for USB_OTG_HCCHAR register ********************/
17654#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
17655#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
17656#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
17657
17658#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
17659#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
17660#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
17661#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
17662#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
17663#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
17664#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
17665#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
17666#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
17667#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
17668#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
17669#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
17670#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
17671
17672#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
17673#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
17674#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
17675#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
17676#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
17677
17678#define USB_OTG_HCCHAR_MC_Pos (20U)
17679#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
17680#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
17681#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
17682#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
17683
17684#define USB_OTG_HCCHAR_DAD_Pos (22U)
17685#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
17686#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
17687#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
17688#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
17689#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
17690#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
17691#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
17692#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
17693#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
17694#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
17695#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
17696#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
17697#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
17698#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
17699#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
17700#define USB_OTG_HCCHAR_CHENA_Pos (31U)
17701#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
17702#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
17703
17704/******************** Bit definition for USB_OTG_HCSPLT register ********************/
17705
17706#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
17707#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
17708#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
17709#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
17710#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
17711#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
17712#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
17713#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
17714#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
17715#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
17716
17717#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
17718#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
17719#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
17720#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
17721#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
17722#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
17723#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
17724#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
17725#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
17726#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
17727
17728#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
17729#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
17730#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
17731#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
17732#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
17733#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
17734#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
17735#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
17736#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
17737#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
17738#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
17739
17740/******************** Bit definition for USB_OTG_HCINT register ********************/
17741#define USB_OTG_HCINT_XFRC_Pos (0U)
17742#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
17743#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
17744#define USB_OTG_HCINT_CHH_Pos (1U)
17745#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
17746#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
17747#define USB_OTG_HCINT_AHBERR_Pos (2U)
17748#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
17749#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
17750#define USB_OTG_HCINT_STALL_Pos (3U)
17751#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
17752#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
17753#define USB_OTG_HCINT_NAK_Pos (4U)
17754#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
17755#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
17756#define USB_OTG_HCINT_ACK_Pos (5U)
17757#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
17758#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
17759#define USB_OTG_HCINT_NYET_Pos (6U)
17760#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
17761#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
17762#define USB_OTG_HCINT_TXERR_Pos (7U)
17763#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
17764#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
17765#define USB_OTG_HCINT_BBERR_Pos (8U)
17766#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
17767#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
17768#define USB_OTG_HCINT_FRMOR_Pos (9U)
17769#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
17770#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
17771#define USB_OTG_HCINT_DTERR_Pos (10U)
17772#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
17773#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
17774
17775/******************** Bit definition for USB_OTG_DIEPINT register ********************/
17776#define USB_OTG_DIEPINT_XFRC_Pos (0U)
17777#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
17778#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
17779#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
17780#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
17781#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
17782#define USB_OTG_DIEPINT_TOC_Pos (3U)
17783#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
17784#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
17785#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
17786#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
17787#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
17788#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
17789#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
17790#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
17791#define USB_OTG_DIEPINT_TXFE_Pos (7U)
17792#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
17793#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
17794#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
17795#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
17796#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
17797#define USB_OTG_DIEPINT_BNA_Pos (9U)
17798#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
17799#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
17800#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
17801#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
17802#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
17803#define USB_OTG_DIEPINT_BERR_Pos (12U)
17804#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
17805#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
17806#define USB_OTG_DIEPINT_NAK_Pos (13U)
17807#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
17808#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
17809
17810/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
17811#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
17812#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
17813#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
17814#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
17815#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
17816#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
17817#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
17818#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
17819#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
17820#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
17821#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
17822#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
17823#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
17824#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
17825#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
17826#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
17827#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
17828#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
17829#define USB_OTG_HCINTMSK_NYET_Pos (6U)
17830#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
17831#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
17832#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
17833#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
17834#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
17835#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
17836#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
17837#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
17838#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
17839#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
17840#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
17841#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
17842#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
17843#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
17844
17845/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
17846
17847#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
17848#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
17849#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
17850#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
17851#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
17852#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
17853#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
17854#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
17855#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
17856/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
17857#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
17858#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
17859#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
17860#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
17861#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
17862#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
17863#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
17864#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
17865#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
17866#define USB_OTG_HCTSIZ_DPID_Pos (29U)
17867#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
17868#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
17869#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
17870#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
17871
17872/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
17873#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
17874#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
17875#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
17876
17877/******************** Bit definition for USB_OTG_HCDMA register ********************/
17878#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
17879#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
17880#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
17881
17882/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
17883#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
17884#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
17885#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
17886
17887/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
17888#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
17889#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
17890#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
17891#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
17892#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
17893#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
17894
17895/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
17896
17897#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
17898#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
17899#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
17900#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
17901#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
17902#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
17903#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
17904#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
17905#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
17906#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
17907#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
17908#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
17909#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
17910#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
17911#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
17912#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
17913#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
17914#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
17915#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
17916#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
17917#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
17918#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
17919#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
17920#define USB_OTG_DOEPCTL_STALL_Pos (21U)
17921#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
17922#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
17923#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
17924#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
17925#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
17926#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
17927#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
17928#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
17929#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
17930#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
17931#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
17932#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
17933#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
17934#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
17935
17936/******************** Bit definition for USB_OTG_DOEPINT register ********************/
17937#define USB_OTG_DOEPINT_XFRC_Pos (0U)
17938#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
17939#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
17940#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
17941#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
17942#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
17943#define USB_OTG_DOEPINT_STUP_Pos (3U)
17944#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
17945#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
17946#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
17947#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
17948#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
17949#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
17950#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
17951#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
17952#define USB_OTG_DOEPINT_NYET_Pos (14U)
17953#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
17954#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
17955
17956/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
17957
17958#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
17959#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
17960#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
17961#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
17962#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
17963#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
17964
17965#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
17966#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
17967#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
17968#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
17969#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
17970
17971/******************** Bit definition for PCGCCTL register ********************/
17972#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
17973#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
17974#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
17975#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
17976#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
17977#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
17978#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
17979#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
17980#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
17981
17982
17983/**
17984 * @}
17985 */
17986
17987/**
17988 * @}
17989 */
17990
17991/** @addtogroup Exported_macros
17992 * @{
17993 */
17994
17995/******************************* ADC Instances ********************************/
17996#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
17997 ((INSTANCE) == ADC2) || \
17998 ((INSTANCE) == ADC3))
17999
18000#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
18001
18002#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
18003
18004/******************************* AES Instances ********************************/
18005#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
18006
18007/******************************** CAN Instances ******************************/
18008#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
18009
18010/******************************** COMP Instances ******************************/
18011#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
18012 ((INSTANCE) == COMP2))
18013
18014#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
18015
18016/******************** COMP Instances with window mode capability **************/
18017#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
18018
18019/******************************* CRC Instances ********************************/
18020#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
18021
18022/******************************* DAC Instances ********************************/
18023#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
18024
18025/****************************** DFSDM Instances *******************************/
18026#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
18027 ((INSTANCE) == DFSDM1_Filter1) || \
18028 ((INSTANCE) == DFSDM1_Filter2) || \
18029 ((INSTANCE) == DFSDM1_Filter3))
18030
18031#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
18032 ((INSTANCE) == DFSDM1_Channel1) || \
18033 ((INSTANCE) == DFSDM1_Channel2) || \
18034 ((INSTANCE) == DFSDM1_Channel3) || \
18035 ((INSTANCE) == DFSDM1_Channel4) || \
18036 ((INSTANCE) == DFSDM1_Channel5) || \
18037 ((INSTANCE) == DFSDM1_Channel6) || \
18038 ((INSTANCE) == DFSDM1_Channel7))
18039
18040/******************************** DMA Instances *******************************/
18041#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
18042 ((INSTANCE) == DMA1_Channel2) || \
18043 ((INSTANCE) == DMA1_Channel3) || \
18044 ((INSTANCE) == DMA1_Channel4) || \
18045 ((INSTANCE) == DMA1_Channel5) || \
18046 ((INSTANCE) == DMA1_Channel6) || \
18047 ((INSTANCE) == DMA1_Channel7) || \
18048 ((INSTANCE) == DMA2_Channel1) || \
18049 ((INSTANCE) == DMA2_Channel2) || \
18050 ((INSTANCE) == DMA2_Channel3) || \
18051 ((INSTANCE) == DMA2_Channel4) || \
18052 ((INSTANCE) == DMA2_Channel5) || \
18053 ((INSTANCE) == DMA2_Channel6) || \
18054 ((INSTANCE) == DMA2_Channel7))
18055
18056/******************************* GPIO Instances *******************************/
18057#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
18058 ((INSTANCE) == GPIOB) || \
18059 ((INSTANCE) == GPIOC) || \
18060 ((INSTANCE) == GPIOD) || \
18061 ((INSTANCE) == GPIOE) || \
18062 ((INSTANCE) == GPIOF) || \
18063 ((INSTANCE) == GPIOG) || \
18064 ((INSTANCE) == GPIOH))
18065
18066/******************************* GPIO AF Instances ****************************/
18067/* On L4, all GPIO Bank support AF */
18068#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
18069
18070/**************************** GPIO Lock Instances *****************************/
18071/* On L4, all GPIO Bank support the Lock mechanism */
18072#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
18073
18074/******************************** I2C Instances *******************************/
18075#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
18076 ((INSTANCE) == I2C2) || \
18077 ((INSTANCE) == I2C3))
18078
18079/****************** I2C Instances : wakeup capability from stop modes *********/
18080#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
18081
18082/******************************* HCD Instances *******************************/
18083#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
18084
18085/****************************** OPAMP Instances *******************************/
18086#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
18087 ((INSTANCE) == OPAMP2))
18088
18089#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
18090
18091/******************************* PCD Instances *******************************/
18092#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
18093
18094/******************************* QSPI Instances *******************************/
18095#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
18096
18097/******************************* RNG Instances ********************************/
18098#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
18099
18100/****************************** RTC Instances *********************************/
18101#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
18102
18103/******************************** SAI Instances *******************************/
18104#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
18105 ((INSTANCE) == SAI1_Block_B) || \
18106 ((INSTANCE) == SAI2_Block_A) || \
18107 ((INSTANCE) == SAI2_Block_B))
18108
18109/****************************** SDMMC Instances *******************************/
18110#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
18111
18112/****************************** SMBUS Instances *******************************/
18113#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
18114 ((INSTANCE) == I2C2) || \
18115 ((INSTANCE) == I2C3))
18116
18117/******************************** SPI Instances *******************************/
18118#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
18119 ((INSTANCE) == SPI2) || \
18120 ((INSTANCE) == SPI3))
18121
18122/******************************** SWPMI Instances *****************************/
18123#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
18124
18125/****************** LPTIM Instances : All supported instances *****************/
18126#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
18127 ((INSTANCE) == LPTIM2))
18128
18129/****************** TIM Instances : All supported instances *******************/
18130#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18131 ((INSTANCE) == TIM2) || \
18132 ((INSTANCE) == TIM3) || \
18133 ((INSTANCE) == TIM4) || \
18134 ((INSTANCE) == TIM5) || \
18135 ((INSTANCE) == TIM6) || \
18136 ((INSTANCE) == TIM7) || \
18137 ((INSTANCE) == TIM8) || \
18138 ((INSTANCE) == TIM15) || \
18139 ((INSTANCE) == TIM16) || \
18140 ((INSTANCE) == TIM17))
18141
18142/****************** TIM Instances : supporting 32 bits counter ****************/
18143#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
18144 ((INSTANCE) == TIM5))
18145
18146/****************** TIM Instances : supporting the break function *************/
18147#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18148 ((INSTANCE) == TIM8) || \
18149 ((INSTANCE) == TIM15) || \
18150 ((INSTANCE) == TIM16) || \
18151 ((INSTANCE) == TIM17))
18152
18153/************** TIM Instances : supporting Break source selection *************/
18154#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18155 ((INSTANCE) == TIM8) || \
18156 ((INSTANCE) == TIM15) || \
18157 ((INSTANCE) == TIM16) || \
18158 ((INSTANCE) == TIM17))
18159
18160/****************** TIM Instances : supporting 2 break inputs *****************/
18161#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18162 ((INSTANCE) == TIM8))
18163
18164/************* TIM Instances : at least 1 capture/compare channel *************/
18165#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18166 ((INSTANCE) == TIM2) || \
18167 ((INSTANCE) == TIM3) || \
18168 ((INSTANCE) == TIM4) || \
18169 ((INSTANCE) == TIM5) || \
18170 ((INSTANCE) == TIM8) || \
18171 ((INSTANCE) == TIM15) || \
18172 ((INSTANCE) == TIM16) || \
18173 ((INSTANCE) == TIM17))
18174
18175/************ TIM Instances : at least 2 capture/compare channels *************/
18176#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18177 ((INSTANCE) == TIM2) || \
18178 ((INSTANCE) == TIM3) || \
18179 ((INSTANCE) == TIM4) || \
18180 ((INSTANCE) == TIM5) || \
18181 ((INSTANCE) == TIM8) || \
18182 ((INSTANCE) == TIM15))
18183
18184/************ TIM Instances : at least 3 capture/compare channels *************/
18185#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18186 ((INSTANCE) == TIM2) || \
18187 ((INSTANCE) == TIM3) || \
18188 ((INSTANCE) == TIM4) || \
18189 ((INSTANCE) == TIM5) || \
18190 ((INSTANCE) == TIM8))
18191
18192/************ TIM Instances : at least 4 capture/compare channels *************/
18193#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18194 ((INSTANCE) == TIM2) || \
18195 ((INSTANCE) == TIM3) || \
18196 ((INSTANCE) == TIM4) || \
18197 ((INSTANCE) == TIM5) || \
18198 ((INSTANCE) == TIM8))
18199
18200/****************** TIM Instances : at least 5 capture/compare channels *******/
18201#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18202 ((INSTANCE) == TIM8))
18203
18204/****************** TIM Instances : at least 6 capture/compare channels *******/
18205#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18206 ((INSTANCE) == TIM8))
18207
18208/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
18209#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18210 ((INSTANCE) == TIM8) || \
18211 ((INSTANCE) == TIM15) || \
18212 ((INSTANCE) == TIM16) || \
18213 ((INSTANCE) == TIM17))
18214
18215/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
18216#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18217 ((INSTANCE) == TIM2) || \
18218 ((INSTANCE) == TIM3) || \
18219 ((INSTANCE) == TIM4) || \
18220 ((INSTANCE) == TIM5) || \
18221 ((INSTANCE) == TIM6) || \
18222 ((INSTANCE) == TIM7) || \
18223 ((INSTANCE) == TIM8) || \
18224 ((INSTANCE) == TIM15) || \
18225 ((INSTANCE) == TIM16) || \
18226 ((INSTANCE) == TIM17))
18227
18228/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
18229#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18230 ((INSTANCE) == TIM2) || \
18231 ((INSTANCE) == TIM3) || \
18232 ((INSTANCE) == TIM4) || \
18233 ((INSTANCE) == TIM5) || \
18234 ((INSTANCE) == TIM8) || \
18235 ((INSTANCE) == TIM15) || \
18236 ((INSTANCE) == TIM16) || \
18237 ((INSTANCE) == TIM17))
18238
18239/******************** TIM Instances : DMA burst feature ***********************/
18240#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18241 ((INSTANCE) == TIM2) || \
18242 ((INSTANCE) == TIM3) || \
18243 ((INSTANCE) == TIM4) || \
18244 ((INSTANCE) == TIM5) || \
18245 ((INSTANCE) == TIM8) || \
18246 ((INSTANCE) == TIM15) || \
18247 ((INSTANCE) == TIM16) || \
18248 ((INSTANCE) == TIM17))
18249
18250/******************* TIM Instances : output(s) available **********************/
18251#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
18252 ((((INSTANCE) == TIM1) && \
18253 (((CHANNEL) == TIM_CHANNEL_1) || \
18254 ((CHANNEL) == TIM_CHANNEL_2) || \
18255 ((CHANNEL) == TIM_CHANNEL_3) || \
18256 ((CHANNEL) == TIM_CHANNEL_4) || \
18257 ((CHANNEL) == TIM_CHANNEL_5) || \
18258 ((CHANNEL) == TIM_CHANNEL_6))) \
18259 || \
18260 (((INSTANCE) == TIM2) && \
18261 (((CHANNEL) == TIM_CHANNEL_1) || \
18262 ((CHANNEL) == TIM_CHANNEL_2) || \
18263 ((CHANNEL) == TIM_CHANNEL_3) || \
18264 ((CHANNEL) == TIM_CHANNEL_4))) \
18265 || \
18266 (((INSTANCE) == TIM3) && \
18267 (((CHANNEL) == TIM_CHANNEL_1) || \
18268 ((CHANNEL) == TIM_CHANNEL_2) || \
18269 ((CHANNEL) == TIM_CHANNEL_3) || \
18270 ((CHANNEL) == TIM_CHANNEL_4))) \
18271 || \
18272 (((INSTANCE) == TIM4) && \
18273 (((CHANNEL) == TIM_CHANNEL_1) || \
18274 ((CHANNEL) == TIM_CHANNEL_2) || \
18275 ((CHANNEL) == TIM_CHANNEL_3) || \
18276 ((CHANNEL) == TIM_CHANNEL_4))) \
18277 || \
18278 (((INSTANCE) == TIM5) && \
18279 (((CHANNEL) == TIM_CHANNEL_1) || \
18280 ((CHANNEL) == TIM_CHANNEL_2) || \
18281 ((CHANNEL) == TIM_CHANNEL_3) || \
18282 ((CHANNEL) == TIM_CHANNEL_4))) \
18283 || \
18284 (((INSTANCE) == TIM8) && \
18285 (((CHANNEL) == TIM_CHANNEL_1) || \
18286 ((CHANNEL) == TIM_CHANNEL_2) || \
18287 ((CHANNEL) == TIM_CHANNEL_3) || \
18288 ((CHANNEL) == TIM_CHANNEL_4) || \
18289 ((CHANNEL) == TIM_CHANNEL_5) || \
18290 ((CHANNEL) == TIM_CHANNEL_6))) \
18291 || \
18292 (((INSTANCE) == TIM15) && \
18293 (((CHANNEL) == TIM_CHANNEL_1) || \
18294 ((CHANNEL) == TIM_CHANNEL_2))) \
18295 || \
18296 (((INSTANCE) == TIM16) && \
18297 (((CHANNEL) == TIM_CHANNEL_1))) \
18298 || \
18299 (((INSTANCE) == TIM17) && \
18300 (((CHANNEL) == TIM_CHANNEL_1))))
18301
18302/****************** TIM Instances : supporting complementary output(s) ********/
18303#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
18304 ((((INSTANCE) == TIM1) && \
18305 (((CHANNEL) == TIM_CHANNEL_1) || \
18306 ((CHANNEL) == TIM_CHANNEL_2) || \
18307 ((CHANNEL) == TIM_CHANNEL_3))) \
18308 || \
18309 (((INSTANCE) == TIM8) && \
18310 (((CHANNEL) == TIM_CHANNEL_1) || \
18311 ((CHANNEL) == TIM_CHANNEL_2) || \
18312 ((CHANNEL) == TIM_CHANNEL_3))) \
18313 || \
18314 (((INSTANCE) == TIM15) && \
18315 ((CHANNEL) == TIM_CHANNEL_1)) \
18316 || \
18317 (((INSTANCE) == TIM16) && \
18318 ((CHANNEL) == TIM_CHANNEL_1)) \
18319 || \
18320 (((INSTANCE) == TIM17) && \
18321 ((CHANNEL) == TIM_CHANNEL_1)))
18322
18323/****************** TIM Instances : supporting clock division *****************/
18324#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18325 ((INSTANCE) == TIM2) || \
18326 ((INSTANCE) == TIM3) || \
18327 ((INSTANCE) == TIM4) || \
18328 ((INSTANCE) == TIM5) || \
18329 ((INSTANCE) == TIM8) || \
18330 ((INSTANCE) == TIM15) || \
18331 ((INSTANCE) == TIM16) || \
18332 ((INSTANCE) == TIM17))
18333
18334/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
18335#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18336 ((INSTANCE) == TIM2) || \
18337 ((INSTANCE) == TIM3) || \
18338 ((INSTANCE) == TIM4) || \
18339 ((INSTANCE) == TIM5) || \
18340 ((INSTANCE) == TIM8) || \
18341 ((INSTANCE) == TIM15))
18342
18343/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
18344#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18345 ((INSTANCE) == TIM2) || \
18346 ((INSTANCE) == TIM3) || \
18347 ((INSTANCE) == TIM4) || \
18348 ((INSTANCE) == TIM5) || \
18349 ((INSTANCE) == TIM8))
18350
18351/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
18352#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18353 ((INSTANCE) == TIM2) || \
18354 ((INSTANCE) == TIM3) || \
18355 ((INSTANCE) == TIM4) || \
18356 ((INSTANCE) == TIM5) || \
18357 ((INSTANCE) == TIM8) || \
18358 ((INSTANCE) == TIM15))
18359
18360/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
18361#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18362 ((INSTANCE) == TIM2) || \
18363 ((INSTANCE) == TIM3) || \
18364 ((INSTANCE) == TIM4) || \
18365 ((INSTANCE) == TIM5) || \
18366 ((INSTANCE) == TIM8) || \
18367 ((INSTANCE) == TIM15))
18368
18369/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
18370#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18371 ((INSTANCE) == TIM8))
18372
18373/****************** TIM Instances : supporting commutation event generation ***/
18374#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18375 ((INSTANCE) == TIM8) || \
18376 ((INSTANCE) == TIM15) || \
18377 ((INSTANCE) == TIM16) || \
18378 ((INSTANCE) == TIM17))
18379
18380/****************** TIM Instances : supporting counting mode selection ********/
18381#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18382 ((INSTANCE) == TIM2) || \
18383 ((INSTANCE) == TIM3) || \
18384 ((INSTANCE) == TIM4) || \
18385 ((INSTANCE) == TIM5) || \
18386 ((INSTANCE) == TIM8))
18387
18388/****************** TIM Instances : supporting encoder interface **************/
18389#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18390 ((INSTANCE) == TIM2) || \
18391 ((INSTANCE) == TIM3) || \
18392 ((INSTANCE) == TIM4) || \
18393 ((INSTANCE) == TIM5) || \
18394 ((INSTANCE) == TIM8))
18395
18396/****************** TIM Instances : supporting Hall sensor interface **********/
18397#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18398 ((INSTANCE) == TIM2) || \
18399 ((INSTANCE) == TIM3) || \
18400 ((INSTANCE) == TIM4) || \
18401 ((INSTANCE) == TIM5) || \
18402 ((INSTANCE) == TIM8))
18403
18404/**************** TIM Instances : external trigger input available ************/
18405#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18406 ((INSTANCE) == TIM2) || \
18407 ((INSTANCE) == TIM3) || \
18408 ((INSTANCE) == TIM4) || \
18409 ((INSTANCE) == TIM5) || \
18410 ((INSTANCE) == TIM8))
18411
18412/************* TIM Instances : supporting ETR source selection ***************/
18413#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18414 ((INSTANCE) == TIM2) || \
18415 ((INSTANCE) == TIM3) || \
18416 ((INSTANCE) == TIM8))
18417
18418/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
18419#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18420 ((INSTANCE) == TIM2) || \
18421 ((INSTANCE) == TIM3) || \
18422 ((INSTANCE) == TIM4) || \
18423 ((INSTANCE) == TIM5) || \
18424 ((INSTANCE) == TIM6) || \
18425 ((INSTANCE) == TIM7) || \
18426 ((INSTANCE) == TIM8) || \
18427 ((INSTANCE) == TIM15))
18428
18429/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
18430#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18431 ((INSTANCE) == TIM2) || \
18432 ((INSTANCE) == TIM3) || \
18433 ((INSTANCE) == TIM4) || \
18434 ((INSTANCE) == TIM5) || \
18435 ((INSTANCE) == TIM8) || \
18436 ((INSTANCE) == TIM15))
18437
18438/****************** TIM Instances : supporting OCxREF clear *******************/
18439#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18440 ((INSTANCE) == TIM2) || \
18441 ((INSTANCE) == TIM3) || \
18442 ((INSTANCE) == TIM4) || \
18443 ((INSTANCE) == TIM5) || \
18444 ((INSTANCE) == TIM8))
18445
18446/****************** TIM Instances : remapping capability **********************/
18447#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18448 ((INSTANCE) == TIM2) || \
18449 ((INSTANCE) == TIM3) || \
18450 ((INSTANCE) == TIM8) || \
18451 ((INSTANCE) == TIM15) || \
18452 ((INSTANCE) == TIM16) || \
18453 ((INSTANCE) == TIM17))
18454
18455/****************** TIM Instances : supporting repetition counter *************/
18456#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18457 ((INSTANCE) == TIM8) || \
18458 ((INSTANCE) == TIM15) || \
18459 ((INSTANCE) == TIM16) || \
18460 ((INSTANCE) == TIM17))
18461
18462/****************** TIM Instances : supporting synchronization ****************/
18463#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
18464
18465/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
18466#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18467 ((INSTANCE) == TIM8))
18468
18469/******************* TIM Instances : Timer input XOR function *****************/
18470#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18471 ((INSTANCE) == TIM2) || \
18472 ((INSTANCE) == TIM3) || \
18473 ((INSTANCE) == TIM4) || \
18474 ((INSTANCE) == TIM5) || \
18475 ((INSTANCE) == TIM8) || \
18476 ((INSTANCE) == TIM15))
18477
18478/****************** TIM Instances : Advanced timer instances *******************/
18479#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18480 ((INSTANCE) == TIM8))
18481
18482/****************************** TSC Instances *********************************/
18483#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
18484
18485/******************** USART Instances : Synchronous mode **********************/
18486#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18487 ((INSTANCE) == USART2) || \
18488 ((INSTANCE) == USART3))
18489
18490/******************** UART Instances : Asynchronous mode **********************/
18491#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18492 ((INSTANCE) == USART2) || \
18493 ((INSTANCE) == USART3) || \
18494 ((INSTANCE) == UART4) || \
18495 ((INSTANCE) == UART5))
18496
18497/****************** UART Instances : Auto Baud Rate detection ****************/
18498#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18499 ((INSTANCE) == USART2) || \
18500 ((INSTANCE) == USART3) || \
18501 ((INSTANCE) == UART4) || \
18502 ((INSTANCE) == UART5))
18503
18504/****************** UART Instances : Driver Enable *****************/
18505#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18506 ((INSTANCE) == USART2) || \
18507 ((INSTANCE) == USART3) || \
18508 ((INSTANCE) == UART4) || \
18509 ((INSTANCE) == UART5) || \
18510 ((INSTANCE) == LPUART1))
18511
18512/******************** UART Instances : Half-Duplex mode **********************/
18513#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18514 ((INSTANCE) == USART2) || \
18515 ((INSTANCE) == USART3) || \
18516 ((INSTANCE) == UART4) || \
18517 ((INSTANCE) == UART5) || \
18518 ((INSTANCE) == LPUART1))
18519
18520/****************** UART Instances : Hardware Flow control ********************/
18521#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18522 ((INSTANCE) == USART2) || \
18523 ((INSTANCE) == USART3) || \
18524 ((INSTANCE) == UART4) || \
18525 ((INSTANCE) == UART5) || \
18526 ((INSTANCE) == LPUART1))
18527
18528/******************** UART Instances : LIN mode **********************/
18529#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18530 ((INSTANCE) == USART2) || \
18531 ((INSTANCE) == USART3) || \
18532 ((INSTANCE) == UART4) || \
18533 ((INSTANCE) == UART5))
18534
18535/******************** UART Instances : Wake-up from Stop mode **********************/
18536#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18537 ((INSTANCE) == USART2) || \
18538 ((INSTANCE) == USART3) || \
18539 ((INSTANCE) == UART4) || \
18540 ((INSTANCE) == UART5) || \
18541 ((INSTANCE) == LPUART1))
18542
18543/*********************** UART Instances : IRDA mode ***************************/
18544#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18545 ((INSTANCE) == USART2) || \
18546 ((INSTANCE) == USART3) || \
18547 ((INSTANCE) == UART4) || \
18548 ((INSTANCE) == UART5))
18549
18550/********************* USART Instances : Smard card mode ***********************/
18551#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18552 ((INSTANCE) == USART2) || \
18553 ((INSTANCE) == USART3))
18554
18555/******************** LPUART Instance *****************************************/
18556#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
18557
18558/****************************** IWDG Instances ********************************/
18559#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
18560
18561/****************************** WWDG Instances ********************************/
18562#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
18563
18564/**
18565 * @}
18566 */
18567
18568
18569/******************************************************************************/
18570/* For a painless codes migration between the STM32L4xx device product */
18571/* lines, the aliases defined below are put in place to overcome the */
18572/* differences in the interrupt handlers and IRQn definitions. */
18573/* No need to update developed interrupt code when moving across */
18574/* product lines within the same STM32L4 Family */
18575/******************************************************************************/
18576
18577/* Aliases for __IRQn */
18578#define ADC1_IRQn ADC1_2_IRQn
18579#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
18580#define TIM8_IRQn TIM8_UP_IRQn
18581#define HASH_RNG_IRQn RNG_IRQn
18582#define DFSDM0_IRQn DFSDM1_FLT0_IRQn
18583#define DFSDM1_IRQn DFSDM1_FLT1_IRQn
18584#define DFSDM2_IRQn DFSDM1_FLT2_IRQn
18585#define DFSDM3_IRQn DFSDM1_FLT3_IRQn
18586
18587/* Aliases for __IRQHandler */
18588#define ADC1_IRQHandler ADC1_2_IRQHandler
18589#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
18590#define TIM8_IRQHandler TIM8_UP_IRQHandler
18591#define HASH_RNG_IRQHandler RNG_IRQHandler
18592#define DFSDM0_IRQHandler DFSDM1_FLT0_IRQHandler
18593#define DFSDM1_IRQHandler DFSDM1_FLT1_IRQHandler
18594#define DFSDM2_IRQHandler DFSDM1_FLT2_IRQHandler
18595#define DFSDM3_IRQHandler DFSDM1_FLT3_IRQHandler
18596
18597#ifdef __cplusplus
18598}
18599#endif /* __cplusplus */
18600
18601#endif /* __STM32L485xx_H */
18602
18603/**
18604 * @}
18605 */
18606
18607 /**
18608 * @}
18609 */
18610
18611/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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