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1/**
2 ******************************************************************************
3 * @file stm32l4s7xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32L4S7xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral�s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42/** @addtogroup CMSIS_Device
43 * @{
44 */
45
46/** @addtogroup stm32l4s7xx
47 * @{
48 */
49
50#ifndef __STM32L4S7xx_H
51#define __STM32L4S7xx_H
52
53#ifdef __cplusplus
54 extern "C" {
55#endif /* __cplusplus */
56
57/** @addtogroup Configuration_section_for_CMSIS
58 * @{
59 */
60
61/**
62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63 */
64#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
65#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
66#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
67#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
68#define __FPU_PRESENT 1 /*!< FPU present */
69
70/**
71 * @}
72 */
73
74/** @addtogroup Peripheral_interrupt_number_definition
75 * @{
76 */
77
78/**
79 * @brief STM32L4XX Interrupt Number Definition, according to the selected device
80 * in @ref Library_configuration_section
81 */
82typedef enum
83{
84/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
86 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
87 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
88 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
89 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
90 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
91 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
92 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
93 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
94/****** STM32 specific Interrupt Numbers **********************************************************************/
95 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
96 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
97 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
98 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
99 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
100 RCC_IRQn = 5, /*!< RCC global Interrupt */
101 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
102 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
103 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
104 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
105 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
106 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
107 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
108 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
109 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
110 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
111 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
112 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
113 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
114 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
115 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
116 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
117 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
118 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
119 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
120 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
121 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
122 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
123 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
124 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
125 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
128 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
129 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
130 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
131 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
132 USART1_IRQn = 37, /*!< USART1 global Interrupt */
133 USART2_IRQn = 38, /*!< USART2 global Interrupt */
134 USART3_IRQn = 39, /*!< USART3 global Interrupt */
135 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
136 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
137 DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */
138 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
139 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
140 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
141 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
142 FMC_IRQn = 48, /*!< FMC global Interrupt */
143 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
144 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
145 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
146 UART4_IRQn = 52, /*!< UART4 global Interrupt */
147 UART5_IRQn = 53, /*!< UART5 global Interrupt */
148 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
149 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
150 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
151 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
152 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
153 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
154 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
155 DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
156 DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
157 DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */
158 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
159 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
160 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
161 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
162 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
163 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
164 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
165 OCTOSPI1_IRQn = 71, /*!< OctoSPI1 global interrupt */
166 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
167 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
168 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
169 SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */
170 OCTOSPI2_IRQn = 76, /*!< OctoSPI2 global interrupt */
171 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
172 AES_IRQn = 79, /*!< AES global interrupt */
173 RNG_IRQn = 80, /*!< RNG global interrupt */
174 FPU_IRQn = 81, /*!< FPU global interrupt */
175 HASH_CRS_IRQn = 82, /*!< HASH and CRS interrupt */
176 I2C4_EV_IRQn = 83, /*!< I2C4 Event interrupt */
177 I2C4_ER_IRQn = 84, /*!< I2C4 Error interrupt */
178 DCMI_IRQn = 85, /*!< DCMI global interrupt */
179 DMA2D_IRQn = 90, /*!< DMA2D global interrupt */
180 LTDC_IRQn = 91, /*!< LTDC global Interrupt */
181 LTDC_ER_IRQn = 92, /*!< LTDC Error global Interrupt */
182 GFXMMU_IRQn = 93, /*!< GFXMMU global error interrupt */
183 DMAMUX1_OVR_IRQn = 94 /*!< DMAMUX1 overrun global interrupt */
184} IRQn_Type;
185
186/**
187 * @}
188 */
189
190#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
191#include "system_stm32l4xx.h"
192#include <stdint.h>
193
194/** @addtogroup Peripheral_registers_structures
195 * @{
196 */
197
198/**
199 * @brief Analog to Digital Converter
200 */
201
202typedef struct
203{
204 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
205 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
206 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
207 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
208 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
209 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
210 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
211 uint32_t RESERVED1; /*!< Reserved, 0x1C */
212 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
213 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
214 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
215 uint32_t RESERVED2; /*!< Reserved, 0x2C */
216 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
217 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
218 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
219 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
220 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
221 uint32_t RESERVED3; /*!< Reserved, 0x44 */
222 uint32_t RESERVED4; /*!< Reserved, 0x48 */
223 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
224 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
225 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
226 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
227 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
228 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
229 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
230 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
231 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
232 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
233 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
234 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
235 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
236 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
237 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
238 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
239 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
240 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
241
242} ADC_TypeDef;
243
244typedef struct
245{
246 uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */
247 uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
248 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
249 uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */
250} ADC_Common_TypeDef;
251
252/**
253 * @brief DCMI
254 */
255
256typedef struct
257{
258 __IO uint32_t CR; /*!< DCMI control register, Address offset: 0x00 */
259 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
260 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
261 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
262 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
263 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
264 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
265 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
266 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
267 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
268 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
269} DCMI_TypeDef;
270
271/**
272 * @brief Controller Area Network TxMailBox
273 */
274
275typedef struct
276{
277 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
278 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
279 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
280 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
281} CAN_TxMailBox_TypeDef;
282
283/**
284 * @brief Controller Area Network FIFOMailBox
285 */
286
287typedef struct
288{
289 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
290 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
291 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
292 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
293} CAN_FIFOMailBox_TypeDef;
294
295/**
296 * @brief Controller Area Network FilterRegister
297 */
298
299typedef struct
300{
301 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
302 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
303} CAN_FilterRegister_TypeDef;
304
305/**
306 * @brief Controller Area Network
307 */
308
309typedef struct
310{
311 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
312 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
313 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
314 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
315 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
316 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
317 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
318 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
319 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
320 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
321 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
322 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
323 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
324 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
325 uint32_t RESERVED2; /*!< Reserved, 0x208 */
326 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
327 uint32_t RESERVED3; /*!< Reserved, 0x210 */
328 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
329 uint32_t RESERVED4; /*!< Reserved, 0x218 */
330 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
331 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
332 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
333} CAN_TypeDef;
334
335
336/**
337 * @brief Comparator
338 */
339
340typedef struct
341{
342 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
343} COMP_TypeDef;
344
345typedef struct
346{
347 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
348} COMP_Common_TypeDef;
349
350/**
351 * @brief CRC calculation unit
352 */
353
354typedef struct
355{
356 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
357 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
358 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
359 uint32_t RESERVED2; /*!< Reserved, 0x0C */
360 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
361 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
362} CRC_TypeDef;
363
364/**
365 * @brief Clock Recovery System
366 */
367typedef struct
368{
369__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
370__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
371__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
372__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
373} CRS_TypeDef;
374
375/**
376 * @brief Digital to Analog Converter
377 */
378
379typedef struct
380{
381 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
382 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
383 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
384 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
385 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
386 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
387 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
388 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
389 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
390 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
391 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
392 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
393 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
394 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
395 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
396 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
397 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
398 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
399 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
400 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
401} DAC_TypeDef;
402
403/**
404 * @brief DFSDM module registers
405 */
406typedef struct
407{
408 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
409 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
410 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
411 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
412 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
413 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
414 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
415 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
416 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
417 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
418 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
419 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
420 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
421 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
422 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
423} DFSDM_Filter_TypeDef;
424
425/**
426 * @brief DFSDM channel configuration registers
427 */
428typedef struct
429{
430 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
431 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
432 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
433 short circuit detector register, Address offset: 0x08 */
434 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
435 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
436 __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */
437} DFSDM_Channel_TypeDef;
438
439/**
440 * @brief Debug MCU
441 */
442
443typedef struct
444{
445 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
446 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
447 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
448 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
449 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
450} DBGMCU_TypeDef;
451
452
453/**
454 * @brief DMA Controller
455 */
456
457typedef struct
458{
459 __IO uint32_t CCR; /*!< DMA channel x configuration register */
460 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
461 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
462 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
463} DMA_Channel_TypeDef;
464
465typedef struct
466{
467 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
468 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
469} DMA_TypeDef;
470
471/**
472 * @brief DMA Multiplexer
473 */
474
475typedef struct
476{
477 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
478}DMAMUX_Channel_TypeDef;
479
480typedef struct
481{
482 __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
483 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
484}DMAMUX_ChannelStatus_TypeDef;
485
486typedef struct
487{
488 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
489}DMAMUX_RequestGen_TypeDef;
490
491typedef struct
492{
493 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
494 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
495}DMAMUX_RequestGenStatus_TypeDef;
496
497
498/**
499 * @brief DMA2D Controller
500 */
501
502typedef struct
503{
504 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
505 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
506 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
507 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
508 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
509 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
510 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
511 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
512 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
513 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
514 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
515 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
516 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
517 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
518 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
519 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
520 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
521 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
522 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
523 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
524 uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */
525 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */
526 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */
527} DMA2D_TypeDef;
528
529/**
530 * @brief External Interrupt/Event Controller
531 */
532
533typedef struct
534{
535 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
536 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
537 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
538 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
539 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
540 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
541 uint32_t RESERVED1; /*!< Reserved, 0x18 */
542 uint32_t RESERVED2; /*!< Reserved, 0x1C */
543 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
544 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
545 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
546 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
547 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
548 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
549} EXTI_TypeDef;
550
551
552/**
553 * @brief Firewall
554 */
555
556typedef struct
557{
558 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
559 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
560 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
561 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
562 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
563 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
564 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
565 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
566 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
567} FIREWALL_TypeDef;
568
569
570/**
571 * @brief FLASH Registers
572 */
573
574typedef struct
575{
576 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
577 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
578 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
579 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
580 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
581 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
582 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
583 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
584 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
585 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
586 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
587 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
588 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
589 uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */
590 __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
591 __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
592 __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
593 __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
594 uint32_t RESERVED3[55]; /*!< Reserved3, Address offset: 0x54-0x12C */
595 __IO uint32_t CFGR; /*!< FLASH configuration register, Address offset: 0x130 */
596} FLASH_TypeDef;
597
598
599/**
600 * @brief Flexible Memory Controller
601 */
602
603typedef struct
604{
605 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
606} FMC_Bank1_TypeDef;
607
608/**
609 * @brief Flexible Memory Controller Bank1E
610 */
611
612typedef struct
613{
614 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
615} FMC_Bank1E_TypeDef;
616
617/**
618 * @brief Flexible Memory Controller Bank3
619 */
620
621typedef struct
622{
623 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
624 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
625 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
626 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
627 uint32_t RESERVED0; /*!< Reserved, 0x90 */
628 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
629} FMC_Bank3_TypeDef;
630
631/**
632 * @brief GFXMMU registers
633 */
634
635typedef struct
636{
637 __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */
638 __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */
639 __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */
640 uint32_t RESERVED0; /*!< Reserved0, Address offset: 0x0C */
641 __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */
642 uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */
643 __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */
644 __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
645 __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
646 __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
647 uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */
648 __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
649 For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
650} GFXMMU_TypeDef;
651
652/**
653 * @brief General Purpose I/O
654 */
655
656typedef struct
657{
658 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
659 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
660 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
661 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
662 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
663 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
664 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
665 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
666 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
667 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
668
669} GPIO_TypeDef;
670
671
672/**
673 * @brief Inter-integrated Circuit Interface
674 */
675
676typedef struct
677{
678 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
679 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
680 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
681 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
682 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
683 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
684 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
685 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
686 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
687 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
688 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
689} I2C_TypeDef;
690
691/**
692 * @brief Independent WATCHDOG
693 */
694
695typedef struct
696{
697 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
698 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
699 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
700 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
701 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
702} IWDG_TypeDef;
703
704/**
705 * @brief LPTIMER
706 */
707typedef struct
708{
709 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
710 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
711 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
712 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
713 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
714 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
715 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
716 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
717 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
718} LPTIM_TypeDef;
719
720/**
721 * @brief LCD-TFT Display Controller
722 */
723
724typedef struct
725{
726 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
727 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
728 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
729 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
730 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
731 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
732 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
733 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
734 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
735 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
736 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
737 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
738 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
739 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
740 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
741 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
742 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
743} LTDC_TypeDef;
744
745/**
746 * @brief LCD-TFT Display layer x Controller
747 */
748
749typedef struct
750{
751 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
752 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
753 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
754 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
755 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
756 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
757 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
758 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
759 uint32_t RESERVED0[2]; /*!< Reserved */
760 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
761 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
762 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
763 uint32_t RESERVED1[3]; /*!< Reserved */
764 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
765
766} LTDC_Layer_TypeDef;
767
768/**
769 * @brief Operational Amplifier (OPAMP)
770 */
771
772typedef struct
773{
774 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
775 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
776 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
777} OPAMP_TypeDef;
778
779typedef struct
780{
781 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
782} OPAMP_Common_TypeDef;
783
784/**
785 * @brief Power Control
786 */
787
788typedef struct
789{
790 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
791 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
792 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
793 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
794 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
795 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
796 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
797 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
798 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
799 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
800 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
801 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
802 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
803 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
804 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
805 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
806 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
807 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
808 __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
809 __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
810 __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
811 __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
812 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
813 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
814 __IO uint32_t PUCRI; /*!< Pull_up control register of portI, Address offset: 0x60 */
815 __IO uint32_t PDCRI; /*!< Pull_Down control register of portI, Address offset: 0x64 */
816 uint32_t RESERVED1[6]; /*!< Reserved, Address offset: 0x68-0x7C */
817 __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */
818} PWR_TypeDef;
819
820
821/**
822 * @brief OCTO Serial Peripheral Interface
823 */
824
825typedef struct
826{
827 __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */
828 uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */
829 __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */
830 __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */
831 __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */
832 uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x014-0x01C */
833 __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */
834 __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */
835 uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
836 __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */
837 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */
838 __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */
839 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */
840 __IO uint32_t DR; /*!< OCTOPSI Data register, Address offset: 0x050 */
841 uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
842 __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */
843 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */
844 __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */
845 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */
846 __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */
847 uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
848 __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */
849 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */
850 __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */
851 uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */
852 __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */
853 uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
854 __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */
855 uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
856 __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */
857 uint32_t RESERVED13[19]; /*!< Reserved, Address offset: 0x134-0x17C */
858 __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */
859 uint32_t RESERVED14; /*!< Reserved, Address offset: 0x184 */
860 __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */
861 uint32_t RESERVED15; /*!< Reserved, Address offset: 0x18C */
862 __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */
863 uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x194-0x19C */
864 __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
865 uint32_t RESERVED17[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
866 __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
867} OCTOSPI_TypeDef;
868
869/**
870 * @brief OCTO Serial Peripheral Interface IO Manager
871 */
872
873typedef struct
874{
875 uint32_t RESERVED; /*!< Reserved, Address offset: 0x00 */
876 __IO uint32_t PCR[2]; /*!< OCTOSPI IO Manager Port[1:2] Configuration register, Address offset: 0x04-0x08 */
877} OCTOSPIM_TypeDef;
878
879/**
880 * @brief Reset and Clock Control
881 */
882
883typedef struct
884{
885 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
886 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
887 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
888 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
889 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
890 __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */
891 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
892 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
893 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
894 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
895 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
896 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
897 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
898 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
899 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
900 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
901 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
902 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
903 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
904 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
905 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
906 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
907 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
908 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
909 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
910 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
911 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
912 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
913 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
914 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
915 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
916 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
917 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
918 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
919 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
920 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
921 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
922 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
923 __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
924 __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
925} RCC_TypeDef;
926
927/**
928 * @brief Real-Time Clock
929 */
930
931typedef struct
932{
933 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
934 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
935 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
936 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
937 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
938 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
939 uint32_t reserved; /*!< Reserved */
940 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
941 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
942 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
943 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
944 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
945 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
946 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
947 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
948 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
949 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
950 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
951 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
952 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
953 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
954 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
955 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
956 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
957 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
958 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
959 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
960 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
961 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
962 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
963 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
964 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
965 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
966 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
967 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
968 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
969 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
970 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
971 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
972 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
973 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
974 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
975 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
976 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
977 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
978 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
979 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
980 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
981 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
982 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
983 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
984 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
985} RTC_TypeDef;
986
987
988/**
989 * @brief Serial Audio Interface
990 */
991
992typedef struct
993{
994 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
995 uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
996 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
997 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
998} SAI_TypeDef;
999
1000typedef struct
1001{
1002 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
1003 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
1004 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
1005 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
1006 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
1007 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
1008 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
1009 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
1010} SAI_Block_TypeDef;
1011
1012
1013/**
1014 * @brief Secure digital input/output Interface
1015 */
1016
1017typedef struct
1018{
1019 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
1020 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
1021 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
1022 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
1023 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
1024 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
1025 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
1026 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
1027 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
1028 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
1029 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
1030 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
1031 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
1032 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
1033 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
1034 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
1035 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
1036 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
1037 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
1038 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
1039 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
1040 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
1041 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
1042 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
1043} SDMMC_TypeDef;
1044/**
1045 * @brief Serial Peripheral Interface
1046 */
1047
1048typedef struct
1049{
1050 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
1051 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
1052 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
1053 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
1054 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
1055 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
1056 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
1057} SPI_TypeDef;
1058
1059
1060/**
1061 * @brief System configuration controller
1062 */
1063
1064typedef struct
1065{
1066 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
1067 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
1068 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
1069 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
1070 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
1071 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
1072 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
1073 __IO uint32_t SWPR2; /*!< SYSCFG SRAM2 write protection register 2, Address offset: 0x28 */
1074} SYSCFG_TypeDef;
1075
1076
1077/**
1078 * @brief TIM
1079 */
1080
1081typedef struct
1082{
1083 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
1084 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
1085 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
1086 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
1087 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
1088 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
1089 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
1090 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
1091 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
1092 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
1093 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
1094 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1095 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
1096 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
1097 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
1098 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
1099 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
1100 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1101 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
1102 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
1103 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
1104 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
1105 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
1106 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
1107 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
1108 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
1109} TIM_TypeDef;
1110
1111
1112/**
1113 * @brief Touch Sensing Controller (TSC)
1114 */
1115
1116typedef struct
1117{
1118 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
1119 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
1120 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
1121 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
1122 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
1123 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
1124 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
1125 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
1126 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
1127 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
1128 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
1129 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
1130 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
1131 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
1132} TSC_TypeDef;
1133
1134/**
1135 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1136 */
1137
1138typedef struct
1139{
1140 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1141 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1142 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1143 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1144 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1145 uint16_t RESERVED2; /*!< Reserved, 0x12 */
1146 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1147 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
1148 uint16_t RESERVED3; /*!< Reserved, 0x1A */
1149 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1150 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1151 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1152 uint16_t RESERVED4; /*!< Reserved, 0x26 */
1153 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1154 uint16_t RESERVED5; /*!< Reserved, 0x2A */
1155 __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
1156} USART_TypeDef;
1157
1158/**
1159 * @brief VREFBUF
1160 */
1161
1162typedef struct
1163{
1164 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
1165 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
1166} VREFBUF_TypeDef;
1167
1168/**
1169 * @brief Window WATCHDOG
1170 */
1171
1172typedef struct
1173{
1174 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1175 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1176 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1177} WWDG_TypeDef;
1178
1179/**
1180 * @brief AES hardware accelerator
1181 */
1182
1183typedef struct
1184{
1185 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
1186 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
1187 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
1188 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
1189 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
1190 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
1191 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
1192 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
1193 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
1194 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
1195 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
1196 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
1197 __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */
1198 __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */
1199 __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */
1200 __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */
1201 __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */
1202 __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */
1203 __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */
1204 __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */
1205 __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */
1206 __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */
1207 __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */
1208 __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */
1209} AES_TypeDef;
1210
1211/**
1212 * @brief HASH
1213 */
1214
1215typedef struct
1216{
1217 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
1218 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
1219 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
1220 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
1221 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
1222 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
1223 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
1224 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
1225} HASH_TypeDef;
1226
1227/**
1228 * @brief HASH_DIGEST
1229 */
1230
1231typedef struct
1232{
1233 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
1234} HASH_DIGEST_TypeDef;
1235
1236/**
1237 * @brief RNG
1238 */
1239
1240typedef struct
1241{
1242 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1243 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1244 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1245} RNG_TypeDef;
1246
1247/**
1248 * @brief USB_OTG_Core_register
1249 */
1250typedef struct
1251{
1252 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
1253 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
1254 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
1255 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
1256 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
1257 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
1258 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
1259 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
1260 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
1261 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
1262 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
1263 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
1264 uint32_t Reserved30[2]; /* Reserved 030h*/
1265 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
1266 __IO uint32_t CID; /* User ID Register 03Ch*/
1267 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1268 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1269 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1270 __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/
1271 uint32_t Reserved6; /* Reserved 050h*/
1272 __IO uint32_t GLPMCFG; /* LPM Register 054h*/
1273 __IO uint32_t GPWRDN; /* Power Down Register 058h*/
1274 __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/
1275 __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/
1276 uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/
1277 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
1278 __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */
1279} USB_OTG_GlobalTypeDef;
1280
1281/**
1282 * @brief USB_OTG_device_Registers
1283 */
1284typedef struct
1285{
1286 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
1287 __IO uint32_t DCTL; /* dev Control Register 804h*/
1288 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
1289 uint32_t Reserved0C; /* Reserved 80Ch*/
1290 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
1291 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
1292 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
1293 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
1294 uint32_t Reserved20; /* Reserved 820h*/
1295 uint32_t Reserved9; /* Reserved 824h*/
1296 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
1297 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
1298 __IO uint32_t DTHRCTL; /* dev thr 830h*/
1299 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
1300 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
1301 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
1302 uint32_t Reserved40; /* dedicated EP mask 840h*/
1303 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
1304 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
1305 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
1306} USB_OTG_DeviceTypeDef;
1307
1308/**
1309 * @brief USB_OTG_IN_Endpoint-Specific_Register
1310 */
1311typedef struct
1312{
1313 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
1314 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
1315 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
1316 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
1317 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
1318 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
1319 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
1320 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
1321} USB_OTG_INEndpointTypeDef;
1322
1323/**
1324 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1325 */
1326typedef struct
1327{
1328 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
1329 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
1330 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
1331 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
1332 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
1333 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
1334 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
1335} USB_OTG_OUTEndpointTypeDef;
1336
1337/**
1338 * @brief USB_OTG_Host_Mode_Register_Structures
1339 */
1340typedef struct
1341{
1342 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
1343 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
1344 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
1345 uint32_t Reserved40C; /* Reserved 40Ch*/
1346 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
1347 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
1348 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
1349} USB_OTG_HostTypeDef;
1350
1351/**
1352 * @brief USB_OTG_Host_Channel_Specific_Registers
1353 */
1354typedef struct
1355{
1356 __IO uint32_t HCCHAR;
1357 __IO uint32_t HCSPLT;
1358 __IO uint32_t HCINT;
1359 __IO uint32_t HCINTMSK;
1360 __IO uint32_t HCTSIZ;
1361 __IO uint32_t HCDMA;
1362 uint32_t Reserved[2];
1363} USB_OTG_HostChannelTypeDef;
1364
1365/**
1366 * @}
1367 */
1368
1369/** @addtogroup Peripheral_memory_map
1370 * @{
1371 */
1372#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 2 MB) base address */
1373#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 192 KB) base address */
1374#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(64 KB) base address */
1375#define SRAM3_BASE ((uint32_t)0x20040000U) /*!< SRAM3(384 KB) base address */
1376#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
1377#define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */
1378#define OCTOSPI1_BASE ((uint32_t)0x90000000U) /*!< OCTOSPI1 memories accessible over AHB base address */
1379#define OCTOSPI2_BASE ((uint32_t)0x70000000U) /*!< OCTOSPI2 memories accessible over AHB base address */
1380
1381#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
1382#define OCTOSPI1_R_BASE ((uint32_t)0xA0001000U) /*!< OCTOSPI1 control registers base address */
1383#define OCTOSPI2_R_BASE ((uint32_t)0xA0001400U) /*!< OCTOSPI2 control registers base address */
1384#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
1385#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
1386/*!< GFXMMU virtual buffers base address */
1387#define GFXMMU_VIRTUAL_BUFFER0_BASE ((uint32_t)0x30000000U)
1388#define GFXMMU_VIRTUAL_BUFFER1_BASE ((uint32_t)0x30400000U)
1389#define GFXMMU_VIRTUAL_BUFFER2_BASE ((uint32_t)0x30800000U)
1390#define GFXMMU_VIRTUAL_BUFFER3_BASE ((uint32_t)0x30C00000U)
1391
1392/* Legacy defines */
1393#define SRAM_BASE SRAM1_BASE
1394#define SRAM_BB_BASE SRAM1_BB_BASE
1395
1396#define SRAM1_SIZE_MAX ((uint32_t)0x00030000U) /*!< maximum SRAM1 size (up to 192 KBytes) */
1397#define SRAM2_SIZE ((uint32_t)0x00010000U) /*!< SRAM2 size (64 KBytes) */
1398#define SRAM3_SIZE ((uint32_t)0x00060000U) /*!< SRAM3 size (384 KBytes) */
1399
1400/*!< Peripheral memory map */
1401#define APB1PERIPH_BASE PERIPH_BASE
1402#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1403#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1404#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
1405
1406#define FMC_BANK1 FMC_BASE
1407#define FMC_BANK1_1 FMC_BANK1
1408#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U)
1409#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U)
1410#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U)
1411#define FMC_BANK3 (FMC_BASE + 0x20000000U)
1412
1413/*!< APB1 peripherals */
1414#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1415#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1416#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1417#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1418#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1419#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1420#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1421#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1422#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1423#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1424#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1425#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1426#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1427#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1428#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1429#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1430#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1431#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1432#define CRS_BASE (APB1PERIPH_BASE + 0x6000U)
1433#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1434#define I2C4_BASE (APB1PERIPH_BASE + 0x8400U)
1435#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1436#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1437#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
1438#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
1439#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
1440#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U)
1441#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
1442#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
1443#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
1444
1445
1446/*!< APB2 peripherals */
1447#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
1448#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U)
1449#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
1450#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
1451#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
1452#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
1453#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
1454#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1455#define TIM8_BASE (APB2PERIPH_BASE + 0x3400U)
1456#define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
1457#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
1458#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
1459#define TIM17_BASE (APB2PERIPH_BASE + 0x4800U)
1460#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
1461#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
1462#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
1463#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
1464#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
1465#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
1466#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
1467#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
1468#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
1469#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
1470#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
1471#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
1472#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
1473#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
1474#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)
1475#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)
1476#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)
1477#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)
1478#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
1479#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
1480#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200)
1481#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280)
1482
1483/*!< AHB1 peripherals */
1484#define DMA1_BASE (AHB1PERIPH_BASE)
1485#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
1486#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800U)
1487#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
1488#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
1489#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1490#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
1491#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1492#define GFXMMU_BASE (AHB1PERIPH_BASE + 0xC000U)
1493
1494
1495#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
1496#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
1497#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
1498#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
1499#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
1500#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
1501#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
1502
1503
1504#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
1505#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
1506#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
1507#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
1508#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
1509#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
1510#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
1511
1512#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
1513#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004)
1514#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008)
1515#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000C)
1516#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010)
1517#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014)
1518#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018)
1519#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001C)
1520#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020)
1521#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024)
1522#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028)
1523#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002C)
1524#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030)
1525#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034)
1526
1527#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100)
1528#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104)
1529#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108)
1530#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010C)
1531
1532#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080)
1533#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140)
1534
1535/*!< AHB2 peripherals */
1536#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
1537#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
1538#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
1539#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U)
1540#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U)
1541#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U)
1542#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U)
1543#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
1544#define GPIOI_BASE (AHB2PERIPH_BASE + 0x2000U)
1545
1546#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U)
1547
1548#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
1549#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
1550
1551#define DCMI_BASE (AHB2PERIPH_BASE + 0x08050000U)
1552
1553#define AES_BASE (AHB2PERIPH_BASE + 0x08060000U)
1554#define HASH_BASE (AHB2PERIPH_BASE + 0x08060400U)
1555#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x08060710U)
1556#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
1557
1558#define OCTOSPIM_BASE (AHB2PERIPH_BASE + 0x08061C00U)
1559#define SDMMC1_BASE (AHB2PERIPH_BASE + 0x08062400U)
1560
1561/*!< FMC Banks registers base address */
1562#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1563#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1564#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1565
1566/* Debug MCU registers base address */
1567#define DBGMCU_BASE ((uint32_t)0xE0042000U)
1568
1569/*!< USB registers base address */
1570#define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U)
1571
1572#define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U)
1573#define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U)
1574#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U)
1575#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U)
1576#define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U)
1577#define USB_OTG_HOST_BASE ((uint32_t)0x00000400U)
1578#define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U)
1579#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U)
1580#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U)
1581#define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U)
1582#define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U)
1583#define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U)
1584
1585
1586#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
1587#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
1588#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
1589/**
1590 * @}
1591 */
1592
1593/** @addtogroup Peripheral_declaration
1594 * @{
1595 */
1596#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1597#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1598#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1599#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1600#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1601#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1602#define RTC ((RTC_TypeDef *) RTC_BASE)
1603#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1604#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1605#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1606#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1607#define USART2 ((USART_TypeDef *) USART2_BASE)
1608#define USART3 ((USART_TypeDef *) USART3_BASE)
1609#define UART4 ((USART_TypeDef *) UART4_BASE)
1610#define UART5 ((USART_TypeDef *) UART5_BASE)
1611#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1612#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1613#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1614#define CRS ((CRS_TypeDef *) CRS_BASE)
1615#define CAN ((CAN_TypeDef *) CAN1_BASE)
1616#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1617#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1618#define PWR ((PWR_TypeDef *) PWR_BASE)
1619#define DAC ((DAC_TypeDef *) DAC1_BASE)
1620#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1621#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1622#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1623#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
1624#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1625#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1626#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1627#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
1628
1629#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1630#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
1631#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1632#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1633#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
1634#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1635#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
1636#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1637#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1638#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1639#define USART1 ((USART_TypeDef *) USART1_BASE)
1640#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1641#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1642#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1643#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1644#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1645#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1646#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1647#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1648#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1649#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1650#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1651#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1652#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1653#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1654#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1655#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1656#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
1657#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
1658#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
1659#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
1660#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1661#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1662#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
1663#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
1664/* Aliases to keep compatibility after DFSDM renaming */
1665#define DFSDM_Channel0 DFSDM1_Channel0
1666#define DFSDM_Channel1 DFSDM1_Channel1
1667#define DFSDM_Channel2 DFSDM1_Channel2
1668#define DFSDM_Channel3 DFSDM1_Channel3
1669#define DFSDM_Channel4 DFSDM1_Channel4
1670#define DFSDM_Channel5 DFSDM1_Channel5
1671#define DFSDM_Channel6 DFSDM1_Channel6
1672#define DFSDM_Channel7 DFSDM1_Channel7
1673#define DFSDM_Filter0 DFSDM1_Filter0
1674#define DFSDM_Filter1 DFSDM1_Filter1
1675#define DFSDM_Filter2 DFSDM1_Filter2
1676#define DFSDM_Filter3 DFSDM1_Filter3
1677#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1678#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1679#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
1680#define RCC ((RCC_TypeDef *) RCC_BASE)
1681#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1682#define CRC ((CRC_TypeDef *) CRC_BASE)
1683#define TSC ((TSC_TypeDef *) TSC_BASE)
1684
1685#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1686#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1687#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1688#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1689#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1690#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1691#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1692#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1693#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1694#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1695#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
1696#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1697#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1698#define HASH ((HASH_TypeDef *) HASH_BASE)
1699#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1700#define AES ((AES_TypeDef *) AES_BASE)
1701#define RNG ((RNG_TypeDef *) RNG_BASE)
1702#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1703
1704
1705#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1706#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1707#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1708#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1709#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1710#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1711#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1712
1713
1714#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1715#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1716#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1717#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1718#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1719#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1720#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1721
1722#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
1723#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
1724#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
1725#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
1726#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
1727#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
1728#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
1729#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
1730#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
1731#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
1732#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
1733#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
1734#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
1735#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
1736
1737#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
1738#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
1739#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
1740#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
1741
1742#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
1743#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
1744
1745
1746#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1747#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1748#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1749
1750#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)
1751#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)
1752#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)
1753
1754#define GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE)
1755
1756#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1757
1758#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1759/**
1760 * @}
1761 */
1762
1763/** @addtogroup Exported_constants
1764 * @{
1765 */
1766
1767/** @addtogroup Peripheral_Registers_Bits_Definition
1768 * @{
1769 */
1770
1771/******************************************************************************/
1772/* Peripheral Registers_Bits_Definition */
1773/******************************************************************************/
1774
1775/******************************************************************************/
1776/* */
1777/* Analog to Digital Converter */
1778/* */
1779/******************************************************************************/
1780
1781/*
1782 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
1783 */
1784
1785/******************** Bit definition for ADC_ISR register *******************/
1786#define ADC_ISR_ADRDY_Pos (0U)
1787#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
1788#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
1789#define ADC_ISR_EOSMP_Pos (1U)
1790#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
1791#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
1792#define ADC_ISR_EOC_Pos (2U)
1793#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
1794#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
1795#define ADC_ISR_EOS_Pos (3U)
1796#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
1797#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
1798#define ADC_ISR_OVR_Pos (4U)
1799#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
1800#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
1801#define ADC_ISR_JEOC_Pos (5U)
1802#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
1803#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
1804#define ADC_ISR_JEOS_Pos (6U)
1805#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
1806#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
1807#define ADC_ISR_AWD1_Pos (7U)
1808#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
1809#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
1810#define ADC_ISR_AWD2_Pos (8U)
1811#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
1812#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
1813#define ADC_ISR_AWD3_Pos (9U)
1814#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
1815#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
1816#define ADC_ISR_JQOVF_Pos (10U)
1817#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
1818#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
1819
1820/******************** Bit definition for ADC_IER register *******************/
1821#define ADC_IER_ADRDYIE_Pos (0U)
1822#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
1823#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
1824#define ADC_IER_EOSMPIE_Pos (1U)
1825#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
1826#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
1827#define ADC_IER_EOCIE_Pos (2U)
1828#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
1829#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
1830#define ADC_IER_EOSIE_Pos (3U)
1831#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
1832#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
1833#define ADC_IER_OVRIE_Pos (4U)
1834#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
1835#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
1836#define ADC_IER_JEOCIE_Pos (5U)
1837#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
1838#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
1839#define ADC_IER_JEOSIE_Pos (6U)
1840#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
1841#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
1842#define ADC_IER_AWD1IE_Pos (7U)
1843#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
1844#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
1845#define ADC_IER_AWD2IE_Pos (8U)
1846#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
1847#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
1848#define ADC_IER_AWD3IE_Pos (9U)
1849#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
1850#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
1851#define ADC_IER_JQOVFIE_Pos (10U)
1852#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
1853#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
1854
1855/* Legacy defines */
1856#define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
1857#define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
1858#define ADC_IER_EOC (ADC_IER_EOCIE)
1859#define ADC_IER_EOS (ADC_IER_EOSIE)
1860#define ADC_IER_OVR (ADC_IER_OVRIE)
1861#define ADC_IER_JEOC (ADC_IER_JEOCIE)
1862#define ADC_IER_JEOS (ADC_IER_JEOSIE)
1863#define ADC_IER_AWD1 (ADC_IER_AWD1IE)
1864#define ADC_IER_AWD2 (ADC_IER_AWD2IE)
1865#define ADC_IER_AWD3 (ADC_IER_AWD3IE)
1866#define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
1867
1868/******************** Bit definition for ADC_CR register ********************/
1869#define ADC_CR_ADEN_Pos (0U)
1870#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
1871#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
1872#define ADC_CR_ADDIS_Pos (1U)
1873#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
1874#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
1875#define ADC_CR_ADSTART_Pos (2U)
1876#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
1877#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
1878#define ADC_CR_JADSTART_Pos (3U)
1879#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
1880#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
1881#define ADC_CR_ADSTP_Pos (4U)
1882#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
1883#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
1884#define ADC_CR_JADSTP_Pos (5U)
1885#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
1886#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
1887#define ADC_CR_ADVREGEN_Pos (28U)
1888#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
1889#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
1890#define ADC_CR_DEEPPWD_Pos (29U)
1891#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
1892#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
1893#define ADC_CR_ADCALDIF_Pos (30U)
1894#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
1895#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
1896#define ADC_CR_ADCAL_Pos (31U)
1897#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
1898#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
1899
1900/******************** Bit definition for ADC_CFGR register ******************/
1901#define ADC_CFGR_DMAEN_Pos (0U)
1902#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
1903#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
1904#define ADC_CFGR_DMACFG_Pos (1U)
1905#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
1906#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
1907
1908#define ADC_CFGR_DFSDMCFG_Pos (2U)
1909#define ADC_CFGR_DFSDMCFG_Msk (0x1U << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */
1910#define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk /*!< ADC DFSDM mode configuration */
1911
1912#define ADC_CFGR_RES_Pos (3U)
1913#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
1914#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
1915#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
1916#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
1917
1918#define ADC_CFGR_ALIGN_Pos (5U)
1919#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
1920#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1921
1922#define ADC_CFGR_EXTSEL_Pos (6U)
1923#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
1924#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
1925#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
1926#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
1927#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
1928#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
1929
1930#define ADC_CFGR_EXTEN_Pos (10U)
1931#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
1932#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
1933#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
1934#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
1935
1936#define ADC_CFGR_OVRMOD_Pos (12U)
1937#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
1938#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
1939#define ADC_CFGR_CONT_Pos (13U)
1940#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
1941#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
1942#define ADC_CFGR_AUTDLY_Pos (14U)
1943#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
1944#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
1945
1946#define ADC_CFGR_DISCEN_Pos (16U)
1947#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
1948#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
1949
1950#define ADC_CFGR_DISCNUM_Pos (17U)
1951#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
1952#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
1953#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
1954#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
1955#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
1956
1957#define ADC_CFGR_JDISCEN_Pos (20U)
1958#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
1959#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
1960#define ADC_CFGR_JQM_Pos (21U)
1961#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
1962#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
1963#define ADC_CFGR_AWD1SGL_Pos (22U)
1964#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
1965#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1966#define ADC_CFGR_AWD1EN_Pos (23U)
1967#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
1968#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1969#define ADC_CFGR_JAWD1EN_Pos (24U)
1970#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
1971#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1972#define ADC_CFGR_JAUTO_Pos (25U)
1973#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
1974#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
1975
1976#define ADC_CFGR_AWD1CH_Pos (26U)
1977#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
1978#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
1979#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
1980#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
1981#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
1982#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
1983#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
1984
1985#define ADC_CFGR_JQDIS_Pos (31U)
1986#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
1987#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
1988
1989/******************** Bit definition for ADC_CFGR2 register *****************/
1990#define ADC_CFGR2_ROVSE_Pos (0U)
1991#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
1992#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
1993#define ADC_CFGR2_JOVSE_Pos (1U)
1994#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
1995#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
1996
1997#define ADC_CFGR2_OVSR_Pos (2U)
1998#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
1999#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
2000#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
2001#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
2002#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
2003
2004#define ADC_CFGR2_OVSS_Pos (5U)
2005#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
2006#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
2007#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
2008#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
2009#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
2010#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
2011
2012#define ADC_CFGR2_TROVS_Pos (9U)
2013#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
2014#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
2015#define ADC_CFGR2_ROVSM_Pos (10U)
2016#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
2017#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
2018
2019/******************** Bit definition for ADC_SMPR1 register *****************/
2020#define ADC_SMPR1_SMP0_Pos (0U)
2021#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
2022#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
2023#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
2024#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
2025#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
2026
2027#define ADC_SMPR1_SMP1_Pos (3U)
2028#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
2029#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
2030#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
2031#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
2032#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
2033
2034#define ADC_SMPR1_SMP2_Pos (6U)
2035#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
2036#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
2037#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
2038#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
2039#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
2040
2041#define ADC_SMPR1_SMP3_Pos (9U)
2042#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
2043#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
2044#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
2045#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
2046#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
2047
2048#define ADC_SMPR1_SMP4_Pos (12U)
2049#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
2050#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
2051#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
2052#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
2053#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
2054
2055#define ADC_SMPR1_SMP5_Pos (15U)
2056#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
2057#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
2058#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
2059#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
2060#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
2061
2062#define ADC_SMPR1_SMP6_Pos (18U)
2063#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
2064#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
2065#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
2066#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
2067#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
2068
2069#define ADC_SMPR1_SMP7_Pos (21U)
2070#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
2071#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
2072#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
2073#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
2074#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
2075
2076#define ADC_SMPR1_SMP8_Pos (24U)
2077#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
2078#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
2079#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
2080#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
2081#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
2082
2083#define ADC_SMPR1_SMP9_Pos (27U)
2084#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
2085#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
2086#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
2087#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
2088#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
2089
2090#define ADC_SMPR1_SMPPLUS_Pos (31U)
2091#define ADC_SMPR1_SMPPLUS_Msk (0x1U << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
2092#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
2093
2094/******************** Bit definition for ADC_SMPR2 register *****************/
2095#define ADC_SMPR2_SMP10_Pos (0U)
2096#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
2097#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
2098#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
2099#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
2100#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
2101
2102#define ADC_SMPR2_SMP11_Pos (3U)
2103#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
2104#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
2105#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
2106#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
2107#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
2108
2109#define ADC_SMPR2_SMP12_Pos (6U)
2110#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
2111#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
2112#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
2113#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
2114#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
2115
2116#define ADC_SMPR2_SMP13_Pos (9U)
2117#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
2118#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
2119#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
2120#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
2121#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
2122
2123#define ADC_SMPR2_SMP14_Pos (12U)
2124#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
2125#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
2126#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
2127#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
2128#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
2129
2130#define ADC_SMPR2_SMP15_Pos (15U)
2131#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
2132#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
2133#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
2134#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
2135#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
2136
2137#define ADC_SMPR2_SMP16_Pos (18U)
2138#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
2139#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
2140#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
2141#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
2142#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
2143
2144#define ADC_SMPR2_SMP17_Pos (21U)
2145#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
2146#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
2147#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
2148#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
2149#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
2150
2151#define ADC_SMPR2_SMP18_Pos (24U)
2152#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
2153#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
2154#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
2155#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
2156#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
2157
2158/******************** Bit definition for ADC_TR1 register *******************/
2159#define ADC_TR1_LT1_Pos (0U)
2160#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
2161#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
2162#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
2163#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
2164#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
2165#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
2166#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
2167#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
2168#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
2169#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
2170#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
2171#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
2172#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
2173#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
2174
2175#define ADC_TR1_HT1_Pos (16U)
2176#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
2177#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
2178#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
2179#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
2180#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
2181#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
2182#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
2183#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
2184#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
2185#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
2186#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
2187#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
2188#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
2189#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
2190
2191/******************** Bit definition for ADC_TR2 register *******************/
2192#define ADC_TR2_LT2_Pos (0U)
2193#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
2194#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
2195#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
2196#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
2197#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
2198#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
2199#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
2200#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
2201#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
2202#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
2203
2204#define ADC_TR2_HT2_Pos (16U)
2205#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
2206#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
2207#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
2208#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
2209#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
2210#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
2211#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
2212#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
2213#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
2214#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
2215
2216/******************** Bit definition for ADC_TR3 register *******************/
2217#define ADC_TR3_LT3_Pos (0U)
2218#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
2219#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
2220#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
2221#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
2222#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
2223#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
2224#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
2225#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
2226#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
2227#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
2228
2229#define ADC_TR3_HT3_Pos (16U)
2230#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
2231#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
2232#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
2233#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
2234#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
2235#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
2236#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
2237#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
2238#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
2239#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
2240
2241/******************** Bit definition for ADC_SQR1 register ******************/
2242#define ADC_SQR1_L_Pos (0U)
2243#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
2244#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
2245#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
2246#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
2247#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
2248#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
2249
2250#define ADC_SQR1_SQ1_Pos (6U)
2251#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
2252#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
2253#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
2254#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
2255#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
2256#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
2257#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
2258
2259#define ADC_SQR1_SQ2_Pos (12U)
2260#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
2261#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
2262#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
2263#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
2264#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
2265#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
2266#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
2267
2268#define ADC_SQR1_SQ3_Pos (18U)
2269#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
2270#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
2271#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
2272#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
2273#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
2274#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
2275#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
2276
2277#define ADC_SQR1_SQ4_Pos (24U)
2278#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
2279#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
2280#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
2281#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
2282#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
2283#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
2284#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
2285
2286/******************** Bit definition for ADC_SQR2 register ******************/
2287#define ADC_SQR2_SQ5_Pos (0U)
2288#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
2289#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
2290#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
2291#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
2292#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
2293#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
2294#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
2295
2296#define ADC_SQR2_SQ6_Pos (6U)
2297#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
2298#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
2299#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
2300#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
2301#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
2302#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
2303#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
2304
2305#define ADC_SQR2_SQ7_Pos (12U)
2306#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
2307#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
2308#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
2309#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
2310#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
2311#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
2312#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
2313
2314#define ADC_SQR2_SQ8_Pos (18U)
2315#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
2316#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
2317#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
2318#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
2319#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
2320#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
2321#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
2322
2323#define ADC_SQR2_SQ9_Pos (24U)
2324#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
2325#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
2326#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
2327#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
2328#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
2329#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
2330#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
2331
2332/******************** Bit definition for ADC_SQR3 register ******************/
2333#define ADC_SQR3_SQ10_Pos (0U)
2334#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
2335#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
2336#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
2337#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
2338#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
2339#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
2340#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
2341
2342#define ADC_SQR3_SQ11_Pos (6U)
2343#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
2344#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
2345#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
2346#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
2347#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
2348#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
2349#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
2350
2351#define ADC_SQR3_SQ12_Pos (12U)
2352#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
2353#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
2354#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
2355#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
2356#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
2357#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
2358#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
2359
2360#define ADC_SQR3_SQ13_Pos (18U)
2361#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
2362#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
2363#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
2364#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
2365#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
2366#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
2367#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
2368
2369#define ADC_SQR3_SQ14_Pos (24U)
2370#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
2371#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
2372#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
2373#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
2374#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
2375#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
2376#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
2377
2378/******************** Bit definition for ADC_SQR4 register ******************/
2379#define ADC_SQR4_SQ15_Pos (0U)
2380#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
2381#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
2382#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
2383#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
2384#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
2385#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
2386#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
2387
2388#define ADC_SQR4_SQ16_Pos (6U)
2389#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
2390#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
2391#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
2392#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
2393#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
2394#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
2395#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
2396
2397/******************** Bit definition for ADC_DR register ********************/
2398#define ADC_DR_RDATA_Pos (0U)
2399#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
2400#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
2401#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
2402#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
2403#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
2404#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
2405#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
2406#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
2407#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
2408#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
2409#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
2410#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
2411#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
2412#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
2413#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
2414#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
2415#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
2416#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
2417
2418/******************** Bit definition for ADC_JSQR register ******************/
2419#define ADC_JSQR_JL_Pos (0U)
2420#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
2421#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
2422#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
2423#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
2424
2425#define ADC_JSQR_JEXTSEL_Pos (2U)
2426#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
2427#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
2428#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
2429#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
2430#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
2431#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
2432
2433#define ADC_JSQR_JEXTEN_Pos (6U)
2434#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
2435#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
2436#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
2437#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
2438
2439#define ADC_JSQR_JSQ1_Pos (8U)
2440#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
2441#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
2442#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
2443#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
2444#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
2445#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
2446#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
2447
2448#define ADC_JSQR_JSQ2_Pos (14U)
2449#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
2450#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
2451#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
2452#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
2453#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
2454#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
2455#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
2456
2457#define ADC_JSQR_JSQ3_Pos (20U)
2458#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
2459#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
2460#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
2461#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
2462#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
2463#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
2464#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
2465
2466#define ADC_JSQR_JSQ4_Pos (26U)
2467#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
2468#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
2469#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
2470#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
2471#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
2472#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
2473#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
2474
2475/******************** Bit definition for ADC_OFR1 register ******************/
2476#define ADC_OFR1_OFFSET1_Pos (0U)
2477#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
2478#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
2479#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
2480#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
2481#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
2482#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
2483#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
2484#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
2485#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
2486#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
2487#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
2488#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
2489#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
2490#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
2491
2492#define ADC_OFR1_OFFSET1_CH_Pos (26U)
2493#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
2494#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
2495#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
2496#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
2497#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
2498#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
2499#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
2500
2501#define ADC_OFR1_OFFSET1_EN_Pos (31U)
2502#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
2503#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
2504
2505/******************** Bit definition for ADC_OFR2 register ******************/
2506#define ADC_OFR2_OFFSET2_Pos (0U)
2507#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
2508#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
2509#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
2510#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
2511#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
2512#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
2513#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
2514#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
2515#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
2516#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
2517#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
2518#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
2519#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
2520#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
2521
2522#define ADC_OFR2_OFFSET2_CH_Pos (26U)
2523#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
2524#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
2525#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
2526#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
2527#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
2528#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
2529#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
2530
2531#define ADC_OFR2_OFFSET2_EN_Pos (31U)
2532#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
2533#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
2534
2535/******************** Bit definition for ADC_OFR3 register ******************/
2536#define ADC_OFR3_OFFSET3_Pos (0U)
2537#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
2538#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
2539#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
2540#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
2541#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
2542#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
2543#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
2544#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
2545#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
2546#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
2547#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
2548#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
2549#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
2550#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
2551
2552#define ADC_OFR3_OFFSET3_CH_Pos (26U)
2553#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
2554#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
2555#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
2556#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
2557#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
2558#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
2559#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
2560
2561#define ADC_OFR3_OFFSET3_EN_Pos (31U)
2562#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
2563#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
2564
2565/******************** Bit definition for ADC_OFR4 register ******************/
2566#define ADC_OFR4_OFFSET4_Pos (0U)
2567#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
2568#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
2569#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
2570#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
2571#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
2572#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
2573#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
2574#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
2575#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
2576#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
2577#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
2578#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
2579#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
2580#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
2581
2582#define ADC_OFR4_OFFSET4_CH_Pos (26U)
2583#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
2584#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
2585#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
2586#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
2587#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
2588#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
2589#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
2590
2591#define ADC_OFR4_OFFSET4_EN_Pos (31U)
2592#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
2593#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
2594
2595/******************** Bit definition for ADC_JDR1 register ******************/
2596#define ADC_JDR1_JDATA_Pos (0U)
2597#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
2598#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
2599#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
2600#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
2601#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
2602#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
2603#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
2604#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
2605#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
2606#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
2607#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
2608#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
2609#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
2610#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
2611#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
2612#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
2613#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
2614#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
2615
2616/******************** Bit definition for ADC_JDR2 register ******************/
2617#define ADC_JDR2_JDATA_Pos (0U)
2618#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
2619#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
2620#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
2621#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
2622#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
2623#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
2624#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
2625#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
2626#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
2627#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
2628#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
2629#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
2630#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
2631#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
2632#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
2633#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
2634#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
2635#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
2636
2637/******************** Bit definition for ADC_JDR3 register ******************/
2638#define ADC_JDR3_JDATA_Pos (0U)
2639#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
2640#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
2641#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
2642#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
2643#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
2644#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
2645#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
2646#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
2647#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
2648#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
2649#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
2650#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
2651#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
2652#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
2653#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
2654#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
2655#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
2656#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
2657
2658/******************** Bit definition for ADC_JDR4 register ******************/
2659#define ADC_JDR4_JDATA_Pos (0U)
2660#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
2661#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
2662#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
2663#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
2664#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
2665#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
2666#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
2667#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
2668#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
2669#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
2670#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
2671#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
2672#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
2673#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
2674#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
2675#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
2676#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
2677#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
2678
2679/******************** Bit definition for ADC_AWD2CR register ****************/
2680#define ADC_AWD2CR_AWD2CH_Pos (0U)
2681#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
2682#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
2683#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
2684#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
2685#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
2686#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
2687#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
2688#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
2689#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
2690#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
2691#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
2692#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
2693#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
2694#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
2695#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
2696#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
2697#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
2698#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
2699#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
2700#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
2701#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
2702
2703/******************** Bit definition for ADC_AWD3CR register ****************/
2704#define ADC_AWD3CR_AWD3CH_Pos (0U)
2705#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
2706#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
2707#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
2708#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
2709#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
2710#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
2711#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
2712#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
2713#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
2714#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
2715#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
2716#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
2717#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
2718#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
2719#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
2720#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
2721#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
2722#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
2723#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
2724#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
2725#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
2726
2727/******************** Bit definition for ADC_DIFSEL register ****************/
2728#define ADC_DIFSEL_DIFSEL_Pos (0U)
2729#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
2730#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
2731#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
2732#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
2733#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
2734#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
2735#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
2736#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
2737#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
2738#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
2739#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
2740#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
2741#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
2742#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
2743#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
2744#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
2745#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
2746#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
2747#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
2748#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
2749#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
2750
2751/******************** Bit definition for ADC_CALFACT register ***************/
2752#define ADC_CALFACT_CALFACT_S_Pos (0U)
2753#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
2754#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
2755#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
2756#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
2757#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
2758#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
2759#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
2760#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
2761#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
2762
2763#define ADC_CALFACT_CALFACT_D_Pos (16U)
2764#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
2765#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
2766#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
2767#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
2768#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
2769#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
2770#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
2771#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
2772#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
2773
2774/************************* ADC Common registers *****************************/
2775/******************** Bit definition for ADC_CCR register *******************/
2776#define ADC_CCR_CKMODE_Pos (16U)
2777#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
2778#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2779#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
2780#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
2781
2782#define ADC_CCR_PRESC_Pos (18U)
2783#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
2784#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
2785#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
2786#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
2787#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
2788#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
2789
2790#define ADC_CCR_VREFEN_Pos (22U)
2791#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
2792#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
2793#define ADC_CCR_TSEN_Pos (23U)
2794#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
2795#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
2796#define ADC_CCR_VBATEN_Pos (24U)
2797#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
2798#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
2799
2800/******************************************************************************/
2801/* */
2802/* Controller Area Network */
2803/* */
2804/******************************************************************************/
2805/*!<CAN control and status registers */
2806/******************* Bit definition for CAN_MCR register ********************/
2807#define CAN_MCR_INRQ_Pos (0U)
2808#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
2809#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
2810#define CAN_MCR_SLEEP_Pos (1U)
2811#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
2812#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
2813#define CAN_MCR_TXFP_Pos (2U)
2814#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
2815#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
2816#define CAN_MCR_RFLM_Pos (3U)
2817#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
2818#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
2819#define CAN_MCR_NART_Pos (4U)
2820#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
2821#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
2822#define CAN_MCR_AWUM_Pos (5U)
2823#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
2824#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
2825#define CAN_MCR_ABOM_Pos (6U)
2826#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
2827#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
2828#define CAN_MCR_TTCM_Pos (7U)
2829#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
2830#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
2831#define CAN_MCR_RESET_Pos (15U)
2832#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
2833#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
2834
2835/******************* Bit definition for CAN_MSR register ********************/
2836#define CAN_MSR_INAK_Pos (0U)
2837#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
2838#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
2839#define CAN_MSR_SLAK_Pos (1U)
2840#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
2841#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
2842#define CAN_MSR_ERRI_Pos (2U)
2843#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
2844#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
2845#define CAN_MSR_WKUI_Pos (3U)
2846#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
2847#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
2848#define CAN_MSR_SLAKI_Pos (4U)
2849#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
2850#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
2851#define CAN_MSR_TXM_Pos (8U)
2852#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
2853#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
2854#define CAN_MSR_RXM_Pos (9U)
2855#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
2856#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
2857#define CAN_MSR_SAMP_Pos (10U)
2858#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
2859#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
2860#define CAN_MSR_RX_Pos (11U)
2861#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
2862#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
2863
2864/******************* Bit definition for CAN_TSR register ********************/
2865#define CAN_TSR_RQCP0_Pos (0U)
2866#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
2867#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
2868#define CAN_TSR_TXOK0_Pos (1U)
2869#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
2870#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
2871#define CAN_TSR_ALST0_Pos (2U)
2872#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
2873#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
2874#define CAN_TSR_TERR0_Pos (3U)
2875#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
2876#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
2877#define CAN_TSR_ABRQ0_Pos (7U)
2878#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
2879#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
2880#define CAN_TSR_RQCP1_Pos (8U)
2881#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
2882#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
2883#define CAN_TSR_TXOK1_Pos (9U)
2884#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
2885#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
2886#define CAN_TSR_ALST1_Pos (10U)
2887#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
2888#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
2889#define CAN_TSR_TERR1_Pos (11U)
2890#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
2891#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
2892#define CAN_TSR_ABRQ1_Pos (15U)
2893#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
2894#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
2895#define CAN_TSR_RQCP2_Pos (16U)
2896#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
2897#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
2898#define CAN_TSR_TXOK2_Pos (17U)
2899#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
2900#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
2901#define CAN_TSR_ALST2_Pos (18U)
2902#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
2903#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
2904#define CAN_TSR_TERR2_Pos (19U)
2905#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
2906#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
2907#define CAN_TSR_ABRQ2_Pos (23U)
2908#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
2909#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
2910#define CAN_TSR_CODE_Pos (24U)
2911#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
2912#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
2913
2914#define CAN_TSR_TME_Pos (26U)
2915#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
2916#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
2917#define CAN_TSR_TME0_Pos (26U)
2918#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
2919#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
2920#define CAN_TSR_TME1_Pos (27U)
2921#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
2922#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
2923#define CAN_TSR_TME2_Pos (28U)
2924#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
2925#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
2926
2927#define CAN_TSR_LOW_Pos (29U)
2928#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
2929#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
2930#define CAN_TSR_LOW0_Pos (29U)
2931#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
2932#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
2933#define CAN_TSR_LOW1_Pos (30U)
2934#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
2935#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
2936#define CAN_TSR_LOW2_Pos (31U)
2937#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
2938#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
2939
2940/******************* Bit definition for CAN_RF0R register *******************/
2941#define CAN_RF0R_FMP0_Pos (0U)
2942#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
2943#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
2944#define CAN_RF0R_FULL0_Pos (3U)
2945#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
2946#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
2947#define CAN_RF0R_FOVR0_Pos (4U)
2948#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
2949#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
2950#define CAN_RF0R_RFOM0_Pos (5U)
2951#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
2952#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
2953
2954/******************* Bit definition for CAN_RF1R register *******************/
2955#define CAN_RF1R_FMP1_Pos (0U)
2956#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
2957#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
2958#define CAN_RF1R_FULL1_Pos (3U)
2959#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
2960#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
2961#define CAN_RF1R_FOVR1_Pos (4U)
2962#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
2963#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
2964#define CAN_RF1R_RFOM1_Pos (5U)
2965#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
2966#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
2967
2968/******************** Bit definition for CAN_IER register *******************/
2969#define CAN_IER_TMEIE_Pos (0U)
2970#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
2971#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
2972#define CAN_IER_FMPIE0_Pos (1U)
2973#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
2974#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
2975#define CAN_IER_FFIE0_Pos (2U)
2976#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
2977#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
2978#define CAN_IER_FOVIE0_Pos (3U)
2979#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
2980#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2981#define CAN_IER_FMPIE1_Pos (4U)
2982#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2983#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2984#define CAN_IER_FFIE1_Pos (5U)
2985#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2986#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2987#define CAN_IER_FOVIE1_Pos (6U)
2988#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2989#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2990#define CAN_IER_EWGIE_Pos (8U)
2991#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2992#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2993#define CAN_IER_EPVIE_Pos (9U)
2994#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2995#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2996#define CAN_IER_BOFIE_Pos (10U)
2997#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2998#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2999#define CAN_IER_LECIE_Pos (11U)
3000#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
3001#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
3002#define CAN_IER_ERRIE_Pos (15U)
3003#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
3004#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
3005#define CAN_IER_WKUIE_Pos (16U)
3006#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
3007#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
3008#define CAN_IER_SLKIE_Pos (17U)
3009#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
3010#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
3011
3012/******************** Bit definition for CAN_ESR register *******************/
3013#define CAN_ESR_EWGF_Pos (0U)
3014#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
3015#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
3016#define CAN_ESR_EPVF_Pos (1U)
3017#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
3018#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
3019#define CAN_ESR_BOFF_Pos (2U)
3020#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
3021#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
3022
3023#define CAN_ESR_LEC_Pos (4U)
3024#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
3025#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
3026#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
3027#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
3028#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
3029
3030#define CAN_ESR_TEC_Pos (16U)
3031#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
3032#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
3033#define CAN_ESR_REC_Pos (24U)
3034#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
3035#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
3036
3037/******************* Bit definition for CAN_BTR register ********************/
3038#define CAN_BTR_BRP_Pos (0U)
3039#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
3040#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
3041#define CAN_BTR_TS1_Pos (16U)
3042#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
3043#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
3044#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
3045#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
3046#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
3047#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
3048#define CAN_BTR_TS2_Pos (20U)
3049#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
3050#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
3051#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
3052#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
3053#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
3054#define CAN_BTR_SJW_Pos (24U)
3055#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
3056#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
3057#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
3058#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
3059#define CAN_BTR_LBKM_Pos (30U)
3060#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
3061#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
3062#define CAN_BTR_SILM_Pos (31U)
3063#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
3064#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
3065
3066/*!<Mailbox registers */
3067/****************** Bit definition for CAN_TI0R register ********************/
3068#define CAN_TI0R_TXRQ_Pos (0U)
3069#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
3070#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
3071#define CAN_TI0R_RTR_Pos (1U)
3072#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
3073#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
3074#define CAN_TI0R_IDE_Pos (2U)
3075#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
3076#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
3077#define CAN_TI0R_EXID_Pos (3U)
3078#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
3079#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
3080#define CAN_TI0R_STID_Pos (21U)
3081#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
3082#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3083
3084/****************** Bit definition for CAN_TDT0R register *******************/
3085#define CAN_TDT0R_DLC_Pos (0U)
3086#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
3087#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
3088#define CAN_TDT0R_TGT_Pos (8U)
3089#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
3090#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
3091#define CAN_TDT0R_TIME_Pos (16U)
3092#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
3093#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
3094
3095/****************** Bit definition for CAN_TDL0R register *******************/
3096#define CAN_TDL0R_DATA0_Pos (0U)
3097#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
3098#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
3099#define CAN_TDL0R_DATA1_Pos (8U)
3100#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
3101#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
3102#define CAN_TDL0R_DATA2_Pos (16U)
3103#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
3104#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
3105#define CAN_TDL0R_DATA3_Pos (24U)
3106#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
3107#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
3108
3109/****************** Bit definition for CAN_TDH0R register *******************/
3110#define CAN_TDH0R_DATA4_Pos (0U)
3111#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
3112#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
3113#define CAN_TDH0R_DATA5_Pos (8U)
3114#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
3115#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
3116#define CAN_TDH0R_DATA6_Pos (16U)
3117#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
3118#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
3119#define CAN_TDH0R_DATA7_Pos (24U)
3120#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
3121#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
3122
3123/******************* Bit definition for CAN_TI1R register *******************/
3124#define CAN_TI1R_TXRQ_Pos (0U)
3125#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
3126#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
3127#define CAN_TI1R_RTR_Pos (1U)
3128#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
3129#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
3130#define CAN_TI1R_IDE_Pos (2U)
3131#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
3132#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
3133#define CAN_TI1R_EXID_Pos (3U)
3134#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
3135#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
3136#define CAN_TI1R_STID_Pos (21U)
3137#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
3138#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3139
3140/******************* Bit definition for CAN_TDT1R register ******************/
3141#define CAN_TDT1R_DLC_Pos (0U)
3142#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
3143#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
3144#define CAN_TDT1R_TGT_Pos (8U)
3145#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
3146#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
3147#define CAN_TDT1R_TIME_Pos (16U)
3148#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
3149#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
3150
3151/******************* Bit definition for CAN_TDL1R register ******************/
3152#define CAN_TDL1R_DATA0_Pos (0U)
3153#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
3154#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
3155#define CAN_TDL1R_DATA1_Pos (8U)
3156#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
3157#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
3158#define CAN_TDL1R_DATA2_Pos (16U)
3159#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
3160#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
3161#define CAN_TDL1R_DATA3_Pos (24U)
3162#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
3163#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
3164
3165/******************* Bit definition for CAN_TDH1R register ******************/
3166#define CAN_TDH1R_DATA4_Pos (0U)
3167#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
3168#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
3169#define CAN_TDH1R_DATA5_Pos (8U)
3170#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
3171#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
3172#define CAN_TDH1R_DATA6_Pos (16U)
3173#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
3174#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
3175#define CAN_TDH1R_DATA7_Pos (24U)
3176#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
3177#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
3178
3179/******************* Bit definition for CAN_TI2R register *******************/
3180#define CAN_TI2R_TXRQ_Pos (0U)
3181#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
3182#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
3183#define CAN_TI2R_RTR_Pos (1U)
3184#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
3185#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
3186#define CAN_TI2R_IDE_Pos (2U)
3187#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
3188#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
3189#define CAN_TI2R_EXID_Pos (3U)
3190#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
3191#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
3192#define CAN_TI2R_STID_Pos (21U)
3193#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
3194#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3195
3196/******************* Bit definition for CAN_TDT2R register ******************/
3197#define CAN_TDT2R_DLC_Pos (0U)
3198#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
3199#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
3200#define CAN_TDT2R_TGT_Pos (8U)
3201#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
3202#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
3203#define CAN_TDT2R_TIME_Pos (16U)
3204#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
3205#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
3206
3207/******************* Bit definition for CAN_TDL2R register ******************/
3208#define CAN_TDL2R_DATA0_Pos (0U)
3209#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
3210#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
3211#define CAN_TDL2R_DATA1_Pos (8U)
3212#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
3213#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
3214#define CAN_TDL2R_DATA2_Pos (16U)
3215#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
3216#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
3217#define CAN_TDL2R_DATA3_Pos (24U)
3218#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
3219#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
3220
3221/******************* Bit definition for CAN_TDH2R register ******************/
3222#define CAN_TDH2R_DATA4_Pos (0U)
3223#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
3224#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
3225#define CAN_TDH2R_DATA5_Pos (8U)
3226#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
3227#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
3228#define CAN_TDH2R_DATA6_Pos (16U)
3229#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
3230#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
3231#define CAN_TDH2R_DATA7_Pos (24U)
3232#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
3233#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
3234
3235/******************* Bit definition for CAN_RI0R register *******************/
3236#define CAN_RI0R_RTR_Pos (1U)
3237#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
3238#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
3239#define CAN_RI0R_IDE_Pos (2U)
3240#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
3241#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
3242#define CAN_RI0R_EXID_Pos (3U)
3243#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
3244#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
3245#define CAN_RI0R_STID_Pos (21U)
3246#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
3247#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3248
3249/******************* Bit definition for CAN_RDT0R register ******************/
3250#define CAN_RDT0R_DLC_Pos (0U)
3251#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
3252#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
3253#define CAN_RDT0R_FMI_Pos (8U)
3254#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
3255#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
3256#define CAN_RDT0R_TIME_Pos (16U)
3257#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
3258#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
3259
3260/******************* Bit definition for CAN_RDL0R register ******************/
3261#define CAN_RDL0R_DATA0_Pos (0U)
3262#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
3263#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
3264#define CAN_RDL0R_DATA1_Pos (8U)
3265#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
3266#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
3267#define CAN_RDL0R_DATA2_Pos (16U)
3268#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
3269#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
3270#define CAN_RDL0R_DATA3_Pos (24U)
3271#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
3272#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
3273
3274/******************* Bit definition for CAN_RDH0R register ******************/
3275#define CAN_RDH0R_DATA4_Pos (0U)
3276#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
3277#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
3278#define CAN_RDH0R_DATA5_Pos (8U)
3279#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
3280#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
3281#define CAN_RDH0R_DATA6_Pos (16U)
3282#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
3283#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
3284#define CAN_RDH0R_DATA7_Pos (24U)
3285#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
3286#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
3287
3288/******************* Bit definition for CAN_RI1R register *******************/
3289#define CAN_RI1R_RTR_Pos (1U)
3290#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
3291#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
3292#define CAN_RI1R_IDE_Pos (2U)
3293#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
3294#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
3295#define CAN_RI1R_EXID_Pos (3U)
3296#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
3297#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
3298#define CAN_RI1R_STID_Pos (21U)
3299#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
3300#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3301
3302/******************* Bit definition for CAN_RDT1R register ******************/
3303#define CAN_RDT1R_DLC_Pos (0U)
3304#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
3305#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
3306#define CAN_RDT1R_FMI_Pos (8U)
3307#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
3308#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
3309#define CAN_RDT1R_TIME_Pos (16U)
3310#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
3311#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
3312
3313/******************* Bit definition for CAN_RDL1R register ******************/
3314#define CAN_RDL1R_DATA0_Pos (0U)
3315#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
3316#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
3317#define CAN_RDL1R_DATA1_Pos (8U)
3318#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
3319#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
3320#define CAN_RDL1R_DATA2_Pos (16U)
3321#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
3322#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
3323#define CAN_RDL1R_DATA3_Pos (24U)
3324#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
3325#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
3326
3327/******************* Bit definition for CAN_RDH1R register ******************/
3328#define CAN_RDH1R_DATA4_Pos (0U)
3329#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
3330#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
3331#define CAN_RDH1R_DATA5_Pos (8U)
3332#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
3333#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
3334#define CAN_RDH1R_DATA6_Pos (16U)
3335#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
3336#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
3337#define CAN_RDH1R_DATA7_Pos (24U)
3338#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
3339#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
3340
3341/*!<CAN filter registers */
3342/******************* Bit definition for CAN_FMR register ********************/
3343#define CAN_FMR_FINIT_Pos (0U)
3344#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
3345#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
3346
3347/******************* Bit definition for CAN_FM1R register *******************/
3348#define CAN_FM1R_FBM_Pos (0U)
3349#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
3350#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
3351#define CAN_FM1R_FBM0_Pos (0U)
3352#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
3353#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
3354#define CAN_FM1R_FBM1_Pos (1U)
3355#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
3356#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
3357#define CAN_FM1R_FBM2_Pos (2U)
3358#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
3359#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
3360#define CAN_FM1R_FBM3_Pos (3U)
3361#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
3362#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
3363#define CAN_FM1R_FBM4_Pos (4U)
3364#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
3365#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
3366#define CAN_FM1R_FBM5_Pos (5U)
3367#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
3368#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
3369#define CAN_FM1R_FBM6_Pos (6U)
3370#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
3371#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
3372#define CAN_FM1R_FBM7_Pos (7U)
3373#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
3374#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
3375#define CAN_FM1R_FBM8_Pos (8U)
3376#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
3377#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
3378#define CAN_FM1R_FBM9_Pos (9U)
3379#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
3380#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
3381#define CAN_FM1R_FBM10_Pos (10U)
3382#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
3383#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
3384#define CAN_FM1R_FBM11_Pos (11U)
3385#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
3386#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
3387#define CAN_FM1R_FBM12_Pos (12U)
3388#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
3389#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
3390#define CAN_FM1R_FBM13_Pos (13U)
3391#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
3392#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
3393
3394/******************* Bit definition for CAN_FS1R register *******************/
3395#define CAN_FS1R_FSC_Pos (0U)
3396#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
3397#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
3398#define CAN_FS1R_FSC0_Pos (0U)
3399#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
3400#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
3401#define CAN_FS1R_FSC1_Pos (1U)
3402#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
3403#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
3404#define CAN_FS1R_FSC2_Pos (2U)
3405#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
3406#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
3407#define CAN_FS1R_FSC3_Pos (3U)
3408#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
3409#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
3410#define CAN_FS1R_FSC4_Pos (4U)
3411#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
3412#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
3413#define CAN_FS1R_FSC5_Pos (5U)
3414#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
3415#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
3416#define CAN_FS1R_FSC6_Pos (6U)
3417#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
3418#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
3419#define CAN_FS1R_FSC7_Pos (7U)
3420#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
3421#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
3422#define CAN_FS1R_FSC8_Pos (8U)
3423#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
3424#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
3425#define CAN_FS1R_FSC9_Pos (9U)
3426#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
3427#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
3428#define CAN_FS1R_FSC10_Pos (10U)
3429#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
3430#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
3431#define CAN_FS1R_FSC11_Pos (11U)
3432#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
3433#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
3434#define CAN_FS1R_FSC12_Pos (12U)
3435#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
3436#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
3437#define CAN_FS1R_FSC13_Pos (13U)
3438#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
3439#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
3440
3441/****************** Bit definition for CAN_FFA1R register *******************/
3442#define CAN_FFA1R_FFA_Pos (0U)
3443#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
3444#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
3445#define CAN_FFA1R_FFA0_Pos (0U)
3446#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
3447#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
3448#define CAN_FFA1R_FFA1_Pos (1U)
3449#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
3450#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
3451#define CAN_FFA1R_FFA2_Pos (2U)
3452#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
3453#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
3454#define CAN_FFA1R_FFA3_Pos (3U)
3455#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
3456#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
3457#define CAN_FFA1R_FFA4_Pos (4U)
3458#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
3459#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
3460#define CAN_FFA1R_FFA5_Pos (5U)
3461#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
3462#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
3463#define CAN_FFA1R_FFA6_Pos (6U)
3464#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
3465#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
3466#define CAN_FFA1R_FFA7_Pos (7U)
3467#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
3468#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
3469#define CAN_FFA1R_FFA8_Pos (8U)
3470#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
3471#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
3472#define CAN_FFA1R_FFA9_Pos (9U)
3473#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
3474#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
3475#define CAN_FFA1R_FFA10_Pos (10U)
3476#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
3477#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
3478#define CAN_FFA1R_FFA11_Pos (11U)
3479#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
3480#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
3481#define CAN_FFA1R_FFA12_Pos (12U)
3482#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
3483#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
3484#define CAN_FFA1R_FFA13_Pos (13U)
3485#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
3486#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
3487
3488/******************* Bit definition for CAN_FA1R register *******************/
3489#define CAN_FA1R_FACT_Pos (0U)
3490#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
3491#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
3492#define CAN_FA1R_FACT0_Pos (0U)
3493#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
3494#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
3495#define CAN_FA1R_FACT1_Pos (1U)
3496#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
3497#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
3498#define CAN_FA1R_FACT2_Pos (2U)
3499#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
3500#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
3501#define CAN_FA1R_FACT3_Pos (3U)
3502#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
3503#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
3504#define CAN_FA1R_FACT4_Pos (4U)
3505#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
3506#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
3507#define CAN_FA1R_FACT5_Pos (5U)
3508#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
3509#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
3510#define CAN_FA1R_FACT6_Pos (6U)
3511#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
3512#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
3513#define CAN_FA1R_FACT7_Pos (7U)
3514#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
3515#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
3516#define CAN_FA1R_FACT8_Pos (8U)
3517#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
3518#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
3519#define CAN_FA1R_FACT9_Pos (9U)
3520#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
3521#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
3522#define CAN_FA1R_FACT10_Pos (10U)
3523#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
3524#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
3525#define CAN_FA1R_FACT11_Pos (11U)
3526#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
3527#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
3528#define CAN_FA1R_FACT12_Pos (12U)
3529#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
3530#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
3531#define CAN_FA1R_FACT13_Pos (13U)
3532#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
3533#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
3534
3535/******************* Bit definition for CAN_F0R1 register *******************/
3536#define CAN_F0R1_FB0_Pos (0U)
3537#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
3538#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
3539#define CAN_F0R1_FB1_Pos (1U)
3540#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
3541#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
3542#define CAN_F0R1_FB2_Pos (2U)
3543#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
3544#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
3545#define CAN_F0R1_FB3_Pos (3U)
3546#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
3547#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
3548#define CAN_F0R1_FB4_Pos (4U)
3549#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
3550#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
3551#define CAN_F0R1_FB5_Pos (5U)
3552#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
3553#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
3554#define CAN_F0R1_FB6_Pos (6U)
3555#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
3556#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
3557#define CAN_F0R1_FB7_Pos (7U)
3558#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
3559#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
3560#define CAN_F0R1_FB8_Pos (8U)
3561#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
3562#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
3563#define CAN_F0R1_FB9_Pos (9U)
3564#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
3565#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
3566#define CAN_F0R1_FB10_Pos (10U)
3567#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
3568#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
3569#define CAN_F0R1_FB11_Pos (11U)
3570#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
3571#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
3572#define CAN_F0R1_FB12_Pos (12U)
3573#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
3574#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
3575#define CAN_F0R1_FB13_Pos (13U)
3576#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
3577#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
3578#define CAN_F0R1_FB14_Pos (14U)
3579#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
3580#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
3581#define CAN_F0R1_FB15_Pos (15U)
3582#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
3583#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
3584#define CAN_F0R1_FB16_Pos (16U)
3585#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
3586#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
3587#define CAN_F0R1_FB17_Pos (17U)
3588#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
3589#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
3590#define CAN_F0R1_FB18_Pos (18U)
3591#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
3592#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
3593#define CAN_F0R1_FB19_Pos (19U)
3594#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
3595#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
3596#define CAN_F0R1_FB20_Pos (20U)
3597#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
3598#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
3599#define CAN_F0R1_FB21_Pos (21U)
3600#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
3601#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
3602#define CAN_F0R1_FB22_Pos (22U)
3603#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
3604#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
3605#define CAN_F0R1_FB23_Pos (23U)
3606#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
3607#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
3608#define CAN_F0R1_FB24_Pos (24U)
3609#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
3610#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
3611#define CAN_F0R1_FB25_Pos (25U)
3612#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
3613#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
3614#define CAN_F0R1_FB26_Pos (26U)
3615#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
3616#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
3617#define CAN_F0R1_FB27_Pos (27U)
3618#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
3619#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
3620#define CAN_F0R1_FB28_Pos (28U)
3621#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
3622#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
3623#define CAN_F0R1_FB29_Pos (29U)
3624#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
3625#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
3626#define CAN_F0R1_FB30_Pos (30U)
3627#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
3628#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
3629#define CAN_F0R1_FB31_Pos (31U)
3630#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
3631#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
3632
3633/******************* Bit definition for CAN_F1R1 register *******************/
3634#define CAN_F1R1_FB0_Pos (0U)
3635#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
3636#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
3637#define CAN_F1R1_FB1_Pos (1U)
3638#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
3639#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
3640#define CAN_F1R1_FB2_Pos (2U)
3641#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
3642#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
3643#define CAN_F1R1_FB3_Pos (3U)
3644#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
3645#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
3646#define CAN_F1R1_FB4_Pos (4U)
3647#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
3648#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
3649#define CAN_F1R1_FB5_Pos (5U)
3650#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
3651#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
3652#define CAN_F1R1_FB6_Pos (6U)
3653#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
3654#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
3655#define CAN_F1R1_FB7_Pos (7U)
3656#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
3657#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
3658#define CAN_F1R1_FB8_Pos (8U)
3659#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
3660#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
3661#define CAN_F1R1_FB9_Pos (9U)
3662#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
3663#defin