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diff --git a/lib/chibios/os/common/ext/ST/STM32L5xx/stm32l562xx.h b/lib/chibios/os/common/ext/ST/STM32L5xx/stm32l562xx.h
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1/**
2 ******************************************************************************
3 * @file stm32l562xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32L562xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.</center></h2>
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26#ifndef STM32L562xx_H
27#define STM32L562xx_H
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33/** @addtogroup ST
34 * @{
35 */
36
37
38/** @addtogroup STM32L562xx
39 * @{
40 */
41
42
43/** @addtogroup Configuration_of_CMSIS
44 * @{
45 */
46
47
48
49/* =========================================================================================================================== */
50/* ================ Interrupt Number Definition ================ */
51/* =========================================================================================================================== */
52
53typedef enum
54{
55/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
56 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
57 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
58 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
59 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
60 and No Match */
61 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
62 related Fault */
63 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
64 SecureFault_IRQn = -9, /*!< -9 Secure Fault */
65 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
66 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
67 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
68 SysTick_IRQn = -1, /*!< -1 System Tick Timer */
69
70/* =========================================== STM32L562xx Specific Interrupt Numbers ========================================= */
71 WWDG_IRQn = 0, /*!< Window WatchDog interrupt */
72 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection interrupts */
73 RTC_IRQn = 2, /*!< RTC non-secure interrupts through the EXTI line 17 */
74 RTC_S_IRQn = 3, /*!< RTC secure interrupts through the EXTI line 18 */
75 TAMP_IRQn = 4, /*!< Tamper non-secure interrupts through the EXTI line 19 */
76 TAMP_S_IRQn = 5, /*!< Tamper and TimeStamp interrupts through the EXTI line 20 */
77 FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */
78 FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */
79 GTZC_IRQn = 8, /*!< Global TrustZone controller global interrupt */
80 RCC_IRQn = 9, /*!< RCC non secure global interrupt */
81 RCC_S_IRQn = 10, /*!< RCC secure global interrupt */
82 EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */
83 EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */
84 EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */
85 EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */
86 EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */
87 EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */
88 EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */
89 EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */
90 EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */
91 EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */
92 EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */
93 EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */
94 EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */
95 EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */
96 EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */
97 EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */
98 DMAMUX1_IRQn = 27, /*!< DMAMUX1 non-secure interrupt */
99 DMAMUX1_S_IRQn = 28, /*!< DMAMUX1 secure interrupt */
100 DMA1_Channel1_IRQn = 29, /*!< DMA1 Channel 1 global interrupt */
101 DMA1_Channel2_IRQn = 30, /*!< DMA1 Channel 2 global interrupt */
102 DMA1_Channel3_IRQn = 31, /*!< DMA1 Channel 3 global interrupt */
103 DMA1_Channel4_IRQn = 32, /*!< DMA1 Channel 4 global interrupt */
104 DMA1_Channel5_IRQn = 33, /*!< DMA1 Channel 5 global interrupt */
105 DMA1_Channel6_IRQn = 34, /*!< DMA1 Channel 6 global interrupt */
106 DMA1_Channel7_IRQn = 35, /*!< DMA1 Channel 7 global interrupt */
107 DMA1_Channel8_IRQn = 36, /*!< DMA1 Channel 8 global interrupt */
108 ADC1_2_IRQn = 37, /*!< ADC1 & ADC2 global interrupts */
109 DAC_IRQn = 38, /*!< DAC global interrupts */
110 FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */
111 FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */
112 TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */
113 TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */
114 TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */
115 TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */
116 TIM2_IRQn = 45, /*!< TIM2 global interrupt */
117 TIM3_IRQn = 46, /*!< TIM3 global interrupt */
118 TIM4_IRQn = 47, /*!< TIM4 global interrupt */
119 TIM5_IRQn = 48, /*!< TIM5 global interrupt */
120 TIM6_IRQn = 49, /*!< TIM6 global interrupt */
121 TIM7_IRQn = 50, /*!< TIM7 global interrupt */
122 TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */
123 TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */
124 TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */
125 TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */
126 I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */
127 I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */
128 I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */
129 I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */
130 SPI1_IRQn = 59, /*!< SPI1 global interrupt */
131 SPI2_IRQn = 60, /*!< SPI2 global interrupt */
132 USART1_IRQn = 61, /*!< USART1 global interrupt */
133 USART2_IRQn = 62, /*!< USART2 global interrupt */
134 USART3_IRQn = 63, /*!< USART3 global interrupt */
135 UART4_IRQn = 64, /*!< UART4 global interrupt */
136 UART5_IRQn = 65, /*!< UART5 global interrupt */
137 LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */
138 LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */
139 LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */
140 TIM15_IRQn = 69, /*!< TIM15 global interrupt */
141 TIM16_IRQn = 70, /*!< TIM16 global interrupt */
142 TIM17_IRQn = 71, /*!< TIM17 global interrupt */
143 COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */
144 USB_FS_IRQn = 73, /*!< USB FS global interrupt */
145 CRS_IRQn = 74, /*!< CRS global interrupt */
146 FMC_IRQn = 75, /*!< FMC global interrupt */
147 OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */
148 SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */
149 DMA2_Channel1_IRQn = 80, /*!< DMA2 Channel 1 global interrupt */
150 DMA2_Channel2_IRQn = 81, /*!< DMA2 Channel 2 global interrupt */
151 DMA2_Channel3_IRQn = 82, /*!< DMA2 Channel 3 global interrupt */
152 DMA2_Channel4_IRQn = 83, /*!< DMA2 Channel 4 global interrupt */
153 DMA2_Channel5_IRQn = 84, /*!< DMA2 Channel 5 global interrupt */
154 DMA2_Channel6_IRQn = 85, /*!< DMA2 Channel 6 global interrupt */
155 DMA2_Channel7_IRQn = 86, /*!< DMA2 Channel 7 global interrupt */
156 DMA2_Channel8_IRQn = 87, /*!< DMA2 Channel 8 global interrupt */
157 I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */
158 I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */
159 SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */
160 SAI2_IRQn = 91, /*!< Serial Audio Interface 2 global interrupt */
161 TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */
162 AES_IRQn = 93, /*!< AES global interrupt */
163 RNG_IRQn = 94, /*!< RNG global interrupt */
164 FPU_IRQn = 95, /*!< FPU global interrupt */
165 HASH_IRQn = 96, /*!< HASH global interrupt */
166 PKA_IRQn = 97, /*!< PKA global interrupt */
167 LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */
168 SPI3_IRQn = 99, /*!< SPI3 global interrupt */
169 I2C4_EV_IRQn = 100, /*!< I2C4 Event interrupt */
170 I2C4_ER_IRQn = 101, /*!< I2C4 Error interrupt */
171 DFSDM1_FLT0_IRQn = 102, /*!< DFSDM1 Filter 0 global interrupt */
172 DFSDM1_FLT1_IRQn = 103, /*!< DFSDM1 Filter 1 global interrupt */
173 DFSDM1_FLT2_IRQn = 104, /*!< DFSDM1 Filter 2 global interrupt */
174 DFSDM1_FLT3_IRQn = 105, /*!< DFSDM1 Filter 3 global interrupt */
175 UCPD1_IRQn = 106, /*!< UCPD1 global interrupt */
176 ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */
177 OTFDEC1_IRQn = 108 /*!< OTFDEC1 global interrupt */
178} IRQn_Type;
179
180
181
182/* =========================================================================================================================== */
183/* ================ Processor and Core Peripheral Section ================ */
184/* =========================================================================================================================== */
185
186/* ------- Start of section using anonymous unions and disabling warnings ------- */
187#if defined (__CC_ARM)
188 #pragma push
189 #pragma anon_unions
190#elif defined (__ICCARM__)
191 #pragma language=extended
192#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
193 #pragma clang diagnostic push
194 #pragma clang diagnostic ignored "-Wc11-extensions"
195 #pragma clang diagnostic ignored "-Wreserved-id-macro"
196#elif defined (__GNUC__)
197 /* anonymous unions are enabled by default */
198#elif defined (__TMS470__)
199 /* anonymous unions are enabled by default */
200#elif defined (__TASKING__)
201 #pragma warning 586
202#elif defined (__CSMC__)
203 /* anonymous unions are enabled by default */
204#else
205 #warning Not supported compiler type
206#endif
207
208/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
209#define __CM33_REV 0x0000U /* Core revision r0p1 */
210#define __SAUREGION_PRESENT 1U /* SAU regions present */
211#define __MPU_PRESENT 1U /* MPU present */
212#define __VTOR_PRESENT 1U /* VTOR present */
213#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
214#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
215#define __FPU_PRESENT 1U /* FPU present */
216#define __DSP_PRESENT 1U /* DSP extension present */
217
218/** @} */ /* End of group Configuration_of_CMSIS */
219
220
221#include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */
222#include "system_stm32l5xx.h" /*!< STM32L5xx System */
223
224
225/* =========================================================================================================================== */
226/* ================ Device Specific Peripheral Section ================ */
227/* =========================================================================================================================== */
228
229
230/** @addtogroup STM32L5xx_peripherals
231 * @{
232 */
233
234/**
235 * @brief Analog to Digital Converter
236 */
237typedef struct
238{
239 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
240 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
241 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
242 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
243 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
244 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
245 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
246 uint32_t RESERVED1; /*!< Reserved, 0x1C */
247 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
248 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
249 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
250 uint32_t RESERVED2; /*!< Reserved, 0x2C */
251 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
252 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
253 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
254 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
255 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
256 uint32_t RESERVED3; /*!< Reserved, 0x44 */
257 uint32_t RESERVED4; /*!< Reserved, 0x48 */
258 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
259 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
260 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
261 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
262 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
263 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
264 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
265 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
266 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
267 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
268 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
269 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
270 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
271 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
272 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
273 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
274 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
275 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
276} ADC_TypeDef;
277
278typedef struct
279{
280 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
281 uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
282 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
283 __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */
284} ADC_Common_TypeDef;
285
286/**
287 * @brief FD Controller Area Network
288 */
289
290typedef struct
291{
292 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
293 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
294 uint32_t RESERVED1; /*!< Reserved, 0x008 */
295 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
296 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
297 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
298 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
299 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
300 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
301 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
302 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
303 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
304 uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
305 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
306 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
307 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
308 uint32_t RESERVED3; /*!< Reserved, 0x04C */
309 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
310 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
311 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
312 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
313 uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
314 __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
315 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */
316 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */
317 uint32_t RESERVED5; /*!< Reserved, 0x08C */
318 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */
319 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */
320 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */
321 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */
322 uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
323 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
324 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
325 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */
326 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */
327 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */
328 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */
329 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */
330 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */
331 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
332 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */
333 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */
334} FDCAN_GlobalTypeDef;
335
336/**
337 * @brief FD Controller Area Network Configuration
338 */
339
340typedef struct
341{
342 __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
343 uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */
344 __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */
345} FDCAN_Config_TypeDef;
346
347/**
348 * @brief CRC calculation unit
349 */
350typedef struct
351{
352 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
353 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
354 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
355 uint32_t RESERVED2; /*!< Reserved, 0x0C */
356 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
357 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
358} CRC_TypeDef;
359
360/**
361 * @brief Clock Recovery System
362 */
363typedef struct
364{
365__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
366__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
367__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
368__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
369} CRS_TypeDef;
370
371/**
372 * @brief AES hardware accelerator
373 */
374typedef struct
375{
376 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
377 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
378 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
379 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
380 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
381 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
382 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
383 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
384 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
385 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
386 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
387 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
388 __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */
389 __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */
390 __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */
391 __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */
392 __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */
393 __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */
394 __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */
395 __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */
396 __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */
397 __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */
398 __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */
399 __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */
400} AES_TypeDef;
401
402/**
403 * @brief Comparator
404 */
405
406typedef struct
407{
408 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
409} COMP_TypeDef;
410
411typedef struct
412{
413 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
414} COMP_Common_TypeDef;
415
416/**
417 * @brief Digital to Analog Converter
418 */
419
420typedef struct
421{
422 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
423 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
424 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
425 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
426 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
427 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
428 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
429 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
430 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
431 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
432 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
433 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
434 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
435 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
436 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
437 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
438 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
439 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
440 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
441 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
442} DAC_TypeDef;
443
444/**
445 * @brief DFSDM module registers
446 */
447typedef struct
448{
449 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
450 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
451 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
452 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
453 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
454 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
455 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
456 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
457 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
458 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
459 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
460 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
461 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
462 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
463 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
464} DFSDM_Filter_TypeDef;
465
466/**
467 * @brief DFSDM channel configuration registers
468 */
469typedef struct
470{
471 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
472 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
473 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
474 short circuit detector register, Address offset: 0x08 */
475 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
476 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
477 __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */
478} DFSDM_Channel_TypeDef;
479
480/**
481 * @brief Debug MCU - TODO review for STM32L5 to be done
482 */
483typedef struct
484{
485 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
486 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
487 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
488 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
489 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
490} DBGMCU_TypeDef;
491
492/**
493 * @brief DMA Controller
494 */
495
496typedef struct
497{
498 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
499 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
500} DMA_TypeDef;
501
502typedef struct
503{
504 __IO uint32_t CCR; /*!< DMA channel x configuration register, Address offset: 0x08 + (x * 0x14) */
505 __IO uint32_t CNDTR; /*!< DMA channel x number of data register, Address offset: 0x0C + (x * 0x14) */
506 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register, Address offset: 0x10 + (x * 0x14) */
507 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register, Address offset: 0x14 + (x * 0x14) */
508 __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register, Address offset: 0x18 + (x * 0x14) */
509} DMA_Channel_TypeDef;
510
511/**
512 * @brief DMA Multiplexer
513 */
514
515typedef struct
516{
517 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
518} DMAMUX_Channel_TypeDef;
519
520typedef struct
521{
522 __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
523 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
524} DMAMUX_ChannelStatus_TypeDef;
525
526typedef struct
527{
528 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
529} DMAMUX_RequestGen_TypeDef;
530
531typedef struct
532{
533 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
534 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
535} DMAMUX_RequestGenStatus_TypeDef;
536
537/**
538 * @brief Asynch Interrupt/Event Controller (EXTI)
539 */
540typedef struct
541{
542 __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */
543 __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */
544 __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */
545 __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */
546 __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */
547 __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */
548 __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */
549 uint32_t RESERVED1; /*!< Reserved 1, 0x1C */
550 __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */
551 __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */
552 __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */
553 __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */
554 __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */
555 __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */
556 __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */
557 uint32_t RESERVED2[9]; /*!< Reserved 2, 0x3C -- 0x5C */
558 __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */
559 __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */
560 uint32_t RESERVED3[3]; /*!< Reserved 3, 0x74 -- 0x7C */
561 __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */
562 __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */
563 uint32_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */
564 __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */
565 __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */
566} EXTI_TypeDef;
567
568/**
569 * @brief FLASH Registers
570 */
571
572typedef struct
573{
574 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
575 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
576 __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */
577 __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */
578 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */
579 __IO uint32_t LVEKEYR; /*!< FLASH LVE key register, Address offset: 0x14 */
580 __IO uint32_t RESERVED1[2]; /*!< Reserved1, Address offset: 0x18-0x1C */
581 __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */
582 __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */
583 __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */
584 __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */
585 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */
586 __IO uint32_t RESERVED2[3]; /*!< Reserved2, Address offset: 0x34-0x3C */
587 __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */
588 __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */
589 __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */
590 __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */
591 __IO uint32_t SECWM1R1; /*!< FLASH watermark-based secure register 1 bank 1, Address offset: 0x50 */
592 __IO uint32_t SECWM1R2; /*!< FLASH watermark-based secure register 2 bank 1, Address offset: 0x54 */
593 __IO uint32_t WRP1AR; /*!< FLASH WRP area A register bank 1, Address offset: 0x58 */
594 __IO uint32_t WRP1BR; /*!< FLASH WRP area B register bank 1, Address offset: 0x5C */
595 __IO uint32_t SECWM2R1; /*!< FLASH watermark-based secure register 1 bank 2, Address offset: 0x60 */
596 __IO uint32_t SECWM2R2; /*!< FLASH watermark-based secure register 2 bank 2, Address offset: 0x64 */
597 __IO uint32_t WRP2AR; /*!< FLASH WRP area A register bank 2, Address offset: 0x68 */
598 __IO uint32_t WRP2BR; /*!< FLASH WRP area B register bank 2, Address offset: 0x6C */
599 __IO uint32_t RESERVED3[4]; /*!< Reserved3, Address offset: 0x70-0x7C */
600 __IO uint32_t SECBB1R1; /*!< FLASH block-based secure bank 1, Address offset: 0x80 */
601 __IO uint32_t SECBB1R2; /*!< FLASH block-based secure bank 1, Address offset: 0x84 */
602 __IO uint32_t SECBB1R3; /*!< FLASH block-based secure bank 1, Address offset: 0x88 */
603 __IO uint32_t SECBB1R4; /*!< FLASH block-based secure bank 1, Address offset: 0x8C */
604 __IO uint32_t RESERVED4[4]; /*!< Reserved4, Address offset: 0x90-0x9C */
605 __IO uint32_t SECBB2R1; /*!< FLASH block-based secure bank 2, Address offset: 0xA0 */
606 __IO uint32_t SECBB2R2; /*!< FLASH block-based secure bank 2, Address offset: 0xA4 */
607 __IO uint32_t SECBB2R3; /*!< FLASH block-based secure bank 2, Address offset: 0xA8 */
608 __IO uint32_t SECBB2R4; /*!< FLASH block-based secure bank 2, Address offset: 0xAC */
609 __IO uint32_t RESERVED5[4]; /*!< Reserved5, Address offset: 0xB0-0xBC */
610 __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */
611 __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */
612} FLASH_TypeDef;
613
614/**
615 * @brief Flexible Memory Controller
616 */
617
618typedef struct
619{
620 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
621 __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */
622} FMC_Bank1_TypeDef;
623
624/**
625 * @brief Flexible Memory Controller Bank1E
626 */
627
628typedef struct
629{
630 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
631} FMC_Bank1E_TypeDef;
632
633/**
634 * @brief Flexible Memory Controller Bank3
635 */
636
637typedef struct
638{
639 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
640 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
641 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
642 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
643 uint32_t RESERVED0; /*!< Reserved, 0x90 */
644 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
645} FMC_Bank3_TypeDef;
646
647/**
648 * @brief General Purpose I/O
649 */
650
651typedef struct
652{
653 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
654 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
655 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
656 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
657 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
658 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
659 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
660 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
661 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
662 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
663 uint32_t RESERVED; /*!< Reserved, Address offset: 0x2C */
664 __IO uint32_t SECCFGR; /*!< GPIO Security configuration register, Address offset: 0x30 */
665} GPIO_TypeDef;
666
667/**
668 * @brief Global TrustZone Controller
669 */
670
671typedef struct{
672 __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */
673 uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */
674 __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */
675 __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */
676 uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x18-0x1C */
677 __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */
678 __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */
679 uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x28-0x2C */
680 __IO uint32_t MPCWM1_NSWMR1; /*!< TZSC external memory 1, non-secure watermark register 1, Address offset: 0x30 */
681 __IO uint32_t MPCWM1_NSWMR2; /*!< TZSC external memory 1, non-secure watermark register 2, Address offset: 0x34 */
682 __IO uint32_t MPCWM2_NSWMR1; /*!< TZSC external memory 2, non-secure watermark register 1, Address offset: 0x38 */
683 __IO uint32_t MPCWM2_NSWMR2; /*!< TZSC external memory 2, non-secure watermark register 2, Address offset: 0x3c */
684 __IO uint32_t MPCWM3_NSWMR1; /*!< TZSC external memory 3, non-secure watermark register 1, Address offset: 0x40 */
685} GTZC_TZSC_TypeDef;
686
687typedef struct{
688 __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */
689 uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */
690 __IO uint32_t LCKVTR1; /*!< MPCBBx lock register 1, Address offset: 0x10 */
691 __IO uint32_t LCKVTR2; /*!< MPCBBx lock register 2, Address offset: 0x14 */
692 uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */
693 __IO uint32_t VCTR[24]; /*!< MPCBBx vector registers, Address offset: 0x100-0x120 */
694} GTZC_MPCBB_TypeDef;
695
696typedef struct{
697 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */
698 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */
699 __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */
700 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x0C */
701 __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */
702 __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */
703 __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */
704 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
705 __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */
706 __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */
707 __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */
708} GTZC_TZIC_TypeDef;
709
710/**
711 * @brief HASH
712 */
713
714typedef struct
715{
716 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
717 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
718 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
719 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
720 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
721 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
722 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
723 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
724} HASH_TypeDef;
725
726/**
727 * @brief HASH_DIGEST
728 */
729
730typedef struct
731{
732 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
733} HASH_DIGEST_TypeDef;
734
735/**
736 * @brief Inter-integrated Circuit Interface
737 */
738
739typedef struct
740{
741 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
742 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
743 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
744 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
745 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
746 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
747 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
748 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
749 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
750 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
751 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
752} I2C_TypeDef;
753
754/**
755 * @brief Instruction Cache
756 */
757
758typedef struct
759{
760 __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */
761 __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */
762 __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */
763 __IO uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x0C */
764 __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */
765 __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */
766 uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
767 __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */
768 __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */
769 __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */
770 __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */
771} ICACHE_TypeDef;
772
773/**
774 * @brief Independent WATCHDOG
775 */
776typedef struct
777{
778 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
779 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
780 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
781 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
782 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
783} IWDG_TypeDef;
784
785/**
786 * @brief LPTIMER
787 */
788
789typedef struct
790{
791 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
792 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
793 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
794 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
795 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
796 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
797 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
798 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
799 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
800 __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x24 */
801 __IO uint32_t RCR; /*!< LPTIM Repetition counter register, Address offset: 0x28 */
802} LPTIM_TypeDef;
803
804/**
805 * @brief OCTO Serial Peripheral Interface
806 */
807
808typedef struct
809{
810 __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */
811 uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */
812 __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */
813 __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */
814 __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */
815 __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */
816 uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
817 __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */
818 __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */
819 uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
820 __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */
821 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */
822 __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */
823 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */
824 __IO uint32_t DR; /*!< OCTOPSI Data register, Address offset: 0x050 */
825 uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
826 __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */
827 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */
828 __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */
829 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */
830 __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */
831 uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
832 __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */
833 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */
834 __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */
835 uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */
836 __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */
837 uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
838 __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */
839 uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
840 __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */
841 uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
842 __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */
843 uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */
844 __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */
845 uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */
846 __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */
847 uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
848 __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */
849 uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
850 __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */
851 uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */
852 __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */
853 uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */
854 __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */
855 uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
856 __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
857 uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
858 __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
859} OCTOSPI_TypeDef;
860
861/**
862 * @brief Operational Amplifier (OPAMP)
863 */
864
865typedef struct
866{
867 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
868 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
869 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
870} OPAMP_TypeDef;
871
872typedef struct
873{
874 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
875} OPAMP_Common_TypeDef;
876
877/**
878 * @brief OTFDEC register
879 */
880typedef struct
881{
882 __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */
883 __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */
884 __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */
885 __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */
886 __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */
887 __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */
888 __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */
889 __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */
890 __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */
891} OTFDEC_Region_TypeDef;
892
893typedef struct
894{
895 __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */
896 uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */
897 __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control configuration register, Address offset: 0x010 */
898 uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */
899 __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */
900 __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */
901 __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */
902} OTFDEC_TypeDef;
903
904/**
905 * @brief Public Key Accelerator (PKA)
906 */
907
908typedef struct
909{
910 __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */
911 __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */
912 __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */
913 uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03FC*/
914 __IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F4 */
915} PKA_TypeDef;
916
917/**
918 * @brief Power Control
919 */
920
921typedef struct
922{
923 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
924 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
925 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
926 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
927 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
928 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
929 __IO uint32_t SCR; /*!< PWR power status clear register, Address offset: 0x18 */
930 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
931 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
932 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
933 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
934 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
935 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
936 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
937 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
938 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
939 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
940 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
941 __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
942 __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
943 __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
944 __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
945 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
946 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
947 uint32_t RESERVED2[6]; /*!< Reserved2, Address offset: 0x60-0x74 */
948 __IO uint32_t SECCFGR; /*!< PWR secure configuration register, Address offset: 0x78 */
949 uint32_t RESERVED3; /*!< Reserved3, Address offset: 0x7C */
950 __IO uint32_t PRIVCFGR; /*!< PWR privilege configuration register, Address offset: 0x80 */
951} PWR_TypeDef;
952
953/**
954 * @brief Reset and Clock Control
955 */
956
957typedef struct
958{
959 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
960 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
961 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
962 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
963 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
964 __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */
965 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
966 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
967 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
968 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
969 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
970 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
971 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
972 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
973 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
974 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
975 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
976 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
977 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
978 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
979 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
980 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
981 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
982 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
983 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
984 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
985 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
986 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
987 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
988 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
989 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
990 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
991 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
992 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
993 __IO uint32_t CCIPR1; /*!< RCC peripherals independent clock configuration register 1, Address offset: 0x88 */
994 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
995 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
996 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
997 __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
998 __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
999 uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0xA0-0xB4 */
1000 __IO uint32_t SECCFGR; /*!< RCC secure configuration register, Address offset: 0xB8 */
1001 __IO uint32_t SECSR; /*!< RCC secure status register, Address offset: 0xBC */
1002 uint32_t RESERVED9[10]; /*!< Reserved, Address offset: 0xC0-0xE4 */
1003 __IO uint32_t AHB1SECSR; /*!< RCC AHB1 security status register, Address offset: 0xE8 */
1004 __IO uint32_t AHB2SECSR; /*!< RCC AHB2 security status register, Address offset: 0xEC */
1005 __IO uint32_t AHB3SECSR; /*!< RCC AHB3 security status register, Address offset: 0xF0 */
1006 uint32_t RESERVED10; /*!< Reserved, Address offset: 0xF4 */
1007 __IO uint32_t APB1SECSR1; /*!< RCC APB1 security status register 1, Address offset: 0xF8 */
1008 __IO uint32_t APB1SECSR2; /*!< RCC APB1 security status register 2, Address offset: 0xFC */
1009 __IO uint32_t APB2SECSR; /*!< RCC APB2 security status register, Address offset: 0x100 */
1010} RCC_TypeDef;
1011
1012/**
1013 * @brief RNG
1014 */
1015typedef struct
1016{
1017 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1018 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1019 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1020 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */
1021 __IO uint32_t HTCR; /*!< RNG health test control register, Address offset: 0x10 */
1022} RNG_TypeDef;
1023
1024
1025
1026/**
1027 * @brief RTC Specific device feature definitions
1028 */
1029#define RTC_BACKUP_NB 32u
1030#define RTC_TAMP_NB 8u
1031
1032/**
1033 * @brief Real-Time Clock
1034 */
1035typedef struct
1036{
1037 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
1038 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
1039 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
1040 __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
1041 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
1042 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
1043 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
1044 __IO uint32_t PRIVCR; /*!< RTC privilege mode control register, Address offset: 0x1C */
1045 __IO uint32_t SMCR; /*!< RTC Secure mode control register, Address offset: 0x20 */
1046 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
1047 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
1048 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
1049 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
1050 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
1051 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
1052 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */
1053 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
1054 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
1055 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
1056 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
1057 __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
1058 __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
1059 __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */
1060 __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */
1061} RTC_TypeDef;
1062
1063/**
1064 * @brief Serial Peripheral Interface
1065 */
1066typedef struct
1067{
1068 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
1069 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
1070 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
1071 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
1072 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
1073 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
1074 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
1075} SPI_TypeDef;
1076
1077/**
1078 * @brief Tamper and backup registers
1079 */
1080typedef struct
1081{
1082 __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
1083 __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
1084 __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */
1085 __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
1086 __IO uint32_t ATCR1; /*!< TAMP active tamper control register 1 Address offset: 0x10 */
1087 __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */
1088 __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */
1089 __IO uint32_t ATCR2; /*!< TAMP active tamper control register 2, Address offset: 0x1C */
1090 __IO uint32_t SMCR; /*!< TAMP secure mode control register, Address offset: 0x20 */
1091 __IO uint32_t PRIVCR; /*!< TAMP privilege mode control register, Address offset: 0x24 */
1092 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */
1093 __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */
1094 __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */
1095 __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */
1096 __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
1097 __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
1098 __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
1099 uint32_t RESERVED1[47];/*!< Reserved, Address offset: 0x54 -- 0xFC */
1100 __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
1101 __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
1102 __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
1103 __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
1104 __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
1105 __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
1106 __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
1107 __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
1108 __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
1109 __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
1110 __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
1111 __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
1112 __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
1113 __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
1114 __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
1115 __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
1116 __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
1117 __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
1118 __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
1119 __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
1120 __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
1121 __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
1122 __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
1123 __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
1124 __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
1125 __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
1126 __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
1127 __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
1128 __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
1129 __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
1130 __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
1131 __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
1132} TAMP_TypeDef;
1133
1134/**
1135 * @brief TIM
1136 */
1137typedef struct
1138{
1139 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
1140 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
1141 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
1142 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
1143 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
1144 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
1145 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
1146 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
1147 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
1148 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
1149 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
1150 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1151 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
1152 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
1153 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
1154 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
1155 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
1156 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1157 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
1158 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
1159 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
1160 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
1161 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
1162 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
1163 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
1164 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
1165} TIM_TypeDef;
1166
1167/**
1168 * @brief Touch Sensing Controller (TSC)
1169 */
1170
1171typedef struct
1172{
1173 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
1174 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
1175 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
1176 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
1177 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
1178 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
1179 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
1180 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
1181 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
1182 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
1183 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
1184 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
1185 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
1186 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
1187} TSC_TypeDef;
1188
1189/**
1190 * @brief Serial Audio Interface
1191 */
1192
1193typedef struct
1194{
1195 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
1196 uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
1197 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
1198 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
1199} SAI_TypeDef;
1200
1201typedef struct
1202{
1203 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
1204 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
1205 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
1206 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
1207 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
1208 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
1209 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
1210 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
1211} SAI_Block_TypeDef;
1212
1213/**
1214 * @brief System configuration controller
1215 */
1216
1217typedef struct
1218{
1219 __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */
1220 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
1221 __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */
1222 __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */
1223 __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */
1224 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */
1225 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
1226 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x1C */
1227 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register 1, Address offset: 0x20 */
1228 __IO uint32_t SWPR2; /*!< SYSCFG SRAM2 write protection register 2, Address offset: 0x24 */
1229 uint32_t RESERVED; /*!< Reserved, Address offset: 0x28 */
1230 __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command register, Address offset: 0x2C */
1231} SYSCFG_TypeDef;
1232
1233/**
1234 * @brief Secure digital input/output Interface
1235 */
1236
1237typedef struct
1238{
1239 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
1240 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
1241 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
1242 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
1243 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
1244 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
1245 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
1246 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
1247 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
1248 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
1249 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
1250 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
1251 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
1252 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
1253 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
1254 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
1255 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
1256 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
1257 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
1258 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
1259 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
1260 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
1261 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
1262 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
1263 uint32_t RESERVED2[220]; /*!< Reserved, 0x84-0x3F0 */
1264 __IO uint32_t VER; /*!< SDMMC IP version register, Address offset: 0x3F4 */
1265 __IO uint32_t ID; /*!< SDMMC IP identification register, Address offset: 0x3F8 */
1266 __IO uint32_t SID; /*!< SDMMC size ID register, Address offset: 0x3FC */
1267} SDMMC_TypeDef;
1268
1269/**
1270 * @brief UCPD
1271 */
1272typedef struct
1273{
1274 __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
1275 __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
1276 __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */
1277 __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
1278 __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
1279 __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
1280 __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
1281 __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
1282 __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
1283 __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
1284 __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
1285 __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
1286 __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
1287 __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
1288 __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
1289} UCPD_TypeDef;
1290
1291/**
1292 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1293 */
1294typedef struct
1295{
1296 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1297 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1298 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1299 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1300 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1301 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1302 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
1303 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1304 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1305 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1306 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1307 __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
1308} USART_TypeDef;
1309
1310/**
1311 * @brief Universal Serial Bus Full Speed Device
1312 */
1313typedef struct
1314{
1315 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
1316 __IO uint16_t RESERVED0; /*!< Reserved */
1317 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
1318 __IO uint16_t RESERVED1; /*!< Reserved */
1319 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
1320 __IO uint16_t RESERVED2; /*!< Reserved */
1321 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
1322 __IO uint16_t RESERVED3; /*!< Reserved */
1323 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
1324 __IO uint16_t RESERVED4; /*!< Reserved */
1325 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
1326 __IO uint16_t RESERVED5; /*!< Reserved */
1327 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
1328 __IO uint16_t RESERVED6; /*!< Reserved */
1329 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
1330 __IO uint16_t RESERVED7[17]; /*!< Reserved */
1331 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
1332 __IO uint16_t RESERVED8; /*!< Reserved */
1333 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
1334 __IO uint16_t RESERVED9; /*!< Reserved */
1335 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
1336 __IO uint16_t RESERVEDA; /*!< Reserved */
1337 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
1338 __IO uint16_t RESERVEDB; /*!< Reserved */
1339 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
1340 __IO uint16_t RESERVEDC; /*!< Reserved */
1341 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
1342 __IO uint16_t RESERVEDD; /*!< Reserved */
1343 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
1344 __IO uint16_t RESERVEDE; /*!< Reserved */
1345} USB_TypeDef;
1346
1347/**
1348 * @brief VREFBUF
1349 */
1350typedef struct
1351{
1352 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
1353 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
1354} VREFBUF_TypeDef;
1355
1356/**
1357 * @brief Window WATCHDOG
1358 */
1359typedef struct
1360{
1361 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1362 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1363 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1364} WWDG_TypeDef;
1365
1366
1367/*@}*/ /* end of group STM32L562xx_Peripherals */
1368
1369
1370/* -------- End of section using anonymous unions and disabling warnings -------- */
1371#if defined (__CC_ARM)
1372 #pragma pop
1373#elif defined (__ICCARM__)
1374 /* leave anonymous unions enabled */
1375#elif (__ARMCC_VERSION >= 6010050)
1376 #pragma clang diagnostic pop
1377#elif defined (__GNUC__)
1378 /* anonymous unions are enabled by default */
1379#elif defined (__TMS470__)
1380 /* anonymous unions are enabled by default */
1381#elif defined (__TASKING__)
1382 #pragma warning restore
1383#elif defined (__CSMC__)
1384 /* anonymous unions are enabled by default */
1385#else
1386 #warning Not supported compiler type
1387#endif
1388
1389
1390/* =========================================================================================================================== */
1391/* ================ Device Specific Peripheral Address Map ================ */
1392/* =========================================================================================================================== */
1393
1394
1395/** @addtogroup STM32L5xx_Peripheral_peripheralAddr
1396 * @{
1397 */
1398
1399/* Internal SRAMs size */
1400#define SRAM1_SIZE 0x30000UL /*!< SRAM1=192k*/
1401#define SRAM2_SIZE 0x10000UL /*!< SRAM2=64k*/
1402
1403/* External memories base addresses - Not aliased */
1404#define FMC_BASE (0x60000000UL) /*!< FMC base address */
1405#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */
1406
1407#define FMC_BANK1 FMC_BASE
1408#define FMC_BANK1_1 FMC_BANK1
1409#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
1410#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
1411#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
1412#define FMC_BANK3 (FMC_BASE + 0x20000000UL)
1413
1414/* Flash, Peripheral and internal SRAMs base addresses - Non secure aliased */
1415#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH(up to 512 KB) base address */
1416#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1(up to 192 KB) base address */
1417#define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2(64 KB) base address */
1418#define SRAM_BASE_NS SRAM1_BASE
1419#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non secure base address */
1420
1421/* Peripheral memory map - Non secure */
1422#define APB1PERIPH_BASE_NS PERIPH_BASE_NS
1423#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL)
1424#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL)
1425#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL)
1426#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL)
1427
1428/*!< APB1 Non secure peripherals */
1429#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL)
1430#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL)
1431#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL)
1432#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL)
1433#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL)
1434#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL)
1435#define RTC_BASE_NS (APB1PERIPH_BASE_NS + 0x2800UL)
1436#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL)
1437#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL)
1438#define TAMP_BASE_NS (APB1PERIPH_BASE_NS + 0x3400UL)
1439#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL)
1440#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL)
1441#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL)
1442#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL)
1443#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL)
1444#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL)
1445#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL)
1446#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL)
1447#define I2C3_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL)
1448#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL)
1449#define PWR_BASE_NS (APB1PERIPH_BASE_NS + 0x7000UL)
1450#define DAC_BASE_NS (APB1PERIPH_BASE_NS + 0x7400UL)
1451#define DAC1_BASE_NS (APB1PERIPH_BASE_NS + 0x7400UL)
1452#define OPAMP_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL)
1453#define OPAMP1_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL)
1454#define OPAMP2_BASE_NS (APB1PERIPH_BASE_NS + 0x7810UL)
1455#define LPTIM1_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL)
1456#define LPUART1_BASE_NS (APB1PERIPH_BASE_NS + 0x8000UL)
1457#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL)
1458#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL)
1459#define LPTIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL)
1460#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL)
1461#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) /*!< FDCAN configuration registers base address */
1462#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL)
1463#define USB_BASE_NS (APB1PERIPH_BASE_NS + 0xD400UL) /*!< USB_IP Peripheral Registers base address */
1464#define USB_PMAADDR_NS (APB1PERIPH_BASE_NS + 0xD800UL) /*!< USB_IP Packet Memory Area base address */
1465#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL)
1466
1467/*!< APB2 Non secure peripherals */
1468#define SYSCFG_BASE_NS (APB2PERIPH_BASE_NS + 0x0000UL)
1469#define VREFBUF_BASE_NS (APB2PERIPH_BASE_NS + 0x0100UL)
1470#define COMP1_BASE_NS (APB2PERIPH_BASE_NS + 0x0200UL)
1471#define COMP2_BASE_NS (APB2PERIPH_BASE_NS + 0x0204UL)
1472#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL)
1473#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL)
1474#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL)
1475#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL)
1476#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL)
1477#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL)
1478#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL)
1479#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL)
1480#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x0004UL)
1481#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x0024UL)
1482#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL)
1483#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x0004UL)
1484#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x0024UL)
1485#define DFSDM1_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL)
1486#define DFSDM1_Channel0_BASE_NS (DFSDM1_BASE_NS + 0x0000UL)
1487#define DFSDM1_Channel1_BASE_NS (DFSDM1_BASE_NS + 0x0020UL)
1488#define DFSDM1_Channel2_BASE_NS (DFSDM1_BASE_NS + 0x0040UL)
1489#define DFSDM1_Channel3_BASE_NS (DFSDM1_BASE_NS + 0x0060UL)
1490#define DFSDM1_Filter0_BASE_NS (DFSDM1_BASE_NS + 0x0100UL)
1491#define DFSDM1_Filter1_BASE_NS (DFSDM1_BASE_NS + 0x0180UL)
1492#define DFSDM1_Filter2_BASE_NS (DFSDM1_BASE_NS + 0x0200UL)
1493#define DFSDM1_Filter3_BASE_NS (DFSDM1_BASE_NS + 0x0280UL)
1494
1495/*!< AHB1 Non secure peripherals */
1496#define DMA1_BASE_NS (AHB1PERIPH_BASE_NS)
1497#define DMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x0400UL)
1498#define DMAMUX1_BASE_NS (AHB1PERIPH_BASE_NS + 0x0800UL)
1499#define RCC_BASE_NS (AHB1PERIPH_BASE_NS + 0x1000UL)
1500#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x2000UL)
1501#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x3000UL)
1502#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x4000UL)
1503#define EXTI_BASE_NS (AHB1PERIPH_BASE_NS + 0xF400UL)
1504#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL)
1505#define GTZC_TZSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL)
1506#define GTZC_TZIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL)
1507#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL)
1508#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL)
1509
1510#define DMA1_Channel1_BASE_NS (DMA1_BASE_NS + 0x0008UL)
1511#define DMA1_Channel2_BASE_NS (DMA1_BASE_NS + 0x001CUL)
1512#define DMA1_Channel3_BASE_NS (DMA1_BASE_NS + 0x0030UL)
1513#define DMA1_Channel4_BASE_NS (DMA1_BASE_NS + 0x0044UL)
1514#define DMA1_Channel5_BASE_NS (DMA1_BASE_NS + 0x0058UL)
1515#define DMA1_Channel6_BASE_NS (DMA1_BASE_NS + 0x006CUL)
1516#define DMA1_Channel7_BASE_NS (DMA1_BASE_NS + 0x0080UL)
1517#define DMA1_Channel8_BASE_NS (DMA1_BASE_NS + 0x0094UL)
1518
1519#define DMA2_Channel1_BASE_NS (DMA2_BASE_NS + 0x0008UL)
1520#define DMA2_Channel2_BASE_NS (DMA2_BASE_NS + 0x001CUL)
1521#define DMA2_Channel3_BASE_NS (DMA2_BASE_NS + 0x0030UL)
1522#define DMA2_Channel4_BASE_NS (DMA2_BASE_NS + 0x0044UL)
1523#define DMA2_Channel5_BASE_NS (DMA2_BASE_NS + 0x0058UL)
1524#define DMA2_Channel6_BASE_NS (DMA2_BASE_NS + 0x006CUL)
1525#define DMA2_Channel7_BASE_NS (DMA2_BASE_NS + 0x0080UL)
1526#define DMA2_Channel8_BASE_NS (DMA2_BASE_NS + 0x0094UL)
1527
1528#define DMAMUX1_Channel0_BASE_NS (DMAMUX1_BASE_NS)
1529#define DMAMUX1_Channel1_BASE_NS (DMAMUX1_BASE_NS + 0x00000004UL)
1530#define DMAMUX1_Channel2_BASE_NS (DMAMUX1_BASE_NS + 0x00000008UL)
1531#define DMAMUX1_Channel3_BASE_NS (DMAMUX1_BASE_NS + 0x0000000CUL)
1532#define DMAMUX1_Channel4_BASE_NS (DMAMUX1_BASE_NS + 0x00000010UL)
1533#define DMAMUX1_Channel5_BASE_NS (DMAMUX1_BASE_NS + 0x00000014UL)
1534#define DMAMUX1_Channel6_BASE_NS (DMAMUX1_BASE_NS + 0x00000018UL)
1535#define DMAMUX1_Channel7_BASE_NS (DMAMUX1_BASE_NS + 0x0000001CUL)
1536#define DMAMUX1_Channel8_BASE_NS (DMAMUX1_BASE_NS + 0x00000020UL)
1537#define DMAMUX1_Channel9_BASE_NS (DMAMUX1_BASE_NS + 0x00000024UL)
1538#define DMAMUX1_Channel10_BASE_NS (DMAMUX1_BASE_NS + 0x00000028UL)
1539#define DMAMUX1_Channel11_BASE_NS (DMAMUX1_BASE_NS + 0x0000002CUL)
1540#define DMAMUX1_Channel12_BASE_NS (DMAMUX1_BASE_NS + 0x00000030UL)
1541#define DMAMUX1_Channel13_BASE_NS (DMAMUX1_BASE_NS + 0x00000034UL)
1542#define DMAMUX1_Channel14_BASE_NS (DMAMUX1_BASE_NS + 0x00000038UL)
1543#define DMAMUX1_Channel15_BASE_NS (DMAMUX1_BASE_NS + 0x0000003CUL)
1544
1545#define DMAMUX1_RequestGenerator0_BASE_NS (DMAMUX1_BASE_NS + 0x00000100UL)
1546#define DMAMUX1_RequestGenerator1_BASE_NS (DMAMUX1_BASE_NS + 0x00000104UL)
1547#define DMAMUX1_RequestGenerator2_BASE_NS (DMAMUX1_BASE_NS + 0x00000108UL)
1548#define DMAMUX1_RequestGenerator3_BASE_NS (DMAMUX1_BASE_NS + 0x0000010CUL)
1549
1550#define DMAMUX1_ChannelStatus_BASE_NS (DMAMUX1_BASE_NS + 0x00000080UL)
1551#define DMAMUX1_RequestGenStatus_BASE_NS (DMAMUX1_BASE_NS + 0x00000140UL)
1552
1553/*!< AHB2 Non secure peripherals */
1554#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x0000UL)
1555#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x0400UL)
1556#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x0800UL)
1557#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C00UL)
1558#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x1000UL)
1559#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x1400UL)
1560#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x1800UL)
1561#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x1C00UL)
1562#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x8000UL)
1563#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x8100UL)
1564#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x8300UL)
1565
1566#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL)
1567#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL)
1568#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL)
1569#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL)
1570#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL)
1571#define OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL)
1572#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL)
1573#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL)
1574#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL)
1575#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL)
1576#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL)
1577
1578/*!< AHB3 Non secure peripherals */
1579#define FMC_R_BASE_NS (AHB3PERIPH_BASE_NS + 0x0000UL) /*!< FMC control registers base address */
1580#define OCTOSPI1_R_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) /*!< OCTOSPI1 control registers base address */
1581
1582/*!< FMC Banks Non secure registers base address */
1583#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL)
1584#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL)
1585#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL)
1586
1587/* Flash, Peripheral and internal SRAMs base addresses - Secure aliased */
1588#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH(up to 512 KB) base address */
1589#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1(up to 192 KB) base address */
1590#define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2(64 KB) base address */
1591#define SRAM_BASE_S SRAM1_BASE_S
1592#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */
1593
1594/* Peripheral memory map - Secure */
1595#define APB1PERIPH_BASE_S PERIPH_BASE_S
1596#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL)
1597#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL)
1598#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL)
1599#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL)
1600
1601/*!< APB1 Secure peripherals */
1602#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL)
1603#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL)
1604#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL)
1605#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL)
1606#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL)
1607#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL)
1608#define RTC_BASE_S (APB1PERIPH_BASE_S + 0x2800UL)
1609#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL)
1610#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL)
1611#define TAMP_BASE_S (APB1PERIPH_BASE_S + 0x3400UL)
1612#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL)
1613#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL)
1614#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL)
1615#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL)
1616#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL)
1617#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL)
1618#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL)
1619#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL)
1620#define I2C3_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL)
1621#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL)
1622#define PWR_BASE_S (APB1PERIPH_BASE_S + 0x7000UL)
1623#define DAC_BASE_S (APB1PERIPH_BASE_S + 0x7400UL)
1624#define DAC1_BASE_S (APB1PERIPH_BASE_S + 0x7400UL)
1625#define OPAMP_BASE_S (APB1PERIPH_BASE_S + 0x7800UL)
1626#define OPAMP1_BASE_S (APB1PERIPH_BASE_S + 0x7800UL)
1627#define OPAMP2_BASE_S (APB1PERIPH_BASE_S + 0x7810UL)
1628#define LPTIM1_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL)
1629#define LPUART1_BASE_S (APB1PERIPH_BASE_S + 0x8000UL)
1630#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL)
1631#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL)
1632#define LPTIM3_BASE_S (APB1PERIPH_BASE_S + 0x9800UL)
1633#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL)
1634#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL)
1635#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL)
1636#define USB_BASE_S (APB1PERIPH_BASE_S + 0xD400UL) /*!< USB_IP Peripheral Registers base address */
1637#define USB_PMAADDR_S (APB1PERIPH_BASE_S + 0xD800UL) /*!< USB_IP Packet Memory Area base address */
1638#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL)
1639
1640/*!< APB2 Secure peripherals */
1641#define SYSCFG_BASE_S (APB2PERIPH_BASE_S + 0x0000UL)
1642#define VREFBUF_BASE_S (APB2PERIPH_BASE_S + 0x0100UL)
1643#define COMP1_BASE_S (APB2PERIPH_BASE_S + 0x0200UL)
1644#define COMP2_BASE_S (APB2PERIPH_BASE_S + 0x0204UL)
1645#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL)
1646#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL)
1647#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL)
1648#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL)
1649#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL)
1650#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL)
1651#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL)
1652#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL)
1653#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x0004UL)
1654#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x0024UL)
1655#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL)
1656#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x0004UL)
1657#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x0024UL)
1658#define DFSDM1_BASE_S (APB2PERIPH_BASE_S + 0x6000UL)
1659#define DFSDM1_Channel0_BASE_S (DFSDM1_BASE_S + 0x0000UL)
1660#define DFSDM1_Channel1_BASE_S (DFSDM1_BASE_S + 0x0020UL)
1661#define DFSDM1_Channel2_BASE_S (DFSDM1_BASE_S + 0x0040UL)
1662#define DFSDM1_Channel3_BASE_S (DFSDM1_BASE_S + 0x0060UL)
1663#define DFSDM1_Filter0_BASE_S (DFSDM1_BASE_S + 0x0100UL)
1664#define DFSDM1_Filter1_BASE_S (DFSDM1_BASE_S + 0x0180UL)
1665#define DFSDM1_Filter2_BASE_S (DFSDM1_BASE_S + 0x0200UL)
1666#define DFSDM1_Filter3_BASE_S (DFSDM1_BASE_S + 0x0280UL)
1667
1668/*!< AHB1 Secure peripherals */
1669#define DMA1_BASE_S (AHB1PERIPH_BASE_S)
1670#define DMA2_BASE_S (AHB1PERIPH_BASE_S + 0x0400UL)
1671#define DMAMUX1_BASE_S (AHB1PERIPH_BASE_S + 0x0800UL)
1672#define RCC_BASE_S (AHB1PERIPH_BASE_S + 0x1000UL)
1673#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x2000UL)
1674#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x3000UL)
1675#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x4000UL)
1676#define EXTI_BASE_S (AHB1PERIPH_BASE_S + 0xF400UL)
1677#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL)
1678#define GTZC_TZSC_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL)
1679#define GTZC_TZIC_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL)
1680#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL)
1681#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL)
1682
1683#define DMA1_Channel1_BASE_S (DMA1_BASE_S + 0x0008UL)
1684#define DMA1_Channel2_BASE_S (DMA1_BASE_S + 0x001CUL)
1685#define DMA1_Channel3_BASE_S (DMA1_BASE_S + 0x0030UL)
1686#define DMA1_Channel4_BASE_S (DMA1_BASE_S + 0x0044UL)
1687#define DMA1_Channel5_BASE_S (DMA1_BASE_S + 0x0058UL)
1688#define DMA1_Channel6_BASE_S (DMA1_BASE_S + 0x006CUL)
1689#define DMA1_Channel7_BASE_S (DMA1_BASE_S + 0x0080UL)
1690#define DMA1_Channel8_BASE_S (DMA1_BASE_S + 0x0094UL)
1691
1692#define DMA2_Channel1_BASE_S (DMA2_BASE_S + 0x0008UL)
1693#define DMA2_Channel2_BASE_S (DMA2_BASE_S + 0x001CUL)
1694#define DMA2_Channel3_BASE_S (DMA2_BASE_S + 0x0030UL)
1695#define DMA2_Channel4_BASE_S (DMA2_BASE_S + 0x0044UL)
1696#define DMA2_Channel5_BASE_S (DMA2_BASE_S + 0x0058UL)
1697#define DMA2_Channel6_BASE_S (DMA2_BASE_S + 0x006CUL)
1698#define DMA2_Channel7_BASE_S (DMA2_BASE_S + 0x0080UL)
1699#define DMA2_Channel8_BASE_S (DMA2_BASE_S + 0x0094UL)
1700
1701#define DMAMUX1_Channel0_BASE_S (DMAMUX1_BASE_S)
1702#define DMAMUX1_Channel1_BASE_S (DMAMUX1_BASE_S + 0x00000004UL)
1703#define DMAMUX1_Channel2_BASE_S (DMAMUX1_BASE_S + 0x00000008UL)
1704#define DMAMUX1_Channel3_BASE_S (DMAMUX1_BASE_S + 0x0000000CUL)
1705#define DMAMUX1_Channel4_BASE_S (DMAMUX1_BASE_S + 0x00000010UL)
1706#define DMAMUX1_Channel5_BASE_S (DMAMUX1_BASE_S + 0x00000014UL)
1707#define DMAMUX1_Channel6_BASE_S (DMAMUX1_BASE_S + 0x00000018UL)
1708#define DMAMUX1_Channel7_BASE_S (DMAMUX1_BASE_S + 0x0000001CUL)
1709#define DMAMUX1_Channel8_BASE_S (DMAMUX1_BASE_S + 0x00000020UL)
1710#define DMAMUX1_Channel9_BASE_S (DMAMUX1_BASE_S + 0x00000024UL)
1711#define DMAMUX1_Channel10_BASE_S (DMAMUX1_BASE_S + 0x00000028UL)
1712#define DMAMUX1_Channel11_BASE_S (DMAMUX1_BASE_S + 0x0000002CUL)
1713#define DMAMUX1_Channel12_BASE_S (DMAMUX1_BASE_S + 0x00000030UL)
1714#define DMAMUX1_Channel13_BASE_S (DMAMUX1_BASE_S + 0x00000034UL)
1715#define DMAMUX1_Channel14_BASE_S (DMAMUX1_BASE_S + 0x00000038UL)
1716#define DMAMUX1_Channel15_BASE_S (DMAMUX1_BASE_S + 0x0000003CUL)
1717
1718#define DMAMUX1_RequestGenerator0_BASE_S (DMAMUX1_BASE_S + 0x00000100UL)
1719#define DMAMUX1_RequestGenerator1_BASE_S (DMAMUX1_BASE_S + 0x00000104UL)
1720#define DMAMUX1_RequestGenerator2_BASE_S (DMAMUX1_BASE_S + 0x00000108UL)
1721#define DMAMUX1_RequestGenerator3_BASE_S (DMAMUX1_BASE_S + 0x0000010CUL)
1722
1723#define DMAMUX1_ChannelStatus_BASE_S (DMAMUX1_BASE_S + 0x00000080UL)
1724#define DMAMUX1_RequestGenStatus_BASE_S (DMAMUX1_BASE_S + 0x00000140UL)
1725
1726/*!< AHB2 Secure peripherals */
1727#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x0000UL)
1728#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x0400UL)
1729#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x0800UL)
1730#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x0C00UL)
1731#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x1000UL)
1732#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x1400UL)
1733#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x1800UL)
1734#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x1C00UL)
1735#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x8000UL)
1736#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x8100UL)
1737#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x8300UL)
1738
1739#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL)
1740#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL)
1741#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL)
1742#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL)
1743#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL)
1744#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL)
1745#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL)
1746#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL)
1747#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL)
1748#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL)
1749#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL)
1750
1751/*!< AHB3 Secure peripherals */
1752#define FMC_R_BASE_S (AHB3PERIPH_BASE_S + 0x0000UL) /*!< FMC control registers base address */
1753#define OCTOSPI1_R_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) /*!< OCTOSPI1 control registers base address */
1754
1755/*!< FMC Banks Secure registers base address */
1756#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL)
1757#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL)
1758#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL)
1759
1760/* Debug MCU registers base address */
1761#define DBGMCU_BASE (0xE0044000UL)
1762
1763#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */
1764#define UID_BASE (0x0BFA0590UL) /*!< Unique device ID register base address */
1765#define FLASHSIZE_BASE (0x0BFA05E0UL) /*!< Flash size data register base address */
1766
1767/* Internal Flash size */
1768#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x80000U : \
1769 ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x80000U : \
1770 (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x0FFFU)) << 10U)))
1771
1772/* OTP Area */
1773#define OTP_BASE (0x0BFA0000UL)
1774#define OTP_SIZE (0x200U)
1775
1776/** @} */ /* End of group STM32L5xx_Peripheral_peripheralAddr */
1777
1778
1779/* =========================================================================================================================== */
1780/* ================ Peripheral declaration ================ */
1781/* =========================================================================================================================== */
1782
1783
1784/** @addtogroup STM32L5xx_Peripheral_declaration
1785 * @{
1786 */
1787
1788/*!< APB1 Non secure peripherals */
1789#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS)
1790#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS)
1791#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS)
1792#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS)
1793#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS)
1794#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS)
1795#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS)
1796#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS)
1797#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS)
1798#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS)
1799#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS)
1800#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS)
1801#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS)
1802#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS)
1803#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS)
1804#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS)
1805#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS)
1806#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS)
1807#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS)
1808#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS)
1809#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS)
1810#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS)
1811#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS)
1812#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS)
1813#define DAC_NS ((DAC_TypeDef *) DAC1_BASE_NS)
1814#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS)
1815#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS)
1816#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS)
1817#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS)
1818#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS)
1819#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
1820#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS)
1821#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS)
1822#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS)
1823#define USB_NS ((USB_TypeDef *) USB_BASE_NS)
1824#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS)
1825
1826/*!< APB2 Non secure peripherals */
1827#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS)
1828#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS)
1829#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS)
1830#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS)
1831#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP2_BASE_NS)
1832#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS)
1833#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS)
1834#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS)
1835#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS)
1836#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS)
1837#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS)
1838#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS)
1839#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS)
1840#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS)
1841#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS)
1842#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS)
1843#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS)
1844#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS)
1845#define DFSDM1_Channel0_NS ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE_NS)
1846#define DFSDM1_Channel1_NS ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE_NS)
1847#define DFSDM1_Channel2_NS ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE_NS)
1848#define DFSDM1_Channel3_NS ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE_NS)
1849#define DFSDM1_Filter0_NS ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE_NS)
1850#define DFSDM1_Filter1_NS ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE_NS)
1851#define DFSDM1_Filter2_NS ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE_NS)
1852#define DFSDM1_Filter3_NS ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE_NS)
1853
1854/*!< AHB1 Non secure peripherals */
1855#define DMA1_NS ((DMA_TypeDef *) DMA1_BASE_NS)
1856#define DMA2_NS ((DMA_TypeDef *) DMA2_BASE_NS)
1857#define DMAMUX1_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE_NS)
1858#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS)
1859#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS)
1860#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS)
1861#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS)
1862#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS)
1863#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS)
1864#define GTZC_TZSC_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE_NS)
1865#define GTZC_TZIC_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE_NS)
1866#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS)
1867#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS)
1868
1869#define DMA1_Channel1_NS ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE_NS)
1870#define DMA1_Channel2_NS ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE_NS)
1871#define DMA1_Channel3_NS ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE_NS)
1872#define DMA1_Channel4_NS ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE_NS)
1873#define DMA1_Channel5_NS ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE_NS)
1874#define DMA1_Channel6_NS ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE_NS)
1875#define DMA1_Channel7_NS ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE_NS)
1876#define DMA1_Channel8_NS ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE_NS)
1877
1878#define DMA2_Channel1_NS ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE_NS)
1879#define DMA2_Channel2_NS ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE_NS)
1880#define DMA2_Channel3_NS ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE_NS)
1881#define DMA2_Channel4_NS ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE_NS)
1882#define DMA2_Channel5_NS ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE_NS)
1883#define DMA2_Channel6_NS ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE_NS)
1884#define DMA2_Channel7_NS ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE_NS)
1885#define DMA2_Channel8_NS ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE_NS)
1886
1887#define DMAMUX1_Channel0_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE_NS)
1888#define DMAMUX1_Channel1_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE_NS)
1889#define DMAMUX1_Channel2_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE_NS)
1890#define DMAMUX1_Channel3_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE_NS)
1891#define DMAMUX1_Channel4_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE_NS)
1892#define DMAMUX1_Channel5_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE_NS)
1893#define DMAMUX1_Channel6_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE_NS)
1894#define DMAMUX1_Channel7_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE_NS)
1895#define DMAMUX1_Channel8_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE_NS)
1896#define DMAMUX1_Channel9_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE_NS)
1897#define DMAMUX1_Channel10_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE_NS)
1898#define DMAMUX1_Channel11_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE_NS)
1899#define DMAMUX1_Channel12_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE_NS)
1900#define DMAMUX1_Channel13_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE_NS)
1901#define DMAMUX1_Channel14_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE_NS)
1902#define DMAMUX1_Channel15_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE_NS)
1903
1904#define DMAMUX1_RequestGenerator0_NS ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE_NS)
1905#define DMAMUX1_RequestGenerator1_NS ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE_NS)
1906#define DMAMUX1_RequestGenerator2_NS ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE_NS)
1907#define DMAMUX1_RequestGenerator3_NS ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE_NS)
1908
1909#define DMAMUX1_ChannelStatus_NS ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE_NS)
1910#define DMAMUX1_RequestGenStatus_NS ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE_NS)
1911
1912/*!< AHB2 Non secure peripherals */
1913#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS)
1914#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS)
1915#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS)
1916#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS)
1917#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS)
1918#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS)
1919#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS)
1920#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS)
1921#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS)
1922#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS)
1923#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
1924#define AES_NS ((AES_TypeDef *) AES_BASE_NS)
1925#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS)
1926#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
1927#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS)
1928#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS)
1929#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS)
1930#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS)
1931#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS)
1932#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS)
1933#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS)
1934#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS)
1935
1936/*!< AHB3 Non secure peripherals */
1937#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS)
1938#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS)
1939#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS)
1940
1941#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS)
1942
1943/*!< APB1 Secure peripherals */
1944#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S)
1945#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S)
1946#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S)
1947#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S)
1948#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S)
1949#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S)
1950#define RTC_S ((RTC_TypeDef *) RTC_BASE_S)
1951#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S)
1952#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S)
1953#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S)
1954#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S)
1955#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S)
1956#define USART2_S ((USART_TypeDef *) USART2_BASE_S)
1957#define USART3_S ((USART_TypeDef *) USART3_BASE_S)
1958#define UART4_S ((USART_TypeDef *) UART4_BASE_S)
1959#define UART5_S ((USART_TypeDef *) UART5_BASE_S)
1960#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S)
1961#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S)
1962#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S)
1963#define CRS_S ((CRS_TypeDef *) CRS_BASE_S)
1964#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S)
1965#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S)
1966#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S)
1967#define PWR_S ((PWR_TypeDef *) PWR_BASE_S)
1968#define DAC_S ((DAC_TypeDef *) DAC1_BASE_S)
1969#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S)
1970#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S)
1971#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S)
1972#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S)
1973#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S)
1974#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S)
1975#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S)
1976#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S)
1977#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S)
1978#define USB_S ((USB_TypeDef *) USB_BASE_S)
1979#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S)
1980
1981/*!< APB2 Secure peripherals */
1982#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S)
1983#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S)
1984#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S)
1985#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S)
1986#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP2_BASE_S)
1987#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S)
1988#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S)
1989#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S)
1990#define USART1_S ((USART_TypeDef *) USART1_BASE_S)
1991#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S)
1992#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S)
1993#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S)
1994#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S)
1995#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S)
1996#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S)
1997#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S)
1998#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S)
1999#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S)
2000#define DFSDM1_Channel0_S ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE_S)
2001#define DFSDM1_Channel1_S ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE_S)
2002#define DFSDM1_Channel2_S ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE_S)
2003#define DFSDM1_Channel3_S ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE_S)
2004#define DFSDM1_Filter0_S ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE_S)
2005#define DFSDM1_Filter1_S ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE_S)
2006#define DFSDM1_Filter2_S ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE_S)
2007#define DFSDM1_Filter3_S ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE_S)
2008
2009/*!< AHB1 Secure peripherals */
2010#define DMA1_S ((DMA_TypeDef *) DMA1_BASE_S)
2011#define DMA2_S ((DMA_TypeDef *) DMA2_BASE_S)
2012#define DMAMUX1_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE_S)
2013#define RCC_S ((RCC_TypeDef *) RCC_BASE_S)
2014#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S)
2015#define CRC_S ((CRC_TypeDef *) CRC_BASE_S)
2016#define TSC_S ((TSC_TypeDef *) TSC_BASE_S)
2017#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S)
2018#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S)
2019#define GTZC_TZSC_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE_S)
2020#define GTZC_TZIC_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE_S)
2021#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S)
2022#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S)
2023
2024#define DMA1_Channel1_S ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE_S)
2025#define DMA1_Channel2_S ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE_S)
2026#define DMA1_Channel3_S ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE_S)
2027#define DMA1_Channel4_S ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE_S)
2028#define DMA1_Channel5_S ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE_S)
2029#define DMA1_Channel6_S ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE_S)
2030#define DMA1_Channel7_S ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE_S)
2031#define DMA1_Channel8_S ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE_S)
2032
2033#define DMA2_Channel1_S ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE_S)
2034#define DMA2_Channel2_S ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE_S)
2035#define DMA2_Channel3_S ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE_S)
2036#define DMA2_Channel4_S ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE_S)
2037#define DMA2_Channel5_S ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE_S)
2038#define DMA2_Channel6_S ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE_S)
2039#define DMA2_Channel7_S ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE_S)
2040#define DMA2_Channel8_S ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE_S)
2041
2042#define DMAMUX1_Channel0_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE_S)
2043#define DMAMUX1_Channel1_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE_S)
2044#define DMAMUX1_Channel2_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE_S)
2045#define DMAMUX1_Channel3_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE_S)
2046#define DMAMUX1_Channel4_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE_S)
2047#define DMAMUX1_Channel5_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE_S)
2048#define DMAMUX1_Channel6_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE_S)
2049#define DMAMUX1_Channel7_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE_S)
2050#define DMAMUX1_Channel8_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE_S)
2051#define DMAMUX1_Channel9_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE_S)
2052#define DMAMUX1_Channel10_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE_S)
2053#define DMAMUX1_Channel11_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE_S)
2054#define DMAMUX1_Channel12_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE_S)
2055#define DMAMUX1_Channel13_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE_S)
2056#define DMAMUX1_Channel14_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE_S)
2057#define DMAMUX1_Channel15_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE_S)
2058
2059#define DMAMUX1_RequestGenerator0_S ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE_S)
2060#define DMAMUX1_RequestGenerator1_S ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE_S)
2061#define DMAMUX1_RequestGenerator2_S ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE_S)
2062#define DMAMUX1_RequestGenerator3_S ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE_S)
2063
2064#define DMAMUX1_ChannelStatus_S ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE_S)
2065#define DMAMUX1_RequestGenStatus_S ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE_S)
2066
2067/*!< AHB2 Secure peripherals */
2068#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S)
2069#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S)
2070#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S)
2071#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S)
2072#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S)
2073#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S)
2074#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S)
2075#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S)
2076#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S)
2077#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S)
2078#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S)
2079#define AES_S ((AES_TypeDef *) AES_BASE_S)
2080#define HASH_S ((HASH_TypeDef *) HASH_BASE_S)
2081#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
2082#define RNG_S ((RNG_TypeDef *) RNG_BASE_S)
2083#define PKA_S ((PKA_TypeDef *) PKA_BASE_S)
2084#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S)
2085#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S)
2086#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S)
2087#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S)
2088#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S)
2089#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S)
2090
2091/*!< AHB3 Secure peripherals */
2092#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S)
2093#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S)
2094#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S)
2095
2096#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S)
2097
2098
2099#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2100
2101/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
2102
2103#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2104
2105/*!< Memory base addresses for Secure peripherals */
2106#define FLASH_BASE FLASH_BASE_S
2107#define SRAM1_BASE SRAM1_BASE_S
2108#define SRAM2_BASE SRAM2_BASE_S
2109#define SRAM_BASE SRAM1_BASE_S
2110#define PERIPH_BASE PERIPH_BASE_S
2111#define APB1PERIPH_BASE APB1PERIPH_BASE_S
2112#define APB2PERIPH_BASE APB2PERIPH_BASE_S
2113#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S
2114#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S
2115#define AHB3PERIPH_BASE AHB3PERIPH_BASE_S
2116
2117/*!< Instance aliases and base addresses for Secure peripherals */
2118#define RCC RCC_S
2119#define RCC_BASE RCC_BASE_S
2120
2121#define FLASH FLASH_S
2122#define FLASH_R_BASE FLASH_R_BASE_S
2123
2124#define DMA1 DMA1_S
2125#define DMA1_BASE DMA1_BASE_S
2126
2127#define DMA1_Channel1 DMA1_Channel1_S
2128#define DMA1_Channel1_BASE DMA1_Channel1_BASE_S
2129
2130#define DMA1_Channel2 DMA1_Channel2_S
2131#define DMA1_Channel2_BASE DMA1_Channel2_BASE_S
2132
2133#define DMA1_Channel3 DMA1_Channel3_S
2134#define DMA1_Channel3_BASE DMA1_Channel3_BASE_S
2135
2136#define DMA1_Channel4 DMA1_Channel4_S
2137#define DMA1_Channel4_BASE DMA1_Channel4_BASE_S
2138
2139#define DMA1_Channel5 DMA1_Channel5_S
2140#define DMA1_Channel5_BASE DMA1_Channel5_BASE_S
2141
2142#define DMA1_Channel6 DMA1_Channel6_S
2143#define DMA1_Channel6_BASE DMA1_Channel6_BASE_S
2144
2145#define DMA1_Channel7 DMA1_Channel7_S
2146#define DMA1_Channel7_BASE DMA1_Channel7_BASE_S
2147
2148#define DMA1_Channel8 DMA1_Channel8_S
2149#define DMA1_Channel8_BASE DMA1_Channel8_BASE_S
2150
2151#define DMA2 DMA2_S
2152#define DMA2_BASE DMA2_BASE_S
2153
2154#define DMA2_Channel1 DMA2_Channel1_S
2155#define DMA2_Channel1_BASE DMA2_Channel1_BASE_S
2156
2157#define DMA2_Channel2 DMA2_Channel2_S
2158#define DMA2_Channel2_BASE DMA2_Channel2_BASE_S
2159
2160#define DMA2_Channel3 DMA2_Channel3_S
2161#define DMA2_Channel3_BASE DMA2_Channel3_BASE_S
2162
2163#define DMA2_Channel4 DMA2_Channel4_S
2164#define DMA2_Channel4_BASE DMA2_Channel4_BASE_S
2165
2166#define DMA2_Channel5 DMA2_Channel5_S
2167#define DMA2_Channel5_BASE DMA2_Channel5_BASE_S
2168
2169#define DMA2_Channel6 DMA2_Channel6_S
2170#define DMA2_Channel6_BASE DMA2_Channel6_BASE_S
2171
2172#define DMA2_Channel7 DMA2_Channel7_S
2173#define DMA2_Channel7_BASE DMA2_Channel7_BASE_S
2174
2175#define DMA2_Channel8 DMA2_Channel8_S
2176#define DMA2_Channel8_BASE DMA2_Channel8_BASE_S
2177
2178#define DMAMUX1 DMAMUX1_S
2179#define DMAMUX1_BASE DMAMUX1_BASE_S
2180
2181#define DMAMUX1_Channel0 DMAMUX1_Channel0_S
2182#define DMAMUX1_Channel0_BASE DMAMUX1_Channel0_BASE_S
2183
2184#define DMAMUX1_Channel1 DMAMUX1_Channel1_S
2185#define DMAMUX1_Channel1_BASE DMAMUX1_Channel1_BASE_S
2186
2187#define DMAMUX1_Channel2 DMAMUX1_Channel2_S
2188#define DMAMUX1_Channel2_BASE DMAMUX1_Channel2_BASE_S
2189
2190#define DMAMUX1_Channel3 DMAMUX1_Channel3_S
2191#define DMAMUX1_Channel3_BASE DMAMUX1_Channel3_BASE_S
2192
2193#define DMAMUX1_Channel4 DMAMUX1_Channel4_S
2194#define DMAMUX1_Channel4_BASE DMAMUX1_Channel4_BASE_S
2195
2196#define DMAMUX1_Channel5 DMAMUX1_Channel5_S
2197#define DMAMUX1_Channel5_BASE DMAMUX1_Channel5_BASE_S
2198
2199#define DMAMUX1_Channel6 DMAMUX1_Channel6_S
2200#define DMAMUX1_Channel6_BASE DMAMUX1_Channel6_BASE_S
2201
2202#define DMAMUX1_Channel7 DMAMUX1_Channel7_S
2203#define DMAMUX1_Channel7_BASE DMAMUX1_Channel7_BASE_S
2204
2205#define DMAMUX1_Channel8 DMAMUX1_Channel8_S
2206#define DMAMUX1_Channel8_BASE DMAMUX1_Channel8_BASE_S
2207
2208#define DMAMUX1_Channel9 DMAMUX1_Channel9_S
2209#define DMAMUX1_Channel9_BASE DMAMUX1_Channel9_BASE_S
2210
2211#define DMAMUX1_Channel10 DMAMUX1_Channel10_S
2212#define DMAMUX1_Channel10_BASE DMAMUX1_Channel10_BASE_S
2213
2214#define DMAMUX1_Channel11 DMAMUX1_Channel11_S
2215#define DMAMUX1_Channel11_BASE DMAMUX1_Channel11_BASE_S
2216
2217#define DMAMUX1_Channel12 DMAMUX1_Channel12_S
2218#define DMAMUX1_Channel12_BASE DMAMUX1_Channel12_BASE_S
2219
2220#define DMAMUX1_Channel13 DMAMUX1_Channel13_S
2221#define DMAMUX1_Channel13_BASE DMAMUX1_Channel13_BASE_S
2222
2223#define DMAMUX1_Channel14 DMAMUX1_Channel14_S
2224#define DMAMUX1_Channel14_BASE DMAMUX1_Channel14_BASE_S
2225
2226#define DMAMUX1_Channel15 DMAMUX1_Channel15_S
2227#define DMAMUX1_Channel15_BASE DMAMUX1_Channel15_BASE_S
2228
2229#define DMAMUX1_RequestGenerator0 DMAMUX1_RequestGenerator0_S
2230#define DMAMUX1_RequestGenerator0_BASE DMAMUX1_RequestGenerator0_BASE_S
2231
2232#define DMAMUX1_RequestGenerator1 DMAMUX1_RequestGenerator1_S
2233#define DMAMUX1_RequestGenerator1_BASE DMAMUX1_RequestGenerator1_BASE_S
2234
2235#define DMAMUX1_RequestGenerator2 DMAMUX1_RequestGenerator2_S
2236#define DMAMUX1_RequestGenerator2_BASE DMAMUX1_RequestGenerator2_BASE_S
2237
2238#define DMAMUX1_RequestGenerator3 DMAMUX1_RequestGenerator3_S
2239#define DMAMUX1_RequestGenerator3_BASE DMAMUX1_RequestGenerator3_BASE_S
2240
2241#define DMAMUX1_ChannelStatus DMAMUX1_ChannelStatus_S
2242#define DMAMUX1_ChannelStatus_BASE DMAMUX1_ChannelStatus_BASE_S
2243
2244#define DMAMUX1_RequestGenStatus DMAMUX1_RequestGenStatus_S
2245#define DMAMUX1_RequestGenStatus_BASE DMAMUX1_RequestGenStatus_BASE_S
2246
2247#define GPIOA GPIOA_S
2248#define GPIOA_BASE GPIOA_BASE_S
2249
2250#define GPIOB GPIOB_S
2251#define GPIOB_BASE GPIOB_BASE_S
2252
2253#define GPIOC GPIOC_S
2254#define GPIOC_BASE GPIOC_BASE_S
2255
2256#define GPIOD GPIOD_S
2257#define GPIOD_BASE GPIOD_BASE_S
2258
2259#define GPIOE GPIOE_S
2260#define GPIOE_BASE GPIOE_BASE_S
2261
2262#define GPIOF GPIOF_S
2263#define GPIOF_BASE GPIOF_BASE_S
2264
2265#define GPIOG GPIOG_S
2266#define GPIOG_BASE GPIOG_BASE_S
2267
2268#define GPIOH GPIOH_S
2269#define GPIOH_BASE GPIOH_BASE_S
2270
2271#define PWR PWR_S
2272#define PWR_BASE PWR_BASE_S
2273
2274#define EXTI EXTI_S
2275#define EXTI_BASE EXTI_BASE_S
2276
2277#define ICACHE ICACHE_S
2278#define ICACHE_BASE ICACHE_BASE_S
2279
2280#define GTZC_TZSC GTZC_TZSC_S
2281#define GTZC_TZSC_BASE GTZC_TZSC_BASE_S
2282
2283#define GTZC_TZIC GTZC_TZIC_S
2284#define GTZC_TZIC_BASE GTZC_TZIC_BASE_S
2285
2286#define GTZC_MPCBB2 GTZC_MPCBB2_S
2287#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S
2288
2289#define GTZC_MPCBB1 GTZC_MPCBB1_S
2290#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S
2291
2292#define RTC RTC_S
2293#define RTC_BASE RTC_BASE_S
2294
2295#define TAMP TAMP_S
2296#define TAMP_BASE TAMP_BASE_S
2297
2298#define TIM1 TIM1_S
2299#define TIM1_BASE TIM1_BASE_S
2300
2301#define TIM2 TIM2_S
2302#define TIM2_BASE TIM2_BASE_S
2303
2304#define TIM3 TIM3_S
2305#define TIM3_BASE TIM3_BASE_S
2306
2307#define TIM4 TIM4_S
2308#define TIM4_BASE TIM4_BASE_S
2309
2310#define TIM5 TIM5_S
2311#define TIM5_BASE TIM5_BASE_S
2312
2313#define TIM6 TIM6_S
2314#define TIM6_BASE TIM6_BASE_S
2315
2316#define TIM7 TIM7_S
2317#define TIM7_BASE TIM7_BASE_S
2318
2319#define TIM8 TIM8_S
2320#define TIM8_BASE TIM8_BASE_S
2321
2322#define TIM15 TIM15_S
2323#define TIM15_BASE TIM15_BASE_S
2324
2325#define TIM16 TIM16_S
2326#define TIM16_BASE TIM16_BASE_S
2327
2328#define TIM17 TIM17_S
2329#define TIM17_BASE TIM17_BASE_S
2330
2331#define WWDG WWDG_S
2332#define WWDG_BASE WWDG_BASE_S
2333
2334#define IWDG IWDG_S
2335#define IWDG_BASE IWDG_BASE_S
2336
2337#define SPI1 SPI1_S
2338#define SPI1_BASE SPI1_BASE_S
2339
2340#define SPI2 SPI2_S
2341#define SPI2_BASE SPI2_BASE_S
2342
2343#define SPI3 SPI3_S
2344#define SPI3_BASE SPI3_BASE_S
2345
2346#define USART1 USART1_S
2347#define USART1_BASE USART1_BASE_S
2348
2349#define USART2 USART2_S
2350#define USART2_BASE USART2_BASE_S
2351
2352#define USART3 USART3_S
2353#define USART3_BASE USART3_BASE_S
2354
2355#define UART4 UART4_S
2356#define UART4_BASE UART4_BASE_S
2357
2358#define UART5 UART5_S
2359#define UART5_BASE UART5_BASE_S
2360
2361#define I2C1 I2C1_S
2362#define I2C1_BASE I2C1_BASE_S
2363
2364#define I2C2 I2C2_S
2365#define I2C2_BASE I2C2_BASE_S
2366
2367#define I2C3 I2C3_S
2368#define I2C3_BASE I2C3_BASE_S
2369
2370#define I2C4 I2C4_S
2371#define I2C4_BASE I2C4_BASE_S
2372
2373#define CRS CRS_S
2374#define CRS_BASE CRS_BASE_S
2375
2376#define FDCAN1 FDCAN1_S
2377#define FDCAN1_BASE FDCAN1_BASE_S
2378
2379#define FDCAN_CONFIG FDCAN_CONFIG_S
2380#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S
2381#define SRAMCAN_BASE SRAMCAN_BASE_S
2382
2383#define DAC DAC_S
2384#define DAC_BASE DAC_BASE_S
2385
2386#define DAC1 DAC1_S
2387#define DAC1_BASE DAC1_BASE_S
2388
2389#define OPAMP OPAMP_S
2390#define OPAMP_BASE OPAMP_BASE_S
2391
2392#define OPAMP1 OPAMP1_S
2393#define OPAMP1_BASE OPAMP1_BASE_S
2394
2395#define OPAMP2 OPAMP2_S
2396#define OPAMP2_BASE OPAMP2_BASE_S
2397
2398#define OPAMP12_COMMON OPAMP12_COMMON_S
2399#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S
2400
2401#define LPTIM1 LPTIM1_S
2402#define LPTIM1_BASE LPTIM1_BASE_S
2403
2404#define LPTIM2 LPTIM2_S
2405#define LPTIM2_BASE LPTIM2_BASE_S
2406
2407#define LPTIM3 LPTIM3_S
2408#define LPTIM3_BASE LPTIM3_BASE_S
2409
2410#define LPUART1 LPUART1_S
2411#define LPUART1_BASE LPUART1_BASE_S
2412
2413#define USB USB_S
2414#define USB_BASE USB_BASE_S
2415
2416#define UCPD1 UCPD1_S
2417#define UCPD1_BASE UCPD1_BASE_S
2418
2419#define SYSCFG SYSCFG_S
2420#define SYSCFG_BASE SYSCFG_BASE_S
2421
2422#define VREFBUF VREFBUF_S
2423#define VREFBUF_BASE VREFBUF_BASE_S
2424
2425#define COMP1 COMP1_S
2426#define COMP1_BASE COMP1_BASE_S
2427
2428#define COMP2 COMP2_S
2429#define COMP2_BASE COMP2_BASE_S
2430
2431#define COMP12_COMMON COMP12_COMMON_S
2432#define COMP12_COMMON_BASE COMP12_COMMON_BASE_S
2433
2434#define SAI1 SAI1_S
2435#define SAI1_BASE SAI1_BASE_S
2436
2437#define SAI1_Block_A SAI1_Block_A_S
2438#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S
2439
2440#define SAI1_Block_B SAI1_Block_B_S
2441#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S
2442
2443#define SAI2 SAI2_S
2444#define SAI2_BASE SAI2_BASE_S
2445
2446#define SAI2_Block_A SAI2_Block_A_S
2447#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S
2448
2449#define SAI2_Block_B SAI2_Block_B_S
2450#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S
2451
2452#define DFSDM1_Channel0 DFSDM1_Channel0_S
2453#define DFSDM1_Channel0_BASE DFSDM1_Channel0_BASE_S
2454
2455#define DFSDM1_Channel1 DFSDM1_Channel1_S
2456#define DFSDM1_Channel1_BASE DFSDM1_Channel1_BASE_S
2457
2458#define DFSDM1_Channel2 DFSDM1_Channel2_S
2459#define DFSDM1_Channel2_BASE DFSDM1_Channel2_BASE_S
2460
2461#define DFSDM1_Channel3 DFSDM1_Channel3_S
2462#define DFSDM1_Channel3_BASE DFSDM1_Channel3_BASE_S
2463
2464#define DFSDM1_Filter0 DFSDM1_Filter0_S
2465#define DFSDM1_Filter0_BASE DFSDM1_Filter0_BASE_S
2466
2467#define DFSDM1_Filter1 DFSDM1_Filter1_S
2468#define DFSDM1_Filter1_BASE DFSDM1_Filter1_BASE_S
2469
2470#define DFSDM1_Filter2 DFSDM1_Filter2_S
2471#define DFSDM1_Filter2_BASE DFSDM1_Filter2_BASE_S
2472
2473#define DFSDM1_Filter3 DFSDM1_Filter3_S
2474#define DFSDM1_Filter3_BASE DFSDM1_Filter3_BASE_S
2475
2476#define CRC CRC_S
2477#define CRC_BASE CRC_BASE_S
2478
2479#define TSC TSC_S
2480#define TSC_BASE TSC_BASE_S
2481
2482#define ADC1 ADC1_S
2483#define ADC1_BASE ADC1_BASE_S
2484
2485#define ADC2 ADC2_S
2486#define ADC2_BASE ADC2_BASE_S
2487
2488#define ADC12_COMMON ADC12_COMMON_S
2489#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S
2490
2491#define AES AES_S
2492#define AES_BASE AES_BASE_S
2493
2494#define HASH HASH_S
2495#define HASH_BASE HASH_BASE_S
2496
2497#define HASH_DIGEST HASH_DIGEST_S
2498#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S
2499
2500#define RNG RNG_S
2501#define RNG_BASE RNG_BASE_S
2502
2503#define PKA PKA_S
2504#define PKA_BASE PKA_BASE_S
2505
2506#define OTFDEC1 OTFDEC1_S
2507#define OTFDEC1_BASE OTFDEC1_BASE_S
2508
2509#define OTFDEC1_REGION1 OTFDEC1_REGION1_S
2510#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S
2511
2512#define OTFDEC1_REGION2 OTFDEC1_REGION2_S
2513#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S
2514
2515#define OTFDEC1_REGION3 OTFDEC1_REGION3_S
2516#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S
2517
2518#define OTFDEC1_REGION4 OTFDEC1_REGION4_S
2519#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S
2520
2521#define SDMMC1 SDMMC1_S
2522#define SDMMC1_BASE SDMMC1_BASE_S
2523
2524#define FMC_R_BASE FMC_R_BASE_S
2525
2526#define FMC_Bank1_R FMC_Bank1_R_S
2527#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S
2528
2529#define FMC_Bank1E_R FMC_Bank1E_R_S
2530#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S
2531
2532#define FMC_Bank3_R FMC_Bank3_R_S
2533#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S
2534
2535#define OCTOSPI1 OCTOSPI1_S
2536#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S
2537
2538#else
2539
2540/*!< Memory base addresses for Non secure peripherals */
2541#define FLASH_BASE FLASH_BASE_NS
2542#define SRAM1_BASE SRAM1_BASE_NS
2543#define SRAM2_BASE SRAM2_BASE_NS
2544#define SRAM_BASE SRAM1_BASE_NS
2545#define PERIPH_BASE PERIPH_BASE_NS
2546#define APB1PERIPH_BASE APB1PERIPH_BASE_NS
2547#define APB2PERIPH_BASE APB2PERIPH_BASE_NS
2548#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS
2549#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS
2550#define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS
2551
2552/*!< Instance aliases and base addresses for Non secure peripherals */
2553#define RCC RCC_NS
2554#define RCC_BASE RCC_BASE_NS
2555
2556#define FLASH FLASH_NS
2557#define FLASH_R_BASE FLASH_R_BASE_NS
2558
2559#define DMA1 DMA1_NS
2560#define DMA1_BASE DMA1_BASE_NS
2561
2562#define DMA1_Channel1 DMA1_Channel1_NS
2563#define DMA1_Channel1_BASE DMA1_Channel1_BASE_NS
2564
2565#define DMA1_Channel2 DMA1_Channel2_NS
2566#define DMA1_Channel2_BASE DMA1_Channel2_BASE_NS
2567
2568#define DMA1_Channel3 DMA1_Channel3_NS
2569#define DMA1_Channel3_BASE DMA1_Channel3_BASE_NS
2570
2571#define DMA1_Channel4 DMA1_Channel4_NS
2572#define DMA1_Channel4_BASE DMA1_Channel4_BASE_NS
2573
2574#define DMA1_Channel5 DMA1_Channel5_NS
2575#define DMA1_Channel5_BASE DMA1_Channel5_BASE_NS
2576
2577#define DMA1_Channel6 DMA1_Channel6_NS
2578#define DMA1_Channel6_BASE DMA1_Channel6_BASE_NS
2579
2580#define DMA1_Channel7 DMA1_Channel7_NS
2581#define DMA1_Channel7_BASE DMA1_Channel7_BASE_NS
2582
2583#define DMA1_Channel8 DMA1_Channel8_NS
2584#define DMA1_Channel8_BASE DMA1_Channel8_BASE_NS
2585
2586#define DMA2 DMA2_NS
2587#define DMA2_BASE DMA2_BASE_NS
2588
2589#define DMA2_Channel1 DMA2_Channel1_NS
2590#define DMA2_Channel1_BASE DMA2_Channel1_BASE_NS
2591
2592#define DMA2_Channel2 DMA2_Channel2_NS
2593#define DMA2_Channel2_BASE DMA2_Channel2_BASE_NS
2594
2595#define DMA2_Channel3 DMA2_Channel3_NS
2596#define DMA2_Channel3_BASE DMA2_Channel3_BASE_NS
2597
2598#define DMA2_Channel4 DMA2_Channel4_NS
2599#define DMA2_Channel4_BASE DMA2_Channel4_BASE_NS
2600
2601#define DMA2_Channel5 DMA2_Channel5_NS
2602#define DMA2_Channel5_BASE DMA2_Channel5_BASE_NS
2603
2604#define DMA2_Channel6 DMA2_Channel6_NS
2605#define DMA2_Channel6_BASE DMA2_Channel6_BASE_NS
2606
2607#define DMA2_Channel7 DMA2_Channel7_NS
2608#define DMA2_Channel7_BASE DMA2_Channel7_BASE_NS
2609
2610#define DMA2_Channel8 DMA2_Channel8_NS
2611#define DMA2_Channel8_BASE DMA2_Channel8_BASE_NS
2612
2613#define DMAMUX1 DMAMUX1_NS
2614#define DMAMUX1_BASE DMAMUX1_BASE_NS
2615
2616#define DMAMUX1_Channel0 DMAMUX1_Channel0_NS
2617#define DMAMUX1_Channel0_BASE DMAMUX1_Channel0_BASE_NS
2618
2619#define DMAMUX1_Channel1 DMAMUX1_Channel1_NS
2620#define DMAMUX1_Channel1_BASE DMAMUX1_Channel1_BASE_NS
2621
2622#define DMAMUX1_Channel2 DMAMUX1_Channel2_NS
2623#define DMAMUX1_Channel2_BASE DMAMUX1_Channel2_BASE_NS
2624
2625#define DMAMUX1_Channel3 DMAMUX1_Channel3_NS
2626#define DMAMUX1_Channel3_BASE DMAMUX1_Channel3_BASE_NS
2627
2628#define DMAMUX1_Channel4 DMAMUX1_Channel4_NS
2629#define DMAMUX1_Channel4_BASE DMAMUX1_Channel4_BASE_NS
2630
2631#define DMAMUX1_Channel5 DMAMUX1_Channel5_NS
2632#define DMAMUX1_Channel5_BASE DMAMUX1_Channel5_BASE_NS
2633
2634#define DMAMUX1_Channel6 DMAMUX1_Channel6_NS
2635#define DMAMUX1_Channel6_BASE DMAMUX1_Channel6_BASE_NS
2636
2637#define DMAMUX1_Channel7 DMAMUX1_Channel7_NS
2638#define DMAMUX1_Channel7_BASE DMAMUX1_Channel7_BASE_NS
2639
2640#define DMAMUX1_Channel8 DMAMUX1_Channel8_NS
2641#define DMAMUX1_Channel8_BASE DMAMUX1_Channel8_BASE_NS
2642
2643#define DMAMUX1_Channel9 DMAMUX1_Channel9_NS
2644#define DMAMUX1_Channel9_BASE DMAMUX1_Channel9_BASE_NS
2645
2646#define DMAMUX1_Channel10 DMAMUX1_Channel10_NS
2647#define DMAMUX1_Channel10_BASE DMAMUX1_Channel10_BASE_NS
2648
2649#define DMAMUX1_Channel11 DMAMUX1_Channel11_NS
2650#define DMAMUX1_Channel11_BASE DMAMUX1_Channel11_BASE_NS
2651
2652#define DMAMUX1_Channel12 DMAMUX1_Channel12_NS
2653#define DMAMUX1_Channel12_BASE DMAMUX1_Channel12_BASE_NS
2654
2655#define DMAMUX1_Channel13 DMAMUX1_Channel13_NS
2656#define DMAMUX1_Channel13_BASE DMAMUX1_Channel13_BASE_NS
2657
2658#define DMAMUX1_Channel14 DMAMUX1_Channel14_NS
2659#define DMAMUX1_Channel14_BASE DMAMUX1_Channel14_BASE_NS
2660
2661#define DMAMUX1_Channel15 DMAMUX1_Channel15_NS
2662#define DMAMUX1_Channel15_BASE DMAMUX1_Channel15_BASE_NS
2663
2664#define DMAMUX1_RequestGenerator0 DMAMUX1_RequestGenerator0_NS
2665#define DMAMUX1_RequestGenerator0_BASE DMAMUX1_RequestGenerator0_BASE_NS
2666
2667#define DMAMUX1_RequestGenerator1 DMAMUX1_RequestGenerator1_NS
2668#define DMAMUX1_RequestGenerator1_BASE DMAMUX1_RequestGenerator1_BASE_NS
2669
2670#define DMAMUX1_RequestGenerator2 DMAMUX1_RequestGenerator2_NS
2671#define DMAMUX1_RequestGenerator2_BASE DMAMUX1_RequestGenerator2_BASE_NS
2672
2673#define DMAMUX1_RequestGenerator3 DMAMUX1_RequestGenerator3_NS
2674#define DMAMUX1_RequestGenerator3_BASE DMAMUX1_RequestGenerator3_BASE_NS
2675
2676#define DMAMUX1_ChannelStatus DMAMUX1_ChannelStatus_NS
2677#define DMAMUX1_ChannelStatus_BASE DMAMUX1_ChannelStatus_BASE_NS
2678
2679#define DMAMUX1_RequestGenStatus DMAMUX1_RequestGenStatus_NS
2680#define DMAMUX1_RequestGenStatus_BASE DMAMUX1_RequestGenStatus_BASE_NS
2681
2682#define GPIOA GPIOA_NS
2683#define GPIOA_BASE GPIOA_BASE_NS
2684
2685#define GPIOB GPIOB_NS
2686#define GPIOB_BASE GPIOB_BASE_NS
2687
2688#define GPIOC GPIOC_NS
2689#define GPIOC_BASE GPIOC_BASE_NS
2690
2691#define GPIOD GPIOD_NS
2692#define GPIOD_BASE GPIOD_BASE_NS
2693
2694#define GPIOE GPIOE_NS
2695#define GPIOE_BASE GPIOE_BASE_NS
2696
2697#define GPIOF GPIOF_NS
2698#define GPIOF_BASE GPIOF_BASE_NS
2699
2700#define GPIOG GPIOG_NS
2701#define GPIOG_BASE GPIOG_BASE_NS
2702
2703#define GPIOH GPIOH_NS
2704#define GPIOH_BASE GPIOH_BASE_NS
2705
2706#define PWR PWR_NS
2707#define PWR_BASE PWR_BASE_NS
2708
2709#define EXTI EXTI_NS
2710#define EXTI_BASE EXTI_BASE_NS
2711
2712#define ICACHE ICACHE_NS
2713#define ICACHE_BASE ICACHE_BASE_NS
2714
2715#define GTZC_TZSC GTZC_TZSC_NS
2716#define GTZC_TZSC_BASE GTZC_TZSC_BASE_NS
2717
2718#define GTZC_TZIC GTZC_TZIC_NS
2719#define GTZC_TZIC_BASE GTZC_TZIC_BASE_NS
2720
2721#define GTZC_MPCBB2 GTZC_MPCBB2_NS
2722#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS
2723
2724#define GTZC_MPCBB1 GTZC_MPCBB1_NS
2725#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS
2726
2727#define RTC RTC_NS
2728#define RTC_BASE RTC_BASE_NS
2729
2730#define TAMP TAMP_NS
2731#define TAMP_BASE TAMP_BASE_NS
2732
2733#define TIM1 TIM1_NS
2734#define TIM1_BASE TIM1_BASE_NS
2735
2736#define TIM2 TIM2_NS
2737#define TIM2_BASE TIM2_BASE_NS
2738
2739#define TIM3 TIM3_NS
2740#define TIM3_BASE TIM3_BASE_NS
2741
2742#define TIM4 TIM4_NS
2743#define TIM4_BASE TIM4_BASE_NS
2744
2745#define TIM5 TIM5_NS
2746#define TIM5_BASE TIM5_BASE_NS
2747
2748#define TIM6 TIM6_NS
2749#define TIM6_BASE TIM6_BASE_NS
2750
2751#define TIM7 TIM7_NS
2752#define TIM7_BASE TIM7_BASE_NS
2753
2754#define TIM8 TIM8_NS
2755#define TIM8_BASE TIM8_BASE_NS
2756
2757#define TIM15 TIM15_NS
2758#define TIM15_BASE TIM15_BASE_NS
2759
2760#define TIM16 TIM16_NS
2761#define TIM16_BASE TIM16_BASE_NS
2762
2763#define TIM17 TIM17_NS
2764#define TIM17_BASE TIM17_BASE_NS
2765
2766#define WWDG WWDG_NS
2767#define WWDG_BASE WWDG_BASE_NS
2768
2769#define IWDG IWDG_NS
2770#define IWDG_BASE IWDG_BASE_NS
2771
2772#define SPI1 SPI1_NS
2773#define SPI1_BASE SPI1_BASE_NS
2774
2775#define SPI2 SPI2_NS
2776#define SPI2_BASE SPI2_BASE_NS
2777
2778#define SPI3 SPI3_NS
2779#define SPI3_BASE SPI3_BASE_NS
2780
2781#define USART1 USART1_NS
2782#define USART1_BASE USART1_BASE_NS
2783
2784#define USART2 USART2_NS
2785#define USART2_BASE USART2_BASE_NS
2786
2787#define USART3 USART3_NS
2788#define USART3_BASE USART3_BASE_NS
2789
2790#define UART4 UART4_NS
2791#define UART4_BASE UART4_BASE_NS
2792
2793#define UART5 UART5_NS
2794#define UART5_BASE UART5_BASE_NS
2795
2796#define I2C1 I2C1_NS
2797#define I2C1_BASE I2C1_BASE_NS
2798
2799#define I2C2 I2C2_NS
2800#define I2C2_BASE I2C2_BASE_NS
2801
2802#define I2C3 I2C3_NS
2803#define I2C3_BASE I2C3_BASE_NS
2804
2805#define I2C4 I2C4_NS
2806#define I2C4_BASE I2C4_BASE_NS
2807
2808#define CRS CRS_NS
2809#define CRS_BASE CRS_BASE_NS
2810
2811#define FDCAN1 FDCAN1_NS
2812#define FDCAN1_BASE FDCAN1_BASE_NS
2813
2814#define FDCAN_CONFIG FDCAN_CONFIG_NS
2815#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS
2816#define SRAMCAN_BASE SRAMCAN_BASE_NS
2817
2818#define DAC DAC_NS
2819#define DAC_BASE DAC_BASE_NS
2820
2821#define DAC1 DAC1_NS
2822#define DAC1_BASE DAC1_BASE_NS
2823
2824#define OPAMP OPAMP_NS
2825#define OPAMP_BASE OPAMP_BASE_NS
2826
2827#define OPAMP1 OPAMP1_NS
2828#define OPAMP1_BASE OPAMP1_BASE_NS
2829
2830#define OPAMP2 OPAMP2_NS
2831#define OPAMP2_BASE OPAMP2_BASE_NS
2832
2833#define OPAMP12_COMMON OPAMP12_COMMON_NS
2834#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS
2835
2836#define LPTIM1 LPTIM1_NS
2837#define LPTIM1_BASE LPTIM1_BASE_NS
2838
2839#define LPTIM2 LPTIM2_NS
2840#define LPTIM2_BASE LPTIM2_BASE_NS
2841
2842#define LPTIM3 LPTIM3_NS
2843#define LPTIM3_BASE LPTIM3_BASE_NS
2844
2845#define LPUART1 LPUART1_NS
2846#define LPUART1_BASE LPUART1_BASE_NS
2847
2848#define USB USB_NS
2849#define USB_BASE USB_BASE_NS
2850
2851#define UCPD1 UCPD1_NS
2852#define UCPD1_BASE UCPD1_BASE_NS
2853
2854#define SYSCFG SYSCFG_NS
2855#define SYSCFG_BASE SYSCFG_BASE_NS
2856
2857#define VREFBUF VREFBUF_NS
2858#define VREFBUF_BASE VREFBUF_BASE_NS
2859
2860#define COMP1 COMP1_NS
2861#define COMP1_BASE COMP1_BASE_NS
2862
2863#define COMP2 COMP2_NS
2864#define COMP2_BASE COMP2_BASE_NS
2865
2866#define COMP12_COMMON COMP12_COMMON_NS
2867#define COMP12_COMMON_BASE COMP12_COMMON_BASE_NS
2868
2869#define SAI1 SAI1_NS
2870#define SAI1_BASE SAI1_BASE_NS
2871
2872#define SAI1_Block_A SAI1_Block_A_NS
2873#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS
2874
2875#define SAI1_Block_B SAI1_Block_B_NS
2876#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS
2877
2878#define SAI2 SAI2_NS
2879#define SAI2_BASE SAI2_BASE_NS
2880
2881#define SAI2_Block_A SAI2_Block_A_NS
2882#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS
2883
2884#define SAI2_Block_B SAI2_Block_B_NS
2885#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS
2886
2887#define DFSDM1_Channel0 DFSDM1_Channel0_NS
2888#define DFSDM1_Channel0_BASE DFSDM1_Channel0_BASE_NS
2889
2890#define DFSDM1_Channel1 DFSDM1_Channel1_NS
2891#define DFSDM1_Channel1_BASE DFSDM1_Channel1_BASE_NS
2892
2893#define DFSDM1_Channel2 DFSDM1_Channel2_NS
2894#define DFSDM1_Channel2_BASE DFSDM1_Channel2_BASE_NS
2895
2896#define DFSDM1_Channel3 DFSDM1_Channel3_NS
2897#define DFSDM1_Channel3_BASE DFSDM1_Channel3_BASE_NS
2898
2899#define DFSDM1_Filter0 DFSDM1_Filter0_NS
2900#define DFSDM1_Filter0_BASE DFSDM1_Filter0_BASE_NS
2901
2902#define DFSDM1_Filter1 DFSDM1_Filter1_NS
2903#define DFSDM1_Filter1_BASE DFSDM1_Filter1_BASE_NS
2904
2905#define DFSDM1_Filter2 DFSDM1_Filter2_NS
2906#define DFSDM1_Filter2_BASE DFSDM1_Filter2_BASE_NS
2907
2908#define DFSDM1_Filter3 DFSDM1_Filter3_NS
2909#define DFSDM1_Filter3_BASE DFSDM1_Filter3_BASE_NS
2910
2911#define CRC CRC_NS
2912#define CRC_BASE CRC_BASE_NS
2913
2914#define TSC TSC_NS
2915#define TSC_BASE TSC_BASE_NS
2916
2917#define ADC1 ADC1_NS
2918#define ADC1_BASE ADC1_BASE_NS
2919
2920#define ADC2 ADC2_NS
2921#define ADC2_BASE ADC2_BASE_NS
2922
2923#define ADC12_COMMON ADC12_COMMON_NS
2924#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS
2925
2926#define AES AES_NS
2927#define AES_BASE AES_BASE_NS
2928
2929#define HASH HASH_NS
2930#define HASH_BASE HASH_BASE_NS
2931
2932#define HASH_DIGEST HASH_DIGEST_NS
2933#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS
2934
2935#define RNG RNG_NS
2936#define RNG_BASE RNG_BASE_NS
2937
2938#define PKA PKA_NS
2939#define PKA_BASE PKA_BASE_NS
2940
2941#define OTFDEC1 OTFDEC1_NS
2942#define OTFDEC1_BASE OTFDEC1_BASE_NS
2943
2944#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS
2945#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS
2946
2947#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS
2948#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS
2949
2950#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS
2951#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS
2952
2953#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS
2954#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS
2955
2956#define SDMMC1 SDMMC1_NS
2957#define SDMMC1_BASE SDMMC1_BASE_NS
2958
2959#define FMC_R_BASE FMC_R_BASE_NS
2960
2961#define FMC_Bank1_R FMC_Bank1_R_NS
2962#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS
2963
2964#define FMC_Bank1E_R FMC_Bank1E_R_NS
2965#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS
2966
2967#define FMC_Bank3_R FMC_Bank3_R_NS
2968#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS
2969
2970#define OCTOSPI1 OCTOSPI1_NS
2971#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS
2972
2973#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2974
2975
2976/******************************************************************************/
2977/* */
2978/* Analog Comparators (COMP) */
2979/* */
2980/******************************************************************************/
2981/********************** Bit definition for COMP_CSR register ****************/
2982#define COMP_CSR_EN_Pos (0U)
2983#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
2984#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
2985
2986#define COMP_CSR_PWRMODE_Pos (2U)
2987#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */
2988#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
2989#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */
2990#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */
2991
2992#define COMP_CSR_INMSEL_Pos (4U)
2993#define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
2994#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
2995#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
2996#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
2997#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
2998
2999#define COMP_CSR_INPSEL_Pos (7U)
3000#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */
3001#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
3002#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
3003#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
3004
3005#define COMP_CSR_WINMODE_Pos (9U)
3006#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */
3007#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
3008
3009#define COMP_CSR_POLARITY_Pos (15U)
3010#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
3011#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
3012
3013#define COMP_CSR_HYST_Pos (16U)
3014#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
3015#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
3016#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
3017#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
3018
3019#define COMP_CSR_BLANKING_Pos (18U)
3020#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
3021#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
3022#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
3023#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
3024#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
3025
3026#define COMP_CSR_BRGEN_Pos (22U)
3027#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
3028#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
3029#define COMP_CSR_SCALEN_Pos (23U)
3030#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
3031#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
3032
3033#define COMP_CSR_VALUE_Pos (30U)
3034#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
3035#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
3036
3037#define COMP_CSR_LOCK_Pos (31U)
3038#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
3039#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
3040
3041/******************************************************************************/
3042/* */
3043/* Analog to Digital Converter */
3044/* */
3045/******************************************************************************/
3046
3047/*
3048 * @brief Specific device feature definitions
3049 */
3050#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
3051
3052/******************** Bit definition for ADC_ISR register *******************/
3053#define ADC_ISR_ADRDY_Pos (0U)
3054#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
3055#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
3056#define ADC_ISR_EOSMP_Pos (1U)
3057#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
3058#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
3059#define ADC_ISR_EOC_Pos (2U)
3060#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
3061#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
3062#define ADC_ISR_EOS_Pos (3U)
3063#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
3064#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
3065#define ADC_ISR_OVR_Pos (4U)
3066#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
3067#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
3068#define ADC_ISR_JEOC_Pos (5U)
3069#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
3070#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
3071#define ADC_ISR_JEOS_Pos (6U)
3072#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
3073#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
3074#define ADC_ISR_AWD1_Pos (7U)
3075#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
3076#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
3077#define ADC_ISR_AWD2_Pos (8U)
3078#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
3079#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
3080#define ADC_ISR_AWD3_Pos (9U)
3081#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
3082#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
3083#define ADC_ISR_JQOVF_Pos (10U)
3084#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
3085#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
3086
3087/******************** Bit definition for ADC_IER register *******************/
3088#define ADC_IER_ADRDYIE_Pos (0U)
3089#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
3090#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
3091#define ADC_IER_EOSMPIE_Pos (1U)
3092#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
3093#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
3094#define ADC_IER_EOCIE_Pos (2U)
3095#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
3096#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
3097#define ADC_IER_EOSIE_Pos (3U)
3098#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
3099#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
3100#define ADC_IER_OVRIE_Pos (4U)
3101#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
3102#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
3103#define ADC_IER_JEOCIE_Pos (5U)
3104#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
3105#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
3106#define ADC_IER_JEOSIE_Pos (6U)
3107#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
3108#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
3109#define ADC_IER_AWD1IE_Pos (7U)
3110#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
3111#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
3112#define ADC_IER_AWD2IE_Pos (8U)
3113#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
3114#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
3115#define ADC_IER_AWD3IE_Pos (9U)
3116#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
3117#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
3118#define ADC_IER_JQOVFIE_Pos (10U)
3119#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
3120#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
3121
3122/******************** Bit definition for ADC_CR register ********************/
3123#define ADC_CR_ADEN_Pos (0U)
3124#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
3125#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
3126#define ADC_CR_ADDIS_Pos (1U)
3127#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
3128#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
3129#define ADC_CR_ADSTART_Pos (2U)
3130#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
3131#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
3132#define ADC_CR_JADSTART_Pos (3U)
3133#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
3134#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
3135#define ADC_CR_ADSTP_Pos (4U)
3136#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
3137#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
3138#define ADC_CR_JADSTP_Pos (5U)
3139#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
3140#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
3141#define ADC_CR_ADVREGEN_Pos (28U)
3142#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
3143#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
3144#define ADC_CR_DEEPPWD_Pos (29U)
3145#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
3146#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
3147#define ADC_CR_ADCALDIF_Pos (30U)
3148#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
3149#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
3150#define ADC_CR_ADCAL_Pos (31U)
3151#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
3152#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
3153
3154/******************** Bit definition for ADC_CFGR register ******************/
3155#define ADC_CFGR_DMAEN_Pos (0U)
3156#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
3157#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
3158#define ADC_CFGR_DMACFG_Pos (1U)
3159#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
3160#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
3161
3162#define ADC_CFGR_DFSDMCFG_Pos (2U)
3163#define ADC_CFGR_DFSDMCFG_Msk (0x1UL << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */
3164#define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk /*!< ADC DFSDM mode configuration */
3165
3166#define ADC_CFGR_RES_Pos (3U)
3167#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
3168#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
3169#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
3170#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
3171
3172#define ADC_CFGR_ALIGN_Pos (5U)
3173#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
3174#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
3175
3176#define ADC_CFGR_EXTSEL_Pos (6U)
3177#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
3178#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
3179#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
3180#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
3181#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
3182#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
3183
3184#define ADC_CFGR_EXTEN_Pos (10U)
3185#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
3186#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
3187#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
3188#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
3189
3190#define ADC_CFGR_OVRMOD_Pos (12U)
3191#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
3192#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
3193#define ADC_CFGR_CONT_Pos (13U)
3194#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
3195#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
3196#define ADC_CFGR_AUTDLY_Pos (14U)
3197#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
3198#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
3199
3200#define ADC_CFGR_DISCEN_Pos (16U)
3201#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
3202#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
3203
3204#define ADC_CFGR_DISCNUM_Pos (17U)
3205#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
3206#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
3207#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
3208#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
3209#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
3210
3211#define ADC_CFGR_JDISCEN_Pos (20U)
3212#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
3213#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
3214#define ADC_CFGR_JQM_Pos (21U)
3215#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
3216#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
3217#define ADC_CFGR_AWD1SGL_Pos (22U)
3218#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
3219#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
3220#define ADC_CFGR_AWD1EN_Pos (23U)
3221#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
3222#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
3223#define ADC_CFGR_JAWD1EN_Pos (24U)
3224#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
3225#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
3226#define ADC_CFGR_JAUTO_Pos (25U)
3227#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
3228#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
3229
3230#define ADC_CFGR_AWD1CH_Pos (26U)
3231#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
3232#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
3233#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
3234#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
3235#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
3236#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
3237#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
3238
3239#define ADC_CFGR_JQDIS_Pos (31U)
3240#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
3241#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
3242
3243/******************** Bit definition for ADC_CFGR2 register *****************/
3244#define ADC_CFGR2_ROVSE_Pos (0U)
3245#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
3246#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
3247#define ADC_CFGR2_JOVSE_Pos (1U)
3248#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
3249#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
3250
3251#define ADC_CFGR2_OVSR_Pos (2U)
3252#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
3253#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
3254#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
3255#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
3256#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
3257
3258#define ADC_CFGR2_OVSS_Pos (5U)
3259#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
3260#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
3261#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
3262#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
3263#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
3264#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
3265
3266#define ADC_CFGR2_TROVS_Pos (9U)
3267#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
3268#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
3269#define ADC_CFGR2_ROVSM_Pos (10U)
3270#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
3271#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
3272
3273/******************** Bit definition for ADC_SMPR1 register *****************/
3274#define ADC_SMPR1_SMP0_Pos (0U)
3275#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
3276#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
3277#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
3278#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
3279#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
3280
3281#define ADC_SMPR1_SMP1_Pos (3U)
3282#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
3283#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
3284#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
3285#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
3286#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
3287
3288#define ADC_SMPR1_SMP2_Pos (6U)
3289#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
3290#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
3291#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
3292#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
3293#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
3294
3295#define ADC_SMPR1_SMP3_Pos (9U)
3296#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
3297#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
3298#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
3299#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
3300#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
3301
3302#define ADC_SMPR1_SMP4_Pos (12U)
3303#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
3304#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
3305#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
3306#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
3307#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
3308
3309#define ADC_SMPR1_SMP5_Pos (15U)
3310#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
3311#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
3312#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
3313#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
3314#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
3315
3316#define ADC_SMPR1_SMP6_Pos (18U)
3317#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
3318#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
3319#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
3320#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
3321#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
3322
3323#define ADC_SMPR1_SMP7_Pos (21U)
3324#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
3325#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
3326#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
3327#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
3328#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
3329
3330#define ADC_SMPR1_SMP8_Pos (24U)
3331#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
3332#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
3333#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
3334#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
3335#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
3336
3337#define ADC_SMPR1_SMP9_Pos (27U)
3338#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
3339#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
3340#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
3341#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
3342#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
3343
3344#define ADC_SMPR1_SMPPLUS_Pos (31U)
3345#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
3346#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
3347
3348/******************** Bit definition for ADC_SMPR2 register *****************/
3349#define ADC_SMPR2_SMP10_Pos (0U)
3350#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
3351#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
3352#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
3353#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
3354#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
3355
3356#define ADC_SMPR2_SMP11_Pos (3U)
3357#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
3358#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
3359#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
3360#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
3361#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
3362
3363#define ADC_SMPR2_SMP12_Pos (6U)
3364#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
3365#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
3366#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
3367#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
3368#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
3369
3370#define ADC_SMPR2_SMP13_Pos (9U)
3371#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
3372#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
3373#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
3374#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
3375#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
3376
3377#define ADC_SMPR2_SMP14_Pos (12U)
3378#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
3379#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
3380#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
3381#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
3382#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
3383
3384#define ADC_SMPR2_SMP15_Pos (15U)
3385#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
3386#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
3387#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
3388#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
3389#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
3390
3391#define ADC_SMPR2_SMP16_Pos (18U)
3392#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
3393#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
3394#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
3395#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
3396#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
3397
3398#define ADC_SMPR2_SMP17_Pos (21U)
3399#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
3400#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
3401#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
3402#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
3403#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
3404
3405#define ADC_SMPR2_SMP18_Pos (24U)
3406#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
3407#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
3408#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
3409#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
3410#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
3411
3412/******************** Bit definition for ADC_TR1 register *******************/
3413#define ADC_TR1_LT1_Pos (0U)
3414#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
3415#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
3416#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
3417#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
3418#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
3419#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
3420#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
3421#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
3422#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
3423#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
3424#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
3425#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
3426#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
3427#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
3428
3429#define ADC_TR1_HT1_Pos (16U)
3430#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
3431#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
3432#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
3433#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
3434#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
3435#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
3436#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
3437#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
3438#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
3439#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
3440#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
3441#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
3442#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
3443#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
3444
3445/******************** Bit definition for ADC_TR2 register *******************/
3446#define ADC_TR2_LT2_Pos (0U)
3447#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
3448#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
3449#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
3450#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
3451#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
3452#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
3453#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
3454#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
3455#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
3456#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
3457
3458#define ADC_TR2_HT2_Pos (16U)
3459#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
3460#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
3461#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
3462#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
3463#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
3464#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
3465#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
3466#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
3467#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
3468#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
3469
3470/******************** Bit definition for ADC_TR3 register *******************/
3471#define ADC_TR3_LT3_Pos (0U)
3472#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
3473#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
3474#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
3475#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
3476#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
3477#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
3478#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
3479#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
3480#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
3481#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
3482
3483#define ADC_TR3_HT3_Pos (16U)
3484#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
3485#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
3486#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
3487#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
3488#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
3489#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
3490#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
3491#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
3492#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
3493#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
3494
3495/******************** Bit definition for ADC_SQR1 register ******************/
3496#define ADC_SQR1_L_Pos (0U)
3497#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
3498#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
3499#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
3500#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
3501#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
3502#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
3503
3504#define ADC_SQR1_SQ1_Pos (6U)
3505#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
3506#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
3507#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
3508#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
3509#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
3510#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
3511#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
3512
3513#define ADC_SQR1_SQ2_Pos (12U)
3514#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
3515#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
3516#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
3517#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
3518#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
3519#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
3520#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
3521
3522#define ADC_SQR1_SQ3_Pos (18U)
3523#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
3524#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
3525#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
3526#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
3527#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
3528#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
3529#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
3530
3531#define ADC_SQR1_SQ4_Pos (24U)
3532#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
3533#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
3534#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
3535#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
3536#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
3537#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
3538#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
3539
3540/******************** Bit definition for ADC_SQR2 register ******************/
3541#define ADC_SQR2_SQ5_Pos (0U)
3542#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
3543#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
3544#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
3545#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
3546#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
3547#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
3548#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
3549
3550#define ADC_SQR2_SQ6_Pos (6U)
3551#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
3552#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
3553#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
3554#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
3555#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
3556#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
3557#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
3558
3559#define ADC_SQR2_SQ7_Pos (12U)
3560#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
3561#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
3562#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
3563#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
3564#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
3565#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
3566#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
3567
3568#define ADC_SQR2_SQ8_Pos (18U)
3569#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
3570#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
3571#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
3572#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
3573#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
3574#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
3575#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
3576
3577#define ADC_SQR2_SQ9_Pos (24U)
3578#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
3579#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
3580#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
3581#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
3582#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
3583#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
3584#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
3585
3586/******************** Bit definition for ADC_SQR3 register ******************/
3587#define ADC_SQR3_SQ10_Pos (0U)
3588#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
3589#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
3590#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
3591#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
3592#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
3593#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
3594#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
3595
3596#define ADC_SQR3_SQ11_Pos (6U)
3597#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
3598#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
3599#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
3600#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
3601#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
3602#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
3603#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
3604
3605#define ADC_SQR3_SQ12_Pos (12U)
3606#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
3607#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
3608#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
3609#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
3610#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
3611#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
3612#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
3613
3614#define ADC_SQR3_SQ13_Pos (18U)
3615#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
3616#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
3617#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
3618#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
3619#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
3620#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
3621#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
3622
3623#define ADC_SQR3_SQ14_Pos (24U)
3624#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
3625#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
3626#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
3627#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
3628#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
3629#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
3630#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
3631
3632/******************** Bit definition for ADC_SQR4 register ******************/
3633#define ADC_SQR4_SQ15_Pos (0U)
3634#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
3635#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
3636#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
3637#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
3638#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
3639#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
3640#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
3641
3642#define ADC_SQR4_SQ16_Pos (6U)
3643#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
3644#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
3645#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
3646#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
3647#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
3648#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
3649#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
3650
3651/******************** Bit definition for ADC_DR register ********************/
3652#define ADC_DR_RDATA_Pos (0U)
3653#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
3654#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
3655#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
3656#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
3657#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
3658#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
3659#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
3660#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
3661#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
3662#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
3663#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
3664#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
3665#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
3666#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
3667#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
3668#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
3669#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
3670#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
3671
3672/******************** Bit definition for ADC_JSQR register ******************/
3673#define ADC_JSQR_JL_Pos (0U)
3674#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
3675#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
3676#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
3677#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
3678
3679#define ADC_JSQR_JEXTSEL_Pos (2U)
3680#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
3681#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
3682#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
3683#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
3684#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
3685#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
3686
3687#define ADC_JSQR_JEXTEN_Pos (6U)
3688#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
3689#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
3690#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
3691#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
3692
3693#define ADC_JSQR_JSQ1_Pos (8U)
3694#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
3695#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
3696#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
3697#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
3698#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
3699#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
3700#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
3701
3702#define ADC_JSQR_JSQ2_Pos (14U)
3703#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
3704#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
3705#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
3706#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
3707#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
3708#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
3709#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
3710
3711#define ADC_JSQR_JSQ3_Pos (20U)
3712#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
3713#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
3714#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
3715#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
3716#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
3717#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
3718#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
3719
3720#define ADC_JSQR_JSQ4_Pos (26U)
3721#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
3722#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
3723#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
3724#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
3725#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
3726#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
3727#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
3728
3729/******************** Bit definition for ADC_OFR1 register ******************/
3730#define ADC_OFR1_OFFSET1_Pos (0U)
3731#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
3732#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
3733#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
3734#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
3735#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
3736#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
3737#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
3738#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
3739#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
3740#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
3741#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
3742#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
3743#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
3744#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
3745
3746#define ADC_OFR1_OFFSET1_CH_Pos (26U)
3747#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
3748#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
3749#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
3750#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
3751#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
3752#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
3753#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
3754
3755#define ADC_OFR1_OFFSET1_EN_Pos (31U)
3756#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
3757#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
3758
3759/******************** Bit definition for ADC_OFR2 register ******************/
3760#define ADC_OFR2_OFFSET2_Pos (0U)
3761#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
3762#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
3763#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
3764#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
3765#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
3766#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
3767#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
3768#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
3769#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
3770#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
3771#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
3772#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
3773#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
3774#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
3775
3776#define ADC_OFR2_OFFSET2_CH_Pos (26U)
3777#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
3778#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
3779#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
3780#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
3781#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
3782#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
3783#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
3784
3785#define ADC_OFR2_OFFSET2_EN_Pos (31U)
3786#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
3787#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
3788
3789/******************** Bit definition for ADC_OFR3 register ******************/
3790#define ADC_OFR3_OFFSET3_Pos (0U)
3791#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
3792#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
3793#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
3794#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
3795#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
3796#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
3797#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
3798#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
3799#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
3800#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
3801#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
3802#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
3803#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
3804#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
3805
3806#define ADC_OFR3_OFFSET3_CH_Pos (26U)
3807#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
3808#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
3809#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
3810#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
3811#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
3812#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
3813#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
3814
3815#define ADC_OFR3_OFFSET3_EN_Pos (31U)
3816#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
3817#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
3818
3819/******************** Bit definition for ADC_OFR4 register ******************/
3820#define ADC_OFR4_OFFSET4_Pos (0U)
3821#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
3822#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
3823#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
3824#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
3825#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
3826#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
3827#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
3828#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
3829#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
3830#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
3831#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
3832#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
3833#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
3834#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
3835
3836#define ADC_OFR4_OFFSET4_CH_Pos (26U)
3837#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
3838#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
3839#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
3840#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
3841#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
3842#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
3843#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
3844
3845#define ADC_OFR4_OFFSET4_EN_Pos (31U)
3846#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
3847#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
3848
3849/******************** Bit definition for ADC_JDR1 register ******************/
3850#define ADC_JDR1_JDATA_Pos (0U)
3851#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
3852#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
3853#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
3854#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
3855#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
3856#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
3857#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
3858#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
3859#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
3860#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
3861#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
3862#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
3863#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
3864#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
3865#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
3866#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
3867#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
3868#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
3869
3870/******************** Bit definition for ADC_JDR2 register ******************/
3871#define ADC_JDR2_JDATA_Pos (0U)
3872#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
3873#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
3874#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
3875#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
3876#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
3877#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
3878#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
3879#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
3880#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
3881#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
3882#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
3883#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
3884#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
3885#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
3886#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
3887#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
3888#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
3889#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
3890
3891/******************** Bit definition for ADC_JDR3 register ******************/
3892#define ADC_JDR3_JDATA_Pos (0U)
3893#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
3894#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
3895#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
3896#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
3897#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
3898#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
3899#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
3900#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
3901#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
3902#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
3903#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
3904#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
3905#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
3906#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
3907#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
3908#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
3909#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
3910#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
3911
3912/******************** Bit definition for ADC_JDR4 register ******************/
3913#define ADC_JDR4_JDATA_Pos (0U)
3914#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
3915#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
3916#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
3917#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
3918#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
3919#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
3920#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
3921#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
3922#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
3923#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
3924#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
3925#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
3926#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
3927#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
3928#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
3929#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
3930#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
3931#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
3932
3933/******************** Bit definition for ADC_AWD2CR register ****************/
3934#define ADC_AWD2CR_AWD2CH_Pos (0U)
3935#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
3936#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
3937#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
3938#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
3939#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
3940#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
3941#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
3942#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
3943#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
3944#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
3945#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
3946#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
3947#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
3948#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
3949#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
3950#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
3951#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
3952#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
3953#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
3954#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
3955#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
3956
3957/******************** Bit definition for ADC_AWD3CR register ****************/
3958#define ADC_AWD3CR_AWD3CH_Pos (0U)
3959#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
3960#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
3961#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
3962#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
3963#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
3964#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
3965#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
3966#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
3967#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
3968#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
3969#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
3970#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
3971#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
3972#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
3973#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
3974#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
3975#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
3976#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
3977#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
3978#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
3979#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
3980
3981/******************** Bit definition for ADC_DIFSEL register ****************/
3982#define ADC_DIFSEL_DIFSEL_Pos (0U)
3983#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
3984#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
3985#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
3986#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
3987#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
3988#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
3989#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
3990#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
3991#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
3992#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
3993#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
3994#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
3995#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
3996#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
3997#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
3998#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
3999#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
4000#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
4001#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
4002#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
4003#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
4004
4005/******************** Bit definition for ADC_CALFACT register ***************/
4006#define ADC_CALFACT_CALFACT_S_Pos (0U)
4007#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
4008#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
4009#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
4010#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
4011#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
4012#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
4013#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
4014#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
4015#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
4016
4017#define ADC_CALFACT_CALFACT_D_Pos (16U)
4018#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
4019#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
4020#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
4021#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
4022#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
4023#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
4024#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
4025#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
4026#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
4027
4028/************************* ADC Common registers *****************************/
4029/******************** Bit definition for ADC_CSR register *******************/
4030#define ADC_CSR_ADRDY_MST_Pos (0U)
4031#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
4032#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
4033#define ADC_CSR_EOSMP_MST_Pos (1U)
4034#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
4035#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
4036#define ADC_CSR_EOC_MST_Pos (2U)
4037#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
4038#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
4039#define ADC_CSR_EOS_MST_Pos (3U)
4040#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
4041#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
4042#define ADC_CSR_OVR_MST_Pos (4U)
4043#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
4044#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
4045#define ADC_CSR_JEOC_MST_Pos (5U)
4046#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
4047#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
4048#define ADC_CSR_JEOS_MST_Pos (6U)
4049#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
4050#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
4051#define ADC_CSR_AWD1_MST_Pos (7U)
4052#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
4053#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
4054#define ADC_CSR_AWD2_MST_Pos (8U)
4055#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
4056#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
4057#define ADC_CSR_AWD3_MST_Pos (9U)
4058#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
4059#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
4060#define ADC_CSR_JQOVF_MST_Pos (10U)
4061#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
4062#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
4063
4064#define ADC_CSR_ADRDY_SLV_Pos (16U)
4065#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
4066#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
4067#define ADC_CSR_EOSMP_SLV_Pos (17U)
4068#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
4069#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
4070#define ADC_CSR_EOC_SLV_Pos (18U)
4071#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
4072#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
4073#define ADC_CSR_EOS_SLV_Pos (19U)
4074#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
4075#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
4076#define ADC_CSR_OVR_SLV_Pos (20U)
4077#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
4078#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
4079#define ADC_CSR_JEOC_SLV_Pos (21U)
4080#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
4081#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
4082#define ADC_CSR_JEOS_SLV_Pos (22U)
4083#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
4084#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
4085#define ADC_CSR_AWD1_SLV_Pos (23U)
4086#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
4087#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
4088#define ADC_CSR_AWD2_SLV_Pos (24U)
4089#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
4090#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
4091#define ADC_CSR_AWD3_SLV_Pos (25U)
4092#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
4093#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
4094#define ADC_CSR_JQOVF_SLV_Pos (26U)
4095#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
4096#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
4097
4098/******************** Bit definition for ADC_CCR register *******************/
4099#define ADC_CCR_DUAL_Pos (0U)
4100#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
4101#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
4102#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
4103#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
4104#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
4105#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
4106#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
4107
4108#define ADC_CCR_DELAY_Pos (8U)
4109#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
4110#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
4111#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
4112#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
4113#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
4114#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
4115
4116#define ADC_CCR_DMACFG_Pos (13U)
4117#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
4118#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
4119
4120#define ADC_CCR_MDMA_Pos (14U)
4121#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
4122#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
4123#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
4124#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
4125
4126#define ADC_CCR_CKMODE_Pos (16U)
4127#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
4128#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
4129#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
4130#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
4131
4132#define ADC_CCR_PRESC_Pos (18U)
4133#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
4134#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
4135#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
4136#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
4137#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
4138#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
4139
4140#define ADC_CCR_VREFEN_Pos (22U)
4141#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
4142#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
4143#define ADC_CCR_TSEN_Pos (23U)
4144#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
4145#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
4146#define ADC_CCR_VBATEN_Pos (24U)
4147#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
4148#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
4149
4150/******************** Bit definition for ADC_CDR register *******************/
4151#define ADC_CDR_RDATA_MST_Pos (0U)
4152#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
4153#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
4154#define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
4155#define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
4156#define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
4157#define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
4158#define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
4159#define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
4160#define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
4161#define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
4162#define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
4163#define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
4164#define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
4165#define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
4166#define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
4167#define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
4168#define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
4169#define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
4170
4171#define ADC_CDR_RDATA_SLV_Pos (16U)
4172#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
4173#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
4174#define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
4175#define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
4176#define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
4177#define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
4178#define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
4179#define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
4180#define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
4181#define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
4182#define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
4183#define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
4184#define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
4185#define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
4186#define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
4187#define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
4188#define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
4189#define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
4190
4191/******************************************************************************/
4192/* */
4193/* CRC calculation unit */
4194/* */
4195/******************************************************************************/
4196/******************* Bit definition for CRC_DR register *********************/
4197#define CRC_DR_DR_Pos (0U)
4198#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
4199#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
4200
4201/******************* Bit definition for CRC_IDR register ********************/
4202#define CRC_IDR_IDR_Pos (0U)
4203#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
4204#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */
4205
4206/******************** Bit definition for CRC_CR register ********************/
4207#define CRC_CR_RESET_Pos (0U)
4208#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
4209#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
4210#define CRC_CR_POLYSIZE_Pos (3U)
4211#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
4212#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
4213#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
4214#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
4215#define CRC_CR_REV_IN_Pos (5U)
4216#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
4217#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
4218#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
4219#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
4220#define CRC_CR_REV_OUT_Pos (7U)
4221#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
4222#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
4223
4224/******************* Bit definition for CRC_INIT register *******************/
4225#define CRC_INIT_INIT_Pos (0U)
4226#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
4227#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
4228
4229/******************* Bit definition for CRC_POL register ********************/
4230#define CRC_POL_POL_Pos (0U)
4231#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
4232#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
4233
4234/******************************************************************************/
4235/* */
4236/* CRS Clock Recovery System */
4237/******************************************************************************/
4238/******************* Bit definition for CRS_CR register *********************/
4239#define CRS_CR_SYNCOKIE_Pos (0U)
4240#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
4241#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
4242#define CRS_CR_SYNCWARNIE_Pos (1U)
4243#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
4244#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
4245#define CRS_CR_ERRIE_Pos (2U)
4246#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
4247#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
4248#define CRS_CR_ESYNCIE_Pos (3U)
4249#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
4250#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
4251#define CRS_CR_CEN_Pos (5U)
4252#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
4253#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
4254#define CRS_CR_AUTOTRIMEN_Pos (6U)
4255#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
4256#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
4257#define CRS_CR_SWSYNC_Pos (7U)
4258#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
4259#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
4260#define CRS_CR_TRIM_Pos (8U)
4261#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */
4262#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
4263
4264/******************* Bit definition for CRS_CFGR register *********************/
4265#define CRS_CFGR_RELOAD_Pos (0U)
4266#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
4267#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
4268#define CRS_CFGR_FELIM_Pos (16U)
4269#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
4270#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
4271
4272#define CRS_CFGR_SYNCDIV_Pos (24U)
4273#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
4274#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
4275#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
4276#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
4277#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
4278
4279#define CRS_CFGR_SYNCSRC_Pos (28U)
4280#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
4281#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
4282#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
4283#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
4284
4285#define CRS_CFGR_SYNCPOL_Pos (31U)
4286#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
4287#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
4288
4289/******************* Bit definition for CRS_ISR register *********************/
4290#define CRS_ISR_SYNCOKF_Pos (0U)
4291#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
4292#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
4293#define CRS_ISR_SYNCWARNF_Pos (1U)
4294#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
4295#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
4296#define CRS_ISR_ERRF_Pos (2U)
4297#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
4298#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
4299#define CRS_ISR_ESYNCF_Pos (3U)
4300#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
4301#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
4302#define CRS_ISR_SYNCERR_Pos (8U)
4303#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
4304#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
4305#define CRS_ISR_SYNCMISS_Pos (9U)
4306#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
4307#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
4308#define CRS_ISR_TRIMOVF_Pos (10U)
4309#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
4310#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
4311#define CRS_ISR_FEDIR_Pos (15U)
4312#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
4313#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
4314#define CRS_ISR_FECAP_Pos (16U)
4315#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
4316#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
4317
4318/******************* Bit definition for CRS_ICR register *********************/
4319#define CRS_ICR_SYNCOKC_Pos (0U)
4320#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
4321#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
4322#define CRS_ICR_SYNCWARNC_Pos (1U)
4323#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
4324#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
4325#define CRS_ICR_ERRC_Pos (2U)
4326#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
4327#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
4328#define CRS_ICR_ESYNCC_Pos (3U)
4329#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
4330#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
4331
4332/******************************************************************************/
4333/* */
4334/* Advanced Encryption Standard (AES) */
4335/* */
4336/******************************************************************************/
4337/******************* Bit definition for AES_CR register *********************/
4338#define AES_CR_EN_Pos (0U)
4339#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */
4340#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
4341#define AES_CR_DATATYPE_Pos (1U)
4342#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
4343#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
4344#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
4345#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
4346
4347#define AES_CR_MODE_Pos (3U)
4348#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */
4349#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
4350#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */
4351#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */
4352
4353#define AES_CR_CHMOD_Pos (5U)
4354#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */
4355#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
4356#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
4357#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
4358#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */
4359
4360#define AES_CR_CCFC_Pos (7U)
4361#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */
4362#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
4363#define AES_CR_ERRC_Pos (8U)
4364#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */
4365#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
4366#define AES_CR_CCFIE_Pos (9U)
4367#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */
4368#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */
4369#define AES_CR_ERRIE_Pos (10U)
4370#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
4371#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
4372#define AES_CR_DMAINEN_Pos (11U)
4373#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
4374#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */
4375#define AES_CR_DMAOUTEN_Pos (12U)
4376#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
4377#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */
4378
4379#define AES_CR_GCMPH_Pos (13U)
4380#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */
4381#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */
4382#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */
4383#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */
4384
4385#define AES_CR_KEYSIZE_Pos (18U)
4386#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */
4387#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */
4388#define AES_CR_NPBLB_Pos (20U)
4389#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */
4390#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */
4391#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */
4392#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */
4393#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */
4394#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */
4395
4396/******************* Bit definition for AES_SR register *********************/
4397#define AES_SR_CCF_Pos (0U)
4398#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */
4399#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
4400#define AES_SR_RDERR_Pos (1U)
4401#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */
4402#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
4403#define AES_SR_WRERR_Pos (2U)
4404#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */
4405#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
4406#define AES_SR_BUSY_Pos (3U)
4407#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */
4408#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */
4409
4410/******************* Bit definition for AES_DINR register *******************/
4411#define AES_DINR_Pos (0U)
4412#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */
4413#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
4414
4415/******************* Bit definition for AES_DOUTR register ******************/
4416#define AES_DOUTR_Pos (0U)
4417#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */
4418#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
4419
4420/******************* Bit definition for AES_KEYR0 register ******************/
4421#define AES_KEYR0_Pos (0U)
4422#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */
4423#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
4424
4425/******************* Bit definition for AES_KEYR1 register ******************/
4426#define AES_KEYR1_Pos (0U)
4427#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */
4428#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
4429
4430/******************* Bit definition for AES_KEYR2 register ******************/
4431#define AES_KEYR2_Pos (0U)
4432#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */
4433#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
4434
4435/******************* Bit definition for AES_KEYR3 register ******************/
4436#define AES_KEYR3_Pos (0U)
4437#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */
4438#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
4439
4440/******************* Bit definition for AES_KEYR4 register ******************/
4441#define AES_KEYR4_Pos (0U)
4442#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */
4443#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */
4444
4445/******************* Bit definition for AES_KEYR5 register ******************/
4446#define AES_KEYR5_Pos (0U)
4447#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */
4448#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */
4449
4450/******************* Bit definition for AES_KEYR6 register ******************/
4451#define AES_KEYR6_Pos (0U)
4452#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */
4453#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */
4454
4455/******************* Bit definition for AES_KEYR7 register ******************/
4456#define AES_KEYR7_Pos (0U)
4457#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */
4458#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */
4459
4460/******************* Bit definition for AES_IVR0 register ******************/
4461#define AES_IVR0_Pos (0U)
4462#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */
4463#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
4464
4465/******************* Bit definition for AES_IVR1 register ******************/
4466#define AES_IVR1_Pos (0U)
4467#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */
4468#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
4469
4470/******************* Bit definition for AES_IVR2 register ******************/
4471#define AES_IVR2_Pos (0U)
4472#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */
4473#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
4474
4475/******************* Bit definition for AES_IVR3 register ******************/
4476#define AES_IVR3_Pos (0U)
4477#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */
4478#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
4479
4480/******************* Bit definition for AES_SUSP0R register ******************/
4481#define AES_SUSP0R_Pos (0U)
4482#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */
4483#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */
4484
4485/******************* Bit definition for AES_SUSP1R register ******************/
4486#define AES_SUSP1R_Pos (0U)
4487#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */
4488#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */
4489
4490/******************* Bit definition for AES_SUSP2R register ******************/
4491#define AES_SUSP2R_Pos (0U)
4492#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */
4493#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */
4494
4495/******************* Bit definition for AES_SUSP3R register ******************/
4496#define AES_SUSP3R_Pos (0U)
4497#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */
4498#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */
4499
4500/******************* Bit definition for AES_SUSP4R register ******************/
4501#define AES_SUSP4R_Pos (0U)
4502#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */
4503#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */
4504
4505/******************* Bit definition for AES_SUSP5R register ******************/
4506#define AES_SUSP5R_Pos (0U)
4507#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */
4508#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */
4509
4510/******************* Bit definition for AES_SUSP6R register ******************/
4511#define AES_SUSP6R_Pos (0U)
4512#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */
4513#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */
4514
4515/******************* Bit definition for AES_SUSP7R register ******************/
4516#define AES_SUSP7R_Pos (0U)
4517#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */
4518#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */
4519
4520
4521/******************************************************************************/
4522/* */
4523/* Digital to Analog Converter */
4524/* */
4525/******************************************************************************/
4526/*
4527 * @brief Specific device feature definitions
4528 */
4529#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
4530
4531/******************** Bit definition for DAC_CR register ********************/
4532#define DAC_CR_EN1_Pos (0U)
4533#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
4534#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
4535#define DAC_CR_TEN1_Pos (1U)
4536#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
4537#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
4538
4539#define DAC_CR_TSEL1_Pos (2U)
4540#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
4541#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
4542#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
4543#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
4544#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
4545#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
4546
4547#define DAC_CR_WAVE1_Pos (6U)
4548#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
4549#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
4550#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
4551#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
4552
4553#define DAC_CR_MAMP1_Pos (8U)
4554#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
4555#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
4556#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
4557#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
4558#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
4559#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
4560
4561#define DAC_CR_DMAEN1_Pos (12U)
4562#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
4563#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
4564#define DAC_CR_DMAUDRIE1_Pos (13U)
4565#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
4566#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
4567#define DAC_CR_CEN1_Pos (14U)
4568#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
4569#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
4570
4571#define DAC_CR_HFSEL_Pos (15U)
4572#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
4573#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/
4574
4575#define DAC_CR_EN2_Pos (16U)
4576#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
4577#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
4578#define DAC_CR_TEN2_Pos (17U)
4579#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
4580#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
4581
4582#define DAC_CR_TSEL2_Pos (18U)
4583#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
4584#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
4585#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
4586#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
4587#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
4588#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
4589
4590#define DAC_CR_WAVE2_Pos (22U)
4591#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
4592#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
4593#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
4594#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
4595
4596#define DAC_CR_MAMP2_Pos (24U)
4597#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
4598#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
4599#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
4600#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
4601#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
4602#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
4603
4604#define DAC_CR_DMAEN2_Pos (28U)
4605#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
4606#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
4607#define DAC_CR_DMAUDRIE2_Pos (29U)
4608#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
4609#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
4610#define DAC_CR_CEN2_Pos (30U)
4611#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
4612#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
4613
4614/***************** Bit definition for DAC_SWTRIGR register ******************/
4615#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
4616#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
4617#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
4618#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
4619#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
4620#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
4621
4622/***************** Bit definition for DAC_DHR12R1 register ******************/
4623#define DAC_DHR12R1_DACC1DHR_Pos (0U)
4624#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
4625#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
4626
4627/***************** Bit definition for DAC_DHR12L1 register ******************/
4628#define DAC_DHR12L1_DACC1DHR_Pos (4U)
4629#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
4630#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
4631
4632/****************** Bit definition for DAC_DHR8R1 register ******************/
4633#define DAC_DHR8R1_DACC1DHR_Pos (0U)
4634#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
4635#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
4636
4637/***************** Bit definition for DAC_DHR12R2 register ******************/
4638#define DAC_DHR12R2_DACC2DHR_Pos (0U)
4639#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
4640#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
4641
4642/***************** Bit definition for DAC_DHR12L2 register ******************/
4643#define DAC_DHR12L2_DACC2DHR_Pos (4U)
4644#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
4645#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
4646
4647/****************** Bit definition for DAC_DHR8R2 register ******************/
4648#define DAC_DHR8R2_DACC2DHR_Pos (0U)
4649#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
4650#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
4651
4652/***************** Bit definition for DAC_DHR12RD register ******************/
4653#define DAC_DHR12RD_DACC1DHR_Pos (0U)
4654#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
4655#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
4656#define DAC_DHR12RD_DACC2DHR_Pos (16U)
4657#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
4658#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
4659
4660/***************** Bit definition for DAC_DHR12LD register ******************/
4661#define DAC_DHR12LD_DACC1DHR_Pos (4U)
4662#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
4663#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
4664#define DAC_DHR12LD_DACC2DHR_Pos (20U)
4665#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
4666#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
4667
4668/****************** Bit definition for DAC_DHR8RD register ******************/
4669#define DAC_DHR8RD_DACC1DHR_Pos (0U)
4670#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
4671#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
4672#define DAC_DHR8RD_DACC2DHR_Pos (8U)
4673#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
4674#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
4675
4676/******************* Bit definition for DAC_DOR1 register *******************/
4677#define DAC_DOR1_DACC1DOR_Pos (0U)
4678#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
4679#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
4680
4681/******************* Bit definition for DAC_DOR2 register *******************/
4682#define DAC_DOR2_DACC2DOR_Pos (0U)
4683#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
4684#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
4685
4686/******************** Bit definition for DAC_SR register ********************/
4687#define DAC_SR_DMAUDR1_Pos (13U)
4688#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
4689#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
4690#define DAC_SR_CAL_FLAG1_Pos (14U)
4691#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
4692#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
4693#define DAC_SR_BWST1_Pos (15U)
4694#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
4695#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
4696
4697#define DAC_SR_DMAUDR2_Pos (29U)
4698#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
4699#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
4700#define DAC_SR_CAL_FLAG2_Pos (30U)
4701#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
4702#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
4703#define DAC_SR_BWST2_Pos (31U)
4704#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
4705#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
4706
4707/******************* Bit definition for DAC_CCR register ********************/
4708#define DAC_CCR_OTRIM1_Pos (0U)
4709#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
4710#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
4711#define DAC_CCR_OTRIM2_Pos (16U)
4712#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
4713#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
4714
4715/******************* Bit definition for DAC_MCR register *******************/
4716#define DAC_MCR_MODE1_Pos (0U)
4717#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
4718#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
4719#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
4720#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
4721#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
4722
4723#define DAC_MCR_MODE2_Pos (16U)
4724#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
4725#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
4726#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
4727#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
4728#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
4729
4730/****************** Bit definition for DAC_SHSR1 register ******************/
4731#define DAC_SHSR1_TSAMPLE1_Pos (0U)
4732#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
4733#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
4734
4735/****************** Bit definition for DAC_SHSR2 register ******************/
4736#define DAC_SHSR2_TSAMPLE2_Pos (0U)
4737#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
4738#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
4739
4740/****************** Bit definition for DAC_SHHR register ******************/
4741#define DAC_SHHR_THOLD1_Pos (0U)
4742#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
4743#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
4744#define DAC_SHHR_THOLD2_Pos (16U)
4745#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
4746#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
4747
4748/****************** Bit definition for DAC_SHRR register ******************/
4749#define DAC_SHRR_TREFRESH1_Pos (0U)
4750#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
4751#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
4752#define DAC_SHRR_TREFRESH2_Pos (16U)
4753#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
4754#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
4755
4756/******************************************************************************/
4757/* */
4758/* Debug MCU */
4759/* */
4760/******************************************************************************/
4761/******************** Bit definition for DBGMCU_IDCODE register *************/
4762#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
4763#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
4764#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
4765#define DBGMCU_IDCODE_REV_ID_Pos (16U)
4766#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
4767#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
4768
4769/******************** Bit definition for DBGMCU_CR register *****************/
4770#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
4771#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
4772#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
4773#define DBGMCU_CR_DBG_STOP_Pos (1U)
4774#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
4775#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
4776#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
4777#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
4778#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
4779#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
4780#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
4781#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
4782
4783#define DBGMCU_CR_TRACE_MODE_Pos (6U)
4784#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
4785#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
4786#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
4787#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
4788
4789/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
4790#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
4791#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
4792#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
4793#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
4794#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
4795#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
4796#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
4797#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
4798#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
4799#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
4800#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x00000008 */
4801#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
4802#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
4803#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
4804#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
4805#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
4806#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
4807#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
4808#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
4809#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
4810#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
4811#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
4812#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
4813#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
4814#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
4815#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
4816#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
4817#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
4818#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
4819#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
4820#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
4821#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
4822#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
4823#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
4824#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x00800000 */
4825#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
4826#define DBGMCU_APB1FZR1_DBG_FDCAN1_STOP_Pos (25U)
4827#define DBGMCU_APB1FZR1_DBG_FDCAN1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_FDCAN1_STOP_Pos)/*!< 0x02000000 */
4828#define DBGMCU_APB1FZR1_DBG_FDCAN1_STOP DBGMCU_APB1FZR1_DBG_FDCAN1_STOP_Msk
4829#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
4830#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
4831#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
4832
4833/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
4834#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos (1U)
4835#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos)/*!< 0x00000002 */
4836#define DBGMCU_APB1FZR2_DBG_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
4837#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
4838#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)/*!< 0x00000020 */
4839#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
4840#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Pos (6U)
4841#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Pos)/*!< 0x00000040 */
4842#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk
4843
4844/******************** Bit definition for DBGMCU_APB2FZ register ************/
4845#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
4846#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
4847#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
4848#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
4849#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
4850#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
4851#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
4852#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
4853#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
4854#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
4855#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
4856#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
4857#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
4858#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
4859#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
4860
4861/******************************************************************************/
4862/* */
4863/* Digital Filter for Sigma Delta Modulators */
4864/* */
4865/******************************************************************************/
4866
4867/**************** DFSDM channel configuration registers ********************/
4868
4869/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
4870#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
4871#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
4872#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
4873#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
4874#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
4875#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
4876#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
4877#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
4878#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
4879#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
4880#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
4881#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
4882#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
4883#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
4884#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
4885#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
4886#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
4887#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
4888#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
4889#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
4890#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
4891#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
4892#define DFSDM_CHCFGR1_CHEN_Pos (7U)
4893#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
4894#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
4895#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
4896#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
4897#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
4898#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
4899#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
4900#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
4901#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
4902#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
4903#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
4904#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
4905#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
4906#define DFSDM_CHCFGR1_SITP_Pos (0U)
4907#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
4908#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
4909#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
4910#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
4911
4912/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
4913#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
4914#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)/*!< 0xFFFFFF00 */
4915#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
4916#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
4917#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
4918#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
4919
4920/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
4921#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
4922#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
4923#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
4924#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
4925#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
4926#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
4927#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
4928#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
4929#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
4930#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
4931#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
4932#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
4933#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
4934#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
4935
4936/**************** Bit definition for DFSDM_CHWDATR register *******************/
4937#define DFSDM_CHWDATR_WDATA_Pos (0U)
4938#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
4939#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
4940
4941/**************** Bit definition for DFSDM_CHDATINR register *****************/
4942#define DFSDM_CHDATINR_INDAT0_Pos (0U)
4943#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)/*!< 0x0000FFFF */
4944#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
4945#define DFSDM_CHDATINR_INDAT1_Pos (16U)
4946#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)/*!< 0xFFFF0000 */
4947#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
4948
4949/**************** Bit definition for DFSDM_CHDLYR register *******************/
4950#define DFSDM_CHDLYR_PLSSKP_Pos (0U)
4951#define DFSDM_CHDLYR_PLSSKP_Msk (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos) /*!< 0x0000003F */
4952#define DFSDM_CHDLYR_PLSSKP DFSDM_CHDLYR_PLSSKP_Msk /*!< PLSSKP[5:0] Number of input serial samples that will be skipped */
4953
4954/************************ DFSDM module registers ****************************/
4955
4956/***************** Bit definition for DFSDM_FLTCR1 register *******************/
4957#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
4958#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
4959#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
4960#define DFSDM_FLTCR1_FAST_Pos (29U)
4961#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
4962#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
4963#define DFSDM_FLTCR1_RCH_Pos (24U)
4964#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
4965#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
4966#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
4967#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
4968#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
4969#define DFSDM_FLTCR1_RSYNC_Pos (19U)
4970#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
4971#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
4972#define DFSDM_FLTCR1_RCONT_Pos (18U)
4973#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
4974#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
4975#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
4976#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
4977#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
4978#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
4979#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
4980#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
4981#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
4982#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
4983#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
4984#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
4985#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
4986#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
4987#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
4988#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
4989#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
4990#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
4991#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
4992#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
4993#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
4994#define DFSDM_FLTCR1_JSCAN_Pos (4U)
4995#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
4996#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
4997#define DFSDM_FLTCR1_JSYNC_Pos (3U)
4998#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
4999#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
5000#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
5001#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
5002#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
5003#define DFSDM_FLTCR1_DFEN_Pos (0U)
5004#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
5005#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
5006
5007/***************** Bit definition for DFSDM_FLTCR2 register *******************/
5008#define DFSDM_FLTCR2_AWDCH_Pos (16U)
5009#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
5010#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
5011#define DFSDM_FLTCR2_EXCH_Pos (8U)
5012#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
5013#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
5014#define DFSDM_FLTCR2_CKABIE_Pos (6U)
5015#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
5016#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
5017#define DFSDM_FLTCR2_SCDIE_Pos (5U)
5018#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
5019#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
5020#define DFSDM_FLTCR2_AWDIE_Pos (4U)
5021#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
5022#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
5023#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
5024#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
5025#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
5026#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
5027#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
5028#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
5029#define DFSDM_FLTCR2_REOCIE_Pos (1U)
5030#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
5031#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
5032#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
5033#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
5034#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
5035
5036/***************** Bit definition for DFSDM_FLTISR register *******************/
5037#define DFSDM_FLTISR_SCDF_Pos (24U)
5038#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
5039#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
5040#define DFSDM_FLTISR_CKABF_Pos (16U)
5041#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
5042#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
5043#define DFSDM_FLTISR_RCIP_Pos (14U)
5044#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
5045#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
5046#define DFSDM_FLTISR_JCIP_Pos (13U)
5047#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
5048#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
5049#define DFSDM_FLTISR_AWDF_Pos (4U)
5050#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
5051#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
5052#define DFSDM_FLTISR_ROVRF_Pos (3U)
5053#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
5054#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
5055#define DFSDM_FLTISR_JOVRF_Pos (2U)
5056#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
5057#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
5058#define DFSDM_FLTISR_REOCF_Pos (1U)
5059#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
5060#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
5061#define DFSDM_FLTISR_JEOCF_Pos (0U)
5062#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
5063#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
5064
5065/***************** Bit definition for DFSDM_FLTICR register *******************/
5066#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
5067#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
5068#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCDF[7:0] Clear the short circuit detector flag */
5069#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
5070#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
5071#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
5072#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
5073#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
5074#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
5075#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
5076#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
5077#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
5078
5079/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
5080#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
5081#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
5082#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
5083
5084/***************** Bit definition for DFSDM_FLTFCR register *******************/
5085#define DFSDM_FLTFCR_FORD_Pos (29U)
5086#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
5087#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
5088#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
5089#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
5090#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
5091#define DFSDM_FLTFCR_FOSR_Pos (16U)
5092#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
5093#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
5094#define DFSDM_FLTFCR_IOSR_Pos (0U)
5095#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
5096#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
5097
5098/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
5099#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
5100#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)/*!< 0xFFFFFF00 */
5101#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
5102#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
5103#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
5104#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
5105
5106/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
5107#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
5108#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)/*!< 0xFFFFFF00 */
5109#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
5110#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
5111#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
5112#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
5113#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
5114#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
5115#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
5116
5117/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
5118#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
5119#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)/*!< 0xFFFFFF00 */
5120#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
5121#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
5122#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
5123#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
5124
5125/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
5126#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
5127#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)/*!< 0xFFFFFF00 */
5128#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
5129#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
5130#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
5131#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
5132
5133/*************** Bit definition for DFSDM_FLTAWSR register *******************/
5134#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
5135#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
5136#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
5137#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
5138#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
5139#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
5140
5141/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
5142#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
5143#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)/*!< 0x0000FF00 */
5144#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
5145#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
5146#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)/*!< 0x000000FF */
5147#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
5148
5149/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
5150#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
5151#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)/*!< 0xFFFFFF00 */
5152#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
5153#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
5154#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
5155#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
5156
5157/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
5158#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
5159#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)/*!< 0xFFFFFF00 */
5160#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
5161#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
5162#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
5163#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
5164
5165/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
5166#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
5167#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)/*!< 0xFFFFFFF0 */
5168#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
5169
5170/******************************************************************************/
5171/* */
5172/* DMA Controller (DMA) */
5173/* */
5174/******************************************************************************/
5175/******************* Bit definition for DMA_ISR register ********************/
5176#define DMA_ISR_GIF1_Pos (0U)
5177#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
5178#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
5179#define DMA_ISR_TCIF1_Pos (1U)
5180#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
5181#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
5182#define DMA_ISR_HTIF1_Pos (2U)
5183#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
5184#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
5185#define DMA_ISR_TEIF1_Pos (3U)
5186#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
5187#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
5188#define DMA_ISR_GIF2_Pos (4U)
5189#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
5190#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
5191#define DMA_ISR_TCIF2_Pos (5U)
5192#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
5193#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
5194#define DMA_ISR_HTIF2_Pos (6U)
5195#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
5196#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
5197#define DMA_ISR_TEIF2_Pos (7U)
5198#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
5199#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
5200#define DMA_ISR_GIF3_Pos (8U)
5201#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
5202#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
5203#define DMA_ISR_TCIF3_Pos (9U)
5204#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
5205#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
5206#define DMA_ISR_HTIF3_Pos (10U)
5207#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
5208#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
5209#define DMA_ISR_TEIF3_Pos (11U)
5210#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
5211#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
5212#define DMA_ISR_GIF4_Pos (12U)
5213#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
5214#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
5215#define DMA_ISR_TCIF4_Pos (13U)
5216#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
5217#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
5218#define DMA_ISR_HTIF4_Pos (14U)
5219#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
5220#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
5221#define DMA_ISR_TEIF4_Pos (15U)
5222#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
5223#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
5224#define DMA_ISR_GIF5_Pos (16U)
5225#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
5226#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
5227#define DMA_ISR_TCIF5_Pos (17U)
5228#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
5229#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
5230#define DMA_ISR_HTIF5_Pos (18U)
5231#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
5232#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
5233#define DMA_ISR_TEIF5_Pos (19U)
5234#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
5235#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
5236#define DMA_ISR_GIF6_Pos (20U)
5237#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
5238#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
5239#define DMA_ISR_TCIF6_Pos (21U)
5240#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
5241#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
5242#define DMA_ISR_HTIF6_Pos (22U)
5243#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
5244#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
5245#define DMA_ISR_TEIF6_Pos (23U)
5246#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
5247#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
5248#define DMA_ISR_GIF7_Pos (24U)
5249#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
5250#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
5251#define DMA_ISR_TCIF7_Pos (25U)
5252#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
5253#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
5254#define DMA_ISR_HTIF7_Pos (26U)
5255#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
5256#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
5257#define DMA_ISR_TEIF7_Pos (27U)
5258#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
5259#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
5260#define DMA_ISR_GIF8_Pos (28U)
5261#define DMA_ISR_GIF8_Msk (0x1UL << DMA_ISR_GIF8_Pos) /*!< 0x10000000 */
5262#define DMA_ISR_GIF8 DMA_ISR_GIF8_Msk /*!< Channel 8 Global interrupt flag */
5263#define DMA_ISR_TCIF8_Pos (29U)
5264#define DMA_ISR_TCIF8_Msk (0x1UL << DMA_ISR_TCIF8_Pos) /*!< 0x20000000 */
5265#define DMA_ISR_TCIF8 DMA_ISR_TCIF8_Msk /*!< Channel 8 Transfer Complete flag */
5266#define DMA_ISR_HTIF8_Pos (30U)
5267#define DMA_ISR_HTIF8_Msk (0x1UL << DMA_ISR_HTIF8_Pos) /*!< 0x40000000 */
5268#define DMA_ISR_HTIF8 DMA_ISR_HTIF8_Msk /*!< Channel 8 Half Transfer flag */
5269#define DMA_ISR_TEIF8_Pos (31U)
5270#define DMA_ISR_TEIF8_Msk (0x1UL << DMA_ISR_TEIF8_Pos) /*!< 0x80000000 */
5271#define DMA_ISR_TEIF8 DMA_ISR_TEIF8_Msk /*!< Channel 8 Transfer Error flag */
5272
5273/******************* Bit definition for DMA_IFCR register *******************/
5274#define DMA_IFCR_CGIF1_Pos (0U)
5275#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
5276#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
5277#define DMA_IFCR_CTCIF1_Pos (1U)
5278#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
5279#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
5280#define DMA_IFCR_CHTIF1_Pos (2U)
5281#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
5282#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
5283#define DMA_IFCR_CTEIF1_Pos (3U)
5284#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
5285#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
5286#define DMA_IFCR_CGIF2_Pos (4U)
5287#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
5288#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
5289#define DMA_IFCR_CTCIF2_Pos (5U)
5290#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
5291#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
5292#define DMA_IFCR_CHTIF2_Pos (6U)
5293#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
5294#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
5295#define DMA_IFCR_CTEIF2_Pos (7U)
5296#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
5297#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
5298#define DMA_IFCR_CGIF3_Pos (8U)
5299#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
5300#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
5301#define DMA_IFCR_CTCIF3_Pos (9U)
5302#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
5303#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
5304#define DMA_IFCR_CHTIF3_Pos (10U)
5305#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
5306#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
5307#define DMA_IFCR_CTEIF3_Pos (11U)
5308#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
5309#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
5310#define DMA_IFCR_CGIF4_Pos (12U)
5311#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
5312#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
5313#define DMA_IFCR_CTCIF4_Pos (13U)
5314#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
5315#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
5316#define DMA_IFCR_CHTIF4_Pos (14U)
5317#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
5318#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
5319#define DMA_IFCR_CTEIF4_Pos (15U)
5320#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
5321#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
5322#define DMA_IFCR_CGIF5_Pos (16U)
5323#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
5324#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
5325#define DMA_IFCR_CTCIF5_Pos (17U)
5326#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
5327#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
5328#define DMA_IFCR_CHTIF5_Pos (18U)
5329#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
5330#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
5331#define DMA_IFCR_CTEIF5_Pos (19U)
5332#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
5333#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
5334#define DMA_IFCR_CGIF6_Pos (20U)
5335#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
5336#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
5337#define DMA_IFCR_CTCIF6_Pos (21U)
5338#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
5339#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
5340#define DMA_IFCR_CHTIF6_Pos (22U)
5341#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
5342#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
5343#define DMA_IFCR_CTEIF6_Pos (23U)
5344#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
5345#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
5346#define DMA_IFCR_CGIF7_Pos (24U)
5347#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
5348#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
5349#define DMA_IFCR_CTCIF7_Pos (25U)
5350#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
5351#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
5352#define DMA_IFCR_CHTIF7_Pos (26U)
5353#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
5354#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
5355#define DMA_IFCR_CTEIF7_Pos (27U)
5356#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
5357#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
5358#define DMA_IFCR_CGIF8_Pos (28U)
5359#define DMA_IFCR_CGIF8_Msk (0x1UL << DMA_IFCR_CGIF8_Pos) /*!< 0x10000000 */
5360#define DMA_IFCR_CGIF8 DMA_IFCR_CGIF8_Msk /*!< Channel 8 Global interrupt clear */
5361#define DMA_IFCR_CTCIF8_Pos (29U)
5362#define DMA_IFCR_CTCIF8_Msk (0x1UL << DMA_IFCR_CTCIF8_Pos) /*!< 0x20000000 */
5363#define DMA_IFCR_CTCIF8 DMA_IFCR_CTCIF8_Msk /*!< Channel 8 Transfer Complete clear */
5364#define DMA_IFCR_CHTIF8_Pos (30U)
5365#define DMA_IFCR_CHTIF8_Msk (0x1UL << DMA_IFCR_CHTIF8_Pos) /*!< 0x40000000 */
5366#define DMA_IFCR_CHTIF8 DMA_IFCR_CHTIF8_Msk /*!< Channel 8 Half Transfer clear */
5367#define DMA_IFCR_CTEIF8_Pos (31U)
5368#define DMA_IFCR_CTEIF8_Msk (0x1UL << DMA_IFCR_CTEIF8_Pos) /*!< 0x80000000 */
5369#define DMA_IFCR_CTEIF8 DMA_IFCR_CTEIF8_Msk /*!< Channel 8 Transfer Error clear */
5370
5371/******************* Bit definition for DMA_CCR register ********************/
5372#define DMA_CCR_EN_Pos (0U)
5373#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
5374#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
5375#define DMA_CCR_TCIE_Pos (1U)
5376#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
5377#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
5378#define DMA_CCR_HTIE_Pos (2U)
5379#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
5380#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
5381#define DMA_CCR_TEIE_Pos (3U)
5382#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
5383#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
5384#define DMA_CCR_DIR_Pos (4U)
5385#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
5386#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
5387#define DMA_CCR_CIRC_Pos (5U)
5388#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
5389#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
5390#define DMA_CCR_PINC_Pos (6U)
5391#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
5392#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
5393#define DMA_CCR_MINC_Pos (7U)
5394#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
5395#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
5396
5397#define DMA_CCR_PSIZE_Pos (8U)
5398#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
5399#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
5400#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
5401#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
5402
5403#define DMA_CCR_MSIZE_Pos (10U)
5404#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
5405#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
5406#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
5407#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
5408
5409#define DMA_CCR_PL_Pos (12U)
5410#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
5411#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
5412#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
5413#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
5414
5415#define DMA_CCR_MEM2MEM_Pos (14U)
5416#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
5417#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
5418#define DMA_CCR_DBM_Pos (15U)
5419#define DMA_CCR_DBM_Msk (0x1UL << DMA_CCR_DBM_Pos) /*!< 0x00008000 */
5420#define DMA_CCR_DBM DMA_CCR_DBM_Msk /*!< Double-buffer mode */
5421#define DMA_CCR_CT_Pos (16U)
5422#define DMA_CCR_CT_Msk (0x1UL << DMA_CCR_CT_Pos) /*!< 0x00010000 */
5423#define DMA_CCR_CT DMA_CCR_CT_Msk /*!< Current target of DMA transfer in double-buffer mode */
5424#define DMA_CCR_SECM_Pos (17U)
5425#define DMA_CCR_SECM_Msk (0x1UL << DMA_CCR_SECM_Pos) /*!< 0x00020000 */
5426#define DMA_CCR_SECM DMA_CCR_SECM_Msk /*!< Secure mode */
5427#define DMA_CCR_SSEC_Pos (18U)
5428#define DMA_CCR_SSEC_Msk (0x1UL << DMA_CCR_SSEC_Pos) /*!< 0x00040000 */
5429#define DMA_CCR_SSEC DMA_CCR_SSEC_Msk /*!< Security of the DMA transfer from the source */
5430#define DMA_CCR_DSEC_Pos (19U)
5431#define DMA_CCR_DSEC_Msk (0x1UL << DMA_CCR_DSEC_Pos) /*!< 0x00080000 */
5432#define DMA_CCR_DSEC DMA_CCR_DSEC_Msk /*!< Security of the DMA transfer to the destination */
5433#define DMA_CCR_PRIV_Pos (20U)
5434#define DMA_CCR_PRIV_Msk (0x1UL << DMA_CCR_PRIV_Pos) /*!< 0x00100000 */
5435#define DMA_CCR_PRIV DMA_CCR_PRIV_Msk /*!< Privileged mode */
5436
5437/****************** Bit definition for DMA_CNDTR register *******************/
5438#define DMA_CNDTR_NDT_Pos (0U)
5439#define DMA_CNDTR_NDT_Msk (0x3FFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
5440#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
5441
5442/****************** Bit definition for DMA_CPAR register ********************/
5443#define DMA_CPAR_PA_Pos (0U)
5444#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
5445#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
5446
5447/****************** Bit definition for DMA_CM0AR register *******************/
5448#define DMA_CM0AR_MA_Pos (0U)
5449#define DMA_CM0AR_MA_Msk (0xFFFFFFFFUL << DMA_CM0AR_MA_Pos) /*!< 0xFFFFFFFF */
5450#define DMA_CM0AR_MA DMA_CM0AR_MA_Msk /*!< Memory 0 Address */
5451
5452/****************** Bit definition for DMA_CM1AR register *******************/
5453#define DMA_CM1AR_MA_Pos (0U)
5454#define DMA_CM1AR_MA_Msk (0xFFFFFFFFUL << DMA_CM1AR_MA_Pos) /*!< 0xFFFFFFFF */
5455#define DMA_CM1AR_MA DMA_CM1AR_MA_Msk /*!< Memory 1 Address */
5456
5457/******************************************************************************/
5458/* */
5459/* DMAMUX Controller */
5460/* */
5461/******************************************************************************/
5462/******************** Bits definition for DMAMUX_CxCR register **************/
5463#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
5464#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
5465#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
5466#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
5467#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
5468#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
5469#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
5470#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
5471#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
5472#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
5473#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
5474
5475#define DMAMUX_CxCR_SOIE_Pos (8U)
5476#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
5477#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
5478
5479#define DMAMUX_CxCR_EGE_Pos (9U)
5480#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
5481#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
5482
5483#define DMAMUX_CxCR_SE_Pos (16U)
5484#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
5485#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
5486
5487#define DMAMUX_CxCR_SPOL_Pos (17U)
5488#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
5489#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
5490#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
5491#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
5492
5493#define DMAMUX_CxCR_NBREQ_Pos (19U)
5494#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
5495#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
5496#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
5497#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
5498#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
5499#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
5500#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
5501
5502#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
5503#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
5504#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
5505#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
5506#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
5507#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
5508#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
5509#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
5510
5511/******************** Bits definition for DMAMUX_CSR register ****************/
5512#define DMAMUX_CSR_SOF0_Pos (0U)
5513#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
5514#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
5515#define DMAMUX_CSR_SOF1_Pos (1U)
5516#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
5517#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
5518#define DMAMUX_CSR_SOF2_Pos (2U)
5519#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
5520#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
5521#define DMAMUX_CSR_SOF3_Pos (3U)
5522#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
5523#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
5524#define DMAMUX_CSR_SOF4_Pos (4U)
5525#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
5526#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
5527#define DMAMUX_CSR_SOF5_Pos (5U)
5528#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
5529#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
5530#define DMAMUX_CSR_SOF6_Pos (6U)
5531#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
5532#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
5533#define DMAMUX_CSR_SOF7_Pos (7U)
5534#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
5535#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
5536#define DMAMUX_CSR_SOF8_Pos (8U)
5537#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
5538#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
5539#define DMAMUX_CSR_SOF9_Pos (9U)
5540#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
5541#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
5542#define DMAMUX_CSR_SOF10_Pos (10U)
5543#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
5544#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
5545#define DMAMUX_CSR_SOF11_Pos (11U)
5546#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
5547#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
5548#define DMAMUX_CSR_SOF12_Pos (12U)
5549#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)/*!< 0x00001000 */
5550#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
5551#define DMAMUX_CSR_SOF13_Pos (13U)
5552#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)/*!< 0x00002000 */
5553#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
5554#define DMAMUX_CSR_SOF14_Pos (14U)
5555#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)/*!< 0x00004000 */
5556#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
5557#define DMAMUX_CSR_SOF15_Pos (15U)
5558#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)/*!< 0x00008000 */
5559#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
5560
5561/******************** Bits definition for DMAMUX_CFR register ****************/
5562#define DMAMUX_CFR_CSOF0_Pos (0U)
5563#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
5564#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
5565#define DMAMUX_CFR_CSOF1_Pos (1U)
5566#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
5567#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
5568#define DMAMUX_CFR_CSOF2_Pos (2U)
5569#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
5570#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
5571#define DMAMUX_CFR_CSOF3_Pos (3U)
5572#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
5573#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
5574#define DMAMUX_CFR_CSOF4_Pos (4U)
5575#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
5576#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
5577#define DMAMUX_CFR_CSOF5_Pos (5U)
5578#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
5579#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
5580#define DMAMUX_CFR_CSOF6_Pos (6U)
5581#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
5582#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
5583#define DMAMUX_CFR_CSOF7_Pos (7U)
5584#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
5585#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
5586#define DMAMUX_CFR_CSOF8_Pos (8U)
5587#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
5588#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
5589#define DMAMUX_CFR_CSOF9_Pos (9U)
5590#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
5591#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
5592#define DMAMUX_CFR_CSOF10_Pos (10U)
5593#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
5594#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
5595#define DMAMUX_CFR_CSOF11_Pos (11U)
5596#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
5597#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
5598#define DMAMUX_CFR_CSOF12_Pos (12U)
5599#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
5600#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
5601#define DMAMUX_CFR_CSOF13_Pos (13U)
5602#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
5603#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
5604#define DMAMUX_CFR_CSOF14_Pos (14U)
5605#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)/*!< 0x00004000 */
5606#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
5607#define DMAMUX_CFR_CSOF15_Pos (15U)
5608#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)/*!< 0x00008000 */
5609#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
5610
5611/******************** Bits definition for DMAMUX_RGxCR register ************/
5612#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
5613#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
5614#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
5615#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
5616#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
5617#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
5618#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
5619#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
5620
5621#define DMAMUX_RGxCR_OIE_Pos (8U)
5622#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
5623#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
5624
5625#define DMAMUX_RGxCR_GE_Pos (16U)
5626#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
5627#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
5628
5629#define DMAMUX_RGxCR_GPOL_Pos (17U)
5630#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
5631#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
5632#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
5633#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
5634
5635#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
5636#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
5637#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
5638#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
5639#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
5640#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
5641#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
5642#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
5643
5644/******************** Bits definition for DMAMUX_RGSR register **************/
5645#define DMAMUX_RGSR_OF0_Pos (0U)
5646#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
5647#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
5648#define DMAMUX_RGSR_OF1_Pos (1U)
5649#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
5650#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
5651#define DMAMUX_RGSR_OF2_Pos (2U)
5652#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
5653#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
5654#define DMAMUX_RGSR_OF3_Pos (3U)
5655#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
5656#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
5657
5658/******************** Bits definition for DMAMUX_RGCFR register ************/
5659#define DMAMUX_RGCFR_COF0_Pos (0U)
5660#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
5661#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
5662#define DMAMUX_RGCFR_COF1_Pos (1U)
5663#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
5664#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
5665#define DMAMUX_RGCFR_COF2_Pos (2U)
5666#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
5667#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
5668#define DMAMUX_RGCFR_COF3_Pos (3U)
5669#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
5670#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
5671
5672/*****************************************************************************/
5673/* */
5674/* External Interrupt/Event Controller */
5675/* */
5676/*****************************************************************************/
5677/******************* Bit definition for EXTI_RTSR1 register ****************/
5678#define EXTI_RTSR1_RT0_Pos (0U)
5679#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
5680#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */
5681#define EXTI_RTSR1_RT1_Pos (1U)
5682#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
5683#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */
5684#define EXTI_RTSR1_RT2_Pos (2U)
5685#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
5686#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */
5687#define EXTI_RTSR1_RT3_Pos (3U)
5688#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
5689#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */
5690#define EXTI_RTSR1_RT4_Pos (4U)
5691#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
5692#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */
5693#define EXTI_RTSR1_RT5_Pos (5U)
5694#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
5695#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */
5696#define EXTI_RTSR1_RT6_Pos (6U)
5697#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
5698#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */
5699#define EXTI_RTSR1_RT7_Pos (7U)
5700#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
5701#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */
5702#define EXTI_RTSR1_RT8_Pos (8U)
5703#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
5704#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */
5705#define EXTI_RTSR1_RT9_Pos (9U)
5706#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
5707#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */
5708#define EXTI_RTSR1_RT10_Pos (10U)
5709#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
5710#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */
5711#define EXTI_RTSR1_RT11_Pos (11U)
5712#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
5713#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */
5714#define EXTI_RTSR1_RT12_Pos (12U)
5715#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
5716#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */
5717#define EXTI_RTSR1_RT13_Pos (13U)
5718#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
5719#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */
5720#define EXTI_RTSR1_RT14_Pos (14U)
5721#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
5722#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */
5723#define EXTI_RTSR1_RT15_Pos (15U)
5724#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
5725#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */
5726#define EXTI_RTSR1_RT16_Pos (16U)
5727#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
5728#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger configuration for input line 16 */
5729#define EXTI_RTSR1_RT21_Pos (21U)
5730#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
5731#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger configuration for input line 21 */
5732#define EXTI_RTSR1_RT22_Pos (22U)
5733#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
5734#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger configuration for input line 22 */
5735#define EXTI_RTSR1_RT23_Pos (23U)
5736#define EXTI_RTSR1_RT23_Msk (0x1UL << EXTI_RTSR1_RT23_Pos) /*!< 0x00800000 */
5737#define EXTI_RTSR1_RT23 EXTI_RTSR1_RT23_Msk /*!< Rising trigger configuration for input line 23 */
5738#define EXTI_RTSR1_RT24_Pos (24U)
5739#define EXTI_RTSR1_RT24_Msk (0x1UL << EXTI_RTSR1_RT24_Pos) /*!< 0x01000000 */
5740#define EXTI_RTSR1_RT24 EXTI_RTSR1_RT24_Msk /*!< Rising trigger configuration for input line 24 */
5741#define EXTI_RTSR1_RT25_Pos (25U)
5742#define EXTI_RTSR1_RT25_Msk (0x1UL << EXTI_RTSR1_RT25_Pos) /*!< 0x02000000 */
5743#define EXTI_RTSR1_RT25 EXTI_RTSR1_RT25_Msk /*!< Rising trigger configuration for input line 25 */
5744#define EXTI_RTSR1_RT26_Pos (26U)
5745#define EXTI_RTSR1_RT26_Msk (0x1UL << EXTI_RTSR1_RT26_Pos) /*!< 0x04000000 */
5746#define EXTI_RTSR1_RT26 EXTI_RTSR1_RT26_Msk /*!< Rising trigger configuration for input line 26 */
5747#define EXTI_RTSR1_RT27_Pos (27U)
5748#define EXTI_RTSR1_RT27_Msk (0x1UL << EXTI_RTSR1_RT27_Pos) /*!< 0x08000000 */
5749#define EXTI_RTSR1_RT27 EXTI_RTSR1_RT27_Msk /*!< Rising trigger configuration for input line 27 */
5750#define EXTI_RTSR1_RT28_Pos (28U)
5751#define EXTI_RTSR1_RT28_Msk (0x1UL << EXTI_RTSR1_RT28_Pos) /*!< 0x10000000 */
5752#define EXTI_RTSR1_RT28 EXTI_RTSR1_RT28_Msk /*!< Rising trigger configuration for input line 28 */
5753#define EXTI_RTSR1_RT29_Pos (29U)
5754#define EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos) /*!< 0x20000000 */
5755#define EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk /*!< Rising trigger configuration for input line 29 */
5756#define EXTI_RTSR1_RT30_Pos (30U)
5757#define EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos) /*!< 0x40000000 */
5758#define EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk /*!< Rising trigger configuration for input line 30 */
5759#define EXTI_RTSR1_RT31_Pos (31U)
5760#define EXTI_RTSR1_RT31_Msk (0x1UL << EXTI_RTSR1_RT31_Pos) /*!< 0x80000000 */
5761#define EXTI_RTSR1_RT31 EXTI_RTSR1_RT31_Msk /*!< Rising trigger configuration for input line 31 */
5762
5763/******************* Bit definition for EXTI_RTSR2 register ****************/
5764#define EXTI_RTSR2_RT32_Pos (0U)
5765#define EXTI_RTSR2_RT32_Msk (0x1UL << EXTI_RTSR2_RT32_Pos) /*!< 0x00000001 */
5766#define EXTI_RTSR2_RT32 EXTI_RTSR2_RT32_Msk /*!< Rising trigger configuration for input line 32 */
5767#define EXTI_RTSR2_RT33_Pos (1U)
5768#define EXTI_RTSR2_RT33_Msk (0x1UL << EXTI_RTSR2_RT33_Pos) /*!< 0x00000002 */
5769#define EXTI_RTSR2_RT33 EXTI_RTSR2_RT33_Msk /*!< Rising trigger configuration for input line 33 */
5770#define EXTI_RTSR2_RT34_Pos (2U)
5771#define EXTI_RTSR2_RT34_Msk (0x1UL << EXTI_RTSR2_RT34_Pos) /*!< 0x00000004 */
5772#define EXTI_RTSR2_RT34 EXTI_RTSR2_RT34_Msk /*!< Rising trigger configuration for input line 34 */
5773#define EXTI_RTSR2_RT35_Pos (3U)
5774#define EXTI_RTSR2_RT35_Msk (0x1UL << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
5775#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger configuration for input line 35 */
5776#define EXTI_RTSR2_RT36_Pos (4U)
5777#define EXTI_RTSR2_RT36_Msk (0x1UL << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
5778#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger configuration for input line 36 */
5779#define EXTI_RTSR2_RT37_Pos (5U)
5780#define EXTI_RTSR2_RT37_Msk (0x1UL << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
5781#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger configuration for input line 37 */
5782#define EXTI_RTSR2_RT38_Pos (6U)
5783#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
5784#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger configuration for input line 38 */
5785#define EXTI_RTSR2_RT39_Pos (7U)
5786#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */
5787#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger configuration for input line 39 */
5788#define EXTI_RTSR2_RT40_Pos (8U)
5789#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */
5790#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger configuration for input line 40 */
5791#define EXTI_RTSR2_RT41_Pos (9U)
5792#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */
5793#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger configuration for input line 41 */
5794#define EXTI_RTSR2_RT42_Pos (10U)
5795#define EXTI_RTSR2_RT42_Msk (0x1UL << EXTI_RTSR2_RT42_Pos) /*!< 0x00000400 */
5796#define EXTI_RTSR2_RT42 EXTI_RTSR2_RT42_Msk /*!< Rising trigger configuration for input line 42 */
5797
5798/******************* Bit definition for EXTI_FTSR1 register ****************/
5799#define EXTI_FTSR1_FT0_Pos (0U)
5800#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
5801#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */
5802#define EXTI_FTSR1_FT1_Pos (1U)
5803#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
5804#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */
5805#define EXTI_FTSR1_FT2_Pos (2U)
5806#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
5807#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */
5808#define EXTI_FTSR1_FT3_Pos (3U)
5809#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
5810#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */
5811#define EXTI_FTSR1_FT4_Pos (4U)
5812#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
5813#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */
5814#define EXTI_FTSR1_FT5_Pos (5U)
5815#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
5816#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */
5817#define EXTI_FTSR1_FT6_Pos (6U)
5818#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
5819#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */
5820#define EXTI_FTSR1_FT7_Pos (7U)
5821#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
5822#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */
5823#define EXTI_FTSR1_FT8_Pos (8U)
5824#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
5825#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */
5826#define EXTI_FTSR1_FT9_Pos (9U)
5827#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
5828#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */
5829#define EXTI_FTSR1_FT10_Pos (10U)
5830#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
5831#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */
5832#define EXTI_FTSR1_FT11_Pos (11U)
5833#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
5834#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */
5835#define EXTI_FTSR1_FT12_Pos (12U)
5836#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
5837#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */
5838#define EXTI_FTSR1_FT13_Pos (13U)
5839#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
5840#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */
5841#define EXTI_FTSR1_FT14_Pos (14U)
5842#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
5843#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */
5844#define EXTI_FTSR1_FT15_Pos (15U)
5845#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
5846#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */
5847#define EXTI_FTSR1_FT16_Pos (16U)
5848#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
5849#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger configuration for input line 16 */
5850#define EXTI_FTSR1_FT21_Pos (21U)
5851#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
5852#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger configuration for input line 21 */
5853#define EXTI_FTSR1_FT22_Pos (22U)
5854#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
5855#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger configuration for input line 22 */
5856#define EXTI_FTSR1_FT23_Pos (23U)
5857#define EXTI_FTSR1_FT23_Msk (0x1UL << EXTI_FTSR1_FT23_Pos) /*!< 0x00800000 */
5858#define EXTI_FTSR1_FT23 EXTI_FTSR1_FT23_Msk /*!< Falling trigger configuration for input line 23 */
5859#define EXTI_FTSR1_FT24_Pos (24U)
5860#define EXTI_FTSR1_FT24_Msk (0x1UL << EXTI_FTSR1_FT24_Pos) /*!< 0x01000000 */
5861#define EXTI_FTSR1_FT24 EXTI_FTSR1_FT24_Msk /*!< Falling trigger configuration for input line 24 */
5862#define EXTI_FTSR1_FT25_Pos (25U)
5863#define EXTI_FTSR1_FT25_Msk (0x1UL << EXTI_FTSR1_FT25_Pos) /*!< 0x02000000 */
5864#define EXTI_FTSR1_FT25 EXTI_FTSR1_FT25_Msk /*!< Falling trigger configuration for input line 25 */
5865#define EXTI_FTSR1_FT26_Pos (26U)
5866#define EXTI_FTSR1_FT26_Msk (0x1UL << EXTI_FTSR1_FT26_Pos) /*!< 0x04000000 */
5867#define EXTI_FTSR1_FT26 EXTI_FTSR1_FT26_Msk /*!< Falling trigger configuration for input line 26 */
5868#define EXTI_FTSR1_FT27_Pos (27U)
5869#define EXTI_FTSR1_FT27_Msk (0x1UL << EXTI_FTSR1_FT27_Pos) /*!< 0x08000000 */
5870#define EXTI_FTSR1_FT27 EXTI_FTSR1_FT27_Msk /*!< Falling trigger configuration for input line 27 */
5871#define EXTI_FTSR1_FT28_Pos (28U)
5872#define EXTI_FTSR1_FT28_Msk (0x1UL << EXTI_FTSR1_FT28_Pos) /*!< 0x10000000 */
5873#define EXTI_FTSR1_FT28 EXTI_FTSR1_FT28_Msk /*!< Falling trigger configuration for input line 28 */
5874#define EXTI_FTSR1_FT29_Pos (29U)
5875#define EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos) /*!< 0x20000000 */
5876#define EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk /*!< Falling trigger configuration for input line 29 */
5877#define EXTI_FTSR1_FT30_Pos (30U)
5878#define EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos) /*!< 0x40000000 */
5879#define EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk /*!< Falling trigger configuration for input line 30 */
5880#define EXTI_FTSR1_FT31_Pos (31U)
5881#define EXTI_FTSR1_FT31_Msk (0x1UL << EXTI_FTSR1_FT31_Pos) /*!< 0x80000000 */
5882#define EXTI_FTSR1_FT31 EXTI_FTSR1_FT31_Msk /*!< Falling trigger configuration for input line 31 */
5883
5884/******************* Bit definition for EXTI_FTSR2 register ****************/
5885#define EXTI_FTSR2_FT32_Pos (0U)
5886#define EXTI_FTSR2_FT32_Msk (0x1UL << EXTI_FTSR2_FT32_Pos) /*!< 0x00000001 */
5887#define EXTI_FTSR2_FT32 EXTI_FTSR2_FT32_Msk /*!< Falling trigger configuration for input line 32 */
5888#define EXTI_FTSR2_FT33_Pos (1U)
5889#define EXTI_FTSR2_FT33_Msk (0x1UL << EXTI_FTSR2_FT33_Pos) /*!< 0x00000002 */
5890#define EXTI_FTSR2_FT33 EXTI_FTSR2_FT33_Msk /*!< Falling trigger configuration for input line 33 */
5891#define EXTI_FTSR2_FT34_Pos (2U)
5892#define EXTI_FTSR2_FT34_Msk (0x1UL << EXTI_FTSR2_FT34_Pos) /*!< 0x00000004 */
5893#define EXTI_FTSR2_FT34 EXTI_FTSR2_FT34_Msk /*!< Falling trigger configuration for input line 34 */
5894#define EXTI_FTSR2_FT35_Pos (3U)
5895#define EXTI_FTSR2_FT35_Msk (0x1UL << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
5896#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger configuration for input line 35 */
5897#define EXTI_FTSR2_FT36_Pos (4U)
5898#define EXTI_FTSR2_FT36_Msk (0x1UL << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
5899#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger configuration for input line 36 */
5900#define EXTI_FTSR2_FT37_Pos (5U)
5901#define EXTI_FTSR2_FT37_Msk (0x1UL << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
5902#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger configuration for input line 37 */
5903#define EXTI_FTSR2_FT38_Pos (6U)
5904#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
5905#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger configuration for input line 38 */
5906#define EXTI_FTSR2_FT39_Pos (7U)
5907#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */
5908#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger configuration for input line 39 */
5909#define EXTI_FTSR2_FT40_Pos (8U)
5910#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */
5911#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger configuration for input line 40 */
5912#define EXTI_FTSR2_FT41_Pos (9U)
5913#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */
5914#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger configuration for input line 41 */
5915#define EXTI_FTSR2_FT42_Pos (10U)
5916#define EXTI_FTSR2_FT42_Msk (0x1UL << EXTI_FTSR2_FT42_Pos) /*!< 0x00000400 */
5917#define EXTI_FTSR2_FT42 EXTI_FTSR2_FT42_Msk /*!< Falling trigger configuration for input line 42 */
5918
5919/******************* Bit definition for EXTI_SWIER1 register ***************/
5920#define EXTI_SWIER1_SWI0_Pos (0U)
5921#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
5922#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
5923#define EXTI_SWIER1_SWI1_Pos (1U)
5924#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
5925#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
5926#define EXTI_SWIER1_SWI2_Pos (2U)
5927#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
5928#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
5929#define EXTI_SWIER1_SWI3_Pos (3U)
5930#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
5931#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
5932#define EXTI_SWIER1_SWI4_Pos (4U)
5933#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
5934#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
5935#define EXTI_SWIER1_SWI5_Pos (5U)
5936#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
5937#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
5938#define EXTI_SWIER1_SWI6_Pos (6U)
5939#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
5940#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
5941#define EXTI_SWIER1_SWI7_Pos (7U)
5942#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
5943#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
5944#define EXTI_SWIER1_SWI8_Pos (8U)
5945#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
5946#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
5947#define EXTI_SWIER1_SWI9_Pos (9U)
5948#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
5949#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
5950#define EXTI_SWIER1_SWI10_Pos (10U)
5951#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
5952#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
5953#define EXTI_SWIER1_SWI11_Pos (11U)
5954#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
5955#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
5956#define EXTI_SWIER1_SWI12_Pos (12U)
5957#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
5958#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
5959#define EXTI_SWIER1_SWI13_Pos (13U)
5960#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
5961#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
5962#define EXTI_SWIER1_SWI14_Pos (14U)
5963#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
5964#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
5965#define EXTI_SWIER1_SWI15_Pos (15U)
5966#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
5967#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
5968#define EXTI_SWIER1_SWI16_Pos (16U)
5969#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
5970#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
5971#define EXTI_SWIER1_SWI21_Pos (21U)
5972#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
5973#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
5974#define EXTI_SWIER1_SWI22_Pos (22U)
5975#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
5976#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
5977#define EXTI_SWIER1_SWI23_Pos (23U)
5978#define EXTI_SWIER1_SWI23_Msk (0x1UL << EXTI_SWIER1_SWI23_Pos) /*!< 0x00800000 */
5979#define EXTI_SWIER1_SWI23 EXTI_SWIER1_SWI23_Msk /*!< Software Interrupt on line 23 */
5980#define EXTI_SWIER1_SWI24_Pos (24U)
5981#define EXTI_SWIER1_SWI24_Msk (0x1UL << EXTI_SWIER1_SWI24_Pos) /*!< 0x01000000 */
5982#define EXTI_SWIER1_SWI24 EXTI_SWIER1_SWI24_Msk /*!< Software Interrupt on line 24 */
5983#define EXTI_SWIER1_SWI25_Pos (25U)
5984#define EXTI_SWIER1_SWI25_Msk (0x1UL << EXTI_SWIER1_SWI25_Pos) /*!< 0x02000000 */
5985#define EXTI_SWIER1_SWI25 EXTI_SWIER1_SWI25_Msk /*!< Software Interrupt on line 25 */
5986#define EXTI_SWIER1_SWI26_Pos (26U)
5987#define EXTI_SWIER1_SWI26_Msk (0x1UL << EXTI_SWIER1_SWI26_Pos) /*!< 0x04000000 */
5988#define EXTI_SWIER1_SWI26 EXTI_SWIER1_SWI26_Msk /*!< Software Interrupt on line 26 */
5989#define EXTI_SWIER1_SWI27_Pos (27U)
5990#define EXTI_SWIER1_SWI27_Msk (0x1UL << EXTI_SWIER1_SWI27_Pos) /*!< 0x08000000 */
5991#define EXTI_SWIER1_SWI27 EXTI_SWIER1_SWI27_Msk /*!< Software Interrupt on line 27 */
5992#define EXTI_SWIER1_SWI28_Pos (28U)
5993#define EXTI_SWIER1_SWI28_Msk (0x1UL << EXTI_SWIER1_SWI28_Pos) /*!< 0x10000000 */
5994#define EXTI_SWIER1_SWI28 EXTI_SWIER1_SWI28_Msk /*!< Software Interrupt on line 28 */
5995#define EXTI_SWIER1_SWI29_Pos (29U)
5996#define EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos) /*!< 0x20000000 */
5997#define EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk /*!< Software Interrupt on line 29 */
5998#define EXTI_SWIER1_SWI30_Pos (30U)
5999#define EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos) /*!< 0x40000000 */
6000#define EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk /*!< Software Interrupt on line 30 */
6001#define EXTI_SWIER1_SWI31_Pos (31U)
6002#define EXTI_SWIER1_SWI31_Msk (0x1UL << EXTI_SWIER1_SWI31_Pos) /*!< 0x80000000 */
6003#define EXTI_SWIER1_SWI31 EXTI_SWIER1_SWI31_Msk /*!< Software Interrupt on line 31 */
6004
6005/******************* Bit definition for EXTI_SWIER2 register ***************/
6006#define EXTI_SWIER2_SWI32_Pos (0U)
6007#define EXTI_SWIER2_SWI32_Msk (0x1UL << EXTI_SWIER2_SWI32_Pos) /*!< 0x00000001 */
6008#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWI32_Msk /*!< Software Interrupt on line 32 */
6009#define EXTI_SWIER2_SWI33_Pos (1U)
6010#define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */
6011#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */
6012#define EXTI_SWIER2_SWI34_Pos (2U)
6013#define EXTI_SWIER2_SWI34_Msk (0x1UL << EXTI_SWIER2_SWI34_Pos) /*!< 0x00000004 */
6014#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWI34_Msk /*!< Software Interrupt on line 34 */
6015#define EXTI_SWIER2_SWI35_Pos (3U)
6016#define EXTI_SWIER2_SWI35_Msk (0x1UL << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
6017#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
6018#define EXTI_SWIER2_SWI36_Pos (4U)
6019#define EXTI_SWIER2_SWI36_Msk (0x1UL << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
6020#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
6021#define EXTI_SWIER2_SWI37_Pos (5U)
6022#define EXTI_SWIER2_SWI37_Msk (0x1UL << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
6023#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
6024#define EXTI_SWIER2_SWI38_Pos (6U)
6025#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
6026#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
6027#define EXTI_SWIER2_SWI39_Pos (7U)
6028#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */
6029#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on line 39 */
6030#define EXTI_SWIER2_SWI40_Pos (8U)
6031#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */
6032#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */
6033#define EXTI_SWIER2_SWI41_Pos (9U)
6034#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */
6035#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */
6036#define EXTI_SWIER2_SWI42_Pos (10U)
6037#define EXTI_SWIER2_SWI42_Msk (0x1UL << EXTI_SWIER2_SWI42_Pos) /*!< 0x00000400 */
6038#define EXTI_SWIER2_SWI42 EXTI_SWIER2_SWI42_Msk /*!< Software Interrupt on line 42 */
6039
6040/******************* Bit definition for EXTI_RPR1 register *****************/
6041#define EXTI_RPR1_RPIF0_Pos (0U)
6042#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */
6043#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */
6044#define EXTI_RPR1_RPIF1_Pos (1U)
6045#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */
6046#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */
6047#define EXTI_RPR1_RPIF2_Pos (2U)
6048#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */
6049#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */
6050#define EXTI_RPR1_RPIF3_Pos (3U)
6051#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */
6052#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */
6053#define EXTI_RPR1_RPIF4_Pos (4U)
6054#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */
6055#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */
6056#define EXTI_RPR1_RPIF5_Pos (5U)
6057#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */
6058#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */
6059#define EXTI_RPR1_RPIF6_Pos (6U)
6060#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */
6061#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */
6062#define EXTI_RPR1_RPIF7_Pos (7U)
6063#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */
6064#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */
6065#define EXTI_RPR1_RPIF8_Pos (8U)
6066#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */
6067#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */
6068#define EXTI_RPR1_RPIF9_Pos (9U)
6069#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */
6070#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */
6071#define EXTI_RPR1_RPIF10_Pos (10U)
6072#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */
6073#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */
6074#define EXTI_RPR1_RPIF11_Pos (11U)
6075#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */
6076#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */
6077#define EXTI_RPR1_RPIF12_Pos (12U)
6078#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */
6079#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */
6080#define EXTI_RPR1_RPIF13_Pos (13U)
6081#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */
6082#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */
6083#define EXTI_RPR1_RPIF14_Pos (14U)
6084#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */
6085#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */
6086#define EXTI_RPR1_RPIF15_Pos (15U)
6087#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */
6088#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */
6089#define EXTI_RPR1_RPIF16_Pos (16U)
6090#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */
6091#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< Rising Pending Interrupt Flag on line 16 */
6092#define EXTI_RPR1_RPIF21_Pos (21U)
6093#define EXTI_RPR1_RPIF21_Msk (0x1UL << EXTI_RPR1_RPIF21_Pos) /*!< 0x00200000 */
6094#define EXTI_RPR1_RPIF21 EXTI_RPR1_RPIF21_Msk /*!< Rising Pending Interrupt Flag on line 21 */
6095#define EXTI_RPR1_RPIF22_Pos (22U)
6096#define EXTI_RPR1_RPIF22_Msk (0x1UL << EXTI_RPR1_RPIF22_Pos) /*!< 0x00400000 */
6097#define EXTI_RPR1_RPIF22 EXTI_RPR1_RPIF22_Msk /*!< Rising Pending Interrupt Flag on line 22 */
6098#define EXTI_RPR1_RPIF23_Pos (23U)
6099#define EXTI_RPR1_RPIF23_Msk (0x1UL << EXTI_RPR1_RPIF23_Pos) /*!< 0x00800000 */
6100#define EXTI_RPR1_RPIF23 EXTI_RPR1_RPIF23_Msk /*!< Rising Pending Interrupt Flag on line 23 */
6101#define EXTI_RPR1_RPIF24_Pos (24U)
6102#define EXTI_RPR1_RPIF24_Msk (0x1UL << EXTI_RPR1_RPIF24_Pos) /*!< 0x01000000 */
6103#define EXTI_RPR1_RPIF24 EXTI_RPR1_RPIF24_Msk /*!< Rising Pending Interrupt Flag on line 24 */
6104#define EXTI_RPR1_RPIF25_Pos (25U)
6105#define EXTI_RPR1_RPIF25_Msk (0x1UL << EXTI_RPR1_RPIF25_Pos) /*!< 0x02000000 */
6106#define EXTI_RPR1_RPIF25 EXTI_RPR1_RPIF25_Msk /*!< Rising Pending Interrupt Flag on line 25 */
6107#define EXTI_RPR1_RPIF26_Pos (26U)
6108#define EXTI_RPR1_RPIF26_Msk (0x1UL << EXTI_RPR1_RPIF26_Pos) /*!< 0x04000000 */
6109#define EXTI_RPR1_RPIF26 EXTI_RPR1_RPIF26_Msk /*!< Rising Pending Interrupt Flag on line 26 */
6110#define EXTI_RPR1_RPIF27_Pos (27U)
6111#define EXTI_RPR1_RPIF27_Msk (0x1UL << EXTI_RPR1_RPIF27_Pos) /*!< 0x08000000 */
6112#define EXTI_RPR1_RPIF27 EXTI_RPR1_RPIF27_Msk /*!< Rising Pending Interrupt Flag on line 27 */
6113#define EXTI_RPR1_RPIF28_Pos (28U)
6114#define EXTI_RPR1_RPIF28_Msk (0x1UL << EXTI_RPR1_RPIF28_Pos) /*!< 0x10000000 */
6115#define EXTI_RPR1_RPIF28 EXTI_RPR1_RPIF28_Msk /*!< Rising Pending Interrupt Flag on line 28 */
6116#define EXTI_RPR1_RPIF29_Pos (29U)
6117#define EXTI_RPR1_RPIF29_Msk (0x1UL << EXTI_RPR1_RPIF29_Pos) /*!< 0x20000000 */
6118#define EXTI_RPR1_RPIF29 EXTI_RPR1_RPIF29_Msk /*!< Rising Pending Interrupt Flag on line 29 */
6119#define EXTI_RPR1_RPIF30_Pos (30U)
6120#define EXTI_RPR1_RPIF30_Msk (0x1UL << EXTI_RPR1_RPIF30_Pos) /*!< 0x40000000 */
6121#define EXTI_RPR1_RPIF30 EXTI_RPR1_RPIF30_Msk /*!< Rising Pending Interrupt Flag on line 30 */
6122#define EXTI_RPR1_RPIF31_Pos (31U)
6123#define EXTI_RPR1_RPIF31_Msk (0x1UL << EXTI_RPR1_RPIF31_Pos) /*!< 0x80000000 */
6124#define EXTI_RPR1_RPIF31 EXTI_RPR1_RPIF31_Msk /*!< Rising Pending Interrupt Flag on line 31 */
6125
6126/******************* Bit definition for EXTI_RPR2 register *****************/
6127#define EXTI_RPR2_RPIF32_Pos (0U)
6128#define EXTI_RPR2_RPIF32_Msk (0x1UL << EXTI_RPR2_RPIF32_Pos) /*!< 0x00000001 */
6129#define EXTI_RPR2_RPIF32 EXTI_RPR2_RPIF32_Msk /*!< Rising Pending Interrupt Flag on line 32 */
6130#define EXTI_RPR2_RPIF33_Pos (1U)
6131#define EXTI_RPR2_RPIF33_Msk (0x1UL << EXTI_RPR2_RPIF33_Pos) /*!< 0x00000002 */
6132#define EXTI_RPR2_RPIF33 EXTI_RPR2_RPIF33_Msk /*!< Rising Pending Interrupt Flag on line 33 */
6133#define EXTI_RPR2_RPIF34_Pos (2U)
6134#define EXTI_RPR2_RPIF34_Msk (0x1UL << EXTI_RPR2_RPIF34_Pos) /*!< 0x00000004 */
6135#define EXTI_RPR2_RPIF34 EXTI_RPR2_RPIF34_Msk /*!< Rising Pending Interrupt Flag on line 34 */
6136#define EXTI_RPR2_RPIF35_Pos (3U)
6137#define EXTI_RPR2_RPIF35_Msk (0x1UL << EXTI_RPR2_RPIF35_Pos) /*!< 0x00000008 */
6138#define EXTI_RPR2_RPIF35 EXTI_RPR2_RPIF35_Msk /*!< Rising Pending Interrupt Flag on line 35 */
6139#define EXTI_RPR2_RPIF36_Pos (4U)
6140#define EXTI_RPR2_RPIF36_Msk (0x1UL << EXTI_RPR2_RPIF36_Pos) /*!< 0x00000010 */
6141#define EXTI_RPR2_RPIF36 EXTI_RPR2_RPIF36_Msk /*!< Rising Pending Interrupt Flag on line 36 */
6142#define EXTI_RPR2_RPIF37_Pos (5U)
6143#define EXTI_RPR2_RPIF37_Msk (0x1UL << EXTI_RPR2_RPIF37_Pos) /*!< 0x00000020 */
6144#define EXTI_RPR2_RPIF37 EXTI_RPR2_RPIF37_Msk /*!< Rising Pending Interrupt Flag on line 37 */
6145#define EXTI_RPR2_RPIF38_Pos (6U)
6146#define EXTI_RPR2_RPIF38_Msk (0x1UL << EXTI_RPR2_RPIF38_Pos) /*!< 0x00000040 */
6147#define EXTI_RPR2_RPIF38 EXTI_RPR2_RPIF38_Msk /*!< Rising Pending Interrupt Flag on line 38 */
6148#define EXTI_RPR2_RPIF39_Pos (7U)
6149#define EXTI_RPR2_RPIF39_Msk (0x1UL << EXTI_RPR2_RPIF39_Pos) /*!< 0x00000080 */
6150#define EXTI_RPR2_RPIF39 EXTI_RPR2_RPIF39_Msk /*!< Rising Pending Interrupt Flag on line 39 */
6151#define EXTI_RPR2_RPIF40_Pos (8U)
6152#define EXTI_RPR2_RPIF40_Msk (0x1UL << EXTI_RPR2_RPIF40_Pos) /*!< 0x00000100 */
6153#define EXTI_RPR2_RPIF40 EXTI_RPR2_RPIF40_Msk /*!< Rising Pending Interrupt Flag on line 40 */
6154#define EXTI_RPR2_RPIF41_Pos (9U)
6155#define EXTI_RPR2_RPIF41_Msk (0x1UL << EXTI_RPR2_RPIF41_Pos) /*!< 0x00000200 */
6156#define EXTI_RPR2_RPIF41 EXTI_RPR2_RPIF41_Msk /*!< Rising Pending Interrupt Flag on line 41 */
6157#define EXTI_RPR2_RPIF42_Pos (10U)
6158#define EXTI_RPR2_RPIF42_Msk (0x1UL << EXTI_RPR2_RPIF42_Pos) /*!< 0x00000400 */
6159#define EXTI_RPR2_RPIF42 EXTI_RPR2_RPIF42_Msk /*!< Rising Pending Interrupt Flag on line 42 */
6160
6161/******************* Bit definition for EXTI_FPR1 register *****************/
6162#define EXTI_FPR1_FPIF0_Pos (0U)
6163#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */
6164#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */
6165#define EXTI_FPR1_FPIF1_Pos (1U)
6166#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */
6167#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */
6168#define EXTI_FPR1_FPIF2_Pos (2U)
6169#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */
6170#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */
6171#define EXTI_FPR1_FPIF3_Pos (3U)
6172#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */
6173#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */
6174#define EXTI_FPR1_FPIF4_Pos (4U)
6175#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */
6176#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */
6177#define EXTI_FPR1_FPIF5_Pos (5U)
6178#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */
6179#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */
6180#define EXTI_FPR1_FPIF6_Pos (6U)
6181#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */
6182#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */
6183#define EXTI_FPR1_FPIF7_Pos (7U)
6184#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */
6185#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */
6186#define EXTI_FPR1_FPIF8_Pos (8U)
6187#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */
6188#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */
6189#define EXTI_FPR1_FPIF9_Pos (9U)
6190#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */
6191#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */
6192#define EXTI_FPR1_FPIF10_Pos (10U)
6193#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */
6194#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */
6195#define EXTI_FPR1_FPIF11_Pos (11U)
6196#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */
6197#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */
6198#define EXTI_FPR1_FPIF12_Pos (12U)
6199#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */
6200#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */
6201#define EXTI_FPR1_FPIF13_Pos (13U)
6202#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */
6203#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */
6204#define EXTI_FPR1_FPIF14_Pos (14U)
6205#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */
6206#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */
6207#define EXTI_FPR1_FPIF15_Pos (15U)
6208#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */
6209#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */
6210#define EXTI_FPR1_FPIF16_Pos (16U)
6211#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */
6212#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< Falling Pending Interrupt Flag on line 16 */
6213#define EXTI_FPR1_FPIF21_Pos (21U)
6214#define EXTI_FPR1_FPIF21_Msk (0x1UL << EXTI_FPR1_FPIF21_Pos) /*!< 0x00200000 */
6215#define EXTI_FPR1_FPIF21 EXTI_FPR1_FPIF21_Msk /*!< Falling Pending Interrupt Flag on line 21 */
6216#define EXTI_FPR1_FPIF22_Pos (22U)
6217#define EXTI_FPR1_FPIF22_Msk (0x1UL << EXTI_FPR1_FPIF22_Pos) /*!< 0x00400000 */
6218#define EXTI_FPR1_FPIF22 EXTI_FPR1_FPIF22_Msk /*!< Falling Pending Interrupt Flag on line 22 */
6219#define EXTI_FPR1_FPIF23_Pos (23U)
6220#define EXTI_FPR1_FPIF23_Msk (0x1UL << EXTI_FPR1_FPIF23_Pos) /*!< 0x00800000 */
6221#define EXTI_FPR1_FPIF23 EXTI_FPR1_FPIF23_Msk /*!< Falling Pending Interrupt Flag on line 23 */
6222#define EXTI_FPR1_FPIF24_Pos (24U)
6223#define EXTI_FPR1_FPIF24_Msk (0x1UL << EXTI_FPR1_FPIF24_Pos) /*!< 0x01000000 */
6224#define EXTI_FPR1_FPIF24 EXTI_FPR1_FPIF24_Msk /*!< Falling Pending Interrupt Flag on line 24 */
6225#define EXTI_FPR1_FPIF25_Pos (25U)
6226#define EXTI_FPR1_FPIF25_Msk (0x1UL << EXTI_FPR1_FPIF25_Pos) /*!< 0x02000000 */
6227#define EXTI_FPR1_FPIF25 EXTI_FPR1_FPIF25_Msk /*!< Falling Pending Interrupt Flag on line 25 */
6228#define EXTI_FPR1_FPIF26_Pos (26U)
6229#define EXTI_FPR1_FPIF26_Msk (0x1UL << EXTI_FPR1_FPIF26_Pos) /*!< 0x04000000 */
6230#define EXTI_FPR1_FPIF26 EXTI_FPR1_FPIF26_Msk /*!< Falling Pending Interrupt Flag on line 26 */
6231#define EXTI_FPR1_FPIF27_Pos (27U)
6232#define EXTI_FPR1_FPIF27_Msk (0x1UL << EXTI_FPR1_FPIF27_Pos) /*!< 0x08000000 */
6233#define EXTI_FPR1_FPIF27 EXTI_FPR1_FPIF27_Msk /*!< Falling Pending Interrupt Flag on line 27 */
6234#define EXTI_FPR1_FPIF28_Pos (28U)
6235#define EXTI_FPR1_FPIF28_Msk (0x1UL << EXTI_FPR1_FPIF28_Pos) /*!< 0x10000000 */
6236#define EXTI_FPR1_FPIF28 EXTI_FPR1_FPIF28_Msk /*!< Falling Pending Interrupt Flag on line 28 */
6237#define EXTI_FPR1_FPIF29_Pos (29U)
6238#define EXTI_FPR1_FPIF29_Msk (0x1UL << EXTI_FPR1_FPIF29_Pos) /*!< 0x20000000 */
6239#define EXTI_FPR1_FPIF29 EXTI_FPR1_FPIF29_Msk /*!< Falling Pending Interrupt Flag on line 29 */
6240#define EXTI_FPR1_FPIF30_Pos (30U)
6241#define EXTI_FPR1_FPIF30_Msk (0x1UL << EXTI_FPR1_FPIF30_Pos) /*!< 0x40000000 */
6242#define EXTI_FPR1_FPIF30 EXTI_FPR1_FPIF30_Msk /*!< Falling Pending Interrupt Flag on line 30 */
6243#define EXTI_FPR1_FPIF31_Pos (31U)
6244#define EXTI_FPR1_FPIF31_Msk (0x1UL << EXTI_FPR1_FPIF31_Pos) /*!< 0x80000000 */
6245#define EXTI_FPR1_FPIF31 EXTI_FPR1_FPIF31_Msk /*!< Falling Pending Interrupt Flag on line 31 */
6246
6247/******************* Bit definition for EXTI_FPR2 register *****************/
6248#define EXTI_FPR2_FPIF32_Pos (0U)
6249#define EXTI_FPR2_FPIF32_Msk (0x1UL << EXTI_FPR2_FPIF32_Pos) /*!< 0x00000001 */
6250#define EXTI_FPR2_FPIF32 EXTI_FPR2_FPIF32_Msk /*!< Falling Pending Interrupt Flag on line 32 */
6251#define EXTI_FPR2_FPIF33_Pos (1U)
6252#define EXTI_FPR2_FPIF33_Msk (0x1UL << EXTI_FPR2_FPIF33_Pos) /*!< 0x00000002 */
6253#define EXTI_FPR2_FPIF33 EXTI_FPR2_FPIF33_Msk /*!< Falling Pending Interrupt Flag on line 33 */
6254#define EXTI_FPR2_FPIF34_Pos (2U)
6255#define EXTI_FPR2_FPIF34_Msk (0x1UL << EXTI_FPR2_FPIF34_Pos) /*!< 0x00000004 */
6256#define EXTI_FPR2_FPIF34 EXTI_FPR2_FPIF34_Msk /*!< Falling Pending Interrupt Flag on line 34 */
6257#define EXTI_FPR2_FPIF35_Pos (3U)
6258#define EXTI_FPR2_FPIF35_Msk (0x1UL << EXTI_FPR2_FPIF35_Pos) /*!< 0x00000008 */
6259#define EXTI_FPR2_FPIF35 EXTI_FPR2_FPIF35_Msk /*!< Falling Pending Interrupt Flag on line 35 */
6260#define EXTI_FPR2_FPIF36_Pos (4U)
6261#define EXTI_FPR2_FPIF36_Msk (0x1UL << EXTI_FPR2_FPIF36_Pos) /*!< 0x00000010 */
6262#define EXTI_FPR2_FPIF36 EXTI_FPR2_FPIF36_Msk /*!< Falling Pending Interrupt Flag on line 36 */
6263#define EXTI_FPR2_FPIF37_Pos (5U)
6264#define EXTI_FPR2_FPIF37_Msk (0x1UL << EXTI_FPR2_FPIF37_Pos) /*!< 0x00000020 */
6265#define EXTI_FPR2_FPIF37 EXTI_FPR2_FPIF37_Msk /*!< Falling Pending Interrupt Flag on line 37 */
6266#define EXTI_FPR2_FPIF38_Pos (6U)
6267#define EXTI_FPR2_FPIF38_Msk (0x1UL << EXTI_FPR2_FPIF38_Pos) /*!< 0x00000040 */
6268#define EXTI_FPR2_FPIF38 EXTI_FPR2_FPIF38_Msk /*!< Falling Pending Interrupt Flag on line 38 */
6269#define EXTI_FPR2_FPIF39_Pos (7U)
6270#define EXTI_FPR2_FPIF39_Msk (0x1UL << EXTI_FPR2_FPIF39_Pos) /*!< 0x00000080 */
6271#define EXTI_FPR2_FPIF39 EXTI_FPR2_FPIF39_Msk /*!< Falling Pending Interrupt Flag on line 39 */
6272#define EXTI_FPR2_FPIF40_Pos (8U)
6273#define EXTI_FPR2_FPIF40_Msk (0x1UL << EXTI_FPR2_FPIF40_Pos) /*!< 0x00000100 */
6274#define EXTI_FPR2_FPIF40 EXTI_FPR2_FPIF40_Msk /*!< Falling Pending Interrupt Flag on line 40 */
6275#define EXTI_FPR2_FPIF41_Pos (9U)
6276#define EXTI_FPR2_FPIF41_Msk (0x1UL << EXTI_FPR2_FPIF41_Pos) /*!< 0x00000200 */
6277#define EXTI_FPR2_FPIF41 EXTI_FPR2_FPIF41_Msk /*!< Falling Pending Interrupt Flag on line 41 */
6278#define EXTI_FPR2_FPIF42_Pos (10U)
6279#define EXTI_FPR2_FPIF42_Msk (0x1UL << EXTI_FPR2_FPIF42_Pos) /*!< 0x00000400 */
6280#define EXTI_FPR2_FPIF42 EXTI_FPR2_FPIF42_Msk /*!< Falling Pending Interrupt Flag on line 42 */
6281
6282/******************* Bit definition for EXTI_SECCFGR1 register *************/
6283#define EXTI_SECCFGR1_SEC0_Pos (0U)
6284#define EXTI_SECCFGR1_SEC0_Msk (0x1UL << EXTI_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */
6285#define EXTI_SECCFGR1_SEC0 EXTI_SECCFGR1_SEC0_Msk /*!< Security enable on Event input 0 */
6286#define EXTI_SECCFGR1_SEC1_Pos (1U)
6287#define EXTI_SECCFGR1_SEC1_Msk (0x1UL << EXTI_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */
6288#define EXTI_SECCFGR1_SEC1 EXTI_SECCFGR1_SEC1_Msk /*!< Security enable on Event input 1 */
6289#define EXTI_SECCFGR1_SEC2_Pos (2U)
6290#define EXTI_SECCFGR1_SEC2_Msk (0x1UL << EXTI_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */
6291#define EXTI_SECCFGR1_SEC2 EXTI_SECCFGR1_SEC2_Msk /*!< Security enable on Event input 2 */
6292#define EXTI_SECCFGR1_SEC3_Pos (3U)
6293#define EXTI_SECCFGR1_SEC3_Msk (0x1UL << EXTI_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */
6294#define EXTI_SECCFGR1_SEC3 EXTI_SECCFGR1_SEC3_Msk /*!< Security enable on Event input 3 */
6295#define EXTI_SECCFGR1_SEC4_Pos (4U)
6296#define EXTI_SECCFGR1_SEC4_Msk (0x1UL << EXTI_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */
6297#define EXTI_SECCFGR1_SEC4 EXTI_SECCFGR1_SEC4_Msk /*!< Security enable on Event input 4 */
6298#define EXTI_SECCFGR1_SEC5_Pos (5U)
6299#define EXTI_SECCFGR1_SEC5_Msk (0x1UL << EXTI_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */
6300#define EXTI_SECCFGR1_SEC5 EXTI_SECCFGR1_SEC5_Msk /*!< Security enable on Event input 5 */
6301#define EXTI_SECCFGR1_SEC6_Pos (6U)
6302#define EXTI_SECCFGR1_SEC6_Msk (0x1UL << EXTI_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */
6303#define EXTI_SECCFGR1_SEC6 EXTI_SECCFGR1_SEC6_Msk /*!< Security enable on Event input 6 */
6304#define EXTI_SECCFGR1_SEC7_Pos (7U)
6305#define EXTI_SECCFGR1_SEC7_Msk (0x1UL << EXTI_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */
6306#define EXTI_SECCFGR1_SEC7 EXTI_SECCFGR1_SEC7_Msk /*!< Security enable on Event input 7 */
6307#define EXTI_SECCFGR1_SEC8_Pos (8U)
6308#define EXTI_SECCFGR1_SEC8_Msk (0x1UL << EXTI_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */
6309#define EXTI_SECCFGR1_SEC8 EXTI_SECCFGR1_SEC8_Msk /*!< Security enable on Event input 8 */
6310#define EXTI_SECCFGR1_SEC9_Pos (9U)
6311#define EXTI_SECCFGR1_SEC9_Msk (0x1UL << EXTI_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */
6312#define EXTI_SECCFGR1_SEC9 EXTI_SECCFGR1_SEC9_Msk /*!< Security enable on Event input 9 */
6313#define EXTI_SECCFGR1_SEC10_Pos (10U)
6314#define EXTI_SECCFGR1_SEC10_Msk (0x1UL << EXTI_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */
6315#define EXTI_SECCFGR1_SEC10 EXTI_SECCFGR1_SEC10_Msk /*!< Security enable on Event input 10 */
6316#define EXTI_SECCFGR1_SEC11_Pos (11U)
6317#define EXTI_SECCFGR1_SEC11_Msk (0x1UL << EXTI_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */
6318#define EXTI_SECCFGR1_SEC11 EXTI_SECCFGR1_SEC11_Msk /*!< Security enable on Event input 11 */
6319#define EXTI_SECCFGR1_SEC12_Pos (12U)
6320#define EXTI_SECCFGR1_SEC12_Msk (0x1UL << EXTI_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */
6321#define EXTI_SECCFGR1_SEC12 EXTI_SECCFGR1_SEC12_Msk /*!< Security enable on Event input 12 */
6322#define EXTI_SECCFGR1_SEC13_Pos (13U)
6323#define EXTI_SECCFGR1_SEC13_Msk (0x1UL << EXTI_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */
6324#define EXTI_SECCFGR1_SEC13 EXTI_SECCFGR1_SEC13_Msk /*!< Security enable on Event input 13 */
6325#define EXTI_SECCFGR1_SEC14_Pos (14U)
6326#define EXTI_SECCFGR1_SEC14_Msk (0x1UL << EXTI_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */
6327#define EXTI_SECCFGR1_SEC14 EXTI_SECCFGR1_SEC14_Msk /*!< Security enable on Event input 14 */
6328#define EXTI_SECCFGR1_SEC15_Pos (15U)
6329#define EXTI_SECCFGR1_SEC15_Msk (0x1UL << EXTI_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */
6330#define EXTI_SECCFGR1_SEC15 EXTI_SECCFGR1_SEC15_Msk /*!< Security enable on Event input 15 */
6331#define EXTI_SECCFGR1_SEC16_Pos (16U)
6332#define EXTI_SECCFGR1_SEC16_Msk (0x1UL << EXTI_SECCFGR1_SEC16_Pos) /*!< 0x00010000 */
6333#define EXTI_SECCFGR1_SEC16 EXTI_SECCFGR1_SEC16_Msk /*!< Security enable on Event input 16 */
6334#define EXTI_SECCFGR1_SEC17_Pos (17U)
6335#define EXTI_SECCFGR1_SEC17_Msk (0x1UL << EXTI_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */
6336#define EXTI_SECCFGR1_SEC17 EXTI_SECCFGR1_SEC17_Msk /*!< Security enable on Event input 17 */
6337#define EXTI_SECCFGR1_SEC18_Pos (18U)
6338#define EXTI_SECCFGR1_SEC18_Msk (0x1UL << EXTI_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */
6339#define EXTI_SECCFGR1_SEC18 EXTI_SECCFGR1_SEC18_Msk /*!< Security enable on Event input 18 */
6340#define EXTI_SECCFGR1_SEC19_Pos (19U)
6341#define EXTI_SECCFGR1_SEC19_Msk (0x1UL << EXTI_SECCFGR1_SEC19_Pos) /*!< 0x00080000 */
6342#define EXTI_SECCFGR1_SEC19 EXTI_SECCFGR1_SEC19_Msk /*!< Security enable on Event input 19 */
6343#define EXTI_SECCFGR1_SEC20_Pos (20U)
6344#define EXTI_SECCFGR1_SEC20_Msk (0x1UL << EXTI_SECCFGR1_SEC20_Pos) /*!< 0x00100000 */
6345#define EXTI_SECCFGR1_SEC20 EXTI_SECCFGR1_SEC20_Msk /*!< Security enable on Event input 20 */
6346#define EXTI_SECCFGR1_SEC21_Pos (21U)
6347#define EXTI_SECCFGR1_SEC21_Msk (0x1UL << EXTI_SECCFGR1_SEC21_Pos) /*!< 0x00200000 */
6348#define EXTI_SECCFGR1_SEC21 EXTI_SECCFGR1_SEC21_Msk /*!< Security enable on Event input 21 */
6349#define EXTI_SECCFGR1_SEC22_Pos (22U)
6350#define EXTI_SECCFGR1_SEC22_Msk (0x1UL << EXTI_SECCFGR1_SEC22_Pos) /*!< 0x00400000 */
6351#define EXTI_SECCFGR1_SEC22 EXTI_SECCFGR1_SEC22_Msk /*!< Security enable on Event input 22 */
6352#define EXTI_SECCFGR1_SEC23_Pos (23U)
6353#define EXTI_SECCFGR1_SEC23_Msk (0x1UL << EXTI_SECCFGR1_SEC23_Pos) /*!< 0x00800000 */
6354#define EXTI_SECCFGR1_SEC23 EXTI_SECCFGR1_SEC23_Msk /*!< Security enable on Event input 23 */
6355#define EXTI_SECCFGR1_SEC24_Pos (24U)
6356#define EXTI_SECCFGR1_SEC24_Msk (0x1UL << EXTI_SECCFGR1_SEC24_Pos) /*!< 0x01000000 */
6357#define EXTI_SECCFGR1_SEC24 EXTI_SECCFGR1_SEC24_Msk /*!< Security enable on Event input 24 */
6358#define EXTI_SECCFGR1_SEC25_Pos (25U)
6359#define EXTI_SECCFGR1_SEC25_Msk (0x1UL << EXTI_SECCFGR1_SEC25_Pos) /*!< 0x02000000 */
6360#define EXTI_SECCFGR1_SEC25 EXTI_SECCFGR1_SEC25_Msk /*!< Security enable on Event input 25 */
6361#define EXTI_SECCFGR1_SEC26_Pos (26U)
6362#define EXTI_SECCFGR1_SEC26_Msk (0x1UL << EXTI_SECCFGR1_SEC26_Pos) /*!< 0x04000000 */
6363#define EXTI_SECCFGR1_SEC26 EXTI_SECCFGR1_SEC26_Msk /*!< Security enable on Event input 26 */
6364#define EXTI_SECCFGR1_SEC27_Pos (27U)
6365#define EXTI_SECCFGR1_SEC27_Msk (0x1UL << EXTI_SECCFGR1_SEC27_Pos) /*!< 0x08000000 */
6366#define EXTI_SECCFGR1_SEC27 EXTI_SECCFGR1_SEC27_Msk /*!< Security enable on Event input 27 */
6367#define EXTI_SECCFGR1_SEC28_Pos (28U)
6368#define EXTI_SECCFGR1_SEC28_Msk (0x1UL << EXTI_SECCFGR1_SEC28_Pos) /*!< 0x10000000 */
6369#define EXTI_SECCFGR1_SEC28 EXTI_SECCFGR1_SEC28_Msk /*!< Security enable on Event input 28 */
6370#define EXTI_SECCFGR1_SEC29_Pos (29U)
6371#define EXTI_SECCFGR1_SEC29_Msk (0x1UL << EXTI_SECCFGR1_SEC29_Pos) /*!< 0x20000000 */
6372#define EXTI_SECCFGR1_SEC29 EXTI_SECCFGR1_SEC29_Msk /*!< Security enable on Event input 29 */
6373#define EXTI_SECCFGR1_SEC30_Pos (30U)
6374#define EXTI_SECCFGR1_SEC30_Msk (0x1UL << EXTI_SECCFGR1_SEC30_Pos) /*!< 0x40000000 */
6375#define EXTI_SECCFGR1_SEC30 EXTI_SECCFGR1_SEC30_Msk /*!< Security enable on Event input 30 */
6376#define EXTI_SECCFGR1_SEC31_Pos (31U)
6377#define EXTI_SECCFGR1_SEC31_Msk (0x1UL << EXTI_SECCFGR1_SEC31_Pos) /*!< 0x80000000 */
6378#define EXTI_SECCFGR1_SEC31 EXTI_SECCFGR1_SEC31_Msk /*!< Security enable on Event input 31 */
6379
6380/******************* Bit definition for EXTI_SECCFGR2 register *************/
6381#define EXTI_SECCFGR2_SEC32_Pos (0U)
6382#define EXTI_SECCFGR2_SEC32_Msk (0x1UL << EXTI_SECCFGR2_SEC32_Pos) /*!< 0x00000001 */
6383#define EXTI_SECCFGR2_SEC32 EXTI_SECCFGR2_SEC32_Msk /*!< Security enable on Event input 32 */
6384#define EXTI_SECCFGR2_SEC33_Pos (1U)
6385#define EXTI_SECCFGR2_SEC33_Msk (0x1UL << EXTI_SECCFGR2_SEC33_Pos) /*!< 0x00000002 */
6386#define EXTI_SECCFGR2_SEC33 EXTI_SECCFGR2_SEC33_Msk /*!< Security enable on Event input 33 */
6387#define EXTI_SECCFGR2_SEC34_Pos (2U)
6388#define EXTI_SECCFGR2_SEC34_Msk (0x1UL << EXTI_SECCFGR2_SEC34_Pos) /*!< 0x00000004 */
6389#define EXTI_SECCFGR2_SEC34 EXTI_SECCFGR2_SEC34_Msk /*!< Security enable on Event input 34 */
6390#define EXTI_SECCFGR2_SEC35_Pos (3U)
6391#define EXTI_SECCFGR2_SEC35_Msk (0x1UL << EXTI_SECCFGR2_SEC35_Pos) /*!< 0x00000008 */
6392#define EXTI_SECCFGR2_SEC35 EXTI_SECCFGR2_SEC35_Msk /*!< Security enable on Event input 35 */
6393#define EXTI_SECCFGR2_SEC36_Pos (4U)
6394#define EXTI_SECCFGR2_SEC36_Msk (0x1UL << EXTI_SECCFGR2_SEC36_Pos) /*!< 0x00000010 */
6395#define EXTI_SECCFGR2_SEC36 EXTI_SECCFGR2_SEC36_Msk /*!< Security enable on Event input 36 */
6396#define EXTI_SECCFGR2_SEC37_Pos (5U)
6397#define EXTI_SECCFGR2_SEC37_Msk (0x1UL << EXTI_SECCFGR2_SEC37_Pos) /*!< 0x00000020 */
6398#define EXTI_SECCFGR2_SEC37 EXTI_SECCFGR2_SEC37_Msk /*!< Security enable on Event input 37 */
6399#define EXTI_SECCFGR2_SEC38_Pos (6U)
6400#define EXTI_SECCFGR2_SEC38_Msk (0x1UL << EXTI_SECCFGR2_SEC38_Pos) /*!< 0x00000040 */
6401#define EXTI_SECCFGR2_SEC38 EXTI_SECCFGR2_SEC38_Msk /*!< Security enable on Event input 38 */
6402#define EXTI_SECCFGR2_SEC39_Pos (7U)
6403#define EXTI_SECCFGR2_SEC39_Msk (0x1UL << EXTI_SECCFGR2_SEC39_Pos) /*!< 0x00000080 */
6404#define EXTI_SECCFGR2_SEC39 EXTI_SECCFGR2_SEC39_Msk /*!< Security enable on Event input 39 */
6405#define EXTI_SECCFGR2_SEC40_Pos (8U)
6406#define EXTI_SECCFGR2_SEC40_Msk (0x1UL << EXTI_SECCFGR2_SEC40_Pos) /*!< 0x00000100 */
6407#define EXTI_SECCFGR2_SEC40 EXTI_SECCFGR2_SEC40_Msk /*!< Security enable on Event input 40 */
6408#define EXTI_SECCFGR2_SEC41_Pos (9U)
6409#define EXTI_SECCFGR2_SEC41_Msk (0x1UL << EXTI_SECCFGR2_SEC41_Pos) /*!< 0x00000200 */
6410#define EXTI_SECCFGR2_SEC41 EXTI_SECCFGR2_SEC41_Msk /*!< Security enable on Event input 41 */
6411#define EXTI_SECCFGR2_SEC42_Pos (10U)
6412#define EXTI_SECCFGR2_SEC42_Msk (0x1UL << EXTI_SECCFGR2_SEC42_Pos) /*!< 0x00000400 */
6413#define EXTI_SECCFGR2_SEC42 EXTI_SECCFGR2_SEC42_Msk /*!< Security enable on Event input 42 */
6414
6415/******************* Bit definition for EXTI_PRIVCFGR1 register ************/
6416#define EXTI_PRIVCFGR1_PRIV0_Pos (0U)
6417#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */
6418#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on Event input 0 */
6419#define EXTI_PRIVCFGR1_PRIV1_Pos (1U)
6420#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */
6421#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on Event input 1 */
6422#define EXTI_PRIVCFGR1_PRIV2_Pos (2U)
6423#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */
6424#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on Event input 2 */
6425#define EXTI_PRIVCFGR1_PRIV3_Pos (3U)
6426#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */
6427#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on Event input 3 */
6428#define EXTI_PRIVCFGR1_PRIV4_Pos (4U)
6429#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */
6430#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on Event input 4 */
6431#define EXTI_PRIVCFGR1_PRIV5_Pos (5U)
6432#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */
6433#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on Event input 5 */
6434#define EXTI_PRIVCFGR1_PRIV6_Pos (6U)
6435#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */
6436#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on Event input 6 */
6437#define EXTI_PRIVCFGR1_PRIV7_Pos (7U)
6438#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */
6439#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on Event input 7 */
6440#define EXTI_PRIVCFGR1_PRIV8_Pos (8U)
6441#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */
6442#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on Event input 8 */
6443#define EXTI_PRIVCFGR1_PRIV9_Pos (9U)
6444#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */
6445#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on Event input 9 */
6446#define EXTI_PRIVCFGR1_PRIV10_Pos (10U)
6447#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */
6448#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on Event input 10 */
6449#define EXTI_PRIVCFGR1_PRIV11_Pos (11U)
6450#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */
6451#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on Event input 11 */
6452#define EXTI_PRIVCFGR1_PRIV12_Pos (12U)
6453#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */
6454#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on Event input 12 */
6455#define EXTI_PRIVCFGR1_PRIV13_Pos (13U)
6456#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */
6457#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on Event input 13 */
6458#define EXTI_PRIVCFGR1_PRIV14_Pos (14U)
6459#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */
6460#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on Event input 14 */
6461#define EXTI_PRIVCFGR1_PRIV15_Pos (15U)
6462#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */
6463#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on Event input 15 */
6464#define EXTI_PRIVCFGR1_PRIV16_Pos (16U)
6465#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */
6466#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on Event input 16 */
6467#define EXTI_PRIVCFGR1_PRIV17_Pos (17U)
6468#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */
6469#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on Event input 17 */
6470#define EXTI_PRIVCFGR1_PRIV18_Pos (18U)
6471#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */
6472#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on Event input 18 */
6473#define EXTI_PRIVCFGR1_PRIV19_Pos (19U)
6474#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */
6475#define EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk /*!< Privilege enable on Event input 19 */
6476#define EXTI_PRIVCFGR1_PRIV20_Pos (20U)
6477#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */
6478#define EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk /*!< Privilege enable on Event input 20 */
6479#define EXTI_PRIVCFGR1_PRIV21_Pos (21U)
6480#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */
6481#define EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk /*!< Privilege enable on Event input 21 */
6482#define EXTI_PRIVCFGR1_PRIV22_Pos (22U)
6483#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */
6484#define EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk /*!< Privilege enable on Event input 22 */
6485#define EXTI_PRIVCFGR1_PRIV23_Pos (23U)
6486#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */
6487#define EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk /*!< Privilege enable on Event input 23 */
6488#define EXTI_PRIVCFGR1_PRIV24_Pos (24U)
6489#define EXTI_PRIVCFGR1_PRIV24_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */
6490#define EXTI_PRIVCFGR1_PRIV24 EXTI_PRIVCFGR1_PRIV24_Msk /*!< Privilege enable on Event input 24 */
6491#define EXTI_PRIVCFGR1_PRIV25_Pos (25U)
6492#define EXTI_PRIVCFGR1_PRIV25_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */
6493#define EXTI_PRIVCFGR1_PRIV25 EXTI_PRIVCFGR1_PRIV25_Msk /*!< Privilege enable on Event input 25 */
6494#define EXTI_PRIVCFGR1_PRIV26_Pos (26U)
6495#define EXTI_PRIVCFGR1_PRIV26_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */
6496#define EXTI_PRIVCFGR1_PRIV26 EXTI_PRIVCFGR1_PRIV26_Msk /*!< Privilege enable on Event input 26 */
6497#define EXTI_PRIVCFGR1_PRIV27_Pos (27U)
6498#define EXTI_PRIVCFGR1_PRIV27_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */
6499#define EXTI_PRIVCFGR1_PRIV27 EXTI_PRIVCFGR1_PRIV27_Msk /*!< Privilege enable on Event input 27 */
6500#define EXTI_PRIVCFGR1_PRIV28_Pos (28U)
6501#define EXTI_PRIVCFGR1_PRIV28_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */
6502#define EXTI_PRIVCFGR1_PRIV28 EXTI_PRIVCFGR1_PRIV28_Msk /*!< Privilege enable on Event input 28 */
6503#define EXTI_PRIVCFGR1_PRIV29_Pos (29U)
6504#define EXTI_PRIVCFGR1_PRIV29_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */
6505#define EXTI_PRIVCFGR1_PRIV29 EXTI_PRIVCFGR1_PRIV29_Msk /*!< Privilege enable on Event input 29 */
6506#define EXTI_PRIVCFGR1_PRIV30_Pos (30U)
6507#define EXTI_PRIVCFGR1_PRIV30_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */
6508#define EXTI_PRIVCFGR1_PRIV30 EXTI_PRIVCFGR1_PRIV30_Msk /*!< Privilege enable on Event input 30 */
6509#define EXTI_PRIVCFGR1_PRIV31_Pos (31U)
6510#define EXTI_PRIVCFGR1_PRIV31_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */
6511#define EXTI_PRIVCFGR1_PRIV31 EXTI_PRIVCFGR1_PRIV31_Msk /*!< Privilege enable on Event input 31 */
6512
6513/******************* Bit definition for EXTI_PRIVCFGR2 register ************/
6514#define EXTI_PRIVCFGR2_PRIV32_Pos (0U)
6515#define EXTI_PRIVCFGR2_PRIV32_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos) /*!< 0x00000001 */
6516#define EXTI_PRIVCFGR2_PRIV32 EXTI_PRIVCFGR2_PRIV32_Msk /*!< Privilege enable on Event input 32 */
6517#define EXTI_PRIVCFGR2_PRIV33_Pos (1U)
6518#define EXTI_PRIVCFGR2_PRIV33_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos) /*!< 0x00000002 */
6519#define EXTI_PRIVCFGR2_PRIV33 EXTI_PRIVCFGR2_PRIV33_Msk /*!< Privilege enable on Event input 33 */
6520#define EXTI_PRIVCFGR2_PRIV34_Pos (2U)
6521#define EXTI_PRIVCFGR2_PRIV34_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos) /*!< 0x00000004 */
6522#define EXTI_PRIVCFGR2_PRIV34 EXTI_PRIVCFGR2_PRIV34_Msk /*!< Privilege enable on Event input 34 */
6523#define EXTI_PRIVCFGR2_PRIV35_Pos (3U)
6524#define EXTI_PRIVCFGR2_PRIV35_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos) /*!< 0x00000008 */
6525#define EXTI_PRIVCFGR2_PRIV35 EXTI_PRIVCFGR2_PRIV35_Msk /*!< Privilege enable on Event input 35 */
6526#define EXTI_PRIVCFGR2_PRIV36_Pos (4U)
6527#define EXTI_PRIVCFGR2_PRIV36_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV36_Pos) /*!< 0x00000010 */
6528#define EXTI_PRIVCFGR2_PRIV36 EXTI_PRIVCFGR2_PRIV36_Msk /*!< Privilege enable on Event input 36 */
6529#define EXTI_PRIVCFGR2_PRIV37_Pos (5U)
6530#define EXTI_PRIVCFGR2_PRIV37_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV37_Pos) /*!< 0x00000020 */
6531#define EXTI_PRIVCFGR2_PRIV37 EXTI_PRIVCFGR2_PRIV37_Msk /*!< Privilege enable on Event input 37 */
6532#define EXTI_PRIVCFGR2_PRIV38_Pos (6U)
6533#define EXTI_PRIVCFGR2_PRIV38_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV38_Pos) /*!< 0x00000040 */
6534#define EXTI_PRIVCFGR2_PRIV38 EXTI_PRIVCFGR2_PRIV38_Msk /*!< Privilege enable on Event input 38 */
6535#define EXTI_PRIVCFGR2_PRIV39_Pos (7U)
6536#define EXTI_PRIVCFGR2_PRIV39_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV39_Pos) /*!< 0x00000080 */
6537#define EXTI_PRIVCFGR2_PRIV39 EXTI_PRIVCFGR2_PRIV39_Msk /*!< Privilege enable on Event input 39 */
6538#define EXTI_PRIVCFGR2_PRIV40_Pos (8U)
6539#define EXTI_PRIVCFGR2_PRIV40_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV40_Pos) /*!< 0x00000100 */
6540#define EXTI_PRIVCFGR2_PRIV40 EXTI_PRIVCFGR2_PRIV40_Msk /*!< Privilege enable on Event input 40 */
6541#define EXTI_PRIVCFGR2_PRIV41_Pos (9U)
6542#define EXTI_PRIVCFGR2_PRIV41_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV41_Pos) /*!< 0x00000200 */
6543#define EXTI_PRIVCFGR2_PRIV41 EXTI_PRIVCFGR2_PRIV41_Msk /*!< Privilege enable on Event input 41 */
6544#define EXTI_PRIVCFGR2_PRIV42_Pos (10U)
6545#define EXTI_PRIVCFGR2_PRIV42_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV42_Pos) /*!< 0x00000400 */
6546#define EXTI_PRIVCFGR2_PRIV42 EXTI_PRIVCFGR2_PRIV42_Msk /*!< Privilege enable on Event input 42 */
6547
6548/***************** Bit definition for EXTI_EXTICR1 register **************/
6549#define EXTI_EXTICR1_EXTI0_Pos (0U)
6550#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
6551#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
6552#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */
6553#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */
6554#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */
6555#define EXTI_EXTICR1_EXTI1_Pos (8U)
6556#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */
6557#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
6558#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */
6559#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */
6560#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */
6561#define EXTI_EXTICR1_EXTI2_Pos (16U)
6562#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */
6563#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
6564#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */
6565#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */
6566#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */
6567#define EXTI_EXTICR1_EXTI3_Pos (24U)
6568#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */
6569#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
6570#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */
6571#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */
6572#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */
6573
6574/***************** Bit definition for EXTI_EXTICR2 register **************/
6575#define EXTI_EXTICR2_EXTI4_Pos (0U)
6576#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
6577#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
6578#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */
6579#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */
6580#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */
6581#define EXTI_EXTICR2_EXTI5_Pos (8U)
6582#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */
6583#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
6584#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */
6585#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */
6586#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */
6587#define EXTI_EXTICR2_EXTI6_Pos (16U)
6588#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */
6589#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
6590#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */
6591#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */
6592#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */
6593#define EXTI_EXTICR2_EXTI7_Pos (24U)
6594#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */
6595#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
6596#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */
6597#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */
6598#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */
6599
6600/***************** Bit definition for EXTI_EXTICR3 register **************/
6601#define EXTI_EXTICR3_EXTI8_Pos (0U)
6602#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
6603#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
6604#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */
6605#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */
6606#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */
6607#define EXTI_EXTICR3_EXTI9_Pos (8U)
6608#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */
6609#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
6610#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */
6611#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */
6612#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */
6613#define EXTI_EXTICR3_EXTI10_Pos (16U)
6614#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */
6615#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
6616#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */
6617#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */
6618#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */
6619#define EXTI_EXTICR3_EXTI11_Pos (24U)
6620#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */
6621#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
6622#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */
6623#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */
6624#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */
6625
6626/***************** Bit definition for EXTI_EXTICR4 register **************/
6627#define EXTI_EXTICR4_EXTI12_Pos (0U)
6628#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
6629#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
6630#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */
6631#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */
6632#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */
6633#define EXTI_EXTICR4_EXTI13_Pos (8U)
6634#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */
6635#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
6636#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */
6637#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */
6638#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */
6639#define EXTI_EXTICR4_EXTI14_Pos (16U)
6640#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */
6641#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
6642#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */
6643#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */
6644#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */
6645#define EXTI_EXTICR4_EXTI15_Pos (24U)
6646#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */
6647#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
6648#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */
6649#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */
6650#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */
6651
6652/******************* Bit definition for EXTI_LOCKR register ****************/
6653#define EXTI_LOCKR_LOCK_Pos (0U)
6654#define EXTI_LOCKR_LOCK_Msk (0x1UL << EXTI_LOCKR_LOCK_Pos) /*!< 0x00000001 */
6655#define EXTI_LOCKR_LOCK EXTI_LOCKR_LOCK_Msk /*!< Global security and privilege configuration lock */
6656
6657/******************* Bit definition for EXTI_IMR1 register *****************/
6658#define EXTI_IMR1_IM0_Pos (0U)
6659#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
6660#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
6661#define EXTI_IMR1_IM1_Pos (1U)
6662#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
6663#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
6664#define EXTI_IMR1_IM2_Pos (2U)
6665#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
6666#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
6667#define EXTI_IMR1_IM3_Pos (3U)
6668#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
6669#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
6670#define EXTI_IMR1_IM4_Pos (4U)
6671#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
6672#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
6673#define EXTI_IMR1_IM5_Pos (5U)
6674#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
6675#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
6676#define EXTI_IMR1_IM6_Pos (6U)
6677#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
6678#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
6679#define EXTI_IMR1_IM7_Pos (7U)
6680#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
6681#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
6682#define EXTI_IMR1_IM8_Pos (8U)
6683#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
6684#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
6685#define EXTI_IMR1_IM9_Pos (9U)
6686#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
6687#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
6688#define EXTI_IMR1_IM10_Pos (10U)
6689#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
6690#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
6691#define EXTI_IMR1_IM11_Pos (11U)
6692#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
6693#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
6694#define EXTI_IMR1_IM12_Pos (12U)
6695#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
6696#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
6697#define EXTI_IMR1_IM13_Pos (13U)
6698#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
6699#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
6700#define EXTI_IMR1_IM14_Pos (14U)
6701#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
6702#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
6703#define EXTI_IMR1_IM15_Pos (15U)
6704#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
6705#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
6706#define EXTI_IMR1_IM16_Pos (16U)
6707#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
6708#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
6709#define EXTI_IMR1_IM17_Pos (17U)
6710#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
6711#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
6712#define EXTI_IMR1_IM18_Pos (18U)
6713#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
6714#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
6715#define EXTI_IMR1_IM19_Pos (19U)
6716#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
6717#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
6718#define EXTI_IMR1_IM20_Pos (20U)
6719#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
6720#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
6721#define EXTI_IMR1_IM21_Pos (21U)
6722#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
6723#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
6724#define EXTI_IMR1_IM22_Pos (22U)
6725#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
6726#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
6727#define EXTI_IMR1_IM23_Pos (23U)
6728#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
6729#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
6730#define EXTI_IMR1_IM24_Pos (24U)
6731#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
6732#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
6733#define EXTI_IMR1_IM25_Pos (25U)
6734#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
6735#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
6736#define EXTI_IMR1_IM26_Pos (26U)
6737#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
6738#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
6739#define EXTI_IMR1_IM27_Pos (27U)
6740#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
6741#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
6742#define EXTI_IMR1_IM28_Pos (28U)
6743#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
6744#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
6745#define EXTI_IMR1_IM29_Pos (29U)
6746#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
6747#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
6748#define EXTI_IMR1_IM30_Pos (30U)
6749#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
6750#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
6751#define EXTI_IMR1_IM31_Pos (31U)
6752#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
6753#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
6754#define EXTI_IMR1_IM_Pos (0U)
6755#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
6756#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
6757
6758/******************* Bit definition for EXTI_IMR2 register *****************/
6759#define EXTI_IMR2_IM32_Pos (0U)
6760#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
6761#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
6762#define EXTI_IMR2_IM33_Pos (1U)
6763#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
6764#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
6765#define EXTI_IMR2_IM34_Pos (2U)
6766#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
6767#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
6768#define EXTI_IMR2_IM35_Pos (3U)
6769#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
6770#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
6771#define EXTI_IMR2_IM36_Pos (4U)
6772#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
6773#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
6774#define EXTI_IMR2_IM37_Pos (5U)
6775#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
6776#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
6777#define EXTI_IMR2_IM38_Pos (6U)
6778#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
6779#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
6780#define EXTI_IMR2_IM40_Pos (8U)
6781#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
6782#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
6783#define EXTI_IMR2_IM41_Pos (9U)
6784#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
6785#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
6786#define EXTI_IMR2_IM42_Pos (10U)
6787#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
6788#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
6789#define EXTI_IMR2_IM_Pos (0U)
6790#define EXTI_IMR2_IM_Msk (0x77FUL << EXTI_IMR2_IM_Pos) /*!< 0x0000077F */
6791#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask All */
6792
6793/******************* Bit definition for EXTI_EMR1 register *****************/
6794#define EXTI_EMR1_EM0_Pos (0U)
6795#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
6796#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
6797#define EXTI_EMR1_EM1_Pos (1U)
6798#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
6799#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
6800#define EXTI_EMR1_EM2_Pos (2U)
6801#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
6802#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
6803#define EXTI_EMR1_EM3_Pos (3U)
6804#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
6805#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
6806#define EXTI_EMR1_EM4_Pos (4U)
6807#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
6808#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
6809#define EXTI_EMR1_EM5_Pos (5U)
6810#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
6811#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
6812#define EXTI_EMR1_EM6_Pos (6U)
6813#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
6814#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
6815#define EXTI_EMR1_EM7_Pos (7U)
6816#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
6817#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
6818#define EXTI_EMR1_EM8_Pos (8U)
6819#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
6820#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
6821#define EXTI_EMR1_EM9_Pos (9U)
6822#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
6823#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
6824#define EXTI_EMR1_EM10_Pos (10U)
6825#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
6826#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
6827#define EXTI_EMR1_EM11_Pos (11U)
6828#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
6829#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
6830#define EXTI_EMR1_EM12_Pos (12U)
6831#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
6832#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
6833#define EXTI_EMR1_EM13_Pos (13U)
6834#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
6835#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
6836#define EXTI_EMR1_EM14_Pos (14U)
6837#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
6838#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
6839#define EXTI_EMR1_EM15_Pos (15U)
6840#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
6841#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
6842#define EXTI_EMR1_EM16_Pos (16U)
6843#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
6844#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
6845#define EXTI_EMR1_EM17_Pos (17U)
6846#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
6847#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
6848#define EXTI_EMR1_EM18_Pos (18U)
6849#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
6850#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
6851#define EXTI_EMR1_EM19_Pos (19U)
6852#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
6853#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
6854#define EXTI_EMR1_EM20_Pos (20U)
6855#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
6856#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
6857#define EXTI_EMR1_EM21_Pos (21U)
6858#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
6859#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
6860#define EXTI_EMR1_EM22_Pos (22U)
6861#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
6862#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
6863#define EXTI_EMR1_EM23_Pos (23U)
6864#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
6865#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
6866#define EXTI_EMR1_EM24_Pos (24U)
6867#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
6868#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
6869#define EXTI_EMR1_EM25_Pos (25U)
6870#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
6871#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
6872#define EXTI_EMR1_EM26_Pos (26U)
6873#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
6874#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
6875#define EXTI_EMR1_EM27_Pos (27U)
6876#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
6877#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
6878#define EXTI_EMR1_EM28_Pos (28U)
6879#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
6880#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
6881#define EXTI_EMR1_EM29_Pos (29U)
6882#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
6883#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
6884#define EXTI_EMR1_EM30_Pos (30U)
6885#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
6886#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
6887#define EXTI_EMR1_EM31_Pos (31U)
6888#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
6889#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
6890#define EXTI_EMR1_EM_Pos (0U)
6891#define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos) /*!< 0xFFFFFFFF */
6892#define EXTI_EMR1_EM EXTI_EMR1_EM_Msk /*!< Event Mask All */
6893
6894/******************* Bit definition for EXTI_EMR2 register *****************/
6895#define EXTI_EMR2_EM32_Pos (0U)
6896#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
6897#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
6898#define EXTI_EMR2_EM33_Pos (1U)
6899#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
6900#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
6901#define EXTI_EMR2_EM34_Pos (2U)
6902#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
6903#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
6904#define EXTI_EMR2_EM35_Pos (3U)
6905#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
6906#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
6907#define EXTI_EMR2_EM36_Pos (4U)
6908#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
6909#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
6910#define EXTI_EMR2_EM37_Pos (5U)
6911#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
6912#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
6913#define EXTI_EMR2_EM38_Pos (6U)
6914#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
6915#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
6916#define EXTI_EMR2_EM40_Pos (8U)
6917#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
6918#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
6919#define EXTI_EMR2_EM41_Pos (9U)
6920#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
6921#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41 */
6922#define EXTI_EMR2_EM42_Pos (10U)
6923#define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
6924#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
6925#define EXTI_EMR2_EM_Pos (0U)
6926#define EXTI_EMR2_EM_Msk (0x77FUL << EXTI_EMR2_EM_Pos) /*!< 0x0000077F */
6927#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Event Mask All */
6928
6929/******************************************************************************/
6930/* */
6931/* Flexible Datarate Controller Area Network */
6932/* */
6933/******************************************************************************/
6934/*!<FDCAN control and status registers */
6935/***************** Bit definition for FDCAN_CREL register *******************/
6936#define FDCAN_CREL_DAY_Pos (0U)
6937#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
6938#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
6939#define FDCAN_CREL_MON_Pos (8U)
6940#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
6941#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
6942#define FDCAN_CREL_YEAR_Pos (16U)
6943#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
6944#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
6945#define FDCAN_CREL_SUBSTEP_Pos (20U)
6946#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
6947#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
6948#define FDCAN_CREL_STEP_Pos (24U)
6949#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
6950#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
6951#define FDCAN_CREL_REL_Pos (28U)
6952#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
6953#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
6954
6955/***************** Bit definition for FDCAN_ENDN register *******************/
6956#define FDCAN_ENDN_ETV_Pos (0U)
6957#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
6958#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
6959
6960/***************** Bit definition for FDCAN_DBTP register *******************/
6961#define FDCAN_DBTP_DSJW_Pos (0U)
6962#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
6963#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
6964#define FDCAN_DBTP_DTSEG2_Pos (4U)
6965#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
6966#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
6967#define FDCAN_DBTP_DTSEG1_Pos (8U)
6968#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
6969#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
6970#define FDCAN_DBTP_DBRP_Pos (16U)
6971#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
6972#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
6973#define FDCAN_DBTP_TDC_Pos (23U)
6974#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
6975#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
6976
6977/***************** Bit definition for FDCAN_TEST register *******************/
6978#define FDCAN_TEST_LBCK_Pos (4U)
6979#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
6980#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
6981#define FDCAN_TEST_TX_Pos (5U)
6982#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
6983#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
6984#define FDCAN_TEST_RX_Pos (7U)
6985#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
6986#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
6987
6988/***************** Bit definition for FDCAN_RWD register ********************/
6989#define FDCAN_RWD_WDC_Pos (0U)
6990#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
6991#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
6992#define FDCAN_RWD_WDV_Pos (8U)
6993#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
6994#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
6995
6996/***************** Bit definition for FDCAN_CCCR register ********************/
6997#define FDCAN_CCCR_INIT_Pos (0U)
6998#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
6999#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
7000#define FDCAN_CCCR_CCE_Pos (1U)
7001#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
7002#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
7003#define FDCAN_CCCR_ASM_Pos (2U)
7004#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
7005#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
7006#define FDCAN_CCCR_CSA_Pos (3U)
7007#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
7008#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
7009#define FDCAN_CCCR_CSR_Pos (4U)
7010#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
7011#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
7012#define FDCAN_CCCR_MON_Pos (5U)
7013#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
7014#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
7015#define FDCAN_CCCR_DAR_Pos (6U)
7016#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
7017#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
7018#define FDCAN_CCCR_TEST_Pos (7U)
7019#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
7020#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
7021#define FDCAN_CCCR_FDOE_Pos (8U)
7022#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
7023#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
7024#define FDCAN_CCCR_BRSE_Pos (9U)
7025#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
7026#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
7027#define FDCAN_CCCR_PXHD_Pos (12U)
7028#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
7029#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
7030#define FDCAN_CCCR_EFBI_Pos (13U)
7031#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
7032#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
7033#define FDCAN_CCCR_TXP_Pos (14U)
7034#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
7035#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
7036#define FDCAN_CCCR_NISO_Pos (15U)
7037#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
7038#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
7039
7040/***************** Bit definition for FDCAN_NBTP register ********************/
7041#define FDCAN_NBTP_NTSEG2_Pos (0U)
7042#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
7043#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
7044#define FDCAN_NBTP_NTSEG1_Pos (8U)
7045#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
7046#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
7047#define FDCAN_NBTP_NBRP_Pos (16U)
7048#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
7049#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
7050#define FDCAN_NBTP_NSJW_Pos (25U)
7051#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
7052#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
7053
7054/***************** Bit definition for FDCAN_TSCC register ********************/
7055#define FDCAN_TSCC_TSS_Pos (0U)
7056#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
7057#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
7058#define FDCAN_TSCC_TCP_Pos (16U)
7059#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
7060#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
7061
7062/***************** Bit definition for FDCAN_TSCV register ********************/
7063#define FDCAN_TSCV_TSC_Pos (0U)
7064#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
7065#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
7066
7067/***************** Bit definition for FDCAN_TOCC register ********************/
7068#define FDCAN_TOCC_ETOC_Pos (0U)
7069#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
7070#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
7071#define FDCAN_TOCC_TOS_Pos (1U)
7072#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
7073#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
7074#define FDCAN_TOCC_TOP_Pos (16U)
7075#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
7076#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
7077
7078/***************** Bit definition for FDCAN_TOCV register ********************/
7079#define FDCAN_TOCV_TOC_Pos (0U)
7080#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
7081#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
7082
7083/***************** Bit definition for FDCAN_ECR register *********************/
7084#define FDCAN_ECR_TEC_Pos (0U)
7085#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */
7086#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
7087#define FDCAN_ECR_REC_Pos (8U)
7088#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
7089#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
7090#define FDCAN_ECR_RP_Pos (15U)
7091#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
7092#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
7093#define FDCAN_ECR_CEL_Pos (16U)
7094#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
7095#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
7096
7097/***************** Bit definition for FDCAN_PSR register *********************/
7098#define FDCAN_PSR_LEC_Pos (0U)
7099#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
7100#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
7101#define FDCAN_PSR_ACT_Pos (3U)
7102#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
7103#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
7104#define FDCAN_PSR_EP_Pos (5U)
7105#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
7106#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
7107#define FDCAN_PSR_EW_Pos (6U)
7108#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
7109#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
7110#define FDCAN_PSR_BO_Pos (7U)
7111#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
7112#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
7113#define FDCAN_PSR_DLEC_Pos (8U)
7114#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
7115#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
7116#define FDCAN_PSR_RESI_Pos (11U)
7117#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
7118#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
7119#define FDCAN_PSR_RBRS_Pos (12U)
7120#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
7121#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
7122#define FDCAN_PSR_REDL_Pos (13U)
7123#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
7124#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
7125#define FDCAN_PSR_PXE_Pos (14U)
7126#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
7127#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
7128#define FDCAN_PSR_TDCV_Pos (16U)
7129#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
7130#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
7131
7132/***************** Bit definition for FDCAN_TDCR register ********************/
7133#define FDCAN_TDCR_TDCF_Pos (0U)
7134#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
7135#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
7136#define FDCAN_TDCR_TDCO_Pos (8U)
7137#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
7138#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
7139
7140/***************** Bit definition for FDCAN_IR register **********************/
7141#define FDCAN_IR_RF0N_Pos (0U)
7142#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
7143#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
7144#define FDCAN_IR_RF0F_Pos (1U)
7145#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000002 */
7146#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
7147#define FDCAN_IR_RF0L_Pos (2U)
7148#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000004 */
7149#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
7150#define FDCAN_IR_RF1N_Pos (3U)
7151#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000008 */
7152#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
7153#define FDCAN_IR_RF1F_Pos (4U)
7154#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000010 */
7155#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
7156#define FDCAN_IR_RF1L_Pos (5U)
7157#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000020 */
7158#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
7159#define FDCAN_IR_HPM_Pos (6U)
7160#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000040 */
7161#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
7162#define FDCAN_IR_TC_Pos (7U)
7163#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000080 */
7164#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
7165#define FDCAN_IR_TCF_Pos (8U)
7166#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000100 */
7167#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
7168#define FDCAN_IR_TFE_Pos (9U)
7169#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000200 */
7170#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
7171#define FDCAN_IR_TEFN_Pos (10U)
7172#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00000400 */
7173#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
7174#define FDCAN_IR_TEFF_Pos (11U)
7175#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00000800 */
7176#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
7177#define FDCAN_IR_TEFL_Pos (12U)
7178#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00001000 */
7179#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
7180#define FDCAN_IR_TSW_Pos (13U)
7181#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00002000 */
7182#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
7183#define FDCAN_IR_MRAF_Pos (14U)
7184#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00004000 */
7185#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
7186#define FDCAN_IR_TOO_Pos (15U)
7187#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00008000 */
7188#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
7189#define FDCAN_IR_ELO_Pos (16U)
7190#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00010000 */
7191#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
7192#define FDCAN_IR_EP_Pos (17U)
7193#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00020000 */
7194#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
7195#define FDCAN_IR_EW_Pos (18U)
7196#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x00040000 */
7197#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
7198#define FDCAN_IR_BO_Pos (19U)
7199#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x00080000 */
7200#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
7201#define FDCAN_IR_WDI_Pos (20U)
7202#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x00100000 */
7203#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
7204#define FDCAN_IR_PEA_Pos (21U)
7205#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x00200000 */
7206#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
7207#define FDCAN_IR_PED_Pos (22U)
7208#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x00400000 */
7209#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
7210#define FDCAN_IR_ARA_Pos (23U)
7211#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x00800000 */
7212#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
7213
7214/***************** Bit definition for FDCAN_IE register **********************/
7215#define FDCAN_IE_RF0NE_Pos (0U)
7216#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
7217#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
7218#define FDCAN_IE_RF0FE_Pos (1U)
7219#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000002 */
7220#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
7221#define FDCAN_IE_RF0LE_Pos (2U)
7222#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000004 */
7223#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
7224#define FDCAN_IE_RF1NE_Pos (3U)
7225#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000008 */
7226#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
7227#define FDCAN_IE_RF1FE_Pos (4U)
7228#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000010 */
7229#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
7230#define FDCAN_IE_RF1LE_Pos (5U)
7231#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000020 */
7232#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
7233#define FDCAN_IE_HPME_Pos (6U)
7234#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000040 */
7235#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
7236#define FDCAN_IE_TCE_Pos (7U)
7237#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000080 */
7238#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
7239#define FDCAN_IE_TCFE_Pos (8U)
7240#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000100 */
7241#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable*/
7242#define FDCAN_IE_TFEE_Pos (9U)
7243#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000200 */
7244#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
7245#define FDCAN_IE_TEFNE_Pos (10U)
7246#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00000400 */
7247#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
7248#define FDCAN_IE_TEFFE_Pos (11U)
7249#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00000800 */
7250#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
7251#define FDCAN_IE_TEFLE_Pos (12U)
7252#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00001000 */
7253#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
7254#define FDCAN_IE_TSWE_Pos (13U)
7255#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00002000 */
7256#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
7257#define FDCAN_IE_MRAFE_Pos (14U)
7258#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00004000 */
7259#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
7260#define FDCAN_IE_TOOE_Pos (15U)
7261#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00008000 */
7262#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
7263#define FDCAN_IE_ELOE_Pos (16U)
7264#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00010000 */
7265#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
7266#define FDCAN_IE_EPE_Pos (17U)
7267#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00020000 */
7268#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
7269#define FDCAN_IE_EWE_Pos (18U)
7270#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x00040000 */
7271#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
7272#define FDCAN_IE_BOE_Pos (19U)
7273#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x00080000 */
7274#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
7275#define FDCAN_IE_WDIE_Pos (20U)
7276#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x00100000 */
7277#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
7278#define FDCAN_IE_PEAE_Pos (21U)
7279#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x00200000 */
7280#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable*/
7281#define FDCAN_IE_PEDE_Pos (22U)
7282#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x00400000 */
7283#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
7284#define FDCAN_IE_ARAE_Pos (23U)
7285#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x00800000 */
7286#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
7287
7288/***************** Bit definition for FDCAN_ILS register **********************/
7289#define FDCAN_ILS_RXFIFO0_Pos (0U)
7290#define FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos) /*!< 0x00000001 */
7291#define FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk /*!<Rx FIFO 0 Message Lost
7292 Rx FIFO 0 is Full
7293 Rx FIFO 0 Has New Message */
7294#define FDCAN_ILS_RXFIFO1_Pos (1U)
7295#define FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos) /*!< 0x00000002 */
7296#define FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk /*!<Rx FIFO 1 Message Lost
7297 Rx FIFO 1 is Full
7298 Rx FIFO 1 Has New Message */
7299#define FDCAN_ILS_SMSG_Pos (2U)
7300#define FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos) /*!< 0x00000004 */
7301#define FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk /*!<Transmission Cancellation Finished
7302 Transmission Completed
7303 High Priority Message */
7304#define FDCAN_ILS_TFERR_Pos (3U)
7305#define FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos) /*!< 0x00000008 */
7306#define FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk /*!<Tx Event FIFO Element Lost
7307 Tx Event FIFO Full
7308 Tx Event FIFO New Entry
7309 Tx FIFO Empty Interrupt Line */
7310#define FDCAN_ILS_MISC_Pos (4U)
7311#define FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos) /*!< 0x00000010 */
7312#define FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk /*!<Timeout Occurred
7313 Message RAM Access Failure
7314 Timestamp Wraparound */
7315#define FDCAN_ILS_BERR_Pos (5U)
7316#define FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos) /*!< 0x00000020 */
7317#define FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk /*!<Error Passive
7318 Error Logging Overflow */
7319#define FDCAN_ILS_PERR_Pos (6U)
7320#define FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos) /*!< 0x00000040 */
7321#define FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk /*!<Access to Reserved Address Line
7322 Protocol Error in Data Phase Line
7323 Protocol Error in Arbitration Phase Line
7324 Watchdog Interrupt Line
7325 Bus_Off Status
7326 Warning Status */
7327
7328/***************** Bit definition for FDCAN_ILE register **********************/
7329#define FDCAN_ILE_EINT0_Pos (0U)
7330#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
7331#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
7332#define FDCAN_ILE_EINT1_Pos (1U)
7333#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
7334#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
7335
7336/***************** Bit definition for FDCAN_RXGFC register ********************/
7337#define FDCAN_RXGFC_RRFE_Pos (0U)
7338#define FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos) /*!< 0x00000001 */
7339#define FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk /*!<Reject Remote Frames Extended */
7340#define FDCAN_RXGFC_RRFS_Pos (1U)
7341#define FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos) /*!< 0x00000002 */
7342#define FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk /*!<Reject Remote Frames Standard */
7343#define FDCAN_RXGFC_ANFE_Pos (2U)
7344#define FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos) /*!< 0x0000000C */
7345#define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
7346#define FDCAN_RXGFC_ANFS_Pos (4U)
7347#define FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos) /*!< 0x00000030 */
7348#define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
7349#define FDCAN_RXGFC_F1OM_Pos (8U)
7350#define FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos) /*!< 0x00000100 */
7351#define FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk /*!<FIFO 1 operation mode */
7352#define FDCAN_RXGFC_F0OM_Pos (9U)
7353#define FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos) /*!< 0x00000200 */
7354#define FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk /*!<FIFO 0 operation mode */
7355#define FDCAN_RXGFC_LSS_Pos (16U)
7356#define FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos) /*!< 0x001F0000 */
7357#define FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk /*!<List Size Standard */
7358#define FDCAN_RXGFC_LSE_Pos (24U)
7359#define FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos) /*!< 0x0F000000 */
7360#define FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk /*!<List Size Extended */
7361
7362/***************** Bit definition for FDCAN_XIDAM register ********************/
7363#define FDCAN_XIDAM_EIDM_Pos (0U)
7364#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
7365#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
7366
7367/***************** Bit definition for FDCAN_HPMS register *********************/
7368#define FDCAN_HPMS_BIDX_Pos (0U)
7369#define FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos) /*!< 0x00000007 */
7370#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
7371#define FDCAN_HPMS_MSI_Pos (6U)
7372#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
7373#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
7374#define FDCAN_HPMS_FIDX_Pos (8U)
7375#define FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00001F00 */
7376#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
7377#define FDCAN_HPMS_FLST_Pos (15U)
7378#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
7379#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
7380
7381/***************** Bit definition for FDCAN_RXF0S register ********************/
7382#define FDCAN_RXF0S_F0FL_Pos (0U)
7383#define FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000000F */
7384#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
7385#define FDCAN_RXF0S_F0GI_Pos (8U)
7386#define FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00000300 */
7387#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
7388#define FDCAN_RXF0S_F0PI_Pos (16U)
7389#define FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x00030000 */
7390#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
7391#define FDCAN_RXF0S_F0F_Pos (24U)
7392#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
7393#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
7394#define FDCAN_RXF0S_RF0L_Pos (25U)
7395#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
7396#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
7397
7398/***************** Bit definition for FDCAN_RXF0A register ********************/
7399#define FDCAN_RXF0A_F0AI_Pos (0U)
7400#define FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x00000007 */
7401#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
7402
7403/***************** Bit definition for FDCAN_RXF1S register ********************/
7404#define FDCAN_RXF1S_F1FL_Pos (0U)
7405#define FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000000F */
7406#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
7407#define FDCAN_RXF1S_F1GI_Pos (8U)
7408#define FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00000300 */
7409#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
7410#define FDCAN_RXF1S_F1PI_Pos (16U)
7411#define FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x00030000 */
7412#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
7413#define FDCAN_RXF1S_F1F_Pos (24U)
7414#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
7415#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
7416#define FDCAN_RXF1S_RF1L_Pos (25U)
7417#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
7418#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
7419
7420/***************** Bit definition for FDCAN_RXF1A register ********************/
7421#define FDCAN_RXF1A_F1AI_Pos (0U)
7422#define FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x00000007 */
7423#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
7424
7425/***************** Bit definition for FDCAN_TXBC register *********************/
7426#define FDCAN_TXBC_TFQM_Pos (24U)
7427#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x01000000 */
7428#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
7429
7430/***************** Bit definition for FDCAN_TXFQS register *********************/
7431#define FDCAN_TXFQS_TFFL_Pos (0U)
7432#define FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x00000007 */
7433#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
7434#define FDCAN_TXFQS_TFGI_Pos (8U)
7435#define FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00000300 */
7436#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
7437#define FDCAN_TXFQS_TFQPI_Pos (16U)
7438#define FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x00030000 */
7439#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
7440#define FDCAN_TXFQS_TFQF_Pos (21U)
7441#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
7442#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
7443
7444/***************** Bit definition for FDCAN_TXBRP register *********************/
7445#define FDCAN_TXBRP_TRP_Pos (0U)
7446#define FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos) /*!< 0x00000007 */
7447#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
7448
7449/***************** Bit definition for FDCAN_TXBAR register *********************/
7450#define FDCAN_TXBAR_AR_Pos (0U)
7451#define FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos) /*!< 0x00000007 */
7452#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
7453
7454/***************** Bit definition for FDCAN_TXBCR register *********************/
7455#define FDCAN_TXBCR_CR_Pos (0U)
7456#define FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos) /*!< 0x00000007 */
7457#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
7458
7459/***************** Bit definition for FDCAN_TXBTO register *********************/
7460#define FDCAN_TXBTO_TO_Pos (0U)
7461#define FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos) /*!< 0x00000007 */
7462#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
7463
7464/***************** Bit definition for FDCAN_TXBCF register *********************/
7465#define FDCAN_TXBCF_CF_Pos (0U)
7466#define FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos) /*!< 0x00000007 */
7467#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
7468
7469/***************** Bit definition for FDCAN_TXBTIE register ********************/
7470#define FDCAN_TXBTIE_TIE_Pos (0U)
7471#define FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos) /*!< 0x00000007 */
7472#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
7473
7474/***************** Bit definition for FDCAN_ TXBCIE register *******************/
7475#define FDCAN_TXBCIE_CFIE_Pos (0U)
7476#define FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0x00000007 */
7477#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
7478
7479/***************** Bit definition for FDCAN_TXEFS register *********************/
7480#define FDCAN_TXEFS_EFFL_Pos (0U)
7481#define FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x00000007 */
7482#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
7483#define FDCAN_TXEFS_EFGI_Pos (8U)
7484#define FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00000300 */
7485#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
7486#define FDCAN_TXEFS_EFPI_Pos (16U)
7487#define FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x00030000 */
7488#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
7489#define FDCAN_TXEFS_EFF_Pos (24U)
7490#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
7491#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
7492#define FDCAN_TXEFS_TEFL_Pos (25U)
7493#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
7494#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
7495
7496/***************** Bit definition for FDCAN_TXEFA register *********************/
7497#define FDCAN_TXEFA_EFAI_Pos (0U)
7498#define FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x00000003 */
7499#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
7500
7501
7502/*!<FDCAN config registers */
7503/***************** Bit definition for FDCAN_CKDIV register *********************/
7504#define FDCAN_CKDIV_PDIV_Pos (0U)
7505#define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos) /*!< 0x0000000F */
7506#define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk /*!<Input Clock Divider */
7507
7508/***************** Bit definition for FDCAN_OPTR register *********************/
7509#define FDCAN_OPTR_OPTR_Pos (0U)
7510#define FDCAN_OPTR_OPTR_Msk (0xFFFFFFFFUL << FDCAN_OPTR_OPTR_Pos) /*!< 0xFFFFFFFF */
7511#define FDCAN_OPTR_OPTR FDCAN_OPTR_OPTR_Msk /*!<Option Register */
7512
7513
7514/******************************************************************************/
7515/* */
7516/* FLASH */
7517/* */
7518/******************************************************************************/
7519/******************* Bits definition for FLASH_ACR register *****************/
7520#define FLASH_ACR_LATENCY_Pos (0U)
7521#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
7522#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
7523#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
7524#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
7525#define FLASH_ACR_LATENCY_2WS (0x00000002UL)
7526#define FLASH_ACR_LATENCY_3WS (0x00000003UL)
7527#define FLASH_ACR_LATENCY_4WS (0x00000004UL)
7528#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
7529#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
7530#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
7531#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
7532#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
7533#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
7534#define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
7535#define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
7536#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
7537#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
7538#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
7539#define FLASH_ACR_RUN_PD_Pos (13U)
7540#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
7541#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
7542#define FLASH_ACR_SLEEP_PD_Pos (14U)
7543#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
7544#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
7545#define FLASH_ACR_LVEN_Pos (15U)
7546#define FLASH_ACR_LVEN_Msk (0x1UL << FLASH_ACR_LVEN_Pos) /*!< 0x00008000 */
7547#define FLASH_ACR_LVEN FLASH_ACR_LVEN_Msk /*!< LVE A/B Flash pin low */
7548
7549/****************** Bits definition for FLASH_NSSR register *****************/
7550#define FLASH_NSSR_NSEOP_Pos (0U)
7551#define FLASH_NSSR_NSEOP_Msk (0x1UL << FLASH_NSSR_NSEOP_Pos) /*!< 0x00000001 */
7552#define FLASH_NSSR_NSEOP FLASH_NSSR_NSEOP_Msk
7553#define FLASH_NSSR_NSOPERR_Pos (1U)
7554#define FLASH_NSSR_NSOPERR_Msk (0x1UL << FLASH_NSSR_NSOPERR_Pos) /*!< 0x00000002 */
7555#define FLASH_NSSR_NSOPERR FLASH_NSSR_NSOPERR_Msk
7556#define FLASH_NSSR_NSPROGERR_Pos (3U)
7557#define FLASH_NSSR_NSPROGERR_Msk (0x1UL << FLASH_NSSR_NSPROGERR_Pos) /*!< 0x00000008 */
7558#define FLASH_NSSR_NSPROGERR FLASH_NSSR_NSPROGERR_Msk
7559#define FLASH_NSSR_NSWRPERR_Pos (4U)
7560#define FLASH_NSSR_NSWRPERR_Msk (0x1UL << FLASH_NSSR_NSWRPERR_Pos) /*!< 0x00000010 */
7561#define FLASH_NSSR_NSWRPERR FLASH_NSSR_NSWRPERR_Msk
7562#define FLASH_NSSR_NSPGAERR_Pos (5U)
7563#define FLASH_NSSR_NSPGAERR_Msk (0x1UL << FLASH_NSSR_NSPGAERR_Pos) /*!< 0x00000020 */
7564#define FLASH_NSSR_NSPGAERR FLASH_NSSR_NSPGAERR_Msk
7565#define FLASH_NSSR_NSSIZERR_Pos (6U)
7566#define FLASH_NSSR_NSSIZERR_Msk (0x1UL << FLASH_NSSR_NSSIZERR_Pos) /*!< 0x00000040 */
7567#define FLASH_NSSR_NSSIZERR FLASH_NSSR_NSSIZERR_Msk
7568#define FLASH_NSSR_NSPGSERR_Pos (7U)
7569#define FLASH_NSSR_NSPGSERR_Msk (0x1UL << FLASH_NSSR_NSPGSERR_Pos) /*!< 0x00000080 */
7570#define FLASH_NSSR_NSPGSERR FLASH_NSSR_NSPGSERR_Msk
7571#define FLASH_NSSR_OPTWERR_Pos (13U)
7572#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */
7573#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk
7574#define FLASH_NSSR_NSBSY_Pos (16U)
7575#define FLASH_NSSR_NSBSY_Msk (0x1UL << FLASH_NSSR_NSBSY_Pos) /*!< 0x00010000 */
7576#define FLASH_NSSR_NSBSY FLASH_NSSR_NSBSY_Msk
7577
7578/****************** Bits definition for FLASH_SECSR register ****************/
7579#define FLASH_SECSR_SECEOP_Pos (0U)
7580#define FLASH_SECSR_SECEOP_Msk (0x1UL << FLASH_SECSR_SECEOP_Pos) /*!< 0x00000001 */
7581#define FLASH_SECSR_SECEOP FLASH_SECSR_SECEOP_Msk
7582#define FLASH_SECSR_SECOPERR_Pos (1U)
7583#define FLASH_SECSR_SECOPERR_Msk (0x1UL << FLASH_SECSR_SECOPERR_Pos) /*!< 0x00000002 */
7584#define FLASH_SECSR_SECOPERR FLASH_SECSR_SECOPERR_Msk
7585#define FLASH_SECSR_SECPROGERR_Pos (3U)
7586#define FLASH_SECSR_SECPROGERR_Msk (0x1UL << FLASH_SECSR_SECPROGERR_Pos)/*!< 0x00000008 */
7587#define FLASH_SECSR_SECPROGERR FLASH_SECSR_SECPROGERR_Msk
7588#define FLASH_SECSR_SECWRPERR_Pos (4U)
7589#define FLASH_SECSR_SECWRPERR_Msk (0x1UL << FLASH_SECSR_SECWRPERR_Pos) /*!< 0x00000010 */
7590#define FLASH_SECSR_SECWRPERR FLASH_SECSR_SECWRPERR_Msk
7591#define FLASH_SECSR_SECPGAERR_Pos (5U)
7592#define FLASH_SECSR_SECPGAERR_Msk (0x1UL << FLASH_SECSR_SECPGAERR_Pos) /*!< 0x00000020 */
7593#define FLASH_SECSR_SECPGAERR FLASH_SECSR_SECPGAERR_Msk
7594#define FLASH_SECSR_SECSIZERR_Pos (6U)
7595#define FLASH_SECSR_SECSIZERR_Msk (0x1UL << FLASH_SECSR_SECSIZERR_Pos) /*!< 0x00000040 */
7596#define FLASH_SECSR_SECSIZERR FLASH_SECSR_SECSIZERR_Msk
7597#define FLASH_SECSR_SECPGSERR_Pos (7U)
7598#define FLASH_SECSR_SECPGSERR_Msk (0x1UL << FLASH_SECSR_SECPGSERR_Pos) /*!< 0x00000080 */
7599#define FLASH_SECSR_SECPGSERR FLASH_SECSR_SECPGSERR_Msk
7600#define FLASH_SECSR_SECBSY_Pos (16U)
7601#define FLASH_SECSR_SECBSY_Msk (0x1UL << FLASH_SECSR_SECBSY_Pos) /*!< 0x00010000 */
7602#define FLASH_SECSR_SECBSY FLASH_SECSR_SECBSY_Msk
7603
7604/****************** Bits definition for FLASH_NSCR register *****************/
7605#define FLASH_NSCR_NSPG_Pos (0U)
7606#define FLASH_NSCR_NSPG_Msk (0x1UL << FLASH_NSCR_NSPG_Pos) /*!< 0x00000001 */
7607#define FLASH_NSCR_NSPG FLASH_NSCR_NSPG_Msk
7608#define FLASH_NSCR_NSPER_Pos (1U)
7609#define FLASH_NSCR_NSPER_Msk (0x1UL << FLASH_NSCR_NSPER_Pos) /*!< 0x00000002 */
7610#define FLASH_NSCR_NSPER FLASH_NSCR_NSPER_Msk
7611#define FLASH_NSCR_NSMER1_Pos (2U)
7612#define FLASH_NSCR_NSMER1_Msk (0x1UL << FLASH_NSCR_NSMER1_Pos) /*!< 0x00000004 */
7613#define FLASH_NSCR_NSMER1 FLASH_NSCR_NSMER1_Msk
7614#define FLASH_NSCR_NSPNB_Pos (3U)
7615#define FLASH_NSCR_NSPNB_Msk (0x7FUL << FLASH_NSCR_NSPNB_Pos) /*!< 0x000003F8 */
7616#define FLASH_NSCR_NSPNB FLASH_NSCR_NSPNB_Msk
7617#define FLASH_NSCR_NSBKER_Pos (11U)
7618#define FLASH_NSCR_NSBKER_Msk (0x1UL << FLASH_NSCR_NSBKER_Pos) /*!< 0x00000800 */
7619#define FLASH_NSCR_NSBKER FLASH_NSCR_NSBKER_Msk
7620#define FLASH_NSCR_NSMER2_Pos (15U)
7621#define FLASH_NSCR_NSMER2_Msk (0x1UL << FLASH_NSCR_NSMER2_Pos) /*!< 0x00008000 */
7622#define FLASH_NSCR_NSMER2 FLASH_NSCR_NSMER2_Msk
7623#define FLASH_NSCR_NSSTRT_Pos (16U)
7624#define FLASH_NSCR_NSSTRT_Msk (0x1UL << FLASH_NSCR_NSSTRT_Pos) /*!< 0x00010000 */
7625#define FLASH_NSCR_NSSTRT FLASH_NSCR_NSSTRT_Msk
7626#define FLASH_NSCR_OPTSTRT_Pos (17U)
7627#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */
7628#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk
7629#define FLASH_NSCR_NSEOPIE_Pos (24U)
7630#define FLASH_NSCR_NSEOPIE_Msk (0x1UL << FLASH_NSCR_NSEOPIE_Pos) /*!< 0x01000000 */
7631#define FLASH_NSCR_NSEOPIE FLASH_NSCR_NSEOPIE_Msk
7632#define FLASH_NSCR_NSERRIE_Pos (25U)
7633#define FLASH_NSCR_NSERRIE_Msk (0x1UL << FLASH_NSCR_NSERRIE_Pos) /*!< 0x02000000 */
7634#define FLASH_NSCR_NSERRIE FLASH_NSCR_NSERRIE_Msk
7635#define FLASH_NSCR_OBL_LAUNCH_Pos (27U)
7636#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
7637#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk
7638#define FLASH_NSCR_OPTLOCK_Pos (30U)
7639#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */
7640#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk
7641#define FLASH_NSCR_NSLOCK_Pos (31U)
7642#define FLASH_NSCR_NSLOCK_Msk (0x1UL << FLASH_NSCR_NSLOCK_Pos) /*!< 0x80000000 */
7643#define FLASH_NSCR_NSLOCK FLASH_NSCR_NSLOCK_Msk
7644
7645/****************** Bits definition for FLASH_SECCR register ****************/
7646#define FLASH_SECCR_SECPG_Pos (0U)
7647#define FLASH_SECCR_SECPG_Msk (0x1UL << FLASH_SECCR_SECPG_Pos) /*!< 0x00000001 */
7648#define FLASH_SECCR_SECPG FLASH_SECCR_SECPG_Msk
7649#define FLASH_SECCR_SECPER_Pos (1U)
7650#define FLASH_SECCR_SECPER_Msk (0x1UL << FLASH_SECCR_SECPER_Pos) /*!< 0x00000002 */
7651#define FLASH_SECCR_SECPER FLASH_SECCR_SECPER_Msk
7652#define FLASH_SECCR_SECMER1_Pos (2U)
7653#define FLASH_SECCR_SECMER1_Msk (0x1UL << FLASH_SECCR_SECMER1_Pos) /*!< 0x00000004 */
7654#define FLASH_SECCR_SECMER1 FLASH_SECCR_SECMER1_Msk
7655#define FLASH_SECCR_SECPNB_Pos (3U)
7656#define FLASH_SECCR_SECPNB_Msk (0x7FUL << FLASH_SECCR_SECPNB_Pos) /*!< 0x000003F8 */
7657#define FLASH_SECCR_SECPNB FLASH_SECCR_SECPNB_Msk
7658#define FLASH_SECCR_SECBKER_Pos (11U)
7659#define FLASH_SECCR_SECBKER_Msk (0x1UL << FLASH_SECCR_SECBKER_Pos) /*!< 0x00000800 */
7660#define FLASH_SECCR_SECBKER FLASH_SECCR_SECBKER_Msk
7661#define FLASH_SECCR_SECMER2_Pos (15U)
7662#define FLASH_SECCR_SECMER2_Msk (0x1UL << FLASH_SECCR_SECMER2_Pos) /*!< 0x00008000 */
7663#define FLASH_SECCR_SECMER2 FLASH_SECCR_SECMER2_Msk
7664#define FLASH_SECCR_SECSTRT_Pos (16U)
7665#define FLASH_SECCR_SECSTRT_Msk (0x1UL << FLASH_SECCR_SECSTRT_Pos) /*!< 0x00010000 */
7666#define FLASH_SECCR_SECSTRT FLASH_SECCR_SECSTRT_Msk
7667#define FLASH_SECCR_SECEOPIE_Pos (24U)
7668#define FLASH_SECCR_SECEOPIE_Msk (0x1UL << FLASH_SECCR_SECEOPIE_Pos) /*!< 0x01000000 */
7669#define FLASH_SECCR_SECEOPIE FLASH_SECCR_SECEOPIE_Msk
7670#define FLASH_SECCR_SECERRIE_Pos (25U)
7671#define FLASH_SECCR_SECERRIE_Msk (0x1UL << FLASH_SECCR_SECERRIE_Pos) /*!< 0x02000000 */
7672#define FLASH_SECCR_SECERRIE FLASH_SECCR_SECERRIE_Msk
7673#define FLASH_SECCR_SECINV_Pos (29U)
7674#define FLASH_SECCR_SECINV_Msk (0x1UL << FLASH_SECCR_SECINV_Pos) /*!< 0x20000000 */
7675#define FLASH_SECCR_SECINV FLASH_SECCR_SECINV_Msk
7676#define FLASH_SECCR_SECLOCK_Pos (31U)
7677#define FLASH_SECCR_SECLOCK_Msk (0x1UL << FLASH_SECCR_SECLOCK_Pos) /*!< 0x80000000 */
7678#define FLASH_SECCR_SECLOCK FLASH_SECCR_SECLOCK_Msk
7679
7680/******************* Bits definition for FLASH_ECCR register ***************/
7681#define FLASH_ECCR_ADDR_ECC_Pos (0U)
7682#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0007FFFF */
7683#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
7684#define FLASH_ECCR_BK_ECC_Pos (21U)
7685#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */
7686#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
7687#define FLASH_ECCR_SYSF_ECC_Pos (22U)
7688#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
7689#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
7690#define FLASH_ECCR_ECCIE_Pos (24U)
7691#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
7692#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
7693#define FLASH_ECCR_ECCC2_Pos (28U)
7694#define FLASH_ECCR_ECCC2_Msk (0x1UL << FLASH_ECCR_ECCC2_Pos) /*!< 0x10000000 */
7695#define FLASH_ECCR_ECCC2 FLASH_ECCR_ECCC2_Msk
7696#define FLASH_ECCR_ECCD2_Pos (29U)
7697#define FLASH_ECCR_ECCD2_Msk (0x1UL << FLASH_ECCR_ECCD2_Pos) /*!< 0x20000000 */
7698#define FLASH_ECCR_ECCD2 FLASH_ECCR_ECCD2_Msk
7699#define FLASH_ECCR_ECCC_Pos (30U)
7700#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
7701#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
7702#define FLASH_ECCR_ECCD_Pos (31U)
7703#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
7704#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
7705
7706/******************* Bits definition for FLASH_OPTR register ***************/
7707#define FLASH_OPTR_RDP_Pos (0U)
7708#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
7709#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
7710#define FLASH_OPTR_BOR_LEV_Pos (8U)
7711#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
7712#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
7713#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
7714#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
7715#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
7716#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
7717#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
7718#define FLASH_OPTR_nRST_STOP_Pos (12U)
7719#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
7720#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
7721#define FLASH_OPTR_nRST_STDBY_Pos (13U)
7722#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
7723#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
7724#define FLASH_OPTR_nRST_SHDW_Pos (14U)
7725#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
7726#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
7727#define FLASH_OPTR_IWDG_SW_Pos (16U)
7728#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
7729#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
7730#define FLASH_OPTR_IWDG_STOP_Pos (17U)
7731#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
7732#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
7733#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
7734#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
7735#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
7736#define FLASH_OPTR_WWDG_SW_Pos (19U)
7737#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
7738#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
7739#define FLASH_OPTR_SWAP_BANK_Pos (20U)
7740#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */
7741#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk
7742#define FLASH_OPTR_DB256K_Pos (21U)
7743#define FLASH_OPTR_DB256K_Msk (0x1UL << FLASH_OPTR_DB256K_Pos) /*!< 0x00200000 */
7744#define FLASH_OPTR_DB256K FLASH_OPTR_DB256K_Msk
7745#define FLASH_OPTR_DBANK_Pos (22U)
7746#define FLASH_OPTR_DBANK_Msk (0x1UL << FLASH_OPTR_DBANK_Pos) /*!< 0x00400000 */
7747#define FLASH_OPTR_DBANK FLASH_OPTR_DBANK_Msk
7748#define FLASH_OPTR_SRAM2_PE_Pos (24U)
7749#define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
7750#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
7751#define FLASH_OPTR_SRAM2_RST_Pos (25U)
7752#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
7753#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
7754#define FLASH_OPTR_nSWBOOT0_Pos (26U)
7755#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
7756#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
7757#define FLASH_OPTR_nBOOT0_Pos (27U)
7758#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
7759#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
7760#define FLASH_OPTR_PA15_PUPEN_Pos (28U)
7761#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */
7762#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk
7763#define FLASH_OPTR_TZEN_Pos (31U)
7764#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */
7765#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk
7766
7767/**************** Bits definition for FLASH_NSBOOTADD0R register ************/
7768#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U)
7769#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos)/*!< 0xFFFFFF80 */
7770#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk
7771
7772/**************** Bits definition for FLASH_NSBOOTADD1R register ************/
7773#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U)
7774#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos)/*!< 0xFFFFFF80 */
7775#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk
7776
7777/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/
7778#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U)
7779#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */
7780#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk
7781#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U)
7782#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos)/*!< 0xFFFFFF80 */
7783#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk
7784
7785/***************** Bits definition for FLASH_SECWM1R1 register **************/
7786#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0U)
7787#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos)/*!< 0x0000007F */
7788#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk
7789#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16U)
7790#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x007F0000 */
7791#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk
7792
7793/***************** Bits definition for FLASH_SECWM1R2 register **************/
7794#define FLASH_SECWM1R2_HDP1_PEND_Pos (16U)
7795#define FLASH_SECWM1R2_HDP1_PEND_Msk (0x7FUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x007F0000 */
7796#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk
7797#define FLASH_SECWM1R2_HDP1EN_Pos (31U)
7798#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */
7799#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk
7800
7801/****************** Bits definition for FLASH_WRP1AR register ***************/
7802#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0U)
7803#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos)/*!< 0x0000007F */
7804#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk
7805#define FLASH_WRP1AR_WRP1A_PEND_Pos (16U)
7806#define FLASH_WRP1AR_WRP1A_PEND_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x007F0000 */
7807#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk
7808
7809/****************** Bits definition for FLASH_WRP1BR register ***************/
7810#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0U)
7811#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos)/*!< 0x0000007F */
7812#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk
7813#define FLASH_WRP1BR_WRP1B_PEND_Pos (16U)
7814#define FLASH_WRP1BR_WRP1B_PEND_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x007F0000 */
7815#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk
7816
7817/***************** Bits definition for FLASH_SECWM2R1 register **************/
7818#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0U)
7819#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos)/*!< 0x0000007F */
7820#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk
7821#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16U)
7822#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PEND_Pos)/*!< 0x007F0000 */
7823#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk
7824
7825/***************** Bits definition for FLASH_SECWM2R2 register **************/
7826#define FLASH_SECWM2R2_HDP2_PEND_Pos (16U)
7827#define FLASH_SECWM2R2_HDP2_PEND_Msk (0x7FUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x007F0000 */
7828#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk
7829#define FLASH_SECWM2R2_HDP2EN_Pos (31U)
7830#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */
7831#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk
7832
7833/****************** Bits definition for FLASH_WRP2AR register ***************/
7834#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0U)
7835#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos)/*!< 0x0000007F */
7836#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk
7837#define FLASH_WRP2AR_WRP2A_PEND_Pos (16U)
7838#define FLASH_WRP2AR_WRP2A_PEND_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x007F0000 */
7839#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk
7840
7841/****************** Bits definition for FLASH_WRPB2R register ***************/
7842#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0U)
7843#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos)/*!< 0x0000007F */
7844#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk
7845#define FLASH_WRP2BR_WRP2B_PEND_Pos (16U)
7846#define FLASH_WRP2BR_WRP2B_PEND_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x007F0000 */
7847#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk
7848
7849/****************** Bits definition for FLASH_SECHDPCR register ***********/
7850#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0U)
7851#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos)/*!< 0x00000001 */
7852#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk
7853#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1U)
7854#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos)/*!< 0x00000002 */
7855#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk
7856
7857/****************** Bits definition for FLASH_PRIVCFGR register ***********/
7858#define FLASH_PRIVCFGR_PRIV_Pos (0U)
7859#define FLASH_PRIVCFGR_PRIV_Msk (0x1UL << FLASH_PRIVCFGR_PRIV_Pos)/*!< 0x00000001 */
7860#define FLASH_PRIVCFGR_PRIV FLASH_PRIVCFGR_PRIV_Msk
7861
7862/******************************************************************************/
7863/* */
7864/* Flexible Memory Controller */
7865/* */
7866/******************************************************************************/
7867/****************** Bit definition for FMC_BCR1 register *******************/
7868#define FMC_BCR1_CCLKEN_Pos (20U)
7869#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
7870#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
7871#define FMC_BCR1_WFDIS_Pos (21U)
7872#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
7873#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
7874
7875/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
7876#define FMC_BCRx_MBKEN_Pos (0U)
7877#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
7878#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
7879#define FMC_BCRx_MUXEN_Pos (1U)
7880#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
7881#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7882
7883#define FMC_BCRx_MTYP_Pos (2U)
7884#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
7885#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7886#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
7887#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
7888
7889#define FMC_BCRx_MWID_Pos (4U)
7890#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
7891#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7892#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
7893#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
7894
7895#define FMC_BCRx_FACCEN_Pos (6U)
7896#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
7897#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
7898#define FMC_BCRx_BURSTEN_Pos (8U)
7899#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
7900#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
7901#define FMC_BCRx_WAITPOL_Pos (9U)
7902#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
7903#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
7904#define FMC_BCRx_WAITCFG_Pos (11U)
7905#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
7906#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
7907#define FMC_BCRx_WREN_Pos (12U)
7908#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
7909#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
7910#define FMC_BCRx_WAITEN_Pos (13U)
7911#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
7912#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
7913#define FMC_BCRx_EXTMOD_Pos (14U)
7914#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
7915#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
7916#define FMC_BCRx_ASYNCWAIT_Pos (15U)
7917#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
7918#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
7919
7920#define FMC_BCRx_CPSIZE_Pos (16U)
7921#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
7922#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<CRAM page size */
7923#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
7924#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
7925#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
7926
7927#define FMC_BCRx_CBURSTRW_Pos (19U)
7928#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
7929#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
7930
7931#define FMC_BCRx_NBLSET_Pos (22U)
7932#define FMC_BCRx_NBLSET_Msk (0x3UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00C00000 */
7933#define FMC_BCRx_NBLSET FMC_BCRx_NBLSET_Msk /*!<Byte lane (NBL) setup */
7934#define FMC_BCRx_NBLSET_0 (0x1UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00400000 */
7935#define FMC_BCRx_NBLSET_1 (0x2UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00800000 */
7936
7937/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
7938#define FMC_BTRx_ADDSET_Pos (0U)
7939#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
7940#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7941#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
7942#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
7943#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
7944#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
7945
7946#define FMC_BTRx_ADDHLD_Pos (4U)
7947#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
7948#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7949#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
7950#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
7951#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
7952#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
7953
7954#define FMC_BTRx_DATAST_Pos (8U)
7955#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
7956#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7957#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
7958#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
7959#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
7960#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
7961#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
7962#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
7963#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
7964#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
7965
7966#define FMC_BTRx_BUSTURN_Pos (16U)
7967#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
7968#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7969#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
7970#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
7971#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
7972#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
7973
7974#define FMC_BTRx_CLKDIV_Pos (20U)
7975#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
7976#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7977#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
7978#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
7979#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
7980#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
7981
7982#define FMC_BTRx_DATLAT_Pos (24U)
7983#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
7984#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLAT[3:0] bits (Data latency) */
7985#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
7986#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
7987#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
7988#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
7989
7990#define FMC_BTRx_ACCMOD_Pos (28U)
7991#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
7992#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7993#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
7994#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
7995
7996#define FMC_BTRx_DATAHLD_Pos (30U)
7997#define FMC_BTRx_DATAHLD_Msk (0x3UL << FMC_BTRx_DATAHLD_Pos) /*!< 0xC0000000 */
7998#define FMC_BTRx_DATAHLD FMC_BTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
7999#define FMC_BTRx_DATAHLD_0 (0x1UL << FMC_BTRx_DATAHLD_Pos) /*!< 0x40000000 */
8000#define FMC_BTRx_DATAHLD_1 (0x2UL << FMC_BTRx_DATAHLD_Pos) /*!< 0x80000000 */
8001
8002/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
8003#define FMC_BWTRx_ADDSET_Pos (0U)
8004#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
8005#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8006#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
8007#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
8008#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
8009#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
8010
8011#define FMC_BWTRx_ADDHLD_Pos (4U)
8012#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
8013#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8014#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
8015#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
8016#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
8017#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
8018
8019#define FMC_BWTRx_DATAST_Pos (8U)
8020#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
8021#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8022#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
8023#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
8024#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
8025#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
8026#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
8027#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
8028#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
8029#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
8030
8031#define FMC_BWTRx_BUSTURN_Pos (16U)
8032#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
8033#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8034#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
8035#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
8036#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
8037#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
8038
8039#define FMC_BWTRx_ACCMOD_Pos (28U)
8040#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
8041#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8042#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
8043#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
8044
8045#define FMC_BWTRx_DATAHLD_Pos (30U)
8046#define FMC_BWTRx_DATAHLD_Msk (0x3UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0xC0000000 */
8047#define FMC_BWTRx_DATAHLD FMC_BWTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
8048#define FMC_BWTRx_DATAHLD_0 (0x1UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0x40000000 */
8049#define FMC_BWTRx_DATAHLD_1 (0x2UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0x80000000 */
8050
8051/****************** Bit definition for FMC_PCSCNTR register ******************/
8052#define FMC_PCSCNTR_CSCOUNT_Pos (0U)
8053#define FMC_PCSCNTR_CSCOUNT_Msk (0xFFFFUL << FMC_PCSCNTR_CSCOUNT_Pos) /*!< 0x0000FFFF */
8054#define FMC_PCSCNTR_CSCOUNT FMC_PCSCNTR_CSCOUNT_Msk /*!<CSCOUNT[15:0] bits (Chip select counter) */
8055
8056#define FMC_PCSCNTR_CNTB1EN_Pos (16U)
8057#define FMC_PCSCNTR_CNTB1EN_Msk (0x1UL << FMC_PCSCNTR_CNTB1EN_Pos) /*!< 0x00010000 */
8058#define FMC_PCSCNTR_CNTB1EN FMC_PCSCNTR_CNTB1EN_Msk /*!<Counter PSRAM/NOR Bank1_1 enable */
8059
8060#define FMC_PCSCNTR_CNTB2EN_Pos (17U)
8061#define FMC_PCSCNTR_CNTB2EN_Msk (0x1UL << FMC_PCSCNTR_CNTB2EN_Pos) /*!< 0x00020000 */
8062#define FMC_PCSCNTR_CNTB2EN FMC_PCSCNTR_CNTB2EN_Msk /*!<Counter PSRAM/NOR Bank1_2 enable */
8063
8064#define FMC_PCSCNTR_CNTB3EN_Pos (18U)
8065#define FMC_PCSCNTR_CNTB3EN_Msk (0x1UL << FMC_PCSCNTR_CNTB3EN_Pos) /*!< 0x00040000 */
8066#define FMC_PCSCNTR_CNTB3EN FMC_PCSCNTR_CNTB3EN_Msk /*!<Counter PSRAM/NOR Bank1_3 enable */
8067
8068#define FMC_PCSCNTR_CNTB4EN_Pos (19U)
8069#define FMC_PCSCNTR_CNTB4EN_Msk (0x1UL << FMC_PCSCNTR_CNTB4EN_Pos) /*!< 0x00080000 */
8070#define FMC_PCSCNTR_CNTB4EN FMC_PCSCNTR_CNTB4EN_Msk /*!<Counter PSRAM/NOR Bank1_4 enable */
8071
8072/****************** Bit definition for FMC_PCR register ********************/
8073#define FMC_PCR_PWAITEN_Pos (1U)
8074#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
8075#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
8076#define FMC_PCR_PBKEN_Pos (2U)
8077#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
8078#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
8079#define FMC_PCR_PTYP_Pos (3U)
8080#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
8081#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
8082
8083#define FMC_PCR_PWID_Pos (4U)
8084#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
8085#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
8086#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
8087#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
8088
8089#define FMC_PCR_ECCEN_Pos (6U)
8090#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
8091#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
8092
8093#define FMC_PCR_TCLR_Pos (9U)
8094#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
8095#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
8096#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
8097#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
8098#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
8099#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
8100
8101#define FMC_PCR_TAR_Pos (13U)
8102#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
8103#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
8104#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
8105#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
8106#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
8107#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
8108
8109#define FMC_PCR_ECCPS_Pos (17U)
8110#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
8111#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
8112#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
8113#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
8114#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
8115
8116/******************* Bit definition for FMC_SR register ********************/
8117#define FMC_SR_IRS_Pos (0U)
8118#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
8119#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
8120#define FMC_SR_ILS_Pos (1U)
8121#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
8122#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
8123#define FMC_SR_IFS_Pos (2U)
8124#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
8125#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
8126#define FMC_SR_IREN_Pos (3U)
8127#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
8128#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
8129#define FMC_SR_ILEN_Pos (4U)
8130#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
8131#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
8132#define FMC_SR_IFEN_Pos (5U)
8133#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
8134#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
8135#define FMC_SR_FEMPT_Pos (6U)
8136#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
8137#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
8138
8139/****************** Bit definition for FMC_PMEM register ******************/
8140#define FMC_PMEM_MEMSET_Pos (0U)
8141#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
8142#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
8143#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
8144#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
8145#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
8146#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
8147#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
8148#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
8149#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
8150#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
8151
8152#define FMC_PMEM_MEMWAIT_Pos (8U)
8153#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
8154#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
8155#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
8156#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
8157#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
8158#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
8159#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
8160#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
8161#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
8162#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
8163
8164#define FMC_PMEM_MEMHOLD_Pos (16U)
8165#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
8166#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
8167#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
8168#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
8169#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
8170#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
8171#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
8172#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
8173#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
8174#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
8175
8176#define FMC_PMEM_MEMHIZ_Pos (24U)
8177#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
8178#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
8179#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
8180#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
8181#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
8182#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
8183#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
8184#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
8185#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
8186#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
8187
8188/****************** Bit definition for FMC_PATT register *******************/
8189#define FMC_PATT_ATTSET_Pos (0U)
8190#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
8191#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
8192#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
8193#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
8194#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
8195#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
8196#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
8197#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
8198#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
8199#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
8200
8201#define FMC_PATT_ATTWAIT_Pos (8U)
8202#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
8203#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
8204#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
8205#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
8206#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
8207#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
8208#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
8209#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
8210#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
8211#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
8212
8213#define FMC_PATT_ATTHOLD_Pos (16U)
8214#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
8215#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
8216#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
8217#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
8218#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
8219#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
8220#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
8221#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
8222#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
8223#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
8224
8225#define FMC_PATT_ATTHIZ_Pos (24U)
8226#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
8227#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
8228#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
8229#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
8230#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
8231#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
8232#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
8233#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
8234#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
8235#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
8236
8237/****************** Bit definition for FMC_ECCR register *******************/
8238#define FMC_ECCR_ECC_Pos (0U)
8239#define FMC_ECCR_ECC_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos) /*!< 0xFFFFFFFF */
8240#define FMC_ECCR_ECC FMC_ECCR_ECC_Msk /*!<ECC result */
8241
8242/******************************************************************************/
8243/* */
8244/* General Purpose IOs (GPIO) */
8245/* */
8246/******************************************************************************/
8247/****************** Bits definition for GPIO_MODER register *****************/
8248#define GPIO_MODER_MODE0_Pos (0U)
8249#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
8250#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
8251#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
8252#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
8253#define GPIO_MODER_MODE1_Pos (2U)
8254#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
8255#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
8256#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
8257#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
8258#define GPIO_MODER_MODE2_Pos (4U)
8259#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
8260#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
8261#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
8262#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
8263#define GPIO_MODER_MODE3_Pos (6U)
8264#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
8265#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
8266#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
8267#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
8268#define GPIO_MODER_MODE4_Pos (8U)
8269#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
8270#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
8271#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
8272#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
8273#define GPIO_MODER_MODE5_Pos (10U)
8274#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
8275#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
8276#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
8277#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
8278#define GPIO_MODER_MODE6_Pos (12U)
8279#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
8280#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
8281#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
8282#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
8283#define GPIO_MODER_MODE7_Pos (14U)
8284#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
8285#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
8286#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
8287#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
8288#define GPIO_MODER_MODE8_Pos (16U)
8289#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
8290#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
8291#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
8292#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
8293#define GPIO_MODER_MODE9_Pos (18U)
8294#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
8295#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
8296#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
8297#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
8298#define GPIO_MODER_MODE10_Pos (20U)
8299#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
8300#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
8301#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
8302#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
8303#define GPIO_MODER_MODE11_Pos (22U)
8304#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
8305#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
8306#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
8307#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
8308#define GPIO_MODER_MODE12_Pos (24U)
8309#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
8310#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
8311#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
8312#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
8313#define GPIO_MODER_MODE13_Pos (26U)
8314#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
8315#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
8316#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
8317#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
8318#define GPIO_MODER_MODE14_Pos (28U)
8319#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
8320#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
8321#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
8322#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
8323#define GPIO_MODER_MODE15_Pos (30U)
8324#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
8325#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
8326#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
8327#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
8328
8329/****************** Bits definition for GPIO_OTYPER register ****************/
8330#define GPIO_OTYPER_OT0_Pos (0U)
8331#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
8332#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8333#define GPIO_OTYPER_OT1_Pos (1U)
8334#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
8335#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8336#define GPIO_OTYPER_OT2_Pos (2U)
8337#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
8338#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8339#define GPIO_OTYPER_OT3_Pos (3U)
8340#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
8341#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8342#define GPIO_OTYPER_OT4_Pos (4U)
8343#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
8344#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8345#define GPIO_OTYPER_OT5_Pos (5U)
8346#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
8347#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8348#define GPIO_OTYPER_OT6_Pos (6U)
8349#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
8350#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8351#define GPIO_OTYPER_OT7_Pos (7U)
8352#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
8353#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8354#define GPIO_OTYPER_OT8_Pos (8U)
8355#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
8356#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8357#define GPIO_OTYPER_OT9_Pos (9U)
8358#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
8359#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8360#define GPIO_OTYPER_OT10_Pos (10U)
8361#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
8362#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8363#define GPIO_OTYPER_OT11_Pos (11U)
8364#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
8365#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8366#define GPIO_OTYPER_OT12_Pos (12U)
8367#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
8368#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8369#define GPIO_OTYPER_OT13_Pos (13U)
8370#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
8371#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8372#define GPIO_OTYPER_OT14_Pos (14U)
8373#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
8374#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8375#define GPIO_OTYPER_OT15_Pos (15U)
8376#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
8377#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8378
8379/****************** Bits definition for GPIO_OSPEEDR register ***************/
8380#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
8381#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
8382#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
8383#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
8384#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
8385#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
8386#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
8387#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
8388#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
8389#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
8390#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
8391#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
8392#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
8393#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
8394#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
8395#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
8396#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
8397#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
8398#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
8399#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
8400#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
8401#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
8402#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
8403#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
8404#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
8405#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
8406#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
8407#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
8408#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
8409#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
8410#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
8411#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
8412#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
8413#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
8414#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
8415#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
8416#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
8417#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
8418#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
8419#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
8420#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
8421#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
8422#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
8423#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
8424#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
8425#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
8426#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
8427#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
8428#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
8429#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
8430#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
8431#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
8432#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
8433#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
8434#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
8435#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
8436#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
8437#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
8438#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
8439#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
8440#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
8441#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
8442#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
8443#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
8444#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
8445#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
8446#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
8447#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
8448#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
8449#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
8450#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
8451#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
8452#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
8453#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
8454#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
8455#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
8456#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
8457#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
8458#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
8459#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
8460
8461/****************** Bits definition for GPIO_PUPDR register *****************/
8462#define GPIO_PUPDR_PUPD0_Pos (0U)
8463#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
8464#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
8465#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
8466#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
8467#define GPIO_PUPDR_PUPD1_Pos (2U)
8468#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
8469#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
8470#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
8471#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
8472#define GPIO_PUPDR_PUPD2_Pos (4U)
8473#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
8474#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
8475#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
8476#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
8477#define GPIO_PUPDR_PUPD3_Pos (6U)
8478#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
8479#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
8480#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
8481#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
8482#define GPIO_PUPDR_PUPD4_Pos (8U)
8483#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
8484#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
8485#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
8486#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
8487#define GPIO_PUPDR_PUPD5_Pos (10U)
8488#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
8489#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
8490#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
8491#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
8492#define GPIO_PUPDR_PUPD6_Pos (12U)
8493#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
8494#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
8495#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
8496#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
8497#define GPIO_PUPDR_PUPD7_Pos (14U)
8498#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
8499#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
8500#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
8501#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
8502#define GPIO_PUPDR_PUPD8_Pos (16U)
8503#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
8504#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
8505#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
8506#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
8507#define GPIO_PUPDR_PUPD9_Pos (18U)
8508#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
8509#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
8510#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
8511#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
8512#define GPIO_PUPDR_PUPD10_Pos (20U)
8513#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
8514#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
8515#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
8516#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
8517#define GPIO_PUPDR_PUPD11_Pos (22U)
8518#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
8519#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
8520#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
8521#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
8522#define GPIO_PUPDR_PUPD12_Pos (24U)
8523#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
8524#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
8525#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
8526#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
8527#define GPIO_PUPDR_PUPD13_Pos (26U)
8528#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
8529#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
8530#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
8531#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
8532#define GPIO_PUPDR_PUPD14_Pos (28U)
8533#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
8534#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
8535#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
8536#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
8537#define GPIO_PUPDR_PUPD15_Pos (30U)
8538#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
8539#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
8540#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
8541#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
8542
8543/****************** Bits definition for GPIO_IDR register *******************/
8544#define GPIO_IDR_ID0_Pos (0U)
8545#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
8546#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8547#define GPIO_IDR_ID1_Pos (1U)
8548#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
8549#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8550#define GPIO_IDR_ID2_Pos (2U)
8551#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
8552#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8553#define GPIO_IDR_ID3_Pos (3U)
8554#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
8555#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8556#define GPIO_IDR_ID4_Pos (4U)
8557#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
8558#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8559#define GPIO_IDR_ID5_Pos (5U)
8560#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
8561#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8562#define GPIO_IDR_ID6_Pos (6U)
8563#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
8564#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8565#define GPIO_IDR_ID7_Pos (7U)
8566#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
8567#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8568#define GPIO_IDR_ID8_Pos (8U)
8569#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
8570#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8571#define GPIO_IDR_ID9_Pos (9U)
8572#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
8573#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8574#define GPIO_IDR_ID10_Pos (10U)
8575#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
8576#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8577#define GPIO_IDR_ID11_Pos (11U)
8578#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
8579#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8580#define GPIO_IDR_ID12_Pos (12U)
8581#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
8582#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8583#define GPIO_IDR_ID13_Pos (13U)
8584#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
8585#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8586#define GPIO_IDR_ID14_Pos (14U)
8587#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
8588#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8589#define GPIO_IDR_ID15_Pos (15U)
8590#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
8591#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8592
8593/****************** Bits definition for GPIO_ODR register *******************/
8594#define GPIO_ODR_OD0_Pos (0U)
8595#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
8596#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8597#define GPIO_ODR_OD1_Pos (1U)
8598#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
8599#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8600#define GPIO_ODR_OD2_Pos (2U)
8601#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
8602#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8603#define GPIO_ODR_OD3_Pos (3U)
8604#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
8605#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8606#define GPIO_ODR_OD4_Pos (4U)
8607#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
8608#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8609#define GPIO_ODR_OD5_Pos (5U)
8610#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
8611#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8612#define GPIO_ODR_OD6_Pos (6U)
8613#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
8614#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8615#define GPIO_ODR_OD7_Pos (7U)
8616#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
8617#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8618#define GPIO_ODR_OD8_Pos (8U)
8619#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
8620#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8621#define GPIO_ODR_OD9_Pos (9U)
8622#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
8623#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8624#define GPIO_ODR_OD10_Pos (10U)
8625#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
8626#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8627#define GPIO_ODR_OD11_Pos (11U)
8628#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
8629#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8630#define GPIO_ODR_OD12_Pos (12U)
8631#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
8632#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8633#define GPIO_ODR_OD13_Pos (13U)
8634#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
8635#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8636#define GPIO_ODR_OD14_Pos (14U)
8637#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
8638#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8639#define GPIO_ODR_OD15_Pos (15U)
8640#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
8641#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8642
8643/****************** Bits definition for GPIO_BSRR register ******************/
8644#define GPIO_BSRR_BS0_Pos (0U)
8645#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
8646#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8647#define GPIO_BSRR_BS1_Pos (1U)
8648#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
8649#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8650#define GPIO_BSRR_BS2_Pos (2U)
8651#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
8652#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8653#define GPIO_BSRR_BS3_Pos (3U)
8654#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
8655#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8656#define GPIO_BSRR_BS4_Pos (4U)
8657#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
8658#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8659#define GPIO_BSRR_BS5_Pos (5U)
8660#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
8661#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8662#define GPIO_BSRR_BS6_Pos (6U)
8663#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
8664#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8665#define GPIO_BSRR_BS7_Pos (7U)
8666#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
8667#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8668#define GPIO_BSRR_BS8_Pos (8U)
8669#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
8670#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8671#define GPIO_BSRR_BS9_Pos (9U)
8672#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
8673#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8674#define GPIO_BSRR_BS10_Pos (10U)
8675#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
8676#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8677#define GPIO_BSRR_BS11_Pos (11U)
8678#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
8679#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8680#define GPIO_BSRR_BS12_Pos (12U)
8681#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
8682#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8683#define GPIO_BSRR_BS13_Pos (13U)
8684#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
8685#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8686#define GPIO_BSRR_BS14_Pos (14U)
8687#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
8688#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8689#define GPIO_BSRR_BS15_Pos (15U)
8690#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
8691#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8692#define GPIO_BSRR_BR0_Pos (16U)
8693#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
8694#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8695#define GPIO_BSRR_BR1_Pos (17U)
8696#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
8697#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8698#define GPIO_BSRR_BR2_Pos (18U)
8699#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
8700#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8701#define GPIO_BSRR_BR3_Pos (19U)
8702#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
8703#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8704#define GPIO_BSRR_BR4_Pos (20U)
8705#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
8706#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8707#define GPIO_BSRR_BR5_Pos (21U)
8708#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
8709#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8710#define GPIO_BSRR_BR6_Pos (22U)
8711#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
8712#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8713#define GPIO_BSRR_BR7_Pos (23U)
8714#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
8715#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8716#define GPIO_BSRR_BR8_Pos (24U)
8717#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
8718#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8719#define GPIO_BSRR_BR9_Pos (25U)
8720#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
8721#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8722#define GPIO_BSRR_BR10_Pos (26U)
8723#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
8724#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8725#define GPIO_BSRR_BR11_Pos (27U)
8726#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
8727#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8728#define GPIO_BSRR_BR12_Pos (28U)
8729#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
8730#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8731#define GPIO_BSRR_BR13_Pos (29U)
8732#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
8733#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8734#define GPIO_BSRR_BR14_Pos (30U)
8735#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
8736#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8737#define GPIO_BSRR_BR15_Pos (31U)
8738#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
8739#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8740
8741/****************** Bit definition for GPIO_LCKR register *********************/
8742#define GPIO_LCKR_LCK0_Pos (0U)
8743#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
8744#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8745#define GPIO_LCKR_LCK1_Pos (1U)
8746#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
8747#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8748#define GPIO_LCKR_LCK2_Pos (2U)
8749#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
8750#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8751#define GPIO_LCKR_LCK3_Pos (3U)
8752#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
8753#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8754#define GPIO_LCKR_LCK4_Pos (4U)
8755#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
8756#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8757#define GPIO_LCKR_LCK5_Pos (5U)
8758#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
8759#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8760#define GPIO_LCKR_LCK6_Pos (6U)
8761#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
8762#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8763#define GPIO_LCKR_LCK7_Pos (7U)
8764#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
8765#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8766#define GPIO_LCKR_LCK8_Pos (8U)
8767#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
8768#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8769#define GPIO_LCKR_LCK9_Pos (9U)
8770#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
8771#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8772#define GPIO_LCKR_LCK10_Pos (10U)
8773#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
8774#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8775#define GPIO_LCKR_LCK11_Pos (11U)
8776#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
8777#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8778#define GPIO_LCKR_LCK12_Pos (12U)
8779#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
8780#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8781#define GPIO_LCKR_LCK13_Pos (13U)
8782#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
8783#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8784#define GPIO_LCKR_LCK14_Pos (14U)
8785#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
8786#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8787#define GPIO_LCKR_LCK15_Pos (15U)
8788#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
8789#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8790#define GPIO_LCKR_LCKK_Pos (16U)
8791#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
8792#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8793
8794/****************** Bit definition for GPIO_AFRL register *********************/
8795#define GPIO_AFRL_AFSEL0_Pos (0U)
8796#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
8797#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8798#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
8799#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
8800#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
8801#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
8802#define GPIO_AFRL_AFSEL1_Pos (4U)
8803#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
8804#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8805#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
8806#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
8807#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
8808#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
8809#define GPIO_AFRL_AFSEL2_Pos (8U)
8810#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
8811#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8812#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
8813#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
8814#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
8815#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
8816#define GPIO_AFRL_AFSEL3_Pos (12U)
8817#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
8818#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8819#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
8820#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
8821#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
8822#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
8823#define GPIO_AFRL_AFSEL4_Pos (16U)
8824#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
8825#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8826#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
8827#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
8828#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
8829#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
8830#define GPIO_AFRL_AFSEL5_Pos (20U)
8831#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
8832#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8833#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
8834#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
8835#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
8836#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
8837#define GPIO_AFRL_AFSEL6_Pos (24U)
8838#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
8839#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8840#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
8841#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
8842#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
8843#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
8844#define GPIO_AFRL_AFSEL7_Pos (28U)
8845#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
8846#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
8847#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
8848#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
8849#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
8850#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
8851
8852/****************** Bit definition for GPIO_AFRH register *********************/
8853#define GPIO_AFRH_AFSEL8_Pos (0U)
8854#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
8855#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
8856#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
8857#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
8858#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
8859#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
8860#define GPIO_AFRH_AFSEL9_Pos (4U)
8861#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
8862#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
8863#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
8864#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
8865#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
8866#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
8867#define GPIO_AFRH_AFSEL10_Pos (8U)
8868#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
8869#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
8870#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
8871#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
8872#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
8873#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
8874#define GPIO_AFRH_AFSEL11_Pos (12U)
8875#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
8876#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
8877#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
8878#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
8879#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
8880#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
8881#define GPIO_AFRH_AFSEL12_Pos (16U)
8882#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
8883#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
8884#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
8885#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
8886#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
8887#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
8888#define GPIO_AFRH_AFSEL13_Pos (20U)
8889#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
8890#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
8891#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
8892#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
8893#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
8894#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
8895#define GPIO_AFRH_AFSEL14_Pos (24U)
8896#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
8897#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
8898#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
8899#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
8900#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
8901#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
8902#define GPIO_AFRH_AFSEL15_Pos (28U)
8903#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
8904#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
8905#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
8906#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
8907#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
8908#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
8909
8910/****************** Bits definition for GPIO_BRR register ******************/
8911#define GPIO_BRR_BR0_Pos (0U)
8912#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
8913#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
8914#define GPIO_BRR_BR1_Pos (1U)
8915#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
8916#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
8917#define GPIO_BRR_BR2_Pos (2U)
8918#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
8919#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
8920#define GPIO_BRR_BR3_Pos (3U)
8921#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
8922#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
8923#define GPIO_BRR_BR4_Pos (4U)
8924#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
8925#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
8926#define GPIO_BRR_BR5_Pos (5U)
8927#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
8928#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
8929#define GPIO_BRR_BR6_Pos (6U)
8930#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
8931#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
8932#define GPIO_BRR_BR7_Pos (7U)
8933#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
8934#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
8935#define GPIO_BRR_BR8_Pos (8U)
8936#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
8937#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
8938#define GPIO_BRR_BR9_Pos (9U)
8939#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
8940#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
8941#define GPIO_BRR_BR10_Pos (10U)
8942#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
8943#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
8944#define GPIO_BRR_BR11_Pos (11U)
8945#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
8946#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
8947#define GPIO_BRR_BR12_Pos (12U)
8948#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
8949#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
8950#define GPIO_BRR_BR13_Pos (13U)
8951#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
8952#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
8953#define GPIO_BRR_BR14_Pos (14U)
8954#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
8955#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
8956#define GPIO_BRR_BR15_Pos (15U)
8957#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
8958#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
8959
8960/****************** Bits definition for GPIO_SECCFGR register ***************/
8961#define GPIO_SECCFGR_SEC0_Pos (0U)
8962#define GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */
8963#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk
8964#define GPIO_SECCFGR_SEC1_Pos (1U)
8965#define GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */
8966#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk
8967#define GPIO_SECCFGR_SEC2_Pos (2U)
8968#define GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */
8969#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk
8970#define GPIO_SECCFGR_SEC3_Pos (3U)
8971#define GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */
8972#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk
8973#define GPIO_SECCFGR_SEC4_Pos (4U)
8974#define GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */
8975#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk
8976#define GPIO_SECCFGR_SEC5_Pos (5U)
8977#define GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */
8978#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk
8979#define GPIO_SECCFGR_SEC6_Pos (6U)
8980#define GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */
8981#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk
8982#define GPIO_SECCFGR_SEC7_Pos (7U)
8983#define GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */
8984#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk
8985#define GPIO_SECCFGR_SEC8_Pos (8U)
8986#define GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) /*!< 0x00000100 */
8987#define GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk
8988#define GPIO_SECCFGR_SEC9_Pos (9U)
8989#define GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) /*!< 0x00000200 */
8990#define GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk
8991#define GPIO_SECCFGR_SEC10_Pos (10U)
8992#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */
8993#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk
8994#define GPIO_SECCFGR_SEC11_Pos (11U)
8995#define GPIO_SECCFGR_SEC11_Msk (0x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
8996#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk
8997#define GPIO_SECCFGR_SEC12_Pos (12U)
8998#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */
8999#define GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk
9000#define GPIO_SECCFGR_SEC13_Pos (13U)
9001#define GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) /*!< 0x00002000 */
9002#define GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk
9003#define GPIO_SECCFGR_SEC14_Pos (14U)
9004#define GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) /*!< 0x00004000 */
9005#define GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk
9006#define GPIO_SECCFGR_SEC15_Pos (15U)
9007#define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */
9008#define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk
9009
9010
9011/******************************************************************************/
9012/* */
9013/* HASH */
9014/* */
9015/******************************************************************************/
9016/****************** Bits definition for HASH_CR register ********************/
9017#define HASH_CR_INIT_Pos (2U)
9018#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */
9019#define HASH_CR_INIT HASH_CR_INIT_Msk
9020#define HASH_CR_DMAE_Pos (3U)
9021#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
9022#define HASH_CR_DMAE HASH_CR_DMAE_Msk
9023#define HASH_CR_DATATYPE_Pos (4U)
9024#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
9025#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
9026#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
9027#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
9028#define HASH_CR_MODE_Pos (6U)
9029#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */
9030#define HASH_CR_MODE HASH_CR_MODE_Msk
9031#define HASH_CR_ALGO_Pos (7U)
9032#define HASH_CR_ALGO_Msk (0x801UL << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
9033#define HASH_CR_ALGO HASH_CR_ALGO_Msk
9034#define HASH_CR_ALGO_0 (0x001UL << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
9035#define HASH_CR_ALGO_1 (0x800UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
9036#define HASH_CR_NBW_Pos (8U)
9037#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
9038#define HASH_CR_NBW HASH_CR_NBW_Msk
9039#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */
9040#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */
9041#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */
9042#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */
9043#define HASH_CR_DINNE_Pos (12U)
9044#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
9045#define HASH_CR_DINNE HASH_CR_DINNE_Msk
9046#define HASH_CR_MDMAT_Pos (13U)
9047#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
9048#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
9049#define HASH_CR_LKEY_Pos (16U)
9050#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
9051#define HASH_CR_LKEY HASH_CR_LKEY_Msk
9052
9053/****************** Bits definition for HASH_STR register *******************/
9054#define HASH_STR_NBLW_Pos (0U)
9055#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
9056#define HASH_STR_NBLW HASH_STR_NBLW_Msk
9057#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
9058#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
9059#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
9060#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
9061#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
9062#define HASH_STR_DCAL_Pos (8U)
9063#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
9064#define HASH_STR_DCAL HASH_STR_DCAL_Msk
9065
9066/****************** Bits definition for HASH_IMR register *******************/
9067#define HASH_IMR_DINIE_Pos (0U)
9068#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
9069#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
9070#define HASH_IMR_DCIE_Pos (1U)
9071#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
9072#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
9073
9074/****************** Bits definition for HASH_SR register ********************/
9075#define HASH_SR_DINIS_Pos (0U)
9076#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
9077#define HASH_SR_DINIS HASH_SR_DINIS_Msk
9078#define HASH_SR_DCIS_Pos (1U)
9079#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
9080#define HASH_SR_DCIS HASH_SR_DCIS_Msk
9081#define HASH_SR_DMAS_Pos (2U)
9082#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
9083#define HASH_SR_DMAS HASH_SR_DMAS_Msk
9084#define HASH_SR_BUSY_Pos (3U)
9085#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
9086#define HASH_SR_BUSY HASH_SR_BUSY_Msk
9087
9088
9089/******************************************************************************/
9090/* */
9091/* Inter-integrated Circuit Interface (I2C) */
9092/* */
9093/******************************************************************************/
9094/******************* Bit definition for I2C_CR1 register ********************/
9095#define I2C_CR1_PE_Pos (0U)
9096#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
9097#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
9098#define I2C_CR1_TXIE_Pos (1U)
9099#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
9100#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
9101#define I2C_CR1_RXIE_Pos (2U)
9102#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
9103#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
9104#define I2C_CR1_ADDRIE_Pos (3U)
9105#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
9106#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
9107#define I2C_CR1_NACKIE_Pos (4U)
9108#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
9109#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
9110#define I2C_CR1_STOPIE_Pos (5U)
9111#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
9112#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
9113#define I2C_CR1_TCIE_Pos (6U)
9114#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
9115#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
9116#define I2C_CR1_ERRIE_Pos (7U)
9117#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
9118#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
9119#define I2C_CR1_DNF_Pos (8U)
9120#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
9121#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
9122#define I2C_CR1_ANFOFF_Pos (12U)
9123#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
9124#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
9125#define I2C_CR1_SWRST_Pos (13U)
9126#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
9127#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
9128#define I2C_CR1_TXDMAEN_Pos (14U)
9129#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
9130#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
9131#define I2C_CR1_RXDMAEN_Pos (15U)
9132#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
9133#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
9134#define I2C_CR1_SBC_Pos (16U)
9135#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
9136#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
9137#define I2C_CR1_NOSTRETCH_Pos (17U)
9138#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
9139#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
9140#define I2C_CR1_WUPEN_Pos (18U)
9141#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
9142#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
9143#define I2C_CR1_GCEN_Pos (19U)
9144#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
9145#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
9146#define I2C_CR1_SMBHEN_Pos (20U)
9147#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
9148#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
9149#define I2C_CR1_SMBDEN_Pos (21U)
9150#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
9151#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
9152#define I2C_CR1_ALERTEN_Pos (22U)
9153#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
9154#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
9155#define I2C_CR1_PECEN_Pos (23U)
9156#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
9157#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
9158
9159/****************** Bit definition for I2C_CR2 register *********************/
9160#define I2C_CR2_SADD_Pos (0U)
9161#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
9162#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
9163#define I2C_CR2_RD_WRN_Pos (10U)
9164#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
9165#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
9166#define I2C_CR2_ADD10_Pos (11U)
9167#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
9168#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
9169#define I2C_CR2_HEAD10R_Pos (12U)
9170#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
9171#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
9172#define I2C_CR2_START_Pos (13U)
9173#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
9174#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
9175#define I2C_CR2_STOP_Pos (14U)
9176#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
9177#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
9178#define I2C_CR2_NACK_Pos (15U)
9179#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
9180#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
9181#define I2C_CR2_NBYTES_Pos (16U)
9182#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
9183#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
9184#define I2C_CR2_RELOAD_Pos (24U)
9185#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
9186#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
9187#define I2C_CR2_AUTOEND_Pos (25U)
9188#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
9189#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
9190#define I2C_CR2_PECBYTE_Pos (26U)
9191#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
9192#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
9193
9194/******************* Bit definition for I2C_OAR1 register *******************/
9195#define I2C_OAR1_OA1_Pos (0U)
9196#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
9197#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
9198#define I2C_OAR1_OA1MODE_Pos (10U)
9199#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
9200#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
9201#define I2C_OAR1_OA1EN_Pos (15U)
9202#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
9203#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
9204
9205/******************* Bit definition for I2C_OAR2 register *******************/
9206#define I2C_OAR2_OA2_Pos (1U)
9207#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
9208#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
9209#define I2C_OAR2_OA2MSK_Pos (8U)
9210#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
9211#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
9212#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */
9213#define I2C_OAR2_OA2MASK01_Pos (8U)
9214#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
9215#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
9216#define I2C_OAR2_OA2MASK02_Pos (9U)
9217#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
9218#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
9219#define I2C_OAR2_OA2MASK03_Pos (8U)
9220#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
9221#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
9222#define I2C_OAR2_OA2MASK04_Pos (10U)
9223#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
9224#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
9225#define I2C_OAR2_OA2MASK05_Pos (8U)
9226#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
9227#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
9228#define I2C_OAR2_OA2MASK06_Pos (9U)
9229#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
9230#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
9231#define I2C_OAR2_OA2MASK07_Pos (8U)
9232#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
9233#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
9234#define I2C_OAR2_OA2EN_Pos (15U)
9235#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
9236#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
9237
9238/******************* Bit definition for I2C_TIMINGR register *****************/
9239#define I2C_TIMINGR_SCLL_Pos (0U)
9240#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
9241#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
9242#define I2C_TIMINGR_SCLH_Pos (8U)
9243#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
9244#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
9245#define I2C_TIMINGR_SDADEL_Pos (16U)
9246#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
9247#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
9248#define I2C_TIMINGR_SCLDEL_Pos (20U)
9249#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
9250#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
9251#define I2C_TIMINGR_PRESC_Pos (28U)
9252#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
9253#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
9254
9255/******************* Bit definition for I2C_TIMEOUTR register *****************/
9256#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
9257#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
9258#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
9259#define I2C_TIMEOUTR_TIDLE_Pos (12U)
9260#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
9261#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
9262#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
9263#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
9264#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
9265#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
9266#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
9267#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
9268#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
9269#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
9270#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
9271
9272/****************** Bit definition for I2C_ISR register *********************/
9273#define I2C_ISR_TXE_Pos (0U)
9274#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
9275#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
9276#define I2C_ISR_TXIS_Pos (1U)
9277#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
9278#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
9279#define I2C_ISR_RXNE_Pos (2U)
9280#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
9281#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
9282#define I2C_ISR_ADDR_Pos (3U)
9283#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
9284#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
9285#define I2C_ISR_NACKF_Pos (4U)
9286#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
9287#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
9288#define I2C_ISR_STOPF_Pos (5U)
9289#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
9290#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
9291#define I2C_ISR_TC_Pos (6U)
9292#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
9293#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
9294#define I2C_ISR_TCR_Pos (7U)
9295#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
9296#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
9297#define I2C_ISR_BERR_Pos (8U)
9298#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
9299#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
9300#define I2C_ISR_ARLO_Pos (9U)
9301#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
9302#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
9303#define I2C_ISR_OVR_Pos (10U)
9304#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
9305#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
9306#define I2C_ISR_PECERR_Pos (11U)
9307#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
9308#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
9309#define I2C_ISR_TIMEOUT_Pos (12U)
9310#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
9311#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
9312#define I2C_ISR_ALERT_Pos (13U)
9313#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
9314#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
9315#define I2C_ISR_BUSY_Pos (15U)
9316#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
9317#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
9318#define I2C_ISR_DIR_Pos (16U)
9319#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
9320#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
9321#define I2C_ISR_ADDCODE_Pos (17U)
9322#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
9323#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
9324
9325/****************** Bit definition for I2C_ICR register *********************/
9326#define I2C_ICR_ADDRCF_Pos (3U)
9327#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
9328#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
9329#define I2C_ICR_NACKCF_Pos (4U)
9330#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
9331#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
9332#define I2C_ICR_STOPCF_Pos (5U)
9333#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
9334#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
9335#define I2C_ICR_BERRCF_Pos (8U)
9336#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
9337#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
9338#define I2C_ICR_ARLOCF_Pos (9U)
9339#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
9340#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
9341#define I2C_ICR_OVRCF_Pos (10U)
9342#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
9343#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
9344#define I2C_ICR_PECCF_Pos (11U)
9345#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
9346#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
9347#define I2C_ICR_TIMOUTCF_Pos (12U)
9348#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
9349#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
9350#define I2C_ICR_ALERTCF_Pos (13U)
9351#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
9352#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
9353
9354/****************** Bit definition for I2C_PECR register ********************/
9355#define I2C_PECR_PEC_Pos (0U)
9356#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
9357#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
9358
9359/****************** Bit definition for I2C_RXDR register ********************/
9360#define I2C_RXDR_RXDATA_Pos (0U)
9361#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
9362#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
9363
9364/****************** Bit definition for I2C_TXDR register ********************/
9365#define I2C_TXDR_TXDATA_Pos (0U)
9366#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
9367#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
9368
9369/******************************************************************************/
9370/* */
9371/* ICACHE */
9372/* */
9373/******************************************************************************/
9374/****************** Bit definition for ICACHE_CR register *******************/
9375#define ICACHE_CR_EN_Pos (0U)
9376#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */
9377#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */
9378#define ICACHE_CR_CACHEINV_Pos (1U)
9379#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */
9380#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */
9381#define ICACHE_CR_WAYSEL_Pos (2U)
9382#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */
9383#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */
9384#define ICACHE_CR_HITMEN_Pos (16U)
9385#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */
9386#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */
9387#define ICACHE_CR_MISSMEN_Pos (17U)
9388#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */
9389#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */
9390#define ICACHE_CR_HITMRST_Pos (18U)
9391#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */
9392#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */
9393#define ICACHE_CR_MISSMRST_Pos (19U)
9394#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */
9395#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */
9396
9397/****************** Bit definition for ICACHE_SR register *******************/
9398#define ICACHE_SR_BUSYF_Pos (0U)
9399#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */
9400#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */
9401#define ICACHE_SR_BSYENDF_Pos (1U)
9402#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */
9403#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */
9404#define ICACHE_SR_ERRF_Pos (2U)
9405#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */
9406#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */
9407
9408/****************** Bit definition for ICACHE_IER register ******************/
9409#define ICACHE_IER_BSYENDIE_Pos (1U)
9410#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */
9411#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */
9412#define ICACHE_IER_ERRIE_Pos (2U)
9413#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */
9414#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */
9415
9416/****************** Bit definition for ICACHE_FCR register ******************/
9417#define ICACHE_FCR_CBSYENDF_Pos (1U)
9418#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */
9419#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */
9420#define ICACHE_FCR_CERRF_Pos (2U)
9421#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */
9422#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag clear */
9423
9424/****************** Bit definition for ICACHE_HMONR register ****************/
9425#define ICACHE_HMONR_HITMON_Pos (0U)
9426#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos)/*!< 0xFFFFFFFF */
9427#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */
9428
9429/****************** Bit definition for ICACHE_MMONR register ****************/
9430#define ICACHE_MMONR_MISSMON_Pos (0U)
9431#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */
9432#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */
9433
9434/****************** Bit definition for ICACHE_CRRx register *****************/
9435#define ICACHE_CRRx_BASEADDR_Pos (0U)
9436#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */
9437#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< Base address of region X to remap */
9438#define ICACHE_CRRx_RSIZE_Pos (9U)
9439#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */
9440#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< Region X size */
9441#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */
9442#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */
9443#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */
9444#define ICACHE_CRRx_REN_Pos (15U)
9445#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */
9446#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< Region X enable */
9447#define ICACHE_CRRx_REMAPADDR_Pos (16U)
9448#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */
9449#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< Remap address of Region X to be remapped */
9450#define ICACHE_CRRx_MSTSEL_Pos (28U)
9451#define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */
9452#define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< Region X AHB cache master selection */
9453#define ICACHE_CRRx_HBURST_Pos (31U)
9454#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */
9455#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< Region X output burst type */
9456
9457/******************************************************************************/
9458/* */
9459/* Independent WATCHDOG (IWDG) */
9460/* */
9461/******************************************************************************/
9462/******************* Bit definition for IWDG_KR register ********************/
9463#define IWDG_KR_KEY_Pos (0U)
9464#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
9465#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
9466
9467/******************* Bit definition for IWDG_PR register ********************/
9468#define IWDG_PR_PR_Pos (0U)
9469#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
9470#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
9471#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
9472#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
9473#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
9474
9475/******************* Bit definition for IWDG_RLR register *******************/
9476#define IWDG_RLR_RL_Pos (0U)
9477#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
9478#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
9479
9480/******************* Bit definition for IWDG_SR register ********************/
9481#define IWDG_SR_PVU_Pos (0U)
9482#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
9483#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
9484#define IWDG_SR_RVU_Pos (1U)
9485#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
9486#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
9487#define IWDG_SR_WVU_Pos (2U)
9488#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
9489#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
9490
9491/******************* Bit definition for IWDG_KR register ********************/
9492#define IWDG_WINR_WIN_Pos (0U)
9493#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
9494#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
9495
9496/******************************************************************************/
9497/* */
9498/* Low Power Timer (LPTIM) */
9499/* */
9500/******************************************************************************/
9501/****************** Bit definition for LPTIM_ISR register *******************/
9502#define LPTIM_ISR_CMPM_Pos (0U)
9503#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
9504#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
9505#define LPTIM_ISR_ARRM_Pos (1U)
9506#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
9507#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
9508#define LPTIM_ISR_EXTTRIG_Pos (2U)
9509#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
9510#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
9511#define LPTIM_ISR_CMPOK_Pos (3U)
9512#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
9513#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
9514#define LPTIM_ISR_ARROK_Pos (4U)
9515#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
9516#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
9517#define LPTIM_ISR_UP_Pos (5U)
9518#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
9519#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
9520#define LPTIM_ISR_DOWN_Pos (6U)
9521#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
9522#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
9523#define LPTIM_ISR_UE_Pos (7U)
9524#define LPTIM_ISR_UE_Msk (0x1UL << LPTIM_ISR_UE_Pos) /*!< 0x00000080 */
9525#define LPTIM_ISR_UE LPTIM_ISR_UE_Msk /*!< Update event occurrence */
9526#define LPTIM_ISR_REPOK_Pos (8U)
9527#define LPTIM_ISR_REPOK_Msk (0x1UL << LPTIM_ISR_REPOK_Pos) /*!< 0x00000100 */
9528#define LPTIM_ISR_REPOK LPTIM_ISR_REPOK_Msk /*!< Repetition register update OK */
9529
9530/****************** Bit definition for LPTIM_ICR register *******************/
9531#define LPTIM_ICR_CMPMCF_Pos (0U)
9532#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
9533#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
9534#define LPTIM_ICR_ARRMCF_Pos (1U)
9535#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
9536#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
9537#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
9538#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
9539#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
9540#define LPTIM_ICR_CMPOKCF_Pos (3U)
9541#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
9542#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
9543#define LPTIM_ICR_ARROKCF_Pos (4U)
9544#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
9545#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
9546#define LPTIM_ICR_UPCF_Pos (5U)
9547#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
9548#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
9549#define LPTIM_ICR_DOWNCF_Pos (6U)
9550#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
9551#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
9552#define LPTIM_ICR_UECF_Pos (7U)
9553#define LPTIM_ICR_UECF_Msk (0x1UL << LPTIM_ICR_UECF_Pos) /*!< 0x00000080 */
9554#define LPTIM_ICR_UECF LPTIM_ICR_UECF_Msk /*!< Update event Clear Flag */
9555#define LPTIM_ICR_REPOKCF_Pos (8U)
9556#define LPTIM_ICR_REPOKCF_Msk (0x1UL << LPTIM_ICR_REPOKCF_Pos) /*!< 0x00000100 */
9557#define LPTIM_ICR_REPOKCF LPTIM_ICR_REPOKCF_Msk /*!< Repetition register update OK Clear Flag */
9558
9559/****************** Bit definition for LPTIM_IER register ********************/
9560#define LPTIM_IER_CMPMIE_Pos (0U)
9561#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
9562#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
9563#define LPTIM_IER_ARRMIE_Pos (1U)
9564#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
9565#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
9566#define LPTIM_IER_EXTTRIGIE_Pos (2U)
9567#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
9568#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
9569#define LPTIM_IER_CMPOKIE_Pos (3U)
9570#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
9571#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
9572#define LPTIM_IER_ARROKIE_Pos (4U)
9573#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
9574#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
9575#define LPTIM_IER_UPIE_Pos (5U)
9576#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
9577#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
9578#define LPTIM_IER_DOWNIE_Pos (6U)
9579#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
9580#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
9581#define LPTIM_IER_UEIE_Pos (7U)
9582#define LPTIM_IER_UEIE_Msk (0x1UL << LPTIM_IER_UEIE_Pos) /*!< 0x00000080 */
9583#define LPTIM_IER_UEIE LPTIM_IER_UEIE_Msk /*!< Update event Interrupt Enable */
9584#define LPTIM_IER_REPOKIE_Pos (8U)
9585#define LPTIM_IER_REPOKIE_Msk (0x1UL << LPTIM_IER_REPOKIE_Pos) /*!< 0x00000100 */
9586#define LPTIM_IER_REPOKIE LPTIM_IER_REPOKIE_Msk /*!< Repetition register update OK Interrupt Enable */
9587
9588/****************** Bit definition for LPTIM_CFGR register *******************/
9589#define LPTIM_CFGR_CKSEL_Pos (0U)
9590#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
9591#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
9592
9593#define LPTIM_CFGR_CKPOL_Pos (1U)
9594#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
9595#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
9596#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
9597#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
9598
9599#define LPTIM_CFGR_CKFLT_Pos (3U)
9600#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
9601#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
9602#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
9603#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
9604
9605#define LPTIM_CFGR_TRGFLT_Pos (6U)
9606#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
9607#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
9608#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
9609#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
9610
9611#define LPTIM_CFGR_PRESC_Pos (9U)
9612#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
9613#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
9614#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
9615#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
9616#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
9617
9618#define LPTIM_CFGR_TRIGSEL_Pos (13U)
9619#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
9620#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
9621#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
9622#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
9623#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
9624
9625#define LPTIM_CFGR_TRIGEN_Pos (17U)
9626#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
9627#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
9628#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
9629#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
9630
9631#define LPTIM_CFGR_TIMOUT_Pos (19U)
9632#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
9633#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
9634#define LPTIM_CFGR_WAVE_Pos (20U)
9635#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
9636#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
9637#define LPTIM_CFGR_WAVPOL_Pos (21U)
9638#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
9639#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
9640#define LPTIM_CFGR_PRELOAD_Pos (22U)
9641#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
9642#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
9643#define LPTIM_CFGR_COUNTMODE_Pos (23U)
9644#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
9645#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
9646#define LPTIM_CFGR_ENC_Pos (24U)
9647#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
9648#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
9649
9650/****************** Bit definition for LPTIM_CR register ********************/
9651#define LPTIM_CR_ENABLE_Pos (0U)
9652#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
9653#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
9654#define LPTIM_CR_SNGSTRT_Pos (1U)
9655#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
9656#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
9657#define LPTIM_CR_CNTSTRT_Pos (2U)
9658#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
9659#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
9660#define LPTIM_CR_COUNTRST_Pos (3U)
9661#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
9662#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
9663#define LPTIM_CR_RSTARE_Pos (4U)
9664#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
9665#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
9666
9667/****************** Bit definition for LPTIM_CMP register *******************/
9668#define LPTIM_CMP_CMP_Pos (0U)
9669#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
9670#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
9671
9672/****************** Bit definition for LPTIM_ARR register *******************/
9673#define LPTIM_ARR_ARR_Pos (0U)
9674#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
9675#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
9676
9677/****************** Bit definition for LPTIM_CNT register *******************/
9678#define LPTIM_CNT_CNT_Pos (0U)
9679#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
9680#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
9681
9682/****************** Bit definition for LPTIM_OR register *******************/
9683#define LPTIM_OR_OR_Pos (0U)
9684#define LPTIM_OR_OR_Msk (0x3UL << LPTIM_OR_OR_Pos) /*!< 0x00000003 */
9685#define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */
9686#define LPTIM_OR_OR_0 (0x1UL << LPTIM_OR_OR_Pos) /*!< 0x00000001 */
9687#define LPTIM_OR_OR_1 (0x2UL << LPTIM_OR_OR_Pos) /*!< 0x00000002 */
9688
9689/****************** Bit definition for LPTIM_RCR register *******************/
9690#define LPTIM_RCR_REP_Pos (0U)
9691#define LPTIM_RCR_REP_Msk (0xFFUL << LPTIM_RCR_REP_Pos) /*!< 0x000000FF */
9692#define LPTIM_RCR_REP LPTIM_RCR_REP_Msk /*!< Repetition Counter Value */
9693
9694/******************************************************************************/
9695/* */
9696/* OCTOSPI */
9697/* */
9698/******************************************************************************/
9699/***************** Bit definition for OCTOSPI_CR register *******************/
9700#define OCTOSPI_CR_EN_Pos (0U)
9701#define OCTOSPI_CR_EN_Msk (0x1UL << OCTOSPI_CR_EN_Pos) /*!< 0x00000001 */
9702#define OCTOSPI_CR_EN OCTOSPI_CR_EN_Msk /*!< Enable */
9703#define OCTOSPI_CR_ABORT_Pos (1U)
9704#define OCTOSPI_CR_ABORT_Msk (0x1UL << OCTOSPI_CR_ABORT_Pos) /*!< 0x00000002 */
9705#define OCTOSPI_CR_ABORT OCTOSPI_CR_ABORT_Msk /*!< Abort request */
9706#define OCTOSPI_CR_DMAEN_Pos (2U)
9707#define OCTOSPI_CR_DMAEN_Msk (0x1UL << OCTOSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
9708#define OCTOSPI_CR_DMAEN OCTOSPI_CR_DMAEN_Msk /*!< DMA Enable */
9709#define OCTOSPI_CR_TCEN_Pos (3U)
9710#define OCTOSPI_CR_TCEN_Msk (0x1UL << OCTOSPI_CR_TCEN_Pos) /*!< 0x00000008 */
9711#define OCTOSPI_CR_TCEN OCTOSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
9712#define OCTOSPI_CR_DQM_Pos (6U)
9713#define OCTOSPI_CR_DQM_Msk (0x1UL << OCTOSPI_CR_DQM_Pos) /*!< 0x00000040 */
9714#define OCTOSPI_CR_DQM OCTOSPI_CR_DQM_Msk /*!< Dual-Quad Mode */
9715#define OCTOSPI_CR_FSEL_Pos (7U)
9716#define OCTOSPI_CR_FSEL_Msk (0x1UL << OCTOSPI_CR_FSEL_Pos) /*!< 0x00000080 */
9717#define OCTOSPI_CR_FSEL OCTOSPI_CR_FSEL_Msk /*!< Flash Select */
9718#define OCTOSPI_CR_FTHRES_Pos (8U)
9719#define OCTOSPI_CR_FTHRES_Msk (0x1FUL << OCTOSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
9720#define OCTOSPI_CR_FTHRES OCTOSPI_CR_FTHRES_Msk /*!< FIFO Threshold Level */
9721#define OCTOSPI_CR_TEIE_Pos (16U)
9722#define OCTOSPI_CR_TEIE_Msk (0x1UL << OCTOSPI_CR_TEIE_Pos) /*!< 0x00010000 */
9723#define OCTOSPI_CR_TEIE OCTOSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
9724#define OCTOSPI_CR_TCIE_Pos (17U)
9725#define OCTOSPI_CR_TCIE_Msk (0x1UL << OCTOSPI_CR_TCIE_Pos) /*!< 0x00020000 */
9726#define OCTOSPI_CR_TCIE OCTOSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
9727#define OCTOSPI_CR_FTIE_Pos (18U)
9728#define OCTOSPI_CR_FTIE_Msk (0x1UL << OCTOSPI_CR_FTIE_Pos) /*!< 0x00040000 */
9729#define OCTOSPI_CR_FTIE OCTOSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
9730#define OCTOSPI_CR_SMIE_Pos (19U)
9731#define OCTOSPI_CR_SMIE_Msk (0x1UL << OCTOSPI_CR_SMIE_Pos) /*!< 0x00080000 */
9732#define OCTOSPI_CR_SMIE OCTOSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
9733#define OCTOSPI_CR_TOIE_Pos (20U)
9734#define OCTOSPI_CR_TOIE_Msk (0x1UL << OCTOSPI_CR_TOIE_Pos) /*!< 0x00100000 */
9735#define OCTOSPI_CR_TOIE OCTOSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
9736#define OCTOSPI_CR_APMS_Pos (22U)
9737#define OCTOSPI_CR_APMS_Msk (0x1UL << OCTOSPI_CR_APMS_Pos) /*!< 0x00400000 */
9738#define OCTOSPI_CR_APMS OCTOSPI_CR_APMS_Msk /*!< Automatic Poll Mode Stop */
9739#define OCTOSPI_CR_PMM_Pos (23U)
9740#define OCTOSPI_CR_PMM_Msk (0x1UL << OCTOSPI_CR_PMM_Pos) /*!< 0x00800000 */
9741#define OCTOSPI_CR_PMM OCTOSPI_CR_PMM_Msk /*!< Polling Match Mode */
9742#define OCTOSPI_CR_FMODE_Pos (28U)
9743#define OCTOSPI_CR_FMODE_Msk (0x3UL << OCTOSPI_CR_FMODE_Pos) /*!< 0x30000000 */
9744#define OCTOSPI_CR_FMODE OCTOSPI_CR_FMODE_Msk /*!< Functional Mode */
9745#define OCTOSPI_CR_FMODE_0 (0x1UL << OCTOSPI_CR_FMODE_Pos) /*!< 0x10000000 */
9746#define OCTOSPI_CR_FMODE_1 (0x2UL << OCTOSPI_CR_FMODE_Pos) /*!< 0x20000000 */
9747
9748/**************** Bit definition for OCTOSPI_DCR1 register ******************/
9749#define OCTOSPI_DCR1_CKMODE_Pos (0U)
9750#define OCTOSPI_DCR1_CKMODE_Msk (0x1UL << OCTOSPI_DCR1_CKMODE_Pos) /*!< 0x00000001 */
9751#define OCTOSPI_DCR1_CKMODE OCTOSPI_DCR1_CKMODE_Msk /*!< Mode 0 / Mode 3 */
9752#define OCTOSPI_DCR1_FRCK_Pos (1U)
9753#define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
9754#define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
9755#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
9756#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
9757#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */
9758#define OCTOSPI_DCR1_CSHT_Pos (8U)
9759#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
9760#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
9761#define OCTOSPI_DCR1_DEVSIZE_Pos (16U)
9762#define OCTOSPI_DCR1_DEVSIZE_Msk (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos) /*!< 0x001F0000 */
9763#define OCTOSPI_DCR1_DEVSIZE OCTOSPI_DCR1_DEVSIZE_Msk /*!< Device Size */
9764#define OCTOSPI_DCR1_MTYP_Pos (24U)
9765#define OCTOSPI_DCR1_MTYP_Msk (0x7UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
9766#define OCTOSPI_DCR1_MTYP OCTOSPI_DCR1_MTYP_Msk /*!< Memory Type */
9767#define OCTOSPI_DCR1_MTYP_0 (0x1UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
9768#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
9769#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
9770
9771/**************** Bit definition for OCTOSPI_DCR2 register ******************/
9772#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
9773#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
9774#define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */
9775#define OCTOSPI_DCR2_WRAPSIZE_Pos (16U)
9776#define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
9777#define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */
9778#define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
9779#define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
9780#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
9781
9782/**************** Bit definition for OCTOSPI_DCR3 register ******************/
9783#define OCTOSPI_DCR3_CSBOUND_Pos (16U)
9784#define OCTOSPI_DCR3_CSBOUND_Msk (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */
9785#define OCTOSPI_DCR3_CSBOUND OCTOSPI_DCR3_CSBOUND_Msk /*!< CS Boundary */
9786
9787/**************** Bit definition for OCTOSPI_DCR4 register ******************/
9788#define OCTOSPI_DCR4_REFRESH_Pos (0U)
9789#define OCTOSPI_DCR4_REFRESH_Msk (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos)/*!< 0xFFFFFFFF */
9790#define OCTOSPI_DCR4_REFRESH OCTOSPI_DCR4_REFRESH_Msk /*!< Refresh rate */
9791
9792/***************** Bit definition for OCTOSPI_SR register *******************/
9793#define OCTOSPI_SR_TEF_Pos (0U)
9794#define OCTOSPI_SR_TEF_Msk (0x1UL << OCTOSPI_SR_TEF_Pos) /*!< 0x00000001 */
9795#define OCTOSPI_SR_TEF OCTOSPI_SR_TEF_Msk /*!< Transfer Error Flag */
9796#define OCTOSPI_SR_TCF_Pos (1U)
9797#define OCTOSPI_SR_TCF_Msk (0x1UL << OCTOSPI_SR_TCF_Pos) /*!< 0x00000002 */
9798#define OCTOSPI_SR_TCF OCTOSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
9799#define OCTOSPI_SR_FTF_Pos (2U)
9800#define OCTOSPI_SR_FTF_Msk (0x1UL << OCTOSPI_SR_FTF_Pos) /*!< 0x00000004 */
9801#define OCTOSPI_SR_FTF OCTOSPI_SR_FTF_Msk /*!< FIFO Threshold Flag */
9802#define OCTOSPI_SR_SMF_Pos (3U)
9803#define OCTOSPI_SR_SMF_Msk (0x1UL << OCTOSPI_SR_SMF_Pos) /*!< 0x00000008 */
9804#define OCTOSPI_SR_SMF OCTOSPI_SR_SMF_Msk /*!< Status Match Flag */
9805#define OCTOSPI_SR_TOF_Pos (4U)
9806#define OCTOSPI_SR_TOF_Msk (0x1UL << OCTOSPI_SR_TOF_Pos) /*!< 0x00000010 */
9807#define OCTOSPI_SR_TOF OCTOSPI_SR_TOF_Msk /*!< Timeout Flag */
9808#define OCTOSPI_SR_BUSY_Pos (5U)
9809#define OCTOSPI_SR_BUSY_Msk (0x1UL << OCTOSPI_SR_BUSY_Pos) /*!< 0x00000020 */
9810#define OCTOSPI_SR_BUSY OCTOSPI_SR_BUSY_Msk /*!< Busy */
9811#define OCTOSPI_SR_FLEVEL_Pos (8U)
9812#define OCTOSPI_SR_FLEVEL_Msk (0x3FUL << OCTOSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
9813#define OCTOSPI_SR_FLEVEL OCTOSPI_SR_FLEVEL_Msk /*!< FIFO Level */
9814
9815/**************** Bit definition for OCTOSPI_FCR register *******************/
9816#define OCTOSPI_FCR_CTEF_Pos (0U)
9817#define OCTOSPI_FCR_CTEF_Msk (0x1UL << OCTOSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
9818#define OCTOSPI_FCR_CTEF OCTOSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
9819#define OCTOSPI_FCR_CTCF_Pos (1U)
9820#define OCTOSPI_FCR_CTCF_Msk (0x1UL << OCTOSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
9821#define OCTOSPI_FCR_CTCF OCTOSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
9822#define OCTOSPI_FCR_CSMF_Pos (3U)
9823#define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
9824#define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
9825#define OCTOSPI_FCR_CTOF_Pos (4U)
9826#define OCTOSPI_FCR_CTOF_Msk (0x1UL << OCTOSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
9827#define OCTOSPI_FCR_CTOF OCTOSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
9828
9829/**************** Bit definition for OCTOSPI_DLR register *******************/
9830#define OCTOSPI_DLR_DL_Pos (0U)
9831#define OCTOSPI_DLR_DL_Msk (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
9832#define OCTOSPI_DLR_DL OCTOSPI_DLR_DL_Msk /*!< Data Length */
9833
9834/***************** Bit definition for OCTOSPI_AR register *******************/
9835#define OCTOSPI_AR_ADDRESS_Pos (0U)
9836#define OCTOSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos)/*!< 0xFFFFFFFF */
9837#define OCTOSPI_AR_ADDRESS OCTOSPI_AR_ADDRESS_Msk /*!< Address */
9838
9839/***************** Bit definition for OCTOSPI_DR register *******************/
9840#define OCTOSPI_DR_DATA_Pos (0U)
9841#define OCTOSPI_DR_DATA_Msk (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
9842#define OCTOSPI_DR_DATA OCTOSPI_DR_DATA_Msk /*!< Data */
9843
9844/*************** Bit definition for OCTOSPI_PSMKR register ******************/
9845#define OCTOSPI_PSMKR_MASK_Pos (0U)
9846#define OCTOSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos)/*!< 0xFFFFFFFF */
9847#define OCTOSPI_PSMKR_MASK OCTOSPI_PSMKR_MASK_Msk /*!< Status mask */
9848
9849/*************** Bit definition for OCTOSPI_PSMAR register ******************/
9850#define OCTOSPI_PSMAR_MATCH_Pos (0U)
9851#define OCTOSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos)/*!< 0xFFFFFFFF */
9852#define OCTOSPI_PSMAR_MATCH OCTOSPI_PSMAR_MATCH_Msk /*!< Status match */
9853
9854/**************** Bit definition for OCTOSPI_PIR register *******************/
9855#define OCTOSPI_PIR_INTERVAL_Pos (0U)
9856#define OCTOSPI_PIR_INTERVAL_Msk (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
9857#define OCTOSPI_PIR_INTERVAL OCTOSPI_PIR_INTERVAL_Msk /*!< Polling Interval */
9858
9859/**************** Bit definition for OCTOSPI_CCR register *******************/
9860#define OCTOSPI_CCR_IMODE_Pos (0U)
9861#define OCTOSPI_CCR_IMODE_Msk (0x7UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000007 */
9862#define OCTOSPI_CCR_IMODE OCTOSPI_CCR_IMODE_Msk /*!< Instruction Mode */
9863#define OCTOSPI_CCR_IMODE_0 (0x1UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000001 */
9864#define OCTOSPI_CCR_IMODE_1 (0x2UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000002 */
9865#define OCTOSPI_CCR_IMODE_2 (0x4UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000004 */
9866#define OCTOSPI_CCR_IDTR_Pos (3U)
9867#define OCTOSPI_CCR_IDTR_Msk (0x1UL << OCTOSPI_CCR_IDTR_Pos) /*!< 0x00000008 */
9868#define OCTOSPI_CCR_IDTR OCTOSPI_CCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
9869#define OCTOSPI_CCR_ISIZE_Pos (4U)
9870#define OCTOSPI_CCR_ISIZE_Msk (0x3UL << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000030 */
9871#define OCTOSPI_CCR_ISIZE OCTOSPI_CCR_ISIZE_Msk /*!< Instruction Size */
9872#define OCTOSPI_CCR_ISIZE_0 (0x1UL << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000010 */
9873#define OCTOSPI_CCR_ISIZE_1 (0x2UL << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000020 */
9874#define OCTOSPI_CCR_ADMODE_Pos (8U)
9875#define OCTOSPI_CCR_ADMODE_Msk (0x7UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000700 */
9876#define OCTOSPI_CCR_ADMODE OCTOSPI_CCR_ADMODE_Msk /*!< Address Mode */
9877#define OCTOSPI_CCR_ADMODE_0 (0x1UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000100 */
9878#define OCTOSPI_CCR_ADMODE_1 (0x2UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000200 */
9879#define OCTOSPI_CCR_ADMODE_2 (0x4UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
9880#define OCTOSPI_CCR_ADDTR_Pos (11U)
9881#define OCTOSPI_CCR_ADDTR_Msk (0x1UL << OCTOSPI_CCR_ADDTR_Pos) /*!< 0x00000800 */
9882#define OCTOSPI_CCR_ADDTR OCTOSPI_CCR_ADDTR_Msk /*!< Address Double Transfer Rate */
9883#define OCTOSPI_CCR_ADSIZE_Pos (12U)
9884#define OCTOSPI_CCR_ADSIZE_Msk (0x3UL << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
9885#define OCTOSPI_CCR_ADSIZE OCTOSPI_CCR_ADSIZE_Msk /*!< Address Size */
9886#define OCTOSPI_CCR_ADSIZE_0 (0x1UL << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
9887#define OCTOSPI_CCR_ADSIZE_1 (0x2UL << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
9888#define OCTOSPI_CCR_ABMODE_Pos (16U)
9889#define OCTOSPI_CCR_ABMODE_Msk (0x7UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00070000 */
9890#define OCTOSPI_CCR_ABMODE OCTOSPI_CCR_ABMODE_Msk /*!< Alternate Bytes Mode */
9891#define OCTOSPI_CCR_ABMODE_0 (0x1UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00010000 */
9892#define OCTOSPI_CCR_ABMODE_1 (0x2UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00020000 */
9893#define OCTOSPI_CCR_ABMODE_2 (0x4UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00040000 */
9894#define OCTOSPI_CCR_ABDTR_Pos (19U)
9895#define OCTOSPI_CCR_ABDTR_Msk (0x1UL << OCTOSPI_CCR_ABDTR_Pos) /*!< 0x00080000 */
9896#define OCTOSPI_CCR_ABDTR OCTOSPI_CCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
9897#define OCTOSPI_CCR_ABSIZE_Pos (20U)
9898#define OCTOSPI_CCR_ABSIZE_Msk (0x3UL << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00300000 */
9899#define OCTOSPI_CCR_ABSIZE OCTOSPI_CCR_ABSIZE_Msk /*!< Alternate Bytes Size */
9900#define OCTOSPI_CCR_ABSIZE_0 (0x1UL << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00100000 */
9901#define OCTOSPI_CCR_ABSIZE_1 (0x2UL << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00200000 */
9902#define OCTOSPI_CCR_DMODE_Pos (24U)
9903#define OCTOSPI_CCR_DMODE_Msk (0x7UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x07000000 */
9904#define OCTOSPI_CCR_DMODE OCTOSPI_CCR_DMODE_Msk /*!< Data Mode */
9905#define OCTOSPI_CCR_DMODE_0 (0x1UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
9906#define OCTOSPI_CCR_DMODE_1 (0x2UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
9907#define OCTOSPI_CCR_DMODE_2 (0x4UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x04000000 */
9908#define OCTOSPI_CCR_DDTR_Pos (27U)
9909#define OCTOSPI_CCR_DDTR_Msk (0x1UL << OCTOSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
9910#define OCTOSPI_CCR_DDTR OCTOSPI_CCR_DDTR_Msk /*!< Data Double Transfer Rate */
9911#define OCTOSPI_CCR_DQSE_Pos (29U)
9912#define OCTOSPI_CCR_DQSE_Msk (0x1UL << OCTOSPI_CCR_DQSE_Pos) /*!< 0x20000000 */
9913#define OCTOSPI_CCR_DQSE OCTOSPI_CCR_DQSE_Msk /*!< DQS Enable */
9914#define OCTOSPI_CCR_SIOO_Pos (31U)
9915#define OCTOSPI_CCR_SIOO_Msk (0x1UL << OCTOSPI_CCR_SIOO_Pos) /*!< 0x80000000 */
9916#define OCTOSPI_CCR_SIOO OCTOSPI_CCR_SIOO_Msk /*!< Send Instruction Only Once Mode */
9917
9918/**************** Bit definition for OCTOSPI_TCR register *******************/
9919#define OCTOSPI_TCR_DCYC_Pos (0U)
9920#define OCTOSPI_TCR_DCYC_Msk (0x1FUL << OCTOSPI_TCR_DCYC_Pos) /*!< 0x0000001F */
9921#define OCTOSPI_TCR_DCYC OCTOSPI_TCR_DCYC_Msk /*!< Number of Dummy Cycles */
9922#define OCTOSPI_TCR_DHQC_Pos (28U)
9923#define OCTOSPI_TCR_DHQC_Msk (0x1UL << OCTOSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
9924#define OCTOSPI_TCR_DHQC OCTOSPI_TCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */
9925#define OCTOSPI_TCR_SSHIFT_Pos (30U)
9926#define OCTOSPI_TCR_SSHIFT_Msk (0x1UL << OCTOSPI_TCR_SSHIFT_Pos) /*!< 0x40000000 */
9927#define OCTOSPI_TCR_SSHIFT OCTOSPI_TCR_SSHIFT_Msk /*!< Sample Shift */
9928
9929/***************** Bit definition for OCTOSPI_IR register *******************/
9930#define OCTOSPI_IR_INSTRUCTION_Pos (0U)
9931#define OCTOSPI_IR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos)/*!< 0xFFFFFFFF */
9932#define OCTOSPI_IR_INSTRUCTION OCTOSPI_IR_INSTRUCTION_Msk /*!< Instruction */
9933
9934/**************** Bit definition for OCTOSPI_ABR register *******************/
9935#define OCTOSPI_ABR_ALTERNATE_Pos (0U)
9936#define OCTOSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos)/*!< 0xFFFFFFFF */
9937#define OCTOSPI_ABR_ALTERNATE OCTOSPI_ABR_ALTERNATE_Msk /*!< Alternate Bytes */
9938
9939/**************** Bit definition for OCTOSPI_LPTR register ******************/
9940#define OCTOSPI_LPTR_TIMEOUT_Pos (0U)
9941#define OCTOSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
9942#define OCTOSPI_LPTR_TIMEOUT OCTOSPI_LPTR_TIMEOUT_Msk /*!< Timeout period */
9943
9944/**************** Bit definition for OCTOSPI_WPCCR register *******************/
9945#define OCTOSPI_WPCCR_IMODE_Pos (0U)
9946#define OCTOSPI_WPCCR_IMODE_Msk (0x7UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000007 */
9947#define OCTOSPI_WPCCR_IMODE OCTOSPI_WPCCR_IMODE_Msk /*!< Instruction Mode */
9948#define OCTOSPI_WPCCR_IMODE_0 (0x1UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000001 */
9949#define OCTOSPI_WPCCR_IMODE_1 (0x2UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000002 */
9950#define OCTOSPI_WPCCR_IMODE_2 (0x4UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000004 */
9951#define OCTOSPI_WPCCR_IDTR_Pos (3U)
9952#define OCTOSPI_WPCCR_IDTR_Msk (0x1UL << OCTOSPI_WPCCR_IDTR_Pos) /*!< 0x00000008 */
9953#define OCTOSPI_WPCCR_IDTR OCTOSPI_WPCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
9954#define OCTOSPI_WPCCR_ISIZE_Pos (4U)
9955#define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
9956#define OCTOSPI_WPCCR_ISIZE OCTOSPI_WPCCR_ISIZE_Msk /*!< Instruction Size */
9957#define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
9958#define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
9959#define OCTOSPI_WPCCR_ADMODE_Pos (8U)
9960#define OCTOSPI_WPCCR_ADMODE_Msk (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000700 */
9961#define OCTOSPI_WPCCR_ADMODE OCTOSPI_WPCCR_ADMODE_Msk /*!< Address Mode */
9962#define OCTOSPI_WPCCR_ADMODE_0 (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000100 */
9963#define OCTOSPI_WPCCR_ADMODE_1 (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000200 */
9964#define OCTOSPI_WPCCR_ADMODE_2 (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000400 */
9965#define OCTOSPI_WPCCR_ADDTR_Pos (11U)
9966#define OCTOSPI_WPCCR_ADDTR_Msk (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos) /*!< 0x00000800 */
9967#define OCTOSPI_WPCCR_ADDTR OCTOSPI_WPCCR_ADDTR_Msk /*!< Address Double Transfer Rate */
9968#define OCTOSPI_WPCCR_ADSIZE_Pos (12U)
9969#define OCTOSPI_WPCCR_ADSIZE_Msk (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos) /*!< 0x00003000 */
9970#define OCTOSPI_WPCCR_ADSIZE OCTOSPI_WPCCR_ADSIZE_Msk /*!< Address Size */
9971#define OCTOSPI_WPCCR_ADSIZE_0 (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos) /*!< 0x00001000 */
9972#define OCTOSPI_WPCCR_ADSIZE_1 (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos) /*!< 0x00002000 */
9973#define OCTOSPI_WPCCR_ABMODE_Pos (16U)
9974#define OCTOSPI_WPCCR_ABMODE_Msk (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00070000 */
9975#define OCTOSPI_WPCCR_ABMODE OCTOSPI_WPCCR_ABMODE_Msk /*!< Alternate Bytes Mode */
9976#define OCTOSPI_WPCCR_ABMODE_0 (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00010000 */
9977#define OCTOSPI_WPCCR_ABMODE_1 (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00020000 */
9978#define OCTOSPI_WPCCR_ABMODE_2 (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00040000 */
9979#define OCTOSPI_WPCCR_ABDTR_Pos (19U)
9980#define OCTOSPI_WPCCR_ABDTR_Msk (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos) /*!< 0x00080000 */
9981#define OCTOSPI_WPCCR_ABDTR OCTOSPI_WPCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
9982#define OCTOSPI_WPCCR_ABSIZE_Pos (20U)
9983#define OCTOSPI_WPCCR_ABSIZE_Msk (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos) /*!< 0x00300000 */
9984#define OCTOSPI_WPCCR_ABSIZE OCTOSPI_WPCCR_ABSIZE_Msk /*!< Alternate Bytes Size */
9985#define OCTOSPI_WPCCR_ABSIZE_0 (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos) /*!< 0x00100000 */
9986#define OCTOSPI_WPCCR_ABSIZE_1 (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos) /*!< 0x00200000 */
9987#define OCTOSPI_WPCCR_DMODE_Pos (24U)
9988#define OCTOSPI_WPCCR_DMODE_Msk (0x7UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x07000000 */
9989#define OCTOSPI_WPCCR_DMODE OCTOSPI_WPCCR_DMODE_Msk /*!< Data Mode */
9990#define OCTOSPI_WPCCR_DMODE_0 (0x1UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x01000000 */
9991#define OCTOSPI_WPCCR_DMODE_1 (0x2UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x02000000 */
9992#define OCTOSPI_WPCCR_DMODE_2 (0x4UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x04000000 */
9993#define OCTOSPI_WPCCR_DDTR_Pos (27U)
9994#define OCTOSPI_WPCCR_DDTR_Msk (0x1UL << OCTOSPI_WPCCR_DDTR_Pos) /*!< 0x08000000 */
9995#define OCTOSPI_WPCCR_DDTR OCTOSPI_WPCCR_DDTR_Msk /*!< Data Double Transfer Rate */
9996#define OCTOSPI_WPCCR_DQSE_Pos (29U)
9997#define OCTOSPI_WPCCR_DQSE_Msk (0x1UL << OCTOSPI_WPCCR_DQSE_Pos) /*!< 0x20000000 */
9998#define OCTOSPI_WPCCR_DQSE OCTOSPI_WPCCR_DQSE_Msk /*!< DQS Enable */
9999
10000/**************** Bit definition for OCTOSPI_WPTCR register *******************/
10001#define OCTOSPI_WPTCR_DCYC_Pos (0U)
10002#define OCTOSPI_WPTCR_DCYC_Msk (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos) /*!< 0x0000001F */
10003#define OCTOSPI_WPTCR_DCYC OCTOSPI_WPTCR_DCYC_Msk /*!< Number of Dummy Cycles */
10004#define OCTOSPI_WPTCR_DHQC_Pos (28U)
10005#define OCTOSPI_WPTCR_DHQC_Msk (0x1UL << OCTOSPI_WPTCR_DHQC_Pos) /*!< 0x10000000 */
10006#define OCTOSPI_WPTCR_DHQC OCTOSPI_WPTCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */
10007#define OCTOSPI_WPTCR_SSHIFT_Pos (30U)
10008#define OCTOSPI_WPTCR_SSHIFT_Msk (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos) /*!< 0x40000000 */
10009#define OCTOSPI_WPTCR_SSHIFT OCTOSPI_WPTCR_SSHIFT_Msk /*!< Sample Shift */
10010
10011/***************** Bit definition for OCTOSPI_WPIR register *******************/
10012#define OCTOSPI_WPIR_INSTRUCTION_Pos (0U)
10013#define OCTOSPI_WPIR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos)/*!< 0xFFFFFFFF */
10014#define OCTOSPI_WPIR_INSTRUCTION OCTOSPI_WPIR_INSTRUCTION_Msk /*!< Instruction */
10015
10016/**************** Bit definition for OCTOSPI_WPABR register *******************/
10017#define OCTOSPI_WPABR_ALTERNATE_Pos (0U)
10018#define OCTOSPI_WPABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos)/*!< 0xFFFFFFFF */
10019#define OCTOSPI_WPABR_ALTERNATE OCTOSPI_WPABR_ALTERNATE_Msk /*!< Alternate Bytes */
10020
10021/**************** Bit definition for OCTOSPI_WCCR register ******************/
10022#define OCTOSPI_WCCR_IMODE_Pos (0U)
10023#define OCTOSPI_WCCR_IMODE_Msk (0x7UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
10024#define OCTOSPI_WCCR_IMODE OCTOSPI_WCCR_IMODE_Msk /*!< Instruction Mode */
10025#define OCTOSPI_WCCR_IMODE_0 (0x1UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
10026#define OCTOSPI_WCCR_IMODE_1 (0x2UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
10027#define OCTOSPI_WCCR_IMODE_2 (0x4UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
10028#define OCTOSPI_WCCR_IDTR_Pos (3U)
10029#define OCTOSPI_WCCR_IDTR_Msk (0x1UL << OCTOSPI_WCCR_IDTR_Pos) /*!< 0x00000008 */
10030#define OCTOSPI_WCCR_IDTR OCTOSPI_WCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
10031#define OCTOSPI_WCCR_ISIZE_Pos (4U)
10032#define OCTOSPI_WCCR_ISIZE_Msk (0x3UL << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000030 */
10033#define OCTOSPI_WCCR_ISIZE OCTOSPI_WCCR_ISIZE_Msk /*!< Instruction Size */
10034#define OCTOSPI_WCCR_ISIZE_0 (0x1UL << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000010 */
10035#define OCTOSPI_WCCR_ISIZE_1 (0x2UL << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000020 */
10036#define OCTOSPI_WCCR_ADMODE_Pos (8U)
10037#define OCTOSPI_WCCR_ADMODE_Msk (0x7UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000700 */
10038#define OCTOSPI_WCCR_ADMODE OCTOSPI_WCCR_ADMODE_Msk /*!< Address Mode */
10039#define OCTOSPI_WCCR_ADMODE_0 (0x1UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000100 */
10040#define OCTOSPI_WCCR_ADMODE_1 (0x2UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000200 */
10041#define OCTOSPI_WCCR_ADMODE_2 (0x4UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000400 */
10042#define OCTOSPI_WCCR_ADDTR_Pos (11U)
10043#define OCTOSPI_WCCR_ADDTR_Msk (0x1UL << OCTOSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
10044#define OCTOSPI_WCCR_ADDTR OCTOSPI_WCCR_ADDTR_Msk /*!< Address Double Transfer Rate */
10045#define OCTOSPI_WCCR_ADSIZE_Pos (12U)
10046#define OCTOSPI_WCCR_ADSIZE_Msk (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00003000 */
10047#define OCTOSPI_WCCR_ADSIZE OCTOSPI_WCCR_ADSIZE_Msk /*!< Address Size */
10048#define OCTOSPI_WCCR_ADSIZE_0 (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00001000 */
10049#define OCTOSPI_WCCR_ADSIZE_1 (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00002000 */
10050#define OCTOSPI_WCCR_ABMODE_Pos (16U)
10051#define OCTOSPI_WCCR_ABMODE_Msk (0x7UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00070000 */
10052#define OCTOSPI_WCCR_ABMODE OCTOSPI_WCCR_ABMODE_Msk /*!< Alternate Bytes Mode */
10053#define OCTOSPI_WCCR_ABMODE_0 (0x1UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00010000 */
10054#define OCTOSPI_WCCR_ABMODE_1 (0x2UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00020000 */
10055#define OCTOSPI_WCCR_ABMODE_2 (0x4UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00040000 */
10056#define OCTOSPI_WCCR_ABDTR_Pos (19U)
10057#define OCTOSPI_WCCR_ABDTR_Msk (0x1UL << OCTOSPI_WCCR_ABDTR_Pos) /*!< 0x00080000 */
10058#define OCTOSPI_WCCR_ABDTR OCTOSPI_WCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
10059#define OCTOSPI_WCCR_ABSIZE_Pos (20U)
10060#define OCTOSPI_WCCR_ABSIZE_Msk (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00300000 */
10061#define OCTOSPI_WCCR_ABSIZE OCTOSPI_WCCR_ABSIZE_Msk /*!< Alternate Bytes Size */
10062#define OCTOSPI_WCCR_ABSIZE_0 (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00100000 */
10063#define OCTOSPI_WCCR_ABSIZE_1 (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00200000 */
10064#define OCTOSPI_WCCR_DMODE_Pos (24U)
10065#define OCTOSPI_WCCR_DMODE_Msk (0x7UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x07000000 */
10066#define OCTOSPI_WCCR_DMODE OCTOSPI_WCCR_DMODE_Msk /*!< Data Mode */
10067#define OCTOSPI_WCCR_DMODE_0 (0x1UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x01000000 */
10068#define OCTOSPI_WCCR_DMODE_1 (0x2UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x02000000 */
10069#define OCTOSPI_WCCR_DMODE_2 (0x4UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x04000000 */
10070#define OCTOSPI_WCCR_DDTR_Pos (27U)
10071#define OCTOSPI_WCCR_DDTR_Msk (0x1UL << OCTOSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
10072#define OCTOSPI_WCCR_DDTR OCTOSPI_WCCR_DDTR_Msk /*!< Data Double Transfer Rate */
10073#define OCTOSPI_WCCR_DQSE_Pos (29U)
10074#define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */
10075#define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */
10076
10077/**************** Bit definition for OCTOSPI_WTCR register ******************/
10078#define OCTOSPI_WTCR_DCYC_Pos (0U)
10079#define OCTOSPI_WTCR_DCYC_Msk (0x1FUL << OCTOSPI_WTCR_DCYC_Pos) /*!< 0x0000001F */
10080#define OCTOSPI_WTCR_DCYC OCTOSPI_WTCR_DCYC_Msk /*!< Number of Dummy Cycles */
10081
10082/**************** Bit definition for OCTOSPI_WIR register *******************/
10083#define OCTOSPI_WIR_INSTRUCTION_Pos (0U)
10084#define OCTOSPI_WIR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos)/*!< 0xFFFFFFFF */
10085#define OCTOSPI_WIR_INSTRUCTION OCTOSPI_WIR_INSTRUCTION_Msk /*!< Instruction */
10086
10087/**************** Bit definition for OCTOSPI_WABR register ******************/
10088#define OCTOSPI_WABR_ALTERNATE_Pos (0U)
10089#define OCTOSPI_WABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos)/*!< 0xFFFFFFFF */
10090#define OCTOSPI_WABR_ALTERNATE OCTOSPI_WABR_ALTERNATE_Msk /*!< Alternate Bytes */
10091
10092/**************** Bit definition for OCTOSPI_HLCR register ******************/
10093#define OCTOSPI_HLCR_LM_Pos (0U)
10094#define OCTOSPI_HLCR_LM_Msk (0x1UL << OCTOSPI_HLCR_LM_Pos) /*!< 0x00000001 */
10095#define OCTOSPI_HLCR_LM OCTOSPI_HLCR_LM_Msk /*!< Latency Mode */
10096#define OCTOSPI_HLCR_WZL_Pos (1U)
10097#define OCTOSPI_HLCR_WZL_Msk (0x1UL << OCTOSPI_HLCR_WZL_Pos) /*!< 0x00000002 */
10098#define OCTOSPI_HLCR_WZL OCTOSPI_HLCR_WZL_Msk /*!< Write Zero Latency */
10099#define OCTOSPI_HLCR_TACC_Pos (8U)
10100#define OCTOSPI_HLCR_TACC_Msk (0xFFUL << OCTOSPI_HLCR_TACC_Pos) /*!< 0x0000FF00 */
10101#define OCTOSPI_HLCR_TACC OCTOSPI_HLCR_TACC_Msk /*!< Access Time */
10102#define OCTOSPI_HLCR_TRWR_Pos (16U)
10103#define OCTOSPI_HLCR_TRWR_Msk (0xFFUL << OCTOSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */
10104#define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */
10105
10106/******************************************************************************/
10107/* */
10108/* Operational Amplifier (OPAMP) */
10109/* */
10110/******************************************************************************/
10111/********************* Bit definition for OPAMPx_CSR register ***************/
10112#define OPAMP_CSR_OPAMPxEN_Pos (0U)
10113#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
10114#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
10115#define OPAMP_CSR_OPALPM_Pos (1U)
10116#define OPAMP_CSR_OPALPM_Msk (0x1UL << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */
10117#define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */
10118
10119#define OPAMP_CSR_OPAMODE_Pos (2U)
10120#define OPAMP_CSR_OPAMODE_Msk (0x3UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */
10121#define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */
10122#define OPAMP_CSR_OPAMODE_0 (0x1UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */
10123#define OPAMP_CSR_OPAMODE_1 (0x2UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */
10124
10125#define OPAMP_CSR_PGGAIN_Pos (4U)
10126#define OPAMP_CSR_PGGAIN_Msk (0x3UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000030 */
10127#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
10128#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000010 */
10129#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000020 */
10130
10131#define OPAMP_CSR_VMSEL_Pos (8U)
10132#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000300 */
10133#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
10134#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000100 */
10135#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000200 */
10136
10137#define OPAMP_CSR_VPSEL_Pos (10U)
10138#define OPAMP_CSR_VPSEL_Msk (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000400 */
10139#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
10140#define OPAMP_CSR_CALON_Pos (12U)
10141#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */
10142#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
10143#define OPAMP_CSR_CALSEL_Pos (13U)
10144#define OPAMP_CSR_CALSEL_Msk (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
10145#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
10146#define OPAMP_CSR_USERTRIM_Pos (14U)
10147#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */
10148#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
10149#define OPAMP_CSR_CALOUT_Pos (15U)
10150#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */
10151#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
10152
10153/********************* Bit definition for OPAMP1_CSR register ***************/
10154#define OPAMP1_CSR_OPAEN_Pos (0U)
10155#define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
10156#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
10157#define OPAMP1_CSR_OPALPM_Pos (1U)
10158#define OPAMP1_CSR_OPALPM_Msk (0x1UL << OPAMP1_CSR_OPALPM_Pos) /*!< 0x00000002 */
10159#define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk /*!< Operational amplifier1 Low Power Mode */
10160
10161#define OPAMP1_CSR_OPAMODE_Pos (2U)
10162#define OPAMP1_CSR_OPAMODE_Msk (0x3UL << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x0000000C */
10163#define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk /*!< Operational amplifier1 PGA mode */
10164#define OPAMP1_CSR_OPAMODE_0 (0x1UL << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000004 */
10165#define OPAMP1_CSR_OPAMODE_1 (0x2UL << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000008 */
10166
10167#define OPAMP1_CSR_PGAGAIN_Pos (4U)
10168#define OPAMP1_CSR_PGAGAIN_Msk (0x3UL << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
10169#define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
10170#define OPAMP1_CSR_PGAGAIN_0 (0x1UL << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
10171#define OPAMP1_CSR_PGAGAIN_1 (0x2UL << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
10172
10173#define OPAMP1_CSR_VMSEL_Pos (8U)
10174#define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000300 */
10175#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
10176#define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000100 */
10177#define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000200 */
10178
10179#define OPAMP1_CSR_VPSEL_Pos (10U)
10180#define OPAMP1_CSR_VPSEL_Msk (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */
10181#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
10182#define OPAMP1_CSR_CALON_Pos (12U)
10183#define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos) /*!< 0x00001000 */
10184#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
10185#define OPAMP1_CSR_CALSEL_Pos (13U)
10186#define OPAMP1_CSR_CALSEL_Msk (0x1UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
10187#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
10188#define OPAMP1_CSR_USERTRIM_Pos (14U)
10189#define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00004000 */
10190#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
10191#define OPAMP1_CSR_CALOUT_Pos (15U)
10192#define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos) /*!< 0x00008000 */
10193#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
10194
10195#define OPAMP1_CSR_OPARANGE_Pos (31U)
10196#define OPAMP1_CSR_OPARANGE_Msk (0x1UL << OPAMP1_CSR_OPARANGE_Pos) /*!< 0x80000000 */
10197#define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
10198
10199/********************* Bit definition for OPAMP2_CSR register ***************/
10200#define OPAMP2_CSR_OPAEN_Pos (0U)
10201#define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
10202#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
10203#define OPAMP2_CSR_OPALPM_Pos (1U)
10204#define OPAMP2_CSR_OPALPM_Msk (0x1UL << OPAMP2_CSR_OPALPM_Pos) /*!< 0x00000002 */
10205#define OPAMP2_CSR_OPALPM OPAMP2_CSR_OPALPM_Msk /*!< Operational amplifier2 Low Power Mode */
10206
10207#define OPAMP2_CSR_OPAMODE_Pos (2U)
10208#define OPAMP2_CSR_OPAMODE_Msk (0x3UL << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x0000000C */
10209#define OPAMP2_CSR_OPAMODE OPAMP2_CSR_OPAMODE_Msk /*!< Operational amplifier2 PGA mode */
10210#define OPAMP2_CSR_OPAMODE_0 (0x1UL << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000004 */
10211#define OPAMP2_CSR_OPAMODE_1 (0x2UL << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000008 */
10212
10213#define OPAMP2_CSR_PGAGAIN_Pos (4U)
10214#define OPAMP2_CSR_PGAGAIN_Msk (0x3UL << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
10215#define OPAMP2_CSR_PGAGAIN OPAMP2_CSR_PGAGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
10216#define OPAMP2_CSR_PGAGAIN_0 (0x1UL << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
10217#define OPAMP2_CSR_PGAGAIN_1 (0x2UL << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
10218
10219#define OPAMP2_CSR_VMSEL_Pos (8U)
10220#define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000300 */
10221#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
10222#define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000100 */
10223#define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000200 */
10224
10225#define OPAMP2_CSR_VPSEL_Pos (10U)
10226#define OPAMP2_CSR_VPSEL_Msk (0x1UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000400 */
10227#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
10228#define OPAMP2_CSR_CALON_Pos (12U)
10229#define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos) /*!< 0x00001000 */
10230#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
10231#define OPAMP2_CSR_CALSEL_Pos (13U)
10232#define OPAMP2_CSR_CALSEL_Msk (0x1UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
10233#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
10234#define OPAMP2_CSR_USERTRIM_Pos (14U)
10235#define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00004000 */
10236#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
10237#define OPAMP2_CSR_CALOUT_Pos (15U)
10238#define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos) /*!< 0x00008000 */
10239#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
10240
10241/******************* Bit definition for OPAMP_OTR register ******************/
10242#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
10243#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
10244#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
10245#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
10246#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
10247#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
10248
10249/******************* Bit definition for OPAMP1_OTR register ******************/
10250#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
10251#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos)/*!< 0x0000001F */
10252#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
10253#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
10254#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos)/*!< 0x00001F00 */
10255#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
10256
10257/******************* Bit definition for OPAMP2_OTR register ******************/
10258#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
10259#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos)/*!< 0x0000001F */
10260#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
10261#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
10262#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos)/*!< 0x00001F00 */
10263#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
10264
10265/******************* Bit definition for OPAMP_LPOTR register ****************/
10266#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
10267#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos)/*!< 0x0000001F */
10268#define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
10269#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
10270#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos)/*!< 0x00001F00 */
10271#define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
10272
10273/******************* Bit definition for OPAMP1_LPOTR register ****************/
10274#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
10275#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos)/*!< 0x0000001F */
10276#define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
10277#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
10278#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos)/*!< 0x00001F00 */
10279#define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
10280
10281/******************* Bit definition for OPAMP2_LPOTR register ****************/
10282#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos (0U)
10283#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos)/*!< 0x0000001F */
10284#define OPAMP2_LPOTR_TRIMLPOFFSETN OPAMP2_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
10285#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos (8U)
10286#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos)/*!< 0x00001F00 */
10287#define OPAMP2_LPOTR_TRIMLPOFFSETP OPAMP2_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
10288
10289/******************************************************************************/
10290/* */
10291/* On The Fly Decryption */
10292/* */
10293/******************************************************************************/
10294/****************** Bit definition for OTFDEC_CR register ******************/
10295#define OTFDEC_CR_ENC_Pos (0U)
10296#define OTFDEC_CR_ENC_Msk (0x1UL << OTFDEC_CR_ENC_Pos) /*!< 0x00000001 */
10297#define OTFDEC_CR_ENC OTFDEC_CR_ENC_Msk /*!< OTFDEC encryption mode */
10298
10299/****************** Bit definition for OTFDEC_PRIVCFGR register ************/
10300#define OTFDEC_PRIVCFGR_PRIV_Pos (0U)
10301#define OTFDEC_PRIVCFGR_PRIV_Msk (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos) /*!< 0x00000001 */
10302#define OTFDEC_PRIVCFGR_PRIV OTFDEC_PRIVCFGR_PRIV_Msk /*!< Privileged access protection */
10303
10304/****************** Bit definition for OTFDEC_REG_CONFIGR register *********/
10305#define OTFDEC_REG_CONFIGR_REG_EN_Pos (0U)
10306#define OTFDEC_REG_CONFIGR_REG_EN_Msk (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos) /*!< 0x00000001 */
10307#define OTFDEC_REG_CONFIGR_REG_EN OTFDEC_REG_CONFIGR_REG_EN_Msk /*!< Region on-the-fly decryption enable */
10308
10309#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos (1U)
10310#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos) /*!< 0x00000002 */
10311#define OTFDEC_REG_CONFIGR_CONFIGLOCK OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk /*!< Region config lock */
10312
10313#define OTFDEC_REG_CONFIGR_KEYLOCK_Pos (2U)
10314#define OTFDEC_REG_CONFIGR_KEYLOCK_Msk (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos) /*!< 0x00000004 */
10315#define OTFDEC_REG_CONFIGR_KEYLOCK OTFDEC_REG_CONFIGR_KEYLOCK_Msk /*!< Region key lock */
10316
10317#define OTFDEC_REG_CONFIGR_MODE_Pos (4U)
10318#define OTFDEC_REG_CONFIGR_MODE_Msk (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos) /*!< 0x00000030 */
10319#define OTFDEC_REG_CONFIGR_MODE OTFDEC_REG_CONFIGR_MODE_Msk /*!< Region operating mode */
10320#define OTFDEC_REG_CONFIGR_MODE_0 (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos) /*!< 0x00000010 */
10321#define OTFDEC_REG_CONFIGR_MODE_1 (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos) /*!< 0x00000020 */
10322
10323#define OTFDEC_REG_CONFIGR_KEYCRC_Pos (8U)
10324#define OTFDEC_REG_CONFIGR_KEYCRC_Msk (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos) /*!< 0x0000FF00 */
10325#define OTFDEC_REG_CONFIGR_KEYCRC OTFDEC_REG_CONFIGR_KEYCRC_Msk /*!< Region key 8-bit CRC */
10326
10327#define OTFDEC_REG_CONFIGR_VERSION_Pos (16U)
10328#define OTFDEC_REG_CONFIGR_VERSION_Msk (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos) /*!< 0xFFFF0000 */
10329#define OTFDEC_REG_CONFIGR_VERSION OTFDEC_REG_CONFIGR_VERSION_Msk /*!< Region firmware version */
10330
10331/****************** Bit definition for OTFDEC_REG_START_ADDR register ******/
10332#define OTFDEC_REG_START_ADDR_Pos (0U)
10333#define OTFDEC_REG_START_ADDR_Msk (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos) /*!< 0xFFFFFFFF */
10334#define OTFDEC_REG_START_ADDR OTFDEC_REG_START_ADDR_Msk /*!< Region AHB start address */
10335
10336/****************** Bit definition for OTFDEC_REG_END_ADDR register ********/
10337#define OTFDEC_REG_END_ADDR_Pos (0U)
10338#define OTFDEC_REG_END_ADDR_Msk (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos) /*!< 0xFFFFFFFF */
10339#define OTFDEC_REG_END_ADDR OTFDEC_REG_END_ADDR_Msk /*!< Region AHB end address */
10340
10341/****************** Bit definition for OTFDEC_REG_NONCER0 register *********/
10342#define OTFDEC_REG_NONCER0_Pos (0U)
10343#define OTFDEC_REG_NONCER0_Msk (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos) /*!< 0xFFFFFFFF */
10344#define OTFDEC_REG_NONCER0 OTFDEC_REG_NONCER0_Msk /*!< Region Nonce Register (LSB nonce[31:0]) */
10345
10346/****************** Bit definition for OTFDEC_REG_NONCER1 register *********/
10347#define OTFDEC_REG_NONCER1_Pos (0U)
10348#define OTFDEC_REG_NONCER1_Msk (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos) /*!< 0xFFFFFFFF */
10349#define OTFDEC_REG_NONCER1 OTFDEC_REG_NONCER1_Msk /*!< Region Nonce Register (MSB nonce[63:32]) */
10350
10351/****************** Bit definition for OTFDEC_REG_KEYR0 register ***********/
10352#define OTFDEC_REG_KEYR0_Pos (0U)
10353#define OTFDEC_REG_KEYR0_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos) /*!< 0xFFFFFFFF */
10354#define OTFDEC_REG_KEYR0 OTFDEC_REG_KEYR0_Msk /*!< Region Key Register (LSB key[31:0]) */
10355
10356/****************** Bit definition for OTFDEC_REG_KEYR1 register ***********/
10357#define OTFDEC_REG_KEYR1_Pos (0U)
10358#define OTFDEC_REG_KEYR1_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos) /*!< 0xFFFFFFFF */
10359#define OTFDEC_REG_KEYR1 OTFDEC_REG_KEYR1_Msk /*!< Region Key Register (key[63:32]) */
10360
10361/****************** Bit definition for OTFDEC_REG_KEYR2 register ***********/
10362#define OTFDEC_REG_KEYR2_Pos (0U)
10363#define OTFDEC_REG_KEYR2_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos) /*!< 0xFFFFFFFF */
10364#define OTFDEC_REG_KEYR2 OTFDEC_REG_KEYR2_Msk /*!< Region Key Register (key[95:64]) */
10365
10366/****************** Bit definition for OTFDEC_REG_KEYR3 register ***********/
10367#define OTFDEC_REG_KEYR3_Pos (0U)
10368#define OTFDEC_REG_KEYR3_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos) /*!< 0xFFFFFFFF */
10369#define OTFDEC_REG_KEYR3 OTFDEC_REG_KEYR3_Msk /*!< Region Key Register (key[127:96]) */
10370
10371/****************** Bit definition for OTFDEC_ISR register *****************/
10372#define OTFDEC_ISR_SEIF_Pos (0U)
10373#define OTFDEC_ISR_SEIF_Msk (0x1UL << OTFDEC_ISR_SEIF_Pos) /*!< 0x00000001 */
10374#define OTFDEC_ISR_SEIF OTFDEC_ISR_SEIF_Msk /*!< Security Error Interrupt Flag status bit before enable (mask) */
10375
10376#define OTFDEC_ISR_XONEIF_Pos (1U)
10377#define OTFDEC_ISR_XONEIF_Msk (0x1UL << OTFDEC_ISR_XONEIF_Pos) /*!< 0x00000002 */
10378#define OTFDEC_ISR_XONEIF OTFDEC_ISR_XONEIF_Msk /*!< Execute-only Error Interrupt Flag status bit before enable (mask) */
10379
10380#define OTFDEC_ISR_KEIF_Pos (2U)
10381#define OTFDEC_ISR_KEIF_Msk (0x1UL << OTFDEC_ISR_KEIF_Pos) /*!< 0x00000004 */
10382#define OTFDEC_ISR_KEIF OTFDEC_ISR_KEIF_Msk /*!< Key Error Interrupt Flag status bit before enable (mask) */
10383
10384/****************** Bit definition for OTFDEC_ICR register *****************/
10385#define OTFDEC_ICR_SEIF_Pos (0U)
10386#define OTFDEC_ICR_SEIF_Msk (0x1UL << OTFDEC_ICR_SEIF_Pos) /*!< 0x00000001 */
10387#define OTFDEC_ICR_SEIF OTFDEC_ICR_SEIF_Msk /*!< Security Error Interrupt Flag clear bit */
10388
10389#define OTFDEC_ICR_XONEIF_Pos (1U)
10390#define OTFDEC_ICR_XONEIF_Msk (0x1UL << OTFDEC_ICR_XONEIF_Pos) /*!< 0x00000002 */
10391#define OTFDEC_ICR_XONEIF OTFDEC_ICR_XONEIF_Msk /*!< Execute-only Error Interrupt Flag clear bit */
10392
10393#define OTFDEC_ICR_KEIF_Pos (2U)
10394#define OTFDEC_ICR_KEIF_Msk (0x1UL << OTFDEC_ICR_KEIF_Pos) /*!< 0x00000004 */
10395#define OTFDEC_ICR_KEIF OTFDEC_ICR_KEIF_Msk /*!< Key Error Interrupt Flag clear bit */
10396
10397/****************** Bit definition for OTFDEC_IER register *****************/
10398#define OTFDEC_IER_SEIE_Pos (0U)
10399#define OTFDEC_IER_SEIE_Msk (0x1UL << OTFDEC_IER_SEIE_Pos) /*!< 0x00000001 */
10400#define OTFDEC_IER_SEIE OTFDEC_IER_SEIE_Msk /*!< Security Error Interrupt Enable bit */
10401
10402#define OTFDEC_IER_XONEIE_Pos (1U)
10403#define OTFDEC_IER_XONEIE_Msk (0x1UL << OTFDEC_IER_XONEIE_Pos) /*!< 0x00000002 */
10404#define OTFDEC_IER_XONEIE OTFDEC_IER_XONEIE_Msk /*!< Execute-only Error Interrupt Enable bit */
10405
10406#define OTFDEC_IER_KEIE_Pos (2U)
10407#define OTFDEC_IER_KEIE_Msk (0x1UL << OTFDEC_IER_KEIE_Pos) /*!< 0x00000004 */
10408#define OTFDEC_IER_KEIE OTFDEC_IER_KEIE_Msk /*!< Key Error Interrupt Enable bit */
10409
10410/******************************************************************************/
10411/* */
10412/* Public Key Accelerator (PKA) */
10413/* */
10414/******************************************************************************/
10415
10416/******************* Bits definition for PKA_CR register **************/
10417#define PKA_CR_EN_Pos (0U)
10418#define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */
10419#define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */
10420#define PKA_CR_START_Pos (1U)
10421#define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */
10422#define PKA_CR_START PKA_CR_START_Msk /*!< Start operation */
10423#define PKA_CR_MODE_Pos (8U)
10424#define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */
10425#define PKA_CR_MODE PKA_CR_MODE_Msk /*!< MODE[5:0] PKA operation code */
10426#define PKA_CR_MODE_0 (0x01UL << PKA_CR_MODE_Pos) /*!< 0x00000100 */
10427#define PKA_CR_MODE_1 (0x02UL << PKA_CR_MODE_Pos) /*!< 0x00000200 */
10428#define PKA_CR_MODE_2 (0x04UL << PKA_CR_MODE_Pos) /*!< 0x00000400 */
10429#define PKA_CR_MODE_3 (0x08UL << PKA_CR_MODE_Pos) /*!< 0x00000800 */
10430#define PKA_CR_MODE_4 (0x10UL << PKA_CR_MODE_Pos) /*!< 0x00001000 */
10431#define PKA_CR_MODE_5 (0x20UL << PKA_CR_MODE_Pos) /*!< 0x00002000 */
10432#define PKA_CR_PROCENDIE_Pos (17U)
10433#define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */
10434#define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */
10435#define PKA_CR_RAMERRIE_Pos (19U)
10436#define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */
10437#define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */
10438#define PKA_CR_ADDRERRIE_Pos (20U)
10439#define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */
10440#define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< RAM error interrupt enable */
10441
10442/******************* Bits definition for PKA_SR register **************/
10443#define PKA_SR_BUSY_Pos (16U)
10444#define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */
10445#define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< PKA operation is in progress */
10446#define PKA_SR_PROCENDF_Pos (17U)
10447#define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */
10448#define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */
10449#define PKA_SR_RAMERRF_Pos (19U)
10450#define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */
10451#define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */
10452#define PKA_SR_ADDRERRF_Pos (20U)
10453#define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */
10454#define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */
10455
10456/******************* Bits definition for PKA_CLRFR register **************/
10457#define PKA_CLRFR_PROCENDFC_Pos (17U)
10458#define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */
10459#define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */
10460#define PKA_CLRFR_RAMERRFC_Pos (19U)
10461#define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */
10462#define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */
10463#define PKA_CLRFR_ADDRERRFC_Pos (20U)
10464#define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */
10465#define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */
10466
10467/******************* Bits definition for PKA RAM *************************/
10468#define PKA_RAM_OFFSET 0x0400UL /*!< PKA RAM address offset */
10469
10470/* Compute Montgomery parameter input data */
10471#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
10472#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x0D5CUL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
10473
10474/* Compute Montgomery parameter output data */
10475#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0594UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */
10476
10477/* Compute modular exponentiation input data */
10478#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */
10479#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
10480#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0594UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
10481#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */
10482#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */
10483#define PKA_MODULAR_EXP_IN_MODULUS ((0x0D5CUL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
10484
10485/* Compute modular exponentiation output data */
10486#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0594UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */
10487#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x0724UL - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 1 */
10488#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x08B4UL - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 2 */
10489#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */
10490#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0x0E3CUL - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 3 */
10491
10492/* Compute ECC scalar multiplication input data */
10493#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */
10494#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
10495#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
10496#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x040CUL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
10497#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x0460UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
10498#define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x04B4UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
10499#define PKA_ECC_SCALAR_MUL_IN_K ((0x0508UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */
10500#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x055CUL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
10501#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x05B0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
10502
10503/* Compute ECC scalar multiplication output data */
10504#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x055CUL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */
10505#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05B0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */
10506#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0x0DE8UL - PKA_RAM_OFFSET)>>2) /*!< Output last double X1 coordinate */
10507#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0x0E3CUL - PKA_RAM_OFFSET)>>2) /*!< Output last double Y1 coordinate */
10508#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0x0E90UL - PKA_RAM_OFFSET)>>2) /*!< Output last double Z1 coordinate */
10509#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0x0EE4UL - PKA_RAM_OFFSET)>>2) /*!< Output check point X2 coordinate */
10510#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0x0F38UL - PKA_RAM_OFFSET)>>2) /*!< Output check point Y2 coordinate */
10511#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0x0F8CUL - PKA_RAM_OFFSET)>>2) /*!< Output check point Z2 coordinate */
10512
10513/* Point check input data */
10514#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
10515#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
10516#define PKA_POINT_CHECK_IN_A_COEFF ((0x040CUL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
10517#define PKA_POINT_CHECK_IN_B_COEFF ((0x07FCUL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */
10518#define PKA_POINT_CHECK_IN_MOD_GF ((0x0460UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
10519#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x055CUL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
10520#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05B0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
10521
10522/* Point check output data */
10523#define PKA_POINT_CHECK_OUT_ERROR ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Output error */
10524
10525/* ECDSA signature input data */
10526#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */
10527#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
10528#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
10529#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x040CUL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
10530#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x0460UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
10531#define PKA_ECDSA_SIGN_IN_K ((0x0508UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */
10532#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x055CUL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
10533#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x05B0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
10534#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0DE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */
10535#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0E3CUL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */
10536#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0E94UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
10537
10538/* ECDSA signature output data */
10539#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0EE8UL - PKA_RAM_OFFSET)>>2) /*!< Output error */
10540#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0700UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */
10541#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0754UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */
10542#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CUL - PKA_RAM_OFFSET)>>2) /*!< Output final point kP X coordinate */
10543#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090UL - PKA_RAM_OFFSET)>>2) /*!< Output final point kP Y coordinate */
10544
10545/* ECDSA verification input data */
10546#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */
10547#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04B4UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
10548#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x045CUL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
10549#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0460UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
10550#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04B8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
10551#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x05E8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
10552#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x063CUL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
10553#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x0F40UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */
10554#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x0F94UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */
10555#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */
10556#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */
10557#define PKA_ECDSA_VERIF_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */
10558#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x0D5CUL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
10559
10560/* ECDSA verification output data */
10561#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05B0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
10562
10563/* RSA CRT exponentiation input data */
10564#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */
10565#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x065CUL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */
10566#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */
10567#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x07ECUL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */
10568#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x097CUL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */
10569#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x0D5CUL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */
10570#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x0EECUL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */
10571
10572/* RSA CRT exponentiation output data */
10573#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0724UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
10574
10575/* Modular reduction input data */
10576#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */
10577#define PKA_MODULAR_REDUC_IN_OPERAND ((0x08B4UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */
10578#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */
10579#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
10580
10581/* Modular reduction output data */
10582#define PKA_MODULAR_REDUC_OUT_RESULT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
10583
10584/* Arithmetic addition input data */
10585#define PKA_ARITHMETIC_ADD_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
10586#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x08B4UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
10587#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
10588
10589/* Arithmetic addition output data */
10590#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
10591
10592/* Arithmetic substraction input data */
10593#define PKA_ARITHMETIC_SUB_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
10594#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x08B4UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
10595#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
10596
10597/* Arithmetic substraction output data */
10598#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
10599
10600/* Arithmetic multiplication input data */
10601#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
10602#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x08B4UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
10603#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
10604
10605/* Arithmetic multiplication output data */
10606#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
10607
10608/* Comparison input data */
10609#define PKA_COMPARISON_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
10610#define PKA_COMPARISON_IN_OP1 ((0x08B4UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
10611#define PKA_COMPARISON_IN_OP2 ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
10612
10613/* Comparison output data */
10614#define PKA_COMPARISON_OUT_RESULT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
10615
10616/* Modular addition input data */
10617#define PKA_MODULAR_ADD_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
10618#define PKA_MODULAR_ADD_IN_OP1 ((0x08B4UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
10619#define PKA_MODULAR_ADD_IN_OP2 ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
10620#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x0D5CUL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */
10621
10622/* Modular addition output data */
10623#define PKA_MODULAR_ADD_OUT_RESULT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
10624
10625/* Modular inversion input data */
10626#define PKA_MODULAR_INV_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
10627#define PKA_MODULAR_INV_IN_OP1 ((0x08B4UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
10628#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */
10629
10630/* Modular inversion output data */
10631#define PKA_MODULAR_INV_OUT_RESULT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
10632
10633/* Modular substraction input data */
10634#define PKA_MODULAR_SUB_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
10635#define PKA_MODULAR_SUB_IN_OP1 ((0x08B4UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
10636#define PKA_MODULAR_SUB_IN_OP2 ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
10637#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x0D5CUL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */
10638
10639/* Modular substraction output data */
10640#define PKA_MODULAR_SUB_OUT_RESULT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
10641
10642/* Montgomery multiplication input data */
10643#define PKA_MONTGOMERY_MUL_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
10644#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x08B4UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
10645#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
10646#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x0D5CUL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
10647
10648/* Montgomery multiplication output data */
10649#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
10650
10651/* Generic Arithmetic input data */
10652#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
10653#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x08B4UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
10654#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
10655#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x0D5CUL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
10656
10657/* Generic Arithmetic output data */
10658#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
10659
10660
10661/******************************************************************************/
10662/* */
10663/* Power Control */
10664/* */
10665/******************************************************************************/
10666/******************** Bit definition for PWR_CR1 register ********************/
10667#define PWR_CR1_LPMS_Pos (0U)
10668#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
10669#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
10670#define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
10671#define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
10672#define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
10673
10674#define PWR_CR1_LPMS_STOP0 (0UL) /*!< Stop 0 mode */
10675#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_0 /*!< Stop 1 mode */
10676#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_1 /*!< Stop 2 mode */
10677#define PWR_CR1_LPMS_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0) /*!< Stand-by mode */
10678#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_2 /*!< Shut-down mode */
10679
10680#define PWR_CR1_DBP_Pos (8U)
10681#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
10682#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
10683
10684#define PWR_CR1_VOS_Pos (9U)
10685#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x0000C000 */
10686#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
10687#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00004000 */
10688#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00008000 */
10689
10690#define PWR_CR1_LPR_Pos (14U)
10691#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
10692#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
10693
10694/******************** Bit definition for PWR_CR2 register ********************/
10695#define PWR_CR2_PVDE_Pos (0U)
10696#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
10697#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
10698#define PWR_CR2_PLS_Pos (1U)
10699#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
10700#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
10701#define PWR_CR2_PLS_0 (0x1UL << PWR_CR2_PLS_Pos) /*!< 0x00000002 */
10702#define PWR_CR2_PLS_1 (0x2UL << PWR_CR2_PLS_Pos) /*!< 0x00000004 */
10703#define PWR_CR2_PLS_2 (0x4UL << PWR_CR2_PLS_Pos) /*!< 0x00000008 */
10704
10705#define PWR_CR2_PLS_LEV0 (0UL) /*!< PVD level 0 */
10706#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_0 /*!< PVD level 1 */
10707#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_1 /*!< PVD level 2 */
10708#define PWR_CR2_PLS_LEV3 (PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /*!< PVD level 3 */
10709#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_2 /*!< PVD level 4 */
10710#define PWR_CR2_PLS_LEV5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0) /*!< PVD level 5 */
10711#define PWR_CR2_PLS_LEV6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1) /*!< PVD level 6 */
10712#define PWR_CR2_PLS_LEV7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /*!< PVD level 7 */
10713
10714#define PWR_CR2_PVME_Pos (4U)
10715#define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
10716#define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
10717#define PWR_CR2_PVME1_Pos (4U)
10718#define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
10719#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
10720#define PWR_CR2_PVME2_Pos (5U)
10721#define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
10722#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
10723#define PWR_CR2_PVME3_Pos (6U)
10724#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
10725#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
10726#define PWR_CR2_PVME4_Pos (7U)
10727#define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
10728#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
10729
10730#define PWR_CR2_IOSV_Pos (9U)
10731#define PWR_CR2_IOSV_Msk (0x1UL << PWR_CR2_IOSV_Pos) /*!< 0x00000200 */
10732#define PWR_CR2_IOSV PWR_CR2_IOSV_Msk /*!< VDD IO2 independent I/Os Supply Valid */
10733#define PWR_CR2_USV_Pos (10U)
10734#define PWR_CR2_USV_Msk (0x1UL << PWR_CR2_USV_Pos) /*!< 0x00000400 */
10735#define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */
10736
10737/******************** Bit definition for PWR_CR3 register ********************/
10738#define PWR_CR3_EWUP_Pos (0U)
10739#define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
10740#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
10741#define PWR_CR3_EWUP1_Pos (0U)
10742#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
10743#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
10744#define PWR_CR3_EWUP2_Pos (1U)
10745#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
10746#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
10747#define PWR_CR3_EWUP3_Pos (2U)
10748#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
10749#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
10750#define PWR_CR3_EWUP4_Pos (3U)
10751#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
10752#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
10753#define PWR_CR3_EWUP5_Pos (4U)
10754#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
10755#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
10756
10757#define PWR_CR3_RRS_Pos (8U)
10758#define PWR_CR3_RRS_Msk (0x3UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
10759#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< RRS[1:0] bits (Ram retention in STANDBY mode)*/
10760#define PWR_CR3_RRS_0 (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
10761#define PWR_CR3_RRS_1 (0x2UL << PWR_CR3_RRS_Pos) /*!< 0x00000200 */
10762
10763#define PWR_CR3_APC_Pos (10U)
10764#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
10765#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
10766#define PWR_CR3_ULPMEN_Pos (11U)
10767#define PWR_CR3_ULPMEN_Msk (0x1UL << PWR_CR3_ULPMEN_Pos) /*!< 0x00000800 */
10768#define PWR_CR3_ULPMEN PWR_CR3_ULPMEN_Msk /*!< Ultra Low Power Mode Enable */
10769#define PWR_CR3_UCPD_STDBY_Pos (13U)
10770#define PWR_CR3_UCPD_STDBY_Msk (0x1UL << PWR_CR3_UCPD_STDBY_Pos) /*!< 0x00002000 */
10771#define PWR_CR3_UCPD_STDBY PWR_CR3_UCPD_STDBY_Msk /*!< UCPD Configuration memorize when enter in STANDBY */
10772#define PWR_CR3_UCPD_DBDIS_Pos (14U)
10773#define PWR_CR3_UCPD_DBDIS_Msk (0x1UL << PWR_CR3_UCPD_DBDIS_Pos) /*!< 0x00004000 */
10774#define PWR_CR3_UCPD_DBDIS PWR_CR3_UCPD_DBDIS_Msk /*!< Dead Battery Behavior Disable */
10775
10776/******************** Bit definition for PWR_CR4 register ********************/
10777#define PWR_CR4_WUPP1_Pos (0U)
10778#define PWR_CR4_WUPP1_Msk (0x1UL << PWR_CR4_WUPP1_Pos) /*!< 0x00000001 */
10779#define PWR_CR4_WUPP1 PWR_CR4_WUPP1_Msk /*!< Wake-Up Pin 1 polarity */
10780#define PWR_CR4_WUPP2_Pos (1U)
10781#define PWR_CR4_WUPP2_Msk (0x1UL << PWR_CR4_WUPP2_Pos) /*!< 0x00000002 */
10782#define PWR_CR4_WUPP2 PWR_CR4_WUPP2_Msk /*!< Wake-Up Pin 2 polarity */
10783#define PWR_CR4_WUPP3_Pos (2U)
10784#define PWR_CR4_WUPP3_Msk (0x1UL << PWR_CR4_WUPP3_Pos) /*!< 0x00000004 */
10785#define PWR_CR4_WUPP3 PWR_CR4_WUPP3_Msk /*!< Wake-Up Pin 3 polarity */
10786#define PWR_CR4_WUPP4_Pos (3U)
10787#define PWR_CR4_WUPP4_Msk (0x1UL << PWR_CR4_WUPP4_Pos) /*!< 0x00000008 */
10788#define PWR_CR4_WUPP4 PWR_CR4_WUPP4_Msk /*!< Wake-Up Pin 4 polarity */
10789#define PWR_CR4_WUPP5_Pos (4U)
10790#define PWR_CR4_WUPP5_Msk (0x1UL << PWR_CR4_WUPP5_Pos) /*!< 0x00000010 */
10791#define PWR_CR4_WUPP5 PWR_CR4_WUPP5_Msk /*!< Wake-Up Pin 5 polarity */
10792#define PWR_CR4_VBE_Pos (8U)
10793#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
10794#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
10795#define PWR_CR4_VBRS_Pos (9U)
10796#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
10797#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
10798#define PWR_CR4_SMPSBYP_Pos (12U)
10799#define PWR_CR4_SMPSBYP_Msk (0x1UL << PWR_CR4_SMPSBYP_Pos) /*!< 0x00001000 */
10800#define PWR_CR4_SMPSBYP PWR_CR4_SMPSBYP_Msk /*!< SMPS Bypass mode */
10801#define PWR_CR4_EXTSMPSEN_Pos (13U)
10802#define PWR_CR4_EXTSMPSEN_Msk (0x1UL << PWR_CR4_EXTSMPSEN_Pos) /*!< 0x00002000 */
10803#define PWR_CR4_EXTSMPSEN PWR_CR4_EXTSMPSEN_Msk /*!< External SMPS mode */
10804#define PWR_CR4_SMPSFSTEN_Pos (14U)
10805#define PWR_CR4_SMPSFSTEN_Msk (0x1UL << PWR_CR4_SMPSFSTEN_Pos) /*!< 0x00004000 */
10806#define PWR_CR4_SMPSFSTEN PWR_CR4_SMPSFSTEN_Msk /*!< SMPS fast soft start */
10807#define PWR_CR4_SMPSLPEN_Pos (15U)
10808#define PWR_CR4_SMPSLPEN_Msk (0x1UL << PWR_CR4_SMPSLPEN_Pos) /*!< 0x00008000 */
10809#define PWR_CR4_SMPSLPEN PWR_CR4_SMPSLPEN_Msk /*!< SMPS low-power mode */
10810
10811/******************** Bit definition for PWR_SR1 register ********************/
10812#define PWR_SR1_WUF_Pos (0U)
10813#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
10814#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
10815#define PWR_SR1_WUF1_Pos (0U)
10816#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
10817#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
10818#define PWR_SR1_WUF2_Pos (1U)
10819#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
10820#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
10821#define PWR_SR1_WUF3_Pos (2U)
10822#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
10823#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
10824#define PWR_SR1_WUF4_Pos (3U)
10825#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
10826#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
10827#define PWR_SR1_WUF5_Pos (4U)
10828#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
10829#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
10830#define PWR_SR1_SBF_Pos (8U)
10831#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
10832#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
10833#define PWR_SR1_SMPSBYPRDY_Pos (12U)
10834#define PWR_SR1_SMPSBYPRDY_Msk (0x1UL << PWR_SR1_SMPSBYPRDY_Pos) /*!< 0x00001000 */
10835#define PWR_SR1_SMPSBYPRDY PWR_SR1_SMPSBYPRDY_Msk /*!< SMPS Bypass ready */
10836#define PWR_SR1_EXTSMPSRDY_Pos (13U)
10837#define PWR_SR1_EXTSMPSRDY_Msk (0x1UL << PWR_SR1_EXTSMPSRDY_Pos) /*!< 0x00002000 */
10838#define PWR_SR1_EXTSMPSRDY PWR_SR1_EXTSMPSRDY_Msk /*!< External SMPS mode ready */
10839#define PWR_SR1_SMPSHPRDY_Pos (15U)
10840#define PWR_SR1_SMPSHPRDY_Msk (0x1UL << PWR_SR1_SMPSHPRDY_Pos) /*!< 0x00008000 */
10841#define PWR_SR1_SMPSHPRDY PWR_SR1_SMPSHPRDY_Msk /*!< SMPS High-power mode ready */
10842
10843/******************** Bit definition for PWR_SR2 register ********************/
10844#define PWR_SR2_REGLPS_Pos (8U)
10845#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
10846#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
10847#define PWR_SR2_REGLPF_Pos (9U)
10848#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
10849#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
10850#define PWR_SR2_VOSF_Pos (10U)
10851#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
10852#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
10853#define PWR_SR2_PVDO_Pos (11U)
10854#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
10855#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
10856#define PWR_SR2_PVMO1_Pos (12U)
10857#define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
10858#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
10859#define PWR_SR2_PVMO2_Pos (13U)
10860#define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
10861#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
10862#define PWR_SR2_PVMO3_Pos (14U)
10863#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
10864#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
10865#define PWR_SR2_PVMO4_Pos (15U)
10866#define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
10867#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
10868
10869/******************** Bit definition for PWR_SCR register ********************/
10870#define PWR_SCR_CWUF_Pos (0U)
10871#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
10872#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
10873#define PWR_SCR_CWUF1_Pos (0U)
10874#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
10875#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
10876#define PWR_SCR_CWUF2_Pos (1U)
10877#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
10878#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
10879#define PWR_SCR_CWUF3_Pos (2U)
10880#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
10881#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
10882#define PWR_SCR_CWUF4_Pos (3U)
10883#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
10884#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
10885#define PWR_SCR_CWUF5_Pos (4U)
10886#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
10887#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
10888#define PWR_SCR_CSBF_Pos (8U)
10889#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
10890#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
10891
10892/******************** Bit definition for PWR_PUCRA register ********************/
10893#define PWR_PUCRA_PU0_Pos (0U)
10894#define PWR_PUCRA_PU0_Msk (0x1UL << PWR_PUCRA_PU0_Pos) /*!< 0x00000001 */
10895#define PWR_PUCRA_PU0 PWR_PUCRA_PU0_Msk /*!< Port PA0 Pull-Up set */
10896#define PWR_PUCRA_PU1_Pos (1U)
10897#define PWR_PUCRA_PU1_Msk (0x1UL << PWR_PUCRA_PU1_Pos) /*!< 0x00000002 */
10898#define PWR_PUCRA_PU1 PWR_PUCRA_PU1_Msk /*!< Port PA1 Pull-Up set */
10899#define PWR_PUCRA_PU2_Pos (2U)
10900#define PWR_PUCRA_PU2_Msk (0x1UL << PWR_PUCRA_PU2_Pos) /*!< 0x00000004 */
10901#define PWR_PUCRA_PU2 PWR_PUCRA_PU2_Msk /*!< Port PA2 Pull-Up set */
10902#define PWR_PUCRA_PU3_Pos (3U)
10903#define PWR_PUCRA_PU3_Msk (0x1UL << PWR_PUCRA_PU3_Pos) /*!< 0x00000008 */
10904#define PWR_PUCRA_PU3 PWR_PUCRA_PU3_Msk /*!< Port PA3 Pull-Up set */
10905#define PWR_PUCRA_PU4_Pos (4U)
10906#define PWR_PUCRA_PU4_Msk (0x1UL << PWR_PUCRA_PU4_Pos) /*!< 0x00000010 */
10907#define PWR_PUCRA_PU4 PWR_PUCRA_PU4_Msk /*!< Port PA4 Pull-Up set */
10908#define PWR_PUCRA_PU5_Pos (5U)
10909#define PWR_PUCRA_PU5_Msk (0x1UL << PWR_PUCRA_PU5_Pos) /*!< 0x00000020 */
10910#define PWR_PUCRA_PU5 PWR_PUCRA_PU5_Msk /*!< Port PA5 Pull-Up set */
10911#define PWR_PUCRA_PU6_Pos (6U)
10912#define PWR_PUCRA_PU6_Msk (0x1UL << PWR_PUCRA_PU6_Pos) /*!< 0x00000040 */
10913#define PWR_PUCRA_PU6 PWR_PUCRA_PU6_Msk /*!< Port PA6 Pull-Up set */
10914#define PWR_PUCRA_PU7_Pos (7U)
10915#define PWR_PUCRA_PU7_Msk (0x1UL << PWR_PUCRA_PU7_Pos) /*!< 0x00000080 */
10916#define PWR_PUCRA_PU7 PWR_PUCRA_PU7_Msk /*!< Port PA7 Pull-Up set */
10917#define PWR_PUCRA_PU8_Pos (8U)
10918#define PWR_PUCRA_PU8_Msk (0x1UL << PWR_PUCRA_PU8_Pos) /*!< 0x00000100 */
10919#define PWR_PUCRA_PU8 PWR_PUCRA_PU8_Msk /*!< Port PA8 Pull-Up set */
10920#define PWR_PUCRA_PU9_Pos (9U)
10921#define PWR_PUCRA_PU9_Msk (0x1UL << PWR_PUCRA_PU9_Pos) /*!< 0x00000200 */
10922#define PWR_PUCRA_PU9 PWR_PUCRA_PU9_Msk /*!< Port PA9 Pull-Up set */
10923#define PWR_PUCRA_PU10_Pos (10U)
10924#define PWR_PUCRA_PU10_Msk (0x1UL << PWR_PUCRA_PU10_Pos) /*!< 0x00000400 */
10925#define PWR_PUCRA_PU10 PWR_PUCRA_PU10_Msk /*!< Port PA10 Pull-Up set */
10926#define PWR_PUCRA_PU11_Pos (11U)
10927#define PWR_PUCRA_PU11_Msk (0x1UL << PWR_PUCRA_PU11_Pos) /*!< 0x00000800 */
10928#define PWR_PUCRA_PU11 PWR_PUCRA_PU11_Msk /*!< Port PA11 Pull-Up set */
10929#define PWR_PUCRA_PU12_Pos (12U)
10930#define PWR_PUCRA_PU12_Msk (0x1UL << PWR_PUCRA_PU12_Pos) /*!< 0x00001000 */
10931#define PWR_PUCRA_PU12 PWR_PUCRA_PU12_Msk /*!< Port PA12 Pull-Up set */
10932#define PWR_PUCRA_PU13_Pos (13U)
10933#define PWR_PUCRA_PU13_Msk (0x1UL << PWR_PUCRA_PU13_Pos) /*!< 0x00002000 */
10934#define PWR_PUCRA_PU13 PWR_PUCRA_PU13_Msk /*!< Port PA13 Pull-Up set */
10935#define PWR_PUCRA_PU14_Pos (14U)
10936#define PWR_PUCRA_PU14_Msk (0x1UL << PWR_PUCRA_PU14_Pos) /*!< 0x00004000 */
10937#define PWR_PUCRA_PU14 PWR_PUCRA_PU14_Msk /*!< Port PA14 Pull-Up set */
10938#define PWR_PUCRA_PU15_Pos (15U)
10939#define PWR_PUCRA_PU15_Msk (0x1UL << PWR_PUCRA_PU15_Pos) /*!< 0x00008000 */
10940#define PWR_PUCRA_PU15 PWR_PUCRA_PU15_Msk /*!< Port PA15 Pull-Up set */
10941
10942/******************** Bit definition for PWR_PDCRA register ********************/
10943#define PWR_PDCRA_PD0_Pos (0U)
10944#define PWR_PDCRA_PD0_Msk (0x1UL << PWR_PDCRA_PD0_Pos) /*!< 0x00000001 */
10945#define PWR_PDCRA_PD0 PWR_PDCRA_PD0_Msk /*!< Port PA0 Pull-Down set */
10946#define PWR_PDCRA_PD1_Pos (1U)
10947#define PWR_PDCRA_PD1_Msk (0x1UL << PWR_PDCRA_PD1_Pos) /*!< 0x00000002 */
10948#define PWR_PDCRA_PD1 PWR_PDCRA_PD1_Msk /*!< Port PA1 Pull-Down set */
10949#define PWR_PDCRA_PD2_Pos (2U)
10950#define PWR_PDCRA_PD2_Msk (0x1UL << PWR_PDCRA_PD2_Pos) /*!< 0x00000004 */
10951#define PWR_PDCRA_PD2 PWR_PDCRA_PD2_Msk /*!< Port PA2 Pull-Down set */
10952#define PWR_PDCRA_PD3_Pos (3U)
10953#define PWR_PDCRA_PD3_Msk (0x1UL << PWR_PDCRA_PD3_Pos) /*!< 0x00000008 */
10954#define PWR_PDCRA_PD3 PWR_PDCRA_PD3_Msk /*!< Port PA3 Pull-Down set */
10955#define PWR_PDCRA_PD4_Pos (4U)
10956#define PWR_PDCRA_PD4_Msk (0x1UL << PWR_PDCRA_PD4_Pos) /*!< 0x00000010 */
10957#define PWR_PDCRA_PD4 PWR_PDCRA_PD4_Msk /*!< Port PA4 Pull-Down set */
10958#define PWR_PDCRA_PD5_Pos (5U)
10959#define PWR_PDCRA_PD5_Msk (0x1UL << PWR_PDCRA_PD5_Pos) /*!< 0x00000020 */
10960#define PWR_PDCRA_PD5 PWR_PDCRA_PD5_Msk /*!< Port PA5 Pull-Down set */
10961#define PWR_PDCRA_PD6_Pos (6U)
10962#define PWR_PDCRA_PD6_Msk (0x1UL << PWR_PDCRA_PD6_Pos) /*!< 0x00000040 */
10963#define PWR_PDCRA_PD6 PWR_PDCRA_PD6_Msk /*!< Port PA6 Pull-Down set */
10964#define PWR_PDCRA_PD7_Pos (7U)
10965#define PWR_PDCRA_PD7_Msk (0x1UL << PWR_PDCRA_PD7_Pos) /*!< 0x00000080 */
10966#define PWR_PDCRA_PD7 PWR_PDCRA_PD7_Msk /*!< Port PA7 Pull-Down set */
10967#define PWR_PDCRA_PD8_Pos (8U)
10968#define PWR_PDCRA_PD8_Msk (0x1UL << PWR_PDCRA_PD8_Pos) /*!< 0x00000100 */
10969#define PWR_PDCRA_PD8 PWR_PDCRA_PD8_Msk /*!< Port PA8 Pull-Down set */
10970#define PWR_PDCRA_PD9_Pos (9U)
10971#define PWR_PDCRA_PD9_Msk (0x1UL << PWR_PDCRA_PD9_Pos) /*!< 0x00000200 */
10972#define PWR_PDCRA_PD9 PWR_PDCRA_PD9_Msk /*!< Port PA9 Pull-Down set */
10973#define PWR_PDCRA_PD10_Pos (10U)
10974#define PWR_PDCRA_PD10_Msk (0x1UL << PWR_PDCRA_PD10_Pos) /*!< 0x00000400 */
10975#define PWR_PDCRA_PD10 PWR_PDCRA_PD10_Msk /*!< Port PA10 Pull-Down set */
10976#define PWR_PDCRA_PD11_Pos (11U)
10977#define PWR_PDCRA_PD11_Msk (0x1UL << PWR_PDCRA_PD11_Pos) /*!< 0x00000800 */
10978#define PWR_PDCRA_PD11 PWR_PDCRA_PD11_Msk /*!< Port PA11 Pull-Down set */
10979#define PWR_PDCRA_PD12_Pos (12U)
10980#define PWR_PDCRA_PD12_Msk (0x1UL << PWR_PDCRA_PD12_Pos) /*!< 0x00001000 */
10981#define PWR_PDCRA_PD12 PWR_PDCRA_PD12_Msk /*!< Port PA12 Pull-Down set */
10982#define PWR_PDCRA_PD13_Pos (13U)
10983#define PWR_PDCRA_PD13_Msk (0x1UL << PWR_PDCRA_PD13_Pos) /*!< 0x00002000 */
10984#define PWR_PDCRA_PD13 PWR_PDCRA_PD13_Msk /*!< Port PA13 Pull-Down set */
10985#define PWR_PDCRA_PD14_Pos (14U)
10986#define PWR_PDCRA_PD14_Msk (0x1UL << PWR_PDCRA_PD14_Pos) /*!< 0x00004000 */
10987#define PWR_PDCRA_PD14 PWR_PDCRA_PD14_Msk /*!< Port PA14 Pull-Down set */
10988#define PWR_PDCRA_PD15_Pos (15U)
10989#define PWR_PDCRA_PD15_Msk (0x1UL << PWR_PDCRA_PD15_Pos) /*!< 0x00008000 */
10990#define PWR_PDCRA_PD15 PWR_PDCRA_PD15_Msk /*!< Port PA15 Pull-Down set */
10991
10992/******************** Bit definition for PWR_PUCRB register ********************/
10993#define PWR_PUCRB_PU0_Pos (0U)
10994#define PWR_PUCRB_PU0_Msk (0x1UL << PWR_PUCRB_PU0_Pos) /*!< 0x00000001 */
10995#define PWR_PUCRB_PU0 PWR_PUCRB_PU0_Msk /*!< Port PB0 Pull-Up set */
10996#define PWR_PUCRB_PU1_Pos (1U)
10997#define PWR_PUCRB_PU1_Msk (0x1UL << PWR_PUCRB_PU1_Pos) /*!< 0x00000002 */
10998#define PWR_PUCRB_PU1 PWR_PUCRB_PU1_Msk /*!< Port PB1 Pull-Up set */
10999#define PWR_PUCRB_PU2_Pos (2U)
11000#define PWR_PUCRB_PU2_Msk (0x1UL << PWR_PUCRB_PU2_Pos) /*!< 0x00000004 */
11001#define PWR_PUCRB_PU2 PWR_PUCRB_PU2_Msk /*!< Port PB2 Pull-Up set */
11002#define PWR_PUCRB_PU3_Pos (3U)
11003#define PWR_PUCRB_PU3_Msk (0x1UL << PWR_PUCRB_PU3_Pos) /*!< 0x00000008 */
11004#define PWR_PUCRB_PU3 PWR_PUCRB_PU3_Msk /*!< Port PB3 Pull-Up set */
11005#define PWR_PUCRB_PU4_Pos (4U)
11006#define PWR_PUCRB_PU4_Msk (0x1UL << PWR_PUCRB_PU4_Pos) /*!< 0x00000010 */
11007#define PWR_PUCRB_PU4 PWR_PUCRB_PU4_Msk /*!< Port PB4 Pull-Up set */
11008#define PWR_PUCRB_PU5_Pos (5U)
11009#define PWR_PUCRB_PU5_Msk (0x1UL << PWR_PUCRB_PU5_Pos) /*!< 0x00000020 */
11010#define PWR_PUCRB_PU5 PWR_PUCRB_PU5_Msk /*!< Port PB5 Pull-Up set */
11011#define PWR_PUCRB_PU6_Pos (6U)
11012#define PWR_PUCRB_PU6_Msk (0x1UL << PWR_PUCRB_PU6_Pos) /*!< 0x00000040 */
11013#define PWR_PUCRB_PU6 PWR_PUCRB_PU6_Msk /*!< Port PB6 Pull-Up set */
11014#define PWR_PUCRB_PU7_Pos (7U)
11015#define PWR_PUCRB_PU7_Msk (0x1UL << PWR_PUCRB_PU7_Pos) /*!< 0x00000080 */
11016#define PWR_PUCRB_PU7 PWR_PUCRB_PU7_Msk /*!< Port PB7 Pull-Up set */
11017#define PWR_PUCRB_PU8_Pos (8U)
11018#define PWR_PUCRB_PU8_Msk (0x1UL << PWR_PUCRB_PU8_Pos) /*!< 0x00000100 */
11019#define PWR_PUCRB_PU8 PWR_PUCRB_PU8_Msk /*!< Port PB8 Pull-Up set */
11020#define PWR_PUCRB_PU9_Pos (9U)
11021#define PWR_PUCRB_PU9_Msk (0x1UL << PWR_PUCRB_PU9_Pos) /*!< 0x00000200 */
11022#define PWR_PUCRB_PU9 PWR_PUCRB_PU9_Msk /*!< Port PB9 Pull-Up set */
11023#define PWR_PUCRB_PU10_Pos (10U)
11024#define PWR_PUCRB_PU10_Msk (0x1UL << PWR_PUCRB_PU10_Pos) /*!< 0x00000400 */
11025#define PWR_PUCRB_PU10 PWR_PUCRB_PU10_Msk /*!< Port PB10 Pull-Up set */
11026#define PWR_PUCRB_PU11_Pos (11U)
11027#define PWR_PUCRB_PU11_Msk (0x1UL << PWR_PUCRB_PU11_Pos) /*!< 0x00000800 */
11028#define PWR_PUCRB_PU11 PWR_PUCRB_PU11_Msk /*!< Port PB11 Pull-Up set */
11029#define PWR_PUCRB_PU12_Pos (12U)
11030#define PWR_PUCRB_PU12_Msk (0x1UL << PWR_PUCRB_PU12_Pos) /*!< 0x00001000 */
11031#define PWR_PUCRB_PU12 PWR_PUCRB_PU12_Msk /*!< Port PB12 Pull-Up set */
11032#define PWR_PUCRB_PU13_Pos (13U)
11033#define PWR_PUCRB_PU13_Msk (0x1UL << PWR_PUCRB_PU13_Pos) /*!< 0x00002000 */
11034#define PWR_PUCRB_PU13 PWR_PUCRB_PU13_Msk /*!< Port PB13 Pull-Up set */
11035#define PWR_PUCRB_PU14_Pos (14U)
11036#define PWR_PUCRB_PU14_Msk (0x1UL << PWR_PUCRB_PU14_Pos) /*!< 0x00004000 */
11037#define PWR_PUCRB_PU14 PWR_PUCRB_PU14_Msk /*!< Port PB14 Pull-Up set */
11038#define PWR_PUCRB_PU15_Pos (15U)
11039#define PWR_PUCRB_PU15_Msk (0x1UL << PWR_PUCRB_PU15_Pos) /*!< 0x00008000 */
11040#define PWR_PUCRB_PU15 PWR_PUCRB_PU15_Msk /*!< Port PB15 Pull-Up set */
11041
11042/******************** Bit definition for PWR_PDCRB register ********************/
11043#define PWR_PDCRB_PD0_Pos (0U)
11044#define PWR_PDCRB_PD0_Msk (0x1UL << PWR_PDCRB_PD0_Pos) /*!< 0x00000001 */
11045#define PWR_PDCRB_PD0 PWR_PDCRB_PD0_Msk /*!< Port PB0 Pull-Down set */
11046#define PWR_PDCRB_PD1_Pos (1U)
11047#define PWR_PDCRB_PD1_Msk (0x1UL << PWR_PDCRB_PD1_Pos) /*!< 0x00000002 */
11048#define PWR_PDCRB_PD1 PWR_PDCRB_PD1_Msk /*!< Port PB1 Pull-Down set */
11049#define PWR_PDCRB_PD2_Pos (2U)
11050#define PWR_PDCRB_PD2_Msk (0x1UL << PWR_PDCRB_PD2_Pos) /*!< 0x00000004 */
11051#define PWR_PDCRB_PD2 PWR_PDCRB_PD2_Msk /*!< Port PB2 Pull-Down set */
11052#define PWR_PDCRB_PD3_Pos (3U)
11053#define PWR_PDCRB_PD3_Msk (0x1UL << PWR_PDCRB_PD3_Pos) /*!< 0x00000008 */
11054#define PWR_PDCRB_PD3 PWR_PDCRB_PD3_Msk /*!< Port PB3 Pull-Down set */
11055#define PWR_PDCRB_PD4_Pos (4U)
11056#define PWR_PDCRB_PD4_Msk (0x1UL << PWR_PDCRB_PD4_Pos) /*!< 0x00000010 */
11057#define PWR_PDCRB_PD4 PWR_PDCRB_PD4_Msk /*!< Port PB4 Pull-Down set */
11058#define PWR_PDCRB_PD5_Pos (5U)
11059#define PWR_PDCRB_PD5_Msk (0x1UL << PWR_PDCRB_PD5_Pos) /*!< 0x00000020 */
11060#define PWR_PDCRB_PD5 PWR_PDCRB_PD5_Msk /*!< Port PB5 Pull-Down set */
11061#define PWR_PDCRB_PD6_Pos (6U)
11062#define PWR_PDCRB_PD6_Msk (0x1UL << PWR_PDCRB_PD6_Pos) /*!< 0x00000040 */
11063#define PWR_PDCRB_PD6 PWR_PDCRB_PD6_Msk /*!< Port PB6 Pull-Down set */
11064#define PWR_PDCRB_PD7_Pos (7U)
11065#define PWR_PDCRB_PD7_Msk (0x1UL << PWR_PDCRB_PD7_Pos) /*!< 0x00000080 */
11066#define PWR_PDCRB_PD7 PWR_PDCRB_PD7_Msk /*!< Port PB7 Pull-Down set */
11067#define PWR_PDCRB_PD8_Pos (8U)
11068#define PWR_PDCRB_PD8_Msk (0x1UL << PWR_PDCRB_PD8_Pos) /*!< 0x00000100 */
11069#define PWR_PDCRB_PD8 PWR_PDCRB_PD8_Msk /*!< Port PB8 Pull-Down set */
11070#define PWR_PDCRB_PD9_Pos (9U)
11071#define PWR_PDCRB_PD9_Msk (0x1UL << PWR_PDCRB_PD9_Pos) /*!< 0x00000200 */
11072#define PWR_PDCRB_PD9 PWR_PDCRB_PD9_Msk /*!< Port PB9 Pull-Down set */
11073#define PWR_PDCRB_PD10_Pos (10U)
11074#define PWR_PDCRB_PD10_Msk (0x1UL << PWR_PDCRB_PD10_Pos) /*!< 0x00000400 */
11075#define PWR_PDCRB_PD10 PWR_PDCRB_PD10_Msk /*!< Port PB10 Pull-Down set */
11076#define PWR_PDCRB_PD11_Pos (11U)
11077#define PWR_PDCRB_PD11_Msk (0x1UL << PWR_PDCRB_PD11_Pos) /*!< 0x00000800 */
11078#define PWR_PDCRB_PD11 PWR_PDCRB_PD11_Msk /*!< Port PB11 Pull-Down set */
11079#define PWR_PDCRB_PD12_Pos (12U)
11080#define PWR_PDCRB_PD12_Msk (0x1UL << PWR_PDCRB_PD12_Pos) /*!< 0x00001000 */
11081#define PWR_PDCRB_PD12 PWR_PDCRB_PD12_Msk /*!< Port PB12 Pull-Down set */
11082#define PWR_PDCRB_PD13_Pos (13U)
11083#define PWR_PDCRB_PD13_Msk (0x1UL << PWR_PDCRB_PD13_Pos) /*!< 0x00002000 */
11084#define PWR_PDCRB_PD13 PWR_PDCRB_PD13_Msk /*!< Port PB13 Pull-Down set */
11085#define PWR_PDCRB_PD14_Pos (14U)
11086#define PWR_PDCRB_PD14_Msk (0x1UL << PWR_PDCRB_PD14_Pos) /*!< 0x00004000 */
11087#define PWR_PDCRB_PD14 PWR_PDCRB_PD14_Msk /*!< Port PB14 Pull-Down set */
11088#define PWR_PDCRB_PD15_Pos (15U)
11089#define PWR_PDCRB_PD15_Msk (0x1UL << PWR_PDCRB_PD15_Pos) /*!< 0x00008000 */
11090#define PWR_PDCRB_PD15 PWR_PDCRB_PD15_Msk /*!< Port PB15 Pull-Down set */
11091
11092/******************** Bit definition for PWR_PUCRC register ********************/
11093#define PWR_PUCRC_PU0_Pos (0U)
11094#define PWR_PUCRC_PU0_Msk (0x1UL << PWR_PUCRC_PU0_Pos) /*!< 0x00000001 */
11095#define PWR_PUCRC_PU0 PWR_PUCRC_PU0_Msk /*!< Port PC0 Pull-Up set */
11096#define PWR_PUCRC_PU1_Pos (1U)
11097#define PWR_PUCRC_PU1_Msk (0x1UL << PWR_PUCRC_PU1_Pos) /*!< 0x00000002 */
11098#define PWR_PUCRC_PU1 PWR_PUCRC_PU1_Msk /*!< Port PC1 Pull-Up set */
11099#define PWR_PUCRC_PU2_Pos (2U)
11100#define PWR_PUCRC_PU2_Msk (0x1UL << PWR_PUCRC_PU2_Pos) /*!< 0x00000004 */
11101#define PWR_PUCRC_PU2 PWR_PUCRC_PU2_Msk /*!< Port PC2 Pull-Up set */
11102#define PWR_PUCRC_PU3_Pos (3U)
11103#define PWR_PUCRC_PU3_Msk (0x1UL << PWR_PUCRC_PU3_Pos) /*!< 0x00000008 */
11104#define PWR_PUCRC_PU3 PWR_PUCRC_PU3_Msk /*!< Port PC3 Pull-Up set */
11105#define PWR_PUCRC_PU4_Pos (4U)
11106#define PWR_PUCRC_PU4_Msk (0x1UL << PWR_PUCRC_PU4_Pos) /*!< 0x00000010 */
11107#define PWR_PUCRC_PU4 PWR_PUCRC_PU4_Msk /*!< Port PC4 Pull-Up set */
11108#define PWR_PUCRC_PU5_Pos (5U)
11109#define PWR_PUCRC_PU5_Msk (0x1UL << PWR_PUCRC_PU5_Pos) /*!< 0x00000020 */
11110#define PWR_PUCRC_PU5 PWR_PUCRC_PU5_Msk /*!< Port PC5 Pull-Up set */
11111#define PWR_PUCRC_PU6_Pos (6U)
11112#define PWR_PUCRC_PU6_Msk (0x1UL << PWR_PUCRC_PU6_Pos) /*!< 0x00000040 */
11113#define PWR_PUCRC_PU6 PWR_PUCRC_PU6_Msk /*!< Port PC6 Pull-Up set */
11114#define PWR_PUCRC_PU7_Pos (7U)
11115#define PWR_PUCRC_PU7_Msk (0x1UL << PWR_PUCRC_PU7_Pos) /*!< 0x00000080 */
11116#define PWR_PUCRC_PU7 PWR_PUCRC_PU7_Msk /*!< Port PC7 Pull-Up set */
11117#define PWR_PUCRC_PU8_Pos (8U)
11118#define PWR_PUCRC_PU8_Msk (0x1UL << PWR_PUCRC_PU8_Pos) /*!< 0x00000100 */
11119#define PWR_PUCRC_PU8 PWR_PUCRC_PU8_Msk /*!< Port PC8 Pull-Up set */
11120#define PWR_PUCRC_PU9_Pos (9U)
11121#define PWR_PUCRC_PU9_Msk (0x1UL << PWR_PUCRC_PU9_Pos) /*!< 0x00000200 */
11122#define PWR_PUCRC_PU9 PWR_PUCRC_PU9_Msk /*!< Port PC9 Pull-Up set */
11123#define PWR_PUCRC_PU10_Pos (10U)
11124#define PWR_PUCRC_PU10_Msk (0x1UL << PWR_PUCRC_PU10_Pos) /*!< 0x00000400 */
11125#define PWR_PUCRC_PU10 PWR_PUCRC_PU10_Msk /*!< Port PC10 Pull-Up set */
11126#define PWR_PUCRC_PU11_Pos (11U)
11127#define PWR_PUCRC_PU11_Msk (0x1UL << PWR_PUCRC_PU11_Pos) /*!< 0x00000800 */
11128#define PWR_PUCRC_PU11 PWR_PUCRC_PU11_Msk /*!< Port PC11 Pull-Up set */
11129#define PWR_PUCRC_PU12_Pos (12U)
11130#define PWR_PUCRC_PU12_Msk (0x1UL << PWR_PUCRC_PU12_Pos) /*!< 0x00001000 */
11131#define PWR_PUCRC_PU12 PWR_PUCRC_PU12_Msk /*!< Port PC12 Pull-Up set */
11132#define PWR_PUCRC_PU13_Pos (13U)
11133#define PWR_PUCRC_PU13_Msk (0x1UL << PWR_PUCRC_PU13_Pos) /*!< 0x00002000 */
11134#define PWR_PUCRC_PU13 PWR_PUCRC_PU13_Msk /*!< Port PC13 Pull-Up set */
11135#define PWR_PUCRC_PU14_Pos (14U)
11136#define PWR_PUCRC_PU14_Msk (0x1UL << PWR_PUCRC_PU14_Pos) /*!< 0x00004000 */
11137#define PWR_PUCRC_PU14 PWR_PUCRC_PU14_Msk /*!< Port PC14 Pull-Up set */
11138#define PWR_PUCRC_PU15_Pos (15U)
11139#define PWR_PUCRC_PU15_Msk (0x1UL << PWR_PUCRC_PU15_Pos) /*!< 0x00008000 */
11140#define PWR_PUCRC_PU15 PWR_PUCRC_PU15_Msk /*!< Port PC15 Pull-Up set */
11141
11142/******************** Bit definition for PWR_PDCRC register ********************/
11143#define PWR_PDCRC_PD0_Pos (0U)
11144#define PWR_PDCRC_PD0_Msk (0x1UL << PWR_PDCRC_PD0_Pos) /*!< 0x00000001 */
11145#define PWR_PDCRC_PD0 PWR_PDCRC_PD0_Msk /*!< Port PC0 Pull-Down set */
11146#define PWR_PDCRC_PD1_Pos (1U)
11147#define PWR_PDCRC_PD1_Msk (0x1UL << PWR_PDCRC_PD1_Pos) /*!< 0x00000002 */
11148#define PWR_PDCRC_PD1 PWR_PDCRC_PD1_Msk /*!< Port PC1 Pull-Down set */
11149#define PWR_PDCRC_PD2_Pos (2U)
11150#define PWR_PDCRC_PD2_Msk (0x1UL << PWR_PDCRC_PD2_Pos) /*!< 0x00000004 */
11151#define PWR_PDCRC_PD2 PWR_PDCRC_PD2_Msk /*!< Port PC2 Pull-Down set */
11152#define PWR_PDCRC_PD3_Pos (3U)
11153#define PWR_PDCRC_PD3_Msk (0x1UL << PWR_PDCRC_PD3_Pos) /*!< 0x00000008 */
11154#define PWR_PDCRC_PD3 PWR_PDCRC_PD3_Msk /*!< Port PC3 Pull-Down set */
11155#define PWR_PDCRC_PD4_Pos (4U)
11156#define PWR_PDCRC_PD4_Msk (0x1UL << PWR_PDCRC_PD4_Pos) /*!< 0x00000010 */
11157#define PWR_PDCRC_PD4 PWR_PDCRC_PD4_Msk /*!< Port PC4 Pull-Down set */
11158#define PWR_PDCRC_PD5_Pos (5U)
11159#define PWR_PDCRC_PD5_Msk (0x1UL << PWR_PDCRC_PD5_Pos) /*!< 0x00000020 */
11160#define PWR_PDCRC_PD5 PWR_PDCRC_PD5_Msk /*!< Port PC5 Pull-Down set */
11161#define PWR_PDCRC_PD6_Pos (6U)
11162#define PWR_PDCRC_PD6_Msk (0x1UL << PWR_PDCRC_PD6_Pos) /*!< 0x00000040 */
11163#define PWR_PDCRC_PD6 PWR_PDCRC_PD6_Msk /*!< Port PC6 Pull-Down set */
11164#define PWR_PDCRC_PD7_Pos (7U)
11165#define PWR_PDCRC_PD7_Msk (0x1UL << PWR_PDCRC_PD7_Pos) /*!< 0x00000080 */
11166#define PWR_PDCRC_PD7 PWR_PDCRC_PD7_Msk /*!< Port PC7 Pull-Down set */
11167#define PWR_PDCRC_PD8_Pos (8U)
11168#define PWR_PDCRC_PD8_Msk (0x1UL << PWR_PDCRC_PD8_Pos) /*!< 0x00000100 */
11169#define PWR_PDCRC_PD8 PWR_PDCRC_PD8_Msk /*!< Port PC8 Pull-Down set */
11170#define PWR_PDCRC_PD9_Pos (9U)
11171#define PWR_PDCRC_PD9_Msk (0x1UL << PWR_PDCRC_PD9_Pos) /*!< 0x00000200 */
11172#define PWR_PDCRC_PD9 PWR_PDCRC_PD9_Msk /*!< Port PC9 Pull-Down set */
11173#define PWR_PDCRC_PD10_Pos (10U)
11174#define PWR_PDCRC_PD10_Msk (0x1UL << PWR_PDCRC_PD10_Pos) /*!< 0x00000400 */
11175#define PWR_PDCRC_PD10 PWR_PDCRC_PD10_Msk /*!< Port PC10 Pull-Down set */
11176#define PWR_PDCRC_PD11_Pos (11U)
11177#define PWR_PDCRC_PD11_Msk (0x1UL << PWR_PDCRC_PD11_Pos) /*!< 0x00000800 */
11178#define PWR_PDCRC_PD11 PWR_PDCRC_PD11_Msk /*!< Port PC11 Pull-Down set */
11179#define PWR_PDCRC_PD12_Pos (12U)
11180#define PWR_PDCRC_PD12_Msk (0x1UL << PWR_PDCRC_PD12_Pos) /*!< 0x00001000 */
11181#define PWR_PDCRC_PD12 PWR_PDCRC_PD12_Msk /*!< Port PC12 Pull-Down set */
11182#define PWR_PDCRC_PD13_Pos (13U)
11183#define PWR_PDCRC_PD13_Msk (0x1UL << PWR_PDCRC_PD13_Pos) /*!< 0x00002000 */
11184#define PWR_PDCRC_PD13 PWR_PDCRC_PD13_Msk /*!< Port PC13 Pull-Down set */
11185#define PWR_PDCRC_PD14_Pos (14U)
11186#define PWR_PDCRC_PD14_Msk (0x1UL << PWR_PDCRC_PD14_Pos) /*!< 0x00004000 */
11187#define PWR_PDCRC_PD14 PWR_PDCRC_PD14_Msk /*!< Port PC14 Pull-Down set */
11188#define PWR_PDCRC_PD15_Pos (15U)
11189#define PWR_PDCRC_PD15_Msk (0x1UL << PWR_PDCRC_PD15_Pos) /*!< 0x00008000 */
11190#define PWR_PDCRC_PD15 PWR_PDCRC_PD15_Msk /*!< Port PC15 Pull-Down set */
11191
11192/******************** Bit definition for PWR_PUCRD register ********************/
11193#define PWR_PUCRD_PU0_Pos (0U)
11194#define PWR_PUCRD_PU0_Msk (0x1UL << PWR_PUCRD_PU0_Pos) /*!< 0x00000001 */
11195#define PWR_PUCRD_PU0 PWR_PUCRD_PU0_Msk /*!< Port PD0 Pull-Up set */
11196#define PWR_PUCRD_PU1_Pos (1U)
11197#define PWR_PUCRD_PU1_Msk (0x1UL << PWR_PUCRD_PU1_Pos) /*!< 0x00000002 */
11198#define PWR_PUCRD_PU1 PWR_PUCRD_PU1_Msk /*!< Port PD1 Pull-Up set */
11199#define PWR_PUCRD_PU2_Pos (2U)
11200#define PWR_PUCRD_PU2_Msk (0x1UL << PWR_PUCRD_PU2_Pos) /*!< 0x00000004 */
11201#define PWR_PUCRD_PU2 PWR_PUCRD_PU2_Msk /*!< Port PD2 Pull-Up set */
11202#define PWR_PUCRD_PU3_Pos (3U)
11203#define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */
11204#define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Port PD3 Pull-Up set */
11205#define PWR_PUCRD_PU4_Pos (4U)
11206#define PWR_PUCRD_PU4_Msk (0x1UL << PWR_PUCRD_PU4_Pos) /*!< 0x00000010 */
11207#define PWR_PUCRD_PU4 PWR_PUCRD_PU4_Msk /*!< Port PD4 Pull-Up set */
11208#define PWR_PUCRD_PU5_Pos (5U)
11209#define PWR_PUCRD_PU5_Msk (0x1UL << PWR_PUCRD_PU5_Pos) /*!< 0x00000020 */
11210#define PWR_PUCRD_PU5 PWR_PUCRD_PU5_Msk /*!< Port PD5 Pull-Up set */
11211#define PWR_PUCRD_PU6_Pos (6U)
11212#define PWR_PUCRD_PU6_Msk (0x1UL << PWR_PUCRD_PU6_Pos) /*!< 0x00000040 */
11213#define PWR_PUCRD_PU6 PWR_PUCRD_PU6_Msk /*!< Port PD6 Pull-Up set */
11214#define PWR_PUCRD_PU7_Pos (7U)
11215#define PWR_PUCRD_PU7_Msk (0x1UL << PWR_PUCRD_PU7_Pos) /*!< 0x00000080 */
11216#define PWR_PUCRD_PU7 PWR_PUCRD_PU7_Msk /*!< Port PD7 Pull-Up set */
11217#define PWR_PUCRD_PU8_Pos (8U)
11218#define PWR_PUCRD_PU8_Msk (0x1UL << PWR_PUCRD_PU8_Pos) /*!< 0x00000100 */
11219#define PWR_PUCRD_PU8 PWR_PUCRD_PU8_Msk /*!< Port PD8 Pull-Up set */
11220#define PWR_PUCRD_PU9_Pos (9U)
11221#define PWR_PUCRD_PU9_Msk (0x1UL << PWR_PUCRD_PU9_Pos) /*!< 0x00000200 */
11222#define PWR_PUCRD_PU9 PWR_PUCRD_PU9_Msk /*!< Port PD9 Pull-Up set */
11223#define PWR_PUCRD_PU10_Pos (10U)
11224#define PWR_PUCRD_PU10_Msk (0x1UL << PWR_PUCRD_PU10_Pos) /*!< 0x00000400 */
11225#define PWR_PUCRD_PU10 PWR_PUCRD_PU10_Msk /*!< Port PD10 Pull-Up set */
11226#define PWR_PUCRD_PU11_Pos (11U)
11227#define PWR_PUCRD_PU11_Msk (0x1UL << PWR_PUCRD_PU11_Pos) /*!< 0x00000800 */
11228#define PWR_PUCRD_PU11 PWR_PUCRD_PU11_Msk /*!< Port PD11 Pull-Up set */
11229#define PWR_PUCRD_PU12_Pos (12U)
11230#define PWR_PUCRD_PU12_Msk (0x1UL << PWR_PUCRD_PU12_Pos) /*!< 0x00001000 */
11231#define PWR_PUCRD_PU12 PWR_PUCRD_PU12_Msk /*!< Port PD12 Pull-Up set */
11232#define PWR_PUCRD_PU13_Pos (13U)
11233#define PWR_PUCRD_PU13_Msk (0x1UL << PWR_PUCRD_PU13_Pos) /*!< 0x00002000 */
11234#define PWR_PUCRD_PU13 PWR_PUCRD_PU13_Msk /*!< Port PD13 Pull-Up set */
11235#define PWR_PUCRD_PU14_Pos (14U)
11236#define PWR_PUCRD_PU14_Msk (0x1UL << PWR_PUCRD_PU14_Pos) /*!< 0x00004000 */
11237#define PWR_PUCRD_PU14 PWR_PUCRD_PU14_Msk /*!< Port PD14 Pull-Up set */
11238#define PWR_PUCRD_PU15_Pos (15U)
11239#define PWR_PUCRD_PU15_Msk (0x1UL << PWR_PUCRD_PU15_Pos) /*!< 0x00008000 */
11240#define PWR_PUCRD_PU15 PWR_PUCRD_PU15_Msk /*!< Port PD15 Pull-Up set */
11241
11242/******************** Bit definition for PWR_PDCRD register ********************/
11243#define PWR_PDCRD_PD0_Pos (0U)
11244#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
11245#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
11246#define PWR_PDCRD_PD1_Pos (1U)
11247#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
11248#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
11249#define PWR_PDCRD_PD2_Pos (2U)
11250#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
11251#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
11252#define PWR_PDCRD_PD3_Pos (3U)
11253#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
11254#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
11255#define PWR_PDCRD_PD4_Pos (4U)
11256#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
11257#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
11258#define PWR_PDCRD_PD5_Pos (5U)
11259#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
11260#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
11261#define PWR_PDCRD_PD6_Pos (6U)
11262#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
11263#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
11264#define PWR_PDCRD_PD7_Pos (7U)
11265#define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
11266#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
11267#define PWR_PDCRD_PD8_Pos (8U)
11268#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
11269#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
11270#define PWR_PDCRD_PD9_Pos (9U)
11271#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
11272#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
11273#define PWR_PDCRD_PD10_Pos (10U)
11274#define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
11275#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
11276#define PWR_PDCRD_PD11_Pos (11U)
11277#define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
11278#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
11279#define PWR_PDCRD_PD12_Pos (12U)
11280#define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
11281#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
11282#define PWR_PDCRD_PD13_Pos (13U)
11283#define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
11284#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
11285#define PWR_PDCRD_PD14_Pos (14U)
11286#define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
11287#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
11288#define PWR_PDCRD_PD15_Pos (15U)
11289#define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
11290#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
11291
11292/******************** Bit definition for PWR_PUCRE register ********************/
11293#define PWR_PUCRE_PU0_Pos (0U)
11294#define PWR_PUCRE_PU0_Msk (0x1UL << PWR_PUCRE_PU0_Pos) /*!< 0x00000001 */
11295#define PWR_PUCRE_PU0 PWR_PUCRE_PU0_Msk /*!< Port PE0 Pull-Up set */
11296#define PWR_PUCRE_PU1_Pos (1U)
11297#define PWR_PUCRE_PU1_Msk (0x1UL << PWR_PUCRE_PU1_Pos) /*!< 0x00000002 */
11298#define PWR_PUCRE_PU1 PWR_PUCRE_PU1_Msk /*!< Port PE1 Pull-Up set */
11299#define PWR_PUCRE_PU2_Pos (2U)
11300#define PWR_PUCRE_PU2_Msk (0x1UL << PWR_PUCRE_PU2_Pos) /*!< 0x00000004 */
11301#define PWR_PUCRE_PU2 PWR_PUCRE_PU2_Msk /*!< Port PE2 Pull-Up set */
11302#define PWR_PUCRE_PU3_Pos (3U)
11303#define PWR_PUCRE_PU3_Msk (0x1UL << PWR_PUCRE_PU3_Pos) /*!< 0x00000008 */
11304#define PWR_PUCRE_PU3 PWR_PUCRE_PU3_Msk /*!< Port PE3 Pull-Up set */
11305#define PWR_PUCRE_PU4_Pos (4U)
11306#define PWR_PUCRE_PU4_Msk (0x1UL << PWR_PUCRE_PU4_Pos) /*!< 0x00000010 */
11307#define PWR_PUCRE_PU4 PWR_PUCRE_PU4_Msk /*!< Port PE4 Pull-Up set */
11308#define PWR_PUCRE_PU5_Pos (5U)
11309#define PWR_PUCRE_PU5_Msk (0x1UL << PWR_PUCRE_PU5_Pos) /*!< 0x00000020 */
11310#define PWR_PUCRE_PU5 PWR_PUCRE_PU5_Msk /*!< Port PE5 Pull-Up set */
11311#define PWR_PUCRE_PU6_Pos (6U)
11312#define PWR_PUCRE_PU6_Msk (0x1UL << PWR_PUCRE_PU6_Pos) /*!< 0x00000040 */
11313#define PWR_PUCRE_PU6 PWR_PUCRE_PU6_Msk /*!< Port PE6 Pull-Up set */
11314#define PWR_PUCRE_PU7_Pos (7U)
11315#define PWR_PUCRE_PU7_Msk (0x1UL << PWR_PUCRE_PU7_Pos) /*!< 0x00000080 */
11316#define PWR_PUCRE_PU7 PWR_PUCRE_PU7_Msk /*!< Port PE7 Pull-Up set */
11317#define PWR_PUCRE_PU8_Pos (8U)
11318#define PWR_PUCRE_PU8_Msk (0x1UL << PWR_PUCRE_PU8_Pos) /*!< 0x00000100 */
11319#define PWR_PUCRE_PU8 PWR_PUCRE_PU8_Msk /*!< Port PE8 Pull-Up set */
11320#define PWR_PUCRE_PU9_Pos (9U)
11321#define PWR_PUCRE_PU9_Msk (0x1UL << PWR_PUCRE_PU9_Pos) /*!< 0x00000200 */
11322#define PWR_PUCRE_PU9 PWR_PUCRE_PU9_Msk /*!< Port PE9 Pull-Up set */
11323#define PWR_PUCRE_PU10_Pos (10U)
11324#define PWR_PUCRE_PU10_Msk (0x1UL << PWR_PUCRE_PU10_Pos) /*!< 0x00000400 */
11325#define PWR_PUCRE_PU10 PWR_PUCRE_PU10_Msk /*!< Port PE10 Pull-Up set */
11326#define PWR_PUCRE_PU11_Pos (11U)
11327#define PWR_PUCRE_PU11_Msk (0x1UL << PWR_PUCRE_PU11_Pos) /*!< 0x00000800 */
11328#define PWR_PUCRE_PU11 PWR_PUCRE_PU11_Msk /*!< Port PE11 Pull-Up set */
11329#define PWR_PUCRE_PU12_Pos (12U)
11330#define PWR_PUCRE_PU12_Msk (0x1UL << PWR_PUCRE_PU12_Pos) /*!< 0x00001000 */
11331#define PWR_PUCRE_PU12 PWR_PUCRE_PU12_Msk /*!< Port PE12 Pull-Up set */
11332#define PWR_PUCRE_PU13_Pos (13U)
11333#define PWR_PUCRE_PU13_Msk (0x1UL << PWR_PUCRE_PU13_Pos) /*!< 0x00002000 */
11334#define PWR_PUCRE_PU13 PWR_PUCRE_PU13_Msk /*!< Port PE13 Pull-Up set */
11335#define PWR_PUCRE_PU14_Pos (14U)
11336#define PWR_PUCRE_PU14_Msk (0x1UL << PWR_PUCRE_PU14_Pos) /*!< 0x00004000 */
11337#define PWR_PUCRE_PU14 PWR_PUCRE_PU14_Msk /*!< Port PE14 Pull-Up set */
11338#define PWR_PUCRE_PU15_Pos (15U)
11339#define PWR_PUCRE_PU15_Msk (0x1UL << PWR_PUCRE_PU15_Pos) /*!< 0x00008000 */
11340#define PWR_PUCRE_PU15 PWR_PUCRE_PU15_Msk /*!< Port PE15 Pull-Up set */
11341
11342/******************** Bit definition for PWR_PDCRE register ********************/
11343#define PWR_PDCRE_PD0_Pos (0U)
11344#define PWR_PDCRE_PD0_Msk (0x1UL << PWR_PDCRE_PD0_Pos) /*!< 0x00000001 */
11345#define PWR_PDCRE_PD0 PWR_PDCRE_PD0_Msk /*!< Port PE0 Pull-Down set */
11346#define PWR_PDCRE_PD1_Pos (1U)
11347#define PWR_PDCRE_PD1_Msk (0x1UL << PWR_PDCRE_PD1_Pos) /*!< 0x00000002 */
11348#define PWR_PDCRE_PD1 PWR_PDCRE_PD1_Msk /*!< Port PE1 Pull-Down set */
11349#define PWR_PDCRE_PD2_Pos (2U)
11350#define PWR_PDCRE_PD2_Msk (0x1UL << PWR_PDCRE_PD2_Pos) /*!< 0x00000004 */
11351#define PWR_PDCRE_PD2 PWR_PDCRE_PD2_Msk /*!< Port PE2 Pull-Down set */
11352#define PWR_PDCRE_PD3_Pos (3U)
11353#define PWR_PDCRE_PD3_Msk (0x1UL << PWR_PDCRE_PD3_Pos) /*!< 0x00000008 */
11354#define PWR_PDCRE_PD3 PWR_PDCRE_PD3_Msk /*!< Port PE3 Pull-Down set */
11355#define PWR_PDCRE_PD4_Pos (4U)
11356#define PWR_PDCRE_PD4_Msk (0x1UL << PWR_PDCRE_PD4_Pos) /*!< 0x00000010 */
11357#define PWR_PDCRE_PD4 PWR_PDCRE_PD4_Msk /*!< Port PE4 Pull-Down set */
11358#define PWR_PDCRE_PD5_Pos (5U)
11359#define PWR_PDCRE_PD5_Msk (0x1UL << PWR_PDCRE_PD5_Pos) /*!< 0x00000020 */
11360#define PWR_PDCRE_PD5 PWR_PDCRE_PD5_Msk /*!< Port PE5 Pull-Down set */
11361#define PWR_PDCRE_PD6_Pos (6U)
11362#define PWR_PDCRE_PD6_Msk (0x1UL << PWR_PDCRE_PD6_Pos) /*!< 0x00000040 */
11363#define PWR_PDCRE_PD6 PWR_PDCRE_PD6_Msk /*!< Port PE6 Pull-Down set */
11364#define PWR_PDCRE_PD7_Pos (7U)
11365#define PWR_PDCRE_PD7_Msk (0x1UL << PWR_PDCRE_PD7_Pos) /*!< 0x00000080 */
11366#define PWR_PDCRE_PD7 PWR_PDCRE_PD7_Msk /*!< Port PE7 Pull-Down set */
11367#define PWR_PDCRE_PD8_Pos (8U)
11368#define PWR_PDCRE_PD8_Msk (0x1UL << PWR_PDCRE_PD8_Pos) /*!< 0x00000100 */
11369#define PWR_PDCRE_PD8 PWR_PDCRE_PD8_Msk /*!< Port PE8 Pull-Down set */
11370#define PWR_PDCRE_PD9_Pos (9U)
11371#define PWR_PDCRE_PD9_Msk (0x1UL << PWR_PDCRE_PD9_Pos) /*!< 0x00000200 */
11372#define PWR_PDCRE_PD9 PWR_PDCRE_PD9_Msk /*!< Port PE9 Pull-Down set */
11373#define PWR_PDCRE_PD10_Pos (10U)
11374#define PWR_PDCRE_PD10_Msk (0x1UL << PWR_PDCRE_PD10_Pos) /*!< 0x00000400 */
11375#define PWR_PDCRE_PD10 PWR_PDCRE_PD10_Msk /*!< Port PE10 Pull-Down set */
11376#define PWR_PDCRE_PD11_Pos (11U)
11377#define PWR_PDCRE_PD11_Msk (0x1UL << PWR_PDCRE_PD11_Pos) /*!< 0x00000800 */
11378#define PWR_PDCRE_PD11 PWR_PDCRE_PD11_Msk /*!< Port PE11 Pull-Down set */
11379#define PWR_PDCRE_PD12_Pos (12U)
11380#define PWR_PDCRE_PD12_Msk (0x1UL << PWR_PDCRE_PD12_Pos) /*!< 0x00001000 */
11381#define PWR_PDCRE_PD12 PWR_PDCRE_PD12_Msk /*!< Port PE12 Pull-Down set */
11382#define PWR_PDCRE_PD13_Pos (13U)
11383#define PWR_PDCRE_PD13_Msk (0x1UL << PWR_PDCRE_PD13_Pos) /*!< 0x00002000 */
11384#define PWR_PDCRE_PD13 PWR_PDCRE_PD13_Msk /*!< Port PE13 Pull-Down set */
11385#define PWR_PDCRE_PD14_Pos (14U)
11386#define PWR_PDCRE_PD14_Msk (0x1UL << PWR_PDCRE_PD14_Pos) /*!< 0x00004000 */
11387#define PWR_PDCRE_PD14 PWR_PDCRE_PD14_Msk /*!< Port PE14 Pull-Down set */
11388#define PWR_PDCRE_PD15_Pos (15U)
11389#define PWR_PDCRE_PD15_Msk (0x1UL << PWR_PDCRE_PD15_Pos) /*!< 0x00008000 */
11390#define PWR_PDCRE_PD15 PWR_PDCRE_PD15_Msk /*!< Port PE15 Pull-Down set */
11391
11392/******************** Bit definition for PWR_PUCRF register ********************/
11393#define PWR_PUCRF_PU0_Pos (0U)
11394#define PWR_PUCRF_PU0_Msk (0x1UL << PWR_PUCRF_PU0_Pos) /*!< 0x00000001 */
11395#define PWR_PUCRF_PU0 PWR_PUCRF_PU0_Msk /*!< Port PF0 Pull-Up set */
11396#define PWR_PUCRF_PU1_Pos (1U)
11397#define PWR_PUCRF_PU1_Msk (0x1UL << PWR_PUCRF_PU1_Pos) /*!< 0x00000002 */
11398#define PWR_PUCRF_PU1 PWR_PUCRF_PU1_Msk /*!< Port PF1 Pull-Up set */
11399#define PWR_PUCRF_PU2_Pos (2U)
11400#define PWR_PUCRF_PU2_Msk (0x1UL << PWR_PUCRF_PU2_Pos) /*!< 0x00000004 */
11401#define PWR_PUCRF_PU2 PWR_PUCRF_PU2_Msk /*!< Port PF2 Pull-Up set */
11402#define PWR_PUCRF_PU3_Pos (3U)
11403#define PWR_PUCRF_PU3_Msk (0x1UL << PWR_PUCRF_PU3_Pos) /*!< 0x00000008 */
11404#define PWR_PUCRF_PU3 PWR_PUCRF_PU3_Msk /*!< Port PF3 Pull-Up set */
11405#define PWR_PUCRF_PU4_Pos (4U)
11406#define PWR_PUCRF_PU4_Msk (0x1UL << PWR_PUCRF_PU4_Pos) /*!< 0x00000010 */
11407#define PWR_PUCRF_PU4 PWR_PUCRF_PU4_Msk /*!< Port PF4 Pull-Up set */
11408#define PWR_PUCRF_PU5_Pos (5U)
11409#define PWR_PUCRF_PU5_Msk (0x1UL << PWR_PUCRF_PU5_Pos) /*!< 0x00000020 */
11410#define PWR_PUCRF_PU5 PWR_PUCRF_PU5_Msk /*!< Port PF5 Pull-Up set */
11411#define PWR_PUCRF_PU6_Pos (6U)
11412#define PWR_PUCRF_PU6_Msk (0x1UL << PWR_PUCRF_PU6_Pos) /*!< 0x00000040 */
11413#define PWR_PUCRF_PU6 PWR_PUCRF_PU6_Msk /*!< Port PF6 Pull-Up set */
11414#define PWR_PUCRF_PU7_Pos (7U)
11415#define PWR_PUCRF_PU7_Msk (0x1UL << PWR_PUCRF_PU7_Pos) /*!< 0x00000080 */
11416#define PWR_PUCRF_PU7 PWR_PUCRF_PU7_Msk /*!< Port PF7 Pull-Up set */
11417#define PWR_PUCRF_PU8_Pos (8U)
11418#define PWR_PUCRF_PU8_Msk (0x1UL << PWR_PUCRF_PU8_Pos) /*!< 0x00000100 */
11419#define PWR_PUCRF_PU8 PWR_PUCRF_PU8_Msk /*!< Port PF8 Pull-Up set */
11420#define PWR_PUCRF_PU9_Pos (9U)
11421#define PWR_PUCRF_PU9_Msk (0x1UL << PWR_PUCRF_PU9_Pos) /*!< 0x00000200 */
11422#define PWR_PUCRF_PU9 PWR_PUCRF_PU9_Msk /*!< Port PF9 Pull-Up set */
11423#define PWR_PUCRF_PU10_Pos (10U)
11424#define PWR_PUCRF_PU10_Msk (0x1UL << PWR_PUCRF_PU10_Pos) /*!< 0x00000400 */
11425#define PWR_PUCRF_PU10 PWR_PUCRF_PU10_Msk /*!< Port PF10 Pull-Up set */
11426#define PWR_PUCRF_PU11_Pos (11U)
11427#define PWR_PUCRF_PU11_Msk (0x1UL << PWR_PUCRF_PU11_Pos) /*!< 0x00000800 */
11428#define PWR_PUCRF_PU11 PWR_PUCRF_PU11_Msk /*!< Port PF11 Pull-Up set */
11429#define PWR_PUCRF_PU12_Pos (12U)
11430#define PWR_PUCRF_PU12_Msk (0x1UL << PWR_PUCRF_PU12_Pos) /*!< 0x00001000 */
11431#define PWR_PUCRF_PU12 PWR_PUCRF_PU12_Msk /*!< Port PF12 Pull-Up set */
11432#define PWR_PUCRF_PU13_Pos (13U)
11433#define PWR_PUCRF_PU13_Msk (0x1UL << PWR_PUCRF_PU13_Pos) /*!< 0x00002000 */
11434#define PWR_PUCRF_PU13 PWR_PUCRF_PU13_Msk /*!< Port PF13 Pull-Up set */
11435#define PWR_PUCRF_PU14_Pos (14U)
11436#define PWR_PUCRF_PU14_Msk (0x1UL << PWR_PUCRF_PU14_Pos) /*!< 0x00004000 */
11437#define PWR_PUCRF_PU14 PWR_PUCRF_PU14_Msk /*!< Port PF14 Pull-Up set */
11438#define PWR_PUCRF_PU15_Pos (15U)
11439#define PWR_PUCRF_PU15_Msk (0x1UL << PWR_PUCRF_PU15_Pos) /*!< 0x00008000 */
11440#define PWR_PUCRF_PU15 PWR_PUCRF_PU15_Msk /*!< Port PF15 Pull-Up set */
11441
11442/******************** Bit definition for PWR_PDCRF register ********************/
11443#define PWR_PDCRF_PD0_Pos (0U)
11444#define PWR_PDCRF_PD0_Msk (0x1UL << PWR_PDCRF_PD0_Pos) /*!< 0x00000001 */
11445#define PWR_PDCRF_PD0 PWR_PDCRF_PD0_Msk /*!< Port PF0 Pull-Down set */
11446#define PWR_PDCRF_PD1_Pos (1U)
11447#define PWR_PDCRF_PD1_Msk (0x1UL << PWR_PDCRF_PD1_Pos) /*!< 0x00000002 */
11448#define PWR_PDCRF_PD1 PWR_PDCRF_PD1_Msk /*!< Port PF1 Pull-Down set */
11449#define PWR_PDCRF_PD2_Pos (2U)
11450#define PWR_PDCRF_PD2_Msk (0x1UL << PWR_PDCRF_PD2_Pos) /*!< 0x00000004 */
11451#define PWR_PDCRF_PD2 PWR_PDCRF_PD2_Msk /*!< Port PF2 Pull-Down set */
11452#define PWR_PDCRF_PD3_Pos (3U)
11453#define PWR_PDCRF_PD3_Msk (0x1UL << PWR_PDCRF_PD3_Pos) /*!< 0x00000008 */
11454#define PWR_PDCRF_PD3 PWR_PDCRF_PD3_Msk /*!< Port PF3 Pull-Down set */
11455#define PWR_PDCRF_PD4_Pos (4U)
11456#define PWR_PDCRF_PD4_Msk (0x1UL << PWR_PDCRF_PD4_Pos) /*!< 0x00000010 */
11457#define PWR_PDCRF_PD4 PWR_PDCRF_PD4_Msk /*!< Port PF4 Pull-Down set */
11458#define PWR_PDCRF_PD5_Pos (5U)
11459#define PWR_PDCRF_PD5_Msk (0x1UL << PWR_PDCRF_PD5_Pos) /*!< 0x00000020 */
11460#define PWR_PDCRF_PD5 PWR_PDCRF_PD5_Msk /*!< Port PF5 Pull-Down set */
11461#define PWR_PDCRF_PD6_Pos (6U)
11462#define PWR_PDCRF_PD6_Msk (0x1UL << PWR_PDCRF_PD6_Pos) /*!< 0x00000040 */
11463#define PWR_PDCRF_PD6 PWR_PDCRF_PD6_Msk /*!< Port PF6 Pull-Down set */
11464#define PWR_PDCRF_PD7_Pos (7U)
11465#define PWR_PDCRF_PD7_Msk (0x1UL << PWR_PDCRF_PD7_Pos) /*!< 0x00000080 */
11466#define PWR_PDCRF_PD7 PWR_PDCRF_PD7_Msk /*!< Port PF7 Pull-Down set */
11467#define PWR_PDCRF_PD8_Pos (8U)
11468#define PWR_PDCRF_PD8_Msk (0x1UL << PWR_PDCRF_PD8_Pos) /*!< 0x00000100 */
11469#define PWR_PDCRF_PD8 PWR_PDCRF_PD8_Msk /*!< Port PF8 Pull-Down set */
11470#define PWR_PDCRF_PD9_Pos (9U)
11471#define PWR_PDCRF_PD9_Msk (0x1UL << PWR_PDCRF_PD9_Pos) /*!< 0x00000200 */
11472#define PWR_PDCRF_PD9 PWR_PDCRF_PD9_Msk /*!< Port PF9 Pull-Down set */
11473#define PWR_PDCRF_PD10_Pos (10U)
11474#define PWR_PDCRF_PD10_Msk (0x1UL << PWR_PDCRF_PD10_Pos) /*!< 0x00000400 */
11475#define PWR_PDCRF_PD10 PWR_PDCRF_PD10_Msk /*!< Port PF10 Pull-Down set */
11476#define PWR_PDCRF_PD11_Pos (11U)
11477#define PWR_PDCRF_PD11_Msk (0x1UL << PWR_PDCRF_PD11_Pos) /*!< 0x00000800 */
11478#define PWR_PDCRF_PD11 PWR_PDCRF_PD11_Msk /*!< Port PF11 Pull-Down set */
11479#define PWR_PDCRF_PD12_Pos (12U)
11480#define PWR_PDCRF_PD12_Msk (0x1UL << PWR_PDCRF_PD12_Pos) /*!< 0x00001000 */
11481#define PWR_PDCRF_PD12 PWR_PDCRF_PD12_Msk /*!< Port PF12 Pull-Down set */
11482#define PWR_PDCRF_PD13_Pos (13U)
11483#define PWR_PDCRF_PD13_Msk (0x1UL << PWR_PDCRF_PD13_Pos) /*!< 0x00002000 */
11484#define PWR_PDCRF_PD13 PWR_PDCRF_PD13_Msk /*!< Port PF13 Pull-Down set */
11485#define PWR_PDCRF_PD14_Pos (14U)
11486#define PWR_PDCRF_PD14_Msk (0x1UL << PWR_PDCRF_PD14_Pos) /*!< 0x00004000 */
11487#define PWR_PDCRF_PD14 PWR_PDCRF_PD14_Msk /*!< Port PF14 Pull-Down set */
11488#define PWR_PDCRF_PD15_Pos (15U)
11489#define PWR_PDCRF_PD15_Msk (0x1UL << PWR_PDCRF_PD15_Pos) /*!< 0x00008000 */
11490#define PWR_PDCRF_PD15 PWR_PDCRF_PD15_Msk /*!< Port PF15 Pull-Down set */
11491
11492/******************** Bit definition for PWR_PUCRG register ********************/
11493#define PWR_PUCRG_PU0_Pos (0U)
11494#define PWR_PUCRG_PU0_Msk (0x1UL << PWR_PUCRG_PU0_Pos) /*!< 0x00000001 */
11495#define PWR_PUCRG_PU0 PWR_PUCRG_PU0_Msk /*!< Port PG0 Pull-Up set */
11496#define PWR_PUCRG_PU1_Pos (1U)
11497#define PWR_PUCRG_PU1_Msk (0x1UL << PWR_PUCRG_PU1_Pos) /*!< 0x00000002 */
11498#define PWR_PUCRG_PU1 PWR_PUCRG_PU1_Msk /*!< Port PG1 Pull-Up set */
11499#define PWR_PUCRG_PU2_Pos (2U)
11500#define PWR_PUCRG_PU2_Msk (0x1UL << PWR_PUCRG_PU2_Pos) /*!< 0x00000004 */
11501#define PWR_PUCRG_PU2 PWR_PUCRG_PU2_Msk /*!< Port PG2 Pull-Up set */
11502#define PWR_PUCRG_PU3_Pos (3U)
11503#define PWR_PUCRG_PU3_Msk (0x1UL << PWR_PUCRG_PU3_Pos) /*!< 0x00000008 */
11504#define PWR_PUCRG_PU3 PWR_PUCRG_PU3_Msk /*!< Port PG3 Pull-Up set */
11505#define PWR_PUCRG_PU4_Pos (4U)
11506#define PWR_PUCRG_PU4_Msk (0x1UL << PWR_PUCRG_PU4_Pos) /*!< 0x00000010 */
11507#define PWR_PUCRG_PU4 PWR_PUCRG_PU4_Msk /*!< Port PG4 Pull-Up set */
11508#define PWR_PUCRG_PU5_Pos (5U)
11509#define PWR_PUCRG_PU5_Msk (0x1UL << PWR_PUCRG_PU5_Pos) /*!< 0x00000020 */
11510#define PWR_PUCRG_PU5 PWR_PUCRG_PU5_Msk /*!< Port PG5 Pull-Up set */
11511#define PWR_PUCRG_PU6_Pos (6U)
11512#define PWR_PUCRG_PU6_Msk (0x1UL << PWR_PUCRG_PU6_Pos) /*!< 0x00000040 */
11513#define PWR_PUCRG_PU6 PWR_PUCRG_PU6_Msk /*!< Port PG6 Pull-Up set */
11514#define PWR_PUCRG_PU7_Pos (7U)
11515#define PWR_PUCRG_PU7_Msk (0x1UL << PWR_PUCRG_PU7_Pos) /*!< 0x00000080 */
11516#define PWR_PUCRG_PU7 PWR_PUCRG_PU7_Msk /*!< Port PG7 Pull-Up set */
11517#define PWR_PUCRG_PU8_Pos (8U)
11518#define PWR_PUCRG_PU8_Msk (0x1UL << PWR_PUCRG_PU8_Pos) /*!< 0x00000100 */
11519#define PWR_PUCRG_PU8 PWR_PUCRG_PU8_Msk /*!< Port PG8 Pull-Up set */
11520#define PWR_PUCRG_PU9_Pos (9U)
11521#define PWR_PUCRG_PU9_Msk (0x1UL << PWR_PUCRG_PU9_Pos) /*!< 0x00000200 */
11522#define PWR_PUCRG_PU9 PWR_PUCRG_PU9_Msk /*!< Port PG9 Pull-Up set */
11523#define PWR_PUCRG_PU10_Pos (10U)
11524#define PWR_PUCRG_PU10_Msk (0x1UL << PWR_PUCRG_PU10_Pos) /*!< 0x00000400 */
11525#define PWR_PUCRG_PU10 PWR_PUCRG_PU10_Msk /*!< Port PG10 Pull-Up set */
11526#define PWR_PUCRG_PU11_Pos (11U)
11527#define PWR_PUCRG_PU11_Msk (0x1UL << PWR_PUCRG_PU11_Pos) /*!< 0x00000800 */
11528#define PWR_PUCRG_PU11 PWR_PUCRG_PU11_Msk /*!< Port PG11 Pull-Up set */
11529#define PWR_PUCRG_PU12_Pos (12U)
11530#define PWR_PUCRG_PU12_Msk (0x1UL << PWR_PUCRG_PU12_Pos) /*!< 0x00001000 */
11531#define PWR_PUCRG_PU12 PWR_PUCRG_PU12_Msk /*!< Port PG12 Pull-Up set */
11532#define PWR_PUCRG_PU13_Pos (13U)
11533#define PWR_PUCRG_PU13_Msk (0x1UL << PWR_PUCRG_PU13_Pos) /*!< 0x00002000 */
11534#define PWR_PUCRG_PU13 PWR_PUCRG_PU13_Msk /*!< Port PG13 Pull-Up set */
11535#define PWR_PUCRG_PU14_Pos (14U)
11536#define PWR_PUCRG_PU14_Msk (0x1UL << PWR_PUCRG_PU14_Pos) /*!< 0x00004000 */
11537#define PWR_PUCRG_PU14 PWR_PUCRG_PU14_Msk /*!< Port PG14 Pull-Up set */
11538#define PWR_PUCRG_PU15_Pos (15U)
11539#define PWR_PUCRG_PU15_Msk (0x1UL << PWR_PUCRG_PU15_Pos) /*!< 0x00008000 */
11540#define PWR_PUCRG_PU15 PWR_PUCRG_PU15_Msk /*!< Port PG15 Pull-Up set */
11541
11542/******************** Bit definition for PWR_PDCRG register ********************/
11543#define PWR_PDCRG_PD0_Pos (0U)
11544#define PWR_PDCRG_PD0_Msk (0x1UL << PWR_PDCRG_PD0_Pos) /*!< 0x00000001 */
11545#define PWR_PDCRG_PD0 PWR_PDCRG_PD0_Msk /*!< Port PG0 Pull-Down set */
11546#define PWR_PDCRG_PD1_Pos (1U)
11547#define PWR_PDCRG_PD1_Msk (0x1UL << PWR_PDCRG_PD1_Pos) /*!< 0x00000002 */
11548#define PWR_PDCRG_PD1 PWR_PDCRG_PD1_Msk /*!< Port PG1 Pull-Down set */
11549#define PWR_PDCRG_PD2_Pos (2U)
11550#define PWR_PDCRG_PD2_Msk (0x1UL << PWR_PDCRG_PD2_Pos) /*!< 0x00000004 */
11551#define PWR_PDCRG_PD2 PWR_PDCRG_PD2_Msk /*!< Port PG2 Pull-Down set */
11552#define PWR_PDCRG_PD3_Pos (3U)
11553#define PWR_PDCRG_PD3_Msk (0x1UL << PWR_PDCRG_PD3_Pos) /*!< 0x00000008 */
11554#define PWR_PDCRG_PD3 PWR_PDCRG_PD3_Msk /*!< Port PG3 Pull-Down set */
11555#define PWR_PDCRG_PD4_Pos (4U)
11556#define PWR_PDCRG_PD4_Msk (0x1UL << PWR_PDCRG_PD4_Pos) /*!< 0x00000010 */
11557#define PWR_PDCRG_PD4 PWR_PDCRG_PD4_Msk /*!< Port PG4 Pull-Down set */
11558#define PWR_PDCRG_PD5_Pos (5U)
11559#define PWR_PDCRG_PD5_Msk (0x1UL << PWR_PDCRG_PD5_Pos) /*!< 0x00000020 */
11560#define PWR_PDCRG_PD5 PWR_PDCRG_PD5_Msk /*!< Port PG5 Pull-Down set */
11561#define PWR_PDCRG_PD6_Pos (6U)
11562#define PWR_PDCRG_PD6_Msk (0x1UL << PWR_PDCRG_PD6_Pos) /*!< 0x00000040 */
11563#define PWR_PDCRG_PD6 PWR_PDCRG_PD6_Msk /*!< Port PG6 Pull-Down set */
11564#define PWR_PDCRG_PD7_Pos (7U)
11565#define PWR_PDCRG_PD7_Msk (0x1UL << PWR_PDCRG_PD7_Pos) /*!< 0x00000080 */
11566#define PWR_PDCRG_PD7 PWR_PDCRG_PD7_Msk /*!< Port PG7 Pull-Down set */
11567#define PWR_PDCRG_PD8_Pos (8U)
11568#define PWR_PDCRG_PD8_Msk (0x1UL << PWR_PDCRG_PD8_Pos) /*!< 0x00000100 */
11569#define PWR_PDCRG_PD8 PWR_PDCRG_PD8_Msk /*!< Port PG8 Pull-Down set */
11570#define PWR_PDCRG_PD9_Pos (9U)
11571#define PWR_PDCRG_PD9_Msk (0x1UL << PWR_PDCRG_PD9_Pos) /*!< 0x00000200 */
11572#define PWR_PDCRG_PD9 PWR_PDCRG_PD9_Msk /*!< Port PG9 Pull-Down set */
11573#define PWR_PDCRG_PD10_Pos (10U)
11574#define PWR_PDCRG_PD10_Msk (0x1UL << PWR_PDCRG_PD10_Pos) /*!< 0x00000400 */
11575#define PWR_PDCRG_PD10 PWR_PDCRG_PD10_Msk /*!< Port PG10 Pull-Down set */
11576#define PWR_PDCRG_PD11_Pos (11U)
11577#define PWR_PDCRG_PD11_Msk (0x1UL << PWR_PDCRG_PD11_Pos) /*!< 0x00000800 */
11578#define PWR_PDCRG_PD11 PWR_PDCRG_PD11_Msk /*!< Port PG11 Pull-Down set */
11579#define PWR_PDCRG_PD12_Pos (12U)
11580#define PWR_PDCRG_PD12_Msk (0x1UL << PWR_PDCRG_PD12_Pos) /*!< 0x00001000 */
11581#define PWR_PDCRG_PD12 PWR_PDCRG_PD12_Msk /*!< Port PG12 Pull-Down set */
11582#define PWR_PDCRG_PD13_Pos (13U)
11583#define PWR_PDCRG_PD13_Msk (0x1UL << PWR_PDCRG_PD13_Pos) /*!< 0x00002000 */
11584#define PWR_PDCRG_PD13 PWR_PDCRG_PD13_Msk /*!< Port PG13 Pull-Down set */
11585#define PWR_PDCRG_PD14_Pos (14U)
11586#define PWR_PDCRG_PD14_Msk (0x1UL << PWR_PDCRG_PD14_Pos) /*!< 0x00004000 */
11587#define PWR_PDCRG_PD14 PWR_PDCRG_PD14_Msk /*!< Port PG14 Pull-Down set */
11588#define PWR_PDCRG_PD15_Pos (15U)
11589#define PWR_PDCRG_PD15_Msk (0x1UL << PWR_PDCRG_PD15_Pos) /*!< 0x00008000 */
11590#define PWR_PDCRG_PD15 PWR_PDCRG_PD15_Msk /*!< Port PG15 Pull-Down set */
11591
11592/******************** Bit definition for PWR_PUCRH register ********************/
11593#define PWR_PUCRH_PU0_Pos (0U)
11594#define PWR_PUCRH_PU0_Msk (0x1UL << PWR_PUCRH_PU0_Pos) /*!< 0x00000001 */
11595#define PWR_PUCRH_PU0 PWR_PUCRH_PU0_Msk /*!< Port PH0 Pull-Up set */
11596#define PWR_PUCRH_PU1_Pos (1U)
11597#define PWR_PUCRH_PU1_Msk (0x1UL << PWR_PUCRH_PU1_Pos) /*!< 0x00000002 */
11598#define PWR_PUCRH_PU1 PWR_PUCRH_PU1_Msk /*!< Port PH1 Pull-Up set */
11599#define PWR_PUCRH_PU2_Pos (2U)
11600#define PWR_PUCRH_PU2_Msk (0x1UL << PWR_PUCRH_PU2_Pos) /*!< 0x00000004 */
11601#define PWR_PUCRH_PU2 PWR_PUCRH_PU2_Msk /*!< Port PH2 Pull-Up set */
11602#define PWR_PUCRH_PU3_Pos (3U)
11603#define PWR_PUCRH_PU3_Msk (0x1UL << PWR_PUCRH_PU3_Pos) /*!< 0x00000008 */
11604#define PWR_PUCRH_PU3 PWR_PUCRH_PU3_Msk /*!< Port PH3 Pull-Up set */
11605
11606/******************** Bit definition for PWR_PDCRH register ********************/
11607#define PWR_PDCRH_PD0_Pos (0U)
11608#define PWR_PDCRH_PD0_Msk (0x1UL << PWR_PDCRH_PD0_Pos) /*!< 0x00000001 */
11609#define PWR_PDCRH_PD0 PWR_PDCRH_PD0_Msk /*!< Port PH0 Pull-Down set */
11610#define PWR_PDCRH_PD1_Pos (1U)
11611#define PWR_PDCRH_PD1_Msk (0x1UL << PWR_PDCRH_PD1_Pos) /*!< 0x00000002 */
11612#define PWR_PDCRH_PD1 PWR_PDCRH_PD1_Msk /*!< Port PH1 Pull-Down set */
11613#define PWR_PDCRH_PD2_Pos (2U)
11614#define PWR_PDCRH_PD2_Msk (0x1UL << PWR_PDCRH_PD2_Pos) /*!< 0x00000004 */
11615#define PWR_PDCRH_PD2 PWR_PDCRH_PD2_Msk /*!< Port PH2 Pull-Down set */
11616#define PWR_PDCRH_PD3_Pos (3U)
11617#define PWR_PDCRH_PD3_Msk (0x1UL << PWR_PDCRH_PD3_Pos) /*!< 0x00000008 */
11618#define PWR_PDCRH_PD3 PWR_PDCRH_PD3_Msk /*!< Port PH3 Pull-Down set */
11619
11620/******************** Bit definition for PWR_SECCFGR register ******************/
11621#define PWR_SECCFGR_WUPSEC_Pos (0U)
11622#define PWR_SECCFGR_WUPSEC_Msk (0x1FUL << PWR_SECCFGR_WUPSEC_Pos) /*!< 0x0000001F */
11623#define PWR_SECCFGR_WUPSEC PWR_SECCFGR_WUPSEC_Msk /*!< Secure Mode Wake-Up Pins */
11624#define PWR_SECCFGR_WUP1SEC_Pos (0U)
11625#define PWR_SECCFGR_WUP1SEC_Msk (0x1UL << PWR_SECCFGR_WUP1SEC_Pos) /*!< 0x00000001 */
11626#define PWR_SECCFGR_WUP1SEC PWR_SECCFGR_WUP1SEC_Msk /*!< Secure Mode Wake-Up Pin 1 */
11627#define PWR_SECCFGR_WUP2SEC_Pos (1U)
11628#define PWR_SECCFGR_WUP2SEC_Msk (0x1UL << PWR_SECCFGR_WUP2SEC_Pos) /*!< 0x00000002 */
11629#define PWR_SECCFGR_WUP2SEC PWR_SECCFGR_WUP2SEC_Msk /*!< Secure Mode Wake-Up Pin 2 */
11630#define PWR_SECCFGR_WUP3SEC_Pos (2U)
11631#define PWR_SECCFGR_WUP3SEC_Msk (0x1UL << PWR_SECCFGR_WUP3SEC_Pos) /*!< 0x00000004 */
11632#define PWR_SECCFGR_WUP3SEC PWR_SECCFGR_WUP3SEC_Msk /*!< Secure Mode Wake-Up Pin 3 */
11633#define PWR_SECCFGR_WUP4SEC_Pos (3U)
11634#define PWR_SECCFGR_WUP4SEC_Msk (0x1UL << PWR_SECCFGR_WUP4SEC_Pos) /*!< 0x00000008 */
11635#define PWR_SECCFGR_WUP4SEC PWR_SECCFGR_WUP4SEC_Msk /*!< Secure Mode Wake-Up Pin 4 */
11636#define PWR_SECCFGR_WUP5SEC_Pos (4U)
11637#define PWR_SECCFGR_WUP5SEC_Msk (0x1UL << PWR_SECCFGR_WUP5SEC_Pos) /*!< 0x00000010 */
11638#define PWR_SECCFGR_WUP5SEC PWR_SECCFGR_WUP5SEC_Msk /*!< Secure Mode Wake-Up Pin 5 */
11639#define PWR_SECCFGR_LPMSEC_Pos (8U)
11640#define PWR_SECCFGR_LPMSEC_Msk (0x1UL << PWR_SECCFGR_LPMSEC_Pos) /*!< 0x00000100 */
11641#define PWR_SECCFGR_LPMSEC PWR_SECCFGR_LPMSEC_Msk /*!< Secure Mode Low Power Modes */
11642#define PWR_SECCFGR_VDMSEC_Pos (9U)
11643#define PWR_SECCFGR_VDMSEC_Msk (0x1UL << PWR_SECCFGR_VDMSEC_Pos) /*!< 0x00000200 */
11644#define PWR_SECCFGR_VDMSEC PWR_SECCFGR_VDMSEC_Msk /*!< Secure Mode Voltage Detection and Monitoring */
11645#define PWR_SECCFGR_VBSEC_Pos (10U)
11646#define PWR_SECCFGR_VBSEC_Msk (0x1UL << PWR_SECCFGR_VBSEC_Pos) /*!< 0x00000400 */
11647#define PWR_SECCFGR_VBSEC PWR_SECCFGR_VBSEC_Msk /*!< Secure Mode VBAT */
11648#define PWR_SECCFGR_APCSEC_Pos (11U)
11649#define PWR_SECCFGR_APCSEC_Msk (0x1UL << PWR_SECCFGR_APCSEC_Pos) /*!< 0x00000800 */
11650#define PWR_SECCFGR_APCSEC PWR_SECCFGR_APCSEC_Msk /*!< Secure Mode Pull-Up/Down Control */
11651
11652/******************** Bit definition for PWR_PRIVCFGR register *****************/
11653#define PWR_PRIVCFGR_PRIV_Pos (0U)
11654#define PWR_PRIVCFGR_PRIV_Msk (0x1UL << PWR_PRIVCFGR_PRIV_Pos) /*!< 0x00000001 */
11655#define PWR_PRIVCFGR_PRIV PWR_PRIVCFGR_PRIV_Msk /*!< Privileged access protection */
11656
11657/******************************************************************************/
11658/* */
11659/* Reset and Clock Control */
11660/* */
11661/******************************************************************************/
11662/******************** Bit definition for RCC_CR register ********************/
11663#define RCC_CR_MSION_Pos (0U)
11664#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000001 */
11665#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */
11666#define RCC_CR_MSIRDY_Pos (1U)
11667#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */
11668#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
11669#define RCC_CR_MSIPLLEN_Pos (2U)
11670#define RCC_CR_MSIPLLEN_Msk (0x1UL << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */
11671#define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */
11672#define RCC_CR_MSIRGSEL_Pos (3U)
11673#define RCC_CR_MSIRGSEL_Msk (0x1UL << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */
11674#define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */
11675
11676/*!< MSIRANGE configuration : 12 frequency ranges available */
11677#define RCC_CR_MSIRANGE_Pos (4U)
11678#define RCC_CR_MSIRANGE_Msk (0xFUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */
11679#define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */
11680#define RCC_CR_MSIRANGE_0 (0x0UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */
11681#define RCC_CR_MSIRANGE_1 (0x1UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */
11682#define RCC_CR_MSIRANGE_2 (0x2UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */
11683#define RCC_CR_MSIRANGE_3 (0x3UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */
11684#define RCC_CR_MSIRANGE_4 (0x4UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */
11685#define RCC_CR_MSIRANGE_5 (0x5UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */
11686#define RCC_CR_MSIRANGE_6 (0x6UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */
11687#define RCC_CR_MSIRANGE_7 (0x7UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */
11688#define RCC_CR_MSIRANGE_8 (0x8UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */
11689#define RCC_CR_MSIRANGE_9 (0x9UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */
11690#define RCC_CR_MSIRANGE_10 (0xAUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */
11691#define RCC_CR_MSIRANGE_11 (0xBUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */
11692
11693#define RCC_CR_HSION_Pos (8U)
11694#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */
11695#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
11696#define RCC_CR_HSIKERON_Pos (9U)
11697#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
11698#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
11699#define RCC_CR_HSIRDY_Pos (10U)
11700#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
11701#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
11702#define RCC_CR_HSIASFS_Pos (11U)
11703#define RCC_CR_HSIASFS_Msk (0x1UL << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */
11704#define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */
11705
11706#define RCC_CR_HSEON_Pos (16U)
11707#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
11708#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
11709#define RCC_CR_HSERDY_Pos (17U)
11710#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
11711#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
11712#define RCC_CR_HSEBYP_Pos (18U)
11713#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
11714#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
11715#define RCC_CR_CSSON_Pos (19U)
11716#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
11717#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
11718
11719#define RCC_CR_PLLON_Pos (24U)
11720#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
11721#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
11722#define RCC_CR_PLLRDY_Pos (25U)
11723#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
11724#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
11725#define RCC_CR_PLLSAI1ON_Pos (26U)
11726#define RCC_CR_PLLSAI1ON_Msk (0x1UL << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
11727#define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
11728#define RCC_CR_PLLSAI1RDY_Pos (27U)
11729#define RCC_CR_PLLSAI1RDY_Msk (0x1UL << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */
11730#define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */
11731#define RCC_CR_PLLSAI2ON_Pos (28U)
11732#define RCC_CR_PLLSAI2ON_Msk (0x1UL << RCC_CR_PLLSAI2ON_Pos) /*!< 0x10000000 */
11733#define RCC_CR_PLLSAI2ON RCC_CR_PLLSAI2ON_Msk /*!< SAI2 PLL enable */
11734#define RCC_CR_PLLSAI2RDY_Pos (29U)
11735#define RCC_CR_PLLSAI2RDY_Msk (0x1UL << RCC_CR_PLLSAI2RDY_Pos) /*!< 0x20000000 */
11736#define RCC_CR_PLLSAI2RDY RCC_CR_PLLSAI2RDY_Msk /*!< SAI2 PLL ready */
11737#define RCC_CR_PRIV_Pos (31U)
11738#define RCC_CR_PRIV_Msk (0x1UL << RCC_CR_PRIV_Pos) /*!< 0x80000000 */
11739#define RCC_CR_PRIV RCC_CR_PRIV_Msk /*!< RCC Privilege enable */
11740
11741/******************** Bit definition for RCC_ICSCR register ***************/
11742/*!< MSICAL configuration */
11743#define RCC_ICSCR_MSICAL_Pos (0U)
11744#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */
11745#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */
11746#define RCC_ICSCR_MSICAL_0 (0x01UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */
11747#define RCC_ICSCR_MSICAL_1 (0x02UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */
11748#define RCC_ICSCR_MSICAL_2 (0x04UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */
11749#define RCC_ICSCR_MSICAL_3 (0x08UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */
11750#define RCC_ICSCR_MSICAL_4 (0x10UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */
11751#define RCC_ICSCR_MSICAL_5 (0x20UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */
11752#define RCC_ICSCR_MSICAL_6 (0x40UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */
11753#define RCC_ICSCR_MSICAL_7 (0x80UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */
11754
11755/*!< MSITRIM configuration */
11756#define RCC_ICSCR_MSITRIM_Pos (8U)
11757#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
11758#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */
11759#define RCC_ICSCR_MSITRIM_0 (0x01UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
11760#define RCC_ICSCR_MSITRIM_1 (0x02UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
11761#define RCC_ICSCR_MSITRIM_2 (0x04UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
11762#define RCC_ICSCR_MSITRIM_3 (0x08UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
11763#define RCC_ICSCR_MSITRIM_4 (0x10UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
11764#define RCC_ICSCR_MSITRIM_5 (0x20UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
11765#define RCC_ICSCR_MSITRIM_6 (0x40UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
11766#define RCC_ICSCR_MSITRIM_7 (0x80UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
11767
11768/*!< HSICAL configuration */
11769#define RCC_ICSCR_HSICAL_Pos (16U)
11770#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
11771#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
11772#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
11773#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
11774#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
11775#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
11776#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
11777#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
11778#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
11779#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
11780
11781/*!< HSITRIM configuration */
11782#define RCC_ICSCR_HSITRIM_Pos (24U)
11783#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
11784#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
11785#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
11786#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
11787#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
11788#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
11789#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
11790#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
11791#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
11792
11793/******************** Bit definition for RCC_CFGR register ******************/
11794/*!< SW configuration */
11795#define RCC_CFGR_SW_Pos (0U)
11796#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
11797#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
11798#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
11799#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
11800
11801#define RCC_CFGR_SW_MSI (0x00000000UL) /*!< MSI oscillator selection as system clock */
11802#define RCC_CFGR_SW_HSI (0x00000001UL) /*!< HSI16 oscillator selection as system clock */
11803#define RCC_CFGR_SW_HSE (0x00000002UL) /*!< HSE oscillator selection as system clock */
11804#define RCC_CFGR_SW_PLL (0x00000003UL) /*!< PLL selection as system clock */
11805
11806/*!< SWS configuration */
11807#define RCC_CFGR_SWS_Pos (2U)
11808#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
11809#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
11810#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
11811#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
11812
11813#define RCC_CFGR_SWS_MSI (0x00000000UL) /*!< MSI oscillator used as system clock */
11814#define RCC_CFGR_SWS_HSI (0x00000004UL) /*!< HSI16 oscillator used as system clock */
11815#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE oscillator used as system clock */
11816#define RCC_CFGR_SWS_PLL (0x0000000CUL) /*!< PLL used as system clock */
11817
11818/*!< HPRE configuration */
11819#define RCC_CFGR_HPRE_Pos (4U)
11820#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
11821#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
11822#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
11823#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
11824#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
11825#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
11826
11827#define RCC_CFGR_HPRE_DIV1 (0x00000000UL) /*!< SYSCLK not divided */
11828#define RCC_CFGR_HPRE_DIV2 (0x00000080UL) /*!< SYSCLK divided by 2 */
11829#define RCC_CFGR_HPRE_DIV4 (0x00000090UL) /*!< SYSCLK divided by 4 */
11830#define RCC_CFGR_HPRE_DIV8 (0x000000A0UL) /*!< SYSCLK divided by 8 */
11831#define RCC_CFGR_HPRE_DIV16 (0x000000B0UL) /*!< SYSCLK divided by 16 */
11832#define RCC_CFGR_HPRE_DIV64 (0x000000C0UL) /*!< SYSCLK divided by 64 */
11833#define RCC_CFGR_HPRE_DIV128 (0x000000D0UL) /*!< SYSCLK divided by 128 */
11834#define RCC_CFGR_HPRE_DIV256 (0x000000E0UL) /*!< SYSCLK divided by 256 */
11835#define RCC_CFGR_HPRE_DIV512 (0x000000F0UL) /*!< SYSCLK divided by 512 */
11836
11837/*!< PPRE1 configuration */
11838#define RCC_CFGR_PPRE1_Pos (8U)
11839#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
11840#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
11841#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
11842#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
11843#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
11844
11845#define RCC_CFGR_PPRE1_DIV1 (0x00000000UL) /*!< HCLK not divided */
11846#define RCC_CFGR_PPRE1_DIV2 (0x00000400UL) /*!< HCLK divided by 2 */
11847#define RCC_CFGR_PPRE1_DIV4 (0x00000500UL) /*!< HCLK divided by 4 */
11848#define RCC_CFGR_PPRE1_DIV8 (0x00000600UL) /*!< HCLK divided by 8 */
11849#define RCC_CFGR_PPRE1_DIV16 (0x00000700UL) /*!< HCLK divided by 16 */
11850
11851/*!< PPRE2 configuration */
11852#define RCC_CFGR_PPRE2_Pos (11U)
11853#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
11854#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
11855#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
11856#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
11857#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
11858
11859#define RCC_CFGR_PPRE2_DIV1 (0x00000000UL) /*!< HCLK not divided */
11860#define RCC_CFGR_PPRE2_DIV2 (0x00002000UL) /*!< HCLK divided by 2 */
11861#define RCC_CFGR_PPRE2_DIV4 (0x00002800UL) /*!< HCLK divided by 4 */
11862#define RCC_CFGR_PPRE2_DIV8 (0x00003000UL) /*!< HCLK divided by 8 */
11863#define RCC_CFGR_PPRE2_DIV16 (0x00003800UL) /*!< HCLK divided by 16 */
11864
11865#define RCC_CFGR_STOPWUCK_Pos (15U)
11866#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
11867#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
11868
11869/*!< MCOSEL configuration */
11870#define RCC_CFGR_MCOSEL_Pos (24U)
11871#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
11872#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
11873#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
11874#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
11875#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
11876#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
11877
11878#define RCC_CFGR_MCOPRE_Pos (28U)
11879#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
11880#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
11881#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
11882#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
11883#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
11884
11885#define RCC_CFGR_MCOPRE_DIV1 (0x00000000UL) /*!< MCO is divided by 1 */
11886#define RCC_CFGR_MCOPRE_DIV2 (0x10000000UL) /*!< MCO is divided by 2 */
11887#define RCC_CFGR_MCOPRE_DIV4 (0x20000000UL) /*!< MCO is divided by 4 */
11888#define RCC_CFGR_MCOPRE_DIV8 (0x30000000UL) /*!< MCO is divided by 8 */
11889#define RCC_CFGR_MCOPRE_DIV16 (0x40000000UL) /*!< MCO is divided by 16 */
11890
11891/******************** Bit definition for RCC_PLLCFGR register ***************/
11892#define RCC_PLLCFGR_PLLSRC_Pos (0U)
11893#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
11894#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
11895#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
11896#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
11897
11898#define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
11899#define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_MSI_Pos)/*!< 0x00000001 */
11900#define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */
11901#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
11902#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
11903#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
11904#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
11905#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
11906#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
11907
11908#define RCC_PLLCFGR_PLLM_Pos (4U)
11909#define RCC_PLLCFGR_PLLM_Msk (0xFUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x000000F0 */
11910#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
11911#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
11912#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
11913#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
11914#define RCC_PLLCFGR_PLLM_3 (0x8UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000080 */
11915
11916#define RCC_PLLCFGR_PLLN_Pos (8U)
11917#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
11918#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
11919#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
11920#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
11921#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
11922#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
11923#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
11924#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
11925#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
11926
11927#define RCC_PLLCFGR_PLLPEN_Pos (16U)
11928#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
11929#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
11930#define RCC_PLLCFGR_PLLP_Pos (17U)
11931#define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
11932#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
11933#define RCC_PLLCFGR_PLLQEN_Pos (20U)
11934#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
11935#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
11936
11937#define RCC_PLLCFGR_PLLQ_Pos (21U)
11938#define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
11939#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
11940#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
11941#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
11942
11943#define RCC_PLLCFGR_PLLREN_Pos (24U)
11944#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
11945#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
11946#define RCC_PLLCFGR_PLLR_Pos (25U)
11947#define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
11948#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
11949#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
11950#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
11951
11952#define RCC_PLLCFGR_PLLPDIV_Pos (27U)
11953#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
11954#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
11955#define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
11956#define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
11957#define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
11958#define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
11959#define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
11960
11961/******************** Bit definition for RCC_PLLSAI1CFGR register ************/
11962#define RCC_PLLSAI1CFGR_PLLSAI1SRC_Pos (0U)
11963#define RCC_PLLSAI1CFGR_PLLSAI1SRC_Msk (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_Pos)/*!< 0x00000003 */
11964#define RCC_PLLSAI1CFGR_PLLSAI1SRC RCC_PLLSAI1CFGR_PLLSAI1SRC_Msk
11965#define RCC_PLLSAI1CFGR_PLLSAI1SRC_0 (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_Pos)/*!< 0x00000001 */
11966#define RCC_PLLSAI1CFGR_PLLSAI1SRC_1 (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_Pos)/*!< 0x00000002 */
11967
11968#define RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI_Pos (0U)
11969#define RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI_Pos)/*!< 0x00000001 */
11970#define RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI_Msk /*!< MSI oscillator source clock selected */
11971#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI_Pos (1U)
11972#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI_Pos)/*!< 0x00000002 */
11973#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
11974#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE_Pos (0U)
11975#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE_Msk (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE_Pos)/*!< 0x00000003 */
11976#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE_Msk /*!< HSE oscillator source clock selected */
11977
11978#define RCC_PLLSAI1CFGR_PLLSAI1M_Pos (4U)
11979#define RCC_PLLSAI1CFGR_PLLSAI1M_Msk (0xFUL << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)/*!< 0x000000F0 */
11980#define RCC_PLLSAI1CFGR_PLLSAI1M RCC_PLLSAI1CFGR_PLLSAI1M_Msk
11981#define RCC_PLLSAI1CFGR_PLLSAI1M_0 (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)/*!< 0x00000010 */
11982#define RCC_PLLSAI1CFGR_PLLSAI1M_1 (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)/*!< 0x00000020 */
11983#define RCC_PLLSAI1CFGR_PLLSAI1M_2 (0x4UL << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)/*!< 0x00000040 */
11984#define RCC_PLLSAI1CFGR_PLLSAI1M_3 (0x8UL << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)/*!< 0x00000080 */
11985
11986#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
11987#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FUL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)/*!< 0x00007F00 */
11988#define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
11989#define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)/*!< 0x00000100 */
11990#define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)/*!< 0x00000200 */
11991#define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)/*!< 0x00000400 */
11992#define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)/*!< 0x00000800 */
11993#define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)/*!< 0x00001000 */
11994#define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)/*!< 0x00002000 */
11995#define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)/*!< 0x00004000 */
11996
11997#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
11998#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos)/*!< 0x00010000 */
11999#define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
12000#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
12001#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)/*!< 0x00020000 */
12002#define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
12003
12004#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
12005#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos)/*!< 0x00100000 */
12006#define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
12007#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
12008#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)/*!< 0x00600000 */
12009#define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
12010#define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)/*!< 0x00200000 */
12011#define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)/*!< 0x00400000 */
12012
12013#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
12014#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos)/*!< 0x01000000 */
12015#define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
12016#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
12017#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)/*!< 0x06000000 */
12018#define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
12019#define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)/*!< 0x02000000 */
12020#define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)/*!< 0x04000000 */
12021
12022#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos (27U)
12023#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk (0x1FUL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)/*!< 0xF8000000 */
12024#define RCC_PLLSAI1CFGR_PLLSAI1PDIV RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk
12025#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 (0x01UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)/*!< 0x08000000 */
12026#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 (0x02UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)/*!< 0x10000000 */
12027#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 (0x04UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)/*!< 0x20000000 */
12028#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 (0x08UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)/*!< 0x40000000 */
12029#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 (0x10UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)/*!< 0x80000000 */
12030
12031/******************** Bit definition for RCC_PLLSAI2CFGR register ************/
12032#define RCC_PLLSAI2CFGR_PLLSAI2SRC_Pos (0U)
12033#define RCC_PLLSAI2CFGR_PLLSAI2SRC_Msk (0x3UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_Pos)/*!< 0x00000003 */
12034#define RCC_PLLSAI2CFGR_PLLSAI2SRC RCC_PLLSAI2CFGR_PLLSAI2SRC_Msk
12035#define RCC_PLLSAI2CFGR_PLLSAI2SRC_0 (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_Pos)/*!< 0x00000001 */
12036#define RCC_PLLSAI2CFGR_PLLSAI2SRC_1 (0x2UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_Pos)/*!< 0x00000002 */
12037
12038#define RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI_Pos (0U)
12039#define RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI_Msk (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI_Pos)/*!< 0x00000001 */
12040#define RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI_Msk /*!< MSI oscillator source clock selected */
12041#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI_Pos (1U)
12042#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI_Msk (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI_Pos)/*!< 0x00000002 */
12043#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
12044#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE_Pos (0U)
12045#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE_Msk (0x3UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE_Pos)/*!< 0x00000003 */
12046#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE_Msk /*!< HSE oscillator source clock selected */
12047
12048#define RCC_PLLSAI2CFGR_PLLSAI2M_Pos (4U)
12049#define RCC_PLLSAI2CFGR_PLLSAI2M_Msk (0xFUL << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)/*!< 0x000000F0 */
12050#define RCC_PLLSAI2CFGR_PLLSAI2M RCC_PLLSAI2CFGR_PLLSAI2M_Msk
12051#define RCC_PLLSAI2CFGR_PLLSAI2M_0 (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)/*!< 0x00000010 */
12052#define RCC_PLLSAI2CFGR_PLLSAI2M_1 (0x2UL << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)/*!< 0x00000020 */
12053#define RCC_PLLSAI2CFGR_PLLSAI2M_2 (0x4UL << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)/*!< 0x00000040 */
12054#define RCC_PLLSAI2CFGR_PLLSAI2M_3 (0x8UL << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)/*!< 0x00000080 */
12055
12056#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos (8U)
12057#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk (0x7FUL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)/*!< 0x00007F00 */
12058#define RCC_PLLSAI2CFGR_PLLSAI2N RCC_PLLSAI2CFGR_PLLSAI2N_Msk
12059#define RCC_PLLSAI2CFGR_PLLSAI2N_0 (0x01UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)/*!< 0x00000100 */
12060#define RCC_PLLSAI2CFGR_PLLSAI2N_1 (0x02UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)/*!< 0x00000200 */
12061#define RCC_PLLSAI2CFGR_PLLSAI2N_2 (0x04UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)/*!< 0x00000400 */
12062#define RCC_PLLSAI2CFGR_PLLSAI2N_3 (0x08UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)/*!< 0x00000800 */
12063#define RCC_PLLSAI2CFGR_PLLSAI2N_4 (0x10UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)/*!< 0x00001000 */
12064#define RCC_PLLSAI2CFGR_PLLSAI2N_5 (0x20UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)/*!< 0x00002000 */
12065#define RCC_PLLSAI2CFGR_PLLSAI2N_6 (0x40UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)/*!< 0x00004000 */
12066
12067#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos (16U)
12068#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos)/*!< 0x00010000 */
12069#define RCC_PLLSAI2CFGR_PLLSAI2PEN RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk
12070#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos (17U)
12071#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)/*!< 0x00020000 */
12072#define RCC_PLLSAI2CFGR_PLLSAI2P RCC_PLLSAI2CFGR_PLLSAI2P_Msk
12073
12074#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos (27U)
12075#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk (0x1FUL << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)/*!< 0xF8000000 */
12076#define RCC_PLLSAI2CFGR_PLLSAI2PDIV RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk
12077#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_0 (0x01UL << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)/*!< 0x08000000 */
12078#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_1 (0x02UL << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)/*!< 0x10000000 */
12079#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_2 (0x04UL << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)/*!< 0x20000000 */
12080#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_3 (0x08UL << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)/*!< 0x40000000 */
12081#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_4 (0x10UL << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)/*!< 0x80000000 */
12082
12083/******************** Bit definition for RCC_CIER register ******************/
12084#define RCC_CIER_LSIRDYIE_Pos (0U)
12085#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
12086#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
12087#define RCC_CIER_LSERDYIE_Pos (1U)
12088#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
12089#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
12090#define RCC_CIER_MSIRDYIE_Pos (2U)
12091#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */
12092#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
12093#define RCC_CIER_HSIRDYIE_Pos (3U)
12094#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
12095#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
12096#define RCC_CIER_HSERDYIE_Pos (4U)
12097#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
12098#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
12099#define RCC_CIER_PLLRDYIE_Pos (5U)
12100#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
12101#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
12102#define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
12103#define RCC_CIER_PLLSAI1RDYIE_Msk (0x1UL << RCC_CIER_PLLSAI1RDYIE_Pos)/*!< 0x00000040 */
12104#define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
12105#define RCC_CIER_PLLSAI2RDYIE_Pos (7U)
12106#define RCC_CIER_PLLSAI2RDYIE_Msk (0x1UL << RCC_CIER_PLLSAI2RDYIE_Pos)/*!< 0x00000080 */
12107#define RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE_Msk
12108#define RCC_CIER_HSI48RDYIE_Pos (10U)
12109#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
12110#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
12111
12112/******************** Bit definition for RCC_CIFR register ****************/
12113#define RCC_CIFR_LSIRDYF_Pos (0U)
12114#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
12115#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
12116#define RCC_CIFR_LSERDYF_Pos (1U)
12117#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
12118#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
12119#define RCC_CIFR_MSIRDYF_Pos (2U)
12120#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */
12121#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
12122#define RCC_CIFR_HSIRDYF_Pos (3U)
12123#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
12124#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
12125#define RCC_CIFR_HSERDYF_Pos (4U)
12126#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
12127#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
12128#define RCC_CIFR_PLLRDYF_Pos (5U)
12129#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
12130#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
12131#define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
12132#define RCC_CIFR_PLLSAI1RDYF_Msk (0x1UL << RCC_CIFR_PLLSAI1RDYF_Pos)/*!< 0x00000040 */
12133#define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
12134#define RCC_CIFR_PLLSAI2RDYF_Pos (7U)
12135#define RCC_CIFR_PLLSAI2RDYF_Msk (0x1UL << RCC_CIFR_PLLSAI2RDYF_Pos)/*!< 0x00000080 */
12136#define RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF_Msk
12137#define RCC_CIFR_CSSF_Pos (8U)
12138#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
12139#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
12140#define RCC_CIFR_HSI48RDYF_Pos (10U)
12141#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
12142#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
12143
12144/******************** Bit definition for RCC_CICR register ****************/
12145#define RCC_CICR_LSIRDYC_Pos (0U)
12146#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
12147#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
12148#define RCC_CICR_LSERDYC_Pos (1U)
12149#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
12150#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
12151#define RCC_CICR_MSIRDYC_Pos (2U)
12152#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */
12153#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
12154#define RCC_CICR_HSIRDYC_Pos (3U)
12155#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
12156#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
12157#define RCC_CICR_HSERDYC_Pos (4U)
12158#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
12159#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
12160#define RCC_CICR_PLLRDYC_Pos (5U)
12161#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
12162#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
12163#define RCC_CICR_PLLSAI1RDYC_Pos (6U)
12164#define RCC_CICR_PLLSAI1RDYC_Msk (0x1UL << RCC_CICR_PLLSAI1RDYC_Pos)/*!< 0x00000040 */
12165#define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
12166#define RCC_CICR_PLLSAI2RDYC_Pos (7U)
12167#define RCC_CICR_PLLSAI2RDYC_Msk (0x1UL << RCC_CICR_PLLSAI2RDYC_Pos)/*!< 0x00000080 */
12168#define RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC_Msk
12169#define RCC_CICR_CSSC_Pos (8U)
12170#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
12171#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
12172#define RCC_CICR_HSI48RDYC_Pos (10U)
12173#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
12174#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
12175
12176/******************** Bit definition for RCC_AHB1RSTR register **************/
12177#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
12178#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
12179#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
12180#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
12181#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
12182#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
12183#define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)
12184#define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
12185#define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk
12186#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
12187#define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
12188#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
12189#define RCC_AHB1RSTR_CRCRST_Pos (12U)
12190#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
12191#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
12192#define RCC_AHB1RSTR_TSCRST_Pos (16U)
12193#define RCC_AHB1RSTR_TSCRST_Msk (0x1UL << RCC_AHB1RSTR_TSCRST_Pos)/*!< 0x00010000 */
12194#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
12195
12196/******************** Bit definition for RCC_AHB2RSTR register **************/
12197#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
12198#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
12199#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
12200#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
12201#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
12202#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
12203#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
12204#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
12205#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
12206#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
12207#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
12208#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
12209#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
12210#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
12211#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
12212#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
12213#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
12214#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
12215#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
12216#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
12217#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
12218#define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
12219#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)/*!< 0x00000080 */
12220#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
12221#define RCC_AHB2RSTR_ADCRST_Pos (13U)
12222#define RCC_AHB2RSTR_ADCRST_Msk (0x1UL << RCC_AHB2RSTR_ADCRST_Pos)/*!< 0x00002000 */
12223#define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
12224#define RCC_AHB2RSTR_AESRST_Pos (16U)
12225#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos)/*!< 0x00010000 */
12226#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk
12227#define RCC_AHB2RSTR_HASHRST_Pos (17U)
12228#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)/*!< 0x00020000 */
12229#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
12230#define RCC_AHB2RSTR_RNGRST_Pos (18U)
12231#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x00040000 */
12232#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
12233#define RCC_AHB2RSTR_PKARST_Pos (19U)
12234#define RCC_AHB2RSTR_PKARST_Msk (0x1UL << RCC_AHB2RSTR_PKARST_Pos)/*!< 0x00080000 */
12235#define RCC_AHB2RSTR_PKARST RCC_AHB2RSTR_PKARST_Msk
12236#define RCC_AHB2RSTR_OTFDEC1RST_Pos (21U)
12237#define RCC_AHB2RSTR_OTFDEC1RST_Msk (0x1UL << RCC_AHB2RSTR_OTFDEC1RST_Pos)/*!< 0x00200000 */
12238#define RCC_AHB2RSTR_OTFDEC1RST RCC_AHB2RSTR_OTFDEC1RST_Msk
12239#define RCC_AHB2RSTR_SDMMC1RST_Pos (22U)
12240#define RCC_AHB2RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC1RST_Pos)/*!< 0x00400000 */
12241#define RCC_AHB2RSTR_SDMMC1RST RCC_AHB2RSTR_SDMMC1RST_Msk
12242
12243/******************** Bit definition for RCC_AHB3RSTR register **************/
12244#define RCC_AHB3RSTR_FMCRST_Pos (0U)
12245#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)/*!< 0x00000001 */
12246#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
12247#define RCC_AHB3RSTR_OSPI1RST_Pos (8U)
12248#define RCC_AHB3RSTR_OSPI1RST_Msk (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos)/*!< 0x00000100 */
12249#define RCC_AHB3RSTR_OSPI1RST RCC_AHB3RSTR_OSPI1RST_Msk
12250
12251/******************** Bit definition for RCC_APB1RSTR1 register **************/
12252#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
12253#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
12254#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
12255#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
12256#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
12257#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
12258#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
12259#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
12260#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
12261#define RCC_APB1RSTR1_TIM5RST_Pos (3U)
12262#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)/*!< 0x00000008 */
12263#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
12264#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
12265#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
12266#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
12267#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
12268#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
12269#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
12270#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
12271#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
12272#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
12273#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
12274#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
12275#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
12276#define RCC_APB1RSTR1_USART2RST_Pos (17U)
12277#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
12278#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
12279#define RCC_APB1RSTR1_USART3RST_Pos (18U)
12280#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
12281#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
12282#define RCC_APB1RSTR1_UART4RST_Pos (19U)
12283#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
12284#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
12285#define RCC_APB1RSTR1_UART5RST_Pos (20U)
12286#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)/*!< 0x00100000 */
12287#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
12288#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
12289#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
12290#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
12291#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
12292#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
12293#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
12294#define RCC_APB1RSTR1_I2C3RST_Pos (23U)
12295#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x00800000 */
12296#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
12297#define RCC_APB1RSTR1_CRSRST_Pos (24U)
12298#define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x01000000 */
12299#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
12300#define RCC_APB1RSTR1_PWRRST_Pos (28U)
12301#define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
12302#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
12303#define RCC_APB1RSTR1_DAC1RST_Pos (29U)
12304#define RCC_APB1RSTR1_DAC1RST_Msk (0x1UL << RCC_APB1RSTR1_DAC1RST_Pos)/*!< 0x20000000 */
12305#define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
12306#define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
12307#define RCC_APB1RSTR1_OPAMPRST_Msk (0x1UL << RCC_APB1RSTR1_OPAMPRST_Pos)/*!< 0x40000000 */
12308#define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
12309#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
12310#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
12311#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
12312
12313/******************** Bit definition for RCC_APB1RSTR2 register **************/
12314#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
12315#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
12316#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
12317#define RCC_APB1RSTR2_I2C4RST_Pos (1U)
12318#define RCC_APB1RSTR2_I2C4RST_Msk (0x1UL << RCC_APB1RSTR2_I2C4RST_Pos)/*!< 0x00000002 */
12319#define RCC_APB1RSTR2_I2C4RST RCC_APB1RSTR2_I2C4RST_Msk
12320#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
12321#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)/*!< 0x00000020 */
12322#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
12323#define RCC_APB1RSTR2_LPTIM3RST_Pos (6U)
12324#define RCC_APB1RSTR2_LPTIM3RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM3RST_Pos)/*!< 0x00000040 */
12325#define RCC_APB1RSTR2_LPTIM3RST RCC_APB1RSTR2_LPTIM3RST_Msk
12326#define RCC_APB1RSTR2_FDCAN1RST_Pos (9U)
12327#define RCC_APB1RSTR2_FDCAN1RST_Msk (0x1UL << RCC_APB1RSTR2_FDCAN1RST_Pos)/*!< 0x00000200 */
12328#define RCC_APB1RSTR2_FDCAN1RST RCC_APB1RSTR2_FDCAN1RST_Msk
12329#define RCC_APB1RSTR2_USBFSRST_Pos (21U)
12330#define RCC_APB1RSTR2_USBFSRST_Msk (0x1UL << RCC_APB1RSTR2_USBFSRST_Pos)/*!< 0x00200000 */
12331#define RCC_APB1RSTR2_USBFSRST RCC_APB1RSTR2_USBFSRST_Msk
12332#define RCC_APB1RSTR2_UCPD1RST_Pos (23U)
12333#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00800000 */
12334#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk
12335
12336/******************** Bit definition for RCC_APB2RSTR register **************/
12337#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
12338#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
12339#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
12340#define RCC_APB2RSTR_TIM1RST_Pos (11U)
12341#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
12342#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
12343#define RCC_APB2RSTR_SPI1RST_Pos (12U)
12344#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
12345#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
12346#define RCC_APB2RSTR_TIM8RST_Pos (13U)
12347#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
12348#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
12349#define RCC_APB2RSTR_USART1RST_Pos (14U)
12350#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
12351#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
12352#define RCC_APB2RSTR_TIM15RST_Pos (16U)
12353#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
12354#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
12355#define RCC_APB2RSTR_TIM16RST_Pos (17U)
12356#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
12357#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
12358#define RCC_APB2RSTR_TIM17RST_Pos (18U)
12359#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
12360#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
12361#define RCC_APB2RSTR_SAI1RST_Pos (21U)
12362#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
12363#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
12364#define RCC_APB2RSTR_SAI2RST_Pos (22U)
12365#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)/*!< 0x00400000 */
12366#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
12367#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
12368#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)/*!< 0x01000000 */
12369#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
12370
12371/******************** Bit definition for RCC_AHB1ENR register ***************/
12372#define RCC_AHB1ENR_DMA1EN_Pos (0U)
12373#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
12374#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
12375#define RCC_AHB1ENR_DMA2EN_Pos (1U)
12376#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
12377#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
12378#define RCC_AHB1ENR_DMAMUX1EN_Pos (2U)
12379#define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
12380#define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk
12381#define RCC_AHB1ENR_FLASHEN_Pos (8U)
12382#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
12383#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
12384#define RCC_AHB1ENR_CRCEN_Pos (12U)
12385#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
12386#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
12387#define RCC_AHB1ENR_TSCEN_Pos (16U)
12388#define RCC_AHB1ENR_TSCEN_Msk (0x1UL << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
12389#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
12390#define RCC_AHB1ENR_GTZCEN_Pos (22U)
12391#define RCC_AHB1ENR_GTZCEN_Msk (0x1UL << RCC_AHB1ENR_GTZCEN_Pos)/*!< 0x00400000 */
12392#define RCC_AHB1ENR_GTZCEN RCC_AHB1ENR_GTZCEN_Msk
12393
12394/******************** Bit definition for RCC_AHB2ENR register ***************/
12395#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
12396#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
12397#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
12398#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
12399#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
12400#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
12401#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
12402#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
12403#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
12404#define RCC_AHB2ENR_GPIODEN_Pos (3U)
12405#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
12406#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
12407#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
12408#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
12409#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
12410#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
12411#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
12412#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
12413#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
12414#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
12415#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
12416#define RCC_AHB2ENR_GPIOHEN_Pos (7U)
12417#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos)/*!< 0x00000080 */
12418#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
12419#define RCC_AHB2ENR_ADCEN_Pos (13U)
12420#define RCC_AHB2ENR_ADCEN_Msk (0x1UL << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */
12421#define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
12422#define RCC_AHB2ENR_AESEN_Pos (16U)
12423#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00010000 */
12424#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk
12425#define RCC_AHB2ENR_HASHEN_Pos (17U)
12426#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */
12427#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
12428#define RCC_AHB2ENR_RNGEN_Pos (18U)
12429#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
12430#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
12431#define RCC_AHB2ENR_PKAEN_Pos (19U)
12432#define RCC_AHB2ENR_PKAEN_Msk (0x1UL << RCC_AHB2ENR_PKAEN_Pos)/*!< 0x00080000 */
12433#define RCC_AHB2ENR_PKAEN RCC_AHB2ENR_PKAEN_Msk
12434#define RCC_AHB2ENR_OTFDEC1EN_Pos (21U)
12435#define RCC_AHB2ENR_OTFDEC1EN_Msk (0x1UL << RCC_AHB2ENR_OTFDEC1EN_Pos)/*!< 0x00200000 */
12436#define RCC_AHB2ENR_OTFDEC1EN RCC_AHB2ENR_OTFDEC1EN_Msk
12437#define RCC_AHB2ENR_SDMMC1EN_Pos (22U)
12438#define RCC_AHB2ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC1EN_Pos)/*!< 0x00400000 */
12439#define RCC_AHB2ENR_SDMMC1EN RCC_AHB2ENR_SDMMC1EN_Msk
12440
12441/******************** Bit definition for RCC_AHB3ENR register ***************/
12442#define RCC_AHB3ENR_FMCEN_Pos (0U)
12443#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
12444#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
12445#define RCC_AHB3ENR_OSPI1EN_Pos (8U)
12446#define RCC_AHB3ENR_OSPI1EN_Msk (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos)/*!< 0x00000100 */
12447#define RCC_AHB3ENR_OSPI1EN RCC_AHB3ENR_OSPI1EN_Msk
12448
12449/******************** Bit definition for RCC_APB1ENR1 register ***************/
12450#define RCC_APB1ENR1_TIM2EN_Pos (0U)
12451#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
12452#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
12453#define RCC_APB1ENR1_TIM3EN_Pos (1U)
12454#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
12455#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
12456#define RCC_APB1ENR1_TIM4EN_Pos (2U)
12457#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
12458#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
12459#define RCC_APB1ENR1_TIM5EN_Pos (3U)
12460#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)/*!< 0x00000008 */
12461#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
12462#define RCC_APB1ENR1_TIM6EN_Pos (4U)
12463#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
12464#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
12465#define RCC_APB1ENR1_TIM7EN_Pos (5U)
12466#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
12467#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
12468#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
12469#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
12470#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
12471#define RCC_APB1ENR1_WWDGEN_Pos (11U)
12472#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
12473#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
12474#define RCC_APB1ENR1_SPI2EN_Pos (14U)
12475#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
12476#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
12477#define RCC_APB1ENR1_SPI3EN_Pos (15U)
12478#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
12479#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
12480#define RCC_APB1ENR1_USART2EN_Pos (17U)
12481#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
12482#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
12483#define RCC_APB1ENR1_USART3EN_Pos (18U)
12484#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */
12485#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
12486#define RCC_APB1ENR1_UART4EN_Pos (19U)
12487#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
12488#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
12489#define RCC_APB1ENR1_UART5EN_Pos (20U)
12490#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos)/*!< 0x00100000 */
12491#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
12492#define RCC_APB1ENR1_I2C1EN_Pos (21U)
12493#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
12494#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
12495#define RCC_APB1ENR1_I2C2EN_Pos (22U)
12496#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
12497#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
12498#define RCC_APB1ENR1_I2C3EN_Pos (23U)
12499#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x00800000 */
12500#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
12501#define RCC_APB1ENR1_CRSEN_Pos (24U)
12502#define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x01000000 */
12503#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
12504#define RCC_APB1ENR1_PWREN_Pos (28U)
12505#define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
12506#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
12507#define RCC_APB1ENR1_DAC1EN_Pos (29U)
12508#define RCC_APB1ENR1_DAC1EN_Msk (0x1UL << RCC_APB1ENR1_DAC1EN_Pos)/*!< 0x20000000 */
12509#define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
12510#define RCC_APB1ENR1_OPAMPEN_Pos (30U)
12511#define RCC_APB1ENR1_OPAMPEN_Msk (0x1UL << RCC_APB1ENR1_OPAMPEN_Pos)/*!< 0x40000000 */
12512#define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
12513#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
12514#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
12515#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
12516
12517/******************** Bit definition for RCC_APB1RSTR2 register **************/
12518#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
12519#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
12520#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
12521#define RCC_APB1ENR2_I2C4EN_Pos (1U)
12522#define RCC_APB1ENR2_I2C4EN_Msk (0x1UL << RCC_APB1ENR2_I2C4EN_Pos)/*!< 0x00000002 */
12523#define RCC_APB1ENR2_I2C4EN RCC_APB1ENR2_I2C4EN_Msk
12524#define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
12525#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)/*!< 0x00000020 */
12526#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
12527#define RCC_APB1ENR2_LPTIM3EN_Pos (6U)
12528#define RCC_APB1ENR2_LPTIM3EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM3EN_Pos)/*!< 0x00000040 */
12529#define RCC_APB1ENR2_LPTIM3EN RCC_APB1ENR2_LPTIM3EN_Msk
12530#define RCC_APB1ENR2_FDCAN1EN_Pos (9U)
12531#define RCC_APB1ENR2_FDCAN1EN_Msk (0x1UL << RCC_APB1ENR2_FDCAN1EN_Pos)/*!< 0x00000200 */
12532#define RCC_APB1ENR2_FDCAN1EN RCC_APB1ENR2_FDCAN1EN_Msk
12533#define RCC_APB1ENR2_USBFSEN_Pos (21U)
12534#define RCC_APB1ENR2_USBFSEN_Msk (0x1UL << RCC_APB1ENR2_USBFSEN_Pos)/*!< 0x00200000 */
12535#define RCC_APB1ENR2_USBFSEN RCC_APB1ENR2_USBFSEN_Msk
12536#define RCC_APB1ENR2_UCPD1EN_Pos (23U)
12537#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00800000 */
12538#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk
12539
12540/******************** Bit definition for RCC_APB2ENR register ***************/
12541#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
12542#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
12543#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
12544#define RCC_APB2ENR_TIM1EN_Pos (11U)
12545#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
12546#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
12547#define RCC_APB2ENR_SPI1EN_Pos (12U)
12548#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
12549#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
12550#define RCC_APB2ENR_TIM8EN_Pos (13U)
12551#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
12552#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
12553#define RCC_APB2ENR_USART1EN_Pos (14U)
12554#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
12555#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
12556#define RCC_APB2ENR_TIM15EN_Pos (16U)
12557#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
12558#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
12559#define RCC_APB2ENR_TIM16EN_Pos (17U)
12560#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
12561#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
12562#define RCC_APB2ENR_TIM17EN_Pos (18U)
12563#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
12564#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
12565#define RCC_APB2ENR_SAI1EN_Pos (21U)
12566#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
12567#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
12568#define RCC_APB2ENR_SAI2EN_Pos (22U)
12569#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */
12570#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
12571#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
12572#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)/*!< 0x01000000 */
12573#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
12574
12575/******************** Bit definition for RCC_AHB1SMENR register ***************/
12576#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
12577#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
12578#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
12579#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
12580#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
12581#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
12582#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)
12583#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
12584#define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk
12585#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
12586#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
12587#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
12588#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
12589#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
12590#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
12591#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
12592#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
12593#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
12594#define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
12595#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos)/*!< 0x00010000 */
12596#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
12597#define RCC_AHB1SMENR_GTZCSMEN_Pos (22U)
12598#define RCC_AHB1SMENR_GTZCSMEN_Msk (0x1UL << RCC_AHB1SMENR_GTZCSMEN_Pos)/*!< 0x00400000 */
12599#define RCC_AHB1SMENR_GTZCSMEN RCC_AHB1SMENR_GTZCSMEN_Msk
12600#define RCC_AHB1SMENR_ICACHESMEN_Pos (23U)
12601#define RCC_AHB1SMENR_ICACHESMEN_Msk (0x1UL << RCC_AHB1SMENR_ICACHESMEN_Pos)/*!< 0x00600000 */
12602#define RCC_AHB1SMENR_ICACHESMEN RCC_AHB1SMENR_ICACHESMEN_Msk
12603
12604/******************** Bit definition for RCC_AHB2SMENR register *************/
12605#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
12606#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
12607#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
12608#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
12609#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
12610#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
12611#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
12612#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
12613#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
12614#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
12615#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
12616#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
12617#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
12618#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
12619#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
12620#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
12621#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
12622#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
12623#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
12624#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
12625#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
12626#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
12627#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos)/*!< 0x00000080 */
12628#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
12629#define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
12630#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000200 */
12631#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
12632#define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
12633#define RCC_AHB2SMENR_ADCSMEN_Msk (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos)/*!< 0x00002000 */
12634#define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
12635#define RCC_AHB2SMENR_AESSMEN_Pos (16U)
12636#define RCC_AHB2SMENR_AESSMEN_Msk (0x1UL << RCC_AHB2SMENR_AESSMEN_Pos)/*!< 0x00010000 */
12637#define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk
12638#define RCC_AHB2SMENR_HASHSMEN_Pos (17U)
12639#define RCC_AHB2SMENR_HASHSMEN_Msk (0x1UL << RCC_AHB2SMENR_HASHSMEN_Pos)/*!< 0x00020000 */
12640#define RCC_AHB2SMENR_HASHSMEN RCC_AHB2SMENR_HASHSMEN_Msk
12641#define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
12642#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x00040000 */
12643#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
12644#define RCC_AHB2SMENR_PKASMEN_Pos (19U)
12645#define RCC_AHB2SMENR_PKASMEN_Msk (0x1UL << RCC_AHB2SMENR_PKASMEN_Pos)/*!< 0x00080000 */
12646#define RCC_AHB2SMENR_PKASMEN RCC_AHB2SMENR_PKASMEN_Msk
12647#define RCC_AHB2SMENR_OTFDEC1SMEN_Pos (21U)
12648#define RCC_AHB2SMENR_OTFDEC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_OTFDEC1SMEN_Pos)/*!< 0x00200000 */
12649#define RCC_AHB2SMENR_OTFDEC1SMEN RCC_AHB2SMENR_OTFDEC1SMEN_Msk
12650#define RCC_AHB2SMENR_SDMMC1SMEN_Pos (22U)
12651#define RCC_AHB2SMENR_SDMMC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_SDMMC1SMEN_Pos)/*!< 0x00400000 */
12652#define RCC_AHB2SMENR_SDMMC1SMEN RCC_AHB2SMENR_SDMMC1SMEN_Msk
12653
12654/******************** Bit definition for RCC_AHB3SMENR register *************/
12655#define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
12656#define RCC_AHB3SMENR_FMCSMEN_Msk (0x1UL << RCC_AHB3SMENR_FMCSMEN_Pos)/*!< 0x00000001 */
12657#define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
12658#define RCC_AHB3SMENR_OSPI1SMEN_Pos (8U)
12659#define RCC_AHB3SMENR_OSPI1SMEN_Msk (0x1UL << RCC_AHB3SMENR_OSPI1SMEN_Pos)/*!< 0x00000100 */
12660#define RCC_AHB3SMENR_OSPI1SMEN RCC_AHB3SMENR_OSPI1SMEN_Msk
12661
12662/******************** Bit definition for RCC_APB1SMENR1 register *************/
12663#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
12664#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
12665#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
12666#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
12667#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
12668#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
12669#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
12670#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
12671#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
12672#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
12673#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)/*!< 0x00000008 */
12674#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
12675#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
12676#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
12677#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
12678#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
12679#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
12680#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
12681#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
12682#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
12683#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
12684#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
12685#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
12686#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
12687#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
12688#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
12689#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
12690#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
12691#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
12692#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
12693#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
12694#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
12695#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
12696#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
12697#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */
12698#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
12699#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
12700#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
12701#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
12702#define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
12703#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)/*!< 0x00100000 */
12704#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
12705#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
12706#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
12707#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
12708#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
12709#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
12710#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
12711#define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
12712#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x00800000 */
12713#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
12714#define RCC_APB1SMENR1_CRSSMEN_Pos (24U)
12715#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x01000000 */
12716#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
12717#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
12718#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
12719#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
12720#define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
12721#define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1UL << RCC_APB1SMENR1_DAC1SMEN_Pos)/*!< 0x20000000 */
12722#define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
12723#define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
12724#define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1UL << RCC_APB1SMENR1_OPAMPSMEN_Pos)/*!< 0x40000000 */
12725#define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
12726#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
12727#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
12728#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
12729
12730/******************** Bit definition for RCC_APB1SMENR2 register *************/
12731#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
12732#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
12733#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
12734#define RCC_APB1SMENR2_I2C4SMEN_Pos (1U)
12735#define RCC_APB1SMENR2_I2C4SMEN_Msk (0x1UL << RCC_APB1SMENR2_I2C4SMEN_Pos)/*!< 0x00000002 */
12736#define RCC_APB1SMENR2_I2C4SMEN RCC_APB1SMENR2_I2C4SMEN_Msk
12737#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
12738#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos)/*!< 0x00000020 */
12739#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
12740#define RCC_APB1SMENR2_LPTIM3SMEN_Pos (6U)
12741#define RCC_APB1SMENR2_LPTIM3SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM3SMEN_Pos)/*!< 0x00000040 */
12742#define RCC_APB1SMENR2_LPTIM3SMEN RCC_APB1SMENR2_LPTIM3SMEN_Msk
12743#define RCC_APB1SMENR2_FDCAN1SMEN_Pos (9U)
12744#define RCC_APB1SMENR2_FDCAN1SMEN_Msk (0x1UL << RCC_APB1SMENR2_FDCAN1SMEN_Pos)/*!< 0x00000200 */
12745#define RCC_APB1SMENR2_FDCAN1SMEN RCC_APB1SMENR2_FDCAN1SMEN_Msk
12746#define RCC_APB1SMENR2_USBFSSMEN_Pos (21U)
12747#define RCC_APB1SMENR2_USBFSSMEN_Msk (0x1UL << RCC_APB1SMENR2_USBFSSMEN_Pos)/*!< 0x00200000 */
12748#define RCC_APB1SMENR2_USBFSSMEN RCC_APB1SMENR2_USBFSSMEN_Msk
12749#define RCC_APB1SMENR2_UCPD1SMEN_Pos (23U)
12750#define RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00800000 */
12751#define RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk
12752
12753/******************** Bit definition for RCC_APB2SMENR register *************/
12754#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
12755#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
12756#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
12757#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
12758#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
12759#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
12760#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
12761#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
12762#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
12763#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
12764#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
12765#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
12766#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
12767#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
12768#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
12769#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
12770#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
12771#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
12772#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
12773#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
12774#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
12775#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
12776#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
12777#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
12778#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
12779#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
12780#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
12781#define RCC_APB2SMENR_SAI2SMEN_Pos (22U)
12782#define RCC_APB2SMENR_SAI2SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI2SMEN_Pos)/*!< 0x00400000 */
12783#define RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk
12784#define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
12785#define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1UL << RCC_APB2SMENR_DFSDM1SMEN_Pos)/*!< 0x01000000 */
12786#define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
12787
12788/******************** Bit definition for RCC_CCIPR1 register ****************/
12789#define RCC_CCIPR1_USART1SEL_Pos (0U)
12790#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos)/*!< 0x00000003 */
12791#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk
12792#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos)/*!< 0x00000001 */
12793#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos)/*!< 0x00000002 */
12794
12795#define RCC_CCIPR1_USART2SEL_Pos (2U)
12796#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos)/*!< 0x0000000C */
12797#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk
12798#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos)/*!< 0x00000004 */
12799#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos)/*!< 0x00000008 */
12800
12801#define RCC_CCIPR1_USART3SEL_Pos (4U)
12802#define RCC_CCIPR1_USART3SEL_Msk (0x3UL << RCC_CCIPR1_USART3SEL_Pos)/*!< 0x00000030 */
12803#define RCC_CCIPR1_USART3SEL RCC_CCIPR1_USART3SEL_Msk
12804#define RCC_CCIPR1_USART3SEL_0 (0x1UL << RCC_CCIPR1_USART3SEL_Pos)/*!< 0x00000010 */
12805#define RCC_CCIPR1_USART3SEL_1 (0x2UL << RCC_CCIPR1_USART3SEL_Pos)/*!< 0x00000020 */
12806
12807#define RCC_CCIPR1_UART4SEL_Pos (6U)
12808#define RCC_CCIPR1_UART4SEL_Msk (0x3UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x000000C0 */
12809#define RCC_CCIPR1_UART4SEL RCC_CCIPR1_UART4SEL_Msk
12810#define RCC_CCIPR1_UART4SEL_0 (0x1UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000040 */
12811#define RCC_CCIPR1_UART4SEL_1 (0x2UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000080 */
12812
12813#define RCC_CCIPR1_UART5SEL_Pos (8U)
12814#define RCC_CCIPR1_UART5SEL_Msk (0x3UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000300 */
12815#define RCC_CCIPR1_UART5SEL RCC_CCIPR1_UART5SEL_Msk
12816#define RCC_CCIPR1_UART5SEL_0 (0x1UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000100 */
12817#define RCC_CCIPR1_UART5SEL_1 (0x2UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000200 */
12818
12819#define RCC_CCIPR1_LPUART1SEL_Pos (10U)
12820#define RCC_CCIPR1_LPUART1SEL_Msk (0x3UL << RCC_CCIPR1_LPUART1SEL_Pos)/*!< 0x00000C00 */
12821#define RCC_CCIPR1_LPUART1SEL RCC_CCIPR1_LPUART1SEL_Msk
12822#define RCC_CCIPR1_LPUART1SEL_0 (0x1UL << RCC_CCIPR1_LPUART1SEL_Pos)/*!< 0x00000400 */
12823#define RCC_CCIPR1_LPUART1SEL_1 (0x2UL << RCC_CCIPR1_LPUART1SEL_Pos)/*!< 0x00000800 */
12824
12825#define RCC_CCIPR1_I2C1SEL_Pos (12U)
12826#define RCC_CCIPR1_I2C1SEL_Msk (0x3UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00003000 */
12827#define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk
12828#define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00001000 */
12829#define RCC_CCIPR1_I2C1SEL_1 (0x2UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00002000 */
12830
12831#define RCC_CCIPR1_I2C2SEL_Pos (14U)
12832#define RCC_CCIPR1_I2C2SEL_Msk (0x3UL << RCC_CCIPR1_I2C2SEL_Pos) /*!< 0x0000C000 */
12833#define RCC_CCIPR1_I2C2SEL RCC_CCIPR1_I2C2SEL_Msk
12834#define RCC_CCIPR1_I2C2SEL_0 (0x1UL << RCC_CCIPR1_I2C2SEL_Pos) /*!< 0x00004000 */
12835#define RCC_CCIPR1_I2C2SEL_1 (0x2UL << RCC_CCIPR1_I2C2SEL_Pos) /*!< 0x00008000 */
12836
12837#define RCC_CCIPR1_I2C3SEL_Pos (16U)
12838#define RCC_CCIPR1_I2C3SEL_Msk (0x3UL << RCC_CCIPR1_I2C3SEL_Pos) /*!< 0x00030000 */
12839#define RCC_CCIPR1_I2C3SEL RCC_CCIPR1_I2C3SEL_Msk
12840#define RCC_CCIPR1_I2C3SEL_0 (0x1UL << RCC_CCIPR1_I2C3SEL_Pos) /*!< 0x00010000 */
12841#define RCC_CCIPR1_I2C3SEL_1 (0x2UL << RCC_CCIPR1_I2C3SEL_Pos) /*!< 0x00020000 */
12842
12843#define RCC_CCIPR1_LPTIM1SEL_Pos (18U)
12844#define RCC_CCIPR1_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR1_LPTIM1SEL_Pos)/*!< 0x000C0000 */
12845#define RCC_CCIPR1_LPTIM1SEL RCC_CCIPR1_LPTIM1SEL_Msk
12846#define RCC_CCIPR1_LPTIM1SEL_0 (0x1UL << RCC_CCIPR1_LPTIM1SEL_Pos)/*!< 0x00040000 */
12847#define RCC_CCIPR1_LPTIM1SEL_1 (0x2UL << RCC_CCIPR1_LPTIM1SEL_Pos)/*!< 0x00080000 */
12848
12849#define RCC_CCIPR1_LPTIM2SEL_Pos (20U)
12850#define RCC_CCIPR1_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR1_LPTIM2SEL_Pos)/*!< 0x00300000 */
12851#define RCC_CCIPR1_LPTIM2SEL RCC_CCIPR1_LPTIM2SEL_Msk
12852#define RCC_CCIPR1_LPTIM2SEL_0 (0x1UL << RCC_CCIPR1_LPTIM2SEL_Pos)/*!< 0x00100000 */
12853#define RCC_CCIPR1_LPTIM2SEL_1 (0x2UL << RCC_CCIPR1_LPTIM2SEL_Pos)/*!< 0x00200000 */
12854
12855#define RCC_CCIPR1_LPTIM3SEL_Pos (22U)
12856#define RCC_CCIPR1_LPTIM3SEL_Msk (0x3UL << RCC_CCIPR1_LPTIM3SEL_Pos)/*!< 0x00C00000 */
12857#define RCC_CCIPR1_LPTIM3SEL RCC_CCIPR1_LPTIM3SEL_Msk
12858#define RCC_CCIPR1_LPTIM3SEL_0 (0x1UL << RCC_CCIPR1_LPTIM3SEL_Pos)/*!< 0x00400000 */
12859#define RCC_CCIPR1_LPTIM3SEL_1 (0x2UL << RCC_CCIPR1_LPTIM3SEL_Pos)/*!< 0x00800000 */
12860
12861#define RCC_CCIPR1_FDCANSEL_Pos (24U)
12862#define RCC_CCIPR1_FDCANSEL_Msk (0x3UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x03000000 */
12863#define RCC_CCIPR1_FDCANSEL RCC_CCIPR1_FDCANSEL_Msk
12864#define RCC_CCIPR1_FDCANSEL_0 (0x1UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x01000000 */
12865#define RCC_CCIPR1_FDCANSEL_1 (0x2UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x02000000 */
12866
12867#define RCC_CCIPR1_CLK48MSEL_Pos (26U)
12868#define RCC_CCIPR1_CLK48MSEL_Msk (0x3UL << RCC_CCIPR1_CLK48MSEL_Pos) /*!< 0x0C000000 */
12869#define RCC_CCIPR1_CLK48MSEL RCC_CCIPR1_CLK48MSEL_Msk
12870#define RCC_CCIPR1_CLK48MSEL_0 (0x1UL << RCC_CCIPR1_CLK48MSEL_Pos) /*!< 0x04000000 */
12871#define RCC_CCIPR1_CLK48MSEL_1 (0x2UL << RCC_CCIPR1_CLK48MSEL_Pos) /*!< 0x08000000 */
12872
12873#define RCC_CCIPR1_ADCSEL_Pos (28U)
12874#define RCC_CCIPR1_ADCSEL_Msk (0x3UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x30000000 */
12875#define RCC_CCIPR1_ADCSEL RCC_CCIPR1_ADCSEL_Msk
12876#define RCC_CCIPR1_ADCSEL_0 (0x1UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x10000000 */
12877#define RCC_CCIPR1_ADCSEL_1 (0x2UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x20000000 */
12878
12879/******************** Bit definition for RCC_BDCR register ******************/
12880#define RCC_BDCR_LSEON_Pos (0U)
12881#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
12882#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
12883#define RCC_BDCR_LSERDY_Pos (1U)
12884#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
12885#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
12886#define RCC_BDCR_LSEBYP_Pos (2U)
12887#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
12888#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
12889
12890#define RCC_BDCR_LSEDRV_Pos (3U)
12891#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
12892#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
12893#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
12894#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
12895
12896#define RCC_BDCR_LSECSSON_Pos (5U)
12897#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
12898#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
12899#define RCC_BDCR_LSECSSD_Pos (6U)
12900#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
12901#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
12902#define RCC_BDCR_LSESYSEN_Pos (7U)
12903#define RCC_BDCR_LSESYSEN_Msk (0x1UL << RCC_BDCR_LSESYSEN_Pos) /*!< 0x00000080 */
12904#define RCC_BDCR_LSESYSEN RCC_BDCR_LSESYSEN_Msk
12905
12906#define RCC_BDCR_RTCSEL_Pos (8U)
12907#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
12908#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
12909#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
12910#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
12911
12912#define RCC_BDCR_LSESYSRDY_Pos (11U)
12913#define RCC_BDCR_LSESYSRDY_Msk (0x1UL << RCC_BDCR_LSESYSRDY_Pos) /*!< 0x00000800 */
12914#define RCC_BDCR_LSESYSRDY RCC_BDCR_LSESYSRDY_Msk
12915#define RCC_BDCR_RTCEN_Pos (15U)
12916#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
12917#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
12918#define RCC_BDCR_BDRST_Pos (16U)
12919#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
12920#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
12921#define RCC_BDCR_LSCOEN_Pos (24U)
12922#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
12923#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
12924#define RCC_BDCR_LSCOSEL_Pos (25U)
12925#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
12926#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
12927
12928/******************** Bit definition for RCC_CSR register *******************/
12929#define RCC_CSR_LSION_Pos (0U)
12930#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
12931#define RCC_CSR_LSION RCC_CSR_LSION_Msk
12932#define RCC_CSR_LSIRDY_Pos (1U)
12933#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
12934#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
12935#define RCC_CSR_LSIPRE_Pos (4U)
12936#define RCC_CSR_LSIPRE_Msk (0x1UL << RCC_CSR_LSIPRE_Pos) /*!< 0x00000010 */
12937#define RCC_CSR_LSIPRE RCC_CSR_LSIPRE_Msk
12938
12939#define RCC_CSR_MSISRANGE_Pos (8U)
12940#define RCC_CSR_MSISRANGE_Msk (0xFUL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */
12941#define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
12942#define RCC_CSR_MSISRANGE_1 (0x4UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */
12943#define RCC_CSR_MSISRANGE_2 (0x5UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */
12944#define RCC_CSR_MSISRANGE_4 (0x6UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */
12945#define RCC_CSR_MSISRANGE_8 (0x7UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */
12946
12947#define RCC_CSR_RMVF_Pos (23U)
12948#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
12949#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
12950#define RCC_CSR_OBLRSTF_Pos (25U)
12951#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
12952#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
12953#define RCC_CSR_PINRSTF_Pos (26U)
12954#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
12955#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
12956#define RCC_CSR_BORRSTF_Pos (27U)
12957#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
12958#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
12959#define RCC_CSR_SFTRSTF_Pos (28U)
12960#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
12961#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
12962#define RCC_CSR_IWDGRSTF_Pos (29U)
12963#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
12964#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
12965#define RCC_CSR_WWDGRSTF_Pos (30U)
12966#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
12967#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
12968#define RCC_CSR_LPWRRSTF_Pos (31U)
12969#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
12970#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
12971
12972/******************** Bit definition for RCC_CRRCR register *****************/
12973#define RCC_CRRCR_HSI48ON_Pos (0U)
12974#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
12975#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
12976#define RCC_CRRCR_HSI48RDY_Pos (1U)
12977#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
12978#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
12979
12980/*!< HSI48CAL configuration */
12981#define RCC_CRRCR_HSI48CAL_Pos (7U)
12982#define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
12983#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
12984#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
12985#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
12986#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
12987#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
12988#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
12989#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
12990#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
12991#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
12992#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
12993
12994/******************** Bit definition for RCC_CCIPR2 register ******************/
12995#define RCC_CCIPR2_I2C4SEL_Pos (0U)
12996#define RCC_CCIPR2_I2C4SEL_Msk (0x3UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000003 */
12997#define RCC_CCIPR2_I2C4SEL RCC_CCIPR2_I2C4SEL_Msk
12998#define RCC_CCIPR2_I2C4SEL_0 (0x1UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000001 */
12999#define RCC_CCIPR2_I2C4SEL_1 (0x2UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000002 */
13000
13001#define RCC_CCIPR2_DFSDMSEL_Pos (2U)
13002#define RCC_CCIPR2_DFSDMSEL_Msk (0x1UL << RCC_CCIPR2_DFSDMSEL_Pos)/*!< 0x00000004 */
13003#define RCC_CCIPR2_DFSDMSEL RCC_CCIPR2_DFSDMSEL_Msk
13004
13005#define RCC_CCIPR2_ADFSDMSEL_Pos (3U)
13006#define RCC_CCIPR2_ADFSDMSEL_Msk (0x3UL << RCC_CCIPR2_ADFSDMSEL_Pos)/*!< 0x00000018 */
13007#define RCC_CCIPR2_ADFSDMSEL RCC_CCIPR2_ADFSDMSEL_Msk
13008#define RCC_CCIPR2_ADFSDMSEL_0 (0x1UL << RCC_CCIPR2_ADFSDMSEL_Pos)/*!< 0x00000008 */
13009#define RCC_CCIPR2_ADFSDMSEL_1 (0x2UL << RCC_CCIPR2_ADFSDMSEL_Pos)/*!< 0x00000010 */
13010
13011#define RCC_CCIPR2_SAI1SEL_Pos (5U)
13012#define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
13013#define RCC_CCIPR2_SAI1SEL RCC_CCIPR2_SAI1SEL_Msk
13014#define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
13015#define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
13016#define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
13017
13018#define RCC_CCIPR2_SAI2SEL_Pos (8U)
13019#define RCC_CCIPR2_SAI2SEL_Msk (0x7UL << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000700 */
13020#define RCC_CCIPR2_SAI2SEL RCC_CCIPR2_SAI2SEL_Msk
13021#define RCC_CCIPR2_SAI2SEL_0 (0x1UL << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000100 */
13022#define RCC_CCIPR2_SAI2SEL_1 (0x2UL << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000200 */
13023#define RCC_CCIPR2_SAI2SEL_2 (0x4UL << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000400 */
13024
13025#define RCC_CCIPR2_SDMMCSEL_Pos (14U)
13026#define RCC_CCIPR2_SDMMCSEL_Msk (0x1UL << RCC_CCIPR2_SDMMCSEL_Pos)/*!< 0x00004000 */
13027#define RCC_CCIPR2_SDMMCSEL RCC_CCIPR2_SDMMCSEL_Msk
13028
13029#define RCC_CCIPR2_OSPISEL_Pos (20U)
13030#define RCC_CCIPR2_OSPISEL_Msk (0x3UL << RCC_CCIPR2_OSPISEL_Pos)/*!< 0x00300000 */
13031#define RCC_CCIPR2_OSPISEL RCC_CCIPR2_OSPISEL_Msk
13032#define RCC_CCIPR2_OSPISEL_0 (0x1UL << RCC_CCIPR2_OSPISEL_Pos)/*!< 0x00100000 */
13033#define RCC_CCIPR2_OSPISEL_1 (0x2UL << RCC_CCIPR2_OSPISEL_Pos)/*!< 0x00200000 */
13034
13035/******************** Bit definition for RCC_SECCFGR register ***************/
13036#define RCC_SECCFGR_HSISEC_Pos (0U)
13037#define RCC_SECCFGR_HSISEC_Msk (0x1UL << RCC_SECCFGR_HSISEC_Pos) /*!< 0x00000001 */
13038#define RCC_SECCFGR_HSISEC RCC_SECCFGR_HSISEC_Msk
13039#define RCC_SECCFGR_HSESEC_Pos (1U)
13040#define RCC_SECCFGR_HSESEC_Msk (0x1UL << RCC_SECCFGR_HSESEC_Pos) /*!< 0x00000002 */
13041#define RCC_SECCFGR_HSESEC RCC_SECCFGR_HSESEC_Msk
13042#define RCC_SECCFGR_MSISEC_Pos (2U)
13043#define RCC_SECCFGR_MSISEC_Msk (0x1UL << RCC_SECCFGR_MSISEC_Pos) /*!< 0x00000004 */
13044#define RCC_SECCFGR_MSISEC RCC_SECCFGR_MSISEC_Msk
13045#define RCC_SECCFGR_LSISEC_Pos (3U)
13046#define RCC_SECCFGR_LSISEC_Msk (0x1UL << RCC_SECCFGR_LSISEC_Pos) /*!< 0x00000008 */
13047#define RCC_SECCFGR_LSISEC RCC_SECCFGR_LSISEC_Msk
13048#define RCC_SECCFGR_LSESEC_Pos (4U)
13049#define RCC_SECCFGR_LSESEC_Msk (0x1UL << RCC_SECCFGR_LSESEC_Pos) /*!< 0x00000010 */
13050#define RCC_SECCFGR_LSESEC RCC_SECCFGR_LSESEC_Msk
13051#define RCC_SECCFGR_SYSCLKSEC_Pos (5U)
13052#define RCC_SECCFGR_SYSCLKSEC_Msk (0x1UL << RCC_SECCFGR_SYSCLKSEC_Pos)/*!< 0x00000020 */
13053#define RCC_SECCFGR_SYSCLKSEC RCC_SECCFGR_SYSCLKSEC_Msk
13054#define RCC_SECCFGR_PRESCSEC_Pos (6U)
13055#define RCC_SECCFGR_PRESCSEC_Msk (0x1UL << RCC_SECCFGR_PRESCSEC_Pos)/*!< 0x00000040 */
13056#define RCC_SECCFGR_PRESCSEC RCC_SECCFGR_PRESCSEC_Msk
13057#define RCC_SECCFGR_PLLSEC_Pos (7U)
13058#define RCC_SECCFGR_PLLSEC_Msk (0x1UL << RCC_SECCFGR_PLLSEC_Pos)/*!< 0x00000080 */
13059#define RCC_SECCFGR_PLLSEC RCC_SECCFGR_PLLSEC_Msk
13060#define RCC_SECCFGR_PLLSAI1SEC_Pos (8U)
13061#define RCC_SECCFGR_PLLSAI1SEC_Msk (0x1UL << RCC_SECCFGR_PLLSAI1SEC_Pos)/*!< 0x00000100 */
13062#define RCC_SECCFGR_PLLSAI1SEC RCC_SECCFGR_PLLSAI1SEC_Msk
13063#define RCC_SECCFGR_PLLSAI2SEC_Pos (9U)
13064#define RCC_SECCFGR_PLLSAI2SEC_Msk (0x1UL << RCC_SECCFGR_PLLSAI2SEC_Pos)/*!< 0x00000200 */
13065#define RCC_SECCFGR_PLLSAI2SEC RCC_SECCFGR_PLLSAI2SEC_Msk
13066#define RCC_SECCFGR_CLK48MSEC_Pos (10U)
13067#define RCC_SECCFGR_CLK48MSEC_Msk (0x1UL << RCC_SECCFGR_CLK48MSEC_Pos) /*!< 0x00000400 */
13068#define RCC_SECCFGR_CLK48MSEC RCC_SECCFGR_CLK48MSEC_Msk
13069#define RCC_SECCFGR_HSI48SEC_Pos (11U)
13070#define RCC_SECCFGR_HSI48SEC_Msk (0x1UL << RCC_SECCFGR_HSI48SEC_Pos) /*!< 0x00000800 */
13071#define RCC_SECCFGR_HSI48SEC RCC_SECCFGR_HSI48SEC_Msk
13072#define RCC_SECCFGR_RMVFSEC_Pos (12U)
13073#define RCC_SECCFGR_RMVFSEC_Msk (0x1UL << RCC_SECCFGR_RMVFSEC_Pos)/*!< 0x00001000 */
13074#define RCC_SECCFGR_RMVFSEC RCC_SECCFGR_RMVFSEC_Msk
13075
13076/******************** Bit definition for RCC_SECSR register *****************/
13077#define RCC_SECSR_HSISECF_Pos (0U)
13078#define RCC_SECSR_HSISECF_Msk (0x1UL << RCC_SECSR_HSISECF_Pos) /*!< 0x00000001 */
13079#define RCC_SECSR_HSISECF RCC_SECSR_HSISECF_Msk
13080#define RCC_SECSR_HSESECF_Pos (1U)
13081#define RCC_SECSR_HSESECF_Msk (0x1UL << RCC_SECSR_HSESECF_Pos) /*!< 0x00000002 */
13082#define RCC_SECSR_HSESECF RCC_SECSR_HSESECF_Msk
13083#define RCC_SECSR_MSISECF_Pos (2U)
13084#define RCC_SECSR_MSISECF_Msk (0x1UL << RCC_SECSR_MSISECF_Pos) /*!< 0x00000004 */
13085#define RCC_SECSR_MSISECF RCC_SECSR_MSISECF_Msk
13086#define RCC_SECSR_LSISECF_Pos (3U)
13087#define RCC_SECSR_LSISECF_Msk (0x1UL << RCC_SECSR_LSISECF_Pos) /*!< 0x00000008 */
13088#define RCC_SECSR_LSISECF RCC_SECSR_LSISECF_Msk
13089#define RCC_SECSR_LSESECF_Pos (4U)
13090#define RCC_SECSR_LSESECF_Msk (0x1UL << RCC_SECSR_LSESECF_Pos) /*!< 0x00000010 */
13091#define RCC_SECSR_LSESECF RCC_SECSR_LSESECF_Msk
13092#define RCC_SECSR_SYSCLKSECF_Pos (5U)
13093#define RCC_SECSR_SYSCLKSECF_Msk (0x1UL << RCC_SECSR_SYSCLKSECF_Pos)/*!< 0x00000020 */
13094#define RCC_SECSR_SYSCLKSECF RCC_SECSR_SYSCLKSECF_Msk
13095#define RCC_SECSR_PRESCSECF_Pos (6U)
13096#define RCC_SECSR_PRESCSECF_Msk (0x1UL << RCC_SECSR_PRESCSECF_Pos)/*!< 0x00000040 */
13097#define RCC_SECSR_PRESCSECF RCC_SECSR_PRESCSECF_Msk
13098#define RCC_SECSR_PLLSECF_Pos (7U)
13099#define RCC_SECSR_PLLSECF_Msk (0x1UL << RCC_SECSR_PLLSECF_Pos) /*!< 0x00000080 */
13100#define RCC_SECSR_PLLSECF RCC_SECSR_PLLSECF_Msk
13101#define RCC_SECSR_PLLSAI1SECF_Pos (8U)
13102#define RCC_SECSR_PLLSAI1SECF_Msk (0x1UL << RCC_SECSR_PLLSAI1SECF_Pos)/*!< 0x00000100 */
13103#define RCC_SECSR_PLLSAI1SECF RCC_SECSR_PLLSAI1SECF_Msk
13104#define RCC_SECSR_PLLSAI2SECF_Pos (9U)
13105#define RCC_SECSR_PLLSAI2SECF_Msk (0x1UL << RCC_SECSR_PLLSAI2SECF_Pos)/*!< 0x00000200 */
13106#define RCC_SECSR_PLLSAI2SECF RCC_SECSR_PLLSAI2SECF_Msk
13107#define RCC_SECSR_CLK48MSECF_Pos (10U)
13108#define RCC_SECSR_CLK48MSECF_Msk (0x1UL << RCC_SECSR_CLK48MSECF_Pos) /*!< 0x00000400 */
13109#define RCC_SECSR_CLK48MSECF RCC_SECSR_CLK48MSECF_Msk
13110#define RCC_SECSR_HSI48SECF_Pos (11U)
13111#define RCC_SECSR_HSI48SECF_Msk (0x1UL << RCC_SECSR_HSI48SECF_Pos) /*!< 0x00000800 */
13112#define RCC_SECSR_HSI48SECF RCC_SECSR_HSI48SECF_Msk
13113#define RCC_SECSR_RMVFSECF_Pos (12U)
13114#define RCC_SECSR_RMVFSECF_Msk (0x1UL << RCC_SECSR_RMVFSECF_Pos)/*!< 0x00001000 */
13115#define RCC_SECSR_RMVFSECF RCC_SECSR_RMVFSECF_Msk
13116
13117/******************** Bit definition for RCC_AHB1SECSR register *************/
13118#define RCC_AHB1SECSR_DMA1SECF_Pos (0U)
13119#define RCC_AHB1SECSR_DMA1SECF_Msk (0x1UL << RCC_AHB1SECSR_DMA1SECF_Pos)/*!< 0x00000001 */
13120#define RCC_AHB1SECSR_DMA1SECF RCC_AHB1SECSR_DMA1SECF_Msk
13121#define RCC_AHB1SECSR_DMA2SECF_Pos (1U)
13122#define RCC_AHB1SECSR_DMA2SECF_Msk (0x1UL << RCC_AHB1SECSR_DMA2SECF_Pos)/*!< 0x00000002 */
13123#define RCC_AHB1SECSR_DMA2SECF RCC_AHB1SECSR_DMA2SECF_Msk
13124#define RCC_AHB1SECSR_DMAMUX1SECF_Pos (2U)
13125#define RCC_AHB1SECSR_DMAMUX1SECF_Msk (0x1UL << RCC_AHB1SECSR_DMAMUX1SECF_Pos)/*!< 0x00000004 */
13126#define RCC_AHB1SECSR_DMAMUX1SECF RCC_AHB1SECSR_DMAMUX1SECF_Msk
13127#define RCC_AHB1SECSR_FLASHSECF_Pos (8U)
13128#define RCC_AHB1SECSR_FLASHSECF_Msk (0x1UL << RCC_AHB1SECSR_FLASHSECF_Pos)/*!< 0x00000100 */
13129#define RCC_AHB1SECSR_FLASHSECF RCC_AHB1SECSR_FLASHSECF_Msk
13130#define RCC_AHB1SECSR_SRAM1SECF_Pos (9U)
13131#define RCC_AHB1SECSR_SRAM1SECF_Msk (0x1UL << RCC_AHB1SECSR_SRAM1SECF_Pos)/*!< 0x00000200 */
13132#define RCC_AHB1SECSR_SRAM1SECF RCC_AHB1SECSR_SRAM1SECF_Msk
13133#define RCC_AHB1SECSR_CRCSECF_Pos (12U)
13134#define RCC_AHB1SECSR_CRCSECF_Msk (0x1UL << RCC_AHB1SECSR_CRCSECF_Pos)/*!< 0x00001000 */
13135#define RCC_AHB1SECSR_CRCSECF RCC_AHB1SECSR_CRCSECF_Msk
13136#define RCC_AHB1SECSR_TSCSECF_Pos (16U)
13137#define RCC_AHB1SECSR_TSCSECF_Msk (0x1UL << RCC_AHB1SECSR_TSCSECF_Pos)/*!< 0x00010000 */
13138#define RCC_AHB1SECSR_TSCSECF RCC_AHB1SECSR_TSCSECF_Msk
13139#define RCC_AHB1SECSR_GTZCSECF_Pos (22U)
13140#define RCC_AHB1SECSR_GTZCSECF_Msk (0x1UL << RCC_AHB1SECSR_GTZCSECF_Pos)/*!< 0x00400000 */
13141#define RCC_AHB1SECSR_GTZCSECF RCC_AHB1SECSR_GTZCSECF_Msk
13142#define RCC_AHB1SECSR_ICACHESECF_Pos (23U)
13143#define RCC_AHB1SECSR_ICACHESECF_Msk (0x1UL << RCC_AHB1SECSR_ICACHESECF_Pos)/*!< 0x00600000 */
13144#define RCC_AHB1SECSR_ICACHESECF RCC_AHB1SECSR_ICACHESECF_Msk
13145
13146/******************** Bit definition for RCC_AHB2SECSR register *************/
13147#define RCC_AHB2SECSR_GPIOASECF_Pos (0U)
13148#define RCC_AHB2SECSR_GPIOASECF_Msk (0x1UL << RCC_AHB2SECSR_GPIOASECF_Pos)/*!< 0x00000001 */
13149#define RCC_AHB2SECSR_GPIOASECF RCC_AHB2SECSR_GPIOASECF_Msk
13150#define RCC_AHB2SECSR_GPIOBSECF_Pos (1U)
13151#define RCC_AHB2SECSR_GPIOBSECF_Msk (0x1UL << RCC_AHB2SECSR_GPIOBSECF_Pos)/*!< 0x00000002 */
13152#define RCC_AHB2SECSR_GPIOBSECF RCC_AHB2SECSR_GPIOBSECF_Msk
13153#define RCC_AHB2SECSR_GPIOCSECF_Pos (2U)
13154#define RCC_AHB2SECSR_GPIOCSECF_Msk (0x1UL << RCC_AHB2SECSR_GPIOCSECF_Pos)/*!< 0x00000004 */
13155#define RCC_AHB2SECSR_GPIOCSECF RCC_AHB2SECSR_GPIOCSECF_Msk
13156#define RCC_AHB2SECSR_GPIODSECF_Pos (3U)
13157#define RCC_AHB2SECSR_GPIODSECF_Msk (0x1UL << RCC_AHB2SECSR_GPIODSECF_Pos)/*!< 0x00000008 */
13158#define RCC_AHB2SECSR_GPIODSECF RCC_AHB2SECSR_GPIODSECF_Msk
13159#define RCC_AHB2SECSR_GPIOESECF_Pos (4U)
13160#define RCC_AHB2SECSR_GPIOESECF_Msk (0x1UL << RCC_AHB2SECSR_GPIOESECF_Pos)/*!< 0x00000010 */
13161#define RCC_AHB2SECSR_GPIOESECF RCC_AHB2SECSR_GPIOESECF_Msk
13162#define RCC_AHB2SECSR_GPIOFSECF_Pos (5U)
13163#define RCC_AHB2SECSR_GPIOFSECF_Msk (0x1UL << RCC_AHB2SECSR_GPIOFSECF_Pos)/*!< 0x00000020 */
13164#define RCC_AHB2SECSR_GPIOFSECF RCC_AHB2SECSR_GPIOFSECF_Msk
13165#define RCC_AHB2SECSR_GPIOGSECF_Pos (6U)
13166#define RCC_AHB2SECSR_GPIOGSECF_Msk (0x1UL << RCC_AHB2SECSR_GPIOGSECF_Pos)/*!< 0x00000040 */
13167#define RCC_AHB2SECSR_GPIOGSECF RCC_AHB2SECSR_GPIOGSECF_Msk
13168#define RCC_AHB2SECSR_GPIOHSECF_Pos (7U)
13169#define RCC_AHB2SECSR_GPIOHSECF_Msk (0x1UL << RCC_AHB2SECSR_GPIOHSECF_Pos)/*!< 0x00000080 */
13170#define RCC_AHB2SECSR_GPIOHSECF RCC_AHB2SECSR_GPIOHSECF_Msk
13171#define RCC_AHB2SECSR_SRAM2SECF_Pos (9U)
13172#define RCC_AHB2SECSR_SRAM2SECF_Msk (0x1UL << RCC_AHB2SECSR_SRAM2SECF_Pos)/*!< 0x00000200 */
13173#define RCC_AHB2SECSR_SRAM2SECF RCC_AHB2SECSR_SRAM2SECF_Msk
13174#define RCC_AHB2SECSR_ADCSECF_Pos (13U)
13175#define RCC_AHB2SECSR_ADCSECF_Msk (0x1UL << RCC_AHB2SECSR_ADCSECF_Pos)/*!< 0x00002000 */
13176#define RCC_AHB2SECSR_ADCSECF RCC_AHB2SECSR_ADCSECF_Msk
13177#define RCC_AHB2SECSR_AESSECF_Pos (16U)
13178#define RCC_AHB2SECSR_AESSECF_Msk (0x1UL << RCC_AHB2SECSR_AESSECF_Pos)/*!< 0x00010000 */
13179#define RCC_AHB2SECSR_AESSECF RCC_AHB2SECSR_AESSECF_Msk
13180#define RCC_AHB2SECSR_HASHSECF_Pos (17U)
13181#define RCC_AHB2SECSR_HASHSECF_Msk (0x1UL << RCC_AHB2SECSR_HASHSECF_Pos)/*!< 0x00020000 */
13182#define RCC_AHB2SECSR_HASHSECF RCC_AHB2SECSR_HASHSECF_Msk
13183#define RCC_AHB2SECSR_RNGSECF_Pos (18U)
13184#define RCC_AHB2SECSR_RNGSECF_Msk (0x1UL << RCC_AHB2SECSR_RNGSECF_Pos)/*!< 0x00040000 */
13185#define RCC_AHB2SECSR_RNGSECF RCC_AHB2SECSR_RNGSECF_Msk
13186#define RCC_AHB2SECSR_PKASECF_Pos (19U)
13187#define RCC_AHB2SECSR_PKASECF_Msk (0x1UL << RCC_AHB2SECSR_PKASECF_Pos)/*!< 0x00080000 */
13188#define RCC_AHB2SECSR_PKASECF RCC_AHB2SECSR_PKASECF_Msk
13189#define RCC_AHB2SECSR_OTFDEC1SECF_Pos (21U)
13190#define RCC_AHB2SECSR_OTFDEC1SECF_Msk (0x1UL << RCC_AHB2SECSR_OTFDEC1SECF_Pos)/*!< 0x00200000 */
13191#define RCC_AHB2SECSR_OTFDEC1SECF RCC_AHB2SECSR_OTFDEC1SECF_Msk
13192#define RCC_AHB2SECSR_SDMMC1SECF_Pos (22U)
13193#define RCC_AHB2SECSR_SDMMC1SECF_Msk (0x1UL << RCC_AHB2SECSR_SDMMC1SECF_Pos)/*!< 0x00400000 */
13194#define RCC_AHB2SECSR_SDMMC1SECF RCC_AHB2SECSR_SDMMC1SECF_Msk
13195
13196/******************** Bit definition for RCC_AHB3SECSR register *************/
13197#define RCC_AHB3SECSR_FMCSECF_Pos (0U)
13198#define RCC_AHB3SECSR_FMCSECF_Msk (0x1UL << RCC_AHB3SECSR_FMCSECF_Pos)/*!< 0x00000001 */
13199#define RCC_AHB3SECSR_FMCSECF RCC_AHB3SECSR_FMCSECF_Msk
13200#define RCC_AHB3SECSR_OSPI1SECF_Pos (8U)
13201#define RCC_AHB3SECSR_OSPI1SECF_Msk (0x1UL << RCC_AHB3SECSR_OSPI1SECF_Pos)/*!< 0x00000100 */
13202#define RCC_AHB3SECSR_OSPI1SECF RCC_AHB3SECSR_OSPI1SECF_Msk
13203
13204/******************** Bit definition for RCC_APB1SECSR1 register ************/
13205#define RCC_APB1SECSR1_TIM2SECF_Pos (0U)
13206#define RCC_APB1SECSR1_TIM2SECF_Msk (0x1UL << RCC_APB1SECSR1_TIM2SECF_Pos)/*!< 0x00000001 */
13207#define RCC_APB1SECSR1_TIM2SECF RCC_APB1SECSR1_TIM2SECF_Msk
13208#define RCC_APB1SECSR1_TIM3SECF_Pos (1U)
13209#define RCC_APB1SECSR1_TIM3SECF_Msk (0x1UL << RCC_APB1SECSR1_TIM3SECF_Pos)/*!< 0x00000002 */
13210#define RCC_APB1SECSR1_TIM3SECF RCC_APB1SECSR1_TIM3SECF_Msk
13211#define RCC_APB1SECSR1_TIM4SECF_Pos (2U)
13212#define RCC_APB1SECSR1_TIM4SECF_Msk (0x1UL << RCC_APB1SECSR1_TIM4SECF_Pos)/*!< 0x00000004 */
13213#define RCC_APB1SECSR1_TIM4SECF RCC_APB1SECSR1_TIM4SECF_Msk
13214#define RCC_APB1SECSR1_TIM5SECF_Pos (3U)
13215#define RCC_APB1SECSR1_TIM5SECF_Msk (0x1UL << RCC_APB1SECSR1_TIM5SECF_Pos)/*!< 0x00000008 */
13216#define RCC_APB1SECSR1_TIM5SECF RCC_APB1SECSR1_TIM5SECF_Msk
13217#define RCC_APB1SECSR1_TIM6SECF_Pos (4U)
13218#define RCC_APB1SECSR1_TIM6SECF_Msk (0x1UL << RCC_APB1SECSR1_TIM6SECF_Pos)/*!< 0x00000010 */
13219#define RCC_APB1SECSR1_TIM6SECF RCC_APB1SECSR1_TIM6SECF_Msk
13220#define RCC_APB1SECSR1_TIM7SECF_Pos (5U)
13221#define RCC_APB1SECSR1_TIM7SECF_Msk (0x1UL << RCC_APB1SECSR1_TIM7SECF_Pos)/*!< 0x00000020 */
13222#define RCC_APB1SECSR1_TIM7SECF RCC_APB1SECSR1_TIM7SECF_Msk
13223#define RCC_APB1SECSR1_RTCAPBSECF_Pos (10U)
13224#define RCC_APB1SECSR1_RTCAPBSECF_Msk (0x1UL << RCC_APB1SECSR1_RTCAPBSECF_Pos)/*!< 0x00000400 */
13225#define RCC_APB1SECSR1_RTCAPBSECF RCC_APB1SECSR1_RTCAPBSECF_Msk
13226#define RCC_APB1SECSR1_WWDGSECF_Pos (11U)
13227#define RCC_APB1SECSR1_WWDGSECF_Msk (0x1UL << RCC_APB1SECSR1_WWDGSECF_Pos)/*!< 0x00000800 */
13228#define RCC_APB1SECSR1_WWDGSECF RCC_APB1SECSR1_WWDGSECF_Msk
13229#define RCC_APB1SECSR1_SPI2SECF_Pos (14U)
13230#define RCC_APB1SECSR1_SPI2SECF_Msk (0x1UL << RCC_APB1SECSR1_SPI2SECF_Pos)/*!< 0x00004000 */
13231#define RCC_APB1SECSR1_SPI2SECF RCC_APB1SECSR1_SPI2SECF_Msk
13232#define RCC_APB1SECSR1_SPI3SECF_Pos (15U)
13233#define RCC_APB1SECSR1_SPI3SECF_Msk (0x1UL << RCC_APB1SECSR1_SPI3SECF_Pos)/*!< 0x00008000 */
13234#define RCC_APB1SECSR1_SPI3SECF RCC_APB1SECSR1_SPI3SECF_Msk
13235#define RCC_APB1SECSR1_USART2SECF_Pos (17U)
13236#define RCC_APB1SECSR1_USART2SECF_Msk (0x1UL << RCC_APB1SECSR1_USART2SECF_Pos)/*!< 0x00020000 */
13237#define RCC_APB1SECSR1_USART2SECF RCC_APB1SECSR1_USART2SECF_Msk
13238#define RCC_APB1SECSR1_USART3SECF_Pos (18U)
13239#define RCC_APB1SECSR1_USART3SECF_Msk (0x1UL << RCC_APB1SECSR1_USART3SECF_Pos)/*!< 0x00040000 */
13240#define RCC_APB1SECSR1_USART3SECF RCC_APB1SECSR1_USART3SECF_Msk
13241#define RCC_APB1SECSR1_UART4SECF_Pos (19U)
13242#define RCC_APB1SECSR1_UART4SECF_Msk (0x1UL << RCC_APB1SECSR1_UART4SECF_Pos)/*!< 0x00080000 */
13243#define RCC_APB1SECSR1_UART4SECF RCC_APB1SECSR1_UART4SECF_Msk
13244#define RCC_APB1SECSR1_UART5SECF_Pos (20U)
13245#define RCC_APB1SECSR1_UART5SECF_Msk (0x1UL << RCC_APB1SECSR1_UART5SECF_Pos)/*!< 0x00100000 */
13246#define RCC_APB1SECSR1_UART5SECF RCC_APB1SECSR1_UART5SECF_Msk
13247#define RCC_APB1SECSR1_I2C1SECF_Pos (21U)
13248#define RCC_APB1SECSR1_I2C1SECF_Msk (0x1UL << RCC_APB1SECSR1_I2C1SECF_Pos)/*!< 0x00200000 */
13249#define RCC_APB1SECSR1_I2C1SECF RCC_APB1SECSR1_I2C1SECF_Msk
13250#define RCC_APB1SECSR1_I2C2SECF_Pos (22U)
13251#define RCC_APB1SECSR1_I2C2SECF_Msk (0x1UL << RCC_APB1SECSR1_I2C2SECF_Pos)/*!< 0x00400000 */
13252#define RCC_APB1SECSR1_I2C2SECF RCC_APB1SECSR1_I2C2SECF_Msk
13253#define RCC_APB1SECSR1_I2C3SECF_Pos (23U)
13254#define RCC_APB1SECSR1_I2C3SECF_Msk (0x1UL << RCC_APB1SECSR1_I2C3SECF_Pos)/*!< 0x00800000 */
13255#define RCC_APB1SECSR1_I2C3SECF RCC_APB1SECSR1_I2C3SECF_Msk
13256#define RCC_APB1SECSR1_CRSSECF_Pos (24U)
13257#define RCC_APB1SECSR1_CRSSECF_Msk (0x1UL << RCC_APB1SECSR1_CRSSECF_Pos)/*!< 0x01000000 */
13258#define RCC_APB1SECSR1_CRSSECF RCC_APB1SECSR1_CRSSECF_Msk
13259#define RCC_APB1SECSR1_PWRSECF_Pos (28U)
13260#define RCC_APB1SECSR1_PWRSECF_Msk (0x1UL << RCC_APB1SECSR1_PWRSECF_Pos)/*!< 0x10000000 */
13261#define RCC_APB1SECSR1_PWRSECF RCC_APB1SECSR1_PWRSECF_Msk
13262#define RCC_APB1SECSR1_DAC1SECF_Pos (29U)
13263#define RCC_APB1SECSR1_DAC1SECF_Msk (0x1UL << RCC_APB1SECSR1_DAC1SECF_Pos)/*!< 0x20000000 */
13264#define RCC_APB1SECSR1_DAC1SECF RCC_APB1SECSR1_DAC1SECF_Msk
13265#define RCC_APB1SECSR1_OPAMPSECF_Pos (30U)
13266#define RCC_APB1SECSR1_OPAMPSECF_Msk (0x1UL << RCC_APB1SECSR1_OPAMPSECF_Pos)/*!< 0x40000000 */
13267#define RCC_APB1SECSR1_OPAMPSECF RCC_APB1SECSR1_OPAMPSECF_Msk
13268#define RCC_APB1SECSR1_LPTIM1SECF_Pos (31U)
13269#define RCC_APB1SECSR1_LPTIM1SECF_Msk (0x1UL << RCC_APB1SECSR1_LPTIM1SECF_Pos)/*!< 0x80000000 */
13270#define RCC_APB1SECSR1_LPTIM1SECF RCC_APB1SECSR1_LPTIM1SECF_Msk
13271
13272/******************** Bit definition for RCC_APB1SECSR2 register ************/
13273#define RCC_APB1SECSR2_LPUART1SECF_Pos (0U)
13274#define RCC_APB1SECSR2_LPUART1SECF_Msk (0x1UL << RCC_APB1SECSR2_LPUART1SECF_Pos)/*!< 0x00000001 */
13275#define RCC_APB1SECSR2_LPUART1SECF RCC_APB1SECSR2_LPUART1SECF_Msk
13276#define RCC_APB1SECSR2_I2C4SECF_Pos (1U)
13277#define RCC_APB1SECSR2_I2C4SECF_Msk (0x1UL << RCC_APB1SECSR2_I2C4SECF_Pos)/*!< 0x00000002 */
13278#define RCC_APB1SECSR2_I2C4SECF RCC_APB1SECSR2_I2C4SECF_Msk
13279#define RCC_APB1SECSR2_LPTIM2SECF_Pos (5U)
13280#define RCC_APB1SECSR2_LPTIM2SECF_Msk (0x1UL << RCC_APB1SECSR2_LPTIM2SECF_Pos)/*!< 0x00000020 */
13281#define RCC_APB1SECSR2_LPTIM2SECF RCC_APB1SECSR2_LPTIM2SECF_Msk
13282#define RCC_APB1SECSR2_LPTIM3SECF_Pos (6U)
13283#define RCC_APB1SECSR2_LPTIM3SECF_Msk (0x1UL << RCC_APB1SECSR2_LPTIM3SECF_Pos)/*!< 0x00000040 */
13284#define RCC_APB1SECSR2_LPTIM3SECF RCC_APB1SECSR2_LPTIM3SECF_Msk
13285#define RCC_APB1SECSR2_FDCAN1SECF_Pos (9U)
13286#define RCC_APB1SECSR2_FDCAN1SECF_Msk (0x1UL << RCC_APB1SECSR2_FDCAN1SECF_Pos)/*!< 0x00000200 */
13287#define RCC_APB1SECSR2_FDCAN1SECF RCC_APB1SECSR2_FDCAN1SECF_Msk
13288#define RCC_APB1SECSR2_USBFSSECF_Pos (21U)
13289#define RCC_APB1SECSR2_USBFSSECF_Msk (0x1UL << RCC_APB1SECSR2_USBFSSECF_Pos)/*!< 0x00200000 */
13290#define RCC_APB1SECSR2_USBFSSECF RCC_APB1SECSR2_USBFSSECF_Msk
13291#define RCC_APB1SECSR2_UCPD1SECF_Pos (23U)
13292#define RCC_APB1SECSR2_UCPD1SECF_Msk (0x1UL << RCC_APB1SECSR2_UCPD1SECF_Pos)/*!< 0x00800000 */
13293#define RCC_APB1SECSR2_UCPD1SECF RCC_APB1SECSR2_UCPD1SECF_Msk
13294
13295/******************** Bit definition for RCC_APB2SECSR register *************/
13296#define RCC_APB2SECSR_SYSCFGSECF_Pos (0U)
13297#define RCC_APB2SECSR_SYSCFGSECF_Msk (0x1UL << RCC_APB2SECSR_SYSCFGSECF_Pos)/*!< 0x00000001 */
13298#define RCC_APB2SECSR_SYSCFGSECF RCC_APB2SECSR_SYSCFGSECF_Msk
13299#define RCC_APB2SECSR_TIM1SECF_Pos (11U)
13300#define RCC_APB2SECSR_TIM1SECF_Msk (0x1UL << RCC_APB2SECSR_TIM1SECF_Pos)/*!< 0x00000800 */
13301#define RCC_APB2SECSR_TIM1SECF RCC_APB2SECSR_TIM1SECF_Msk
13302#define RCC_APB2SECSR_SPI1SECF_Pos (12U)
13303#define RCC_APB2SECSR_SPI1SECF_Msk (0x1UL << RCC_APB2SECSR_SPI1SECF_Pos)/*!< 0x00001000 */
13304#define RCC_APB2SECSR_SPI1SECF RCC_APB2SECSR_SPI1SECF_Msk
13305#define RCC_APB2SECSR_TIM8SECF_Pos (13U)
13306#define RCC_APB2SECSR_TIM8SECF_Msk (0x1UL << RCC_APB2SECSR_TIM8SECF_Pos)/*!< 0x00002000 */
13307#define RCC_APB2SECSR_TIM8SECF RCC_APB2SECSR_TIM8SECF_Msk
13308#define RCC_APB2SECSR_USART1SECF_Pos (14U)
13309#define RCC_APB2SECSR_USART1SECF_Msk (0x1UL << RCC_APB2SECSR_USART1SECF_Pos)/*!< 0x00004000 */
13310#define RCC_APB2SECSR_USART1SECF RCC_APB2SECSR_USART1SECF_Msk
13311#define RCC_APB2SECSR_TIM15SECF_Pos (16U)
13312#define RCC_APB2SECSR_TIM15SECF_Msk (0x1UL << RCC_APB2SECSR_TIM15SECF_Pos)/*!< 0x00010000 */
13313#define RCC_APB2SECSR_TIM15SECF RCC_APB2SECSR_TIM15SECF_Msk
13314#define RCC_APB2SECSR_TIM16SECF_Pos (17U)
13315#define RCC_APB2SECSR_TIM16SECF_Msk (0x1UL << RCC_APB2SECSR_TIM16SECF_Pos)/*!< 0x00020000 */
13316#define RCC_APB2SECSR_TIM16SECF RCC_APB2SECSR_TIM16SECF_Msk
13317#define RCC_APB2SECSR_TIM17SECF_Pos (18U)
13318#define RCC_APB2SECSR_TIM17SECF_Msk (0x1UL << RCC_APB2SECSR_TIM17SECF_Pos)/*!< 0x00040000 */
13319#define RCC_APB2SECSR_TIM17SECF RCC_APB2SECSR_TIM17SECF_Msk
13320#define RCC_APB2SECSR_SAI1SECF_Pos (21U)
13321#define RCC_APB2SECSR_SAI1SECF_Msk (0x1UL << RCC_APB2SECSR_SAI1SECF_Pos)/*!< 0x00200000 */
13322#define RCC_APB2SECSR_SAI1SECF RCC_APB2SECSR_SAI1SECF_Msk
13323#define RCC_APB2SECSR_SAI2SECF_Pos (22U)
13324#define RCC_APB2SECSR_SAI2SECF_Msk (0x1UL << RCC_APB2SECSR_SAI2SECF_Pos)/*!< 0x00400000 */
13325#define RCC_APB2SECSR_SAI2SECF RCC_APB2SECSR_SAI2SECF_Msk
13326#define RCC_APB2SECSR_DFSDM1SECF_Pos (24U)
13327#define RCC_APB2SECSR_DFSDM1SECF_Msk (0x1UL << RCC_APB2SECSR_DFSDM1SECF_Pos)/*!< 0x01000000 */
13328#define RCC_APB2SECSR_DFSDM1SECF RCC_APB2SECSR_DFSDM1SECF_Msk
13329
13330
13331/******************************************************************************/
13332/* */
13333/* RNG */
13334/* */
13335/******************************************************************************/
13336
13337/*
13338 * @brief Specific device feature definitions
13339 */
13340#define RNG_VER_3_1
13341
13342/******************** Bits definition for RNG_CR register *******************/
13343#define RNG_CR_RNGEN_Pos (2U)
13344#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
13345#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
13346#define RNG_CR_IE_Pos (3U)
13347#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
13348#define RNG_CR_IE RNG_CR_IE_Msk
13349#define RNG_CR_CED_Pos (5U)
13350#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
13351#define RNG_CR_CED RNG_CR_CED_Msk
13352#define RNG_CR_RNG_CONFIG3_Pos (8U)
13353#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */
13354#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk
13355#define RNG_CR_RNG_CONFIG3_0 (0x01UL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000100 */
13356#define RNG_CR_RNG_CONFIG3_1 (0x02UL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000200 */
13357#define RNG_CR_RNG_CONFIG3_2 (0x04UL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000400 */
13358#define RNG_CR_RNG_CONFIG3_3 (0x08UL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000800 */
13359#define RNG_CR_NISTC_Pos (12U)
13360#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */
13361#define RNG_CR_NISTC RNG_CR_NISTC_Msk
13362#define RNG_CR_RNG_CONFIG2_Pos (13U)
13363#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */
13364#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk
13365#define RNG_CR_RNG_CONFIG2_0 (0x01UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x00002000 */
13366#define RNG_CR_RNG_CONFIG2_1 (0x02UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x00004000 */
13367#define RNG_CR_RNG_CONFIG2_2 (0x04UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x00008000 */
13368#define RNG_CR_CLKDIV_Pos (16U)
13369#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */
13370#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
13371#define RNG_CR_CLKDIV_0 (0x01UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
13372#define RNG_CR_CLKDIV_1 (0x02UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
13373#define RNG_CR_CLKDIV_2 (0x04UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
13374#define RNG_CR_CLKDIV_3 (0x08UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
13375#define RNG_CR_RNG_CONFIG1_Pos (20U)
13376#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */
13377#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
13378#define RNG_CR_RNG_CONFIG1_0 (0x01UL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x00100000 */
13379#define RNG_CR_RNG_CONFIG1_1 (0x02UL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x00200000 */
13380#define RNG_CR_RNG_CONFIG1_2 (0x04UL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x00400000 */
13381#define RNG_CR_RNG_CONFIG1_3 (0x08UL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x00800000 */
13382#define RNG_CR_RNG_CONFIG1_4 (0x08UL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x01000000 */
13383#define RNG_CR_RNG_CONFIG1_5 (0x08UL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x02000000 */
13384#define RNG_CR_CONDRST_Pos (30U)
13385#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */
13386#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk
13387#define RNG_CR_CONFIGLOCK_Pos (31U)
13388#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */
13389#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk
13390
13391/******************** Bits definition for RNG_SR register *******************/
13392#define RNG_SR_DRDY_Pos (0U)
13393#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
13394#define RNG_SR_DRDY RNG_SR_DRDY_Msk
13395#define RNG_SR_CECS_Pos (1U)
13396#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
13397#define RNG_SR_CECS RNG_SR_CECS_Msk
13398#define RNG_SR_SECS_Pos (2U)
13399#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
13400#define RNG_SR_SECS RNG_SR_SECS_Msk
13401#define RNG_SR_CEIS_Pos (5U)
13402#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
13403#define RNG_SR_CEIS RNG_SR_CEIS_Msk
13404#define RNG_SR_SEIS_Pos (6U)
13405#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
13406#define RNG_SR_SEIS RNG_SR_SEIS_Msk
13407
13408/******************** Bits definition for RNG_DR register *******************/
13409#define RNG_DR_RNDATA_Pos (0U)
13410#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */
13411#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk
13412
13413/******************** Bits definition for RNG_HTCR register *****************/
13414#define RNG_HTCR_HTCFG_Pos (0U)
13415#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
13416#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
13417
13418
13419/******************************************************************************/
13420/* */
13421/* Real-Time Clock (RTC) */
13422/* */
13423/******************************************************************************/
13424/******************** Bits definition for RTC_TR register *******************/
13425#define RTC_TR_PM_Pos (22U)
13426#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
13427#define RTC_TR_PM RTC_TR_PM_Msk
13428#define RTC_TR_HT_Pos (20U)
13429#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
13430#define RTC_TR_HT RTC_TR_HT_Msk
13431#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
13432#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
13433#define RTC_TR_HU_Pos (16U)
13434#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
13435#define RTC_TR_HU RTC_TR_HU_Msk
13436#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
13437#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
13438#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
13439#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
13440#define RTC_TR_MNT_Pos (12U)
13441#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
13442#define RTC_TR_MNT RTC_TR_MNT_Msk
13443#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
13444#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
13445#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
13446#define RTC_TR_MNU_Pos (8U)
13447#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
13448#define RTC_TR_MNU RTC_TR_MNU_Msk
13449#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
13450#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
13451#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
13452#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
13453#define RTC_TR_ST_Pos (4U)
13454#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
13455#define RTC_TR_ST RTC_TR_ST_Msk
13456#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
13457#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
13458#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
13459#define RTC_TR_SU_Pos (0U)
13460#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
13461#define RTC_TR_SU RTC_TR_SU_Msk
13462#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
13463#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
13464#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
13465#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
13466
13467/******************** Bits definition for RTC_DR register *******************/
13468#define RTC_DR_YT_Pos (20U)
13469#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
13470#define RTC_DR_YT RTC_DR_YT_Msk
13471#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
13472#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
13473#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
13474#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
13475#define RTC_DR_YU_Pos (16U)
13476#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
13477#define RTC_DR_YU RTC_DR_YU_Msk
13478#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
13479#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
13480#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
13481#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
13482#define RTC_DR_WDU_Pos (13U)
13483#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
13484#define RTC_DR_WDU RTC_DR_WDU_Msk
13485#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
13486#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
13487#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
13488#define RTC_DR_MT_Pos (12U)
13489#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
13490#define RTC_DR_MT RTC_DR_MT_Msk
13491#define RTC_DR_MU_Pos (8U)
13492#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
13493#define RTC_DR_MU RTC_DR_MU_Msk
13494#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
13495#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
13496#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
13497#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
13498#define RTC_DR_DT_Pos (4U)
13499#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
13500#define RTC_DR_DT RTC_DR_DT_Msk
13501#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
13502#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
13503#define RTC_DR_DU_Pos (0U)
13504#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
13505#define RTC_DR_DU RTC_DR_DU_Msk
13506#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
13507#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
13508#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
13509#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
13510
13511/******************** Bits definition for RTC_SSR register ******************/
13512#define RTC_SSR_SS_Pos (0U)
13513#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
13514#define RTC_SSR_SS RTC_SSR_SS_Msk
13515
13516/******************** Bits definition for RTC_ICSR register ******************/
13517#define RTC_ICSR_RECALPF_Pos (16U)
13518#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
13519#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
13520#define RTC_ICSR_INIT_Pos (7U)
13521#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
13522#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
13523#define RTC_ICSR_INITF_Pos (6U)
13524#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
13525#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
13526#define RTC_ICSR_RSF_Pos (5U)
13527#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
13528#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
13529#define RTC_ICSR_INITS_Pos (4U)
13530#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
13531#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
13532#define RTC_ICSR_SHPF_Pos (3U)
13533#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
13534#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
13535#define RTC_ICSR_WUTWF_Pos (2U)
13536#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
13537#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
13538
13539/******************** Bits definition for RTC_PRER register *****************/
13540#define RTC_PRER_PREDIV_A_Pos (16U)
13541#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
13542#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
13543#define RTC_PRER_PREDIV_S_Pos (0U)
13544#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
13545#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
13546
13547/******************** Bits definition for RTC_WUTR register *****************/
13548#define RTC_WUTR_WUTOCLR_Pos (16U)
13549#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0xFFFF0000 */
13550#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk
13551#define RTC_WUTR_WUT_Pos (0U)
13552#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
13553#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
13554
13555/******************** Bits definition for RTC_CR register *******************/
13556#define RTC_CR_OUT2EN_Pos (31U)
13557#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
13558#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */
13559#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
13560#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
13561#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */
13562#define RTC_CR_TAMPALRM_PU_Pos (29U)
13563#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
13564#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
13565#define RTC_CR_TAMPOE_Pos (26U)
13566#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
13567#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */
13568#define RTC_CR_TAMPTS_Pos (25U)
13569#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
13570#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */
13571#define RTC_CR_ITSE_Pos (24U)
13572#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
13573#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!<Timestamp on internal event enable */
13574#define RTC_CR_COE_Pos (23U)
13575#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
13576#define RTC_CR_COE RTC_CR_COE_Msk
13577#define RTC_CR_OSEL_Pos (21U)
13578#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
13579#define RTC_CR_OSEL RTC_CR_OSEL_Msk
13580#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
13581#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
13582#define RTC_CR_POL_Pos (20U)
13583#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
13584#define RTC_CR_POL RTC_CR_POL_Msk
13585#define RTC_CR_COSEL_Pos (19U)
13586#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
13587#define RTC_CR_COSEL RTC_CR_COSEL_Msk
13588#define RTC_CR_BKP_Pos (18U)
13589#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
13590#define RTC_CR_BKP RTC_CR_BKP_Msk
13591#define RTC_CR_SUB1H_Pos (17U)
13592#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
13593#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
13594#define RTC_CR_ADD1H_Pos (16U)
13595#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
13596#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
13597#define RTC_CR_TSIE_Pos (15U)
13598#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
13599#define RTC_CR_TSIE RTC_CR_TSIE_Msk
13600#define RTC_CR_WUTIE_Pos (14U)
13601#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
13602#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
13603#define RTC_CR_ALRBIE_Pos (13U)
13604#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
13605#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
13606#define RTC_CR_ALRAIE_Pos (12U)
13607#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
13608#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
13609#define RTC_CR_TSE_Pos (11U)
13610#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
13611#define RTC_CR_TSE RTC_CR_TSE_Msk
13612#define RTC_CR_WUTE_Pos (10U)
13613#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
13614#define RTC_CR_WUTE RTC_CR_WUTE_Msk
13615#define RTC_CR_ALRBE_Pos (9U)
13616#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
13617#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
13618#define RTC_CR_ALRAE_Pos (8U)
13619#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
13620#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
13621#define RTC_CR_FMT_Pos (6U)
13622#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
13623#define RTC_CR_FMT RTC_CR_FMT_Msk
13624#define RTC_CR_BYPSHAD_Pos (5U)
13625#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
13626#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
13627#define RTC_CR_REFCKON_Pos (4U)
13628#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
13629#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
13630#define RTC_CR_TSEDGE_Pos (3U)
13631#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
13632#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
13633#define RTC_CR_WUCKSEL_Pos (0U)
13634#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
13635#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
13636#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
13637#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
13638#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
13639
13640/******************** Bits definition for RTC_PRIVCR register ******************/
13641#define RTC_PRIVCR_PRIV_Pos (15U)
13642#define RTC_PRIVCR_PRIV_Msk (0x1UL << RTC_PRIVCR_PRIV_Pos) /*!< 0x00008000 */
13643#define RTC_PRIVCR_PRIV RTC_PRIVCR_PRIV_Msk
13644#define RTC_PRIVCR_INITPRIV_Pos (14U)
13645#define RTC_PRIVCR_INITPRIV_Msk (0x1UL << RTC_PRIVCR_INITPRIV_Pos) /*!< 0x00004000 */
13646#define RTC_PRIVCR_INITPRIV RTC_PRIVCR_INITPRIV_Msk
13647#define RTC_PRIVCR_CALPRIV_Pos (13U)
13648#define RTC_PRIVCR_CALPRIV_Msk (0x1UL << RTC_PRIVCR_CALPRIV_Pos) /*!< 0x00002000 */
13649#define RTC_PRIVCR_CALPRIV RTC_PRIVCR_CALPRIV_Msk
13650#define RTC_PRIVCR_TSPRIV_Pos (3U)
13651#define RTC_PRIVCR_TSPRIV_Msk (0x1UL << RTC_PRIVCR_TSPRIV_Pos) /*!< 0x00000008 */
13652#define RTC_PRIVCR_TSPRIV RTC_PRIVCR_TSPRIV_Msk
13653#define RTC_PRIVCR_WUTPRIV_Pos (2U)
13654#define RTC_PRIVCR_WUTPRIV_Msk (0x1UL << RTC_PRIVCR_WUTPRIV_Pos) /*!< 0x00000004 */
13655#define RTC_PRIVCR_WUTPRIV RTC_PRIVCR_WUTPRIV_Msk
13656#define RTC_PRIVCR_ALRBPRIV_Pos (1U)
13657#define RTC_PRIVCR_ALRBPRIV_Msk (0x1UL << RTC_PRIVCR_ALRBPRIV_Pos) /*!< 0x00000002 */
13658#define RTC_PRIVCR_ALRBPRIV RTC_PRIVCR_ALRBPRIV_Msk
13659#define RTC_PRIVCR_ALRAPRIV_Pos (0U)
13660#define RTC_PRIVCR_ALRAPRIV_Msk (0x1UL << RTC_PRIVCR_ALRAPRIV_Pos) /*!< 0x00000001 */
13661#define RTC_PRIVCR_ALRAPRIV RTC_PRIVCR_ALRAPRIV_Msk
13662
13663/******************** Bits definition for RTC_SMCR register ******************/
13664#define RTC_SMCR_DECPROT_Pos (15U)
13665#define RTC_SMCR_DECPROT_Msk (0x1UL << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */
13666#define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk
13667#define RTC_SMCR_INITDPROT_Pos (14U)
13668#define RTC_SMCR_INITDPROT_Msk (0x1UL << RTC_SMCR_INITDPROT_Pos) /*!< 0x00004000 */
13669#define RTC_SMCR_INITDPROT RTC_SMCR_INITDPROT_Msk
13670#define RTC_SMCR_CALDPROT_Pos (13U)
13671#define RTC_SMCR_CALDPROT_Msk (0x1UL << RTC_SMCR_CALDPROT_Pos) /*!< 0x00002000 */
13672#define RTC_SMCR_CALDPROT RTC_SMCR_CALDPROT_Msk
13673#define RTC_SMCR_TSDPROT_Pos (3U)
13674#define RTC_SMCR_TSDPROT_Msk (0x1UL << RTC_SMCR_TSDPROT_Pos) /*!< 0x00000008 */
13675#define RTC_SMCR_TSDPROT RTC_SMCR_TSDPROT_Msk
13676#define RTC_SMCR_WUTDPROT_Pos (2U)
13677#define RTC_SMCR_WUTDPROT_Msk (0x1UL << RTC_SMCR_WUTDPROT_Pos) /*!< 0x00000004 */
13678#define RTC_SMCR_WUTDPROT RTC_SMCR_WUTDPROT_Msk
13679#define RTC_SMCR_ALRBDPROT_Pos (1U)
13680#define RTC_SMCR_ALRBDPROT_Msk (0x1UL << RTC_SMCR_ALRBDPROT_Pos) /*!< 0x00000002 */
13681#define RTC_SMCR_ALRBDPROT RTC_SMCR_ALRBDPROT_Msk
13682#define RTC_SMCR_ALRADPROT_Pos (0U)
13683#define RTC_SMCR_ALRADPROT_Msk (0x1UL << RTC_SMCR_ALRADPROT_Pos) /*!< 0x00000001 */
13684#define RTC_SMCR_ALRADPROT RTC_SMCR_ALRADPROT_Msk
13685
13686/******************** Bits definition for RTC_WPR register ******************/
13687#define RTC_WPR_KEY_Pos (0U)
13688#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
13689#define RTC_WPR_KEY RTC_WPR_KEY_Msk
13690
13691/******************** Bits definition for RTC_CALR register *****************/
13692#define RTC_CALR_CALP_Pos (15U)
13693#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
13694#define RTC_CALR_CALP RTC_CALR_CALP_Msk
13695#define RTC_CALR_CALW8_Pos (14U)
13696#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
13697#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
13698#define RTC_CALR_CALW16_Pos (13U)
13699#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
13700#define RTC_CALR_LPCAL RTC_CALR_LPCAL_Msk
13701#define RTC_CALR_LPCAL_Pos (12U)
13702#define RTC_CALR_LPCAL_Msk (0x1UL << RTC_CALR_LPCAL_Pos) /*!< 0x00001000 */
13703#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
13704#define RTC_CALR_CALM_Pos (0U)
13705#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
13706#define RTC_CALR_CALM RTC_CALR_CALM_Msk
13707#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
13708#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
13709#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
13710#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
13711#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
13712#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
13713#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
13714#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
13715#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
13716
13717/******************** Bits definition for RTC_SHIFTR register ***************/
13718#define RTC_SHIFTR_ADD1S_Pos (31U)
13719#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
13720#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
13721#define RTC_SHIFTR_SUBFS_Pos (0U)
13722#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
13723#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
13724
13725/******************** Bits definition for RTC_TSTR register *****************/
13726#define RTC_TSTR_PM_Pos (22U)
13727#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
13728#define RTC_TSTR_PM RTC_TSTR_PM_Msk
13729#define RTC_TSTR_HT_Pos (20U)
13730#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
13731#define RTC_TSTR_HT RTC_TSTR_HT_Msk
13732#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
13733#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
13734#define RTC_TSTR_HU_Pos (16U)
13735#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
13736#define RTC_TSTR_HU RTC_TSTR_HU_Msk
13737#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
13738#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
13739#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
13740#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
13741#define RTC_TSTR_MNT_Pos (12U)
13742#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
13743#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
13744#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
13745#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
13746#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
13747#define RTC_TSTR_MNU_Pos (8U)
13748#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
13749#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
13750#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
13751#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
13752#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
13753#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
13754#define RTC_TSTR_ST_Pos (4U)
13755#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
13756#define RTC_TSTR_ST RTC_TSTR_ST_Msk
13757#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
13758#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
13759#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
13760#define RTC_TSTR_SU_Pos (0U)
13761#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
13762#define RTC_TSTR_SU RTC_TSTR_SU_Msk
13763#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
13764#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
13765#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
13766#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
13767
13768/******************** Bits definition for RTC_TSDR register *****************/
13769#define RTC_TSDR_WDU_Pos (13U)
13770#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
13771#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
13772#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
13773#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
13774#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
13775#define RTC_TSDR_MT_Pos (12U)
13776#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
13777#define RTC_TSDR_MT RTC_TSDR_MT_Msk
13778#define RTC_TSDR_MU_Pos (8U)
13779#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
13780#define RTC_TSDR_MU RTC_TSDR_MU_Msk
13781#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
13782#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
13783#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
13784#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
13785#define RTC_TSDR_DT_Pos (4U)
13786#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
13787#define RTC_TSDR_DT RTC_TSDR_DT_Msk
13788#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
13789#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
13790#define RTC_TSDR_DU_Pos (0U)
13791#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
13792#define RTC_TSDR_DU RTC_TSDR_DU_Msk
13793#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
13794#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
13795#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
13796#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
13797
13798/******************** Bits definition for RTC_TSSSR register ****************/
13799#define RTC_TSSSR_SS_Pos (0U)
13800#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
13801#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
13802
13803/******************** Bits definition for RTC_ALRMAR register ***************/
13804#define RTC_ALRMAR_MSK4_Pos (31U)
13805#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
13806#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
13807#define RTC_ALRMAR_WDSEL_Pos (30U)
13808#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
13809#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
13810#define RTC_ALRMAR_DT_Pos (28U)
13811#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
13812#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
13813#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
13814#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
13815#define RTC_ALRMAR_DU_Pos (24U)
13816#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
13817#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
13818#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
13819#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
13820#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
13821#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
13822#define RTC_ALRMAR_MSK3_Pos (23U)
13823#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
13824#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
13825#define RTC_ALRMAR_PM_Pos (22U)
13826#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
13827#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
13828#define RTC_ALRMAR_HT_Pos (20U)
13829#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
13830#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
13831#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
13832#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
13833#define RTC_ALRMAR_HU_Pos (16U)
13834#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
13835#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
13836#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
13837#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
13838#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
13839#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
13840#define RTC_ALRMAR_MSK2_Pos (15U)
13841#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
13842#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
13843#define RTC_ALRMAR_MNT_Pos (12U)
13844#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
13845#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
13846#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
13847#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
13848#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
13849#define RTC_ALRMAR_MNU_Pos (8U)
13850#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
13851#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
13852#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
13853#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
13854#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
13855#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
13856#define RTC_ALRMAR_MSK1_Pos (7U)
13857#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
13858#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
13859#define RTC_ALRMAR_ST_Pos (4U)
13860#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
13861#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
13862#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
13863#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
13864#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
13865#define RTC_ALRMAR_SU_Pos (0U)
13866#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
13867#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
13868#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
13869#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
13870#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
13871#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
13872
13873/******************** Bits definition for RTC_ALRMASSR register *************/
13874#define RTC_ALRMASSR_MASKSS_Pos (24U)
13875#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
13876#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
13877#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
13878#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
13879#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
13880#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
13881#define RTC_ALRMASSR_SS_Pos (0U)
13882#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
13883#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
13884
13885/******************** Bits definition for RTC_ALRMBR register ***************/
13886#define RTC_ALRMBR_MSK4_Pos (31U)
13887#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
13888#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
13889#define RTC_ALRMBR_WDSEL_Pos (30U)
13890#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
13891#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
13892#define RTC_ALRMBR_DT_Pos (28U)
13893#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
13894#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
13895#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
13896#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
13897#define RTC_ALRMBR_DU_Pos (24U)
13898#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
13899#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
13900#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
13901#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
13902#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
13903#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
13904#define RTC_ALRMBR_MSK3_Pos (23U)
13905#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
13906#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
13907#define RTC_ALRMBR_PM_Pos (22U)
13908#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
13909#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
13910#define RTC_ALRMBR_HT_Pos (20U)
13911#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
13912#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
13913#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
13914#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
13915#define RTC_ALRMBR_HU_Pos (16U)
13916#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
13917#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
13918#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
13919#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
13920#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
13921#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
13922#define RTC_ALRMBR_MSK2_Pos (15U)
13923#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
13924#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
13925#define RTC_ALRMBR_MNT_Pos (12U)
13926#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
13927#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
13928#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
13929#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
13930#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
13931#define RTC_ALRMBR_MNU_Pos (8U)
13932#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
13933#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
13934#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
13935#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
13936#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
13937#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
13938#define RTC_ALRMBR_MSK1_Pos (7U)
13939#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
13940#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
13941#define RTC_ALRMBR_ST_Pos (4U)
13942#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
13943#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
13944#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
13945#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
13946#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
13947#define RTC_ALRMBR_SU_Pos (0U)
13948#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
13949#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
13950#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
13951#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
13952#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
13953#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
13954
13955/******************** Bits definition for RTC_ALRMBSSR register *************/
13956#define RTC_ALRMBSSR_MASKSS_Pos (24U)
13957#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
13958#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
13959#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
13960#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
13961#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
13962#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
13963#define RTC_ALRMBSSR_SS_Pos (0U)
13964#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
13965#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
13966
13967/******************** Bits definition for RTC_SR register *******************/
13968#define RTC_SR_ITSF_Pos (5U)
13969#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
13970#define RTC_SR_ITSF RTC_SR_ITSF_Msk
13971#define RTC_SR_TSOVF_Pos (4U)
13972#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
13973#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
13974#define RTC_SR_TSF_Pos (3U)
13975#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
13976#define RTC_SR_TSF RTC_SR_TSF_Msk
13977#define RTC_SR_WUTF_Pos (2U)
13978#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
13979#define RTC_SR_WUTF RTC_SR_WUTF_Msk
13980#define RTC_SR_ALRBF_Pos (1U)
13981#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
13982#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
13983#define RTC_SR_ALRAF_Pos (0U)
13984#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
13985#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
13986
13987/******************** Bits definition for RTC_MISR register *****************/
13988#define RTC_MISR_ITSMF_Pos (5U)
13989#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
13990#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
13991#define RTC_MISR_TSOVMF_Pos (4U)
13992#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
13993#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
13994#define RTC_MISR_TSMF_Pos (3U)
13995#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
13996#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
13997#define RTC_MISR_WUTMF_Pos (2U)
13998#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
13999#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
14000#define RTC_MISR_ALRBMF_Pos (1U)
14001#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
14002#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
14003#define RTC_MISR_ALRAMF_Pos (0U)
14004#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
14005#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
14006
14007/******************** Bits definition for RTC_SMISR register *****************/
14008#define RTC_SMISR_ITSMF_Pos (5U)
14009#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */
14010#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk
14011#define RTC_SMISR_TSOVMF_Pos (4U)
14012#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */
14013#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk
14014#define RTC_SMISR_TSMF_Pos (3U)
14015#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */
14016#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk
14017#define RTC_SMISR_WUTMF_Pos (2U)
14018#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */
14019#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk
14020#define RTC_SMISR_ALRBMF_Pos (1U)
14021#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */
14022#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk
14023#define RTC_SMISR_ALRAMF_Pos (0U)
14024#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */
14025#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk
14026
14027/******************** Bits definition for RTC_SCR register ******************/
14028#define RTC_SCR_CITSF_Pos (5U)
14029#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
14030#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
14031#define RTC_SCR_CTSOVF_Pos (4U)
14032#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
14033#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
14034#define RTC_SCR_CTSF_Pos (3U)
14035#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
14036#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
14037#define RTC_SCR_CWUTF_Pos (2U)
14038#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
14039#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
14040#define RTC_SCR_CALRBF_Pos (1U)
14041#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
14042#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
14043#define RTC_SCR_CALRAF_Pos (0U)
14044#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
14045#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
14046
14047
14048/******************************************************************************/
14049/* */
14050/* Serial Peripheral Interface (SPI) */
14051/* */
14052/******************************************************************************/
14053/******************* Bit definition for SPI_CR1 register ********************/
14054#define SPI_CR1_CPHA_Pos (0U)
14055#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
14056#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
14057#define SPI_CR1_CPOL_Pos (1U)
14058#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
14059#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
14060#define SPI_CR1_MSTR_Pos (2U)
14061#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
14062#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
14063
14064#define SPI_CR1_BR_Pos (3U)
14065#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
14066#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
14067#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
14068#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
14069#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
14070
14071#define SPI_CR1_SPE_Pos (6U)
14072#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
14073#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
14074#define SPI_CR1_LSBFIRST_Pos (7U)
14075#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
14076#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
14077#define SPI_CR1_SSI_Pos (8U)
14078#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
14079#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
14080#define SPI_CR1_SSM_Pos (9U)
14081#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
14082#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
14083#define SPI_CR1_RXONLY_Pos (10U)
14084#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
14085#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
14086#define SPI_CR1_CRCL_Pos (11U)
14087#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
14088#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
14089#define SPI_CR1_CRCNEXT_Pos (12U)
14090#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
14091#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
14092#define SPI_CR1_CRCEN_Pos (13U)
14093#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
14094#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
14095#define SPI_CR1_BIDIOE_Pos (14U)
14096#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
14097#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
14098#define SPI_CR1_BIDIMODE_Pos (15U)
14099#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
14100#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
14101
14102/******************* Bit definition for SPI_CR2 register ********************/
14103#define SPI_CR2_RXDMAEN_Pos (0U)
14104#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
14105#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
14106#define SPI_CR2_TXDMAEN_Pos (1U)
14107#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
14108#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
14109#define SPI_CR2_SSOE_Pos (2U)
14110#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
14111#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
14112#define SPI_CR2_NSSP_Pos (3U)
14113#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
14114#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
14115#define SPI_CR2_FRF_Pos (4U)
14116#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
14117#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
14118#define SPI_CR2_ERRIE_Pos (5U)
14119#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
14120#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
14121#define SPI_CR2_RXNEIE_Pos (6U)
14122#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
14123#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
14124#define SPI_CR2_TXEIE_Pos (7U)
14125#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
14126#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
14127#define SPI_CR2_DS_Pos (8U)
14128#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
14129#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
14130#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
14131#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
14132#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
14133#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
14134#define SPI_CR2_FRXTH_Pos (12U)
14135#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
14136#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
14137#define SPI_CR2_LDMARX_Pos (13U)
14138#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
14139#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
14140#define SPI_CR2_LDMATX_Pos (14U)
14141#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
14142#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
14143
14144/******************** Bit definition for SPI_SR register ********************/
14145#define SPI_SR_RXNE_Pos (0U)
14146#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
14147#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
14148#define SPI_SR_TXE_Pos (1U)
14149#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
14150#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
14151#define SPI_SR_CRCERR_Pos (4U)
14152#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
14153#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
14154#define SPI_SR_MODF_Pos (5U)
14155#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
14156#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
14157#define SPI_SR_OVR_Pos (6U)
14158#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
14159#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
14160#define SPI_SR_BSY_Pos (7U)
14161#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
14162#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
14163#define SPI_SR_FRE_Pos (8U)
14164#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
14165#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
14166#define SPI_SR_FRLVL_Pos (9U)
14167#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
14168#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
14169#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
14170#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
14171#define SPI_SR_FTLVL_Pos (11U)
14172#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
14173#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
14174#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
14175#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
14176
14177/******************** Bit definition for SPI_DR register ********************/
14178#define SPI_DR_DR_Pos (0U)
14179#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
14180#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
14181
14182/******************* Bit definition for SPI_CRCPR register ******************/
14183#define SPI_CRCPR_CRCPOLY_Pos (0U)
14184#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
14185#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
14186
14187/****************** Bit definition for SPI_RXCRCR register ******************/
14188#define SPI_RXCRCR_RXCRC_Pos (0U)
14189#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
14190#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
14191
14192/****************** Bit definition for SPI_TXCRCR register ******************/
14193#define SPI_TXCRCR_TXCRC_Pos (0U)
14194#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
14195#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
14196
14197
14198/******************************************************************************/
14199/* */
14200/* Tamper and backup register (TAMP) */
14201/* */
14202/******************************************************************************/
14203/******************** Bits definition for TAMP_CR1 register *****************/
14204#define TAMP_CR1_TAMP1E_Pos (0U)
14205#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
14206#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
14207#define TAMP_CR1_TAMP2E_Pos (1U)
14208#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
14209#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
14210#define TAMP_CR1_TAMP3E_Pos (2U)
14211#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
14212#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
14213#define TAMP_CR1_TAMP4E_Pos (3U)
14214#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */
14215#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk
14216#define TAMP_CR1_TAMP5E_Pos (4U)
14217#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */
14218#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk
14219#define TAMP_CR1_TAMP6E_Pos (5U)
14220#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */
14221#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk
14222#define TAMP_CR1_TAMP7E_Pos (6U)
14223#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */
14224#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk
14225#define TAMP_CR1_TAMP8E_Pos (7U)
14226#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */
14227#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk
14228#define TAMP_CR1_ITAMP1E_Pos (16U)
14229#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */
14230#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk
14231#define TAMP_CR1_ITAMP2E_Pos (17U)
14232#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */
14233#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk
14234#define TAMP_CR1_ITAMP3E_Pos (18U)
14235#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
14236#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
14237#define TAMP_CR1_ITAMP5E_Pos (20U)
14238#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
14239#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
14240#define TAMP_CR1_ITAMP8E_Pos (23U)
14241#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */
14242#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk
14243
14244/******************** Bits definition for TAMP_CR2 register *****************/
14245#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
14246#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
14247#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
14248#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
14249#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
14250#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
14251#define TAMP_CR2_TAMP3NOERASE_Pos (2U)
14252#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
14253#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
14254#define TAMP_CR2_TAMP4NOERASE_Pos (3U)
14255#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */
14256#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk
14257#define TAMP_CR2_TAMP5NOERASE_Pos (4U)
14258#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */
14259#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk
14260#define TAMP_CR2_TAMP6NOERASE_Pos (5U)
14261#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */
14262#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk
14263#define TAMP_CR2_TAMP7NOERASE_Pos (6U)
14264#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */
14265#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk
14266#define TAMP_CR2_TAMP8NOERASE_Pos (7U)
14267#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */
14268#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk
14269#define TAMP_CR2_TAMP1MSK_Pos (16U)
14270#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */
14271#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
14272#define TAMP_CR2_TAMP2MSK_Pos (17U)
14273#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */
14274#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
14275#define TAMP_CR2_TAMP3MSK_Pos (18U)
14276#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */
14277#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk
14278#define TAMP_CR2_BKERASE_Pos (23U)
14279#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */
14280#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk
14281#define TAMP_CR2_TAMP1TRG_Pos (24U)
14282#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
14283#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
14284#define TAMP_CR2_TAMP2TRG_Pos (25U)
14285#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
14286#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
14287#define TAMP_CR2_TAMP3TRG_Pos (26U)
14288#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */
14289#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
14290#define TAMP_CR2_TAMP4TRG_Pos (27U)
14291#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */
14292#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk
14293#define TAMP_CR2_TAMP5TRG_Pos (28U)
14294#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */
14295#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk
14296#define TAMP_CR2_TAMP6TRG_Pos (29U)
14297#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */
14298#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk
14299#define TAMP_CR2_TAMP7TRG_Pos (30U)
14300#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */
14301#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk
14302#define TAMP_CR2_TAMP8TRG_Pos (31U)
14303#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */
14304#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk
14305
14306/******************** Bits definition for TAMP_CR3 register *****************/
14307#define TAMP_CR3_ITAMP1NOER_Pos (0U)
14308#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */
14309#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk
14310#define TAMP_CR3_ITAMP2NOER_Pos (1U)
14311#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */
14312#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk
14313#define TAMP_CR3_ITAMP3NOER_Pos (2U)
14314#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */
14315#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk
14316#define TAMP_CR3_ITAMP5NOER_Pos (4U)
14317#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */
14318#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk
14319#define TAMP_CR3_ITAMP8NOER_Pos (7U)
14320#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */
14321#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk
14322
14323/******************** Bits definition for TAMP_FLTCR register ***************/
14324#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
14325#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
14326#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
14327#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */
14328#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */
14329#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */
14330#define TAMP_FLTCR_TAMPFLT_Pos (3U)
14331#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
14332#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
14333#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */
14334#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */
14335#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
14336#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
14337#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
14338#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */
14339#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */
14340#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
14341#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
14342#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
14343
14344/******************** Bits definition for TAMP_ATCR1 register ***************/
14345#define TAMP_ATCR1_TAMP1AM_Pos (0U)
14346#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <<TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */
14347#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk
14348#define TAMP_ATCR1_TAMP2AM_Pos (1U)
14349#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL <<TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */
14350#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk
14351#define TAMP_ATCR1_TAMP3AM_Pos (2U)
14352#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL <<TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */
14353#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk
14354#define TAMP_ATCR1_TAMP4AM_Pos (3U)
14355#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL <<TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */
14356#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk
14357#define TAMP_ATCR1_TAMP5AM_Pos (4U)
14358#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL <<TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */
14359#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk
14360#define TAMP_ATCR1_TAMP6AM_Pos (6U)
14361#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL <<TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000020 */
14362#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk
14363#define TAMP_ATCR1_TAMP7AM_Pos (6U)
14364#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL <<TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */
14365#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk
14366#define TAMP_ATCR1_TAMP8AM_Pos (7U)
14367#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL <<TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */
14368#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk
14369#define TAMP_ATCR1_ATOSEL1_Pos (8U)
14370#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL <<TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */
14371#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk
14372#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */
14373#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */
14374#define TAMP_ATCR1_ATOSEL2_Pos (10U)
14375#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL <<TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */
14376#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk
14377#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */
14378#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */
14379#define TAMP_ATCR1_ATOSEL3_Pos (12U)
14380#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL <<TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */
14381#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk
14382#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */
14383#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */
14384#define TAMP_ATCR1_ATOSEL4_Pos (14U)
14385#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL <<TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */
14386#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk
14387#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */
14388#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */
14389#define TAMP_ATCR1_ATCKSEL_Pos (16U)
14390#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL <<TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */
14391#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk
14392#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */
14393#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */
14394#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */
14395#define TAMP_ATCR1_ATPER_Pos (24U)
14396#define TAMP_ATCR1_ATPER_Msk (0x7UL <<TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */
14397#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk
14398#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */
14399#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */
14400#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */
14401#define TAMP_ATCR1_ATOSHARE_Pos (30U)
14402#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL <<TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */
14403#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk
14404#define TAMP_ATCR1_FLTEN_Pos (31U)
14405#define TAMP_ATCR1_FLTEN_Msk (0x1UL <<TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */
14406#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk
14407
14408/******************** Bits definition for TAMP_ATSEEDR register ******************/
14409#define TAMP_ATSEEDR_SEED_Pos (0U)
14410#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
14411#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk
14412
14413/******************** Bits definition for TAMP_ATOR register ******************/
14414#define TAMP_ATOR_PRNG_Pos (0U)
14415#define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */
14416#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk
14417#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */
14418#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */
14419#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */
14420#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */
14421#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */
14422#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */
14423#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */
14424#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */
14425#define TAMP_ATOR_SEEDF_Pos (14U)
14426#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */
14427#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk
14428#define TAMP_ATOR_INITS_Pos (15U)
14429#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */
14430#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk
14431
14432/******************** Bits definition for TAMP_ATCR2 register ***************/
14433#define TAMP_ATCR2_ATOSEL1_Pos (8U)
14434#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL <<TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */
14435#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk
14436#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */
14437#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */
14438#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */
14439#define TAMP_ATCR2_ATOSEL2_Pos (11U)
14440#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL <<TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */
14441#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk
14442#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */
14443#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */
14444#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */
14445#define TAMP_ATCR2_ATOSEL3_Pos (14U)
14446#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL <<TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */
14447#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk
14448#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */
14449#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */
14450#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */
14451#define TAMP_ATCR2_ATOSEL4_Pos (17U)
14452#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL <<TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */
14453#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk
14454#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */
14455#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */
14456#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */
14457#define TAMP_ATCR2_ATOSEL5_Pos (20U)
14458#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL <<TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */
14459#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk
14460#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */
14461#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */
14462#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */
14463#define TAMP_ATCR2_ATOSEL6_Pos (23U)
14464#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL <<TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */
14465#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk
14466#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */
14467#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */
14468#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */
14469#define TAMP_ATCR2_ATOSEL7_Pos (26U)
14470#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL <<TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */
14471#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk
14472#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */
14473#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */
14474#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */
14475#define TAMP_ATCR2_ATOSEL8_Pos (29U)
14476#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL <<TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */
14477#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk
14478#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */
14479#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */
14480#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */
14481
14482/******************** Bits definition for TAMP_SMCR register ******************/
14483#define TAMP_SMCR_BKPRWDPROT_Pos (0U)
14484#define TAMP_SMCR_BKPRWDPROT_Msk (0xFFUL << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x000000FF */
14485#define TAMP_SMCR_BKPRWDPROT TAMP_SMCR_BKPRWDPROT_Msk
14486#define TAMP_SMCR_BKPRWDPROT_0 (0x1UL << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000001 */
14487#define TAMP_SMCR_BKPRWDPROT_1 (0x2UL << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000002 */
14488#define TAMP_SMCR_BKPRWDPROT_2 (0x4UL << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000004 */
14489#define TAMP_SMCR_BKPRWDPROT_3 (0x8UL << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000008 */
14490#define TAMP_SMCR_BKPRWDPROT_4 (0x1UL << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000010 */
14491#define TAMP_SMCR_BKPRWDPROT_5 (0x20UL << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000020 */
14492#define TAMP_SMCR_BKPRWDPROT_6 (0x40UL << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000040 */
14493#define TAMP_SMCR_BKPRWDPROT_7 (0x80UL << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000080 */
14494#define TAMP_SMCR_BKPWDPROT_Pos (16U)
14495#define TAMP_SMCR_BKPWDPROT_Msk (0xFFUL << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00FF0000 */
14496#define TAMP_SMCR_BKPWDPROT TAMP_SMCR_BKPWDPROT_Msk
14497#define TAMP_SMCR_BKPWDPROT_0 (0x1UL << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00010000 */
14498#define TAMP_SMCR_BKPWDPROT_1 (0x2UL << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00020000 */
14499#define TAMP_SMCR_BKPWDPROT_2 (0x4UL << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00040000 */
14500#define TAMP_SMCR_BKPWDPROT_3 (0x8UL << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00080000 */
14501#define TAMP_SMCR_BKPWDPROT_4 (0x1UL << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00100000 */
14502#define TAMP_SMCR_BKPWDPROT_5 (0x20UL << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00200000 */
14503#define TAMP_SMCR_BKPWDPROT_6 (0x40UL << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00400000 */
14504#define TAMP_SMCR_BKPWDPROT_7 (0x80UL << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00800000 */
14505#define TAMP_SMCR_TAMPDPROT_Pos (31U)
14506#define TAMP_SMCR_TAMPDPROT_Msk (0x1UL << TAMP_SMCR_TAMPDPROT_Pos) /*!< 0x80000000 */
14507#define TAMP_SMCR_TAMPDPROT TAMP_SMCR_TAMPDPROT_Msk
14508
14509/******************** Bits definition for TAMP_PRIVCR register ******************/
14510#define TAMP_PRIVCR_BKPRWPRIV_Pos (29U)
14511#define TAMP_PRIVCR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCR_BKPRWPRIV_Pos) /*!< 0x20000000 */
14512#define TAMP_PRIVCR_BKPRWPRIV TAMP_PRIVCR_BKPRWPRIV_Msk
14513#define TAMP_PRIVCR_BKPWPRIV_Pos (30U)
14514#define TAMP_PRIVCR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCR_BKPWPRIV_Pos) /*!< 0x40000000 */
14515#define TAMP_PRIVCR_BKPWPRIV TAMP_PRIVCR_BKPWPRIV_Msk
14516#define TAMP_PRIVCR_TAMPPRIV_Pos (31U)
14517#define TAMP_PRIVCR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCR_TAMPPRIV_Pos) /*!< 0x80000000 */
14518#define TAMP_PRIVCR_TAMPPRIV TAMP_PRIVCR_TAMPPRIV_Msk
14519
14520/******************** Bits definition for TAMP_IER register *****************/
14521#define TAMP_IER_TAMP1IE_Pos (0U)
14522#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
14523#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
14524#define TAMP_IER_TAMP2IE_Pos (1U)
14525#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
14526#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
14527#define TAMP_IER_TAMP3IE_Pos (2U)
14528#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
14529#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
14530#define TAMP_IER_TAMP4IE_Pos (3U)
14531#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */
14532#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk
14533#define TAMP_IER_TAMP5IE_Pos (4U)
14534#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */
14535#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk
14536#define TAMP_IER_TAMP6IE_Pos (5U)
14537#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */
14538#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk
14539#define TAMP_IER_TAMP7IE_Pos (6U)
14540#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */
14541#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk
14542#define TAMP_IER_TAMP8IE_Pos (7U)
14543#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */
14544#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk
14545#define TAMP_IER_ITAMP1IE_Pos (16U)
14546#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */
14547#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk
14548#define TAMP_IER_ITAMP2IE_Pos (17U)
14549#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */
14550#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk
14551#define TAMP_IER_ITAMP3IE_Pos (18U)
14552#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
14553#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
14554#define TAMP_IER_ITAMP5IE_Pos (20U)
14555#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
14556#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
14557#define TAMP_IER_ITAMP8IE_Pos (23U)
14558#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00400000 */
14559#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk
14560
14561/******************** Bits definition for TAMP_SR register *****************/
14562#define TAMP_SR_TAMP1F_Pos (0U)
14563#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
14564#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
14565#define TAMP_SR_TAMP2F_Pos (1U)
14566#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
14567#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
14568#define TAMP_SR_TAMP3F_Pos (2U)
14569#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
14570#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
14571#define TAMP_SR_TAMP4F_Pos (3U)
14572#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */
14573#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk
14574#define TAMP_SR_TAMP5F_Pos (4U)
14575#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */
14576#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk
14577#define TAMP_SR_TAMP6F_Pos (5U)
14578#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */
14579#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk
14580#define TAMP_SR_TAMP7F_Pos (6U)
14581#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */
14582#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk
14583#define TAMP_SR_TAMP8F_Pos (7U)
14584#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */
14585#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk
14586#define TAMP_SR_ITAMP1F_Pos (16U)
14587#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */
14588#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk
14589#define TAMP_SR_ITAMP2F_Pos (17U)
14590#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */
14591#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk
14592#define TAMP_SR_ITAMP3F_Pos (18U)
14593#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
14594#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
14595#define TAMP_SR_ITAMP5F_Pos (20U)
14596#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
14597#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
14598#define TAMP_SR_ITAMP8F_Pos (23U)
14599#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00400000 */
14600#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk
14601
14602/******************** Bits definition for TAMP_MISR register ************ *****/
14603#define TAMP_MISR_TAMP1MF_Pos (0U)
14604#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
14605#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
14606#define TAMP_MISR_TAMP2MF_Pos (1U)
14607#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
14608#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
14609#define TAMP_MISR_TAMP3MF_Pos (2U)
14610#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
14611#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
14612#define TAMP_MISR_TAMP4MF_Pos (3U)
14613#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */
14614#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk
14615#define TAMP_MISR_TAMP5MF_Pos (4U)
14616#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */
14617#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk
14618#define TAMP_MISR_TAMP6MF_Pos (5U)
14619#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */
14620#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk
14621#define TAMP_MISR_TAMP7MF_Pos (6U)
14622#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */
14623#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk
14624#define TAMP_MISR_TAMP8MF_Pos (7U)
14625#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */
14626#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk
14627#define TAMP_MISR_ITAMP1MF_Pos (16U)
14628#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */
14629#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk
14630#define TAMP_MISR_ITAMP2MF_Pos (17U)
14631#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */
14632#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk
14633#define TAMP_MISR_ITAMP3MF_Pos (18U)
14634#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
14635#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
14636#define TAMP_MISR_ITAMP5MF_Pos (20U)
14637#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
14638#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
14639#define TAMP_MISR_ITAMP8MF_Pos (23U)
14640#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00400000 */
14641#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk
14642
14643/******************** Bits definition for TAMP_SMISR register ************ *****/
14644#define TAMP_SMISR_TAMP1MF_Pos (0U)
14645#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */
14646#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk
14647#define TAMP_SMISR_TAMP2MF_Pos (1U)
14648#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */
14649#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk
14650#define TAMP_SMISR_TAMP3MF_Pos (2U)
14651#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */
14652#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk
14653#define TAMP_SMISR_TAMP4MF_Pos (3U)
14654#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */
14655#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk
14656#define TAMP_SMISR_TAMP5MF_Pos (4U)
14657#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */
14658#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk
14659#define TAMP_SMISR_TAMP6MF_Pos (5U)
14660#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */
14661#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk
14662#define TAMP_SMISR_TAMP7MF_Pos (6U)
14663#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */
14664#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk
14665#define TAMP_SMISR_TAMP8MF_Pos (7U)
14666#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */
14667#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk
14668#define TAMP_SMISR_ITAMP1MF_Pos (16U)
14669#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */
14670#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk
14671#define TAMP_SMISR_ITAMP2MF_Pos (17U)
14672#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */
14673#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk
14674#define TAMP_SMISR_ITAMP3MF_Pos (18U)
14675#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */
14676#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk
14677#define TAMP_SMISR_ITAMP5MF_Pos (20U)
14678#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */
14679#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk
14680#define TAMP_SMISR_ITAMP8MF_Pos (23U)
14681#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00400000 */
14682#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk
14683
14684/******************** Bits definition for TAMP_SCR register *****************/
14685#define TAMP_SCR_CTAMP1F_Pos (0U)
14686#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
14687#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
14688#define TAMP_SCR_CTAMP2F_Pos (1U)
14689#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
14690#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
14691#define TAMP_SCR_CTAMP3F_Pos (2U)
14692#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
14693#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
14694#define TAMP_SCR_CTAMP4F_Pos (3U)
14695#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */
14696#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk
14697#define TAMP_SCR_CTAMP5F_Pos (4U)
14698#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */
14699#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk
14700#define TAMP_SCR_CTAMP6F_Pos (5U)
14701#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */
14702#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk
14703#define TAMP_SCR_CTAMP7F_Pos (6U)
14704#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */
14705#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk
14706#define TAMP_SCR_CTAMP8F_Pos (7U)
14707#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */
14708#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk
14709#define TAMP_SCR_CITAMP1F_Pos (16U)
14710#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */
14711#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk
14712#define TAMP_SCR_CITAMP2F_Pos (17U)
14713#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */
14714#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk
14715#define TAMP_SCR_CITAMP3F_Pos (18U)
14716#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
14717#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
14718#define TAMP_SCR_CITAMP5F_Pos (20U)
14719#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
14720#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
14721#define TAMP_SCR_CITAMP8F_Pos (23U)
14722#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00400000 */
14723#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk
14724
14725/******************** Bits definition for TAMP_COUNTR register ***************/
14726#define TAMP_COUNTR_Pos (16U)
14727#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
14728#define TAMP_COUNTR TAMP_COUNTR_Msk
14729
14730/******************** Bits definition for TAMP_BKP0R register ***************/
14731#define TAMP_BKP0R_Pos (0U)
14732#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
14733#define TAMP_BKP0R TAMP_BKP0R_Msk
14734
14735/******************** Bits definition for TAMP_BKP1R register ****************/
14736#define TAMP_BKP1R_Pos (0U)
14737#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
14738#define TAMP_BKP1R TAMP_BKP1R_Msk
14739
14740/******************** Bits definition for TAMP_BKP2R register ****************/
14741#define TAMP_BKP2R_Pos (0U)
14742#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
14743#define TAMP_BKP2R TAMP_BKP2R_Msk
14744
14745/******************** Bits definition for TAMP_BKP3R register ****************/
14746#define TAMP_BKP3R_Pos (0U)
14747#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
14748#define TAMP_BKP3R TAMP_BKP3R_Msk
14749
14750/******************** Bits definition for TAMP_BKP4R register ****************/
14751#define TAMP_BKP4R_Pos (0U)
14752#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
14753#define TAMP_BKP4R TAMP_BKP4R_Msk
14754
14755/******************** Bits definition for TAMP_BKP5R register ****************/
14756#define TAMP_BKP5R_Pos (0U)
14757#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
14758#define TAMP_BKP5R TAMP_BKP5R_Msk
14759
14760/******************** Bits definition for TAMP_BKP6R register ****************/
14761#define TAMP_BKP6R_Pos (0U)
14762#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
14763#define TAMP_BKP6R TAMP_BKP6R_Msk
14764
14765/******************** Bits definition for TAMP_BKP7R register ****************/
14766#define TAMP_BKP7R_Pos (0U)
14767#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
14768#define TAMP_BKP7R TAMP_BKP7R_Msk
14769
14770/******************** Bits definition for TAMP_BKP8R register ****************/
14771#define TAMP_BKP8R_Pos (0U)
14772#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
14773#define TAMP_BKP8R TAMP_BKP8R_Msk
14774
14775/******************** Bits definition for TAMP_BKP9R register ****************/
14776#define TAMP_BKP9R_Pos (0U)
14777#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
14778#define TAMP_BKP9R TAMP_BKP9R_Msk
14779
14780/******************** Bits definition for TAMP_BKP10R register ***************/
14781#define TAMP_BKP10R_Pos (0U)
14782#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
14783#define TAMP_BKP10R TAMP_BKP10R_Msk
14784
14785/******************** Bits definition for TAMP_BKP11R register ***************/
14786#define TAMP_BKP11R_Pos (0U)
14787#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
14788#define TAMP_BKP11R TAMP_BKP11R_Msk
14789
14790/******************** Bits definition for TAMP_BKP12R register ***************/
14791#define TAMP_BKP12R_Pos (0U)
14792#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
14793#define TAMP_BKP12R TAMP_BKP12R_Msk
14794
14795/******************** Bits definition for TAMP_BKP13R register ***************/
14796#define TAMP_BKP13R_Pos (0U)
14797#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
14798#define TAMP_BKP13R TAMP_BKP13R_Msk
14799
14800/******************** Bits definition for TAMP_BKP14R register ***************/
14801#define TAMP_BKP14R_Pos (0U)
14802#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
14803#define TAMP_BKP14R TAMP_BKP14R_Msk
14804
14805/******************** Bits definition for TAMP_BKP15R register ***************/
14806#define TAMP_BKP15R_Pos (0U)
14807#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
14808#define TAMP_BKP15R TAMP_BKP15R_Msk
14809
14810/******************** Bits definition for TAMP_BKP16R register ***************/
14811#define TAMP_BKP16R_Pos (0U)
14812#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */
14813#define TAMP_BKP16R TAMP_BKP16R_Msk
14814
14815/******************** Bits definition for TAMP_BKP17R register ***************/
14816#define TAMP_BKP17R_Pos (0U)
14817#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */
14818#define TAMP_BKP17R TAMP_BKP17R_Msk
14819
14820/******************** Bits definition for TAMP_BKP18R register ***************/
14821#define TAMP_BKP18R_Pos (0U)
14822#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */
14823#define TAMP_BKP18R TAMP_BKP18R_Msk
14824
14825/******************** Bits definition for TAMP_BKP19R register ***************/
14826#define TAMP_BKP19R_Pos (0U)
14827#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */
14828#define TAMP_BKP19R TAMP_BKP19R_Msk
14829
14830/******************** Bits definition for TAMP_BKP20R register ***************/
14831#define TAMP_BKP20R_Pos (0U)
14832#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */
14833#define TAMP_BKP20R TAMP_BKP20R_Msk
14834
14835/******************** Bits definition for TAMP_BKP21R register ***************/
14836#define TAMP_BKP21R_Pos (0U)
14837#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */
14838#define TAMP_BKP21R TAMP_BKP21R_Msk
14839
14840/******************** Bits definition for TAMP_BKP22R register ***************/
14841#define TAMP_BKP22R_Pos (0U)
14842#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */
14843#define TAMP_BKP22R TAMP_BKP22R_Msk
14844
14845/******************** Bits definition for TAMP_BKP23R register ***************/
14846#define TAMP_BKP23R_Pos (0U)
14847#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */
14848#define TAMP_BKP23R TAMP_BKP23R_Msk
14849
14850/******************** Bits definition for TAMP_BKP24R register ***************/
14851#define TAMP_BKP24R_Pos (0U)
14852#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */
14853#define TAMP_BKP24R TAMP_BKP24R_Msk
14854
14855/******************** Bits definition for TAMP_BKP25R register ***************/
14856#define TAMP_BKP25R_Pos (0U)
14857#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */
14858#define TAMP_BKP25R TAMP_BKP25R_Msk
14859
14860/******************** Bits definition for TAMP_BKP26R register ***************/
14861#define TAMP_BKP26R_Pos (0U)
14862#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */
14863#define TAMP_BKP26R TAMP_BKP26R_Msk
14864
14865/******************** Bits definition for TAMP_BKP27R register ***************/
14866#define TAMP_BKP27R_Pos (0U)
14867#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */
14868#define TAMP_BKP27R TAMP_BKP27R_Msk
14869
14870/******************** Bits definition for TAMP_BKP28R register ***************/
14871#define TAMP_BKP28R_Pos (0U)
14872#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */
14873#define TAMP_BKP28R TAMP_BKP28R_Msk
14874
14875/******************** Bits definition for TAMP_BKP29R register ***************/
14876#define TAMP_BKP29R_Pos (0U)
14877#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */
14878#define TAMP_BKP29R TAMP_BKP29R_Msk
14879
14880/******************** Bits definition for TAMP_BKP30R register ***************/
14881#define TAMP_BKP30R_Pos (0U)
14882#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */
14883#define TAMP_BKP30R TAMP_BKP30R_Msk
14884
14885/******************** Bits definition for TAMP_BKP31R register ***************/
14886#define TAMP_BKP31R_Pos (0U)
14887#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */
14888#define TAMP_BKP31R TAMP_BKP31R_Msk
14889
14890/******************************************************************************/
14891/* */
14892/* TIM */
14893/* */
14894/******************************************************************************/
14895/******************* Bit definition for TIM_CR1 register ********************/
14896#define TIM_CR1_CEN_Pos (0U)
14897#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
14898#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
14899#define TIM_CR1_UDIS_Pos (1U)
14900#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
14901#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
14902#define TIM_CR1_URS_Pos (2U)
14903#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
14904#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
14905#define TIM_CR1_OPM_Pos (3U)
14906#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
14907#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
14908#define TIM_CR1_DIR_Pos (4U)
14909#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
14910#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
14911
14912#define TIM_CR1_CMS_Pos (5U)
14913#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
14914#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
14915#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
14916#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
14917
14918#define TIM_CR1_ARPE_Pos (7U)
14919#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
14920#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
14921
14922#define TIM_CR1_CKD_Pos (8U)
14923#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
14924#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
14925#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
14926#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
14927
14928#define TIM_CR1_UIFREMAP_Pos (11U)
14929#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
14930#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
14931
14932/******************* Bit definition for TIM_CR2 register ********************/
14933#define TIM_CR2_CCPC_Pos (0U)
14934#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
14935#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
14936#define TIM_CR2_CCUS_Pos (2U)
14937#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
14938#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
14939#define TIM_CR2_CCDS_Pos (3U)
14940#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
14941#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
14942
14943#define TIM_CR2_MMS_Pos (4U)
14944#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
14945#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
14946#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
14947#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
14948#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
14949
14950#define TIM_CR2_TI1S_Pos (7U)
14951#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
14952#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
14953#define TIM_CR2_OIS1_Pos (8U)
14954#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
14955#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
14956#define TIM_CR2_OIS1N_Pos (9U)
14957#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
14958#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
14959#define TIM_CR2_OIS2_Pos (10U)
14960#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
14961#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
14962#define TIM_CR2_OIS2N_Pos (11U)
14963#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
14964#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
14965#define TIM_CR2_OIS3_Pos (12U)
14966#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
14967#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
14968#define TIM_CR2_OIS3N_Pos (13U)
14969#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
14970#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
14971#define TIM_CR2_OIS4_Pos (14U)
14972#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
14973#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
14974#define TIM_CR2_OIS5_Pos (16U)
14975#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
14976#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
14977#define TIM_CR2_OIS6_Pos (18U)
14978#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
14979#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
14980
14981#define TIM_CR2_MMS2_Pos (20U)
14982#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
14983#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
14984#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
14985#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
14986#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
14987#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
14988
14989/******************* Bit definition for TIM_SMCR register *******************/
14990#define TIM_SMCR_SMS_Pos (0U)
14991#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
14992#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
14993#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
14994#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
14995#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
14996#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
14997
14998#define TIM_SMCR_TS_Pos (4U)
14999#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
15000#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
15001#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
15002#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
15003#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
15004#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
15005#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
15006
15007#define TIM_SMCR_MSM_Pos (7U)
15008#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
15009#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
15010
15011#define TIM_SMCR_ETF_Pos (8U)
15012#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
15013#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
15014#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
15015#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
15016#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
15017#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
15018
15019#define TIM_SMCR_ETPS_Pos (12U)
15020#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
15021#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
15022#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
15023#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
15024
15025#define TIM_SMCR_ECE_Pos (14U)
15026#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
15027#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
15028#define TIM_SMCR_ETP_Pos (15U)
15029#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
15030#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
15031
15032/******************* Bit definition for TIM_DIER register *******************/
15033#define TIM_DIER_UIE_Pos (0U)
15034#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
15035#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
15036#define TIM_DIER_CC1IE_Pos (1U)
15037#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
15038#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
15039#define TIM_DIER_CC2IE_Pos (2U)
15040#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
15041#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
15042#define TIM_DIER_CC3IE_Pos (3U)
15043#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
15044#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
15045#define TIM_DIER_CC4IE_Pos (4U)
15046#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
15047#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
15048#define TIM_DIER_COMIE_Pos (5U)
15049#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
15050#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
15051#define TIM_DIER_TIE_Pos (6U)
15052#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
15053#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
15054#define TIM_DIER_BIE_Pos (7U)
15055#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
15056#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
15057#define TIM_DIER_UDE_Pos (8U)
15058#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
15059#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
15060#define TIM_DIER_CC1DE_Pos (9U)
15061#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
15062#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
15063#define TIM_DIER_CC2DE_Pos (10U)
15064#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
15065#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
15066#define TIM_DIER_CC3DE_Pos (11U)
15067#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
15068#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
15069#define TIM_DIER_CC4DE_Pos (12U)
15070#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
15071#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
15072#define TIM_DIER_COMDE_Pos (13U)
15073#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
15074#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
15075#define TIM_DIER_TDE_Pos (14U)
15076#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
15077#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
15078
15079/******************** Bit definition for TIM_SR register ********************/
15080#define TIM_SR_UIF_Pos (0U)
15081#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
15082#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
15083#define TIM_SR_CC1IF_Pos (1U)
15084#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
15085#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
15086#define TIM_SR_CC2IF_Pos (2U)
15087#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
15088#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
15089#define TIM_SR_CC3IF_Pos (3U)
15090#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
15091#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
15092#define TIM_SR_CC4IF_Pos (4U)
15093#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
15094#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
15095#define TIM_SR_COMIF_Pos (5U)
15096#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
15097#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
15098#define TIM_SR_TIF_Pos (6U)
15099#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
15100#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
15101#define TIM_SR_BIF_Pos (7U)
15102#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
15103#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
15104#define TIM_SR_B2IF_Pos (8U)
15105#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
15106#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
15107#define TIM_SR_CC1OF_Pos (9U)
15108#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
15109#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
15110#define TIM_SR_CC2OF_Pos (10U)
15111#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
15112#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
15113#define TIM_SR_CC3OF_Pos (11U)
15114#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
15115#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
15116#define TIM_SR_CC4OF_Pos (12U)
15117#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
15118#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
15119#define TIM_SR_SBIF_Pos (13U)
15120#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
15121#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
15122#define TIM_SR_CC5IF_Pos (16U)
15123#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
15124#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
15125#define TIM_SR_CC6IF_Pos (17U)
15126#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
15127#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
15128
15129
15130/******************* Bit definition for TIM_EGR register ********************/
15131#define TIM_EGR_UG_Pos (0U)
15132#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
15133#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
15134#define TIM_EGR_CC1G_Pos (1U)
15135#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
15136#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
15137#define TIM_EGR_CC2G_Pos (2U)
15138#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
15139#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
15140#define TIM_EGR_CC3G_Pos (3U)
15141#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
15142#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
15143#define TIM_EGR_CC4G_Pos (4U)
15144#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
15145#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
15146#define TIM_EGR_COMG_Pos (5U)
15147#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
15148#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
15149#define TIM_EGR_TG_Pos (6U)
15150#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
15151#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
15152#define TIM_EGR_BG_Pos (7U)
15153#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
15154#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
15155#define TIM_EGR_B2G_Pos (8U)
15156#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
15157#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
15158
15159
15160/****************** Bit definition for TIM_CCMR1 register *******************/
15161#define TIM_CCMR1_CC1S_Pos (0U)
15162#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
15163#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
15164#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
15165#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
15166
15167#define TIM_CCMR1_OC1FE_Pos (2U)
15168#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
15169#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
15170#define TIM_CCMR1_OC1PE_Pos (3U)
15171#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
15172#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
15173
15174#define TIM_CCMR1_OC1M_Pos (4U)
15175#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
15176#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
15177#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
15178#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
15179#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
15180#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
15181
15182#define TIM_CCMR1_OC1CE_Pos (7U)
15183#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
15184#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
15185
15186#define TIM_CCMR1_CC2S_Pos (8U)
15187#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
15188#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
15189#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
15190#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
15191
15192#define TIM_CCMR1_OC2FE_Pos (10U)
15193#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
15194#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
15195#define TIM_CCMR1_OC2PE_Pos (11U)
15196#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
15197#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
15198
15199#define TIM_CCMR1_OC2M_Pos (12U)
15200#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
15201#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
15202#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
15203#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
15204#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
15205#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
15206
15207#define TIM_CCMR1_OC2CE_Pos (15U)
15208#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
15209#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
15210
15211/*----------------------------------------------------------------------------*/
15212#define TIM_CCMR1_IC1PSC_Pos (2U)
15213#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
15214#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
15215#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
15216#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
15217
15218#define TIM_CCMR1_IC1F_Pos (4U)
15219#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
15220#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
15221#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
15222#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
15223#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
15224#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
15225
15226#define TIM_CCMR1_IC2PSC_Pos (10U)
15227#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
15228#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
15229#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
15230#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
15231
15232#define TIM_CCMR1_IC2F_Pos (12U)
15233#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
15234#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
15235#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
15236#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
15237#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
15238#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
15239
15240/****************** Bit definition for TIM_CCMR2 register *******************/
15241#define TIM_CCMR2_CC3S_Pos (0U)
15242#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
15243#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
15244#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
15245#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
15246
15247#define TIM_CCMR2_OC3FE_Pos (2U)
15248#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
15249#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
15250#define TIM_CCMR2_OC3PE_Pos (3U)
15251#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
15252#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
15253
15254#define TIM_CCMR2_OC3M_Pos (4U)
15255#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
15256#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
15257#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
15258#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
15259#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
15260#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
15261
15262#define TIM_CCMR2_OC3CE_Pos (7U)
15263#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
15264#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
15265
15266#define TIM_CCMR2_CC4S_Pos (8U)
15267#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
15268#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
15269#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
15270#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
15271
15272#define TIM_CCMR2_OC4FE_Pos (10U)
15273#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
15274#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
15275#define TIM_CCMR2_OC4PE_Pos (11U)
15276#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
15277#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
15278
15279#define TIM_CCMR2_OC4M_Pos (12U)
15280#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
15281#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
15282#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
15283#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
15284#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
15285#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
15286
15287#define TIM_CCMR2_OC4CE_Pos (15U)
15288#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
15289#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
15290
15291/*----------------------------------------------------------------------------*/
15292#define TIM_CCMR2_IC3PSC_Pos (2U)
15293#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
15294#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
15295#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
15296#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
15297
15298#define TIM_CCMR2_IC3F_Pos (4U)
15299#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
15300#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
15301#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
15302#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
15303#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
15304#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
15305
15306#define TIM_CCMR2_IC4PSC_Pos (10U)
15307#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
15308#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
15309#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
15310#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
15311
15312#define TIM_CCMR2_IC4F_Pos (12U)
15313#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
15314#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
15315#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
15316#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
15317#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
15318#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
15319
15320/****************** Bit definition for TIM_CCMR3 register *******************/
15321#define TIM_CCMR3_OC5FE_Pos (2U)
15322#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
15323#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
15324#define TIM_CCMR3_OC5PE_Pos (3U)
15325#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
15326#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
15327
15328#define TIM_CCMR3_OC5M_Pos (4U)
15329#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
15330#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
15331#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
15332#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
15333#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
15334#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
15335
15336#define TIM_CCMR3_OC5CE_Pos (7U)
15337#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
15338#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
15339
15340#define TIM_CCMR3_OC6FE_Pos (10U)
15341#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
15342#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
15343#define TIM_CCMR3_OC6PE_Pos (11U)
15344#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
15345#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
15346
15347#define TIM_CCMR3_OC6M_Pos (12U)
15348#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
15349#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
15350#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
15351#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
15352#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
15353#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
15354
15355#define TIM_CCMR3_OC6CE_Pos (15U)
15356#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
15357#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
15358
15359/******************* Bit definition for TIM_CCER register *******************/
15360#define TIM_CCER_CC1E_Pos (0U)
15361#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
15362#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
15363#define TIM_CCER_CC1P_Pos (1U)
15364#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
15365#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
15366#define TIM_CCER_CC1NE_Pos (2U)
15367#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
15368#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
15369#define TIM_CCER_CC1NP_Pos (3U)
15370#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
15371#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
15372#define TIM_CCER_CC2E_Pos (4U)
15373#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
15374#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
15375#define TIM_CCER_CC2P_Pos (5U)
15376#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
15377#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
15378#define TIM_CCER_CC2NE_Pos (6U)
15379#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
15380#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
15381#define TIM_CCER_CC2NP_Pos (7U)
15382#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
15383#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
15384#define TIM_CCER_CC3E_Pos (8U)
15385#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
15386#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
15387#define TIM_CCER_CC3P_Pos (9U)
15388#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
15389#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
15390#define TIM_CCER_CC3NE_Pos (10U)
15391#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
15392#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
15393#define TIM_CCER_CC3NP_Pos (11U)
15394#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
15395#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
15396#define TIM_CCER_CC4E_Pos (12U)
15397#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
15398#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
15399#define TIM_CCER_CC4P_Pos (13U)
15400#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
15401#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
15402#define TIM_CCER_CC4NP_Pos (15U)
15403#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
15404#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
15405#define TIM_CCER_CC5E_Pos (16U)
15406#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
15407#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
15408#define TIM_CCER_CC5P_Pos (17U)
15409#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
15410#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
15411#define TIM_CCER_CC6E_Pos (20U)
15412#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
15413#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
15414#define TIM_CCER_CC6P_Pos (21U)
15415#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
15416#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
15417
15418/******************* Bit definition for TIM_CNT register ********************/
15419#define TIM_CNT_CNT_Pos (0U)
15420#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
15421#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
15422#define TIM_CNT_UIFCPY_Pos (31U)
15423#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
15424#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
15425
15426/******************* Bit definition for TIM_PSC register ********************/
15427#define TIM_PSC_PSC_Pos (0U)
15428#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
15429#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
15430
15431/******************* Bit definition for TIM_ARR register ********************/
15432#define TIM_ARR_ARR_Pos (0U)
15433#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
15434#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
15435
15436/******************* Bit definition for TIM_RCR register ********************/
15437#define TIM_RCR_REP_Pos (0U)
15438#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
15439#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
15440
15441/******************* Bit definition for TIM_CCR1 register *******************/
15442#define TIM_CCR1_CCR1_Pos (0U)
15443#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
15444#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
15445
15446/******************* Bit definition for TIM_CCR2 register *******************/
15447#define TIM_CCR2_CCR2_Pos (0U)
15448#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
15449#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
15450
15451/******************* Bit definition for TIM_CCR3 register *******************/
15452#define TIM_CCR3_CCR3_Pos (0U)
15453#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
15454#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
15455
15456/******************* Bit definition for TIM_CCR4 register *******************/
15457#define TIM_CCR4_CCR4_Pos (0U)
15458#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
15459#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
15460
15461/******************* Bit definition for TIM_CCR5 register *******************/
15462#define TIM_CCR5_CCR5_Pos (0U)
15463#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
15464#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
15465#define TIM_CCR5_GC5C1_Pos (29U)
15466#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
15467#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
15468#define TIM_CCR5_GC5C2_Pos (30U)
15469#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
15470#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
15471#define TIM_CCR5_GC5C3_Pos (31U)
15472#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
15473#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
15474
15475/******************* Bit definition for TIM_CCR6 register *******************/
15476#define TIM_CCR6_CCR6_Pos (0U)
15477#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
15478#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
15479
15480/******************* Bit definition for TIM_BDTR register *******************/
15481#define TIM_BDTR_DTG_Pos (0U)
15482#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
15483#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
15484#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
15485#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
15486#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
15487#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
15488#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
15489#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
15490#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
15491#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
15492
15493#define TIM_BDTR_LOCK_Pos (8U)
15494#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
15495#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
15496#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
15497#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
15498
15499#define TIM_BDTR_OSSI_Pos (10U)
15500#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
15501#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
15502#define TIM_BDTR_OSSR_Pos (11U)
15503#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
15504#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
15505#define TIM_BDTR_BKE_Pos (12U)
15506#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
15507#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
15508#define TIM_BDTR_BKP_Pos (13U)
15509#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
15510#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
15511#define TIM_BDTR_AOE_Pos (14U)
15512#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
15513#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
15514#define TIM_BDTR_MOE_Pos (15U)
15515#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
15516#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
15517
15518#define TIM_BDTR_BKF_Pos (16U)
15519#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
15520#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
15521#define TIM_BDTR_BK2F_Pos (20U)
15522#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
15523#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
15524
15525#define TIM_BDTR_BK2E_Pos (24U)
15526#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
15527#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
15528#define TIM_BDTR_BK2P_Pos (25U)
15529#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
15530#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
15531
15532#define TIM_BDTR_BKDSRM_Pos (26U)
15533#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
15534#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
15535#define TIM_BDTR_BK2DSRM_Pos (27U)
15536#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
15537#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
15538
15539#define TIM_BDTR_BKBID_Pos (28U)
15540#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
15541#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
15542#define TIM_BDTR_BK2BID_Pos (29U)
15543#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
15544#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
15545
15546/******************* Bit definition for TIM_DCR register ********************/
15547#define TIM_DCR_DBA_Pos (0U)
15548#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
15549#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
15550#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
15551#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
15552#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
15553#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
15554#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
15555
15556#define TIM_DCR_DBL_Pos (8U)
15557#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
15558#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
15559#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
15560#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
15561#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
15562#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
15563#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
15564
15565/******************* Bit definition for TIM_DMAR register *******************/
15566#define TIM_DMAR_DMAB_Pos (0U)
15567#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
15568#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
15569
15570/******************* Bit definition for TIM1_OR1 register *******************/
15571#define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
15572#define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
15573#define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
15574#define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
15575#define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
15576
15577#define TIM1_OR1_TI1_RMP_Pos (4U)
15578#define TIM1_OR1_TI1_RMP_Msk (0x1UL << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
15579#define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */
15580
15581/******************* Bit definition for TIM1_OR2 register *******************/
15582#define TIM1_OR2_BKINE_Pos (0U)
15583#define TIM1_OR2_BKINE_Msk (0x1UL << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */
15584#define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */
15585#define TIM1_OR2_BKCMP1E_Pos (1U)
15586#define TIM1_OR2_BKCMP1E_Msk (0x1UL << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
15587#define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
15588#define TIM1_OR2_BKCMP2E_Pos (2U)
15589#define TIM1_OR2_BKCMP2E_Msk (0x1UL << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
15590#define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
15591#define TIM1_OR2_BKDF1BK0E_Pos (8U)
15592#define TIM1_OR2_BKDF1BK0E_Msk (0x1UL << TIM1_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
15593#define TIM1_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
15594#define TIM1_OR2_BKINP_Pos (9U)
15595#define TIM1_OR2_BKINP_Msk (0x1UL << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */
15596#define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
15597#define TIM1_OR2_BKCMP1P_Pos (10U)
15598#define TIM1_OR2_BKCMP1P_Msk (0x1UL << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
15599#define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
15600#define TIM1_OR2_BKCMP2P_Pos (11U)
15601#define TIM1_OR2_BKCMP2P_Msk (0x1UL << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
15602#define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
15603
15604#define TIM1_OR2_ETRSEL_Pos (14U)
15605#define TIM1_OR2_ETRSEL_Msk (0x7UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
15606#define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
15607#define TIM1_OR2_ETRSEL_0 (0x1UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */
15608#define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */
15609#define TIM1_OR2_ETRSEL_2 (0x4UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */
15610
15611/******************* Bit definition for TIM1_OR3 register *******************/
15612#define TIM1_OR3_BK2INE_Pos (0U)
15613#define TIM1_OR3_BK2INE_Msk (0x1UL << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */
15614#define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
15615#define TIM1_OR3_BK2CMP1E_Pos (1U)
15616#define TIM1_OR3_BK2CMP1E_Msk (0x1UL << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
15617#define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
15618#define TIM1_OR3_BK2CMP2E_Pos (2U)
15619#define TIM1_OR3_BK2CMP2E_Msk (0x1UL << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
15620#define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
15621#define TIM1_OR3_BK2DF1BK1E_Pos (8U)
15622#define TIM1_OR3_BK2DF1BK1E_Msk (0x1UL << TIM1_OR3_BK2DF1BK1E_Pos) /*!< 0x00000100 */
15623#define TIM1_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E_Msk /*!<BRK2 DFSDM1_BREAK[1] enable */
15624#define TIM1_OR3_BK2INP_Pos (9U)
15625#define TIM1_OR3_BK2INP_Msk (0x1UL << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */
15626#define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
15627#define TIM1_OR3_BK2CMP1P_Pos (10U)
15628#define TIM1_OR3_BK2CMP1P_Msk (0x1UL << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
15629#define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
15630#define TIM1_OR3_BK2CMP2P_Pos (11U)
15631#define TIM1_OR3_BK2CMP2P_Msk (0x1UL << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
15632#define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
15633
15634/******************* Bit definition for TIM8_OR1 register *******************/
15635#define TIM8_OR1_TI1_RMP_Pos (4U)
15636#define TIM8_OR1_TI1_RMP_Msk (0x1UL << TIM8_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
15637#define TIM8_OR1_TI1_RMP TIM8_OR1_TI1_RMP_Msk /*!<TIM8 Input Capture 1 remap */
15638
15639/******************* Bit definition for TIM8_OR2 register *******************/
15640#define TIM8_OR2_BKINE_Pos (0U)
15641#define TIM8_OR2_BKINE_Msk (0x1UL << TIM8_OR2_BKINE_Pos) /*!< 0x00000001 */
15642#define TIM8_OR2_BKINE TIM8_OR2_BKINE_Msk /*!<BRK BKIN input enable */
15643#define TIM8_OR2_BKCMP1E_Pos (1U)
15644#define TIM8_OR2_BKCMP1E_Msk (0x1UL << TIM8_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
15645#define TIM8_OR2_BKCMP1E TIM8_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
15646#define TIM8_OR2_BKCMP2E_Pos (2U)
15647#define TIM8_OR2_BKCMP2E_Msk (0x1UL << TIM8_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
15648#define TIM8_OR2_BKCMP2E TIM8_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
15649#define TIM8_OR2_BKDF1BK2E_Pos (8U)
15650#define TIM8_OR2_BKDF1BK2E_Msk (0x1UL << TIM8_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
15651#define TIM8_OR2_BKDF1BK2E TIM8_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
15652#define TIM8_OR2_BKINP_Pos (9U)
15653#define TIM8_OR2_BKINP_Msk (0x1UL << TIM8_OR2_BKINP_Pos) /*!< 0x00000200 */
15654#define TIM8_OR2_BKINP TIM8_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
15655#define TIM8_OR2_BKCMP1P_Pos (10U)
15656#define TIM8_OR2_BKCMP1P_Msk (0x1UL << TIM8_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
15657#define TIM8_OR2_BKCMP1P TIM8_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
15658#define TIM8_OR2_BKCMP2P_Pos (11U)
15659#define TIM8_OR2_BKCMP2P_Msk (0x1UL << TIM8_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
15660#define TIM8_OR2_BKCMP2P TIM8_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
15661
15662#define TIM8_OR2_ETRSEL_Pos (14U)
15663#define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
15664#define TIM8_OR2_ETRSEL TIM8_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
15665#define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */
15666#define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */
15667#define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
15668
15669/******************* Bit definition for TIM8_OR3 register *******************/
15670#define TIM8_OR3_BK2INE_Pos (0U)
15671#define TIM8_OR3_BK2INE_Msk (0x1UL << TIM8_OR3_BK2INE_Pos) /*!< 0x00000001 */
15672#define TIM8_OR3_BK2INE TIM8_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
15673#define TIM8_OR3_BK2CMP1E_Pos (1U)
15674#define TIM8_OR3_BK2CMP1E_Msk (0x1UL << TIM8_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
15675#define TIM8_OR3_BK2CMP1E TIM8_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
15676#define TIM8_OR3_BK2CMP2E_Pos (2U)
15677#define TIM8_OR3_BK2CMP2E_Msk (0x1UL << TIM8_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
15678#define TIM8_OR3_BK2CMP2E TIM8_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
15679#define TIM8_OR3_BK2DF1BK3E_Pos (8U)
15680#define TIM8_OR3_BK2DF1BK3E_Msk (0x1UL << TIM8_OR3_BK2DF1BK3E_Pos) /*!< 0x00000100 */
15681#define TIM8_OR3_BK2DF1BK3E TIM8_OR3_BK2DF1BK3E_Msk /*!<BRK2 DFSDM1_BREAK[3] enable */
15682#define TIM8_OR3_BK2INP_Pos (9U)
15683#define TIM8_OR3_BK2INP_Msk (0x1UL << TIM8_OR3_BK2INP_Pos) /*!< 0x00000200 */
15684#define TIM8_OR3_BK2INP TIM8_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
15685#define TIM8_OR3_BK2CMP1P_Pos (10U)
15686#define TIM8_OR3_BK2CMP1P_Msk (0x1UL << TIM8_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
15687#define TIM8_OR3_BK2CMP1P TIM8_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
15688#define TIM8_OR3_BK2CMP2P_Pos (11U)
15689#define TIM8_OR3_BK2CMP2P_Msk (0x1UL << TIM8_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
15690#define TIM8_OR3_BK2CMP2P TIM8_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
15691
15692/******************* Bit definition for TIM2_OR1 register *******************/
15693#define TIM2_OR1_ITR1_RMP_Pos (0U)
15694#define TIM2_OR1_ITR1_RMP_Msk (0x1UL << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */
15695#define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
15696#define TIM2_OR1_ETR1_RMP_Pos (1U)
15697#define TIM2_OR1_ETR1_RMP_Msk (0x1UL << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */
15698#define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */
15699
15700#define TIM2_OR1_TI4_RMP_Pos (2U)
15701#define TIM2_OR1_TI4_RMP_Msk (0x3UL << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */
15702#define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
15703#define TIM2_OR1_TI4_RMP_0 (0x1UL << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */
15704#define TIM2_OR1_TI4_RMP_1 (0x2UL << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */
15705
15706/******************* Bit definition for TIM2_OR2 register *******************/
15707#define TIM2_OR2_ETRSEL_Pos (14U)
15708#define TIM2_OR2_ETRSEL_Msk (0x7UL << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
15709#define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
15710#define TIM2_OR2_ETRSEL_0 (0x1UL << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */
15711#define TIM2_OR2_ETRSEL_1 (0x2UL << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */
15712#define TIM2_OR2_ETRSEL_2 (0x4UL << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */
15713
15714/******************* Bit definition for TIM3_OR1 register *******************/
15715#define TIM3_OR1_TI1_RMP_Pos (0U)
15716#define TIM3_OR1_TI1_RMP_Msk (0x3UL << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
15717#define TIM3_OR1_TI1_RMP TIM3_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
15718#define TIM3_OR1_TI1_RMP_0 (0x1UL << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
15719#define TIM3_OR1_TI1_RMP_1 (0x2UL << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
15720
15721/******************* Bit definition for TIM3_OR2 register *******************/
15722#define TIM3_OR2_ETRSEL_Pos (14U)
15723#define TIM3_OR2_ETRSEL_Msk (0x7UL << TIM3_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
15724#define TIM3_OR2_ETRSEL TIM3_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
15725#define TIM3_OR2_ETRSEL_0 (0x1UL << TIM3_OR2_ETRSEL_Pos) /*!< 0x00004000 */
15726#define TIM3_OR2_ETRSEL_1 (0x2UL << TIM3_OR2_ETRSEL_Pos) /*!< 0x00008000 */
15727#define TIM3_OR2_ETRSEL_2 (0x4UL << TIM3_OR2_ETRSEL_Pos) /*!< 0x00010000 */
15728
15729/******************* Bit definition for TIM15_OR1 register ******************/
15730#define TIM15_OR1_TI1_RMP_Pos (0U)
15731#define TIM15_OR1_TI1_RMP_Msk (0x1UL << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
15732#define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */
15733
15734#define TIM15_OR1_ENCODER_MODE_Pos (1U)
15735#define TIM15_OR1_ENCODER_MODE_Msk (0x3UL << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */
15736#define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
15737#define TIM15_OR1_ENCODER_MODE_0 (0x1UL << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */
15738#define TIM15_OR1_ENCODER_MODE_1 (0x2UL << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */
15739
15740/******************* Bit definition for TIM15_OR2 register ******************/
15741#define TIM15_OR2_BKINE_Pos (0U)
15742#define TIM15_OR2_BKINE_Msk (0x1UL << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */
15743#define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */
15744#define TIM15_OR2_BKCMP1E_Pos (1U)
15745#define TIM15_OR2_BKCMP1E_Msk (0x1UL << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
15746#define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
15747#define TIM15_OR2_BKCMP2E_Pos (2U)
15748#define TIM15_OR2_BKCMP2E_Msk (0x1UL << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
15749#define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
15750#define TIM15_OR2_BKDF1BK0E_Pos (8U)
15751#define TIM15_OR2_BKDF1BK0E_Msk (0x1UL << TIM15_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
15752#define TIM15_OR2_BKDF1BK0E TIM15_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
15753#define TIM15_OR2_BKINP_Pos (9U)
15754#define TIM15_OR2_BKINP_Msk (0x1UL << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */
15755#define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
15756#define TIM15_OR2_BKCMP1P_Pos (10U)
15757#define TIM15_OR2_BKCMP1P_Msk (0x1UL << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
15758#define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
15759#define TIM15_OR2_BKCMP2P_Pos (11U)
15760#define TIM15_OR2_BKCMP2P_Msk (0x1UL << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
15761#define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
15762
15763/******************* Bit definition for TIM16_OR1 register ******************/
15764#define TIM16_OR1_TI1_RMP_Pos (0U)
15765#define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
15766#define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
15767#define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
15768#define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
15769
15770/******************* Bit definition for TIM16_OR2 register ******************/
15771#define TIM16_OR2_BKINE_Pos (0U)
15772#define TIM16_OR2_BKINE_Msk (0x1UL << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */
15773#define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */
15774#define TIM16_OR2_BKCMP1E_Pos (1U)
15775#define TIM16_OR2_BKCMP1E_Msk (0x1UL << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
15776#define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
15777#define TIM16_OR2_BKCMP2E_Pos (2U)
15778#define TIM16_OR2_BKCMP2E_Msk (0x1UL << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
15779#define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
15780#define TIM16_OR2_BKDF1BK1E_Pos (8U)
15781#define TIM16_OR2_BKDF1BK1E_Msk (0x1UL << TIM16_OR2_BKDF1BK1E_Pos) /*!< 0x00000100 */
15782#define TIM16_OR2_BKDF1BK1E TIM16_OR2_BKDF1BK1E_Msk /*!<BRK DFSDM1_BREAK[1] enable */
15783#define TIM16_OR2_BKINP_Pos (9U)
15784#define TIM16_OR2_BKINP_Msk (0x1UL << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */
15785#define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
15786#define TIM16_OR2_BKCMP1P_Pos (10U)
15787#define TIM16_OR2_BKCMP1P_Msk (0x1UL << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
15788#define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
15789#define TIM16_OR2_BKCMP2P_Pos (11U)
15790#define TIM16_OR2_BKCMP2P_Msk (0x1UL << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
15791#define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
15792
15793/******************* Bit definition for TIM17_OR1 register ******************/
15794#define TIM17_OR1_TI1_RMP_Pos (0U)
15795#define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
15796#define TIM17_OR1_TI1_RMP TIM17_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
15797#define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
15798#define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
15799
15800/******************* Bit definition for TIM17_OR2 register ******************/
15801#define TIM17_OR2_BKINE_Pos (0U)
15802#define TIM17_OR2_BKINE_Msk (0x1UL << TIM17_OR2_BKINE_Pos) /*!< 0x00000001 */
15803#define TIM17_OR2_BKINE TIM17_OR2_BKINE_Msk /*!<BRK BKIN input enable */
15804#define TIM17_OR2_BKCMP1E_Pos (1U)
15805#define TIM17_OR2_BKCMP1E_Msk (0x1UL << TIM17_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
15806#define TIM17_OR2_BKCMP1E TIM17_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
15807#define TIM17_OR2_BKCMP2E_Pos (2U)
15808#define TIM17_OR2_BKCMP2E_Msk (0x1UL << TIM17_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
15809#define TIM17_OR2_BKCMP2E TIM17_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
15810#define TIM17_OR2_BKDF1BK2E_Pos (8U)
15811#define TIM17_OR2_BKDF1BK2E_Msk (0x1UL << TIM17_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
15812#define TIM17_OR2_BKDF1BK2E TIM17_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
15813#define TIM17_OR2_BKINP_Pos (9U)
15814#define TIM17_OR2_BKINP_Msk (0x1UL << TIM17_OR2_BKINP_Pos) /*!< 0x00000200 */
15815#define TIM17_OR2_BKINP TIM17_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
15816#define TIM17_OR2_BKCMP1P_Pos (10U)
15817#define TIM17_OR2_BKCMP1P_Msk (0x1UL << TIM17_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
15818#define TIM17_OR2_BKCMP1P TIM17_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
15819#define TIM17_OR2_BKCMP2P_Pos (11U)
15820#define TIM17_OR2_BKCMP2P_Msk (0x1UL << TIM17_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
15821#define TIM17_OR2_BKCMP2P TIM17_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
15822
15823/******************************************************************************/
15824/* */
15825/* Touch Sensing Controller (TSC) */
15826/* */
15827/******************************************************************************/
15828/******************* Bit definition for TSC_CR register *********************/
15829#define TSC_CR_TSCE_Pos (0U)
15830#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
15831#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
15832#define TSC_CR_START_Pos (1U)
15833#define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos) /*!< 0x00000002 */
15834#define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
15835#define TSC_CR_AM_Pos (2U)
15836#define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos) /*!< 0x00000004 */
15837#define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
15838#define TSC_CR_SYNCPOL_Pos (3U)
15839#define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
15840#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
15841#define TSC_CR_IODEF_Pos (4U)
15842#define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
15843#define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
15844
15845#define TSC_CR_MCV_Pos (5U)
15846#define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
15847#define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
15848#define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos) /*!< 0x00000020 */
15849#define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos) /*!< 0x00000040 */
15850#define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos) /*!< 0x00000080 */
15851
15852#define TSC_CR_PGPSC_Pos (12U)
15853#define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
15854#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
15855#define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
15856#define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
15857#define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
15858
15859#define TSC_CR_SSPSC_Pos (15U)
15860#define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
15861#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
15862#define TSC_CR_SSE_Pos (16U)
15863#define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos) /*!< 0x00010000 */
15864#define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
15865
15866#define TSC_CR_SSD_Pos (17U)
15867#define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
15868#define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
15869#define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos) /*!< 0x00020000 */
15870#define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos) /*!< 0x00040000 */
15871#define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos) /*!< 0x00080000 */
15872#define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos) /*!< 0x00100000 */
15873#define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos) /*!< 0x00200000 */
15874#define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos) /*!< 0x00400000 */
15875#define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos) /*!< 0x00800000 */
15876
15877#define TSC_CR_CTPL_Pos (24U)
15878#define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
15879#define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
15880#define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
15881#define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
15882#define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
15883#define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
15884
15885#define TSC_CR_CTPH_Pos (28U)
15886#define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
15887#define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
15888#define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
15889#define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
15890#define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
15891#define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
15892
15893/******************* Bit definition for TSC_IER register ********************/
15894#define TSC_IER_EOAIE_Pos (0U)
15895#define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
15896#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
15897#define TSC_IER_MCEIE_Pos (1U)
15898#define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
15899#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
15900
15901/******************* Bit definition for TSC_ICR register ********************/
15902#define TSC_ICR_EOAIC_Pos (0U)
15903#define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
15904#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
15905#define TSC_ICR_MCEIC_Pos (1U)
15906#define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
15907#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
15908
15909/******************* Bit definition for TSC_ISR register ********************/
15910#define TSC_ISR_EOAF_Pos (0U)
15911#define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
15912#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
15913#define TSC_ISR_MCEF_Pos (1U)
15914#define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
15915#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
15916
15917/******************* Bit definition for TSC_IOHCR register ******************/
15918#define TSC_IOHCR_G1_IO1_Pos (0U)
15919#define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
15920#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
15921#define TSC_IOHCR_G1_IO2_Pos (1U)
15922#define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
15923#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
15924#define TSC_IOHCR_G1_IO3_Pos (2U)
15925#define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
15926#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
15927#define TSC_IOHCR_G1_IO4_Pos (3U)
15928#define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
15929#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
15930#define TSC_IOHCR_G2_IO1_Pos (4U)
15931#define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
15932#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
15933#define TSC_IOHCR_G2_IO2_Pos (5U)
15934#define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
15935#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
15936#define TSC_IOHCR_G2_IO3_Pos (6U)
15937#define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
15938#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
15939#define TSC_IOHCR_G2_IO4_Pos (7U)
15940#define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
15941#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
15942#define TSC_IOHCR_G3_IO1_Pos (8U)
15943#define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
15944#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
15945#define TSC_IOHCR_G3_IO2_Pos (9U)
15946#define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
15947#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
15948#define TSC_IOHCR_G3_IO3_Pos (10U)
15949#define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
15950#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
15951#define TSC_IOHCR_G3_IO4_Pos (11U)
15952#define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
15953#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
15954#define TSC_IOHCR_G4_IO1_Pos (12U)
15955#define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
15956#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
15957#define TSC_IOHCR_G4_IO2_Pos (13U)
15958#define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
15959#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
15960#define TSC_IOHCR_G4_IO3_Pos (14U)
15961#define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
15962#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
15963#define TSC_IOHCR_G4_IO4_Pos (15U)
15964#define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
15965#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
15966#define TSC_IOHCR_G5_IO1_Pos (16U)
15967#define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
15968#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
15969#define TSC_IOHCR_G5_IO2_Pos (17U)
15970#define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
15971#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
15972#define TSC_IOHCR_G5_IO3_Pos (18U)
15973#define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
15974#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
15975#define TSC_IOHCR_G5_IO4_Pos (19U)
15976#define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
15977#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
15978#define TSC_IOHCR_G6_IO1_Pos (20U)
15979#define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
15980#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
15981#define TSC_IOHCR_G6_IO2_Pos (21U)
15982#define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
15983#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
15984#define TSC_IOHCR_G6_IO3_Pos (22U)
15985#define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
15986#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
15987#define TSC_IOHCR_G6_IO4_Pos (23U)
15988#define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
15989#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
15990#define TSC_IOHCR_G7_IO1_Pos (24U)
15991#define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
15992#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
15993#define TSC_IOHCR_G7_IO2_Pos (25U)
15994#define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
15995#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
15996#define TSC_IOHCR_G7_IO3_Pos (26U)
15997#define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
15998#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
15999#define TSC_IOHCR_G7_IO4_Pos (27U)
16000#define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
16001#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
16002#define TSC_IOHCR_G8_IO1_Pos (28U)
16003#define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
16004#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
16005#define TSC_IOHCR_G8_IO2_Pos (29U)
16006#define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
16007#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
16008#define TSC_IOHCR_G8_IO3_Pos (30U)
16009#define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
16010#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
16011#define TSC_IOHCR_G8_IO4_Pos (31U)
16012#define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
16013#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
16014
16015/******************* Bit definition for TSC_IOASCR register *****************/
16016#define TSC_IOASCR_G1_IO1_Pos (0U)
16017#define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
16018#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
16019#define TSC_IOASCR_G1_IO2_Pos (1U)
16020#define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
16021#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
16022#define TSC_IOASCR_G1_IO3_Pos (2U)
16023#define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
16024#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
16025#define TSC_IOASCR_G1_IO4_Pos (3U)
16026#define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
16027#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
16028#define TSC_IOASCR_G2_IO1_Pos (4U)
16029#define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
16030#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
16031#define TSC_IOASCR_G2_IO2_Pos (5U)
16032#define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
16033#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
16034#define TSC_IOASCR_G2_IO3_Pos (6U)
16035#define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
16036#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
16037#define TSC_IOASCR_G2_IO4_Pos (7U)
16038#define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
16039#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
16040#define TSC_IOASCR_G3_IO1_Pos (8U)
16041#define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
16042#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
16043#define TSC_IOASCR_G3_IO2_Pos (9U)
16044#define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
16045#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
16046#define TSC_IOASCR_G3_IO3_Pos (10U)
16047#define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
16048#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
16049#define TSC_IOASCR_G3_IO4_Pos (11U)
16050#define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
16051#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
16052#define TSC_IOASCR_G4_IO1_Pos (12U)
16053#define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
16054#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
16055#define TSC_IOASCR_G4_IO2_Pos (13U)
16056#define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
16057#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
16058#define TSC_IOASCR_G4_IO3_Pos (14U)
16059#define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
16060#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
16061#define TSC_IOASCR_G4_IO4_Pos (15U)
16062#define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
16063#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
16064#define TSC_IOASCR_G5_IO1_Pos (16U)
16065#define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
16066#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
16067#define TSC_IOASCR_G5_IO2_Pos (17U)
16068#define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
16069#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
16070#define TSC_IOASCR_G5_IO3_Pos (18U)
16071#define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
16072#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
16073#define TSC_IOASCR_G5_IO4_Pos (19U)
16074#define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
16075#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
16076#define TSC_IOASCR_G6_IO1_Pos (20U)
16077#define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
16078#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
16079#define TSC_IOASCR_G6_IO2_Pos (21U)
16080#define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
16081#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
16082#define TSC_IOASCR_G6_IO3_Pos (22U)
16083#define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
16084#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
16085#define TSC_IOASCR_G6_IO4_Pos (23U)
16086#define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
16087#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
16088#define TSC_IOASCR_G7_IO1_Pos (24U)
16089#define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
16090#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
16091#define TSC_IOASCR_G7_IO2_Pos (25U)
16092#define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
16093#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
16094#define TSC_IOASCR_G7_IO3_Pos (26U)
16095#define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
16096#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
16097#define TSC_IOASCR_G7_IO4_Pos (27U)
16098#define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
16099#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
16100#define TSC_IOASCR_G8_IO1_Pos (28U)
16101#define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
16102#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
16103#define TSC_IOASCR_G8_IO2_Pos (29U)
16104#define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
16105#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
16106#define TSC_IOASCR_G8_IO3_Pos (30U)
16107#define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
16108#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
16109#define TSC_IOASCR_G8_IO4_Pos (31U)
16110#define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
16111#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
16112
16113/******************* Bit definition for TSC_IOSCR register ******************/
16114#define TSC_IOSCR_G1_IO1_Pos (0U)
16115#define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
16116#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
16117#define TSC_IOSCR_G1_IO2_Pos (1U)
16118#define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
16119#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
16120#define TSC_IOSCR_G1_IO3_Pos (2U)
16121#define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
16122#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
16123#define TSC_IOSCR_G1_IO4_Pos (3U)
16124#define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
16125#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
16126#define TSC_IOSCR_G2_IO1_Pos (4U)
16127#define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
16128#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
16129#define TSC_IOSCR_G2_IO2_Pos (5U)
16130#define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
16131#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
16132#define TSC_IOSCR_G2_IO3_Pos (6U)
16133#define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
16134#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
16135#define TSC_IOSCR_G2_IO4_Pos (7U)
16136#define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
16137#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
16138#define TSC_IOSCR_G3_IO1_Pos (8U)
16139#define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
16140#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
16141#define TSC_IOSCR_G3_IO2_Pos (9U)
16142#define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
16143#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
16144#define TSC_IOSCR_G3_IO3_Pos (10U)
16145#define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
16146#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
16147#define TSC_IOSCR_G3_IO4_Pos (11U)
16148#define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
16149#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
16150#define TSC_IOSCR_G4_IO1_Pos (12U)
16151#define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
16152#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
16153#define TSC_IOSCR_G4_IO2_Pos (13U)
16154#define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
16155#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
16156#define TSC_IOSCR_G4_IO3_Pos (14U)
16157#define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
16158#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
16159#define TSC_IOSCR_G4_IO4_Pos (15U)
16160#define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
16161#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
16162#define TSC_IOSCR_G5_IO1_Pos (16U)
16163#define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
16164#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
16165#define TSC_IOSCR_G5_IO2_Pos (17U)
16166#define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
16167#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
16168#define TSC_IOSCR_G5_IO3_Pos (18U)
16169#define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
16170#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
16171#define TSC_IOSCR_G5_IO4_Pos (19U)
16172#define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
16173#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
16174#define TSC_IOSCR_G6_IO1_Pos (20U)
16175#define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
16176#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
16177#define TSC_IOSCR_G6_IO2_Pos (21U)
16178#define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
16179#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
16180#define TSC_IOSCR_G6_IO3_Pos (22U)
16181#define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
16182#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
16183#define TSC_IOSCR_G6_IO4_Pos (23U)
16184#define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
16185#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
16186#define TSC_IOSCR_G7_IO1_Pos (24U)
16187#define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
16188#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
16189#define TSC_IOSCR_G7_IO2_Pos (25U)
16190#define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
16191#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
16192#define TSC_IOSCR_G7_IO3_Pos (26U)
16193#define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
16194#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
16195#define TSC_IOSCR_G7_IO4_Pos (27U)
16196#define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
16197#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
16198#define TSC_IOSCR_G8_IO1_Pos (28U)
16199#define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
16200#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
16201#define TSC_IOSCR_G8_IO2_Pos (29U)
16202#define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
16203#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
16204#define TSC_IOSCR_G8_IO3_Pos (30U)
16205#define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
16206#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
16207#define TSC_IOSCR_G8_IO4_Pos (31U)
16208#define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
16209#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
16210
16211/******************* Bit definition for TSC_IOCCR register ******************/
16212#define TSC_IOCCR_G1_IO1_Pos (0U)
16213#define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
16214#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
16215#define TSC_IOCCR_G1_IO2_Pos (1U)
16216#define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
16217#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
16218#define TSC_IOCCR_G1_IO3_Pos (2U)
16219#define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
16220#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
16221#define TSC_IOCCR_G1_IO4_Pos (3U)
16222#define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
16223#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
16224#define TSC_IOCCR_G2_IO1_Pos (4U)
16225#define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
16226#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
16227#define TSC_IOCCR_G2_IO2_Pos (5U)
16228#define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
16229#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
16230#define TSC_IOCCR_G2_IO3_Pos (6U)
16231#define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
16232#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
16233#define TSC_IOCCR_G2_IO4_Pos (7U)
16234#define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
16235#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
16236#define TSC_IOCCR_G3_IO1_Pos (8U)
16237#define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
16238#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
16239#define TSC_IOCCR_G3_IO2_Pos (9U)
16240#define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
16241#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
16242#define TSC_IOCCR_G3_IO3_Pos (10U)
16243#define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
16244#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
16245#define TSC_IOCCR_G3_IO4_Pos (11U)
16246#define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
16247#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
16248#define TSC_IOCCR_G4_IO1_Pos (12U)
16249#define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
16250#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
16251#define TSC_IOCCR_G4_IO2_Pos (13U)
16252#define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
16253#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
16254#define TSC_IOCCR_G4_IO3_Pos (14U)
16255#define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
16256#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
16257#define TSC_IOCCR_G4_IO4_Pos (15U)
16258#define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
16259#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
16260#define TSC_IOCCR_G5_IO1_Pos (16U)
16261#define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
16262#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
16263#define TSC_IOCCR_G5_IO2_Pos (17U)
16264#define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
16265#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
16266#define TSC_IOCCR_G5_IO3_Pos (18U)
16267#define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
16268#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
16269#define TSC_IOCCR_G5_IO4_Pos (19U)
16270#define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
16271#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
16272#define TSC_IOCCR_G6_IO1_Pos (20U)
16273#define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
16274#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
16275#define TSC_IOCCR_G6_IO2_Pos (21U)
16276#define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
16277#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
16278#define TSC_IOCCR_G6_IO3_Pos (22U)
16279#define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
16280#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
16281#define TSC_IOCCR_G6_IO4_Pos (23U)
16282#define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
16283#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
16284#define TSC_IOCCR_G7_IO1_Pos (24U)
16285#define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
16286#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
16287#define TSC_IOCCR_G7_IO2_Pos (25U)
16288#define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
16289#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
16290#define TSC_IOCCR_G7_IO3_Pos (26U)
16291#define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
16292#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
16293#define TSC_IOCCR_G7_IO4_Pos (27U)
16294#define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
16295#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
16296#define TSC_IOCCR_G8_IO1_Pos (28U)
16297#define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
16298#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
16299#define TSC_IOCCR_G8_IO2_Pos (29U)
16300#define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
16301#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
16302#define TSC_IOCCR_G8_IO3_Pos (30U)
16303#define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
16304#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
16305#define TSC_IOCCR_G8_IO4_Pos (31U)
16306#define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
16307#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
16308
16309/******************* Bit definition for TSC_IOGCSR register *****************/
16310#define TSC_IOGCSR_G1E_Pos (0U)
16311#define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
16312#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
16313#define TSC_IOGCSR_G2E_Pos (1U)
16314#define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
16315#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
16316#define TSC_IOGCSR_G3E_Pos (2U)
16317#define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
16318#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
16319#define TSC_IOGCSR_G4E_Pos (3U)
16320#define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
16321#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
16322#define TSC_IOGCSR_G5E_Pos (4U)
16323#define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
16324#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
16325#define TSC_IOGCSR_G6E_Pos (5U)
16326#define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
16327#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
16328#define TSC_IOGCSR_G7E_Pos (6U)
16329#define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
16330#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
16331#define TSC_IOGCSR_G8E_Pos (7U)
16332#define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
16333#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
16334#define TSC_IOGCSR_G1S_Pos (16U)
16335#define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
16336#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
16337#define TSC_IOGCSR_G2S_Pos (17U)
16338#define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
16339#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
16340#define TSC_IOGCSR_G3S_Pos (18U)
16341#define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
16342#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
16343#define TSC_IOGCSR_G4S_Pos (19U)
16344#define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
16345#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
16346#define TSC_IOGCSR_G5S_Pos (20U)
16347#define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
16348#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
16349#define TSC_IOGCSR_G6S_Pos (21U)
16350#define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
16351#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
16352#define TSC_IOGCSR_G7S_Pos (22U)
16353#define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
16354#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
16355#define TSC_IOGCSR_G8S_Pos (23U)
16356#define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
16357#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
16358
16359/******************* Bit definition for TSC_IOGXCR register *****************/
16360#define TSC_IOGXCR_CNT_Pos (0U)
16361#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
16362#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
16363
16364/******************************************************************************/
16365/* */
16366/* Serial Audio Interface */
16367/* */
16368/******************************************************************************/
16369/******************** Bit definition for SAI_GCR register *******************/
16370#define SAI_GCR_SYNCIN_Pos (0U)
16371#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
16372#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
16373#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
16374#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
16375
16376#define SAI_GCR_SYNCOUT_Pos (4U)
16377#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
16378#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
16379#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
16380#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
16381
16382/******************* Bit definition for SAI_xCR1 register *******************/
16383#define SAI_xCR1_MODE_Pos (0U)
16384#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
16385#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
16386#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
16387#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
16388
16389#define SAI_xCR1_PRTCFG_Pos (2U)
16390#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
16391#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
16392#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
16393#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
16394
16395#define SAI_xCR1_DS_Pos (5U)
16396#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
16397#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
16398#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
16399#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
16400#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
16401
16402#define SAI_xCR1_LSBFIRST_Pos (8U)
16403#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
16404#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
16405#define SAI_xCR1_CKSTR_Pos (9U)
16406#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
16407#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
16408
16409#define SAI_xCR1_SYNCEN_Pos (10U)
16410#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
16411#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
16412#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
16413#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
16414
16415#define SAI_xCR1_MONO_Pos (12U)
16416#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
16417#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
16418#define SAI_xCR1_OUTDRIV_Pos (13U)
16419#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
16420#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
16421#define SAI_xCR1_SAIEN_Pos (16U)
16422#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
16423#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
16424#define SAI_xCR1_DMAEN_Pos (17U)
16425#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
16426#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
16427#define SAI_xCR1_NODIV_Pos (19U)
16428#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
16429#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
16430
16431#define SAI_xCR1_MCKDIV_Pos (20U)
16432#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
16433#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
16434#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
16435#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
16436#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
16437#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
16438#define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x01000000 */
16439#define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x02000000 */
16440
16441#define SAI_xCR1_OSR_Pos (26U)
16442#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
16443#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */
16444
16445#define SAI_xCR1_MCKEN_Pos (27U)
16446#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
16447#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master clock generation enable */
16448
16449/******************* Bit definition for SAI_xCR2 register *******************/
16450#define SAI_xCR2_FTH_Pos (0U)
16451#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
16452#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
16453#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
16454#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
16455#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
16456
16457#define SAI_xCR2_FFLUSH_Pos (3U)
16458#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
16459#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
16460#define SAI_xCR2_TRIS_Pos (4U)
16461#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
16462#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
16463#define SAI_xCR2_MUTE_Pos (5U)
16464#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
16465#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
16466#define SAI_xCR2_MUTEVAL_Pos (6U)
16467#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
16468#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
16469
16470
16471#define SAI_xCR2_MUTECNT_Pos (7U)
16472#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
16473#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
16474#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
16475#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
16476#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
16477#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
16478#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
16479#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
16480
16481#define SAI_xCR2_CPL_Pos (13U)
16482#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
16483#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
16484#define SAI_xCR2_COMP_Pos (14U)
16485#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
16486#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
16487#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
16488#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
16489
16490
16491/****************** Bit definition for SAI_xFRCR register *******************/
16492#define SAI_xFRCR_FRL_Pos (0U)
16493#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
16494#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
16495#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
16496#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
16497#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
16498#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
16499#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
16500#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
16501#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
16502#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
16503
16504#define SAI_xFRCR_FSALL_Pos (8U)
16505#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
16506#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
16507#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
16508#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
16509#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
16510#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
16511#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
16512#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
16513#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
16514
16515#define SAI_xFRCR_FSDEF_Pos (16U)
16516#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
16517#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
16518#define SAI_xFRCR_FSPOL_Pos (17U)
16519#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
16520#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
16521#define SAI_xFRCR_FSOFF_Pos (18U)
16522#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
16523#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
16524
16525/****************** Bit definition for SAI_xSLOTR register *******************/
16526#define SAI_xSLOTR_FBOFF_Pos (0U)
16527#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
16528#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
16529#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
16530#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
16531#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
16532#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
16533#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
16534
16535#define SAI_xSLOTR_SLOTSZ_Pos (6U)
16536#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
16537#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
16538#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
16539#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
16540
16541#define SAI_xSLOTR_NBSLOT_Pos (8U)
16542#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
16543#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
16544#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
16545#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
16546#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
16547#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
16548
16549#define SAI_xSLOTR_SLOTEN_Pos (16U)
16550#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
16551#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
16552
16553/******************* Bit definition for SAI_xIMR register *******************/
16554#define SAI_xIMR_OVRUDRIE_Pos (0U)
16555#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
16556#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
16557#define SAI_xIMR_MUTEDETIE_Pos (1U)
16558#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
16559#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
16560#define SAI_xIMR_WCKCFGIE_Pos (2U)
16561#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
16562#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
16563#define SAI_xIMR_FREQIE_Pos (3U)
16564#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
16565#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
16566#define SAI_xIMR_CNRDYIE_Pos (4U)
16567#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
16568#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
16569#define SAI_xIMR_AFSDETIE_Pos (5U)
16570#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
16571#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
16572#define SAI_xIMR_LFSDETIE_Pos (6U)
16573#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
16574#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
16575
16576/******************** Bit definition for SAI_xSR register *******************/
16577#define SAI_xSR_OVRUDR_Pos (0U)
16578#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
16579#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
16580#define SAI_xSR_MUTEDET_Pos (1U)
16581#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
16582#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
16583#define SAI_xSR_WCKCFG_Pos (2U)
16584#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
16585#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
16586#define SAI_xSR_FREQ_Pos (3U)
16587#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
16588#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
16589#define SAI_xSR_CNRDY_Pos (4U)
16590#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
16591#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
16592#define SAI_xSR_AFSDET_Pos (5U)
16593#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
16594#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
16595#define SAI_xSR_LFSDET_Pos (6U)
16596#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
16597#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
16598
16599#define SAI_xSR_FLVL_Pos (16U)
16600#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
16601#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
16602#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
16603#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
16604#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
16605
16606/****************** Bit definition for SAI_xCLRFR register ******************/
16607#define SAI_xCLRFR_COVRUDR_Pos (0U)
16608#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
16609#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
16610#define SAI_xCLRFR_CMUTEDET_Pos (1U)
16611#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
16612#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
16613#define SAI_xCLRFR_CWCKCFG_Pos (2U)
16614#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
16615#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
16616#define SAI_xCLRFR_CFREQ_Pos (3U)
16617#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
16618#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
16619#define SAI_xCLRFR_CCNRDY_Pos (4U)
16620#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
16621#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
16622#define SAI_xCLRFR_CAFSDET_Pos (5U)
16623#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
16624#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
16625#define SAI_xCLRFR_CLFSDET_Pos (6U)
16626#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
16627#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
16628
16629/****************** Bit definition for SAI_xDR register ******************/
16630#define SAI_xDR_DATA_Pos (0U)
16631#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
16632#define SAI_xDR_DATA SAI_xDR_DATA_Msk
16633
16634/****************** Bit definition for SAI_PDMCR register *******************/
16635#define SAI_PDMCR_PDMEN_Pos (0U)
16636#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
16637#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */
16638
16639#define SAI_PDMCR_MICNBR_Pos (4U)
16640#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
16641#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */
16642#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
16643#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
16644
16645#define SAI_PDMCR_CKEN1_Pos (8U)
16646#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
16647#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */
16648#define SAI_PDMCR_CKEN2_Pos (9U)
16649#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
16650#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */
16651#define SAI_PDMCR_CKEN3_Pos (10U)
16652#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
16653#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */
16654#define SAI_PDMCR_CKEN4_Pos (11U)
16655#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
16656#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */
16657
16658/****************** Bit definition for SAI_PDMDLY register ******************/
16659#define SAI_PDMDLY_DLYM1L_Pos (0U)
16660#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
16661#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
16662#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
16663#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
16664#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
16665
16666#define SAI_PDMDLY_DLYM1R_Pos (4U)
16667#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
16668#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
16669#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
16670#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
16671#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
16672
16673#define SAI_PDMDLY_DLYM2L_Pos (8U)
16674#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
16675#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
16676#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
16677#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
16678#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
16679
16680#define SAI_PDMDLY_DLYM2R_Pos (12U)
16681#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
16682#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
16683#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
16684#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
16685#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
16686
16687#define SAI_PDMDLY_DLYM3L_Pos (16U)
16688#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
16689#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
16690#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
16691#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
16692#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
16693
16694#define SAI_PDMDLY_DLYM3R_Pos (20U)
16695#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
16696#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
16697#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
16698#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
16699#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
16700
16701#define SAI_PDMDLY_DLYM4L_Pos (24U)
16702#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
16703#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
16704#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
16705#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
16706#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
16707
16708#define SAI_PDMDLY_DLYM4R_Pos (28U)
16709#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
16710#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
16711#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
16712#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
16713#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
16714
16715/******************************************************************************/
16716/* */
16717/* SYSCFG */
16718/* */
16719/******************************************************************************/
16720/****************** Bit definition for SYSCFG_SECCFGR register **************/
16721#define SYSCFG_SECCFGR_SYSCFGSEC_Pos (0U)
16722#define SYSCFG_SECCFGR_SYSCFGSEC_Msk (0x1UL << SYSCFG_SECCFGR_SYSCFGSEC_Pos) /*!< 0x00000001 */
16723#define SYSCFG_SECCFGR_SYSCFGSEC SYSCFG_SECCFGR_SYSCFGSEC_Msk /*!< SYSCFG clock control security enable */
16724#define SYSCFG_SECCFGR_CLASSBSEC_Pos (1U)
16725#define SYSCFG_SECCFGR_CLASSBSEC_Msk (0x1UL << SYSCFG_SECCFGR_CLASSBSEC_Pos) /*!< 0x00000002 */
16726#define SYSCFG_SECCFGR_CLASSBSEC SYSCFG_SECCFGR_CLASSBSEC_Msk /*!< ClassB SYSCFG security enable */
16727#define SYSCFG_SECCFGR_SRAM2SEC_Pos (2U)
16728#define SYSCFG_SECCFGR_SRAM2SEC_Msk (0x1UL << SYSCFG_SECCFGR_SRAM2SEC_Pos) /*!< 0x00000004 */
16729#define SYSCFG_SECCFGR_SRAM2SEC SYSCFG_SECCFGR_SRAM2SEC_Msk /*!< SRAM2 SYSCFG security enable */
16730#define SYSCFG_SECCFGR_FPUSEC_Pos (3U)
16731#define SYSCFG_SECCFGR_FPUSEC_Msk (0x1UL << SYSCFG_SECCFGR_FPUSEC_Pos) /*!< 0x00000008 */
16732#define SYSCFG_SECCFGR_FPUSEC SYSCFG_SECCFGR_FPUSEC_Msk /*!< FPU SYSCFG security enable */
16733
16734/****************** Bit definition for SYSCFG_CFGR1 register ****************/
16735#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
16736#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
16737#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
16738#define SYSCFG_CFGR1_ANASWVDD_Pos (9U)
16739#define SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos) /*!< 0x00000200 */
16740#define SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk /*!< GPIO analog switch control voltage selection enable */
16741#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
16742#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
16743#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
16744#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
16745#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
16746#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
16747#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
16748#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
16749#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
16750#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
16751#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
16752#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
16753#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
16754#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
16755#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
16756#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
16757#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
16758#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
16759#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
16760#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
16761#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
16762#define SYSCFG_CFGR1_I2C4_FMP_Pos (23U)
16763#define SYSCFG_CFGR1_I2C4_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C4_FMP_Pos) /*!< 0x00800000 */
16764#define SYSCFG_CFGR1_I2C4_FMP SYSCFG_CFGR1_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
16765
16766/****************** Bit definition for SYSCFG_FPUIMR register ***************/
16767#define SYSCFG_FPUIMR_FPU_IE_Pos (0U)
16768#define SYSCFG_FPUIMR_FPU_IE_Msk (0x3FUL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F */
16769#define SYSCFG_FPUIMR_FPU_IE SYSCFG_FPUIMR_FPU_IE_Msk /*!< All FPU interrupts enable */
16770#define SYSCFG_FPUIMR_FPU_IE_0_Pos (0U)
16771#define SYSCFG_FPUIMR_FPU_IE_0_Msk (0x1UL << SYSCFG_FPUIMR_FPU_IE_0_Pos) /*!< 0x00000001 */
16772#define SYSCFG_FPUIMR_FPU_IE_0 SYSCFG_FPUIMR_FPU_IE_0_Msk /*!< Invalid operation Interrupt enable */
16773#define SYSCFG_FPUIMR_FPU_IE_1_Pos (1U)
16774#define SYSCFG_FPUIMR_FPU_IE_1_Msk (0x1UL << SYSCFG_FPUIMR_FPU_IE_1_Pos) /*!< 0x00000002 */
16775#define SYSCFG_FPUIMR_FPU_IE_1 SYSCFG_FPUIMR_FPU_IE_1_Msk /*!< Divide-by-zero Interrupt enable */
16776#define SYSCFG_FPUIMR_FPU_IE_2_Pos (2U)
16777#define SYSCFG_FPUIMR_FPU_IE_2_Msk (0x1UL << SYSCFG_FPUIMR_FPU_IE_2_Pos) /*!< 0x00000004 */
16778#define SYSCFG_FPUIMR_FPU_IE_2 SYSCFG_FPUIMR_FPU_IE_2_Msk /*!< Underflow Interrupt enable */
16779#define SYSCFG_FPUIMR_FPU_IE_3_Pos (3U)
16780#define SYSCFG_FPUIMR_FPU_IE_3_Msk (0x1UL << SYSCFG_FPUIMR_FPU_IE_3_Pos) /*!< 0x00000008 */
16781#define SYSCFG_FPUIMR_FPU_IE_3 SYSCFG_FPUIMR_FPU_IE_3_Msk /*!< Overflow Interrupt enable */
16782#define SYSCFG_FPUIMR_FPU_IE_4_Pos (4U)
16783#define SYSCFG_FPUIMR_FPU_IE_4_Msk (0x1UL << SYSCFG_FPUIMR_FPU_IE_4_Pos) /*!< 0x00000010 */
16784#define SYSCFG_FPUIMR_FPU_IE_4 SYSCFG_FPUIMR_FPU_IE_4_Msk /*!< Input denormal Interrupt enable */
16785#define SYSCFG_FPUIMR_FPU_IE_5_Pos (5U)
16786#define SYSCFG_FPUIMR_FPU_IE_5_Msk (0x1UL << SYSCFG_FPUIMR_FPU_IE_5_Pos) /*!< 0x00000020 */
16787#define SYSCFG_FPUIMR_FPU_IE_5 SYSCFG_FPUIMR_FPU_IE_5_Msk /*!< Inexact Interrupt enable */
16788
16789/****************** Bit definition for SYSCFG_CNSLCKR register **************/
16790#define SYSCFG_CNSLCKR_LOCKNSVTOR_Pos (0U)
16791#define SYSCFG_CNSLCKR_LOCKNSVTOR_Msk (0x1UL << SYSCFG_CNSLCKR_LOCKNSVTOR_Pos)/*!< 0x00000001 */
16792#define SYSCFG_CNSLCKR_LOCKNSVTOR SYSCFG_CNSLCKR_LOCKNSVTOR_Msk /*!< Disable VTOR_NS register writes by SW or debug agent */
16793#define SYSCFG_CNSLCKR_LOCKNSMPU_Pos (1U)
16794#define SYSCFG_CNSLCKR_LOCKNSMPU_Msk (0x1UL << SYSCFG_CNSLCKR_LOCKNSMPU_Pos)/*!< 0x00000002 */
16795#define SYSCFG_CNSLCKR_LOCKNSMPU SYSCFG_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Secure MPU registers writes by SW or debug agent */
16796
16797/****************** Bit definition for SYSCFG_CSLCKR register ***************/
16798#define SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos (0U)
16799#define SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos)/*!< 0x00000001 */
16800#define SYSCFG_CSLCKR_LOCKSVTAIRCR SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vectror table address, handling of system faults */
16801#define SYSCFG_CSLCKR_LOCKSMPU_Pos (1U)
16802#define SYSCFG_CSLCKR_LOCKSMPU_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSMPU_Pos) /*!< 0x00000002 */
16803#define SYSCFG_CSLCKR_LOCKSMPU SYSCFG_CSLCKR_LOCKSMPU_Msk /*!< Disable changes to the secure MPU registers writes by SW or debug agent */
16804#define SYSCFG_CSLCKR_LOCKSAU_Pos (2U)
16805#define SYSCFG_CSLCKR_LOCKSAU_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSAU_Pos) /*!< 0x00000002 */
16806#define SYSCFG_CSLCKR_LOCKSAU SYSCFG_CSLCKR_LOCKSAU_Msk /*!< Disable changes to SAU registers */
16807
16808/****************** Bit definition for SYSCFG_CFGR2 register ****************/
16809#define SYSCFG_CFGR2_CLL_Pos (0U)
16810#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
16811#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
16812#define SYSCFG_CFGR2_SPL_Pos (1U)
16813#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
16814#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
16815#define SYSCFG_CFGR2_PVDL_Pos (2U)
16816#define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
16817#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
16818#define SYSCFG_CFGR2_ECCL_Pos (3U)
16819#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
16820#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
16821#define SYSCFG_CFGR2_SPF_Pos (8U)
16822#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
16823#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
16824
16825/****************** Bit definition for SYSCFG_SCSR register *****************/
16826#define SYSCFG_SCSR_SRAM2ER_Pos (0U)
16827#define SYSCFG_SCSR_SRAM2ER_Msk (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */
16828#define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */
16829#define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
16830#define SYSCFG_SCSR_SRAM2BSY_Msk (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */
16831#define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */
16832
16833/****************** Bit definition for SYSCFG_SKR register *****************/
16834#define SYSCFG_SKR_KEY_Pos (0U)
16835#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
16836#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */
16837
16838/****************** Bit definition for SYSCFG_SWPR register *****************/
16839#define SYSCFG_SWPR_P0WP_Pos (0U)
16840#define SYSCFG_SWPR_P0WP_Msk (0x1UL << SYSCFG_SWPR_P0WP_Pos) /*!< 0x00000001 */
16841#define SYSCFG_SWPR_P0WP SYSCFG_SWPR_P0WP_Msk /*!< SRAM2 Write protection page 0 */
16842#define SYSCFG_SWPR_P1WP_Pos (1U)
16843#define SYSCFG_SWPR_P1WP_Msk (0x1UL << SYSCFG_SWPR_P1WP_Pos) /*!< 0x00000002 */
16844#define SYSCFG_SWPR_P1WP SYSCFG_SWPR_P1WP_Msk /*!< SRAM2 Write protection page 1 */
16845#define SYSCFG_SWPR_P2WP_Pos (2U)
16846#define SYSCFG_SWPR_P2WP_Msk (0x1UL << SYSCFG_SWPR_P2WP_Pos) /*!< 0x00000004 */
16847#define SYSCFG_SWPR_P2WP SYSCFG_SWPR_P2WP_Msk /*!< SRAM2 Write protection page 2 */
16848#define SYSCFG_SWPR_P3WP_Pos (3U)
16849#define SYSCFG_SWPR_P3WP_Msk (0x1UL << SYSCFG_SWPR_P3WP_Pos) /*!< 0x00000008 */
16850#define SYSCFG_SWPR_P3WP SYSCFG_SWPR_P3WP_Msk /*!< SRAM2 Write protection page 3 */
16851#define SYSCFG_SWPR_P4WP_Pos (4U)
16852#define SYSCFG_SWPR_P4WP_Msk (0x1UL << SYSCFG_SWPR_P4WP_Pos) /*!< 0x00000010 */
16853#define SYSCFG_SWPR_P4WP SYSCFG_SWPR_P4WP_Msk /*!< SRAM2 Write protection page 4 */
16854#define SYSCFG_SWPR_P5WP_Pos (5U)
16855#define SYSCFG_SWPR_P5WP_Msk (0x1UL << SYSCFG_SWPR_P5WP_Pos) /*!< 0x00000020 */
16856#define SYSCFG_SWPR_P5WP SYSCFG_SWPR_P5WP_Msk /*!< SRAM2 Write protection page 5 */
16857#define SYSCFG_SWPR_P6WP_Pos (6U)
16858#define SYSCFG_SWPR_P6WP_Msk (0x1UL << SYSCFG_SWPR_P6WP_Pos) /*!< 0x00000040 */
16859#define SYSCFG_SWPR_P6WP SYSCFG_SWPR_P6WP_Msk /*!< SRAM2 Write protection page 6 */
16860#define SYSCFG_SWPR_P7WP_Pos (7U)
16861#define SYSCFG_SWPR_P7WP_Msk (0x1UL << SYSCFG_SWPR_P7WP_Pos) /*!< 0x00000080 */
16862#define SYSCFG_SWPR_P7WP SYSCFG_SWPR_P7WP_Msk /*!< SRAM2 Write protection page 7 */
16863#define SYSCFG_SWPR_P8WP_Pos (8U)
16864#define SYSCFG_SWPR_P8WP_Msk (0x1UL << SYSCFG_SWPR_P8WP_Pos) /*!< 0x00000100 */
16865#define SYSCFG_SWPR_P8WP SYSCFG_SWPR_P8WP_Msk /*!< SRAM2 Write protection page 8 */
16866#define SYSCFG_SWPR_P9WP_Pos (9U)
16867#define SYSCFG_SWPR_P9WP_Msk (0x1UL << SYSCFG_SWPR_P9WP_Pos) /*!< 0x00000200 */
16868#define SYSCFG_SWPR_P9WP SYSCFG_SWPR_P9WP_Msk /*!< SRAM2 Write protection page 9 */
16869#define SYSCFG_SWPR_P10WP_Pos (10U)
16870#define SYSCFG_SWPR_P10WP_Msk (0x1UL << SYSCFG_SWPR_P10WP_Pos) /*!< 0x00000400 */
16871#define SYSCFG_SWPR_P10WP SYSCFG_SWPR_P10WP_Msk /*!< SRAM2 Write protection page 10*/
16872#define SYSCFG_SWPR_P11WP_Pos (11U)
16873#define SYSCFG_SWPR_P11WP_Msk (0x1UL << SYSCFG_SWPR_P11WP_Pos) /*!< 0x00000800 */
16874#define SYSCFG_SWPR_P11WP SYSCFG_SWPR_P11WP_Msk /*!< SRAM2 Write protection page 11*/
16875#define SYSCFG_SWPR_P12WP_Pos (12U)
16876#define SYSCFG_SWPR_P12WP_Msk (0x1UL << SYSCFG_SWPR_P12WP_Pos) /*!< 0x00001000 */
16877#define SYSCFG_SWPR_P12WP SYSCFG_SWPR_P12WP_Msk /*!< SRAM2 Write protection page 12*/
16878#define SYSCFG_SWPR_P13WP_Pos (13U)
16879#define SYSCFG_SWPR_P13WP_Msk (0x1UL << SYSCFG_SWPR_P13WP_Pos) /*!< 0x00002000 */
16880#define SYSCFG_SWPR_P13WP SYSCFG_SWPR_P13WP_Msk /*!< SRAM2 Write protection page 13*/
16881#define SYSCFG_SWPR_P14WP_Pos (14U)
16882#define SYSCFG_SWPR_P14WP_Msk (0x1UL << SYSCFG_SWPR_P14WP_Pos) /*!< 0x00004000 */
16883#define SYSCFG_SWPR_P14WP SYSCFG_SWPR_P14WP_Msk /*!< SRAM2 Write protection page 14*/
16884#define SYSCFG_SWPR_P15WP_Pos (15U)
16885#define SYSCFG_SWPR_P15WP_Msk (0x1UL << SYSCFG_SWPR_P15WP_Pos) /*!< 0x00008000 */
16886#define SYSCFG_SWPR_P15WP SYSCFG_SWPR_P15WP_Msk /*!< SRAM2 Write protection page 15*/
16887#define SYSCFG_SWPR_P16WP_Pos (16U)
16888#define SYSCFG_SWPR_P16WP_Msk (0x1UL << SYSCFG_SWPR_P16WP_Pos) /*!< 0x00010000 */
16889#define SYSCFG_SWPR_P16WP SYSCFG_SWPR_P16WP_Msk /*!< SRAM2 Write protection page 16*/
16890#define SYSCFG_SWPR_P17WP_Pos (17U)
16891#define SYSCFG_SWPR_P17WP_Msk (0x1UL << SYSCFG_SWPR_P17WP_Pos) /*!< 0x00020000 */
16892#define SYSCFG_SWPR_P17WP SYSCFG_SWPR_P17WP_Msk /*!< SRAM2 Write protection page 17*/
16893#define SYSCFG_SWPR_P18WP_Pos (18U)
16894#define SYSCFG_SWPR_P18WP_Msk (0x1UL << SYSCFG_SWPR_P18WP_Pos) /*!< 0x00040000 */
16895#define SYSCFG_SWPR_P18WP SYSCFG_SWPR_P18WP_Msk /*!< SRAM2 Write protection page 18*/
16896#define SYSCFG_SWPR_P19WP_Pos (19U)
16897#define SYSCFG_SWPR_P19WP_Msk (0x1UL << SYSCFG_SWPR_P19WP_Pos) /*!< 0x00080000 */
16898#define SYSCFG_SWPR_P19WP SYSCFG_SWPR_P19WP_Msk /*!< SRAM2 Write protection page 19*/
16899#define SYSCFG_SWPR_P20WP_Pos (20U)
16900#define SYSCFG_SWPR_P20WP_Msk (0x1UL << SYSCFG_SWPR_P20WP_Pos) /*!< 0x00100000 */
16901#define SYSCFG_SWPR_P20WP SYSCFG_SWPR_P20WP_Msk /*!< SRAM2 Write protection page 20*/
16902#define SYSCFG_SWPR_P21WP_Pos (21U)
16903#define SYSCFG_SWPR_P21WP_Msk (0x1UL << SYSCFG_SWPR_P21WP_Pos) /*!< 0x00200000 */
16904#define SYSCFG_SWPR_P21WP SYSCFG_SWPR_P21WP_Msk /*!< SRAM2 Write protection page 21*/
16905#define SYSCFG_SWPR_P22WP_Pos (22U)
16906#define SYSCFG_SWPR_P22WP_Msk (0x1UL << SYSCFG_SWPR_P22WP_Pos) /*!< 0x00400000 */
16907#define SYSCFG_SWPR_P22WP SYSCFG_SWPR_P22WP_Msk /*!< SRAM2 Write protection page 22*/
16908#define SYSCFG_SWPR_P23WP_Pos (23U)
16909#define SYSCFG_SWPR_P23WP_Msk (0x1UL << SYSCFG_SWPR_P23WP_Pos) /*!< 0x00800000 */
16910#define SYSCFG_SWPR_P23WP SYSCFG_SWPR_P23WP_Msk /*!< SRAM2 Write protection page 23*/
16911#define SYSCFG_SWPR_P24WP_Pos (24U)
16912#define SYSCFG_SWPR_P24WP_Msk (0x1UL << SYSCFG_SWPR_P24WP_Pos) /*!< 0x01000000 */
16913#define SYSCFG_SWPR_P24WP SYSCFG_SWPR_P24WP_Msk /*!< SRAM2 Write protection page 24*/
16914#define SYSCFG_SWPR_P25WP_Pos (25U)
16915#define SYSCFG_SWPR_P25WP_Msk (0x1UL << SYSCFG_SWPR_P25WP_Pos) /*!< 0x02000000 */
16916#define SYSCFG_SWPR_P25WP SYSCFG_SWPR_P25WP_Msk /*!< SRAM2 Write protection page 25*/
16917#define SYSCFG_SWPR_P26WP_Pos (26U)
16918#define SYSCFG_SWPR_P26WP_Msk (0x1UL << SYSCFG_SWPR_P26WP_Pos) /*!< 0x04000000 */
16919#define SYSCFG_SWPR_P26WP SYSCFG_SWPR_P26WP_Msk /*!< SRAM2 Write protection page 26*/
16920#define SYSCFG_SWPR_P27WP_Pos (27U)
16921#define SYSCFG_SWPR_P27WP_Msk (0x1UL << SYSCFG_SWPR_P27WP_Pos) /*!< 0x08000000 */
16922#define SYSCFG_SWPR_P27WP SYSCFG_SWPR_P27WP_Msk /*!< SRAM2 Write protection page 27*/
16923#define SYSCFG_SWPR_P28WP_Pos (28U)
16924#define SYSCFG_SWPR_P28WP_Msk (0x1UL << SYSCFG_SWPR_P28WP_Pos) /*!< 0x10000000 */
16925#define SYSCFG_SWPR_P28WP SYSCFG_SWPR_P28WP_Msk /*!< SRAM2 Write protection page 28*/
16926#define SYSCFG_SWPR_P29WP_Pos (29U)
16927#define SYSCFG_SWPR_P29WP_Msk (0x1UL << SYSCFG_SWPR_P29WP_Pos) /*!< 0x20000000 */
16928#define SYSCFG_SWPR_P29WP SYSCFG_SWPR_P29WP_Msk /*!< SRAM2 Write protection page 29*/
16929#define SYSCFG_SWPR_P30WP_Pos (30U)
16930#define SYSCFG_SWPR_P30WP_Msk (0x1UL << SYSCFG_SWPR_P30WP_Pos) /*!< 0x40000000 */
16931#define SYSCFG_SWPR_P30WP SYSCFG_SWPR_P30WP_Msk /*!< SRAM2 Write protection page 30*/
16932#define SYSCFG_SWPR_P31WP_Pos (31U)
16933#define SYSCFG_SWPR_P31WP_Msk (0x1UL << SYSCFG_SWPR_P31WP_Pos) /*!< 0x80000000 */
16934#define SYSCFG_SWPR_P31WP SYSCFG_SWPR_P31WP_Msk /*!< SRAM2 Write protection page 31*/
16935
16936/****************** Bit definition for SYSCFG_SWPR2 register ****************/
16937#define SYSCFG_SWPR2_P32WP_Pos (0U)
16938#define SYSCFG_SWPR2_P32WP_Msk (0x1UL << SYSCFG_SWPR2_P32WP_Pos) /*!< 0x00000001 */
16939#define SYSCFG_SWPR2_P32WP SYSCFG_SWPR2_P32WP_Msk /*!< SRAM2 Write protection page 32*/
16940#define SYSCFG_SWPR2_P33WP_Pos (1U)
16941#define SYSCFG_SWPR2_P33WP_Msk (0x1UL << SYSCFG_SWPR2_P33WP_Pos) /*!< 0x00000002 */
16942#define SYSCFG_SWPR2_P33WP SYSCFG_SWPR2_P33WP_Msk /*!< SRAM2 Write protection page 33*/
16943#define SYSCFG_SWPR2_P34WP_Pos (2U)
16944#define SYSCFG_SWPR2_P34WP_Msk (0x1UL << SYSCFG_SWPR2_P34WP_Pos) /*!< 0x00000004 */
16945#define SYSCFG_SWPR2_P34WP SYSCFG_SWPR2_P34WP_Msk /*!< SRAM2 Write protection page 34*/
16946#define SYSCFG_SWPR2_P35WP_Pos (3U)
16947#define SYSCFG_SWPR2_P35WP_Msk (0x1UL << SYSCFG_SWPR2_P35WP_Pos) /*!< 0x00000008 */
16948#define SYSCFG_SWPR2_P35WP SYSCFG_SWPR2_P35WP_Msk /*!< SRAM2 Write protection page 35*/
16949#define SYSCFG_SWPR2_P36WP_Pos (4U)
16950#define SYSCFG_SWPR2_P36WP_Msk (0x1UL << SYSCFG_SWPR2_P36WP_Pos) /*!< 0x00000010 */
16951#define SYSCFG_SWPR2_P36WP SYSCFG_SWPR2_P36WP_Msk /*!< SRAM2 Write protection page 36*/
16952#define SYSCFG_SWPR2_P37WP_Pos (5U)
16953#define SYSCFG_SWPR2_P37WP_Msk (0x1UL << SYSCFG_SWPR2_P37WP_Pos) /*!< 0x00000020 */
16954#define SYSCFG_SWPR2_P37WP SYSCFG_SWPR2_P37WP_Msk /*!< SRAM2 Write protection page 37*/
16955#define SYSCFG_SWPR2_P38WP_Pos (6U)
16956#define SYSCFG_SWPR2_P38WP_Msk (0x1UL << SYSCFG_SWPR2_P38WP_Pos) /*!< 0x00000040 */
16957#define SYSCFG_SWPR2_P38WP SYSCFG_SWPR2_P38WP_Msk /*!< SRAM2 Write protection page 38*/
16958#define SYSCFG_SWPR2_P39WP_Pos (7U)
16959#define SYSCFG_SWPR2_P39WP_Msk (0x1UL << SYSCFG_SWPR2_P39WP_Pos) /*!< 0x00000080 */
16960#define SYSCFG_SWPR2_P39WP SYSCFG_SWPR2_P39WP_Msk /*!< SRAM2 Write protection page 39*/
16961#define SYSCFG_SWPR2_P40WP_Pos (8U)
16962#define SYSCFG_SWPR2_P40WP_Msk (0x1UL << SYSCFG_SWPR2_P40WP_Pos) /*!< 0x00000100 */
16963#define SYSCFG_SWPR2_P40WP SYSCFG_SWPR2_P40WP_Msk /*!< SRAM2 Write protection page 40*/
16964#define SYSCFG_SWPR2_P41WP_Pos (9U)
16965#define SYSCFG_SWPR2_P41WP_Msk (0x1UL << SYSCFG_SWPR2_P41WP_Pos) /*!< 0x00000200 */
16966#define SYSCFG_SWPR2_P41WP SYSCFG_SWPR2_P41WP_Msk /*!< SRAM2 Write protection page 41*/
16967#define SYSCFG_SWPR2_P42WP_Pos (10U)
16968#define SYSCFG_SWPR2_P42WP_Msk (0x1UL << SYSCFG_SWPR2_P42WP_Pos) /*!< 0x00000400 */
16969#define SYSCFG_SWPR2_P42WP SYSCFG_SWPR2_P42WP_Msk /*!< SRAM2 Write protection page 42*/
16970#define SYSCFG_SWPR2_P43WP_Pos (11U)
16971#define SYSCFG_SWPR2_P43WP_Msk (0x1UL << SYSCFG_SWPR2_P43WP_Pos) /*!< 0x00000800 */
16972#define SYSCFG_SWPR2_P43WP SYSCFG_SWPR2_P43WP_Msk /*!< SRAM2 Write protection page 43*/
16973#define SYSCFG_SWPR2_P44WP_Pos (12U)
16974#define SYSCFG_SWPR2_P44WP_Msk (0x1UL << SYSCFG_SWPR2_P44WP_Pos) /*!< 0x00001000 */
16975#define SYSCFG_SWPR2_P44WP SYSCFG_SWPR2_P44WP_Msk /*!< SRAM2 Write protection page 44*/
16976#define SYSCFG_SWPR2_P45WP_Pos (13U)
16977#define SYSCFG_SWPR2_P45WP_Msk (0x1UL << SYSCFG_SWPR2_P45WP_Pos) /*!< 0x00002000 */
16978#define SYSCFG_SWPR2_P45WP SYSCFG_SWPR2_P45WP_Msk /*!< SRAM2 Write protection page 45*/
16979#define SYSCFG_SWPR2_P46WP_Pos (14U)
16980#define SYSCFG_SWPR2_P46WP_Msk (0x1UL << SYSCFG_SWPR2_P46WP_Pos) /*!< 0x00004000 */
16981#define SYSCFG_SWPR2_P46WP SYSCFG_SWPR2_P46WP_Msk /*!< SRAM2 Write protection page 46*/
16982#define SYSCFG_SWPR2_P47WP_Pos (15U)
16983#define SYSCFG_SWPR2_P47WP_Msk (0x1UL << SYSCFG_SWPR2_P47WP_Pos) /*!< 0x00008000 */
16984#define SYSCFG_SWPR2_P47WP SYSCFG_SWPR2_P47WP_Msk /*!< SRAM2 Write protection page 47*/
16985#define SYSCFG_SWPR2_P48WP_Pos (16U)
16986#define SYSCFG_SWPR2_P48WP_Msk (0x1UL << SYSCFG_SWPR2_P48WP_Pos) /*!< 0x00010000 */
16987#define SYSCFG_SWPR2_P48WP SYSCFG_SWPR2_P48WP_Msk /*!< SRAM2 Write protection page 48*/
16988#define SYSCFG_SWPR2_P49WP_Pos (17U)
16989#define SYSCFG_SWPR2_P49WP_Msk (0x1UL << SYSCFG_SWPR2_P49WP_Pos) /*!< 0x00020000 */
16990#define SYSCFG_SWPR2_P49WP SYSCFG_SWPR2_P49WP_Msk /*!< SRAM2 Write protection page 49*/
16991#define SYSCFG_SWPR2_P50WP_Pos (18U)
16992#define SYSCFG_SWPR2_P50WP_Msk (0x1UL << SYSCFG_SWPR2_P50WP_Pos) /*!< 0x00040000 */
16993#define SYSCFG_SWPR2_P50WP SYSCFG_SWPR2_P50WP_Msk /*!< SRAM2 Write protection page 50*/
16994#define SYSCFG_SWPR2_P51WP_Pos (19U)
16995#define SYSCFG_SWPR2_P51WP_Msk (0x1UL << SYSCFG_SWPR2_P51WP_Pos) /*!< 0x00080000 */
16996#define SYSCFG_SWPR2_P51WP SYSCFG_SWPR2_P51WP_Msk /*!< SRAM2 Write protection page 51*/
16997#define SYSCFG_SWPR2_P52WP_Pos (20U)
16998#define SYSCFG_SWPR2_P52WP_Msk (0x1UL << SYSCFG_SWPR2_P52WP_Pos) /*!< 0x00100000 */
16999#define SYSCFG_SWPR2_P52WP SYSCFG_SWPR2_P52WP_Msk /*!< SRAM2 Write protection page 52*/
17000#define SYSCFG_SWPR2_P53WP_Pos (21U)
17001#define SYSCFG_SWPR2_P53WP_Msk (0x1UL << SYSCFG_SWPR2_P53WP_Pos) /*!< 0x00200000 */
17002#define SYSCFG_SWPR2_P53WP SYSCFG_SWPR2_P53WP_Msk /*!< SRAM2 Write protection page 53*/
17003#define SYSCFG_SWPR2_P54WP_Pos (22U)
17004#define SYSCFG_SWPR2_P54WP_Msk (0x1UL << SYSCFG_SWPR2_P54WP_Pos) /*!< 0x00400000 */
17005#define SYSCFG_SWPR2_P54WP SYSCFG_SWPR2_P54WP_Msk /*!< SRAM2 Write protection page 54*/
17006#define SYSCFG_SWPR2_P55WP_Pos (23U)
17007#define SYSCFG_SWPR2_P55WP_Msk (0x1UL << SYSCFG_SWPR2_P55WP_Pos) /*!< 0x00800000 */
17008#define SYSCFG_SWPR2_P55WP SYSCFG_SWPR2_P55WP_Msk /*!< SRAM2 Write protection page 55*/
17009#define SYSCFG_SWPR2_P56WP_Pos (24U)
17010#define SYSCFG_SWPR2_P56WP_Msk (0x1UL << SYSCFG_SWPR2_P56WP_Pos) /*!< 0x01000000 */
17011#define SYSCFG_SWPR2_P56WP SYSCFG_SWPR2_P56WP_Msk /*!< SRAM2 Write protection page 56*/
17012#define SYSCFG_SWPR2_P57WP_Pos (25U)
17013#define SYSCFG_SWPR2_P57WP_Msk (0x1UL << SYSCFG_SWPR2_P57WP_Pos) /*!< 0x02000000 */
17014#define SYSCFG_SWPR2_P57WP SYSCFG_SWPR2_P57WP_Msk /*!< SRAM2 Write protection page 57*/
17015#define SYSCFG_SWPR2_P58WP_Pos (26U)
17016#define SYSCFG_SWPR2_P58WP_Msk (0x1UL << SYSCFG_SWPR2_P58WP_Pos) /*!< 0x04000000 */
17017#define SYSCFG_SWPR2_P58WP SYSCFG_SWPR2_P58WP_Msk /*!< SRAM2 Write protection page 58*/
17018#define SYSCFG_SWPR2_P59WP_Pos (27U)
17019#define SYSCFG_SWPR2_P59WP_Msk (0x1UL << SYSCFG_SWPR2_P59WP_Pos) /*!< 0x08000000 */
17020#define SYSCFG_SWPR2_P59WP SYSCFG_SWPR2_P59WP_Msk /*!< SRAM2 Write protection page 59*/
17021#define SYSCFG_SWPR2_P60WP_Pos (28U)
17022#define SYSCFG_SWPR2_P60WP_Msk (0x1UL << SYSCFG_SWPR2_P60WP_Pos) /*!< 0x10000000 */
17023#define SYSCFG_SWPR2_P60WP SYSCFG_SWPR2_P60WP_Msk /*!< SRAM2 Write protection page 60*/
17024#define SYSCFG_SWPR2_P61WP_Pos (29U)
17025#define SYSCFG_SWPR2_P61WP_Msk (0x1UL << SYSCFG_SWPR2_P61WP_Pos) /*!< 0x20000000 */
17026#define SYSCFG_SWPR2_P61WP SYSCFG_SWPR2_P61WP_Msk /*!< SRAM2 Write protection page 61*/
17027#define SYSCFG_SWPR2_P62WP_Pos (30U)
17028#define SYSCFG_SWPR2_P62WP_Msk (0x1UL << SYSCFG_SWPR2_P62WP_Pos) /*!< 0x40000000 */
17029#define SYSCFG_SWPR2_P62WP SYSCFG_SWPR2_P62WP_Msk /*!< SRAM2 Write protection page 62*/
17030#define SYSCFG_SWPR2_P63WP_Pos (31U)
17031#define SYSCFG_SWPR2_P63WP_Msk (0x1UL << SYSCFG_SWPR2_P63WP_Pos) /*!< 0x80000000 */
17032#define SYSCFG_SWPR2_P63WP SYSCFG_SWPR2_P63WP_Msk /*!< SRAM2 Write protection page 63*/
17033
17034/****************** Bit definition for SYSCFG_RSSCMDR register **************/
17035#define SYSCFG_RSSCMDR_RSSCMD_Pos (0U)
17036#if defined(USE_CUT2_0)
17037#define SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */
17038#else
17039#define SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x000000FF */
17040#endif
17041#define SYSCFG_RSSCMDR_RSSCMD SYSCFG_RSSCMDR_RSSCMD_Msk /*!< RSS commands */
17042
17043/*****************************************************************************/
17044/* */
17045/* Global TrustZone Control */
17046/* */
17047/*****************************************************************************/
17048/******************* Bits definition for GTZC_TZSC_CR register ******************/
17049#define GTZC_TZSC_CR_LCK_Pos (0U)
17050#define GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) /*!< 0x00000001 */
17051
17052/******************* Bits definition for GTZC_TZSC_MPCWM1_NSWMR1 register *******/
17053#define GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Pos (0U)
17054#define GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Msk (0x7FFUL << GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Pos)
17055#define GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Pos (16U)
17056#define GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Pos)
17057
17058/******************* Bits definition for GTZC_TZSC_MPCWM1_NSWMR2 register *******/
17059#define GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Pos (0U)
17060#define GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Msk (0x7FFUL << GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Pos)
17061#define GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Pos (16U)
17062#define GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Pos)
17063
17064/******************* Bits definition for GTZC_TZSC_MPCWM2_NSWMR1 register *******/
17065#define GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Pos (0U)
17066#define GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Msk (0x7FFUL << GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Pos)
17067#define GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Pos (16U)
17068#define GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Pos)
17069
17070/******************* Bits definition for GTZC_TZSC_MPCWM2_NSWMR2 register *******/
17071#define GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Pos (0U)
17072#define GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Msk (0x7FFUL << GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Pos)
17073#define GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Pos (16U)
17074#define GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Pos)
17075
17076/******************* Bits definition for GTZC_TZSC_MPCWM3_NSWMR1 register *******/
17077#define GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Pos (0U)
17078#define GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Msk (0x7FFUL << GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Pos)
17079#define GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Pos (16U)
17080#define GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Pos)
17081
17082/******* Bits definition for GTZC_TZSC_SECCFGRx/_PRIVCFGRx registers *****/
17083/******* Bits definition for GTZC_TZIC_IERx/_SRx/_IFCRx registers ********/
17084
17085/******************* Bits definition for registers x=1 ***************/
17086#define GTZC_CFGR1_SPI1_Pos (31U)
17087#define GTZC_CFGR1_SPI1_Msk ( 0x01UL << GTZC_CFGR1_SPI1_Pos )
17088#define GTZC_CFGR1_TIM1_Pos (30U)
17089#define GTZC_CFGR1_TIM1_Msk ( 0x01UL << GTZC_CFGR1_TIM1_Pos )
17090#define GTZC_CFGR1_COMP_Pos (29U)
17091#define GTZC_CFGR1_COMP_Msk ( 0x01UL << GTZC_CFGR1_COMP_Pos )
17092#define GTZC_CFGR1_VREFBUF_Pos (28U)
17093#define GTZC_CFGR1_VREFBUF_Msk ( 0x01UL << GTZC_CFGR1_VREFBUF_Pos )
17094#define GTZC_CFGR1_UCPD1_Pos (27U)
17095#define GTZC_CFGR1_UCPD1_Msk ( 0x01UL << GTZC_CFGR1_UCPD1_Pos )
17096#define GTZC_CFGR1_USBFS_Pos (26U)
17097#define GTZC_CFGR1_USBFS_Msk ( 0x01UL << GTZC_CFGR1_USBFS_Pos )
17098#define GTZC_CFGR1_FDCAN1_Pos (25U)
17099#define GTZC_CFGR1_FDCAN1_Msk ( 0x01UL << GTZC_CFGR1_FDCAN1_Pos )
17100#define GTZC_CFGR1_LPTIM3_Pos (24U)
17101#define GTZC_CFGR1_LPTIM3_Msk ( 0x01UL << GTZC_CFGR1_LPTIM3_Pos )
17102#define GTZC_CFGR1_LPTIM2_Pos (23U)
17103#define GTZC_CFGR1_LPTIM2_Msk ( 0x01UL << GTZC_CFGR1_LPTIM2_Pos )
17104#define GTZC_CFGR1_I2C4_Pos (22U)
17105#define GTZC_CFGR1_I2C4_Msk ( 0x01UL << GTZC_CFGR1_I2C4_Pos )
17106#define GTZC_CFGR1_LPUART1_Pos (21U)
17107#define GTZC_CFGR1_LPUART1_Msk ( 0x01UL << GTZC_CFGR1_LPUART1_Pos )
17108#define GTZC_CFGR1_LPTIM1_Pos (20U)
17109#define GTZC_CFGR1_LPTIM1_Msk ( 0x01UL << GTZC_CFGR1_LPTIM1_Pos )
17110#define GTZC_CFGR1_OPAMP_Pos (19U)
17111#define GTZC_CFGR1_OPAMP_Msk ( 0x01UL << GTZC_CFGR1_OPAMP_Pos )
17112#define GTZC_CFGR1_DAC1_Pos (18U)
17113#define GTZC_CFGR1_DAC1_Msk ( 0x01UL << GTZC_CFGR1_DAC1_Pos )
17114#define GTZC_CFGR1_CRS_Pos (17U)
17115#define GTZC_CFGR1_CRS_Msk ( 0x01UL << GTZC_CFGR1_CRS_Pos )
17116#define GTZC_CFGR1_I2C3_Pos (16U)
17117#define GTZC_CFGR1_I2C3_Msk ( 0x01UL << GTZC_CFGR1_I2C3_Pos )
17118#define GTZC_CFGR1_I2C2_Pos (15U)
17119#define GTZC_CFGR1_I2C2_Msk ( 0x01UL << GTZC_CFGR1_I2C2_Pos )
17120#define GTZC_CFGR1_I2C1_Pos (14U)
17121#define GTZC_CFGR1_I2C1_Msk ( 0x01UL << GTZC_CFGR1_I2C1_Pos )
17122#define GTZC_CFGR1_UART5_Pos (13U)
17123#define GTZC_CFGR1_UART5_Msk ( 0x01UL << GTZC_CFGR1_UART5_Pos )
17124#define GTZC_CFGR1_UART4_Pos (12U)
17125#define GTZC_CFGR1_UART4_Msk ( 0x01UL << GTZC_CFGR1_UART4_Pos )
17126#define GTZC_CFGR1_USART3_Pos (11U)
17127#define GTZC_CFGR1_USART3_Msk ( 0x01UL << GTZC_CFGR1_USART3_Pos )
17128#define GTZC_CFGR1_USART2_Pos (10U)
17129#define GTZC_CFGR1_USART2_Msk ( 0x01UL << GTZC_CFGR1_USART2_Pos )
17130#define GTZC_CFGR1_SPI3_Pos (9U)
17131#define GTZC_CFGR1_SPI3_Msk ( 0x01UL << GTZC_CFGR1_SPI3_Pos )
17132#define GTZC_CFGR1_SPI2_Pos (8U)
17133#define GTZC_CFGR1_SPI2_Msk ( 0x01UL << GTZC_CFGR1_SPI2_Pos )
17134#define GTZC_CFGR1_IWDG_Pos (7U)
17135#define GTZC_CFGR1_IWDG_Msk ( 0x01UL << GTZC_CFGR1_IWDG_Pos )
17136#define GTZC_CFGR1_WWDG_Pos (6U)
17137#define GTZC_CFGR1_WWDG_Msk ( 0x01UL << GTZC_CFGR1_WWDG_Pos )
17138#define GTZC_CFGR1_TIM7_Pos (5U)
17139#define GTZC_CFGR1_TIM7_Msk ( 0x01UL << GTZC_CFGR1_TIM7_Pos )
17140#define GTZC_CFGR1_TIM6_Pos (4U)
17141#define GTZC_CFGR1_TIM6_Msk ( 0x01UL << GTZC_CFGR1_TIM6_Pos )
17142#define GTZC_CFGR1_TIM5_Pos (3U)
17143#define GTZC_CFGR1_TIM5_Msk ( 0x01UL << GTZC_CFGR1_TIM5_Pos )
17144#define GTZC_CFGR1_TIM4_Pos (2U)
17145#define GTZC_CFGR1_TIM4_Msk ( 0x01UL << GTZC_CFGR1_TIM4_Pos )
17146#define GTZC_CFGR1_TIM3_Pos (1U)
17147#define GTZC_CFGR1_TIM3_Msk ( 0x01UL << GTZC_CFGR1_TIM3_Pos )
17148#define GTZC_CFGR1_TIM2_Pos (0U)
17149#define GTZC_CFGR1_TIM2_Msk ( 0x01UL << GTZC_CFGR1_TIM2_Pos )
17150
17151/******************* Bits definition for registers x=2 ***************/
17152#define GTZC_CFGR2_OTFDEC1_Pos (29U)
17153#define GTZC_CFGR2_OTFDEC1_Msk ( 0x01UL << GTZC_CFGR2_OTFDEC1_Pos )
17154#define GTZC_CFGR2_EXTI_Pos (28U)
17155#define GTZC_CFGR2_EXTI_Msk ( 0x01UL << GTZC_CFGR2_EXTI_Pos )
17156#define GTZC_CFGR2_FLASH_REG_Pos (27U)
17157#define GTZC_CFGR2_FLASH_REG_Msk ( 0x01UL << GTZC_CFGR2_FLASH_REG_Pos )
17158#define GTZC_CFGR2_FLASH_Pos (26U)
17159#define GTZC_CFGR2_FLASH_Msk ( 0x01UL << GTZC_CFGR2_FLASH_Pos )
17160#define GTZC_CFGR2_RCC_Pos (25U)
17161#define GTZC_CFGR2_RCC_Msk ( 0x01UL << GTZC_CFGR2_RCC_Pos )
17162#define GTZC_CFGR2_DMAMUX1_Pos (24U)
17163#define GTZC_CFGR2_DMAMUX1_Msk ( 0x01UL << GTZC_CFGR2_DMAMUX1_Pos )
17164#define GTZC_CFGR2_DMA2_Pos (23U)
17165#define GTZC_CFGR2_DMA2_Msk ( 0x01UL << GTZC_CFGR2_DMA2_Pos )
17166#define GTZC_CFGR2_DMA1_Pos (22U)
17167#define GTZC_CFGR2_DMA1_Msk ( 0x01UL << GTZC_CFGR2_DMA1_Pos )
17168#define GTZC_CFGR2_SYSCFG_Pos (21U)
17169#define GTZC_CFGR2_SYSCFG_Msk ( 0x01UL << GTZC_CFGR2_SYSCFG_Pos )
17170#define GTZC_CFGR2_PWR_Pos (20U)
17171#define GTZC_CFGR2_PWR_Msk ( 0x01UL << GTZC_CFGR2_PWR_Pos )
17172#define GTZC_CFGR2_RTC_Pos (19U)
17173#define GTZC_CFGR2_RTC_Msk ( 0x01UL << GTZC_CFGR2_RTC_Pos )
17174#define GTZC_CFGR2_OCTOSPI1_REG_Pos (18U)
17175#define GTZC_CFGR2_OCTOSPI1_REG_Msk ( 0x01UL << GTZC_CFGR2_OCTOSPI1_REG_Pos )
17176#define GTZC_CFGR2_FMC_REG_Pos (17U)
17177#define GTZC_CFGR2_FMC_REG_Msk ( 0x01UL << GTZC_CFGR2_FMC_REG_Pos )
17178#define GTZC_CFGR2_SDMMC1_Pos (16U)
17179#define GTZC_CFGR2_SDMMC1_Msk ( 0x01UL << GTZC_CFGR2_SDMMC1_Pos )
17180#define GTZC_CFGR2_PKA_Pos (15U)
17181#define GTZC_CFGR2_PKA_Msk ( 0x01UL << GTZC_CFGR2_PKA_Pos )
17182#define GTZC_CFGR2_RNG_Pos (14U)
17183#define GTZC_CFGR2_RNG_Msk ( 0x01UL << GTZC_CFGR2_RNG_Pos )
17184#define GTZC_CFGR2_HASH_Pos (13U)
17185#define GTZC_CFGR2_HASH_Msk ( 0x01UL << GTZC_CFGR2_HASH_Pos )
17186#define GTZC_CFGR2_AES_Pos (12U)
17187#define GTZC_CFGR2_AES_Msk ( 0x01UL << GTZC_CFGR2_AES_Pos )
17188#define GTZC_CFGR2_ADC_Pos (11U)
17189#define GTZC_CFGR2_ADC_Msk ( 0x01UL << GTZC_CFGR2_ADC_Pos )
17190#define GTZC_CFGR2_ICACHE_REG_Pos (10U)
17191#define GTZC_CFGR2_ICACHE_REG_Msk ( 0x01UL << GTZC_CFGR2_ICACHE_REG_Pos )
17192#define GTZC_CFGR2_TSC_Pos (9U)
17193#define GTZC_CFGR2_TSC_Msk ( 0x01UL << GTZC_CFGR2_TSC_Pos )
17194#define GTZC_CFGR2_CRC_Pos (8U)
17195#define GTZC_CFGR2_CRC_Msk ( 0x01UL << GTZC_CFGR2_CRC_Pos )
17196#define GTZC_CFGR2_DFSDM1_Pos (7U)
17197#define GTZC_CFGR2_DFSDM1_Msk ( 0x01UL << GTZC_CFGR2_DFSDM1_Pos )
17198#define GTZC_CFGR2_SAI2_Pos (6U)
17199#define GTZC_CFGR2_SAI2_Msk ( 0x01UL << GTZC_CFGR2_SAI2_Pos )
17200#define GTZC_CFGR2_SAI1_Pos (5U)
17201#define GTZC_CFGR2_SAI1_Msk ( 0x01UL << GTZC_CFGR2_SAI1_Pos )
17202#define GTZC_CFGR2_TIM17_Pos (4U)
17203#define GTZC_CFGR2_TIM17_Msk ( 0x01UL << GTZC_CFGR2_TIM17_Pos )
17204#define GTZC_CFGR2_TIM16_Pos (3U)
17205#define GTZC_CFGR2_TIM16_Msk ( 0x01UL << GTZC_CFGR2_TIM16_Pos )
17206#define GTZC_CFGR2_TIM15_Pos (2U)
17207#define GTZC_CFGR2_TIM15_Msk ( 0x01UL << GTZC_CFGR2_TIM15_Pos )
17208#define GTZC_CFGR2_USART1_Pos (1U)
17209#define GTZC_CFGR2_USART1_Msk ( 0x01UL << GTZC_CFGR2_USART1_Pos )
17210#define GTZC_CFGR2_TIM8_Pos (0U)
17211#define GTZC_CFGR2_TIM8_Msk ( 0x01UL << GTZC_CFGR2_TIM8_Pos )
17212
17213/******************* Bits definition for registers x=3 ***************/
17214#define GTZC_CFGR3_MPCBB2_REG_Pos (7U)
17215#define GTZC_CFGR3_MPCBB2_REG_Msk ( 0x01UL << GTZC_CFGR3_MPCBB2_REG_Pos )
17216#define GTZC_CFGR3_SRAM2_Pos (6U)
17217#define GTZC_CFGR3_SRAM2_Msk ( 0x01UL << GTZC_CFGR3_SRAM2_Pos )
17218#define GTZC_CFGR3_MPCBB1_REG_Pos (5U)
17219#define GTZC_CFGR3_MPCBB1_REG_Msk ( 0x01UL << GTZC_CFGR3_MPCBB1_REG_Pos )
17220#define GTZC_CFGR3_SRAM1_Pos (4U)
17221#define GTZC_CFGR3_SRAM1_Msk ( 0x01UL << GTZC_CFGR3_SRAM1_Pos )
17222#define GTZC_CFGR3_OCTOSPI1_MEM_Pos (3U)
17223#define GTZC_CFGR3_OCTOSPI1_MEM_Msk ( 0x01UL << GTZC_CFGR3_OCTOSPI1_MEM_Pos )
17224#define GTZC_CFGR3_FMC_MEM_Pos (2U)
17225#define GTZC_CFGR3_FMC_MEM_Msk ( 0x01UL << GTZC_CFGR3_FMC_MEM_Pos )
17226#define GTZC_CFGR3_TZIC_Pos (1U)
17227#define GTZC_CFGR3_TZIC_Msk ( 0x01UL << GTZC_CFGR3_TZIC_Pos )
17228#define GTZC_CFGR3_TZSC_Pos (0U)
17229#define GTZC_CFGR3_TZSC_Msk ( 0x01UL << GTZC_CFGR3_TZSC_Pos )
17230
17231/******************* Bits definition for GTZC_TZSC_SECCFGR1 register ***************/
17232#define GTZC_TZSC_SECCFGR1_SPI1SEC_Pos GTZC_CFGR1_SPI1_Pos
17233#define GTZC_TZSC_SECCFGR1_SPI1SEC_Msk GTZC_CFGR1_SPI1_Msk
17234#define GTZC_TZSC_SECCFGR1_TIM1SEC_Pos GTZC_CFGR1_TIM1_Pos
17235#define GTZC_TZSC_SECCFGR1_TIM1SEC_Msk GTZC_CFGR1_TIM1_Msk
17236#define GTZC_TZSC_SECCFGR1_COMPSEC_Pos GTZC_CFGR1_COMP_Pos
17237#define GTZC_TZSC_SECCFGR1_COMPSEC_Msk GTZC_CFGR1_COMP_Msk
17238#define GTZC_TZSC_SECCFGR1_VREFBUFSEC_Pos GTZC_CFGR1_VREFBUF_Pos
17239#define GTZC_TZSC_SECCFGR1_VREFBUFSEC_Msk GTZC_CFGR1_VREFBUF_Msk
17240#define GTZC_TZSC_SECCFGR1_UCPD1SEC_Pos GTZC_CFGR1_UCPD1_Pos
17241#define GTZC_TZSC_SECCFGR1_UCPD1SEC_Msk GTZC_CFGR1_UCPD1_Msk
17242#define GTZC_TZSC_SECCFGR1_USBFSSEC_Pos GTZC_CFGR1_USBFS_Pos
17243#define GTZC_TZSC_SECCFGR1_USBFSSEC_Msk GTZC_CFGR1_USBFS_Msk
17244#define GTZC_TZSC_SECCFGR1_FDCAN1SEC_Pos GTZC_CFGR1_FDCAN1_Pos
17245#define GTZC_TZSC_SECCFGR1_FDCAN1SEC_Msk GTZC_CFGR1_FDCAN1_Msk
17246#define GTZC_TZSC_SECCFGR1_LPTIM3SEC_Pos GTZC_CFGR1_LPTIM3_Pos
17247#define GTZC_TZSC_SECCFGR1_LPTIM3SEC_Msk GTZC_CFGR1_LPTIM3_Msk
17248#define GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos GTZC_CFGR1_LPTIM2_Pos
17249#define GTZC_TZSC_SECCFGR1_LPTIM2SEC_Msk GTZC_CFGR1_LPTIM2_Msk
17250#define GTZC_TZSC_SECCFGR1_I2C4SEC_Pos GTZC_CFGR1_I2C4_Pos
17251#define GTZC_TZSC_SECCFGR1_I2C4SEC_Msk GTZC_CFGR1_I2C4_Msk
17252#define GTZC_TZSC_SECCFGR1_LPUART1SEC_Pos GTZC_CFGR1_LPUART1_Pos
17253#define GTZC_TZSC_SECCFGR1_LPUART1SEC_Msk GTZC_CFGR1_LPUART1_Msk
17254#define GTZC_TZSC_SECCFGR1_LPTIM1SEC_Pos GTZC_CFGR1_LPTIM1_Pos
17255#define GTZC_TZSC_SECCFGR1_LPTIM1SEC_Msk GTZC_CFGR1_LPTIM1_Msk
17256#define GTZC_TZSC_SECCFGR1_OPAMPSEC_Pos GTZC_CFGR1_OPAMP_Pos
17257#define GTZC_TZSC_SECCFGR1_OPAMPSEC_Msk GTZC_CFGR1_OPAMP_Msk
17258#define GTZC_TZSC_SECCFGR1_DAC1SEC_Pos GTZC_CFGR1_DAC1_Pos
17259#define GTZC_TZSC_SECCFGR1_DAC1SEC_Msk GTZC_CFGR1_DAC1_Msk
17260#define GTZC_TZSC_SECCFGR1_CRSSEC_Pos GTZC_CFGR1_CRS_Pos
17261#define GTZC_TZSC_SECCFGR1_CRSSEC_Msk GTZC_CFGR1_CRS_Msk
17262#define GTZC_TZSC_SECCFGR1_I2C3SEC_Pos GTZC_CFGR1_I2C3_Pos
17263#define GTZC_TZSC_SECCFGR1_I2C3SEC_Msk GTZC_CFGR1_I2C3_Msk
17264#define GTZC_TZSC_SECCFGR1_I2C2SEC_Pos GTZC_CFGR1_I2C2_Pos
17265#define GTZC_TZSC_SECCFGR1_I2C2SEC_Msk GTZC_CFGR1_I2C2_Msk
17266#define GTZC_TZSC_SECCFGR1_I2C1SEC_Pos GTZC_CFGR1_I2C1_Pos
17267#define GTZC_TZSC_SECCFGR1_I2C1SEC_Msk GTZC_CFGR1_I2C1_Msk
17268#define GTZC_TZSC_SECCFGR1_UART5SEC_Pos GTZC_CFGR1_UART5_Pos
17269#define GTZC_TZSC_SECCFGR1_UART5SEC_Msk GTZC_CFGR1_UART5_Msk
17270#define GTZC_TZSC_SECCFGR1_UART4SEC_Pos GTZC_CFGR1_UART4_Pos
17271#define GTZC_TZSC_SECCFGR1_UART4SEC_Msk GTZC_CFGR1_UART4_Msk
17272#define GTZC_TZSC_SECCFGR1_USART3SEC_Pos GTZC_CFGR1_USART3_Pos
17273#define GTZC_TZSC_SECCFGR1_USART3SEC_Msk GTZC_CFGR1_USART3_Msk
17274#define GTZC_TZSC_SECCFGR1_USART2SEC_Pos GTZC_CFGR1_USART2_Pos
17275#define GTZC_TZSC_SECCFGR1_USART2SEC_Msk GTZC_CFGR1_USART2_Msk
17276#define GTZC_TZSC_SECCFGR1_SPI3SEC_Pos GTZC_CFGR1_SPI3_Pos
17277#define GTZC_TZSC_SECCFGR1_SPI3SEC_Msk GTZC_CFGR1_SPI3_Msk
17278#define GTZC_TZSC_SECCFGR1_SPI2SEC_Pos GTZC_CFGR1_SPI2_Pos
17279#define GTZC_TZSC_SECCFGR1_SPI2SEC_Msk GTZC_CFGR1_SPI2_Msk
17280#define GTZC_TZSC_SECCFGR1_IWDGSEC_Pos GTZC_CFGR1_IWDG_Pos
17281#define GTZC_TZSC_SECCFGR1_IWDGSEC_Msk GTZC_CFGR1_IWDG_Msk
17282#define GTZC_TZSC_SECCFGR1_WWDGSEC_Pos GTZC_CFGR1_WWDG_Pos
17283#define GTZC_TZSC_SECCFGR1_WWDGSEC_Msk GTZC_CFGR1_WWDG_Msk
17284#define GTZC_TZSC_SECCFGR1_TIM7SEC_Pos GTZC_CFGR1_TIM7_Pos
17285#define GTZC_TZSC_SECCFGR1_TIM7SEC_Msk GTZC_CFGR1_TIM7_Msk
17286#define GTZC_TZSC_SECCFGR1_TIM6SEC_Pos GTZC_CFGR1_TIM6_Pos
17287#define GTZC_TZSC_SECCFGR1_TIM6SEC_Msk GTZC_CFGR1_TIM6_Msk
17288#define GTZC_TZSC_SECCFGR1_TIM5SEC_Pos GTZC_CFGR1_TIM5_Pos
17289#define GTZC_TZSC_SECCFGR1_TIM5SEC_Msk GTZC_CFGR1_TIM5_Msk
17290#define GTZC_TZSC_SECCFGR1_TIM4SEC_Pos GTZC_CFGR1_TIM4_Pos
17291#define GTZC_TZSC_SECCFGR1_TIM4SEC_Msk GTZC_CFGR1_TIM4_Msk
17292#define GTZC_TZSC_SECCFGR1_TIM3SEC_Pos GTZC_CFGR1_TIM3_Pos
17293#define GTZC_TZSC_SECCFGR1_TIM3SEC_Msk GTZC_CFGR1_TIM3_Msk
17294#define GTZC_TZSC_SECCFGR1_TIM2SEC_Pos GTZC_CFGR1_TIM2_Pos
17295#define GTZC_TZSC_SECCFGR1_TIM2SEC_Msk GTZC_CFGR1_TIM2_Msk
17296
17297/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/
17298#define GTZC_TZSC_SECCFGR2_OCTOSPI1_REGSEC_Pos GTZC_CFGR2_OCTOSPI1_REG_Pos
17299#define GTZC_TZSC_SECCFGR2_OCTOSPI1_REGSEC_Msk GTZC_CFGR2_OCTOSPI1_REG_Msk
17300#define GTZC_TZSC_SECCFGR2_FMC_REGSEC_Pos GTZC_CFGR2_FMC_REG_Pos
17301#define GTZC_TZSC_SECCFGR2_FMC_REGSEC_Msk GTZC_CFGR2_FMC_REG_Msk
17302#define GTZC_TZSC_SECCFGR2_SDMMC1SEC_Pos GTZC_CFGR2_SDMMC1_Pos
17303#define GTZC_TZSC_SECCFGR2_SDMMC1SEC_Msk GTZC_CFGR2_SDMMC1_Msk
17304#define GTZC_TZSC_SECCFGR2_PKASEC_Pos GTZC_CFGR2_PKA_Pos
17305#define GTZC_TZSC_SECCFGR2_PKASEC_Msk GTZC_CFGR2_PKA_Msk
17306#define GTZC_TZSC_SECCFGR2_RNGSEC_Pos GTZC_CFGR2_RNG_Pos
17307#define GTZC_TZSC_SECCFGR2_RNGSEC_Msk GTZC_CFGR2_RNG_Msk
17308#define GTZC_TZSC_SECCFGR2_HASHSEC_Pos GTZC_CFGR2_HASH_Pos
17309#define GTZC_TZSC_SECCFGR2_HASHSEC_Msk GTZC_CFGR2_HASH_Msk
17310#define GTZC_TZSC_SECCFGR2_AESSEC_Pos GTZC_CFGR2_AES_Pos
17311#define GTZC_TZSC_SECCFGR2_AESSEC_Msk GTZC_CFGR2_AES_Msk
17312#define GTZC_TZSC_SECCFGR2_ADCSEC_Pos GTZC_CFGR2_ADC_Pos
17313#define GTZC_TZSC_SECCFGR2_ADCSEC_Msk GTZC_CFGR2_ADC_Msk
17314#define GTZC_TZSC_SECCFGR2_ICACHE_REGSEC_Pos GTZC_CFGR2_ICACHE_REG_Pos
17315#define GTZC_TZSC_SECCFGR2_ICACHE_REGSEC_Msk GTZC_CFGR2_ICACHE_REG_Msk
17316#define GTZC_TZSC_SECCFGR2_TSCSEC_Pos GTZC_CFGR2_TSC_Pos
17317#define GTZC_TZSC_SECCFGR2_TSCSEC_Msk GTZC_CFGR2_TSC_Msk
17318#define GTZC_TZSC_SECCFGR2_CRCSEC_Pos GTZC_CFGR2_CRC_Pos
17319#define GTZC_TZSC_SECCFGR2_CRCSEC_Msk GTZC_CFGR2_CRC_Msk
17320#define GTZC_TZSC_SECCFGR2_DFSDM1SEC_Pos GTZC_CFGR2_DFSDM1_Pos
17321#define GTZC_TZSC_SECCFGR2_DFSDM1SEC_Msk GTZC_CFGR2_DFSDM1_Msk
17322#define GTZC_TZSC_SECCFGR2_SAI2SEC_Pos GTZC_CFGR2_SAI2_Pos
17323#define GTZC_TZSC_SECCFGR2_SAI2SEC_Msk GTZC_CFGR2_SAI2_Msk
17324#define GTZC_TZSC_SECCFGR2_SAI1SEC_Pos GTZC_CFGR2_SAI1_Pos
17325#define GTZC_TZSC_SECCFGR2_SAI1SEC_Msk GTZC_CFGR2_SAI1_Msk
17326#define GTZC_TZSC_SECCFGR2_TIM17SEC_Pos GTZC_CFGR2_TIM17_Pos
17327#define GTZC_TZSC_SECCFGR2_TIM17SEC_Msk GTZC_CFGR2_TIM17_Msk
17328#define GTZC_TZSC_SECCFGR2_TIM16SEC_Pos GTZC_CFGR2_TIM16_Pos
17329#define GTZC_TZSC_SECCFGR2_TIM16SEC_Msk GTZC_CFGR2_TIM16_Msk
17330#define GTZC_TZSC_SECCFGR2_TIM15SEC_Pos GTZC_CFGR2_TIM15_Pos
17331#define GTZC_TZSC_SECCFGR2_TIM15SEC_Msk GTZC_CFGR2_TIM15_Msk
17332#define GTZC_TZSC_SECCFGR2_USART1SEC_Pos GTZC_CFGR2_USART1_Pos
17333#define GTZC_TZSC_SECCFGR2_USART1SEC_Msk GTZC_CFGR2_USART1_Msk
17334#define GTZC_TZSC_SECCFGR2_TIM8SEC_Pos GTZC_CFGR2_TIM8_Pos
17335#define GTZC_TZSC_SECCFGR2_TIM8SEC_Msk GTZC_CFGR2_TIM8_Msk
17336
17337/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/
17338#define GTZC_TZSC_PRIVCFGR1_SPI1PRIV_Pos GTZC_CFGR1_SPI1_Pos
17339#define GTZC_TZSC_PRIVCFGR1_SPI1PRIV_Msk GTZC_CFGR1_SPI1_Msk
17340#define GTZC_TZSC_PRIVCFGR1_TIM1PRIV_Pos GTZC_CFGR1_TIM1_Pos
17341#define GTZC_TZSC_PRIVCFGR1_TIM1PRIV_Msk GTZC_CFGR1_TIM1_Msk
17342#define GTZC_TZSC_PRIVCFGR1_COMPPRIV_Pos GTZC_CFGR1_COMP_Pos
17343#define GTZC_TZSC_PRIVCFGR1_COMPPRIV_Msk GTZC_CFGR1_COMP_Msk
17344#define GTZC_TZSC_PRIVCFGR1_VREFBUFPRIV_Pos GTZC_CFGR1_VREFBUF_Pos
17345#define GTZC_TZSC_PRIVCFGR1_VREFBUFPRIV_Msk GTZC_CFGR1_VREFBUF_Msk
17346#define GTZC_TZSC_PRIVCFGR1_UCPD1PRIV_Pos GTZC_CFGR1_UCPD1_Pos
17347#define GTZC_TZSC_PRIVCFGR1_UCPD1PRIV_Msk GTZC_CFGR1_UCPD1_Msk
17348#define GTZC_TZSC_PRIVCFGR1_USBFSPRIV_Pos GTZC_CFGR1_USBFS_Pos
17349#define GTZC_TZSC_PRIVCFGR1_USBFSPRIV_Msk GTZC_CFGR1_USBFS_Msk
17350#define GTZC_TZSC_PRIVCFGR1_FDCAN1PRIV_Pos GTZC_CFGR1_FDCAN1_Pos
17351#define GTZC_TZSC_PRIVCFGR1_FDCAN1PRIV_Msk GTZC_CFGR1_FDCAN1_Msk
17352#define GTZC_TZSC_PRIVCFGR1_LPTIM3PRIV_Pos GTZC_CFGR1_LPTIM3_Pos
17353#define GTZC_TZSC_PRIVCFGR1_LPTIM3PRIV_Msk GTZC_CFGR1_LPTIM3_Msk
17354#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Pos GTZC_CFGR1_LPTIM2_Pos
17355#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Msk GTZC_CFGR1_LPTIM2_Msk
17356#define GTZC_TZSC_PRIVCFGR1_I2C4PRIV_Pos GTZC_CFGR1_I2C4_Pos
17357#define GTZC_TZSC_PRIVCFGR1_I2C4PRIV_Msk GTZC_CFGR1_I2C4_Msk
17358#define GTZC_TZSC_PRIVCFGR1_LPUART1PRIV_Pos GTZC_CFGR1_LPUART1_Pos
17359#define GTZC_TZSC_PRIVCFGR1_LPUART1PRIV_Msk GTZC_CFGR1_LPUART1_Msk
17360#define GTZC_TZSC_PRIVCFGR1_LPTIM1PRIV_Pos GTZC_CFGR1_LPTIM1_Pos
17361#define GTZC_TZSC_PRIVCFGR1_LPTIM1PRIV_Msk GTZC_CFGR1_LPTIM1_Msk
17362#define GTZC_TZSC_PRIVCFGR1_OPAMPPRIV_Pos GTZC_CFGR1_OPAMP_Pos
17363#define GTZC_TZSC_PRIVCFGR1_OPAMPPRIV_Msk GTZC_CFGR1_OPAMP_Msk
17364#define GTZC_TZSC_PRIVCFGR1_DAC1PRIV_Pos GTZC_CFGR1_DAC1_Pos
17365#define GTZC_TZSC_PRIVCFGR1_DAC1PRIV_Msk GTZC_CFGR1_DAC1_Msk
17366#define GTZC_TZSC_PRIVCFGR1_CRSPRIV_Pos GTZC_CFGR1_CRS_Pos
17367#define GTZC_TZSC_PRIVCFGR1_CRSPRIV_Msk GTZC_CFGR1_CRS_Msk
17368#define GTZC_TZSC_PRIVCFGR1_I2C3PRIV_Pos GTZC_CFGR1_I2C3_Pos
17369#define GTZC_TZSC_PRIVCFGR1_I2C3PRIV_Msk GTZC_CFGR1_I2C3_Msk
17370#define GTZC_TZSC_PRIVCFGR1_I2C2PRIV_Pos GTZC_CFGR1_I2C2_Pos
17371#define GTZC_TZSC_PRIVCFGR1_I2C2PRIV_Msk GTZC_CFGR1_I2C2_Msk
17372#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Pos GTZC_CFGR1_I2C1_Pos
17373#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Msk GTZC_CFGR1_I2C1_Msk
17374#define GTZC_TZSC_PRIVCFGR1_UART5PRIV_Pos GTZC_CFGR1_UART5_Pos
17375#define GTZC_TZSC_PRIVCFGR1_UART5PRIV_Msk GTZC_CFGR1_UART5_Msk
17376#define GTZC_TZSC_PRIVCFGR1_UART4PRIV_Pos GTZC_CFGR1_UART4_Pos
17377#define GTZC_TZSC_PRIVCFGR1_UART4PRIV_Msk GTZC_CFGR1_UART4_Msk
17378#define GTZC_TZSC_PRIVCFGR1_USART3PRIV_Pos GTZC_CFGR1_USART3_Pos
17379#define GTZC_TZSC_PRIVCFGR1_USART3PRIV_Msk GTZC_CFGR1_USART3_Msk
17380#define GTZC_TZSC_PRIVCFGR1_USART2PRIV_Pos GTZC_CFGR1_USART2_Pos
17381#define GTZC_TZSC_PRIVCFGR1_USART2PRIV_Msk GTZC_CFGR1_USART2_Msk
17382#define GTZC_TZSC_PRIVCFGR1_SPI3PRIV_Pos GTZC_CFGR1_PI3_Pos
17383#define GTZC_TZSC_PRIVCFGR1_SPI3PRIV_Msk GTZC_CFGR1_SPI3_Msk
17384#define GTZC_TZSC_PRIVCFGR1_SPI2PRIV_Pos GTZC_CFGR1_SPI2_Pos
17385#define GTZC_TZSC_PRIVCFGR1_SPI2PRIV_Msk GTZC_CFGR1_SPI2_Msk
17386#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Pos GTZC_CFGR1_IWDG_Pos
17387#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Msk GTZC_CFGR1_IWDG_Msk
17388#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Pos GTZC_CFGR1_WWDG_Pos
17389#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Msk GTZC_CFGR1_WWDG_Msk
17390#define GTZC_TZSC_PRIVCFGR1_TIM7PRIV_Pos GTZC_CFGR1_TIM7_Pos
17391#define GTZC_TZSC_PRIVCFGR1_TIM7PRIV_Msk GTZC_CFGR1_TIM7_Msk
17392#define GTZC_TZSC_PRIVCFGR1_TIM6PRIV_Pos GTZC_CFGR1_TIM6_Pos
17393#define GTZC_TZSC_PRIVCFGR1_TIM6PRIV_Msk GTZC_CFGR1_TIM6_Msk
17394#define GTZC_TZSC_PRIVCFGR1_TIM5PRIV_Pos GTZC_CFGR1_TIM5_Pos
17395#define GTZC_TZSC_PRIVCFGR1_TIM5PRIV_Msk GTZC_CFGR1_TIM5_Msk
17396#define GTZC_TZSC_PRIVCFGR1_TIM4PRIV_Pos GTZC_CFGR1_TIM4_Pos
17397#define GTZC_TZSC_PRIVCFGR1_TIM4PRIV_Msk GTZC_CFGR1_TIM4_Msk
17398#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Pos GTZC_CFGR1_TIM3_Pos
17399#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Msk GTZC_CFGR1_TIM3_Msk
17400#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Pos GTZC_CFGR1_TIM2_Pos
17401#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Msk GTZC_CFGR1_TIM2_Msk
17402
17403/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/
17404#define GTZC_TZSC_PRIVCFGR2_OCTOSPI1_REGPRIV_Pos GTZC_CFGR2_OCTOSPI1_REG_Pos
17405#define GTZC_TZSC_PRIVCFGR2_OCTOSPI1_REGPRIV_Msk GTZC_CFGR2_OCTOSPI1_REG_Msk
17406#define GTZC_TZSC_PRIVCFGR2_FMC_REGPRIV_Pos GTZC_CFGR2_FMC_REG_Pos
17407#define GTZC_TZSC_PRIVCFGR2_FMC_REGPRIV_Msk GTZC_CFGR2_FMC_REG_Msk
17408#define GTZC_TZSC_PRIVCFGR2_SDMMC1PRIV_Pos GTZC_CFGR2_SDMMC1_Pos
17409#define GTZC_TZSC_PRIVCFGR2_SDMMC1PRIV_Msk GTZC_CFGR2_SDMMC1_Msk
17410#define GTZC_TZSC_PRIVCFGR2_PKAPRIV_Pos GTZC_CFGR2_PKA_Pos
17411#define GTZC_TZSC_PRIVCFGR2_PKAPRIV_Msk GTZC_CFGR2_PKA_Msk
17412#define GTZC_TZSC_PRIVCFGR2_RNGPRIV_Pos GTZC_CFGR2_RNG_Pos
17413#define GTZC_TZSC_PRIVCFGR2_RNGPRIV_Msk GTZC_CFGR2_RNG_Msk
17414#define GTZC_TZSC_PRIVCFGR2_HASHPRIV_Pos GTZC_CFGR2_HASH_Pos
17415#define GTZC_TZSC_PRIVCFGR2_HASHPRIV_Msk GTZC_CFGR2_HASH_Msk
17416#define GTZC_TZSC_PRIVCFGR2_AESPRIV_Pos GTZC_CFGR2_AES_Pos
17417#define GTZC_TZSC_PRIVCFGR2_AESPRIV_Msk GTZC_CFGR2_AES_Msk
17418#define GTZC_TZSC_PRIVCFGR2_ADCPRIV_Pos GTZC_CFGR2_ADC_Pos
17419#define GTZC_TZSC_PRIVCFGR2_ADCPRIV_Msk GTZC_CFGR2_ADC_Msk
17420#define GTZC_TZSC_PRIVCFGR2_ICACHE_REGPRIV_Pos GTZC_CFGR2_ICACHE_REG_Pos
17421#define GTZC_TZSC_PRIVCFGR2_ICACHE_REGPRIV_Msk GTZC_CFGR2_ICACHE_REG_Msk
17422#define GTZC_TZSC_PRIVCFGR2_TSCPRIV_Pos GTZC_CFGR2_TSC_Pos
17423#define GTZC_TZSC_PRIVCFGR2_TSCPRIV_Msk GTZC_CFGR2_TSC_Msk
17424#define GTZC_TZSC_PRIVCFGR2_CRCPRIV_Pos GTZC_CFGR2_CRC_Pos
17425#define GTZC_TZSC_PRIVCFGR2_CRCPRIV_Msk GTZC_CFGR2_CRC_Msk
17426#define GTZC_TZSC_PRIVCFGR2_DFSDM1PRIV_Pos GTZC_CFGR2_DFSDM1_Pos
17427#define GTZC_TZSC_PRIVCFGR2_DFSDM1PRIV_Msk GTZC_CFGR2_DFSDM1_Msk
17428#define GTZC_TZSC_PRIVCFGR2_SAI2PRIV_Pos GTZC_CFGR2_SAI2_Pos
17429#define GTZC_TZSC_PRIVCFGR2_SAI2PRIV_Msk GTZC_CFGR2_SAI2_Msk
17430#define GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Pos GTZC_CFGR2_SAI1_Pos
17431#define GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Msk GTZC_CFGR2_SAI1_Msk
17432#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Pos GTZC_CFGR2_TIM17_Pos
17433#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Msk GTZC_CFGR2_TIM17_Msk
17434#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Pos GTZC_CFGR2_TIM16_Pos
17435#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Msk GTZC_CFGR2_TIM16_Msk
17436#define GTZC_TZSC_PRIVCFGR2_TIM15PRIV_Pos GTZC_CFGR2_TIM15_Pos
17437#define GTZC_TZSC_PRIVCFGR2_TIM15PRIV_Msk GTZC_CFGR2_TIM15_Msk
17438#define GTZC_TZSC_PRIVCFGR2_USART1PRIV_Pos GTZC_CFGR2_USART1_Pos
17439#define GTZC_TZSC_PRIVCFGR2_USART1PRIV_Msk GTZC_CFGR2_USART1_Msk
17440#define GTZC_TZSC_PRIVCFGR2_TIM8PRIV_Pos GTZC_CFGR2_TIM8_Pos
17441#define GTZC_TZSC_PRIVCFGR2_TIM8PRIV_Msk GTZC_CFGR2_TIM8_Msk
17442
17443/******************* Bits definition for GTZC_TZIC_IER1 register ***************/
17444#define GTZC_TZIC_IER1_SPI1IE_Pos GTZC_CFGR1_SPI1_Pos
17445#define GTZC_TZIC_IER1_SPI1IE_Msk GTZC_CFGR1_SPI1_Msk
17446#define GTZC_TZIC_IER1_TIM1IE_Pos GTZC_CFGR1_TIM1_Pos
17447#define GTZC_TZIC_IER1_TIM1IE_Msk GTZC_CFGR1_TIM1_Msk
17448#define GTZC_TZIC_IER1_COMPIE_Pos GTZC_CFGR1_COMP_Pos
17449#define GTZC_TZIC_IER1_COMPIE_Msk GTZC_CFGR1_COMP_Msk
17450#define GTZC_TZIC_IER1_VREFBUFIE_Pos GTZC_CFGR1_VREFBUF_Pos
17451#define GTZC_TZIC_IER1_VREFBUFIE_Msk GTZC_CFGR1_VREFBUF_Msk
17452#define GTZC_TZIC_IER1_UCPD1IE_Pos GTZC_CFGR1_UCPD1_Pos
17453#define GTZC_TZIC_IER1_UCPD1IE_Msk GTZC_CFGR1_UCPD1_Msk
17454#define GTZC_TZIC_IER1_USBFSIE_Pos GTZC_CFGR1_USBFS_Pos
17455#define GTZC_TZIC_IER1_USBFSIE_Msk GTZC_CFGR1_USBFS_Msk
17456#define GTZC_TZIC_IER1_FDCAN1IE_Pos GTZC_CFGR1_FDCAN1_Pos
17457#define GTZC_TZIC_IER1_FDCAN1IE_Msk GTZC_CFGR1_FDCAN1_Msk
17458#define GTZC_TZIC_IER1_LPTIM3IE_Pos GTZC_CFGR1_LPTIM3_Pos
17459#define GTZC_TZIC_IER1_LPTIM3IE_Msk GTZC_CFGR1_LPTIM3_Msk
17460#define GTZC_TZIC_IER1_LPTIM2IE_Pos GTZC_CFGR1_LPTIM2_Pos
17461#define GTZC_TZIC_IER1_LPTIM2IE_Msk GTZC_CFGR1_LPTIM2_Msk
17462#define GTZC_TZIC_IER1_I2C4IE_Pos GTZC_CFGR1_I2C4_Pos
17463#define GTZC_TZIC_IER1_I2C4IE_Msk GTZC_CFGR1_I2C4_Msk
17464#define GTZC_TZIC_IER1_LPUART1IE_Pos GTZC_CFGR1_LPUART1_Pos
17465#define GTZC_TZIC_IER1_LPUART1IE_Msk GTZC_CFGR1_LPUART1_Msk
17466#define GTZC_TZIC_IER1_LPTIM1IE_Pos GTZC_CFGR1_LPTIM1_Pos
17467#define GTZC_TZIC_IER1_LPTIM1IE_Msk GTZC_CFGR1_LPTIM1_Msk
17468#define GTZC_TZIC_IER1_OPAMPIE_Pos GTZC_CFGR1_OPAMP_Pos
17469#define GTZC_TZIC_IER1_OPAMPIE_Msk GTZC_CFGR1_OPAMP_Msk
17470#define GTZC_TZIC_IER1_DAC1IE_Pos GTZC_CFGR1_DAC1_Pos
17471#define GTZC_TZIC_IER1_DAC1IE_Msk GTZC_CFGR1_DAC1_Msk
17472#define GTZC_TZIC_IER1_CRSIE_Pos GTZC_CFGR1_CRS_Pos
17473#define GTZC_TZIC_IER1_CRSIE_Msk GTZC_CFGR1_CRS_Msk
17474#define GTZC_TZIC_IER1_I2C3IE_Pos GTZC_CFGR1_I2C3_Pos
17475#define GTZC_TZIC_IER1_I2C3IE_Msk GTZC_CFGR1_I2C3_Msk
17476#define GTZC_TZIC_IER1_I2C2IE_Pos GTZC_CFGR1_I2C2_Pos
17477#define GTZC_TZIC_IER1_I2C2IE_Msk GTZC_CFGR1_I2C2_Msk
17478#define GTZC_TZIC_IER1_I2C1IE_Pos GTZC_CFGR1_I2C1_Pos
17479#define GTZC_TZIC_IER1_I2C1IE_Msk GTZC_CFGR1_I2C1_Msk
17480#define GTZC_TZIC_IER1_UART5IE_Pos GTZC_CFGR1_UART5_Pos
17481#define GTZC_TZIC_IER1_UART5IE_Msk GTZC_CFGR1_UART5_Msk
17482#define GTZC_TZIC_IER1_UART4IE_Pos GTZC_CFGR1_UART4_Pos
17483#define GTZC_TZIC_IER1_UART4IE_Msk GTZC_CFGR1_UART4_Msk
17484#define GTZC_TZIC_IER1_USART3IE_Pos GTZC_CFGR1_USART3_Pos
17485#define GTZC_TZIC_IER1_USART3IE_Msk GTZC_CFGR1_USART3_Msk
17486#define GTZC_TZIC_IER1_USART2IE_Pos GTZC_CFGR1_USART2_Pos
17487#define GTZC_TZIC_IER1_USART2IE_Msk GTZC_CFGR1_USART2_Msk
17488#define GTZC_TZIC_IER1_SPI3IE_Pos GTZC_CFGR1_SPI3_Pos
17489#define GTZC_TZIC_IER1_SPI3IE_Msk GTZC_CFGR1_SPI3_Msk
17490#define GTZC_TZIC_IER1_SPI2IE_Pos GTZC_CFGR1_SPI2_Pos
17491#define GTZC_TZIC_IER1_SPI2IE_Msk GTZC_CFGR1_SPI2_Msk
17492#define GTZC_TZIC_IER1_IWDGIE_Pos GTZC_CFGR1_IWDG_Pos
17493#define GTZC_TZIC_IER1_IWDGIE_Msk GTZC_CFGR1_IWDG_Msk
17494#define GTZC_TZIC_IER1_WWDGIE_Pos GTZC_CFGR1_WWDG_Pos
17495#define GTZC_TZIC_IER1_WWDGIE_Msk GTZC_CFGR1_WWDG_Msk
17496#define GTZC_TZIC_IER1_TIM7IE_Pos GTZC_CFGR1_TIM7_Pos
17497#define GTZC_TZIC_IER1_TIM7IE_Msk GTZC_CFGR1_TIM7_Msk
17498#define GTZC_TZIC_IER1_TIM6IE_Pos GTZC_CFGR1_TIM6_Pos
17499#define GTZC_TZIC_IER1_TIM6IE_Msk GTZC_CFGR1_TIM6_Msk
17500#define GTZC_TZIC_IER1_TIM5IE_Pos GTZC_CFGR1_TIM5_Pos
17501#define GTZC_TZIC_IER1_TIM5IE_Msk GTZC_CFGR1_TIM5_Msk
17502#define GTZC_TZIC_IER1_TIM4IE_Pos GTZC_CFGR1_TIM4_Pos
17503#define GTZC_TZIC_IER1_TIM4IE_Msk GTZC_CFGR1_TIM4_Msk
17504#define GTZC_TZIC_IER1_TIM3IE_Pos GTZC_CFGR1_TIM3_Pos
17505#define GTZC_TZIC_IER1_TIM3IE_Msk GTZC_CFGR1_TIM3_Msk
17506#define GTZC_TZIC_IER1_TIM2IE_Pos GTZC_CFGR1_TIM2_Pos
17507#define GTZC_TZIC_IER1_TIM2IE_Msk GTZC_CFGR1_TIM2_Msk
17508
17509/******************* Bits definition for GTZC_TZIC_IER2 register ***************/
17510#define GTZC_TZIC_IER2_OTFDEC1IE_Pos GTZC_CFGR2_OTFDEC1_Pos
17511#define GTZC_TZIC_IER2_OTFDEC1IE_Msk GTZC_CFGR2_OTFDEC1_Msk
17512#define GTZC_TZIC_IER2_EXTIIE_Pos GTZC_CFGR2_EXTI_Pos
17513#define GTZC_TZIC_IER2_EXTIIE_Msk GTZC_CFGR2_EXTI_Msk
17514#define GTZC_TZIC_IER2_FLASH_REGIE_Pos GTZC_CFGR2_FLASH_REG_Pos
17515#define GTZC_TZIC_IER2_FLASH_REGIE_Msk GTZC_CFGR2_FLASH_REG_Msk
17516#define GTZC_TZIC_IER2_FLASHIE_Pos GTZC_CFGR2_FLASH_Pos
17517#define GTZC_TZIC_IER2_FLASHIE_Msk GTZC_CFGR2_FLASH_Msk
17518#define GTZC_TZIC_IER2_RCCIE_Pos GTZC_CFGR2_RCC_Pos
17519#define GTZC_TZIC_IER2_RCCIE_Msk GTZC_CFGR2_RCC_Msk
17520#define GTZC_TZIC_IER2_DMAMUX1IE_Pos GTZC_CFGR2_DMAMUX1_Pos
17521#define GTZC_TZIC_IER2_DMAMUX1IE_Msk GTZC_CFGR2_DMAMUX1_Msk
17522#define GTZC_TZIC_IER2_DMA2IE_Pos GTZC_CFGR2_DMA2_Pos
17523#define GTZC_TZIC_IER2_DMA2IE_Msk GTZC_CFGR2_DMA2_Msk
17524#define GTZC_TZIC_IER2_DMA1IE_Pos GTZC_CFGR2_DMA1_Pos
17525#define GTZC_TZIC_IER2_DMA1IE_Msk GTZC_CFGR2_DMA1_Msk
17526#define GTZC_TZIC_IER2_SYSCFGIE_Pos GTZC_CFGR2_SYSCFG_Pos
17527#define GTZC_TZIC_IER2_SYSCFGIE_Msk GTZC_CFGR2_SYSCFG_Msk
17528#define GTZC_TZIC_IER2_PWRIE_Pos GTZC_CFGR2_PWR_Pos
17529#define GTZC_TZIC_IER2_PWRIE_Msk GTZC_CFGR2_PWR_Msk
17530#define GTZC_TZIC_IER2_RTCIE_Pos GTZC_CFGR2_RTC_Pos
17531#define GTZC_TZIC_IER2_RTCIE_Msk GTZC_CFGR2_RTC_Msk
17532#define GTZC_TZIC_IER2_OCTOSPI1_REGIE_Pos GTZC_CFGR2_OCTOSPI1_REG_Pos
17533#define GTZC_TZIC_IER2_OCTOSPI1_REGIE_Msk GTZC_CFGR2_OCTOSPI1_REG_Msk
17534#define GTZC_TZIC_IER2_FMC_REGIE_Pos GTZC_CFGR2_FMC_REG_Pos
17535#define GTZC_TZIC_IER2_FMC_REGIE_Msk GTZC_CFGR2_FMC_REG_Msk
17536#define GTZC_TZIC_IER2_SDMMC1IE_Pos GTZC_CFGR2_SDMMC1_Pos
17537#define GTZC_TZIC_IER2_SDMMC1IE_Msk GTZC_CFGR2_SDMMC1_Msk
17538#define GTZC_TZIC_IER2_PKAIE_Pos GTZC_CFGR2_PKA_Pos
17539#define GTZC_TZIC_IER2_PKAIE_Msk GTZC_CFGR2_PKA_Msk
17540#define GTZC_TZIC_IER2_RNGIE_Pos GTZC_CFGR2_RNG_Pos
17541#define GTZC_TZIC_IER2_RNGIE_Msk GTZC_CFGR2_RNG_Msk
17542#define GTZC_TZIC_IER2_HASHIE_Pos GTZC_CFGR2_HASH_Pos
17543#define GTZC_TZIC_IER2_HASHIE_Msk GTZC_CFGR2_HASH_Msk
17544#define GTZC_TZIC_IER2_AESIE_Pos GTZC_CFGR2_AES_Pos
17545#define GTZC_TZIC_IER2_AESIE_Msk GTZC_CFGR2_AES_Msk
17546#define GTZC_TZIC_IER2_ADCIE_Pos GTZC_CFGR2_ADC_Pos
17547#define GTZC_TZIC_IER2_ADCIE_Msk GTZC_CFGR2_ADC_Msk
17548#define GTZC_TZIC_IER2_ICACHE_REGIE_Pos GTZC_CFGR2_ICACHE_REG_Pos
17549#define GTZC_TZIC_IER2_ICACHE_REGIE_Msk GTZC_CFGR2_ICACHE_REG_Msk
17550#define GTZC_TZIC_IER2_TSCIE_Pos GTZC_CFGR2_TSC_Pos
17551#define GTZC_TZIC_IER2_TSCIE_Msk GTZC_CFGR2_TSC_Msk
17552#define GTZC_TZIC_IER2_CRCIE_Pos GTZC_CFGR2_CRC_Pos
17553#define GTZC_TZIC_IER2_CRCIE_Msk GTZC_CFGR2_CRC_Msk
17554#define GTZC_TZIC_IER2_DFSDM1IE_Pos GTZC_CFGR2_DFSDM1_Pos
17555#define GTZC_TZIC_IER2_DFSDM1IE_Msk GTZC_CFGR2_DFSDM1_Msk
17556#define GTZC_TZIC_IER2_SAI2IE_Pos GTZC_CFGR2_SAI2_Pos
17557#define GTZC_TZIC_IER2_SAI2IE_Msk GTZC_CFGR2_SAI2_Msk
17558#define GTZC_TZIC_IER2_SAI1IE_Pos GTZC_CFGR2_SAI1_Pos
17559#define GTZC_TZIC_IER2_SAI1IE_Msk GTZC_CFGR2_SAI1_Msk
17560#define GTZC_TZIC_IER2_TIM17IE_Pos GTZC_CFGR2_TIM17_Pos
17561#define GTZC_TZIC_IER2_TIM17IE_Msk GTZC_CFGR2_TIM17_Msk
17562#define GTZC_TZIC_IER2_TIM16IE_Pos GTZC_CFGR2_TIM16_Pos
17563#define GTZC_TZIC_IER2_TIM16IE_Msk GTZC_CFGR2_TIM16_Msk
17564#define GTZC_TZIC_IER2_TIM15IE_Pos GTZC_CFGR2_TIM15_Pos
17565#define GTZC_TZIC_IER2_TIM15IE_Msk GTZC_CFGR2_TIM15_Msk
17566#define GTZC_TZIC_IER2_USART1IE_Pos GTZC_CFGR2_USART1_Pos
17567#define GTZC_TZIC_IER2_USART1IE_Msk GTZC_CFGR2_USART1_Msk
17568#define GTZC_TZIC_IER2_TIM8IE_Pos GTZC_CFGR2_TIM8_Pos
17569#define GTZC_TZIC_IER2_TIM8IE_Msk GTZC_CFGR2_TIM8_Msk
17570
17571/******************* Bits definition for GTZC_TZIC_IER3 register ***************/
17572#define GTZC_TZIC_IER3_MPCBB2_REGIE_Pos GTZC_CFGR3_MPCBB2_REG_Pos
17573#define GTZC_TZIC_IER3_MPCBB2_REGIE_Msk GTZC_CFGR3_MPCBB2_REG_Msk
17574#define GTZC_TZIC_IER3_SRAM2IE_Pos GTZC_CFGR3_SRAM2_Pos
17575#define GTZC_TZIC_IER3_SRAM2IE_Msk GTZC_CFGR3_SRAM2_Msk
17576#define GTZC_TZIC_IER3_MPCBB1_REGIE_Pos GTZC_CFGR3_MPCBB1_REG_Pos
17577#define GTZC_TZIC_IER3_MPCBB1_REGIE_Msk GTZC_CFGR3_MPCBB1_REG_Msk
17578#define GTZC_TZIC_IER3_SRAM1IE_Pos GTZC_CFGR3_SRAM1_Pos
17579#define GTZC_TZIC_IER3_SRAM1IE_Msk GTZC_CFGR3_SRAM1_Msk
17580#define GTZC_TZIC_IER3_OCTOSPI1_MEMIE_Pos GTZC_CFGR3_OCTOSPI1_MEM_Pos
17581#define GTZC_TZIC_IER3_OCTOSPI1_MEMIE_Msk GTZC_CFGR3_OCTOSPI1_MEM_Msk
17582#define GTZC_TZIC_IER3_FMC_MEMIE_Pos GTZC_CFGR3_FMC_MEM_Pos
17583#define GTZC_TZIC_IER3_FMC_MEMIE_Msk GTZC_CFGR3_FMC_MEM_Msk
17584#define GTZC_TZIC_IER3_TZICIE_Pos GTZC_CFGR3_TZIC_Pos
17585#define GTZC_TZIC_IER3_TZICIE_Msk GTZC_CFGR3_TZIC_Msk
17586#define GTZC_TZIC_IER3_TZSCIE_Pos GTZC_CFGR3_TZSC_Pos
17587#define GTZC_TZIC_IER3_TZSCIE_Msk GTZC_CFGR3_TZSC_Msk
17588
17589/******************* Bits definition for GTZC_TZIC_SR1 register **************/
17590#define GTZC_TZIC_SR1_SPI1F_Pos GTZC_CFGR1_SPI1_Pos
17591#define GTZC_TZIC_SR1_SPI1F_Msk GTZC_CFGR1_SPI1_Msk
17592#define GTZC_TZIC_SR1_TIM1F_Pos GTZC_CFGR1_TIM1_Pos
17593#define GTZC_TZIC_SR1_TIM1F_Msk GTZC_CFGR1_TIM1_Msk
17594#define GTZC_TZIC_SR1_COMPF_Pos GTZC_CFGR1_COMP_Pos
17595#define GTZC_TZIC_SR1_COMPF_Msk GTZC_CFGR1_COMP_Msk
17596#define GTZC_TZIC_SR1_VREFBUFF_Pos GTZC_CFGR1_VREFBUF_Pos
17597#define GTZC_TZIC_SR1_VREFBUFF_Msk GTZC_CFGR1_VREFBUF_Msk
17598#define GTZC_TZIC_SR1_UCPD1F_Pos GTZC_CFGR1_UCPD1_Pos
17599#define GTZC_TZIC_SR1_UCPD1F_Msk GTZC_CFGR1_UCPD1_Msk
17600#define GTZC_TZIC_SR1_USBFSF_Pos GTZC_CFGR1_USBFS_Pos
17601#define GTZC_TZIC_SR1_USBFSF_Msk GTZC_CFGR1_USBFS_Msk
17602#define GTZC_TZIC_SR1_FDCAN1F_Pos GTZC_CFGR1_FDCAN1_Pos
17603#define GTZC_TZIC_SR1_FDCAN1F_Msk GTZC_CFGR1_FDCAN1_Msk
17604#define GTZC_TZIC_SR1_LPTIM3F_Pos GTZC_CFGR1_LPTIM3_Pos
17605#define GTZC_TZIC_SR1_LPTIM3F_Msk GTZC_CFGR1_LPTIM3_Msk
17606#define GTZC_TZIC_SR1_LPTIM2F_Pos GTZC_CFGR1_LPTIM2_Pos
17607#define GTZC_TZIC_SR1_LPTIM2F_Msk GTZC_CFGR1_LPTIM2_Msk
17608#define GTZC_TZIC_SR1_I2C4F_Pos GTZC_CFGR1_I2C4_Pos
17609#define GTZC_TZIC_SR1_I2C4F_Msk GTZC_CFGR1_I2C4_Msk
17610#define GTZC_TZIC_SR1_LPUART1F_Pos GTZC_CFGR1_LPUART1_Pos
17611#define GTZC_TZIC_SR1_LPUART1F_Msk GTZC_CFGR1_LPUART1_Msk
17612#define GTZC_TZIC_SR1_LPTIM1F_Pos GTZC_CFGR1_LPTIM1_Pos
17613#define GTZC_TZIC_SR1_LPTIM1F_Msk GTZC_CFGR1_LPTIM1_Msk
17614#define GTZC_TZIC_SR1_OPAMPF_Pos GTZC_CFGR1_OPAMP_Pos
17615#define GTZC_TZIC_SR1_OPAMPF_Msk GTZC_CFGR1_OPAMP_Msk
17616#define GTZC_TZIC_SR1_DAC1F_Pos GTZC_CFGR1_DAC1_Pos
17617#define GTZC_TZIC_SR1_DAC1F_Msk GTZC_CFGR1_DAC1_Msk
17618#define GTZC_TZIC_SR1_CRSF_Pos GTZC_CFGR1_CRS_Pos
17619#define GTZC_TZIC_SR1_CRSF_Msk GTZC_CFGR1_CRS_Msk
17620#define GTZC_TZIC_SR1_I2C3F_Pos GTZC_CFGR1_I2C3_Pos
17621#define GTZC_TZIC_SR1_I2C3F_Msk GTZC_CFGR1_I2C3_Msk
17622#define GTZC_TZIC_SR1_I2C2F_Pos GTZC_CFGR1_I2C2_Pos
17623#define GTZC_TZIC_SR1_I2C2F_Msk GTZC_CFGR1_I2C2_Msk
17624#define GTZC_TZIC_SR1_I2C1F_Pos GTZC_CFGR1_I2C1_Pos
17625#define GTZC_TZIC_SR1_I2C1F_Msk GTZC_CFGR1_I2C1_Msk
17626#define GTZC_TZIC_SR1_UART5F_Pos GTZC_CFGR1_UART5_Pos
17627#define GTZC_TZIC_SR1_UART5F_Msk GTZC_CFGR1_UART5_Msk
17628#define GTZC_TZIC_SR1_UART4F_Pos GTZC_CFGR1_UART4_Pos
17629#define GTZC_TZIC_SR1_UART4F_Msk GTZC_CFGR1_UART4_Msk
17630#define GTZC_TZIC_SR1_USART3F_Pos GTZC_CFGR1_USART3_Pos
17631#define GTZC_TZIC_SR1_USART3F_Msk GTZC_CFGR1_USART3_Msk
17632#define GTZC_TZIC_SR1_USART2F_Pos GTZC_CFGR1_USART2_Pos
17633#define GTZC_TZIC_SR1_USART2F_Msk GTZC_CFGR1_USART2_Msk
17634#define GTZC_TZIC_SR1_SPI3F_Pos GTZC_CFGR1_SPI3_Pos
17635#define GTZC_TZIC_SR1_SPI3F_Msk GTZC_CFGR1_SPI3_Msk
17636#define GTZC_TZIC_SR1_SPI2F_Pos GTZC_CFGR1_SPI2_Pos
17637#define GTZC_TZIC_SR1_SPI2F_Msk GTZC_CFGR1_SPI2_Msk
17638#define GTZC_TZIC_SR1_IWDGF_Pos GTZC_CFGR1_IWDG_Pos
17639#define GTZC_TZIC_SR1_IWDGF_Msk GTZC_CFGR1_IWDG_Msk
17640#define GTZC_TZIC_SR1_WWDGF_Pos GTZC_CFGR1_WWDG_Pos
17641#define GTZC_TZIC_SR1_WWDGF_Msk GTZC_CFGR1_WWDG_Msk
17642#define GTZC_TZIC_SR1_TIM7F_Pos GTZC_CFGR1_TIM7_Pos
17643#define GTZC_TZIC_SR1_TIM7F_Msk GTZC_CFGR1_TIM7_Msk
17644#define GTZC_TZIC_SR1_TIM6F_Pos GTZC_CFGR1_TIM6_Pos
17645#define GTZC_TZIC_SR1_TIM6F_Msk GTZC_CFGR1_TIM6_Msk
17646#define GTZC_TZIC_SR1_TIM5F_Pos GTZC_CFGR1_TIM5_Pos
17647#define GTZC_TZIC_SR1_TIM5F_Msk GTZC_CFGR1_TIM5_Msk
17648#define GTZC_TZIC_SR1_TIM4F_Pos GTZC_CFGR1_TIM4_Pos
17649#define GTZC_TZIC_SR1_TIM4F_Msk GTZC_CFGR1_TIM4_Msk
17650#define GTZC_TZIC_SR1_TIM3F_Pos GTZC_CFGR1_TIM3_Pos
17651#define GTZC_TZIC_SR1_TIM3F_Msk GTZC_CFGR1_TIM3_Msk
17652#define GTZC_TZIC_SR1_TIM2F_Pos GTZC_CFGR1_TIM2_Pos
17653#define GTZC_TZIC_SR1_TIM2F_Msk GTZC_CFGR1_TIM2_Msk
17654
17655/******************* Bits definition for GTZC_TZIC_SR2 register **************/
17656#define GTZC_TZIC_SR2_OTFDEC1F_Pos GTZC_CFGR2_OTFDEC1_Pos
17657#define GTZC_TZIC_SR2_OTFDEC1F_Msk GTZC_CFGR2_OTFDEC1_Msk
17658#define GTZC_TZIC_SR2_EXTIF_Pos GTZC_CFGR2_EXTI_Pos
17659#define GTZC_TZIC_SR2_EXTIF_Msk GTZC_CFGR2_EXTI_Msk
17660#define GTZC_TZIC_SR2_FLASH_REGF_Pos GTZC_CFGR2_FLASH_REG_Pos
17661#define GTZC_TZIC_SR2_FLASH_REGF_Msk GTZC_CFGR2_FLASH_REG_Msk
17662#define GTZC_TZIC_SR2_FLASHF_Pos GTZC_CFGR2_FLASH_Pos
17663#define GTZC_TZIC_SR2_FLASHF_Msk GTZC_CFGR2_FLASH_Msk
17664#define GTZC_TZIC_SR2_RCCF_Pos GTZC_CFGR2_RCC_Pos
17665#define GTZC_TZIC_SR2_RCCF_Msk GTZC_CFGR2_RCC_Msk
17666#define GTZC_TZIC_SR2_DMAMUX1F_Pos GTZC_CFGR2_DMAMUX1_Pos
17667#define GTZC_TZIC_SR2_DMAMUX1F_Msk GTZC_CFGR2_DMAMUX1_Msk
17668#define GTZC_TZIC_SR2_DMA2F_Pos GTZC_CFGR2_DMA2_Pos
17669#define GTZC_TZIC_SR2_DMA2F_Msk GTZC_CFGR2_DMA2_Msk
17670#define GTZC_TZIC_SR2_DMA1F_Pos GTZC_CFGR2_DMA1_Pos
17671#define GTZC_TZIC_SR2_DMA1F_Msk GTZC_CFGR2_DMA1_Msk
17672#define GTZC_TZIC_SR2_SYSCFGF_Pos GTZC_CFGR2_SYSCFG_Pos
17673#define GTZC_TZIC_SR2_SYSCFGF_Msk GTZC_CFGR2_SYSCFG_Msk
17674#define GTZC_TZIC_SR2_PWRF_Pos GTZC_CFGR2_PWR_Pos
17675#define GTZC_TZIC_SR2_PWRF_Msk GTZC_CFGR2_PWR_Msk
17676#define GTZC_TZIC_SR2_RTCF_Pos GTZC_CFGR2_RTC_Pos
17677#define GTZC_TZIC_SR2_RTCF_Msk GTZC_CFGR2_RTC_Msk
17678#define GTZC_TZIC_SR2_OCTOSPI1_REGF_Pos GTZC_CFGR2_OCTOSPI1_REG_Pos
17679#define GTZC_TZIC_SR2_OCTOSPI1_REGF_Msk GTZC_CFGR2_OCTOSPI1_REG_Msk
17680#define GTZC_TZIC_SR2_FMC_REGF_Pos GTZC_CFGR2_FMC_REG_Pos
17681#define GTZC_TZIC_SR2_FMC_REGF_Msk GTZC_CFGR2_FMC_REG_Msk
17682#define GTZC_TZIC_SR2_SDMMC1F_Pos GTZC_CFGR2_SDMMC1_Pos
17683#define GTZC_TZIC_SR2_SDMMC1F_Msk GTZC_CFGR2_SDMMC1_Msk
17684#define GTZC_TZIC_SR2_PKAF_Pos GTZC_CFGR2_PKA_Pos
17685#define GTZC_TZIC_SR2_PKAF_Msk GTZC_CFGR2_PKA_Msk
17686#define GTZC_TZIC_SR2_RNGF_Pos GTZC_CFGR2_RNG_Pos
17687#define GTZC_TZIC_SR2_RNGF_Msk GTZC_CFGR2_RNG_Msk
17688#define GTZC_TZIC_SR2_HASHF_Pos GTZC_CFGR2_HASH_Pos
17689#define GTZC_TZIC_SR2_HASHF_Msk GTZC_CFGR2_HASH_Msk
17690#define GTZC_TZIC_SR2_AESF_Pos GTZC_CFGR2_AES_Pos
17691#define GTZC_TZIC_SR2_AESF_Msk GTZC_CFGR2_AES_Msk
17692#define GTZC_TZIC_SR2_ADCF_Pos GTZC_CFGR2_ADC_Pos
17693#define GTZC_TZIC_SR2_ADCF_Msk GTZC_CFGR2_ADC_Msk
17694#define GTZC_TZIC_SR2_ICACHE_REGF_Pos GTZC_CFGR2_ICACHE_REG_Pos
17695#define GTZC_TZIC_SR2_ICACHE_REGF_Msk GTZC_CFGR2_ICACHE_REG_Msk
17696#define GTZC_TZIC_SR2_TSCF_Pos GTZC_CFGR2_TSC_Pos
17697#define GTZC_TZIC_SR2_TSCF_Msk GTZC_CFGR2_TSC_Msk
17698#define GTZC_TZIC_SR2_CRCF_Pos GTZC_CFGR2_CRC_Pos
17699#define GTZC_TZIC_SR2_CRCF_Msk GTZC_CFGR2_CRC_Msk
17700#define GTZC_TZIC_SR2_DFSDM1F_Pos GTZC_CFGR2_DFSDM1_Pos
17701#define GTZC_TZIC_SR2_DFSDM1F_Msk GTZC_CFGR2_DFSDM1_Msk
17702#define GTZC_TZIC_SR2_SAI2F_Pos GTZC_CFGR2_SAI2_Pos
17703#define GTZC_TZIC_SR2_SAI2F_Msk GTZC_CFGR2_SAI2_Msk
17704#define GTZC_TZIC_SR2_SAI1F_Pos GTZC_CFGR2_SAI1_Pos
17705#define GTZC_TZIC_SR2_SAI1F_Msk GTZC_CFGR2_SAI1_Msk
17706#define GTZC_TZIC_SR2_TIM17F_Pos GTZC_CFGR2_TIM17_Pos
17707#define GTZC_TZIC_SR2_TIM17F_Msk GTZC_CFGR2_TIM17_Msk
17708#define GTZC_TZIC_SR2_TIM16F_Pos GTZC_CFGR2_TIM16_Pos
17709#define GTZC_TZIC_SR2_TIM16F_Msk GTZC_CFGR2_TIM16_Msk
17710#define GTZC_TZIC_SR2_TIM15F_Pos GTZC_CFGR2_TIM15_Pos
17711#define GTZC_TZIC_SR2_TIM15F_Msk GTZC_CFGR2_TIM15_Msk
17712#define GTZC_TZIC_SR2_USART1F_Pos GTZC_CFGR2_USART1_Pos
17713#define GTZC_TZIC_SR2_USART1F_Msk GTZC_CFGR2_USART1_Msk
17714#define GTZC_TZIC_SR2_TIM8F_Pos GTZC_CFGR2_TIM8_Pos
17715#define GTZC_TZIC_SR2_TIM8F_Msk GTZC_CFGR2_TIM8_Msk
17716
17717/******************* Bits definition for GTZC_TZIC_SR3 register **************/
17718#define GTZC_TZIC_SR3_MPCBB2_REGF_Pos GTZC_CFGR3_MPCBB2_REG_Pos
17719#define GTZC_TZIC_SR3_MPCBB2_REGF_Msk GTZC_CFGR3_MPCBB2_REG_Msk
17720#define GTZC_TZIC_SR3_SRAM2F_Pos GTZC_CFGR3_SRAM2_Pos
17721#define GTZC_TZIC_SR3_SRAM2F_Msk GTZC_CFGR3_SRAM2_Msk
17722#define GTZC_TZIC_SR3_MPCBB1_REGF_Pos GTZC_CFGR3_MPCBB1_REG_Pos
17723#define GTZC_TZIC_SR3_MPCBB1_REGF_Msk GTZC_CFGR3_MPCBB1_REG_Msk
17724#define GTZC_TZIC_SR3_SRAM1F_Pos GTZC_CFGR3_SRAM1_Pos
17725#define GTZC_TZIC_SR3_SRAM1F_Msk GTZC_CFGR3_SRAM1_Msk
17726#define GTZC_TZIC_SR3_OCTOSPI1_MEMF_Pos GTZC_CFGR3_OCTOSPI1_MEM_Pos
17727#define GTZC_TZIC_SR3_OCTOSPI1_MEMF_Msk GTZC_CFGR3_OCTOSPI1_MEM_Msk
17728#define GTZC_TZIC_SR3_FMC_MEMF_Pos GTZC_CFGR3_FMC_MEM_Pos
17729#define GTZC_TZIC_SR3_FMC_MEMF_Msk GTZC_CFGR3_FMC_MEM_Msk
17730#define GTZC_TZIC_SR3_TZICF_Pos GTZC_CFGR3_TZIC_Pos
17731#define GTZC_TZIC_SR3_TZICF_Msk GTZC_CFGR3_TZIC_Msk
17732#define GTZC_TZIC_SR3_TZSCF_Pos GTZC_CFGR3_TZSC_Pos
17733#define GTZC_TZIC_SR3_TZSCF_Msk GTZC_CFGR3_TZSC_Msk
17734
17735/****************** Bits definition for GTZC_TZIC_FCR1 register ****************/
17736#define GTZC_TZIC_FCR1_SPI1FC_Pos GTZC_CFGR1_SPI1_Pos
17737#define GTZC_TZIC_FCR1_SPI1FC_Msk GTZC_CFGR1_SPI1_Msk
17738#define GTZC_TZIC_FCR1_TIM1FC_Pos GTZC_CFGR1_TIM1_Pos
17739#define GTZC_TZIC_FCR1_TIM1FC_Msk GTZC_CFGR1_TIM1_Msk
17740#define GTZC_TZIC_FCR1_COMPFC_Pos GTZC_CFGR1_COMP_Pos
17741#define GTZC_TZIC_FCR1_COMPFC_Msk GTZC_CFGR1_COMP_Msk
17742#define GTZC_TZIC_FCR1_VREFBUFFC_Pos GTZC_CFGR1_VREFBUF_Pos
17743#define GTZC_TZIC_FCR1_VREFBUFFC_Msk GTZC_CFGR1_VREFBUF_Msk
17744#define GTZC_TZIC_FCR1_UCPD1FC_Pos GTZC_CFGR1_UCPD1_Pos
17745#define GTZC_TZIC_FCR1_UCPD1FC_Msk GTZC_CFGR1_UCPD1_Msk
17746#define GTZC_TZIC_FCR1_USBFSFC_Pos GTZC_CFGR1_USBFS_Pos
17747#define GTZC_TZIC_FCR1_USBFSFC_Msk GTZC_CFGR1_USBFS_Msk
17748#define GTZC_TZIC_FCR1_FDCAN1FC_Pos GTZC_CFGR1_FDCAN1_Pos
17749#define GTZC_TZIC_FCR1_FDCAN1FC_Msk GTZC_CFGR1_FDCAN1_Msk
17750#define GTZC_TZIC_FCR1_LPTIM3FC_Pos GTZC_CFGR1_LPTIM3_Pos
17751#define GTZC_TZIC_FCR1_LPTIM3FC_Msk GTZC_CFGR1_LPTIM3_Msk
17752#define GTZC_TZIC_FCR1_LPTIM2FC_Pos GTZC_CFGR1_LPTIM2_Pos
17753#define GTZC_TZIC_FCR1_LPTIM2FC_Msk GTZC_CFGR1_LPTIM2_Msk
17754#define GTZC_TZIC_FCR1_I2C4FC_Pos GTZC_CFGR1_I2C4_Pos
17755#define GTZC_TZIC_FCR1_I2C4FC_Msk GTZC_CFGR1_I2C4_Msk
17756#define GTZC_TZIC_FCR1_LPUART1FC_Pos GTZC_CFGR1_LPUART1_Pos
17757#define GTZC_TZIC_FCR1_LPUART1FC_Msk GTZC_CFGR1_LPUART1_Msk
17758#define GTZC_TZIC_FCR1_LPTIM1FC_Pos GTZC_CFGR1_LPTIM1_Pos
17759#define GTZC_TZIC_FCR1_LPTIM1FC_Msk GTZC_CFGR1_LPTIM1_Msk
17760#define GTZC_TZIC_FCR1_OPAMPFC_Pos GTZC_CFGR1_OPAMP_Pos
17761#define GTZC_TZIC_FCR1_OPAMPFC_Msk GTZC_CFGR1_OPAMP_Msk
17762#define GTZC_TZIC_FCR1_DAC1FC_Pos GTZC_CFGR1_DAC1_Pos
17763#define GTZC_TZIC_FCR1_DAC1FC_Msk GTZC_CFGR1_DAC1_Msk
17764#define GTZC_TZIC_FCR1_CRSFC_Pos GTZC_CFGR1_CRS_Pos
17765#define GTZC_TZIC_FCR1_CRSFC_Msk GTZC_CFGR1_CRS_Msk
17766#define GTZC_TZIC_FCR1_I2C3FC_Pos GTZC_CFGR1_I2C3_Pos
17767#define GTZC_TZIC_FCR1_I2C3FC_Msk GTZC_CFGR1_I2C3_Msk
17768#define GTZC_TZIC_FCR1_I2C2FC_Pos GTZC_CFGR1_I2C2_Pos
17769#define GTZC_TZIC_FCR1_I2C2FC_Msk GTZC_CFGR1_I2C2_Msk
17770#define GTZC_TZIC_FCR1_I2C1FC_Pos GTZC_CFGR1_I2C1_Pos
17771#define GTZC_TZIC_FCR1_I2C1FC_Msk GTZC_CFGR1_I2C1_Msk
17772#define GTZC_TZIC_FCR1_UART5FC_Pos GTZC_CFGR1_UART5_Pos
17773#define GTZC_TZIC_FCR1_UART5FC_Msk GTZC_CFGR1_UART5_Msk
17774#define GTZC_TZIC_FCR1_UART4FC_Pos GTZC_CFGR1_UART4_Pos
17775#define GTZC_TZIC_FCR1_UART4FC_Msk GTZC_CFGR1_UART4_Msk
17776#define GTZC_TZIC_FCR1_USART3FC_Pos GTZC_CFGR1_USART3_Pos
17777#define GTZC_TZIC_FCR1_USART3FC_Msk GTZC_CFGR1_USART3_Msk
17778#define GTZC_TZIC_FCR1_USART2FC_Pos GTZC_CFGR1_USART2_Pos
17779#define GTZC_TZIC_FCR1_USART2FC_Msk GTZC_CFGR1_USART2_Msk
17780#define GTZC_TZIC_FCR1_SPI3FC_Pos GTZC_CFGR1_SPI3_Pos
17781#define GTZC_TZIC_FCR1_SPI3FC_Msk GTZC_CFGR1_SPI3_Msk
17782#define GTZC_TZIC_FCR1_SPI2FC_Pos GTZC_CFGR1_SPI2_Pos
17783#define GTZC_TZIC_FCR1_SPI2FC_Msk GTZC_CFGR1_SPI2_Msk
17784#define GTZC_TZIC_FCR1_IWDGFC_Pos GTZC_CFGR1_IWDG_Pos
17785#define GTZC_TZIC_FCR1_IWDGFC_Msk GTZC_CFGR1_IWDG_Msk
17786#define GTZC_TZIC_FCR1_WWDGFC_Pos GTZC_CFGR1_WWDG_Pos
17787#define GTZC_TZIC_FCR1_WWDGFC_Msk GTZC_CFGR1_WWDG_Msk
17788#define GTZC_TZIC_FCR1_TIM7FC_Pos GTZC_CFGR1_TIM7_Pos
17789#define GTZC_TZIC_FCR1_TIM7FC_Msk GTZC_CFGR1_TIM7_Msk
17790#define GTZC_TZIC_FCR1_TIM6FC_Pos GTZC_CFGR1_TIM6_Pos
17791#define GTZC_TZIC_FCR1_TIM6FC_Msk GTZC_CFGR1_TIM6_Msk
17792#define GTZC_TZIC_FCR1_TIM5FC_Pos GTZC_CFGR1_TIM5_Pos
17793#define GTZC_TZIC_FCR1_TIM5FC_Msk GTZC_CFGR1_TIM5_Msk
17794#define GTZC_TZIC_FCR1_TIM4FC_Pos GTZC_CFGR1_TIM4_Pos
17795#define GTZC_TZIC_FCR1_TIM4FC_Msk GTZC_CFGR1_TIM4_Msk
17796#define GTZC_TZIC_FCR1_TIM3FC_Pos GTZC_CFGR1_TIM3_Pos
17797#define GTZC_TZIC_FCR1_TIM3FC_Msk GTZC_CFGR1_TIM3_Msk
17798#define GTZC_TZIC_FCR1_TIM2FC_Pos GTZC_CFGR1_TIM2_Pos
17799#define GTZC_TZIC_FCR1_TIM2FC_Msk GTZC_CFGR1_TIM2_Msk
17800
17801/****************** Bits definition for GTZC_TZIC_FCR2 register ****************/
17802#define GTZC_TZIC_FCR2_OTFDEC1FC_Pos GTZC_CFGR2_OTFDEC1_Pos
17803#define GTZC_TZIC_FCR2_OTFDEC1FC_Msk GTZC_CFGR2_OTFDEC1_Msk
17804#define GTZC_TZIC_FCR2_EXTIFC_Pos GTZC_CFGR2_EXTI_Pos
17805#define GTZC_TZIC_FCR2_EXTIFC_Msk GTZC_CFGR2_EXTI_Msk
17806#define GTZC_TZIC_FCR2_FLASH_REGFC_Pos GTZC_CFGR2_FLASH_REG_Pos
17807#define GTZC_TZIC_FCR2_FLASH_REGFC_Msk GTZC_CFGR2_FLASH_REG_Msk
17808#define GTZC_TZIC_FCR2_FLASHFC_Pos GTZC_CFGR2_FLASH_Pos
17809#define GTZC_TZIC_FCR2_FLASHFC_Msk GTZC_CFGR2_FLASH_Msk
17810#define GTZC_TZIC_FCR2_RCCFC_Pos GTZC_CFGR2_RCC_Pos
17811#define GTZC_TZIC_FCR2_RCCFC_Msk GTZC_CFGR2_RCC_Msk
17812#define GTZC_TZIC_FCR2_DMAMUX1FC_Pos GTZC_CFGR2_DMAMUX1_Pos
17813#define GTZC_TZIC_FCR2_DMAMUX1FC_Msk GTZC_CFGR2_DMAMUX1_Msk
17814#define GTZC_TZIC_FCR2_DMA2FC_Pos GTZC_CFGR2_DMA2_Pos
17815#define GTZC_TZIC_FCR2_DMA2FC_Msk GTZC_CFGR2_DMA2_Msk
17816#define GTZC_TZIC_FCR2_DMA1FC_Pos GTZC_CFGR2_DMA1_Pos
17817#define GTZC_TZIC_FCR2_DMA1FC_Msk GTZC_CFGR2_DMA1_Msk
17818#define GTZC_TZIC_FCR2_SYSCFGFC_Pos GTZC_CFGR2_SYSCFG_Pos
17819#define GTZC_TZIC_FCR2_SYSCFGFC_Msk GTZC_CFGR2_SYSCFG_Msk
17820#define GTZC_TZIC_FCR2_PWRFC_Pos GTZC_CFGR2_PWR_Pos
17821#define GTZC_TZIC_FCR2_PWRFC_Msk GTZC_CFGR2_PWR_Msk
17822#define GTZC_TZIC_FCR2_RTCFC_Pos GTZC_CFGR2_RTC_Pos
17823#define GTZC_TZIC_FCR2_RTCFC_Msk GTZC_CFGR2_RTC_Msk
17824#define GTZC_TZIC_FCR2_OCTOSPI1_REGFC_Pos GTZC_CFGR2_OCTOSPI1_REG_Pos
17825#define GTZC_TZIC_FCR2_OCTOSPI1_REGFC_Msk GTZC_CFGR2_OCTOSPI1_REG_Msk
17826#define GTZC_TZIC_FCR2_FMC_REGFC_Pos GTZC_CFGR2_FMC_REG_Pos
17827#define GTZC_TZIC_FCR2_FMC_REGFC_Msk GTZC_CFGR2_FMC_REG_Msk
17828#define GTZC_TZIC_FCR2_SDMMC1FC_Pos GTZC_CFGR2_SDMMC1_Pos
17829#define GTZC_TZIC_FCR2_SDMMC1FC_Msk GTZC_CFGR2_SDMMC1_Msk
17830#define GTZC_TZIC_FCR2_PKAFC_Pos GTZC_CFGR2_PKA_Pos
17831#define GTZC_TZIC_FCR2_PKAFC_Msk GTZC_CFGR2_PKA_Msk
17832#define GTZC_TZIC_FCR2_RNGFC_Pos GTZC_CFGR2_RNG_Pos
17833#define GTZC_TZIC_FCR2_RNGFC_Msk GTZC_CFGR2_RNG_Msk
17834#define GTZC_TZIC_FCR2_HASHFC_Pos GTZC_CFGR2_HASH_Pos
17835#define GTZC_TZIC_FCR2_HASHFC_Msk GTZC_CFGR2_HASH_Msk
17836#define GTZC_TZIC_FCR2_AESFC_Pos GTZC_CFGR2_AES_Pos
17837#define GTZC_TZIC_FCR2_AESFC_Msk GTZC_CFGR2_AES_Msk
17838#define GTZC_TZIC_FCR2_ADCFC_Pos GTZC_CFGR2_ADC_Pos
17839#define GTZC_TZIC_FCR2_ADCFC_Msk GTZC_CFGR2_ADC_Msk
17840#define GTZC_TZIC_FCR2_ICACHE_REGFC_Pos GTZC_CFGR2_ICACHE_REG_Pos
17841#define GTZC_TZIC_FCR2_ICACHE_REGFC_Msk GTZC_CFGR2_ICACHE_REG_Msk
17842#define GTZC_TZIC_FCR2_TSCFC_Pos GTZC_CFGR2_TSC_Pos
17843#define GTZC_TZIC_FCR2_TSCFC_Msk GTZC_CFGR2_TSC_Msk
17844#define GTZC_TZIC_FCR2_CRCFC_Pos GTZC_CFGR2_CRC_Pos
17845#define GTZC_TZIC_FCR2_CRCFC_Msk GTZC_CFGR2_CRC_Msk
17846#define GTZC_TZIC_FCR2_DFSDM1FC_Pos GTZC_CFGR2_DFSDM1_Pos
17847#define GTZC_TZIC_FCR2_DFSDM1FC_Msk GTZC_CFGR2_DFSDM1_Msk
17848#define GTZC_TZIC_FCR2_SAI2FC_Pos GTZC_CFGR2_SAI2_Pos
17849#define GTZC_TZIC_FCR2_SAI2FC_Msk GTZC_CFGR2_SAI2_Msk
17850#define GTZC_TZIC_FCR2_SAI1FC_Pos GTZC_CFGR2_SAI1_Pos
17851#define GTZC_TZIC_FCR2_SAI1FC_Msk GTZC_CFGR2_SAI1_Msk
17852#define GTZC_TZIC_FCR2_TIM17FC_Pos GTZC_CFGR2_TIM17_Pos
17853#define GTZC_TZIC_FCR2_TIM17FC_Msk GTZC_CFGR2_TIM17_Msk
17854#define GTZC_TZIC_FCR2_TIM16FC_Pos GTZC_CFGR2_TIM16_Pos
17855#define GTZC_TZIC_FCR2_TIM16FC_Msk GTZC_CFGR2_TIM16_Msk
17856#define GTZC_TZIC_FCR2_TIM15FC_Pos GTZC_CFGR2_TIM15_Pos
17857#define GTZC_TZIC_FCR2_TIM15FC_Msk GTZC_CFGR2_TIM15_Msk
17858#define GTZC_TZIC_FCR2_USART1FC_Pos GTZC_CFGR2_USART1_Pos
17859#define GTZC_TZIC_FCR2_USART1FC_Msk GTZC_CFGR2_USART1_Msk
17860#define GTZC_TZIC_FCR2_TIM8FC_Pos GTZC_CFGR2_TIM8_Pos
17861#define GTZC_TZIC_FCR2_TIM8FC_Msk GTZC_CFGR2_TIM8_Msk
17862
17863/****************** Bits definition for GTZC_TZIC_FCR3 register ****************/
17864#define GTZC_TZIC_FCR3_MPCBB2_REGFC_Pos GTZC_CFGR3_MPCBB2_REG_Pos
17865#define GTZC_TZIC_FCR3_MPCBB2_REGFC_Msk GTZC_CFGR3_MPCBB2_REG_Msk
17866#define GTZC_TZIC_FCR3_MPCBB2FC_Pos GTZC_CFGR3_SRAM2_Pos
17867#define GTZC_TZIC_FCR3_MPCBB2FC_Msk GTZC_CFGR3_SRAM2_Msk
17868#define GTZC_TZIC_FCR3_MPCBB1_REGFC_Pos GTZC_CFGR3_MPCBB1_REG_Pos
17869#define GTZC_TZIC_FCR3_MPCBB1_REGFC_Msk GTZC_CFGR3_MPCBB1_REG_Msk
17870#define GTZC_TZIC_FCR3_MPCBB1FC_Pos GTZC_CFGR3_SRAM1_Pos
17871#define GTZC_TZIC_FCR3_MPCBB1FC_Msk GTZC_CFGR3_MPCBB1_Msk
17872#define GTZC_TZIC_FCR3_OCTOSPI1_MEMFC_Pos GTZC_CFGR3_OCTOSPI1_MEM_Pos
17873#define GTZC_TZIC_FCR3_OCTOSPI1_MEMFC_Msk GTZC_CFGR3_OCTOSPI1_MEM_Msk
17874#define GTZC_TZIC_FCR3_FMC_MEMFC_Pos GTZC_CFGR3_FMC_MEM_Pos
17875#define GTZC_TZIC_FCR3_FMC_MEMFC_Msk GTZC_CFGR3_FMC_MEM_Msk
17876#define GTZC_TZIC_FCR3_TZICFC_Pos GTZC_CFGR3_TZIC_Pos
17877#define GTZC_TZIC_FCR3_TZICFC_Msk GTZC_CFGR3_TZIC_Msk
17878#define GTZC_TZIC_FCR3_TZSCFC_Pos GTZC_CFGR3_TZSC_Pos
17879#define GTZC_TZIC_FCR3_TZSCFC_Msk GTZC_CFGR3_TZSC_Msk
17880
17881/******************* Bits definition for GTZC_MPCBB_CR register *****************/
17882#define GTZC_MPCBB_CR_LCK_Pos (0U)
17883#define GTZC_MPCBB_CR_LCK_Msk (0x01UL << GTZC_MPCBB_CR_LCK_Pos) /*!< 0x00000001 */
17884#define GTZC_MPCBB_CR_INVSECSTATE_Pos (30U)
17885#define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */
17886#define GTZC_MPCBB_CR_SRWILADIS_Pos (31U)
17887#define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */
17888
17889/******************* Bits definition for GTZC_MPCBB_LCKVTR1 register ************/
17890#define GTZC_MPCBB_LCKVTR1_LCKSB0_Pos (0U)
17891#define GTZC_MPCBB_LCKVTR1_LCKSB0_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB0_Pos) /*!< 0x00000001 */
17892#define GTZC_MPCBB_LCKVTR1_LCKSB1_Pos (1U)
17893#define GTZC_MPCBB_LCKVTR1_LCKSB1_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB1_Pos) /*!< 0x00000002 */
17894#define GTZC_MPCBB_LCKVTR1_LCKSB2_Pos (2U)
17895#define GTZC_MPCBB_LCKVTR1_LCKSB2_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB2_Pos) /*!< 0x00000004 */
17896#define GTZC_MPCBB_LCKVTR1_LCKSB3_Pos (3U)
17897#define GTZC_MPCBB_LCKVTR1_LCKSB3_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB3_Pos) /*!< 0x00000008 */
17898#define GTZC_MPCBB_LCKVTR1_LCKSB4_Pos (4U)
17899#define GTZC_MPCBB_LCKVTR1_LCKSB4_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB4_Pos) /*!< 0x00000010 */
17900#define GTZC_MPCBB_LCKVTR1_LCKSB5_Pos (5U)
17901#define GTZC_MPCBB_LCKVTR1_LCKSB5_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB5_Pos) /*!< 0x00000020 */
17902#define GTZC_MPCBB_LCKVTR1_LCKSB6_Pos (6U)
17903#define GTZC_MPCBB_LCKVTR1_LCKSB6_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB6_Pos) /*!< 0x00000040 */
17904#define GTZC_MPCBB_LCKVTR1_LCKSB7_Pos (7U)
17905#define GTZC_MPCBB_LCKVTR1_LCKSB7_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB7_Pos) /*!< 0x00000080 */
17906#define GTZC_MPCBB_LCKVTR1_LCKSB8_Pos (8U)
17907#define GTZC_MPCBB_LCKVTR1_LCKSB8_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB8_Pos) /*!< 0x00000100 */
17908#define GTZC_MPCBB_LCKVTR1_LCKSB9_Pos (9U)
17909#define GTZC_MPCBB_LCKVTR1_LCKSB9_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB9_Pos) /*!< 0x00000200 */
17910#define GTZC_MPCBB_LCKVTR1_LCKSB10_Pos (10U)
17911#define GTZC_MPCBB_LCKVTR1_LCKSB10_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB10_Pos) /*!< 0x00000400 */
17912#define GTZC_MPCBB_LCKVTR1_LCKSB11_Pos (11U)
17913#define GTZC_MPCBB_LCKVTR1_LCKSB11_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB11_Pos) /*!< 0x00000800 */
17914#define GTZC_MPCBB_LCKVTR1_LCKSB12_Pos (12U)
17915#define GTZC_MPCBB_LCKVTR1_LCKSB12_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB12_Pos) /*!< 0x00001000 */
17916#define GTZC_MPCBB_LCKVTR1_LCKSB13_Pos (13U)
17917#define GTZC_MPCBB_LCKVTR1_LCKSB13_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB13_Pos) /*!< 0x00002000 */
17918#define GTZC_MPCBB_LCKVTR1_LCKSB14_Pos (14U)
17919#define GTZC_MPCBB_LCKVTR1_LCKSB14_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB14_Pos) /*!< 0x00004000 */
17920#define GTZC_MPCBB_LCKVTR1_LCKSB15_Pos (15U)
17921#define GTZC_MPCBB_LCKVTR1_LCKSB15_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB15_Pos) /*!< 0x00008000 */
17922#define GTZC_MPCBB_LCKVTR1_LCKSB16_Pos (16U)
17923#define GTZC_MPCBB_LCKVTR1_LCKSB16_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB16_Pos) /*!< 0x00010000 */
17924#define GTZC_MPCBB_LCKVTR1_LCKSB17_Pos (17U)
17925#define GTZC_MPCBB_LCKVTR1_LCKSB17_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB17_Pos) /*!< 0x00020000 */
17926#define GTZC_MPCBB_LCKVTR1_LCKSB18_Pos (18U)
17927#define GTZC_MPCBB_LCKVTR1_LCKSB18_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB18_Pos) /*!< 0x00040000 */
17928#define GTZC_MPCBB_LCKVTR1_LCKSB19_Pos (19U)
17929#define GTZC_MPCBB_LCKVTR1_LCKSB19_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB19_Pos) /*!< 0x00080000 */
17930#define GTZC_MPCBB_LCKVTR1_LCKSB20_Pos (20U)
17931#define GTZC_MPCBB_LCKVTR1_LCKSB20_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB20_Pos) /*!< 0x00100000 */
17932#define GTZC_MPCBB_LCKVTR1_LCKSB21_Pos (21U)
17933#define GTZC_MPCBB_LCKVTR1_LCKSB21_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB21_Pos) /*!< 0x00200000 */
17934#define GTZC_MPCBB_LCKVTR1_LCKSB22_Pos (22U)
17935#define GTZC_MPCBB_LCKVTR1_LCKSB22_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB22_Pos) /*!< 0x00400000 */
17936#define GTZC_MPCBB_LCKVTR1_LCKSB23_Pos (23U)
17937#define GTZC_MPCBB_LCKVTR1_LCKSB23_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB23_Pos) /*!< 0x00800000 */
17938#define GTZC_MPCBB_LCKVTR1_LCKSB24_Pos (24U)
17939#define GTZC_MPCBB_LCKVTR1_LCKSB24_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB24_Pos) /*!< 0x01000000 */
17940#define GTZC_MPCBB_LCKVTR1_LCKSB25_Pos (25U)
17941#define GTZC_MPCBB_LCKVTR1_LCKSB25_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB25_Pos) /*!< 0x02000000 */
17942#define GTZC_MPCBB_LCKVTR1_LCKSB26_Pos (26U)
17943#define GTZC_MPCBB_LCKVTR1_LCKSB26_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB26_Pos) /*!< 0x04000000 */
17944#define GTZC_MPCBB_LCKVTR1_LCKSB27_Pos (27U)
17945#define GTZC_MPCBB_LCKVTR1_LCKSB27_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB27_Pos) /*!< 0x08000000 */
17946#define GTZC_MPCBB_LCKVTR1_LCKSB28_Pos (28U)
17947#define GTZC_MPCBB_LCKVTR1_LCKSB28_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB28_Pos) /*!< 0x10000000 */
17948#define GTZC_MPCBB_LCKVTR1_LCKSB29_Pos (29U)
17949#define GTZC_MPCBB_LCKVTR1_LCKSB29_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB29_Pos) /*!< 0x20000000 */
17950#define GTZC_MPCBB_LCKVTR1_LCKSB30_Pos (30U)
17951#define GTZC_MPCBB_LCKVTR1_LCKSB30_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB30_Pos) /*!< 0x40000000 */
17952#define GTZC_MPCBB_LCKVTR1_LCKSB31_Pos (31U)
17953#define GTZC_MPCBB_LCKVTR1_LCKSB31_Msk (0x01UL << GTZC_MPCBB_LCKVTR1_LCKSB31_Pos) /*!< 0x80000000 */
17954
17955/******************* Bits definition for GTZC_MPCBB_LCKVTR2 register ************/
17956#define GTZC_MPCBB_LCKVTR2_LCKSB32_Pos (0U)
17957#define GTZC_MPCBB_LCKVTR2_LCKSB32_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB32_Msk) /*!< 0x00000001 */
17958#define GTZC_MPCBB_LCKVTR2_LCKSB33_Pos (1U)
17959#define GTZC_MPCBB_LCKVTR2_LCKSB33_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB33_Pos) /*!< 0x00000002 */
17960#define GTZC_MPCBB_LCKVTR2_LCKSB34_Pos (2U)
17961#define GTZC_MPCBB_LCKVTR2_LCKSB34_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB34_Pos) /*!< 0x00000004 */
17962#define GTZC_MPCBB_LCKVTR2_LCKSB35_Pos (3U)
17963#define GTZC_MPCBB_LCKVTR2_LCKSB35_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB35_Pos) /*!< 0x00000008 */
17964#define GTZC_MPCBB_LCKVTR2_LCKSB36_Pos (4U)
17965#define GTZC_MPCBB_LCKVTR2_LCKSB36_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB36_Pos) /*!< 0x00000010 */
17966#define GTZC_MPCBB_LCKVTR2_LCKSB37_Pos (5U)
17967#define GTZC_MPCBB_LCKVTR2_LCKSB37_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB37_Pos) /*!< 0x00000020 */
17968#define GTZC_MPCBB_LCKVTR2_LCKSB38_Pos (6U)
17969#define GTZC_MPCBB_LCKVTR2_LCKSB38_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB38_Pos) /*!< 0x00000040 */
17970#define GTZC_MPCBB_LCKVTR2_LCKSB39_Pos (7U)
17971#define GTZC_MPCBB_LCKVTR2_LCKSB39_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB39_Pos) /*!< 0x00000080 */
17972#define GTZC_MPCBB_LCKVTR2_LCKSB40_Pos (8U)
17973#define GTZC_MPCBB_LCKVTR2_LCKSB40_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB40_Pos) /*!< 0x00000100 */
17974#define GTZC_MPCBB_LCKVTR2_LCKSB41_Pos (9U)
17975#define GTZC_MPCBB_LCKVTR2_LCKSB41_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB41_Pos) /*!< 0x00000200 */
17976#define GTZC_MPCBB_LCKVTR2_LCKSB42_Pos (10U)
17977#define GTZC_MPCBB_LCKVTR2_LCKSB42_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB42_Pos) /*!< 0x00000400 */
17978#define GTZC_MPCBB_LCKVTR2_LCKSB43_Pos (11U)
17979#define GTZC_MPCBB_LCKVTR2_LCKSB43_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB43_Pos) /*!< 0x00000800 */
17980#define GTZC_MPCBB_LCKVTR2_LCKSB44_Pos (12U)
17981#define GTZC_MPCBB_LCKVTR2_LCKSB44_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB44_Pos) /*!< 0x00001000 */
17982#define GTZC_MPCBB_LCKVTR2_LCKSB45_Pos (13U)
17983#define GTZC_MPCBB_LCKVTR2_LCKSB45_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB45_Pos) /*!< 0x00002000 */
17984#define GTZC_MPCBB_LCKVTR2_LCKSB46_Pos (14U)
17985#define GTZC_MPCBB_LCKVTR2_LCKSB46_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB46_Pos) /*!< 0x00004000 */
17986#define GTZC_MPCBB_LCKVTR2_LCKSB47_Pos (15U)
17987#define GTZC_MPCBB_LCKVTR2_LCKSB47_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB47_Pos) /*!< 0x00008000 */
17988#define GTZC_MPCBB_LCKVTR2_LCKSB48_Pos (16U)
17989#define GTZC_MPCBB_LCKVTR2_LCKSB48_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB48_Pos) /*!< 0x00010000 */
17990#define GTZC_MPCBB_LCKVTR2_LCKSB49_Pos (17U)
17991#define GTZC_MPCBB_LCKVTR2_LCKSB49_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB49_Pos) /*!< 0x00020000 */
17992#define GTZC_MPCBB_LCKVTR2_LCKSB50_Pos (18U)
17993#define GTZC_MPCBB_LCKVTR2_LCKSB50_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB50_Pos) /*!< 0x00040000 */
17994#define GTZC_MPCBB_LCKVTR2_LCKSB51_Pos (19U)
17995#define GTZC_MPCBB_LCKVTR2_LCKSB51_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB51_Pos) /*!< 0x00080000 */
17996#define GTZC_MPCBB_LCKVTR2_LCKSB52_Pos (20U)
17997#define GTZC_MPCBB_LCKVTR2_LCKSB52_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB52_Pos) /*!< 0x00100000 */
17998#define GTZC_MPCBB_LCKVTR2_LCKSB53_Pos (21U)
17999#define GTZC_MPCBB_LCKVTR2_LCKSB53_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB53_Pos) /*!< 0x00200000 */
18000#define GTZC_MPCBB_LCKVTR2_LCKSB54_Pos (22U)
18001#define GTZC_MPCBB_LCKVTR2_LCKSB54_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB54_Pos) /*!< 0x00400000 */
18002#define GTZC_MPCBB_LCKVTR2_LCKSB55_Pos (23U)
18003#define GTZC_MPCBB_LCKVTR2_LCKSB55_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB55_Pos) /*!< 0x00800000 */
18004#define GTZC_MPCBB_LCKVTR2_LCKSB56_Pos (24U)
18005#define GTZC_MPCBB_LCKVTR2_LCKSB56_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB56_Pos) /*!< 0x01000000 */
18006#define GTZC_MPCBB_LCKVTR2_LCKSB57_Pos (25U)
18007#define GTZC_MPCBB_LCKVTR2_LCKSB57_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB57_Pos) /*!< 0x02000000 */
18008#define GTZC_MPCBB_LCKVTR2_LCKSB58_Pos (26U)
18009#define GTZC_MPCBB_LCKVTR2_LCKSB58_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB58_Pos) /*!< 0x04000000 */
18010#define GTZC_MPCBB_LCKVTR2_LCKSB59_Pos (27U)
18011#define GTZC_MPCBB_LCKVTR2_LCKSB59_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB59_Pos) /*!< 0x08000000 */
18012#define GTZC_MPCBB_LCKVTR2_LCKSB60_Pos (28U)
18013#define GTZC_MPCBB_LCKVTR2_LCKSB60_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB60_Pos) /*!< 0x10000000 */
18014#define GTZC_MPCBB_LCKVTR2_LCKSB61_Pos (29U)
18015#define GTZC_MPCBB_LCKVTR2_LCKSB61_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB61_Pos) /*!< 0x20000000 */
18016#define GTZC_MPCBB_LCKVTR2_LCKSB62_Pos (30U)
18017#define GTZC_MPCBB_LCKVTR2_LCKSB62_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB62_Pos) /*!< 0x40000000 */
18018#define GTZC_MPCBB_LCKVTR2_LCKSB63_Pos (31U)
18019#define GTZC_MPCBB_LCKVTR2_LCKSB63_Msk (0x01UL << GTZC_MPCBB_LCKVTR2_LCKSB63_Pos) /*!< 0x80000000 */
18020
18021/******************************************************************************/
18022/* */
18023/* SDMMC Interface */
18024/* */
18025/******************************************************************************/
18026/****************** Bit definition for SDMMC_POWER register ******************/
18027#define SDMMC_POWER_PWRCTRL_Pos (0U)
18028#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
18029#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
18030#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
18031#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
18032#define SDMMC_POWER_VSWITCH_Pos (2U)
18033#define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */
18034#define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Pos /*!<Voltage switch sequence start */
18035#define SDMMC_POWER_VSWITCHEN_Pos (3U)
18036#define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */
18037#define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Pos /*!<Voltage switch procedure enable */
18038#define SDMMC_POWER_DIRPOL_Pos (4U)
18039#define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */
18040#define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Pos /*!<Data and Command direction signals polarity selection */
18041
18042/****************** Bit definition for SDMMC_CLKCR register ******************/
18043#define SDMMC_CLKCR_CLKDIV_Pos (0U)
18044#define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */
18045#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
18046#define SDMMC_CLKCR_PWRSAV_Pos (12U)
18047#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */
18048#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
18049
18050#define SDMMC_CLKCR_WIDBUS_Pos (14U)
18051#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */
18052#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
18053#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00000800 */
18054#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001000 */
18055
18056#define SDMMC_CLKCR_NEGEDGE_Pos (16U)
18057#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */
18058#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
18059#define SDMMC_CLKCR_HWFC_EN_Pos (17U)
18060#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */
18061#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
18062#define SDMMC_CLKCR_DDR_Pos (18U)
18063#define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
18064#define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */
18065#define SDMMC_CLKCR_BUSSPEED_Pos (19U)
18066#define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */
18067#define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */
18068
18069#define SDMMC_CLKCR_SELCLKRX_Pos (20U)
18070#define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00300000 */
18071#define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */
18072#define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00100000 */
18073#define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00200000 */
18074
18075/******************* Bit definition for SDMMC_ARG register *******************/
18076#define SDMMC_ARG_CMDARG_Pos (0U)
18077#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
18078#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
18079
18080/******************* Bit definition for SDMMC_CMD register *******************/
18081#define SDMMC_CMD_CMDINDEX_Pos (0U)
18082#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
18083#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
18084#define SDMMC_CMD_CMDTRANS_Pos (6U)
18085#define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */
18086#define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */
18087#define SDMMC_CMD_CMDSTOP_Pos (7U)
18088#define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */
18089#define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */
18090
18091#define SDMMC_CMD_WAITRESP_Pos (8U)
18092#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */
18093#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
18094#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */
18095#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */
18096
18097#define SDMMC_CMD_WAITINT_Pos (10U)
18098#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */
18099#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
18100#define SDMMC_CMD_WAITPEND_Pos (11U)
18101#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */
18102#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
18103#define SDMMC_CMD_CPSMEN_Pos (12U)
18104#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */
18105#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
18106#define SDMMC_CMD_DTHOLD_Pos (13U)
18107#define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */
18108#define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */
18109#define SDMMC_CMD_BOOTMODE_Pos (14U)
18110#define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */
18111#define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */
18112#define SDMMC_CMD_BOOTEN_Pos (15U)
18113#define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */
18114#define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */
18115#define SDMMC_CMD_CMDSUSPEND_Pos (16U)
18116#define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */
18117#define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM treats command as a Suspend or Resume command */
18118
18119/***************** Bit definition for SDMMC_RESPCMD register *****************/
18120#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
18121#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
18122#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
18123
18124/****************** Bit definition for SDMMC_RESP1 register ******************/
18125#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
18126#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)/*!< 0xFFFFFFFF */
18127#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
18128
18129/****************** Bit definition for SDMMC_RESP2 register ******************/
18130#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
18131#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)/*!< 0xFFFFFFFF */
18132#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
18133
18134/****************** Bit definition for SDMMC_RESP3 register ******************/
18135#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
18136#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)/*!< 0xFFFFFFFF */
18137#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
18138
18139/****************** Bit definition for SDMMC_RESP4 register ******************/
18140#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
18141#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)/*!< 0xFFFFFFFF */
18142#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
18143
18144/****************** Bit definition for SDMMC_DTIMER register *****************/
18145#define SDMMC_DTIMER_DATATIME_Pos (0U)
18146#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)/*!< 0xFFFFFFFF */
18147#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
18148
18149/****************** Bit definition for SDMMC_DLEN register *******************/
18150#define SDMMC_DLEN_DATALENGTH_Pos (0U)
18151#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)/*!< 0x01FFFFFF */
18152#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
18153
18154/****************** Bit definition for SDMMC_DCTRL register ******************/
18155#define SDMMC_DCTRL_DTEN_Pos (0U)
18156#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
18157#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
18158#define SDMMC_DCTRL_DTDIR_Pos (1U)
18159#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
18160#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
18161
18162#define SDMMC_DCTRL_DTMODE_Pos (2U)
18163#define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */
18164#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
18165#define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
18166#define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000008 */
18167
18168#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
18169#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
18170#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
18171#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
18172#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
18173#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
18174#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
18175
18176#define SDMMC_DCTRL_RWSTART_Pos (8U)
18177#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
18178#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
18179#define SDMMC_DCTRL_RWSTOP_Pos (9U)
18180#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
18181#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
18182#define SDMMC_DCTRL_RWMOD_Pos (10U)
18183#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
18184#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
18185#define SDMMC_DCTRL_SDIOEN_Pos (11U)
18186#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
18187#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
18188#define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
18189#define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */
18190#define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Data transfer mode selection */
18191#define SDMMC_DCTRL_FIFORST_Pos (13U)
18192#define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */
18193#define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */
18194
18195/****************** Bit definition for SDMMC_DCOUNT register *****************/
18196#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
18197#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)/*!< 0x01FFFFFF */
18198#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
18199
18200/****************** Bit definition for SDMMC_STA register ********************/
18201#define SDMMC_STA_CCRCFAIL_Pos (0U)
18202#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
18203#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
18204#define SDMMC_STA_DCRCFAIL_Pos (1U)
18205#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
18206#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
18207#define SDMMC_STA_CTIMEOUT_Pos (2U)
18208#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
18209#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
18210#define SDMMC_STA_DTIMEOUT_Pos (3U)
18211#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
18212#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
18213#define SDMMC_STA_TXUNDERR_Pos (4U)
18214#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
18215#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
18216#define SDMMC_STA_RXOVERR_Pos (5U)
18217#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
18218#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
18219#define SDMMC_STA_CMDREND_Pos (6U)
18220#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
18221#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
18222#define SDMMC_STA_CMDSENT_Pos (7U)
18223#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
18224#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
18225#define SDMMC_STA_DATAEND_Pos (8U)
18226#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
18227#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
18228#define SDMMC_STA_DHOLD_Pos (9U)
18229#define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */
18230#define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */
18231#define SDMMC_STA_DBCKEND_Pos (10U)
18232#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
18233#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
18234#define SDMMC_STA_DABORT_Pos (11U)
18235#define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
18236#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
18237#define SDMMC_STA_DPSMACT_Pos (12U)
18238#define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos) /*!< 0x00001000 */
18239#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Data path state machine active */
18240#define SDMMC_STA_CPSMACT_Pos (13U)
18241#define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos) /*!< 0x00002000 */
18242#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Command path state machine active */
18243#define SDMMC_STA_TXFIFOHE_Pos (14U)
18244#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
18245#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
18246#define SDMMC_STA_RXFIFOHF_Pos (15U)
18247#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
18248#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
18249#define SDMMC_STA_TXFIFOF_Pos (16U)
18250#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
18251#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
18252#define SDMMC_STA_RXFIFOF_Pos (17U)
18253#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
18254#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
18255#define SDMMC_STA_TXFIFOE_Pos (18U)
18256#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
18257#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
18258#define SDMMC_STA_RXFIFOE_Pos (19U)
18259#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
18260#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
18261#define SDMMC_STA_BUSYD0_Pos (20U)
18262#define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */
18263#define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */
18264#define SDMMC_STA_BUSYD0END_Pos (21U)
18265#define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */
18266#define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */
18267#define SDMMC_STA_SDIOIT_Pos (22U)
18268#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
18269#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
18270#define SDMMC_STA_ACKFAIL_Pos (23U)
18271#define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */
18272#define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */
18273#define SDMMC_STA_ACKTIMEOUT_Pos (24U)
18274#define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */
18275#define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */
18276#define SDMMC_STA_VSWEND_Pos (25U)
18277#define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */
18278#define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */
18279#define SDMMC_STA_CKSTOP_Pos (26U)
18280#define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */
18281#define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */
18282#define SDMMC_STA_IDMATE_Pos (27U)
18283#define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */
18284#define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */
18285#define SDMMC_STA_IDMABTC_Pos (28U)
18286#define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */
18287#define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */
18288
18289/******************* Bit definition for SDMMC_ICR register *******************/
18290#define SDMMC_ICR_CCRCFAILC_Pos (0U)
18291#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
18292#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
18293#define SDMMC_ICR_DCRCFAILC_Pos (1U)
18294#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
18295#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
18296#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
18297#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
18298#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
18299#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
18300#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
18301#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
18302#define SDMMC_ICR_TXUNDERRC_Pos (4U)
18303#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
18304#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
18305#define SDMMC_ICR_RXOVERRC_Pos (5U)
18306#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
18307#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
18308#define SDMMC_ICR_CMDRENDC_Pos (6U)
18309#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
18310#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
18311#define SDMMC_ICR_CMDSENTC_Pos (7U)
18312#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
18313#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
18314#define SDMMC_ICR_DATAENDC_Pos (8U)
18315#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
18316#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
18317#define SDMMC_ICR_DHOLDC_Pos (9U)
18318#define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */
18319#define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */
18320#define SDMMC_ICR_DBCKENDC_Pos (10U)
18321#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
18322#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
18323#define SDMMC_ICR_DABORTC_Pos (11U)
18324#define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */
18325#define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */
18326#define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
18327#define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */
18328#define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */
18329#define SDMMC_ICR_SDIOITC_Pos (22U)
18330#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
18331#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
18332#define SDMMC_ICR_ACKFAILC_Pos (23U)
18333#define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */
18334#define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */
18335#define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
18336#define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */
18337#define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */
18338#define SDMMC_ICR_VSWENDC_Pos (25U)
18339#define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */
18340#define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */
18341#define SDMMC_ICR_CKSTOPC_Pos (26U)
18342#define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */
18343#define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */
18344#define SDMMC_ICR_IDMATEC_Pos (27U)
18345#define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */
18346#define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */
18347#define SDMMC_ICR_IDMABTCC_Pos (28U)
18348#define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */
18349#define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */
18350
18351/****************** Bit definition for SDMMC_MASK register *******************/
18352#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
18353#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
18354#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
18355#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
18356#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
18357#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
18358#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
18359#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
18360#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
18361#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
18362#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
18363#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
18364#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
18365#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
18366#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
18367#define SDMMC_MASK_RXOVERRIE_Pos (5U)
18368#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
18369#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
18370#define SDMMC_MASK_CMDRENDIE_Pos (6U)
18371#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
18372#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
18373#define SDMMC_MASK_CMDSENTIE_Pos (7U)
18374#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
18375#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
18376#define SDMMC_MASK_DATAENDIE_Pos (8U)
18377#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
18378#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
18379#define SDMMC_MASK_DHOLDIE_Pos (9U)
18380#define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */
18381#define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */
18382#define SDMMC_MASK_DBCKENDIE_Pos (10U)
18383#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
18384#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
18385#define SDMMC_MASK_DABORTIE_Pos (11U)
18386#define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */
18387#define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted Interrupt Enable */
18388
18389#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
18390#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
18391#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
18392#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
18393#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
18394#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
18395
18396#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
18397#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
18398#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
18399#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
18400#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
18401#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
18402
18403#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
18404#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
18405#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
18406#define SDMMC_MASK_SDIOITIE_Pos (22U)
18407#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
18408#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
18409#define SDMMC_MASK_ACKFAILIE_Pos (23U)
18410#define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
18411#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
18412#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
18413#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
18414#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
18415#define SDMMC_MASK_VSWENDIE_Pos (25U)
18416#define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
18417#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
18418#define SDMMC_MASK_CKSTOPIE_Pos (26U)
18419#define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
18420#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
18421#define SDMMC_MASK_IDMABTCIE_Pos (28U)
18422#define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
18423#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
18424
18425/****************** Bit definition for SDMMC_ACKTIMER register **************/
18426#define SDMMC_ACKTIME_ACKTIME_Pos (0U)
18427#define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos)/*!< 0x01FFFFFF */
18428#define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk /*!<Boot acknowledgment timeout period */
18429
18430/****************** Bit definition for SDMMC_FIFO register *******************/
18431#define SDMMC_FIFO_FIFODATA_Pos (0U)
18432#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)/*!< 0xFFFFFFFF */
18433#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
18434
18435/****************** Bit definition for SDMMC_IDMACTRL register ***************/
18436#define SDMMC_IDMA_IDMAEN_Pos (0U)
18437#define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */
18438#define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */
18439#define SDMMC_IDMA_IDMABMODE_Pos (1U)
18440#define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */
18441#define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */
18442#define SDMMC_IDMA_IDMABACT_Pos (2U)
18443#define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
18444#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
18445
18446/****************** Bit definition for SDMMC_IDMABSIZE register *************/
18447#define SDMMC_IDMABSIZE_IDMABND_Pos (5U)
18448#define SDMMC_IDMABSIZE_IDMABND_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABND_Pos)/*!< 0x00001FE0 */
18449#define SDMMC_IDMABSIZE_IDMABND SDMMC_IDMABSIZE_IDMABND_Msk /*!<Number of transfers per buffer */
18450
18451/****************** Bit definition for SDMMC_IDMABASE0 register *************/
18452#define SDMMC_IDMABASE0_IDMABASE0_Pos (0U)
18453#define SDMMC_IDMABASE0_IDMABASE0_Msk (0xFFFFFFFFUL << SDMMC_IDMABASE0_IDMABASE0_Pos)/*!< 0xFFFFFFFF */
18454#define SDMMC_IDMABASE0_IDMABASE0 SDMMC_IDMABASE0_IDMABASE0_Msk /*!<Buffer 0 memory base address */
18455
18456/****************** Bit definition for SDMMC_IDMABASE1 register *************/
18457#define SDMMC_IDMABASE1_IDMABASE1_Pos (0U)
18458#define SDMMC_IDMABASE1_IDMABASE1_Msk (0xFFFFFFFFUL << SDMMC_IDMABASE1_IDMABASE0_Pos)/*!< 0xFFFFFFFF */
18459#define SDMMC_IDMABASE1_IDMABASE1 SDMMC_IDMABASE0_IDMABASE1_Msk /*!<Buffer 1 memory base address */
18460
18461/******************************************************************************/
18462/* */
18463/* UCPD */
18464/* */
18465/******************************************************************************/
18466/******************** Bits definition for UCPD_CFG1 register *******************/
18467#define UCPD_CFG1_HBITCLKDIV_Pos (0U)
18468#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
18469#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */
18470#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
18471#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
18472#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
18473#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
18474#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
18475#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
18476#define UCPD_CFG1_IFRGAP_Pos (6U)
18477#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */
18478#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */
18479#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */
18480#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */
18481#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */
18482#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */
18483#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */
18484#define UCPD_CFG1_TRANSWIN_Pos (11U)
18485#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */
18486#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */
18487#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */
18488#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */
18489#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */
18490#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */
18491#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */
18492#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U)
18493#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
18494#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */
18495#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
18496#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
18497#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
18498#define UCPD_CFG1_RXORDSETEN_Pos (20U)
18499#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
18500#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */
18501#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
18502#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
18503#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
18504#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
18505#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
18506#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
18507#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
18508#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
18509#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
18510#define UCPD_CFG1_TXDMAEN_Pos (29U)
18511#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */
18512#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */
18513#define UCPD_CFG1_RXDMAEN_Pos (30U)
18514#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */
18515#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */
18516#define UCPD_CFG1_UCPDEN_Pos (31U)
18517#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */
18518#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */
18519
18520/******************** Bits definition for UCPD_CFG2 register *******************/
18521#define UCPD_CFG2_RXFILTDIS_Pos (0U)
18522#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */
18523#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */
18524#define UCPD_CFG2_RXFILT2N3_Pos (1U)
18525#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */
18526#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
18527#define UCPD_CFG2_FORCECLK_Pos (2U)
18528#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */
18529#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */
18530#define UCPD_CFG2_WUPEN_Pos (3U)
18531#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */
18532#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */
18533
18534/******************** Bits definition for UCPD_CFG3 register *******************/
18535#define UCPD_CFG3_TRIM1_NG_CCRPD_Pos (0U)
18536#define UCPD_CFG3_TRIM1_NG_CCRPD_Msk (0xFUL << UCPD_CFG3_TRIM1_NG_CCRPD_Pos) /*!< 0x0000000F */
18537#define UCPD_CFG3_TRIM1_NG_CCRPD UCPD_CFG3_TRIM1_NG_CCRPD_Msk /*!< SW trim value for RPDEFAULT resistors (CC1) */
18538#define UCPD_CFG3_TRIM1_NG_CC1A5_Pos (4U)
18539#define UCPD_CFG3_TRIM1_NG_CC1A5_Msk (0x1FUL << UCPD_CFG3_TRIM1_NG_CC1A5_Pos)/*!< 0x000001F0 */
18540#define UCPD_CFG3_TRIM1_NG_CC1A5 UCPD_CFG3_TRIM1_NG_CC1A5_Msk /*!< SW trim value for RP1A5 resistors (CC1) */
18541#define UCPD_CFG3_TRIM1_NG_CC3A0_Pos (9U)
18542#define UCPD_CFG3_TRIM1_NG_CC3A0_Msk (0xFUL << UCPD_CFG3_TRIM1_NG_CC3A0_Pos) /*!< 0x00001E00 */
18543#define UCPD_CFG3_TRIM1_NG_CC3A0 UCPD_CFG3_TRIM1_NG_CC3A0_Msk /*!< SW trim value for RP3A0 resistors (CC1) */
18544#define UCPD_CFG3_TRIM2_NG_CCRPD_Pos (16U)
18545#define UCPD_CFG3_TRIM2_NG_CCRPD_Msk (0xFUL << UCPD_CFG3_TRIM2_NG_CCRPD_Pos) /*!< 0x000F0000 */
18546#define UCPD_CFG3_TRIM2_NG_CCRPD UCPD_CFG3_TRIM2_NG_CCRPD_Msk /*!< SW trim value for RPDEFAULT resistors (CC1) */
18547#define UCPD_CFG3_TRIM2_NG_CC1A5_Pos (20U)
18548#define UCPD_CFG3_TRIM2_NG_CC1A5_Msk (0x1FUL << UCPD_CFG3_TRIM2_NG_CC1A5_Pos)/*!< 0x01F00000 */
18549#define UCPD_CFG3_TRIM2_NG_CC1A5 UCPD_CFG3_TRIM2_NG_CC1A5_Msk /*!< SW trim value for RP1A5 resistors (CC1) */
18550#define UCPD_CFG3_TRIM2_NG_CC3A0_Pos (25U)
18551#define UCPD_CFG3_TRIM2_NG_CC3A0_Msk (0xFUL << UCPD_CFG3_TRIM2_NG_CC3A0_Pos) /*!< 0x1E000000 */
18552#define UCPD_CFG3_TRIM2_NG_CC3A0 UCPD_CFG3_TRIM2_NG_CC3A0_Msk /*!< SW trim value for RP3A0 resistors (CC1) */
18553
18554/******************** Bits definition for UCPD_CR register ********************/
18555#define UCPD_CR_TXMODE_Pos (0U)
18556#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */
18557#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */
18558#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */
18559#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */
18560#define UCPD_CR_TXSEND_Pos (2U)
18561#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */
18562#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */
18563#define UCPD_CR_TXHRST_Pos (3U)
18564#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */
18565#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */
18566#define UCPD_CR_RXMODE_Pos (4U)
18567#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */
18568#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */
18569#define UCPD_CR_PHYRXEN_Pos (5U)
18570#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */
18571#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */
18572#define UCPD_CR_PHYCCSEL_Pos (6U)
18573#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */
18574#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */
18575#define UCPD_CR_ANASUBMODE_Pos (7U)
18576#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */
18577#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
18578#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */
18579#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */
18580#define UCPD_CR_ANAMODE_Pos (9U)
18581#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */
18582#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */
18583#define UCPD_CR_CCENABLE_Pos (10U)
18584#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */
18585#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */
18586#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */
18587#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */
18588#define UCPD_CR_USEEXTPHY_Pos (12U)
18589#define UCPD_CR_USEEXTPHY_Msk (0x1UL << UCPD_CR_USEEXTPHY_Pos) /*!< 0x00001000 */
18590#define UCPD_CR_USEEXTPHY UCPD_CR_USEEXTPHY_Msk /*!< Controls enable of USB Power Delivery transmitter */
18591#define UCPD_CR_CC2VCONNEN_Pos (13U)
18592#define UCPD_CR_CC2VCONNEN_Msk (0x1UL << UCPD_CR_CC2VCONNEN_Pos) /*!< 0x00002000 */
18593#define UCPD_CR_CC2VCONNEN UCPD_CR_CC2VCONNEN_Msk /*!< VCONN enable for CC2 */
18594#define UCPD_CR_CC1VCONNEN_Pos (14U)
18595#define UCPD_CR_CC1VCONNEN_Msk (0x1UL << UCPD_CR_CC1VCONNEN_Pos) /*!< 0x00004000 */
18596#define UCPD_CR_CC1VCONNEN UCPD_CR_CC1VCONNEN_Msk /*!< VCONN enable for CC1 */
18597#define UCPD_CR_DBATEN_Pos (15U)
18598#define UCPD_CR_DBATEN_Msk (0x1UL << UCPD_CR_DBATEN_Pos) /*!< 0x00008000 */
18599#define UCPD_CR_DBATEN UCPD_CR_DBATEN_Msk /*!< Enable dead battery behavior (Active High) */
18600#define UCPD_CR_FRSRXEN_Pos (16U)
18601#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */
18602#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */
18603#define UCPD_CR_FRSTX_Pos (17U)
18604#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */
18605#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
18606#define UCPD_CR_RDCH_Pos (18U)
18607#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */
18608#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */
18609#define UCPD_CR_RPUSBABSENT_Pos (19U)
18610#define UCPD_CR_RPUSBABSENT_Msk (0x1UL << UCPD_CR_RPUSBABSENT_Pos) /*!< 0x00080000 */
18611#define UCPD_CR_RPUSBABSENT UCPD_CR_RPUSBABSENT_Msk /*!< */
18612#define UCPD_CR_CC1TCDIS_Pos (20U)
18613#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */
18614#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */
18615#define UCPD_CR_CC2TCDIS_Pos (21U)
18616#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */
18617#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */
18618
18619/******************** Bits definition for UCPD_IMR register *******************/
18620#define UCPD_IMR_TXISIE_Pos (0U)
18621#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */
18622#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */
18623#define UCPD_IMR_TXMSGDISCIE_Pos (1U)
18624#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */
18625#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */
18626#define UCPD_IMR_TXMSGSENTIE_Pos (2U)
18627#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */
18628#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */
18629#define UCPD_IMR_TXMSGABTIE_Pos (3U)
18630#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */
18631#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */
18632#define UCPD_IMR_HRSTDISCIE_Pos (4U)
18633#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */
18634#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */
18635#define UCPD_IMR_HRSTSENTIE_Pos (5U)
18636#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */
18637#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */
18638#define UCPD_IMR_TXUNDIE_Pos (6U)
18639#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */
18640#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */
18641#define UCPD_IMR_RXNEIE_Pos (8U)
18642#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */
18643#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */
18644#define UCPD_IMR_RXORDDETIE_Pos (9U)
18645#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */
18646#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */
18647#define UCPD_IMR_RXHRSTDETIE_Pos (10U)
18648#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */
18649#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */
18650#define UCPD_IMR_RXOVRIE_Pos (11U)
18651#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */
18652#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */
18653#define UCPD_IMR_RXMSGENDIE_Pos (12U)
18654#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */
18655#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */
18656#define UCPD_IMR_TYPECEVT1IE_Pos (14U)
18657#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */
18658#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */
18659#define UCPD_IMR_TYPECEVT2IE_Pos (15U)
18660#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */
18661#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */
18662#define UCPD_IMR_FRSEVTIE_Pos (20U)
18663#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */
18664#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */
18665
18666/******************** Bits definition for UCPD_SR register ********************/
18667#define UCPD_SR_TXIS_Pos (0U)
18668#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */
18669#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */
18670#define UCPD_SR_TXMSGDISC_Pos (1U)
18671#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */
18672#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */
18673#define UCPD_SR_TXMSGSENT_Pos (2U)
18674#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */
18675#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */
18676#define UCPD_SR_TXMSGABT_Pos (3U)
18677#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */
18678#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */
18679#define UCPD_SR_HRSTDISC_Pos (4U)
18680#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */
18681#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */
18682#define UCPD_SR_HRSTSENT_Pos (5U)
18683#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */
18684#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */
18685#define UCPD_SR_TXUND_Pos (6U)
18686#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */
18687#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */
18688#define UCPD_SR_RXNE_Pos (8U)
18689#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */
18690#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */
18691#define UCPD_SR_RXORDDET_Pos (9U)
18692#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */
18693#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */
18694#define UCPD_SR_RXHRSTDET_Pos (10U)
18695#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */
18696#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */
18697#define UCPD_SR_RXOVR_Pos (11U)
18698#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */
18699#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */
18700#define UCPD_SR_RXMSGEND_Pos (12U)
18701#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */
18702#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */
18703#define UCPD_SR_RXERR_Pos (13U)
18704#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */
18705#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */
18706#define UCPD_SR_TYPECEVT1_Pos (14U)
18707#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */
18708#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */
18709#define UCPD_SR_TYPECEVT2_Pos (15U)
18710#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */
18711#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */
18712#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)
18713#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
18714#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */
18715#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
18716#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
18717#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)
18718#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
18719#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!<Status of DC level on CC2 pin */
18720#define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
18721#define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
18722#define UCPD_SR_FRSEVT_Pos (20U)
18723#define UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos) /*!< 0x00100000 */
18724#define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role Swap detection event */
18725
18726/******************** Bits definition for UCPD_ICR register *******************/
18727#define UCPD_ICR_TXMSGDISCCF_Pos (1U)
18728#define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos) /*!< 0x00000002 */
18729#define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk /*!< Tx message discarded flag (TXMSGDISC) clear */
18730#define UCPD_ICR_TXMSGSENTCF_Pos (2U)
18731#define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos) /*!< 0x00000004 */
18732#define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk /*!< Tx message sent flag (TXMSGSENT) clear */
18733#define UCPD_ICR_TXMSGABTCF_Pos (3U)
18734#define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos) /*!< 0x00000008 */
18735#define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk /*!< Tx message abort flag (TXMSGABT) clear */
18736#define UCPD_ICR_HRSTDISCCF_Pos (4U)
18737#define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */
18738#define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset discarded flag (HRSTDISC) clear */
18739#define UCPD_ICR_HRSTSENTCF_Pos (5U)
18740#define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos) /*!< 0x00000020 */
18741#define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk /*!< Hard reset sent flag (HRSTSENT) clear */
18742#define UCPD_ICR_TXUNDCF_Pos (6U)
18743#define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos) /*!< 0x00000040 */
18744#define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk /*!< Tx underflow flag (TXUND) clear */
18745#define UCPD_ICR_RXORDDETCF_Pos (9U)
18746#define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos) /*!< 0x00000200 */
18747#define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk /*!< Rx ordered set detect flag (RXORDDET) clear */
18748#define UCPD_ICR_RXHRSTDETCF_Pos (10U)
18749#define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos) /*!< 0x00000400 */
18750#define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk /*!< Rx Hard Reset detected flag (RXHRSTDET) clear */
18751#define UCPD_ICR_RXOVRCF_Pos (11U)
18752#define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos) /*!< 0x00000800 */
18753#define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk /*!< Rx overflow flag (RXOVR) clear */
18754#define UCPD_ICR_RXMSGENDCF_Pos (12U)
18755#define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos) /*!< 0x00001000 */
18756#define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk /*!< Rx message received flag (RXMSGEND) clear */
18757#define UCPD_ICR_TYPECEVT1CF_Pos (14U)
18758#define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos) /*!< 0x00004000 */
18759#define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk /*!< TypeC event (CC1) flag (TYPECEVT1) clear */
18760#define UCPD_ICR_TYPECEVT2CF_Pos (15U)
18761#define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos) /*!< 0x00008000 */
18762#define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk /*!< TypeC event (CC2) flag (TYPECEVT2) clear */
18763#define UCPD_ICR_FRSEVTCF_Pos (20U)
18764#define UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos) /*!< 0x00100000 */
18765#define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role Swap event flag clear */
18766
18767/******************** Bits definition for UCPD_TXORDSET register **************/
18768#define UCPD_TX_ORDSET_TXORDSET_Pos (0U)
18769#define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
18770#define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk /*!< Tx Ordered Set */
18771
18772/******************** Bits definition for UCPD_TXPAYSZ register ****************/
18773#define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)
18774#define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
18775#define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk /*!< Tx payload size in bytes */
18776
18777/******************** Bits definition for UCPD_TXDR register *******************/
18778#define UCPD_TXDR_TXDATA_Pos (0U)
18779#define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos) /*!< 0x000000FF */
18780#define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk /*!< Tx Data Register */
18781
18782/******************** Bits definition for UCPD_RXORDSET register **************/
18783#define UCPD_RX_ORDSET_RXORDSET_Pos (0U)
18784#define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
18785#define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk /*!< Rx Ordered Set Code detected */
18786#define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
18787#define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
18788#define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
18789#define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)
18790#define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
18791#define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk /*!< Rx Ordered Set Debug indication */
18792#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)
18793#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
18794#define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
18795
18796/******************** Bits definition for UCPD_RXPAYSZ register ****************/
18797#define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)
18798#define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
18799#define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk /*!< Rx payload size in bytes */
18800
18801/******************** Bits definition for UCPD_RXDR register *******************/
18802#define UCPD_RXDR_RXDATA_Pos (0U)
18803#define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos) /*!< 0x000000FF */
18804#define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit receive data */
18805
18806/******************** Bits definition for UCPD_RXORDEXT1 register **************/
18807#define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)
18808#define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
18809#define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk /*!< RX Ordered Set Extension Register 1 */
18810
18811/******************** Bits definition for UCPD_RXORDEXT2 register **************/
18812#define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)
18813#define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
18814#define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk /*!< RX Ordered Set Extension Register 1 */
18815
18816/******************************************************************************/
18817/* */
18818/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
18819/* */
18820/******************************************************************************/
18821/****************** Bit definition for USART_CR1 register *******************/
18822#define USART_CR1_UE_Pos (0U)
18823#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
18824#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
18825#define USART_CR1_UESM_Pos (1U)
18826#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
18827#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
18828#define USART_CR1_RE_Pos (2U)
18829#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
18830#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
18831#define USART_CR1_TE_Pos (3U)
18832#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
18833#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
18834#define USART_CR1_IDLEIE_Pos (4U)
18835#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
18836#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
18837#define USART_CR1_RXNEIE_Pos (5U)
18838#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
18839#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
18840#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
18841#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */
18842#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
18843#define USART_CR1_TCIE_Pos (6U)
18844#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
18845#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
18846#define USART_CR1_TXEIE_Pos (7U)
18847#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
18848#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
18849#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
18850#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
18851#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE /*!< TXE and TX FIFO Not Full Interrupt Enable */
18852#define USART_CR1_PEIE_Pos (8U)
18853#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
18854#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
18855#define USART_CR1_PS_Pos (9U)
18856#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
18857#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
18858#define USART_CR1_PCE_Pos (10U)
18859#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
18860#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
18861#define USART_CR1_WAKE_Pos (11U)
18862#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
18863#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
18864#define USART_CR1_M0_Pos (12U)
18865#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
18866#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
18867#define USART_CR1_MME_Pos (13U)
18868#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
18869#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
18870#define USART_CR1_CMIE_Pos (14U)
18871#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
18872#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
18873#define USART_CR1_OVER8_Pos (15U)
18874#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
18875#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
18876#define USART_CR1_DEDT_Pos (16U)
18877#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
18878#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
18879#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
18880#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
18881#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
18882#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
18883#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
18884#define USART_CR1_DEAT_Pos (21U)
18885#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
18886#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
18887#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
18888#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
18889#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
18890#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
18891#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
18892#define USART_CR1_RTOIE_Pos (26U)
18893#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
18894#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out Interrupt Enable */
18895#define USART_CR1_EOBIE_Pos (27U)
18896#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
18897#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block Interrupt Enable */
18898#define USART_CR1_M1_Pos (28U)
18899#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
18900#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
18901#define USART_CR1_M (uint32_t)(USART_CR1_M1 | USART_CR1_M0) /*!< Word length */
18902#define USART_CR1_FIFOEN_Pos (29U)
18903#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
18904#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
18905#define USART_CR1_TXFEIE_Pos (30U)
18906#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
18907#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TX FIFO Empty Interrupt Enable */
18908#define USART_CR1_RXFFIE_Pos (31U)
18909#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
18910#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RX FIFO Full Interrupt Enable */
18911
18912/****************** Bit definition for USART_CR2 register *******************/
18913#define USART_CR2_SLVEN_Pos (0U)
18914#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
18915#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
18916#define USART_CR2_DIS_NSS_Pos (3U)
18917#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
18918#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */
18919#define USART_CR2_ADDM7_Pos (4U)
18920#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
18921#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
18922#define USART_CR2_LBDL_Pos (5U)
18923#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
18924#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
18925#define USART_CR2_LBDIE_Pos (6U)
18926#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
18927#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
18928#define USART_CR2_LBCL_Pos (8U)
18929#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
18930#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
18931#define USART_CR2_CPHA_Pos (9U)
18932#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
18933#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
18934#define USART_CR2_CPOL_Pos (10U)
18935#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
18936#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
18937#define USART_CR2_CLKEN_Pos (11U)
18938#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
18939#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
18940#define USART_CR2_STOP_Pos (12U)
18941#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
18942#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
18943#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
18944#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
18945#define USART_CR2_LINEN_Pos (14U)
18946#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
18947#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
18948#define USART_CR2_SWAP_Pos (15U)
18949#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
18950#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
18951#define USART_CR2_RXINV_Pos (16U)
18952#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
18953#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
18954#define USART_CR2_TXINV_Pos (17U)
18955#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
18956#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
18957#define USART_CR2_DATAINV_Pos (18U)
18958#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
18959#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
18960#define USART_CR2_MSBFIRST_Pos (19U)
18961#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
18962#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
18963#define USART_CR2_ABREN_Pos (20U)
18964#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
18965#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
18966#define USART_CR2_ABRMODE_Pos (21U)
18967#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
18968#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
18969#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
18970#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
18971#define USART_CR2_RTOEN_Pos (23U)
18972#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
18973#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
18974#define USART_CR2_ADD_Pos (24U)
18975#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
18976#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
18977
18978/****************** Bit definition for USART_CR3 register *******************/
18979#define USART_CR3_EIE_Pos (0U)
18980#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
18981#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
18982#define USART_CR3_IREN_Pos (1U)
18983#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
18984#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
18985#define USART_CR3_IRLP_Pos (2U)
18986#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
18987#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
18988#define USART_CR3_HDSEL_Pos (3U)
18989#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
18990#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
18991#define USART_CR3_NACK_Pos (4U)
18992#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
18993#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
18994#define USART_CR3_SCEN_Pos (5U)
18995#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
18996#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
18997#define USART_CR3_DMAR_Pos (6U)
18998#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
18999#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
19000#define USART_CR3_DMAT_Pos (7U)
19001#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
19002#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
19003#define USART_CR3_RTSE_Pos (8U)
19004#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
19005#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
19006#define USART_CR3_CTSE_Pos (9U)
19007#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
19008#define USART_CR3_CTSE USART_CR3_CTSE_Msk
19009#define USART_CR3_CTSIE_Pos (10U)
19010#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
19011#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
19012#define USART_CR3_ONEBIT_Pos (11U)
19013#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
19014#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
19015#define USART_CR3_OVRDIS_Pos (12U)
19016#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
19017#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
19018#define USART_CR3_DDRE_Pos (13U)
19019#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
19020#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
19021#define USART_CR3_DEM_Pos (14U)
19022#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
19023#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
19024#define USART_CR3_DEP_Pos (15U)
19025#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
19026#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
19027#define USART_CR3_SCARCNT_Pos (17U)
19028#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
19029#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
19030#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
19031#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
19032#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
19033#define USART_CR3_WUS_Pos (20U)
19034#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
19035#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
19036#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
19037#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
19038#define USART_CR3_WUFIE_Pos (22U)
19039#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
19040#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
19041#define USART_CR3_TXFTIE_Pos (23U)
19042#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
19043#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TX FIFO Threshold Interrupt Enable */
19044#define USART_CR3_TCBGTIE_Pos (24U)
19045#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
19046#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
19047#define USART_CR3_RXFTCFG_Pos (25U)
19048#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
19049#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RX FIFO Threshold Configuration */
19050#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
19051#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
19052#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
19053#define USART_CR3_RXFTIE_Pos (28U)
19054#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
19055#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RX FIFO Threshold Interrupt Enable */
19056#define USART_CR3_TXFTCFG_Pos (29U)
19057#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
19058#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TX FIFO Threshold configuration */
19059#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
19060#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
19061#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
19062
19063/****************** Bit definition for USART_BRR register *******************/
19064#define USART_BRR_LPUART ((uint32_t)0x000FFFFF) /*!< LPUART Baud rate register [19:0] */
19065#define USART_BRR_BRR ((uint16_t)0xFFFF) /*!< USART Baud rate register [15:0] */
19066
19067/****************** Bit definition for USART_GTPR register ******************/
19068#define USART_GTPR_PSC_Pos (0U)
19069#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
19070#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
19071#define USART_GTPR_GT_Pos (8U)
19072#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
19073#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
19074
19075/******************* Bit definition for USART_RTOR register *****************/
19076#define USART_RTOR_RTO_Pos (0U)
19077#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
19078#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Timeout Value */
19079#define USART_RTOR_BLEN_Pos (24U)
19080#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
19081#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
19082
19083/******************* Bit definition for USART_RQR register ******************/
19084#define USART_RQR_ABRRQ_Pos (0U)
19085#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
19086#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
19087#define USART_RQR_SBKRQ_Pos (1U)
19088#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
19089#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
19090#define USART_RQR_MMRQ_Pos (2U)
19091#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
19092#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
19093#define USART_RQR_RXFRQ_Pos (3U)
19094#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
19095#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
19096#define USART_RQR_TXFRQ_Pos (4U)
19097#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
19098#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit Data flush Request */
19099
19100/******************* Bit definition for USART_ISR register ******************/
19101#define USART_ISR_PE_Pos (0U)
19102#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
19103#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
19104#define USART_ISR_FE_Pos (1U)
19105#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
19106#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
19107#define USART_ISR_NE_Pos (2U)
19108#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
19109#define USART_ISR_NE USART_ISR_NE_Msk /*!< START bit Noise Error detection Flag */
19110#define USART_ISR_ORE_Pos (3U)
19111#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
19112#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
19113#define USART_ISR_IDLE_Pos (4U)
19114#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
19115#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
19116#define USART_ISR_RXNE_Pos (5U)
19117#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
19118#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
19119#define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos
19120#define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */
19121#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
19122#define USART_ISR_TC_Pos (6U)
19123#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
19124#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
19125#define USART_ISR_TXE_Pos (7U)
19126#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
19127#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
19128#define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos
19129#define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */
19130#define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
19131#define USART_ISR_LBDF_Pos (8U)
19132#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
19133#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
19134#define USART_ISR_CTSIF_Pos (9U)
19135#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
19136#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt Flag */
19137#define USART_ISR_CTS_Pos (10U)
19138#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
19139#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS Flag */
19140#define USART_ISR_RTOF_Pos (11U)
19141#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
19142#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Timeout */
19143#define USART_ISR_EOBF_Pos (12U)
19144#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
19145#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
19146#define USART_ISR_UDR_Pos (13U)
19147#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
19148#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI Slave Underrun error Flag */
19149#define USART_ISR_ABRE_Pos (14U)
19150#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
19151#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
19152#define USART_ISR_ABRF_Pos (15U)
19153#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
19154#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
19155#define USART_ISR_BUSY_Pos (16U)
19156#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
19157#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
19158#define USART_ISR_CMF_Pos (17U)
19159#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
19160#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
19161#define USART_ISR_SBKF_Pos (18U)
19162#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
19163#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
19164#define USART_ISR_RWU_Pos (19U)
19165#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
19166#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
19167#define USART_ISR_WUF_Pos (20U)
19168#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
19169#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
19170#define USART_ISR_TEACK_Pos (21U)
19171#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
19172#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
19173#define USART_ISR_REACK_Pos (22U)
19174#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
19175#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
19176#define USART_ISR_TXFE_Pos (23U)
19177#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
19178#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TX FIFO Empty Flag */
19179#define USART_ISR_RXFF_Pos (24U)
19180#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
19181#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RX FIFO Full Flag */
19182#define USART_ISR_TCBGT_Pos (25U)
19183#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
19184#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */
19185#define USART_ISR_RXFT_Pos (26U)
19186#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
19187#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RX FIFO Threshold Flag */
19188#define USART_ISR_TXFT_Pos (27U)
19189#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
19190#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TX FIFO Threshold Flag */
19191
19192/******************* Bit definition for USART_ICR register ******************/
19193#define USART_ICR_PECF_Pos (0U)
19194#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
19195#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
19196#define USART_ICR_FECF_Pos (1U)
19197#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
19198#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
19199#define USART_ICR_NECF_Pos (2U)
19200#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
19201#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
19202#define USART_ICR_ORECF_Pos (3U)
19203#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
19204#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
19205#define USART_ICR_IDLECF_Pos (4U)
19206#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
19207#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
19208#define USART_ICR_TXFECF_Pos (5U)
19209#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
19210#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TX FIFO Empty Clear Flag */
19211#define USART_ICR_TCCF_Pos (6U)
19212#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
19213#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
19214#define USART_ICR_TCBGTCF_Pos (7U)
19215#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
19216#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
19217#define USART_ICR_LBDCF_Pos (8U)
19218#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
19219#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
19220#define USART_ICR_CTSCF_Pos (9U)
19221#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
19222#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
19223#define USART_ICR_RTOCF_Pos (11U)
19224#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
19225#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
19226#define USART_ICR_EOBCF_Pos (12U)
19227#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
19228#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
19229#define USART_ICR_UDRCF_Pos (13U)
19230#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
19231#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
19232#define USART_ICR_CMCF_Pos (17U)
19233#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
19234#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
19235#define USART_ICR_WUCF_Pos (20U)
19236#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
19237#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
19238
19239/******************* Bit definition for USART_RDR register ******************/
19240#define USART_RDR_RDR_Pos (0U)
19241#define USART_RDR_RDR_Msk (0x01FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
19242#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
19243
19244/******************* Bit definition for USART_TDR register ******************/
19245#define USART_TDR_TDR_Pos (0U)
19246#define USART_TDR_TDR_Msk (0x01FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
19247#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
19248
19249/******************* Bit definition for USART_PRESC register ******************/
19250#define USART_PRESC_PRESCALER_Pos (0U)
19251#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
19252#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
19253#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
19254#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
19255#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
19256#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
19257
19258
19259/******************************************************************************/
19260/* */
19261/* USB Device FS Endpoint registers */
19262/* */
19263/******************************************************************************/
19264#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
19265#define USB_EP1R (USB_BASE + 0x00000004UL) /*!< endpoint 1 register address */
19266#define USB_EP2R (USB_BASE + 0x00000008UL) /*!< endpoint 2 register address */
19267#define USB_EP3R (USB_BASE + 0x0000000CUL) /*!< endpoint 3 register address */
19268#define USB_EP4R (USB_BASE + 0x00000010UL) /*!< endpoint 4 register address */
19269#define USB_EP5R (USB_BASE + 0x00000014UL) /*!< endpoint 5 register address */
19270#define USB_EP6R (USB_BASE + 0x00000018UL) /*!< endpoint 6 register address */
19271#define USB_EP7R (USB_BASE + 0x0000001CUL) /*!< endpoint 7 register address */
19272
19273/* bit positions */
19274#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
19275#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
19276#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
19277#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
19278#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
19279#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
19280#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
19281#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
19282#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
19283#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
19284
19285/* EndPoint REGister MASK (no toggle fields) */
19286#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
19287 /*!< EP_TYPE[1:0] EndPoint TYPE */
19288#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
19289#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
19290#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
19291#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
19292#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
19293#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
19294
19295#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
19296 /*!< STAT_TX[1:0] STATus for TX transfer */
19297#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
19298#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
19299#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
19300#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
19301#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
19302#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
19303#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
19304 /*!< STAT_RX[1:0] STATus for RX transfer */
19305#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
19306#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
19307#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
19308#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
19309#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
19310#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
19311#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
19312
19313/******************************************************************************/
19314/* */
19315/* USB Device FS General registers */
19316/* */
19317/******************************************************************************/
19318#define USB_CNTR (USB_BASE + 0x00000040UL) /*!< Control register */
19319#define USB_ISTR (USB_BASE + 0x00000044UL) /*!< Interrupt status register */
19320#define USB_FNR (USB_BASE + 0x00000048UL) /*!< Frame number register */
19321#define USB_DADDR (USB_BASE + 0x0000004CUL) /*!< Device address register */
19322#define USB_BTABLE (USB_BASE + 0x00000050UL) /*!< Buffer Table address register */
19323#define USB_LPMCSR (USB_BASE + 0x00000054UL) /*!< LPM Control and Status register */
19324#define USB_BCDR (USB_BASE + 0x00000058UL) /*!< Battery Charging detector register*/
19325
19326/****************** Bits definition for USB_CNTR register *******************/
19327#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
19328#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
19329#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
19330#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
19331#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
19332#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
19333#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
19334#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
19335#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
19336#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
19337#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
19338#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
19339#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
19340#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
19341#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
19342
19343/****************** Bits definition for USB_ISTR register *******************/
19344#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
19345#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
19346#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
19347#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
19348#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
19349#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
19350#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
19351#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
19352#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
19353#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
19354#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
19355
19356#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
19357#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
19358#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
19359#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
19360#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
19361#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
19362#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
19363#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
19364#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
19365
19366/****************** Bits definition for USB_FNR register ********************/
19367#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
19368#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
19369#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
19370#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
19371#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
19372
19373/****************** Bits definition for USB_DADDR register ****************/
19374#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */
19375#define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */
19376#define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */
19377#define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */
19378#define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */
19379#define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */
19380#define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */
19381#define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */
19382
19383#define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */
19384
19385/****************** Bit definition for USB_BTABLE register ******************/
19386#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */
19387
19388/****************** Bits definition for USB_BCDR register *******************/
19389#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
19390#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
19391#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
19392#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
19393#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
19394#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
19395#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
19396#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
19397#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
19398
19399/******************* Bit definition for LPMCSR register *********************/
19400#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
19401#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
19402#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
19403#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
19404
19405/*!< Buffer descriptor table */
19406/***************** Bit definition for USB_ADDR0_TX register *****************/
19407#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
19408#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
19409#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
19410
19411/***************** Bit definition for USB_ADDR1_TX register *****************/
19412#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
19413#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
19414#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
19415
19416/***************** Bit definition for USB_ADDR2_TX register *****************/
19417#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
19418#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
19419#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
19420
19421/***************** Bit definition for USB_ADDR3_TX register *****************/
19422#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
19423#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
19424#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
19425
19426/***************** Bit definition for USB_ADDR4_TX register *****************/
19427#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
19428#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
19429#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
19430
19431/***************** Bit definition for USB_ADDR5_TX register *****************/
19432#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
19433#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
19434#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
19435
19436/***************** Bit definition for USB_ADDR6_TX register *****************/
19437#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
19438#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
19439#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
19440
19441/***************** Bit definition for USB_ADDR7_TX register *****************/
19442#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
19443#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
19444#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
19445
19446/*----------------------------------------------------------------------------*/
19447
19448/***************** Bit definition for USB_COUNT0_TX register ****************/
19449#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
19450#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
19451#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
19452
19453/***************** Bit definition for USB_COUNT1_TX register ****************/
19454#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
19455#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
19456#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
19457
19458/***************** Bit definition for USB_COUNT2_TX register ****************/
19459#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
19460#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
19461#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
19462
19463/***************** Bit definition for USB_COUNT3_TX register ****************/
19464#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
19465#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
19466#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
19467
19468/***************** Bit definition for USB_COUNT4_TX register ****************/
19469#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
19470#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
19471#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
19472
19473/***************** Bit definition for USB_COUNT5_TX register ****************/
19474#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
19475#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
19476#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
19477
19478/***************** Bit definition for USB_COUNT6_TX register ****************/
19479#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
19480#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
19481#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
19482
19483/***************** Bit definition for USB_COUNT7_TX register ****************/
19484#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
19485#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
19486#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
19487
19488/*----------------------------------------------------------------------------*/
19489
19490/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
19491#define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 0 (low) */
19492
19493/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
19494#define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 0 (high) */
19495
19496/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
19497#define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 1 (low) */
19498
19499/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
19500#define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 1 (high) */
19501
19502/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
19503#define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 2 (low) */
19504
19505/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
19506#define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 2 (high) */
19507
19508/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
19509#define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 3 (low) */
19510
19511/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
19512#define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 3 (high) */
19513
19514/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
19515#define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 4 (low) */
19516
19517/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
19518#define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 4 (high) */
19519
19520/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
19521#define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 5 (low) */
19522
19523/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
19524#define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 5 (high) */
19525
19526/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
19527#define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 6 (low) */
19528
19529/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
19530#define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 6 (high) */
19531
19532/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
19533#define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 7 (low) */
19534
19535/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
19536#define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 7 (high) */
19537
19538/*----------------------------------------------------------------------------*/
19539
19540/***************** Bit definition for USB_ADDR0_RX register *****************/
19541#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
19542#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
19543#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
19544
19545/***************** Bit definition for USB_ADDR1_RX register *****************/
19546#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
19547#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
19548#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
19549
19550/***************** Bit definition for USB_ADDR2_RX register *****************/
19551#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
19552#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
19553#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
19554
19555/***************** Bit definition for USB_ADDR3_RX register *****************/
19556#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
19557#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
19558#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
19559
19560/***************** Bit definition for USB_ADDR4_RX register *****************/
19561#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
19562#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
19563#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
19564
19565/***************** Bit definition for USB_ADDR5_RX register *****************/
19566#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
19567#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
19568#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
19569
19570/***************** Bit definition for USB_ADDR6_RX register *****************/
19571#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
19572#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
19573#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
19574
19575/***************** Bit definition for USB_ADDR7_RX register *****************/
19576#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
19577#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
19578#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
19579
19580/*----------------------------------------------------------------------------*/
19581
19582/***************** Bit definition for USB_COUNT0_RX register ****************/
19583#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
19584#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
19585#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
19586
19587#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
19588#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
19589#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
19590#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
19591#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
19592#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
19593#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
19594#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
19595
19596#define USB_COUNT0_RX_BLSIZE_Pos (15U)
19597#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
19598#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
19599
19600/***************** Bit definition for USB_COUNT1_RX register ****************/
19601#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
19602#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
19603#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
19604
19605#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
19606#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
19607#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
19608#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
19609#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
19610#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
19611#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
19612#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
19613
19614#define USB_COUNT1_RX_BLSIZE_Pos (15U)
19615#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
19616#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
19617
19618/***************** Bit definition for USB_COUNT2_RX register ****************/
19619#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
19620#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
19621#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
19622
19623#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
19624#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
19625#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
19626#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
19627#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
19628#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
19629#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
19630#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
19631
19632#define USB_COUNT2_RX_BLSIZE_Pos (15U)
19633#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
19634#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
19635
19636/***************** Bit definition for USB_COUNT3_RX register ****************/
19637#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
19638#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
19639#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
19640
19641#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
19642#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
19643#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
19644#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
19645#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
19646#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
19647#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
19648#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
19649
19650#define USB_COUNT3_RX_BLSIZE_Pos (15U)
19651#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
19652#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
19653
19654/***************** Bit definition for USB_COUNT4_RX register ****************/
19655#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
19656#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
19657#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
19658
19659#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
19660#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
19661#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
19662#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
19663#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
19664#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
19665#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
19666#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
19667
19668#define USB_COUNT4_RX_BLSIZE_Pos (15U)
19669#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
19670#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
19671
19672/***************** Bit definition for USB_COUNT5_RX register ****************/
19673#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
19674#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
19675#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
19676
19677#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
19678#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
19679#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
19680#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
19681#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
19682#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
19683#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
19684#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
19685
19686#define USB_COUNT5_RX_BLSIZE_Pos (15U)
19687#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
19688#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
19689
19690/***************** Bit definition for USB_COUNT6_RX register ****************/
19691#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
19692#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
19693#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
19694
19695#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
19696#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
19697#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
19698#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
19699#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
19700#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
19701#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
19702#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
19703
19704#define USB_COUNT6_RX_BLSIZE_Pos (15U)
19705#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
19706#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
19707
19708/***************** Bit definition for USB_COUNT7_RX register ****************/
19709#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
19710#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
19711#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
19712
19713#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
19714#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
19715#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
19716#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
19717#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
19718#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
19719#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
19720#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
19721
19722#define USB_COUNT7_RX_BLSIZE_Pos (15U)
19723#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
19724#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
19725
19726/*----------------------------------------------------------------------------*/
19727
19728/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
19729#define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */
19730
19731#define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
19732#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */
19733#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */
19734#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */
19735#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */
19736#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */
19737
19738#define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */
19739
19740/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
19741#define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */
19742
19743#define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
19744#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 1 */
19745#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */
19746#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */
19747#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */
19748#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */
19749
19750#define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */
19751
19752/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
19753#define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */
19754
19755#define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
19756#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */
19757#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */
19758#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */
19759#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */
19760#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */
19761
19762#define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */
19763
19764/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
19765#define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */
19766
19767#define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
19768#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 0 */
19769#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */
19770#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */
19771#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */
19772#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */
19773
19774#define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */
19775
19776/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
19777#define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */
19778
19779#define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
19780#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */
19781#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */
19782#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */
19783#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */
19784#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */
19785
19786#define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */
19787
19788/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
19789#define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */
19790
19791#define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
19792#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 0 */
19793#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */
19794#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */
19795#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */
19796#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */
19797
19798#define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */
19799
19800/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
19801#define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */
19802
19803#define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
19804#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */
19805#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */
19806#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */
19807#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */
19808#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */
19809
19810#define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */
19811
19812/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
19813#define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */
19814
19815#define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
19816#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 0 */
19817#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */
19818#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */
19819#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */
19820#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */
19821
19822#define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */
19823
19824/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
19825#define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */
19826
19827#define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
19828#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */
19829#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */
19830#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */
19831#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */
19832#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */
19833
19834#define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */
19835
19836/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
19837#define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */
19838
19839#define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
19840#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 0 */
19841#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */
19842#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */
19843#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */
19844#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */
19845
19846#define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */
19847
19848/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
19849#define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */
19850
19851#define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
19852#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */
19853#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */
19854#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */
19855#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */
19856#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */
19857
19858#define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */
19859
19860/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
19861#define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */
19862
19863#define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
19864#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 0 */
19865#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */
19866#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */
19867#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */
19868#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */
19869
19870#define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */
19871
19872/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
19873#define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */
19874
19875#define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
19876#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */
19877#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */
19878#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */
19879#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */
19880#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */
19881
19882#define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */
19883
19884/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
19885#define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */
19886
19887#define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
19888#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 0 */
19889#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */
19890#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */
19891#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */
19892#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */
19893
19894#define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */
19895
19896/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
19897#define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */
19898
19899#define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
19900#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */
19901#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */
19902#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */
19903#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */
19904#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */
19905
19906#define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */
19907
19908/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
19909#define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */
19910
19911#define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
19912#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 0 */
19913#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */
19914#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */
19915#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */
19916#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */
19917
19918#define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */
19919
19920
19921/******************************************************************************/
19922/* */
19923/* VREFBUF */
19924/* */
19925/******************************************************************************/
19926/******************* Bit definition for VREFBUF_CSR register ****************/
19927#define VREFBUF_CSR_ENVR_Pos (0U)
19928#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
19929#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
19930#define VREFBUF_CSR_HIZ_Pos (1U)
19931#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
19932#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
19933#define VREFBUF_CSR_VRS_Pos (2U)
19934#define VREFBUF_CSR_VRS_Msk (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */
19935#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
19936#define VREFBUF_CSR_VRR_Pos (3U)
19937#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
19938#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
19939
19940/******************* Bit definition for VREFBUF_CCR register ******************/
19941#define VREFBUF_CCR_TRIM_Pos (0U)
19942#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
19943#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
19944
19945/******************************************************************************/
19946/* */
19947/* Window WATCHDOG */
19948/* */
19949/******************************************************************************/
19950/******************* Bit definition for WWDG_CR register ********************/
19951#define WWDG_CR_T_Pos (0U)
19952#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
19953#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
19954#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
19955#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
19956#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
19957#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
19958#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
19959#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
19960#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
19961
19962#define WWDG_CR_WDGA_Pos (7U)
19963#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
19964#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
19965
19966/******************* Bit definition for WWDG_CFR register *******************/
19967#define WWDG_CFR_W_Pos (0U)
19968#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
19969#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
19970#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
19971#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
19972#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
19973#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
19974#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
19975#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
19976#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
19977
19978#define WWDG_CFR_WDGTB_Pos (11U)
19979#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
19980#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
19981#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
19982#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
19983#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
19984
19985#define WWDG_CFR_EWI_Pos (9U)
19986#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
19987#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
19988
19989/******************* Bit definition for WWDG_SR register ********************/
19990#define WWDG_SR_EWIF_Pos (0U)
19991#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
19992#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
19993
19994/** @} */ /* End of group STM32L5xx_Peripheral_Declaration */
19995
19996/** @addtogroup STM32L5xx_Peripheral_Exported_macros
19997 * @{
19998 */
19999
20000#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
20001/* Instances allowed from Secure state */
20002
20003/******************************* ADC Instances ********************************/
20004#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_S) || \
20005 ((INSTANCE) == ADC2_S))
20006
20007#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_S)
20008
20009#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON_S)
20010
20011/******************************* AES Instances ********************************/
20012#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES_S)
20013
20014/******************************** FDCAN Instances *****************************/
20015#define IS_FDCAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN1_S)
20016
20017#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG_S)
20018
20019/******************************** COMP Instances ******************************/
20020#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_S) || \
20021 ((INSTANCE) == COMP2_S))
20022
20023#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON_S)
20024
20025/******************** COMP Instances with window mode capability **************/
20026#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2_S)
20027
20028/******************************* CRC Instances ********************************/
20029#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC_S)
20030
20031/******************************* DAC Instances ********************************/
20032#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1_S)
20033
20034/****************************** DFSDM Instances *******************************/
20035#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0_S) || \
20036 ((INSTANCE) == DFSDM1_Filter1_S) || \
20037 ((INSTANCE) == DFSDM1_Filter2_S) || \
20038 ((INSTANCE) == DFSDM1_Filter3_S))
20039
20040#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0_S) || \
20041 ((INSTANCE) == DFSDM1_Channel1_S) || \
20042 ((INSTANCE) == DFSDM1_Channel2_S) || \
20043 ((INSTANCE) == DFSDM1_Channel3_S))
20044
20045/******************************** DMA Instances *******************************/
20046#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1_S) || \
20047 ((INSTANCE) == DMA1_Channel2_S) || \
20048 ((INSTANCE) == DMA1_Channel3_S) || \
20049 ((INSTANCE) == DMA1_Channel4_S) || \
20050 ((INSTANCE) == DMA1_Channel5_S) || \
20051 ((INSTANCE) == DMA1_Channel6_S) || \
20052 ((INSTANCE) == DMA1_Channel7_S) || \
20053 ((INSTANCE) == DMA1_Channel8_S) || \
20054 ((INSTANCE) == DMA2_Channel1_S) || \
20055 ((INSTANCE) == DMA2_Channel2_S) || \
20056 ((INSTANCE) == DMA2_Channel3_S) || \
20057 ((INSTANCE) == DMA2_Channel4_S) || \
20058 ((INSTANCE) == DMA2_Channel5_S) || \
20059 ((INSTANCE) == DMA2_Channel6_S) || \
20060 ((INSTANCE) == DMA2_Channel7_S) || \
20061 ((INSTANCE) == DMA2_Channel8_S))
20062
20063/******************************* GPIO Instances *******************************/
20064#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_S) || \
20065 ((INSTANCE) == GPIOB_S) || \
20066 ((INSTANCE) == GPIOC_S) || \
20067 ((INSTANCE) == GPIOD_S) || \
20068 ((INSTANCE) == GPIOE_S) || \
20069 ((INSTANCE) == GPIOF_S) || \
20070 ((INSTANCE) == GPIOG_S) || \
20071 ((INSTANCE) == GPIOH_S))
20072
20073/******************************* GPIO AF Instances ****************************/
20074/* All GPIO Banks support AF */
20075#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
20076
20077/**************************** GPIO Lock Instances *****************************/
20078/* All GPIO Banks support the Lock mechanism */
20079#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
20080
20081/******************************** I2C Instances *******************************/
20082#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_S) || \
20083 ((INSTANCE) == I2C2_S) || \
20084 ((INSTANCE) == I2C3_S) || \
20085 ((INSTANCE) == I2C4_S))
20086
20087/****************** I2C Instances : wakeup capability from stop modes *********/
20088#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
20089
20090/****************************** OPAMP Instances *******************************/
20091#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_S) || \
20092 ((INSTANCE) == OPAMP2_S))
20093
20094#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON_S)
20095
20096/******************************* OSPI Instances *******************************/
20097#define IS_OSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OCTOSPI1_S)
20098
20099/******************************** OTFDEC Instances ****************************/
20100#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OTFDEC1_S)
20101
20102/******************************** OTFDEC Regions Instances ********************/
20103#define IS_OTFDEC_REGION_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_REGION1_S) || \
20104 ((INSTANCE) == OTFDEC1_REGION2_S) || \
20105 ((INSTANCE) == OTFDEC1_REGION3_S) || \
20106 ((INSTANCE) == OTFDEC1_REGION4_S))
20107
20108/******************************** PKA Instances *******************************/
20109#define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_S)
20110
20111/******************************* RNG Instances ********************************/
20112#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG_S)
20113
20114/****************************** RTC Instances *********************************/
20115#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC_S)
20116
20117/******************************** SAI Instances *******************************/
20118#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_S) || \
20119 ((INSTANCE) == SAI1_Block_B_S) || \
20120 ((INSTANCE) == SAI2_Block_A_S) || \
20121 ((INSTANCE) == SAI2_Block_B_S))
20122
20123/****************************** SDMMC Instances *******************************/
20124#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1_S)
20125
20126/****************************** SMBUS Instances *******************************/
20127#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
20128
20129/******************************** SPI Instances *******************************/
20130#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || \
20131 ((INSTANCE) == SPI2_S) || \
20132 ((INSTANCE) == SPI3_S))
20133
20134/****************** LPTIM Instances : All supported instances *****************/
20135#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || \
20136 ((INSTANCE) == LPTIM2_S) || \
20137 ((INSTANCE) == LPTIM3_S))
20138
20139#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1_S)
20140
20141/****************** TIM Instances : All supported instances *******************/
20142#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20143 ((INSTANCE) == TIM2_S) || \
20144 ((INSTANCE) == TIM3_S) || \
20145 ((INSTANCE) == TIM4_S) || \
20146 ((INSTANCE) == TIM5_S) || \
20147 ((INSTANCE) == TIM6_S) || \
20148 ((INSTANCE) == TIM7_S) || \
20149 ((INSTANCE) == TIM8_S) || \
20150 ((INSTANCE) == TIM15_S) || \
20151 ((INSTANCE) == TIM16_S) || \
20152 ((INSTANCE) == TIM17_S))
20153
20154/****************** TIM Instances : supporting 32 bits counter ****************/
20155#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_S) || \
20156 ((INSTANCE) == TIM5_S))
20157
20158/****************** TIM Instances : supporting the break function *************/
20159#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20160 ((INSTANCE) == TIM8_S) || \
20161 ((INSTANCE) == TIM15_S) || \
20162 ((INSTANCE) == TIM16_S) || \
20163 ((INSTANCE) == TIM17_S))
20164
20165/************** TIM Instances : supporting Break source selection *************/
20166#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20167 ((INSTANCE) == TIM8_S) || \
20168 ((INSTANCE) == TIM15_S) || \
20169 ((INSTANCE) == TIM16_S) || \
20170 ((INSTANCE) == TIM17_S))
20171
20172/****************** TIM Instances : supporting 2 break inputs *****************/
20173#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20174 ((INSTANCE) == TIM8_S))
20175
20176/************* TIM Instances : at least 1 capture/compare channel *************/
20177#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20178 ((INSTANCE) == TIM2_S) || \
20179 ((INSTANCE) == TIM3_S) || \
20180 ((INSTANCE) == TIM4_S) || \
20181 ((INSTANCE) == TIM5_S) || \
20182 ((INSTANCE) == TIM8_S) || \
20183 ((INSTANCE) == TIM15_S) || \
20184 ((INSTANCE) == TIM16_S) || \
20185 ((INSTANCE) == TIM17_S))
20186
20187/************ TIM Instances : at least 2 capture/compare channels *************/
20188#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20189 ((INSTANCE) == TIM2_S) || \
20190 ((INSTANCE) == TIM3_S) || \
20191 ((INSTANCE) == TIM4_S) || \
20192 ((INSTANCE) == TIM5_S) || \
20193 ((INSTANCE) == TIM8_S) || \
20194 ((INSTANCE) == TIM15_S))
20195
20196/************ TIM Instances : at least 3 capture/compare channels *************/
20197#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20198 ((INSTANCE) == TIM2_S) || \
20199 ((INSTANCE) == TIM3_S) || \
20200 ((INSTANCE) == TIM4_S) || \
20201 ((INSTANCE) == TIM5_S) || \
20202 ((INSTANCE) == TIM8_S))
20203
20204/************ TIM Instances : at least 4 capture/compare channels *************/
20205#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20206 ((INSTANCE) == TIM2_S) || \
20207 ((INSTANCE) == TIM3_S) || \
20208 ((INSTANCE) == TIM4_S) || \
20209 ((INSTANCE) == TIM5_S) || \
20210 ((INSTANCE) == TIM8_S))
20211
20212/****************** TIM Instances : at least 5 capture/compare channels *******/
20213#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20214 ((INSTANCE) == TIM8_S))
20215
20216/****************** TIM Instances : at least 6 capture/compare channels *******/
20217#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20218 ((INSTANCE) == TIM8_S))
20219
20220/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
20221#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20222 ((INSTANCE) == TIM8_S) || \
20223 ((INSTANCE) == TIM15_S) || \
20224 ((INSTANCE) == TIM16_S) || \
20225 ((INSTANCE) == TIM17_S))
20226
20227/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
20228#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20229 ((INSTANCE) == TIM2_S) || \
20230 ((INSTANCE) == TIM3_S) || \
20231 ((INSTANCE) == TIM4_S) || \
20232 ((INSTANCE) == TIM5_S) || \
20233 ((INSTANCE) == TIM6_S) || \
20234 ((INSTANCE) == TIM7_S) || \
20235 ((INSTANCE) == TIM8_S) || \
20236 ((INSTANCE) == TIM15_S) || \
20237 ((INSTANCE) == TIM16_S) || \
20238 ((INSTANCE) == TIM17_S))
20239
20240/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
20241#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20242 ((INSTANCE) == TIM2_S) || \
20243 ((INSTANCE) == TIM3_S) || \
20244 ((INSTANCE) == TIM4_S) || \
20245 ((INSTANCE) == TIM5_S) || \
20246 ((INSTANCE) == TIM8_S) || \
20247 ((INSTANCE) == TIM15_S) || \
20248 ((INSTANCE) == TIM16_S) || \
20249 ((INSTANCE) == TIM17_S))
20250
20251/******************** TIM Instances : DMA burst feature ***********************/
20252#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20253 ((INSTANCE) == TIM2_S) || \
20254 ((INSTANCE) == TIM3_S) || \
20255 ((INSTANCE) == TIM4_S) || \
20256 ((INSTANCE) == TIM5_S) || \
20257 ((INSTANCE) == TIM8_S) || \
20258 ((INSTANCE) == TIM15_S) || \
20259 ((INSTANCE) == TIM16_S) || \
20260 ((INSTANCE) == TIM17_S))
20261
20262/******************* TIM Instances : output(s) available **********************/
20263#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
20264 ((((INSTANCE) == TIM1_S) && \
20265 (((CHANNEL) == TIM_CHANNEL_1) || \
20266 ((CHANNEL) == TIM_CHANNEL_2) || \
20267 ((CHANNEL) == TIM_CHANNEL_3) || \
20268 ((CHANNEL) == TIM_CHANNEL_4) || \
20269 ((CHANNEL) == TIM_CHANNEL_5) || \
20270 ((CHANNEL) == TIM_CHANNEL_6))) \
20271 || \
20272 (((INSTANCE) == TIM2_S) && \
20273 (((CHANNEL) == TIM_CHANNEL_1) || \
20274 ((CHANNEL) == TIM_CHANNEL_2) || \
20275 ((CHANNEL) == TIM_CHANNEL_3) || \
20276 ((CHANNEL) == TIM_CHANNEL_4))) \
20277 || \
20278 (((INSTANCE) == TIM3_S) && \
20279 (((CHANNEL) == TIM_CHANNEL_1) || \
20280 ((CHANNEL) == TIM_CHANNEL_2) || \
20281 ((CHANNEL) == TIM_CHANNEL_3) || \
20282 ((CHANNEL) == TIM_CHANNEL_4))) \
20283 || \
20284 (((INSTANCE) == TIM4_S) && \
20285 (((CHANNEL) == TIM_CHANNEL_1) || \
20286 ((CHANNEL) == TIM_CHANNEL_2) || \
20287 ((CHANNEL) == TIM_CHANNEL_3) || \
20288 ((CHANNEL) == TIM_CHANNEL_4))) \
20289 || \
20290 (((INSTANCE) == TIM5_S) && \
20291 (((CHANNEL) == TIM_CHANNEL_1) || \
20292 ((CHANNEL) == TIM_CHANNEL_2) || \
20293 ((CHANNEL) == TIM_CHANNEL_3) || \
20294 ((CHANNEL) == TIM_CHANNEL_4))) \
20295 || \
20296 (((INSTANCE) == TIM8_S) && \
20297 (((CHANNEL) == TIM_CHANNEL_1) || \
20298 ((CHANNEL) == TIM_CHANNEL_2) || \
20299 ((CHANNEL) == TIM_CHANNEL_3) || \
20300 ((CHANNEL) == TIM_CHANNEL_4) || \
20301 ((CHANNEL) == TIM_CHANNEL_5) || \
20302 ((CHANNEL) == TIM_CHANNEL_6))) \
20303 || \
20304 (((INSTANCE) == TIM15_S) && \
20305 (((CHANNEL) == TIM_CHANNEL_1) || \
20306 ((CHANNEL) == TIM_CHANNEL_2))) \
20307 || \
20308 (((INSTANCE) == TIM16_S) && \
20309 (((CHANNEL) == TIM_CHANNEL_1))) \
20310 || \
20311 (((INSTANCE) == TIM17_S) && \
20312 (((CHANNEL) == TIM_CHANNEL_1))))
20313
20314/****************** TIM Instances : supporting complementary output(s) ********/
20315#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
20316 ((((INSTANCE) == TIM1_S) && \
20317 (((CHANNEL) == TIM_CHANNEL_1) || \
20318 ((CHANNEL) == TIM_CHANNEL_2) || \
20319 ((CHANNEL) == TIM_CHANNEL_3))) \
20320 || \
20321 (((INSTANCE) == TIM8_S) && \
20322 (((CHANNEL) == TIM_CHANNEL_1) || \
20323 ((CHANNEL) == TIM_CHANNEL_2) || \
20324 ((CHANNEL) == TIM_CHANNEL_3))) \
20325 || \
20326 (((INSTANCE) == TIM15_S) && \
20327 ((CHANNEL) == TIM_CHANNEL_1)) \
20328 || \
20329 (((INSTANCE) == TIM16_S) && \
20330 ((CHANNEL) == TIM_CHANNEL_1)) \
20331 || \
20332 (((INSTANCE) == TIM17_S) && \
20333 ((CHANNEL) == TIM_CHANNEL_1)))
20334
20335/****************** TIM Instances : supporting clock division *****************/
20336#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20337 ((INSTANCE) == TIM2_S) || \
20338 ((INSTANCE) == TIM3_S) || \
20339 ((INSTANCE) == TIM4_S) || \
20340 ((INSTANCE) == TIM5_S) || \
20341 ((INSTANCE) == TIM8_S) || \
20342 ((INSTANCE) == TIM15_S) || \
20343 ((INSTANCE) == TIM16_S) || \
20344 ((INSTANCE) == TIM17_S))
20345
20346/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
20347#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20348 ((INSTANCE) == TIM2_S) || \
20349 ((INSTANCE) == TIM3_S) || \
20350 ((INSTANCE) == TIM4_S) || \
20351 ((INSTANCE) == TIM5_S) || \
20352 ((INSTANCE) == TIM8_S) || \
20353 ((INSTANCE) == TIM15_S))
20354
20355/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
20356#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20357 ((INSTANCE) == TIM2_S) || \
20358 ((INSTANCE) == TIM3_S) || \
20359 ((INSTANCE) == TIM4_S) || \
20360 ((INSTANCE) == TIM5_S) || \
20361 ((INSTANCE) == TIM8_S))
20362
20363/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
20364#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20365 ((INSTANCE) == TIM2_S) || \
20366 ((INSTANCE) == TIM3_S) || \
20367 ((INSTANCE) == TIM4_S) || \
20368 ((INSTANCE) == TIM5_S) || \
20369 ((INSTANCE) == TIM8_S) || \
20370 ((INSTANCE) == TIM15_S))
20371
20372/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
20373#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20374 ((INSTANCE) == TIM2_S) || \
20375 ((INSTANCE) == TIM3_S) || \
20376 ((INSTANCE) == TIM4_S) || \
20377 ((INSTANCE) == TIM5_S) || \
20378 ((INSTANCE) == TIM8_S) || \
20379 ((INSTANCE) == TIM15_S))
20380
20381/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
20382#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20383 ((INSTANCE) == TIM8_S))
20384
20385/****************** TIM Instances : supporting commutation event generation ***/
20386#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20387 ((INSTANCE) == TIM8_S) || \
20388 ((INSTANCE) == TIM15_S) || \
20389 ((INSTANCE) == TIM16_S) || \
20390 ((INSTANCE) == TIM17_S))
20391
20392/****************** TIM Instances : supporting counting mode selection ********/
20393#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20394 ((INSTANCE) == TIM2_S) || \
20395 ((INSTANCE) == TIM3_S) || \
20396 ((INSTANCE) == TIM4_S) || \
20397 ((INSTANCE) == TIM5_S) || \
20398 ((INSTANCE) == TIM8_S))
20399
20400/****************** TIM Instances : supporting encoder interface **************/
20401#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20402 ((INSTANCE) == TIM2_S) || \
20403 ((INSTANCE) == TIM3_S) || \
20404 ((INSTANCE) == TIM4_S) || \
20405 ((INSTANCE) == TIM5_S) || \
20406 ((INSTANCE) == TIM8_S))
20407
20408/****************** TIM Instances : supporting Hall sensor interface **********/
20409#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20410 ((INSTANCE) == TIM2_S) || \
20411 ((INSTANCE) == TIM3_S) || \
20412 ((INSTANCE) == TIM4_S) || \
20413 ((INSTANCE) == TIM5_S))
20414
20415/**************** TIM Instances : external trigger input available ************/
20416#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20417 ((INSTANCE) == TIM2_S) || \
20418 ((INSTANCE) == TIM3_S) || \
20419 ((INSTANCE) == TIM4_S) || \
20420 ((INSTANCE) == TIM5_S) || \
20421 ((INSTANCE) == TIM8_S))
20422
20423/************* TIM Instances : supporting ETR source selection ***************/
20424#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20425 ((INSTANCE) == TIM2_S) || \
20426 ((INSTANCE) == TIM3_S) || \
20427 ((INSTANCE) == TIM8_S))
20428
20429/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
20430#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20431 ((INSTANCE) == TIM2_S) || \
20432 ((INSTANCE) == TIM3_S) || \
20433 ((INSTANCE) == TIM4_S) || \
20434 ((INSTANCE) == TIM5_S) || \
20435 ((INSTANCE) == TIM6_S) || \
20436 ((INSTANCE) == TIM7_S) || \
20437 ((INSTANCE) == TIM8_S) || \
20438 ((INSTANCE) == TIM15_S))
20439
20440/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
20441#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20442 ((INSTANCE) == TIM2_S) || \
20443 ((INSTANCE) == TIM3_S) || \
20444 ((INSTANCE) == TIM4_S) || \
20445 ((INSTANCE) == TIM5_S) || \
20446 ((INSTANCE) == TIM8_S) || \
20447 ((INSTANCE) == TIM15_S))
20448
20449/****************** TIM Instances : supporting OCxREF clear *******************/
20450#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20451 ((INSTANCE) == TIM2_S) || \
20452 ((INSTANCE) == TIM3_S) || \
20453 ((INSTANCE) == TIM4_S) || \
20454 ((INSTANCE) == TIM5_S) || \
20455 ((INSTANCE) == TIM8_S))
20456
20457/****************** TIM Instances : remapping capability **********************/
20458#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20459 ((INSTANCE) == TIM2_S) || \
20460 ((INSTANCE) == TIM3_S) || \
20461 ((INSTANCE) == TIM8_S) || \
20462 ((INSTANCE) == TIM15_S) || \
20463 ((INSTANCE) == TIM16_S) || \
20464 ((INSTANCE) == TIM17_S))
20465
20466/****************** TIM Instances : supporting repetition counter *************/
20467#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20468 ((INSTANCE) == TIM8_S) || \
20469 ((INSTANCE) == TIM15_S) || \
20470 ((INSTANCE) == TIM16_S) || \
20471 ((INSTANCE) == TIM17_S))
20472
20473/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
20474#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20475 ((INSTANCE) == TIM8_S))
20476
20477/******************* TIM Instances : Timer input XOR function *****************/
20478#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20479 ((INSTANCE) == TIM2_S) || \
20480 ((INSTANCE) == TIM3_S) || \
20481 ((INSTANCE) == TIM4_S) || \
20482 ((INSTANCE) == TIM5_S) || \
20483 ((INSTANCE) == TIM8_S) || \
20484 ((INSTANCE) == TIM15_S))
20485
20486/****************** TIM Instances : Advanced timer instances *******************/
20487#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || \
20488 ((INSTANCE) == TIM8_S))
20489
20490/****************************** TSC Instances *********************************/
20491#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_S)
20492
20493/******************** USART Instances : Synchronous mode **********************/
20494#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || \
20495 ((INSTANCE) == USART2_S) || \
20496 ((INSTANCE) == USART3_S))
20497
20498/******************** UART Instances : Asynchronous mode **********************/
20499#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || \
20500 ((INSTANCE) == USART2_S) || \
20501 ((INSTANCE) == USART3_S) || \
20502 ((INSTANCE) == UART4_S) || \
20503 ((INSTANCE) == UART5_S))
20504
20505/*********************** UART Instances : FIFO mode ***************************/
20506#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || \
20507 ((INSTANCE) == USART2_S) || \
20508 ((INSTANCE) == USART3_S) || \
20509 ((INSTANCE) == UART4_S) || \
20510 ((INSTANCE) == UART5_S) || \
20511 ((INSTANCE) == LPUART1_S))
20512
20513/*********************** UART Instances : SPI Slave mode **********************/
20514#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || \
20515 ((INSTANCE) == USART2_S) || \
20516 ((INSTANCE) == USART3_S))
20517
20518/****************** UART Instances : Auto Baud Rate detection ****************/
20519#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || \
20520 ((INSTANCE) == USART2_S) || \
20521 ((INSTANCE) == USART3_S) || \
20522 ((INSTANCE) == UART4_S) || \
20523 ((INSTANCE) == UART5_S))
20524
20525/****************** UART Instances : Driver Enable *****************/
20526#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || \
20527 ((INSTANCE) == USART2_S) || \
20528 ((INSTANCE) == USART3_S) || \
20529 ((INSTANCE) == UART4_S) || \
20530 ((INSTANCE) == UART5_S) || \
20531 ((INSTANCE) == LPUART1_S))
20532
20533/******************** UART Instances : Half-Duplex mode **********************/
20534#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || \
20535 ((INSTANCE) == USART2_S) || \
20536 ((INSTANCE) == USART3_S) || \
20537 ((INSTANCE) == UART4_S) || \
20538 ((INSTANCE) == UART5_S) || \
20539 ((INSTANCE) == LPUART1_S))
20540
20541/****************** UART Instances : Hardware Flow control ********************/
20542#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || \
20543 ((INSTANCE) == USART2_S) || \
20544 ((INSTANCE) == USART3_S) || \
20545 ((INSTANCE) == UART4_S) || \
20546 ((INSTANCE) == UART5_S) || \
20547 ((INSTANCE) == LPUART1_S))
20548
20549/******************** UART Instances : LIN mode **********************/
20550#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || \
20551 ((INSTANCE) == USART2_S) || \
20552 ((INSTANCE) == USART3_S) || \
20553 ((INSTANCE) == UART4_S) || \
20554 ((INSTANCE) == UART5_S))
20555
20556/******************** UART Instances : Wake-up from Stop mode **********************/
20557#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || \
20558 ((INSTANCE) == USART2_S) || \
20559 ((INSTANCE) == USART3_S) || \
20560 ((INSTANCE) == UART4_S) || \
20561 ((INSTANCE) == UART5_S) || \
20562 ((INSTANCE) == LPUART1_S))
20563
20564/*********************** UART Instances : IRDA mode ***************************/
20565#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || \
20566 ((INSTANCE) == USART2_S) || \
20567 ((INSTANCE) == USART3_S) || \
20568 ((INSTANCE) == UART4_S) || \
20569 ((INSTANCE) == UART5_S))
20570
20571/********************* USART Instances : Smard card mode ***********************/
20572#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || \
20573 ((INSTANCE) == USART2_S) || \
20574 ((INSTANCE) == USART3_S))
20575
20576/******************** LPUART Instance *****************************************/
20577#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1_S)
20578
20579/****************************** IWDG Instances ********************************/
20580#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG_S)
20581
20582/****************************** WWDG Instances ********************************/
20583#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG_S)
20584
20585/****************************** UCPD Instances ********************************/
20586#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1_S)
20587
20588/******************************* USB Instances ********************************/
20589#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_S)
20590#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
20591
20592#else
20593/* Instances allowed from Non-Secure state - only alias Non-Secure */
20594
20595/******************************* ADC Instances ********************************/
20596#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \
20597 ((INSTANCE) == ADC2_NS))
20598
20599#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_NS)
20600
20601#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON_NS)
20602
20603/******************************* AES Instances ********************************/
20604#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES_NS)
20605
20606/******************************** FDCAN Instances *****************************/
20607#define IS_FDCAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN1_NS)
20608
20609#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG_NS)
20610
20611/******************************** COMP Instances ******************************/
20612#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || \
20613 ((INSTANCE) == COMP2_NS))
20614
20615#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON_NS)
20616
20617/******************** COMP Instances with window mode capability **************/
20618#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2_NS)
20619
20620/******************************* CRC Instances ********************************/
20621#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC_NS)
20622
20623/******************************* DAC Instances ********************************/
20624#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1_NS)
20625
20626/****************************** DFSDM Instances *******************************/
20627#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0_NS) || \
20628 ((INSTANCE) == DFSDM1_Filter1_NS) || \
20629 ((INSTANCE) == DFSDM1_Filter2_NS) || \
20630 ((INSTANCE) == DFSDM1_Filter3_NS))
20631
20632#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0_NS) || \
20633 ((INSTANCE) == DFSDM1_Channel1_NS) || \
20634 ((INSTANCE) == DFSDM1_Channel2_NS) || \
20635 ((INSTANCE) == DFSDM1_Channel3_NS))
20636
20637/******************************** DMA Instances *******************************/
20638#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1_NS) || \
20639 ((INSTANCE) == DMA1_Channel2_NS) || \
20640 ((INSTANCE) == DMA1_Channel3_NS) || \
20641 ((INSTANCE) == DMA1_Channel4_NS) || \
20642 ((INSTANCE) == DMA1_Channel5_NS) || \
20643 ((INSTANCE) == DMA1_Channel6_NS) || \
20644 ((INSTANCE) == DMA1_Channel7_NS) || \
20645 ((INSTANCE) == DMA1_Channel8_NS) || \
20646 ((INSTANCE) == DMA2_Channel1_NS) || \
20647 ((INSTANCE) == DMA2_Channel2_NS) || \
20648 ((INSTANCE) == DMA2_Channel3_NS) || \
20649 ((INSTANCE) == DMA2_Channel4_NS) || \
20650 ((INSTANCE) == DMA2_Channel5_NS) || \
20651 ((INSTANCE) == DMA2_Channel6_NS) || \
20652 ((INSTANCE) == DMA2_Channel7_NS) || \
20653 ((INSTANCE) == DMA2_Channel8_NS))
20654
20655/******************************* GPIO Instances *******************************/
20656#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || \
20657 ((INSTANCE) == GPIOB_NS) || \
20658 ((INSTANCE) == GPIOC_NS) || \
20659 ((INSTANCE) == GPIOD_NS) || \
20660 ((INSTANCE) == GPIOE_NS) || \
20661 ((INSTANCE) == GPIOF_NS) || \
20662 ((INSTANCE) == GPIOG_NS) || \
20663 ((INSTANCE) == GPIOH_NS))
20664
20665/******************************* GPIO AF Instances ****************************/
20666/* All GPIO Banks support AF */
20667#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
20668
20669/**************************** GPIO Lock Instances *****************************/
20670/* All GPIO Banks support the Lock mechanism */
20671#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
20672
20673/******************************** I2C Instances *******************************/
20674#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
20675 ((INSTANCE) == I2C2_NS) || \
20676 ((INSTANCE) == I2C3_NS) || \
20677 ((INSTANCE) == I2C4_NS))
20678
20679/****************** I2C Instances : wakeup capability from stop modes *********/
20680#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
20681
20682/****************************** OPAMP Instances *******************************/
20683#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || \
20684 ((INSTANCE) == OPAMP2_NS))
20685
20686#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON_NS)
20687
20688/******************************* OSPI Instances *******************************/
20689#define IS_OSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OCTOSPI1_NS)
20690
20691/******************************** OTFDEC Instances ****************************/
20692#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OTFDEC1_NS)
20693
20694/******************************** OTFDEC Regions Instances ********************/
20695#define IS_OTFDEC_REGION_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_REGION1_NS) || \
20696 ((INSTANCE) == OTFDEC1_REGION2_NS) || \
20697 ((INSTANCE) == OTFDEC1_REGION3_NS) || \
20698 ((INSTANCE) == OTFDEC1_REGION4_NS))
20699
20700/******************************** PKA Instances *******************************/
20701#define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_NS)
20702
20703/******************************* RNG Instances ********************************/
20704#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG_NS)
20705
20706/****************************** RTC Instances *********************************/
20707#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC_NS)
20708
20709/******************************** SAI Instances *******************************/
20710#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || \
20711 ((INSTANCE) == SAI1_Block_B_NS) || \
20712 ((INSTANCE) == SAI2_Block_A_NS) || \
20713 ((INSTANCE) == SAI2_Block_B_NS))
20714
20715/****************************** SDMMC Instances *******************************/
20716#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1_NS)
20717
20718/****************************** SMBUS Instances *******************************/
20719#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
20720
20721/******************************** SPI Instances *******************************/
20722#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
20723 ((INSTANCE) == SPI2_NS) || \
20724 ((INSTANCE) == SPI3_NS))
20725
20726/****************** LPTIM Instances : All supported instances *****************/
20727#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
20728 ((INSTANCE) == LPTIM2_NS) || \
20729 ((INSTANCE) == LPTIM3_NS))
20730
20731#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1_NS)
20732
20733/****************** TIM Instances : All supported instances *******************/
20734#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20735 ((INSTANCE) == TIM2_NS) || \
20736 ((INSTANCE) == TIM3_NS) || \
20737 ((INSTANCE) == TIM4_NS) || \
20738 ((INSTANCE) == TIM5_NS) || \
20739 ((INSTANCE) == TIM6_NS) || \
20740 ((INSTANCE) == TIM7_NS) || \
20741 ((INSTANCE) == TIM8_NS) || \
20742 ((INSTANCE) == TIM15_NS) || \
20743 ((INSTANCE) == TIM16_NS) || \
20744 ((INSTANCE) == TIM17_NS))
20745
20746/****************** TIM Instances : supporting 32 bits counter ****************/
20747#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \
20748 ((INSTANCE) == TIM5_NS))
20749
20750/****************** TIM Instances : supporting the break function *************/
20751#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20752 ((INSTANCE) == TIM8_NS) || \
20753 ((INSTANCE) == TIM15_NS) || \
20754 ((INSTANCE) == TIM16_NS) || \
20755 ((INSTANCE) == TIM17_NS))
20756
20757/************** TIM Instances : supporting Break source selection *************/
20758#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20759 ((INSTANCE) == TIM8_NS) || \
20760 ((INSTANCE) == TIM15_NS) || \
20761 ((INSTANCE) == TIM16_NS) || \
20762 ((INSTANCE) == TIM17_NS))
20763
20764/****************** TIM Instances : supporting 2 break inputs *****************/
20765#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20766 ((INSTANCE) == TIM8_NS))
20767
20768/************* TIM Instances : at least 1 capture/compare channel *************/
20769#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20770 ((INSTANCE) == TIM2_NS) || \
20771 ((INSTANCE) == TIM3_NS) || \
20772 ((INSTANCE) == TIM4_NS) || \
20773 ((INSTANCE) == TIM5_NS) || \
20774 ((INSTANCE) == TIM8_NS) || \
20775 ((INSTANCE) == TIM15_NS) || \
20776 ((INSTANCE) == TIM16_NS) || \
20777 ((INSTANCE) == TIM17_NS))
20778
20779/************ TIM Instances : at least 2 capture/compare channels *************/
20780#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20781 ((INSTANCE) == TIM2_NS) || \
20782 ((INSTANCE) == TIM3_NS) || \
20783 ((INSTANCE) == TIM4_NS) || \
20784 ((INSTANCE) == TIM5_NS) || \
20785 ((INSTANCE) == TIM8_NS) || \
20786 ((INSTANCE) == TIM15_NS))
20787
20788/************ TIM Instances : at least 3 capture/compare channels *************/
20789#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20790 ((INSTANCE) == TIM2_NS) || \
20791 ((INSTANCE) == TIM3_NS) || \
20792 ((INSTANCE) == TIM4_NS) || \
20793 ((INSTANCE) == TIM5_NS) || \
20794 ((INSTANCE) == TIM8_NS))
20795
20796/************ TIM Instances : at least 4 capture/compare channels *************/
20797#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20798 ((INSTANCE) == TIM2_NS) || \
20799 ((INSTANCE) == TIM3_NS) || \
20800 ((INSTANCE) == TIM4_NS) || \
20801 ((INSTANCE) == TIM5_NS) || \
20802 ((INSTANCE) == TIM8_NS))
20803
20804/****************** TIM Instances : at least 5 capture/compare channels *******/
20805#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20806 ((INSTANCE) == TIM8_NS))
20807
20808/****************** TIM Instances : at least 6 capture/compare channels *******/
20809#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20810 ((INSTANCE) == TIM8_NS))
20811
20812/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
20813#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20814 ((INSTANCE) == TIM8_NS) || \
20815 ((INSTANCE) == TIM15_NS) || \
20816 ((INSTANCE) == TIM16_NS) || \
20817 ((INSTANCE) == TIM17_NS))
20818
20819/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
20820#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20821 ((INSTANCE) == TIM2_NS) || \
20822 ((INSTANCE) == TIM3_NS) || \
20823 ((INSTANCE) == TIM4_NS) || \
20824 ((INSTANCE) == TIM5_NS) || \
20825 ((INSTANCE) == TIM6_NS) || \
20826 ((INSTANCE) == TIM7_NS) || \
20827 ((INSTANCE) == TIM8_NS) || \
20828 ((INSTANCE) == TIM15_NS) || \
20829 ((INSTANCE) == TIM16_NS) || \
20830 ((INSTANCE) == TIM17_NS))
20831
20832/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
20833#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20834 ((INSTANCE) == TIM2_NS) || \
20835 ((INSTANCE) == TIM3_NS) || \
20836 ((INSTANCE) == TIM4_NS) || \
20837 ((INSTANCE) == TIM5_NS) || \
20838 ((INSTANCE) == TIM8_NS) || \
20839 ((INSTANCE) == TIM15_NS) || \
20840 ((INSTANCE) == TIM16_NS) || \
20841 ((INSTANCE) == TIM17_NS))
20842
20843/******************** TIM Instances : DMA burst feature ***********************/
20844#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20845 ((INSTANCE) == TIM2_NS) || \
20846 ((INSTANCE) == TIM3_NS) || \
20847 ((INSTANCE) == TIM4_NS) || \
20848 ((INSTANCE) == TIM5_NS) || \
20849 ((INSTANCE) == TIM8_NS) || \
20850 ((INSTANCE) == TIM15_NS) || \
20851 ((INSTANCE) == TIM16_NS) || \
20852 ((INSTANCE) == TIM17_NS))
20853
20854/******************* TIM Instances : output(s) available **********************/
20855#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
20856 ((((INSTANCE) == TIM1_NS) && \
20857 (((CHANNEL) == TIM_CHANNEL_1) || \
20858 ((CHANNEL) == TIM_CHANNEL_2) || \
20859 ((CHANNEL) == TIM_CHANNEL_3) || \
20860 ((CHANNEL) == TIM_CHANNEL_4) || \
20861 ((CHANNEL) == TIM_CHANNEL_5) || \
20862 ((CHANNEL) == TIM_CHANNEL_6))) \
20863 || \
20864 (((INSTANCE) == TIM2_NS) && \
20865 (((CHANNEL) == TIM_CHANNEL_1) || \
20866 ((CHANNEL) == TIM_CHANNEL_2) || \
20867 ((CHANNEL) == TIM_CHANNEL_3) || \
20868 ((CHANNEL) == TIM_CHANNEL_4))) \
20869 || \
20870 (((INSTANCE) == TIM3_NS) && \
20871 (((CHANNEL) == TIM_CHANNEL_1) || \
20872 ((CHANNEL) == TIM_CHANNEL_2) || \
20873 ((CHANNEL) == TIM_CHANNEL_3) || \
20874 ((CHANNEL) == TIM_CHANNEL_4))) \
20875 || \
20876 (((INSTANCE) == TIM4_NS) && \
20877 (((CHANNEL) == TIM_CHANNEL_1) || \
20878 ((CHANNEL) == TIM_CHANNEL_2) || \
20879 ((CHANNEL) == TIM_CHANNEL_3) || \
20880 ((CHANNEL) == TIM_CHANNEL_4))) \
20881 || \
20882 (((INSTANCE) == TIM5_NS) && \
20883 (((CHANNEL) == TIM_CHANNEL_1) || \
20884 ((CHANNEL) == TIM_CHANNEL_2) || \
20885 ((CHANNEL) == TIM_CHANNEL_3) || \
20886 ((CHANNEL) == TIM_CHANNEL_4))) \
20887 || \
20888 (((INSTANCE) == TIM8_NS) && \
20889 (((CHANNEL) == TIM_CHANNEL_1) || \
20890 ((CHANNEL) == TIM_CHANNEL_2) || \
20891 ((CHANNEL) == TIM_CHANNEL_3) || \
20892 ((CHANNEL) == TIM_CHANNEL_4) || \
20893 ((CHANNEL) == TIM_CHANNEL_5) || \
20894 ((CHANNEL) == TIM_CHANNEL_6))) \
20895 || \
20896 (((INSTANCE) == TIM15_NS) && \
20897 (((CHANNEL) == TIM_CHANNEL_1) || \
20898 ((CHANNEL) == TIM_CHANNEL_2))) \
20899 || \
20900 (((INSTANCE) == TIM16_NS) && \
20901 (((CHANNEL) == TIM_CHANNEL_1))) \
20902 || \
20903 (((INSTANCE) == TIM17_NS) && \
20904 (((CHANNEL) == TIM_CHANNEL_1))))
20905
20906/****************** TIM Instances : supporting complementary output(s) ********/
20907#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
20908 ((((INSTANCE) == TIM1_NS) && \
20909 (((CHANNEL) == TIM_CHANNEL_1) || \
20910 ((CHANNEL) == TIM_CHANNEL_2) || \
20911 ((CHANNEL) == TIM_CHANNEL_3))) \
20912 || \
20913 (((INSTANCE) == TIM8_NS) && \
20914 (((CHANNEL) == TIM_CHANNEL_1) || \
20915 ((CHANNEL) == TIM_CHANNEL_2) || \
20916 ((CHANNEL) == TIM_CHANNEL_3))) \
20917 || \
20918 (((INSTANCE) == TIM15_NS) && \
20919 ((CHANNEL) == TIM_CHANNEL_1)) \
20920 || \
20921 (((INSTANCE) == TIM16_NS) && \
20922 ((CHANNEL) == TIM_CHANNEL_1)) \
20923 || \
20924 (((INSTANCE) == TIM17_NS) && \
20925 ((CHANNEL) == TIM_CHANNEL_1)))
20926
20927/****************** TIM Instances : supporting clock division *****************/
20928#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20929 ((INSTANCE) == TIM2_NS) || \
20930 ((INSTANCE) == TIM3_NS) || \
20931 ((INSTANCE) == TIM4_NS) || \
20932 ((INSTANCE) == TIM5_NS) || \
20933 ((INSTANCE) == TIM8_NS) || \
20934 ((INSTANCE) == TIM15_NS) || \
20935 ((INSTANCE) == TIM16_NS) || \
20936 ((INSTANCE) == TIM17_NS))
20937
20938/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
20939#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20940 ((INSTANCE) == TIM2_NS) || \
20941 ((INSTANCE) == TIM3_NS) || \
20942 ((INSTANCE) == TIM4_NS) || \
20943 ((INSTANCE) == TIM5_NS) || \
20944 ((INSTANCE) == TIM8_NS) || \
20945 ((INSTANCE) == TIM15_NS))
20946
20947/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
20948#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20949 ((INSTANCE) == TIM2_NS) || \
20950 ((INSTANCE) == TIM3_NS) || \
20951 ((INSTANCE) == TIM4_NS) || \
20952 ((INSTANCE) == TIM5_NS) || \
20953 ((INSTANCE) == TIM8_NS))
20954
20955/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
20956#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20957 ((INSTANCE) == TIM2_NS) || \
20958 ((INSTANCE) == TIM3_NS) || \
20959 ((INSTANCE) == TIM4_NS) || \
20960 ((INSTANCE) == TIM5_NS) || \
20961 ((INSTANCE) == TIM8_NS) || \
20962 ((INSTANCE) == TIM15_NS))
20963
20964/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
20965#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20966 ((INSTANCE) == TIM2_NS) || \
20967 ((INSTANCE) == TIM3_NS) || \
20968 ((INSTANCE) == TIM4_NS) || \
20969 ((INSTANCE) == TIM5_NS) || \
20970 ((INSTANCE) == TIM8_NS) || \
20971 ((INSTANCE) == TIM15_NS))
20972
20973/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
20974#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20975 ((INSTANCE) == TIM8_NS))
20976
20977/****************** TIM Instances : supporting commutation event generation ***/
20978#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20979 ((INSTANCE) == TIM8_NS) || \
20980 ((INSTANCE) == TIM15_NS) || \
20981 ((INSTANCE) == TIM16_NS) || \
20982 ((INSTANCE) == TIM17_NS))
20983
20984/****************** TIM Instances : supporting counting mode selection ********/
20985#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20986 ((INSTANCE) == TIM2_NS) || \
20987 ((INSTANCE) == TIM3_NS) || \
20988 ((INSTANCE) == TIM4_NS) || \
20989 ((INSTANCE) == TIM5_NS) || \
20990 ((INSTANCE) == TIM8_NS))
20991
20992/****************** TIM Instances : supporting encoder interface **************/
20993#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
20994 ((INSTANCE) == TIM2_NS) || \
20995 ((INSTANCE) == TIM3_NS) || \
20996 ((INSTANCE) == TIM4_NS) || \
20997 ((INSTANCE) == TIM5_NS) || \
20998 ((INSTANCE) == TIM8_NS))
20999
21000/****************** TIM Instances : supporting Hall sensor interface **********/
21001#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
21002 ((INSTANCE) == TIM2_NS) || \
21003 ((INSTANCE) == TIM3_NS) || \
21004 ((INSTANCE) == TIM4_NS) || \
21005 ((INSTANCE) == TIM5_NS))
21006
21007/**************** TIM Instances : external trigger input available ************/
21008#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
21009 ((INSTANCE) == TIM2_NS) || \
21010 ((INSTANCE) == TIM3_NS) || \
21011 ((INSTANCE) == TIM4_NS) || \
21012 ((INSTANCE) == TIM5_NS) || \
21013 ((INSTANCE) == TIM8_NS))
21014
21015/************* TIM Instances : supporting ETR source selection ***************/
21016#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
21017 ((INSTANCE) == TIM2_NS) || \
21018 ((INSTANCE) == TIM3_NS) || \
21019 ((INSTANCE) == TIM8_NS))
21020
21021/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
21022#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
21023 ((INSTANCE) == TIM2_NS) || \
21024 ((INSTANCE) == TIM3_NS) || \
21025 ((INSTANCE) == TIM4_NS) || \
21026 ((INSTANCE) == TIM5_NS) || \
21027 ((INSTANCE) == TIM6_NS) || \
21028 ((INSTANCE) == TIM7_NS) || \
21029 ((INSTANCE) == TIM8_NS) || \
21030 ((INSTANCE) == TIM15_NS))
21031
21032/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
21033#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
21034 ((INSTANCE) == TIM2_NS) || \
21035 ((INSTANCE) == TIM3_NS) || \
21036 ((INSTANCE) == TIM4_NS) || \
21037 ((INSTANCE) == TIM5_NS) || \
21038 ((INSTANCE) == TIM8_NS) || \
21039 ((INSTANCE) == TIM15_NS))
21040
21041/****************** TIM Instances : supporting OCxREF clear *******************/
21042#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
21043 ((INSTANCE) == TIM2_NS) || \
21044 ((INSTANCE) == TIM3_NS) || \
21045 ((INSTANCE) == TIM4_NS) || \
21046 ((INSTANCE) == TIM5_NS) || \
21047 ((INSTANCE) == TIM8_NS))
21048
21049/****************** TIM Instances : remapping capability **********************/
21050#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
21051 ((INSTANCE) == TIM2_NS) || \
21052 ((INSTANCE) == TIM3_NS) || \
21053 ((INSTANCE) == TIM8_NS) || \
21054 ((INSTANCE) == TIM15_NS) || \
21055 ((INSTANCE) == TIM16_NS) || \
21056 ((INSTANCE) == TIM17_NS))
21057
21058/****************** TIM Instances : supporting repetition counter *************/
21059#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
21060 ((INSTANCE) == TIM8_NS) || \
21061 ((INSTANCE) == TIM15_NS) || \
21062 ((INSTANCE) == TIM16_NS) || \
21063 ((INSTANCE) == TIM17_NS))
21064
21065/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
21066#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
21067 ((INSTANCE) == TIM8_NS))
21068
21069/******************* TIM Instances : Timer input XOR function *****************/
21070#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
21071 ((INSTANCE) == TIM2_NS) || \
21072 ((INSTANCE) == TIM3_NS) || \
21073 ((INSTANCE) == TIM4_NS) || \
21074 ((INSTANCE) == TIM5_NS) || \
21075 ((INSTANCE) == TIM8_NS) || \
21076 ((INSTANCE) == TIM15_NS))
21077
21078/****************** TIM Instances : Advanced timer instances *******************/
21079#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
21080 ((INSTANCE) == TIM8_NS))
21081
21082/****************************** TSC Instances *********************************/
21083#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS)
21084
21085/******************** USART Instances : Synchronous mode **********************/
21086#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
21087 ((INSTANCE) == USART2_NS) || \
21088 ((INSTANCE) == USART3_NS))
21089
21090/******************** UART Instances : Asynchronous mode **********************/
21091#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
21092 ((INSTANCE) == USART2_NS) || \
21093 ((INSTANCE) == USART3_NS) || \
21094 ((INSTANCE) == UART4_NS) || \
21095 ((INSTANCE) == UART5_NS))
21096
21097/*********************** UART Instances : FIFO mode ***************************/
21098#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
21099 ((INSTANCE) == USART2_NS) || \
21100 ((INSTANCE) == USART3_NS) || \
21101 ((INSTANCE) == UART4_NS) || \
21102 ((INSTANCE) == UART5_NS) || \
21103 ((INSTANCE) == LPUART1_NS))
21104
21105/*********************** UART Instances : SPI Slave mode **********************/
21106#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
21107 ((INSTANCE) == USART2_NS) || \
21108 ((INSTANCE) == USART3_NS))
21109
21110/****************** UART Instances : Auto Baud Rate detection ****************/
21111#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
21112 ((INSTANCE) == USART2_NS) || \
21113 ((INSTANCE) == USART3_NS) || \
21114 ((INSTANCE) == UART4_NS) || \
21115 ((INSTANCE) == UART5_NS))
21116
21117/****************** UART Instances : Driver Enable *****************/
21118#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
21119 ((INSTANCE) == USART2_NS) || \
21120 ((INSTANCE) == USART3_NS) || \
21121 ((INSTANCE) == UART4_NS) || \
21122 ((INSTANCE) == UART5_NS) || \
21123 ((INSTANCE) == LPUART1_NS))
21124
21125/******************** UART Instances : Half-Duplex mode **********************/
21126#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
21127 ((INSTANCE) == USART2_NS) || \
21128 ((INSTANCE) == USART3_NS) || \
21129 ((INSTANCE) == UART4_NS) || \
21130 ((INSTANCE) == UART5_NS) || \
21131 ((INSTANCE) == LPUART1_NS))
21132
21133/****************** UART Instances : Hardware Flow control ********************/
21134#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
21135 ((INSTANCE) == USART2_NS) || \
21136 ((INSTANCE) == USART3_NS) || \
21137 ((INSTANCE) == UART4_NS) || \
21138 ((INSTANCE) == UART5_NS) || \
21139 ((INSTANCE) == LPUART1_NS))
21140
21141/******************** UART Instances : LIN mode **********************/
21142#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
21143 ((INSTANCE) == USART2_NS) || \
21144 ((INSTANCE) == USART3_NS) || \
21145 ((INSTANCE) == UART4_NS) || \
21146 ((INSTANCE) == UART5_NS))
21147
21148/******************** UART Instances : Wake-up from Stop mode **********************/
21149#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
21150 ((INSTANCE) == USART2_NS) || \
21151 ((INSTANCE) == USART3_NS) || \
21152 ((INSTANCE) == UART4_NS) || \
21153 ((INSTANCE) == UART5_NS) || \
21154 ((INSTANCE) == LPUART1_NS))
21155
21156/*********************** UART Instances : IRDA mode ***************************/
21157#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
21158 ((INSTANCE) == USART2_NS) || \
21159 ((INSTANCE) == USART3_NS) || \
21160 ((INSTANCE) == UART4_NS) || \
21161 ((INSTANCE) == UART5_NS))
21162
21163/********************* USART Instances : Smard card mode ***********************/
21164#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
21165 ((INSTANCE) == USART2_NS) || \
21166 ((INSTANCE) == USART3_NS))
21167
21168/******************** LPUART Instance *****************************************/
21169#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1_NS)
21170
21171/****************************** IWDG Instances ********************************/
21172#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG_NS)
21173
21174/****************************** WWDG Instances ********************************/
21175#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG_NS)
21176
21177/****************************** UCPD Instances ********************************/
21178#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1_NS)
21179
21180/******************************* USB Instances ********************************/
21181#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_NS)
21182#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
21183
21184#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
21185
21186/** @} */ /* End of group STM32L5xx_Peripheral_Exported_macros */
21187
21188/** @} */ /* End of group STM32L562xx */
21189
21190/** @} */ /* End of group ST */
21191
21192#ifdef __cplusplus
21193}
21194#endif
21195
21196#endif /* STM32L562xx_H */
21197
21198/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:56:11 +0100