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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file common/ARMCMx/mpu.h
19 * @brief Cortex-Mx MPU support macros and structures.
20 *
21 * @addtogroup COMMON_ARMCMx_MPU
22 * @{
23 */
24
25#ifndef MPU_H
26#define MPU_H
27
28/* Other layers may include another header named mpu_v7m.h which is perfectly
29 compatible, doing a check here to avoid name conflicts.*/
30#ifndef MPUV7M_H
31
32/*===========================================================================*/
33/* Driver constants. */
34/*===========================================================================*/
35
36/**
37 * @name MPU registers definitions
38 * @{
39 */
40#define MPU_TYPE_SEPARATED (1U << 0U)
41#define MPU_TYPE_DREGION(n) (((n) >> 8U) & 255U)
42#define MPU_TYPE_IREGION(n) (((n) >> 16U) & 255U)
43
44#define MPU_CTRL_ENABLE (1U << 0U)
45#define MPU_CTRL_HFNMIENA (1U << 1U)
46#define MPU_CTRL_PRIVDEFENA (1U << 2U)
47
48#define MPU_RNR_REGION_MASK (255U << 0U)
49#define MPU_RNR_REGION(n) ((n) << 0U)
50
51#define MPU_RBAR_REGION_MASK (15U << 0U)
52#define MPU_RBAR_REGION(n) ((n) << 0U)
53#define MPU_RBAR_VALID (1U << 4U)
54#define MPU_RBAR_ADDR_MASK 0xFFFFFFE0U
55#define MPU_RBAR_ADDR(n) ((n) << 5U)
56
57#define MPU_RASR_ENABLE (1U << 0U)
58#define MPU_RASR_SIZE_MASK (31U << 1U)
59#define MPU_RASR_SIZE(n) ((n) << 1U)
60#define MPU_RASR_SIZE_32 MPU_RASR_SIZE(4U)
61#define MPU_RASR_SIZE_64 MPU_RASR_SIZE(5U)
62#define MPU_RASR_SIZE_128 MPU_RASR_SIZE(6U)
63#define MPU_RASR_SIZE_256 MPU_RASR_SIZE(7U)
64#define MPU_RASR_SIZE_512 MPU_RASR_SIZE(8U)
65#define MPU_RASR_SIZE_1K MPU_RASR_SIZE(9U)
66#define MPU_RASR_SIZE_2K MPU_RASR_SIZE(10U)
67#define MPU_RASR_SIZE_4K MPU_RASR_SIZE(11U)
68#define MPU_RASR_SIZE_8K MPU_RASR_SIZE(12U)
69#define MPU_RASR_SIZE_16K MPU_RASR_SIZE(13U)
70#define MPU_RASR_SIZE_32K MPU_RASR_SIZE(14U)
71#define MPU_RASR_SIZE_64K MPU_RASR_SIZE(15U)
72#define MPU_RASR_SIZE_128K MPU_RASR_SIZE(16U)
73#define MPU_RASR_SIZE_256K MPU_RASR_SIZE(17U)
74#define MPU_RASR_SIZE_512K MPU_RASR_SIZE(18U)
75#define MPU_RASR_SIZE_1M MPU_RASR_SIZE(19U)
76#define MPU_RASR_SIZE_2M MPU_RASR_SIZE(20U)
77#define MPU_RASR_SIZE_4M MPU_RASR_SIZE(21U)
78#define MPU_RASR_SIZE_8M MPU_RASR_SIZE(22U)
79#define MPU_RASR_SIZE_16M MPU_RASR_SIZE(23U)
80#define MPU_RASR_SIZE_32M MPU_RASR_SIZE(24U)
81#define MPU_RASR_SIZE_64M MPU_RASR_SIZE(25U)
82#define MPU_RASR_SIZE_128M MPU_RASR_SIZE(26U)
83#define MPU_RASR_SIZE_256M MPU_RASR_SIZE(27U)
84#define MPU_RASR_SIZE_512M MPU_RASR_SIZE(28U)
85#define MPU_RASR_SIZE_1G MPU_RASR_SIZE(29U)
86#define MPU_RASR_SIZE_2G MPU_RASR_SIZE(30U)
87#define MPU_RASR_SIZE_4G MPU_RASR_SIZE(31U)
88#define MPU_RASR_SRD_MASK (255U << 8U)
89#define MPU_RASR_SRD(n) ((n) << 8U)
90#define MPU_RASR_SRD_ALL (0U << 8U)
91#define MPU_RASR_SRD_DISABLE_SUB0 (1U << 8U)
92#define MPU_RASR_SRD_DISABLE_SUB1 (2U << 8U)
93#define MPU_RASR_SRD_DISABLE_SUB2 (4U << 8U)
94#define MPU_RASR_SRD_DISABLE_SUB3 (8U << 8U)
95#define MPU_RASR_SRD_DISABLE_SUB4 (16U << 8U)
96#define MPU_RASR_SRD_DISABLE_SUB5 (32U << 8U)
97#define MPU_RASR_SRD_DISABLE_SUB6 (64U << 8U)
98#define MPU_RASR_SRD_DISABLE_SUB7 (128U << 8U)
99#define MPU_RASR_ATTR_B (1U << 16U)
100#define MPU_RASR_ATTR_C (1U << 17U)
101#define MPU_RASR_ATTR_S (1U << 18U)
102#define MPU_RASR_ATTR_TEX_MASK (7U << 19U)
103#define MPU_RASR_ATTR_TEX(n) ((n) << 19U)
104#define MPU_RASR_ATTR_AP_MASK (7U << 24U)
105#define MPU_RASR_ATTR_AP(n) ((n) << 24U)
106#define MPU_RASR_ATTR_AP_NA_NA (0U << 24U)
107#define MPU_RASR_ATTR_AP_RW_NA (1U << 24U)
108#define MPU_RASR_ATTR_AP_RW_RO (2U << 24U)
109#define MPU_RASR_ATTR_AP_RW_RW (3U << 24U)
110#define MPU_RASR_ATTR_AP_RO_NA (5U << 24U)
111#define MPU_RASR_ATTR_AP_RO_RO (6U << 24U)
112#define MPU_RASR_ATTR_XN (1U << 28U)
113/** @} */
114
115/**
116 * @name Region attributes
117 * @{
118 */
119#define MPU_RASR_ATTR_STRONGLY_ORDERED (MPU_RASR_ATTR_TEX(0))
120#define MPU_RASR_ATTR_SHARED_DEVICE (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B)
121#define MPU_RASR_ATTR_CACHEABLE_WT_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_C)
122#define MPU_RASR_ATTR_CACHEABLE_WB_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C)
123#define MPU_RASR_ATTR_NON_CACHEABLE (MPU_RASR_ATTR_TEX(1))
124#define MPU_RASR_ATTR_CACHEABLE_WB_WA (MPU_RASR_ATTR_TEX(1) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C)
125#define MPU_RASR_ATTR_NON_SHARED_DEVICE (MPU_RASR_ATTR_TEX(2))
126/** @} */
127
128/**
129 * @name Region identifiers
130 * @{
131 */
132#define MPU_REGION_0 0U
133#define MPU_REGION_1 1U
134#define MPU_REGION_2 2U
135#define MPU_REGION_3 3U
136#define MPU_REGION_4 4U
137#define MPU_REGION_5 5U
138#define MPU_REGION_6 6U
139#define MPU_REGION_7 7U
140/** @} */
141
142/*===========================================================================*/
143/* Driver pre-compile time settings. */
144/*===========================================================================*/
145
146/*===========================================================================*/
147/* Derived constants and error checks. */
148/*===========================================================================*/
149
150/*===========================================================================*/
151/* Driver data structures and types. */
152/*===========================================================================*/
153
154/*===========================================================================*/
155/* Driver macros. */
156/*===========================================================================*/
157
158/**
159 * @brief Enables the MPU.
160 * @note MEMFAULENA is enabled in SCB_SHCSR.
161 *
162 * @param[in] ctrl MPU control modes as defined in @p MPU_CTRL register,
163 * the enable bit is enforced
164 *
165 * @api
166 */
167#define mpuEnable(ctrl) { \
168 MPU->CTRL = ((uint32_t)ctrl) | MPU_CTRL_ENABLE; \
169 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; \
170}
171
172/**
173 * @brief Disables the MPU.
174 * @note MEMFAULENA is disabled in SCB_SHCSR.
175 *
176 * @api
177 */
178#define mpuDisable() { \
179 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; \
180 MPU->CTRL = 0; \
181}
182
183/**
184 * @brief Configures an MPU region.
185 *
186 * @param[in] region the region number
187 * @param[in] address start address of the region, note, there are alignment
188 * constraints
189 * @param[in] attribs attributes mask as defined in @p MPU_RASR register
190 *
191 * @api
192 */
193#define mpuConfigureRegion(region, addr, attribs) { \
194 MPU->RNR = ((uint32_t)region); \
195 MPU->RBAR = ((uint32_t)addr); \
196 MPU->RASR = ((uint32_t)attribs); \
197}
198
199/**
200 * @brief Changes an MPU region base address.
201 *
202 * @param[in] region the region number
203 * @param[in] address start address of the region, note, there are alignment
204 * constraints
205 *
206 * @api
207 */
208#define mpuSetRegionAddress(region, addr) { \
209 MPU->RNR = ((uint32_t)region); \
210 MPU->RBAR = ((uint32_t)addr); \
211}
212
213/*===========================================================================*/
214/* External declarations. */
215/*===========================================================================*/
216
217#ifdef __cplusplus
218extern "C" {
219#endif
220#ifdef __cplusplus
221}
222#endif
223
224#endif /* MPUV7M_H */
225
226#endif /* MPU_H */
227
228/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 09:00:33 +0100