1 files changed, 523 insertions, 0 deletions
diff --git a/lib/chibios/os/common/startup/ARM/devices/LPC214x/lpc214x.h b/lib/chibios/os/common/startup/ARM/devices/LPC214x/lpc214x.h
new file mode 100644
index 000000000..5f08329cf
--- /dev/null
+++ b/lib/chibios/os/common/startup/ARM/devices/LPC214x/lpc214x.h
@@ -0,0 +1,523 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/**
+ * @file    lpc214x.h
+ * @brief   LPC214x register definitions.
+ */
+#ifndef LPC214X_H
+#define LPC214X_H
+typedef volatile uint8_t IOREG8;
+typedef volatile uint16_t IOREG16;
+typedef volatile uint32_t IOREG32;
+/*
+ * System.
+ */
+#define MEMMAP                  (*((IOREG32 *)0xE01FC040))
+#define PCON                    (*((IOREG32 *)0xE01FC0C0))
+#define PCONP                   (*((IOREG32 *)0xE01FC0C4))
+#define VPBDIV                  (*((IOREG32 *)0xE01FC100))
+#define EXTINT                  (*((IOREG32 *)0xE01FC140))
+#define INTWAKE                 (*((IOREG32 *)0xE01FC144))
+#define EXTMODE                 (*((IOREG32 *)0xE01FC148))
+#define EXTPOLAR                (*((IOREG32 *)0xE01FC14C))
+#define RSID                    (*((IOREG32 *)0xE01FC180))
+#define CSPR                    (*((IOREG32 *)0xE01FC184))
+#define SCS                     (*((IOREG32 *)0xE01FC1A0))
+#define VPD_D4                  0
+#define VPD_D1                  1
+#define VPD_D2                  2
+#define VPD_RESERVED            3
+#define PCTIM0                  (1 << 1)
+#define PCTIM1                  (1 << 2)
+#define PCUART0                 (1 << 3)
+#define PCUART1                 (1 << 4)
+#define PCPWM0                  (1 << 5)
+#define PCI2C0                  (1 << 7)
+#define PCSPI0                  (1 << 8)
+#define PCRTC                   (1 << 9)
+#define PCSPI1                  (1 << 10)
+#define PCAD0                   (1 << 12)
+#define PCI2C1                  (1 << 19)
+#define PCAD1                   (1 << 20)
+#define PCUSB                   (1 << 31)
+#define PCALL                   (PCTIM0 | PCTIM1 | PCUART0 | PCUART1 | \
+                                 PCPWM0 | PCI2C0 | PCSPI0 | PCRTC | PCSPI1 | \
+                                 PCAD0 | PCI2C1 | PCAD1 | PCUSB)
+#define EINT0                   1
+#define EINT1                   2
+#define EINT2                   4
+#define EINT3                   8
+#define EXTWAKE0                1
+#define EXTWAKE1                2
+#define EXTWAKE2                4
+#define EXTWAKE3                8
+#define USBWAKE                 0x20
+#define BODWAKE                 0x4000
+#define RTCWAKE                 0x8000
+#define EXTMODE0                1
+#define EXTMODE1                2
+#define EXTMODE2                4
+#define EXTMODE3                8
+#define EXTPOLAR0               1
+#define EXTPOLAR1               2
+#define EXTPOLAR2               4
+#define EXTPOLAR3               8
+typedef struct {
+  IOREG32       PLL_CON;
+  IOREG32       PLL_CFG;
+  IOREG32       PLL_STAT;
+  IOREG32       PLL_FEED;
+} PLL;
+#define PLL0Base                ((PLL *)0xE01FC080)
+#define PLL1Base                ((PLL *)0xE01FC0A0)
+#define PLL0CON                 (PLL0Base->PLL_CON)
+#define PLL0CFG                 (PLL0Base->PLL_CFG)
+#define PLL0STAT                (PLL0Base->PLL_STAT)
+#define PLL0FEED                (PLL0Base->PLL_FEED)
+#define PLL1CON                 (PLL1Base->PLL_CON)
+#define PLL1CFG                 (PLL1Base->PLL_CFG)
+#define PLL1STAT                (PLL1Base->PLL_STAT)
+#define PLL1FEED                (PLL1Base->PLL_FEED)
+/*
+ * Pins.
+ */
+typedef struct {
+  IOREG32       PS_SEL0;
+  IOREG32       PS_SEL1;
+  IOREG32       _dummy[3];
+  IOREG32       PS_SEL2;
+} PS;
+#define PSBase                  ((PS *)0xE002C000)
+#define PINSEL0                 (PSBase->PS_SEL0)
+#define PINSEL1                 (PSBase->PS_SEL1)
+#define PINSEL2                 (PSBase->PS_SEL2)
+/*
+ * VIC
+ */
+#define SOURCE_WDT              0
+#define SOURCE_ARMCore0         2
+#define SOURCE_ARMCore1         3
+#define SOURCE_Timer0           4
+#define SOURCE_Timer1           5
+#define SOURCE_UART0            6
+#define SOURCE_UART1            7
+#define SOURCE_PWM0             8
+#define SOURCE_I2C0             9
+#define SOURCE_SPI0             10
+#define SOURCE_SPI1             11
+#define SOURCE_PLL              12
+#define SOURCE_RTC              13
+#define SOURCE_EINT0            14
+#define SOURCE_EINT1            15
+#define SOURCE_EINT2            16
+#define SOURCE_EINT3            17
+#define SOURCE_ADC0             18
+#define SOURCE_I2C1             19
+#define SOURCE_BOD              20
+#define SOURCE_ADC1             21
+#define SOURCE_USB              22
+#define INTMASK(n)              (1 << (n))
+#define ALLINTMASK (INTMASK(SOURCE_WDT) | INTMASK(SOURCE_ARMCore0) | \
+                    INTMASK(SOURCE_ARMCore1) | INTMASK(SOURCE_Timer0) | \
+                    INTMASK(SOURCE_Timer1) | INTMASK(SOURCE_UART0) | \
+                    INTMASK(SOURCE_UART1) | INTMASK(SOURCE_PWM0) | \
+                    INTMASK(SOURCE_I2C0) | INTMASK(SOURCE_SPI0) | \
+                    INTMASK(SOURCE_SPI1) | INTMASK(SOURCE_PLL) | \
+                    INTMASK(SOURCE_RTC) | INTMASK(SOURCE_EINT0) | \
+                    INTMASK(SOURCE_EINT1) | INTMASK(SOURCE_EINT2) | \
+                    INTMASK(SOURCE_EINT3) | INTMASK(SOURCE_ADC0) | \
+                    INTMASK(SOURCE_I2C1) | INTMASK(SOURCE_BOD) | \
+                    INTMASK(SOURCE_ADC1) | INTMASK(SOURCE_USB))
+typedef struct {
+  IOREG32       VIC_IRQStatus;
+  IOREG32       VIC_FIQStatus;
+  IOREG32       VIC_RawIntr;
+  IOREG32       VIC_IntSelect;
+  IOREG32       VIC_IntEnable;
+  IOREG32       VIC_IntEnClear;
+  IOREG32       VIC_SoftInt;
+  IOREG32       VIC_SoftIntClear;
+  IOREG32       VIC_Protection;
+  IOREG32       unused1[3];
+  IOREG32       VIC_VectAddr;
+  IOREG32       VIC_DefVectAddr;
+  IOREG32       unused2[50];
+  IOREG32       VIC_VectAddrs[16];
+  IOREG32       unused3[48];
+  IOREG32       VIC_VectCntls[16];
+} VIC;
+#define VICBase                 ((VIC *)0xFFFFF000)
+#define VICVectorsBase          ((IOREG32 *)0xFFFFF100)
+#define VICControlsBase         ((IOREG32 *)0xFFFFF200)
+#define VICIRQStatus            (VICBase->VIC_IRQStatus)
+#define VICFIQStatus            (VICBase->VIC_FIQStatus)
+#define VICRawIntr              (VICBase->VIC_RawIntr)
+#define VICIntSelect            (VICBase->VIC_IntSelect)
+#define VICIntEnable            (VICBase->VIC_IntEnable)
+#define VICIntEnClear           (VICBase->VIC_IntEnClear)
+#define VICSoftInt              (VICBase->VIC_SoftInt)
+#define VICSoftIntClear         (VICBase->VIC_SoftIntClear)
+#define VICProtection           (VICBase->VIC_Protection)
+#define VICVectAddr             (VICBase->VIC_VectAddr)
+#define VICDefVectAddr          (VICBase->VIC_DefVectAddr)
+#define VICVectAddrs(n)         (VICBase->VIC_VectAddrs[n])
+#define VICVectCntls(n)         (VICBase->VIC_VectCntls[n])
+/*
+ * MAM.
+ */
+typedef struct {
+  IOREG32       MAM_Control;
+  IOREG32       MAM_Timing;
+} MAM;
+#define MAMBase                 ((MAM *)0xE01FC000)
+#define MAMCR                   (MAMBase->MAM_Control)
+#define MAMTIM                  (MAMBase->MAM_Timing)
+/*
+ * GPIO - FIO.
+ */
+typedef struct {
+  IOREG32       IO_PIN;
+  IOREG32       IO_SET;
+  IOREG32       IO_DIR;
+  IOREG32       IO_CLR;
+} GPIO;
+#define GPIO0Base                ((GPIO *)0xE0028000)
+#define IO0PIN                   (GPIO0Base->IO_PIN)
+#define IO0SET                   (GPIO0Base->IO_SET)
+#define IO0DIR                   (GPIO0Base->IO_DIR)
+#define IO0CLR                   (GPIO0Base->IO_CLR)
+#define GPIO1Base                ((GPIO *)0xE0028010)
+#define IO1PIN                   (GPIO1Base->IO_PIN)
+#define IO1SET                   (GPIO1Base->IO_SET)
+#define IO1DIR                   (GPIO1Base->IO_DIR)
+#define IO1CLR                   (GPIO1Base->IO_CLR)
+typedef struct {
+  IOREG32       FIO_DIR;
+  IOREG32       unused1;
+  IOREG32       unused2;
+  IOREG32       unused3;
+  IOREG32       FIO_MASK;
+  IOREG32       FIO_PIN;
+  IOREG32       FIO_SET;
+  IOREG32       FIO_CLR;
+} FIO;
+#define FIO0Base                ((FIO *)0x3FFFC000)
+#define FIO0DIR                 (FIO0Base->FIO_DIR)
+#define FIO0MASK                (FIO0Base->FIO_MASK)
+#define FIO0PIN                 (FIO0Base->FIO_PIN)
+#define FIO0SET                 (FIO0Base->FIO_SET)
+#define FIO0CLR                 (FIO0Base->FIO_CLR)
+#define FIO1Base                ((FIO *)0x3FFFC020)
+#define FIO1DIR                 (FIO1Base->FIO_DIR)
+#define FIO1MASK                (FIO1Base->FIO_MASK)
+#define FIO1PIN                 (FIO1Base->FIO_PIN)
+#define FIO1SET                 (FIO1Base->FIO_SET)
+#define FIO1CLR                 (FIO1Base->FIO_CLR)
+/*
+ * UART.
+ */
+typedef struct {
+  union {
+    IOREG32     UART_RBR;
+    IOREG32     UART_THR;
+    IOREG32     UART_DLL;
+  };
+  union {
+    IOREG32     UART_IER;
+    IOREG32     UART_DLM;
+  };
+  union {
+    IOREG32     UART_IIR;
+    IOREG32     UART_FCR;
+  };
+  IOREG32       UART_LCR;
+  IOREG32       UART_MCR;
+  IOREG32       UART_LSR;
+  IOREG32       unused18;
+  IOREG32       UART_SCR;
+  IOREG32       UART_ACR;
+  IOREG32       unused24;
+  IOREG32       UART_FDR;
+  IOREG32       unused2C;
+  IOREG32       UART_TER;
+} UART;
+#define U0Base                  ((UART *)0xE000C000)
+#define U0RBR                   (U0Base->UART_RBR)
+#define U0THR                   (U0Base->UART_THR)
+#define U0DLL                   (U0Base->UART_DLL)
+#define U0IER                   (U0Base->UART_IER)
+#define U0DLM                   (U0Base->UART_DLM)
+#define U0IIR                   (U0Base->UART_IIR)
+#define U0FCR                   (U0Base->UART_FCR)
+#define U0LCR                   (U0Base->UART_LCR)
+#define U0LSR                   (U0Base->UART_LSR)
+#define U0SCR                   (U0Base->UART_SCR)
+#define U0ACR                   (U0Base->UART_ACR)
+#define U0FDR                   (U0Base->UART_FDR)
+#define U0TER                   (U0Base->UART_TER)
+#define U1Base                  ((UART *)0xE0010000)
+#define U1RBR                   (U1Base->UART_RBR)
+#define U1THR                   (U1Base->UART_THR)
+#define U1DLL                   (U1Base->UART_DLL)
+#define U1IER                   (U1Base->UART_IER)
+#define U1DLM                   (U1Base->UART_DLM)
+#define U1IIR                   (U1Base->UART_IIR)
+#define U1FCR                   (U1Base->UART_FCR)
+#define U1MCR                   (U1Base->UART_MCR)
+#define U1LCR                   (U1Base->UART_LCR)
+#define U1LSR                   (U1Base->UART_LSR)
+#define U1SCR                   (U1Base->UART_SCR)
+#define U1ACR                   (U1Base->UART_ACR)
+#define U1FDR                   (U1Base->UART_FDR)
+#define U1TER                   (U1Base->UART_TER)
+#define IIR_SRC_MASK    0x0F
+#define IIR_SRC_NONE    0x01
+#define IIR_SRC_TX      0x02
+#define IIR_SRC_RX      0x04
+#define IIR_SRC_ERROR   0x06
+#define IIR_SRC_TIMEOUT 0x0C
+#define IER_RBR         1
+#define IER_THRE        2
+#define IER_STATUS      4
+#define IIR_INT_PENDING 1
+#define LCR_WL5         0
+#define LCR_WL6         1
+#define LCR_WL7         2
+#define LCR_WL8         3
+#define LCR_STOP1       0
+#define LCR_STOP2       4
+#define LCR_NOPARITY    0
+#define LCR_PARITYODD   0x08
+#define LCR_PARITYEVEN  0x18
+#define LCR_PARITYONE   0x28
+#define LCR_PARITYZERO  0x38
+#define LCR_BREAK_ON    0x40
+#define LCR_DLAB        0x80
+#define FCR_ENABLE      1
+#define FCR_RXRESET     2
+#define FCR_TXRESET     4
+#define FCR_TRIGGER0    0
+#define FCR_TRIGGER1    0x40
+#define FCR_TRIGGER2    0x80
+#define FCR_TRIGGER3    0xC0
+#define LSR_RBR_FULL    1
+#define LSR_OVERRUN     2
+#define LSR_PARITY      4
+#define LSR_FRAMING     8
+#define LSR_BREAK       0x10
+#define LSR_THRE        0x20
+#define LSR_TEMT        0x40
+#define LSR_RXFE        0x80
+#define TER_ENABLE      0x80
+/*
+ * SSP.
+ */
+typedef struct {
+  IOREG32       SSP_CR0;
+  IOREG32       SSP_CR1;
+  IOREG32       SSP_DR;
+  IOREG32       SSP_SR;
+  IOREG32       SSP_CPSR;
+  IOREG32       SSP_IMSC;
+  IOREG32       SSP_RIS;
+  IOREG32       SSP_MIS;
+  IOREG32       SSP_ICR;
+} SSP;
+#define SSPBase                 ((SSP *)0xE0068000)
+#define SSPCR0                  (SSPBase->SSP_CR0)
+#define SSPCR1                  (SSPBase->SSP_CR1)
+#define SSPDR                   (SSPBase->SSP_DR)
+#define SSPSR                   (SSPBase->SSP_SR)
+#define SSPCPSR                 (SSPBase->SSP_CPSR)
+#define SSPIMSC                 (SSPBase->SSP_IMSC)
+#define SSPRIS                  (SSPBase->SSP_RIS)
+#define SSPMIS                  (SSPBase->SSP_MIS)
+#define SSPICR                  (SSPBase->SSP_ICR)
+#define CR0_DSSMASK             0x0F
+#define CR0_DSS4BIT             3
+#define CR0_DSS5BIT             4
+#define CR0_DSS6BIT             5
+#define CR0_DSS7BIT             6
+#define CR0_DSS8BIT             7
+#define CR0_DSS9BIT             8
+#define CR0_DSS10BIT            9
+#define CR0_DSS11BIT            0xA
+#define CR0_DSS12BIT            0xB
+#define CR0_DSS13BIT            0xC
+#define CR0_DSS14BIT            0xD
+#define CR0_DSS15BIT            0xE
+#define CR0_DSS16BIT            0xF
+#define CR0_FRFSPI              0
+#define CR0_FRFSSI              0x10
+#define CR0_FRFMW               0x20
+#define CR0_CPOL                0x40
+#define CR0_CPHA                0x80
+#define CR0_CLOCKRATE(n)        ((n) << 8)
+#define CR1_LBM                 1
+#define CR1_SSE                 2
+#define CR1_MS                  4
+#define CR1_SOD                 8
+#define SR_TFE                  1
+#define SR_TNF                  2
+#define SR_RNE                  4
+#define SR_RFF                  8
+#define SR_BSY                  0x10
+#define IMSC_ROR                1
+#define IMSC_RT                 2
+#define IMSC_RX                 4
+#define IMSC_TX                 8
+#define RIS_ROR                 1
+#define RIS_RT                  2
+#define RIS_RX                  4
+#define RIS_TX                  8
+#define MIS_ROR                 1
+#define MIS_RT                  2
+#define MIS_RX                  4
+#define MIS_TX                  8
+#define ICR_ROR                 1
+#define ICR_RT                  2
+/*
+ * Timers/Counters.
+ */
+typedef struct {
+  IOREG32       TC_IR;
+  IOREG32       TC_TCR;
+  IOREG32       TC_TC;
+  IOREG32       TC_PR;
+  IOREG32       TC_PC;
+  IOREG32       TC_MCR;
+  IOREG32       TC_MR0;
+  IOREG32       TC_MR1;
+  IOREG32       TC_MR2;
+  IOREG32       TC_MR3;
+  IOREG32       TC_CCR;
+  IOREG32       TC_CR0;
+  IOREG32       TC_CR1;
+  IOREG32       TC_CR2;
+  IOREG32       TC_CR3;
+  IOREG32       TC_EMR;
+  IOREG32       TC_CTCR;
+} TC;
+#define T0Base                  ((TC *)0xE0004000)
+#define T0IR                    (T0Base->TC_IR)
+#define T0TCR                   (T0Base->TC_TCR)
+#define T0TC                    (T0Base->TC_TC)
+#define T0PR                    (T0Base->TC_PR)
+#define T0PC                    (T0Base->TC_PC)
+#define T0MCR                   (T0Base->TC_MCR)
+#define T0MR0                   (T0Base->TC_MR0)
+#define T0MR1                   (T0Base->TC_MR1)
+#define T0MR2                   (T0Base->TC_MR2)
+#define T0MR3                   (T0Base->TC_MR3)
+#define T0CCR                   (T0Base->TC_CCR)
+#define T0CR0                   (T0Base->TC_CR0)
+#define T0CR1                   (T0Base->TC_CR1)
+#define T0CR2                   (T0Base->TC_CR2)
+#define T0CR3                   (T0Base->TC_CR3)
+#define T0EMR                   (T0Base->TC_EMR)
+#define T0CTCR                  (T0Base->TC_CTCR)
+#define T1Base                  ((TC *)0xE0008000)
+#define T1IR                    (T1Base->TC_IR)
+#define T1TCR                   (T1Base->TC_TCR)
+#define T1TC                    (T1Base->TC_TC)
+#define T1PR                    (T1Base->TC_PR)
+#define T1PC                    (T1Base->TC_PC)
+#define T1MCR                   (T1Base->TC_MCR)
+#define T1MR0                   (T1Base->TC_MR0)
+#define T1MR1                   (T1Base->TC_MR1)
+#define T1MR2                   (T1Base->TC_MR2)
+#define T1MR3                   (T1Base->TC_MR3)
+#define T1CCR                   (T1Base->TC_CCR)
+#define T1CR0                   (T1Base->TC_CR0)
+#define T1CR1                   (T1Base->TC_CR1)
+#define T1CR2                   (T1Base->TC_CR2)
+#define T1CR3                   (T1Base->TC_CR3)
+#define T1EMR                   (T1Base->TC_EMR)
+#define T1CTCR                  (T1Base->TC_CTCR)
+/*
+ * Watchdog.
+ */
+typedef struct {
+  IOREG32       WD_MOD;
+  IOREG32       WD_TC;
+  IOREG32       WD_FEED;
+  IOREG32       WD_TV;
+} WD;
+#define WDBase                  ((WD *)0xE0000000)
+#define WDMOD                   (WDBase->WD_MOD)
+#define WDTC                    (WDBase->WD_TC)
+#define WDFEED                  (WDBase->WD_FEED)
+#define WDTV                    (WDBase->WD_TV)
+/*
+ * DAC.
+ */
+#define DACR                    (*((IOREG32 *)0xE006C000))
+#endif /* LPC214X_H */

diff --git a/lib/chibios/os/common/startup/ARM/devices/LPC214x/lpc214x.h b/lib/chibios/os/common/startup/ARM/devices/LPC214x/lpc214x.h new file mode 100644 index 000000000..5f08329cf --- /dev/null +++ b/lib/chibios/os/common/startup/ARM/devices/LPC214x/lpc214x.h
@@ -0,0 +1,523 @@
	1	/*
	2	ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
	3
	4	Licensed under the Apache License, Version 2.0 (the "License");
	5	you may not use this file except in compliance with the License.
	6	You may obtain a copy of the License at
	7
	8	http://www.apache.org/licenses/LICENSE-2.0
	9
	10	Unless required by applicable law or agreed to in writing, software
	11	distributed under the License is distributed on an "AS IS" BASIS,
	12	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
	13	See the License for the specific language governing permissions and
	14	limitations under the License.
	15	*/
	16
	17	/**
	18	* @file lpc214x.h
	19	* @brief LPC214x register definitions.
	20	*/
	21
	22	#ifndef LPC214X_H
	23	#define LPC214X_H
	24
	25	typedef volatile uint8_t IOREG8;
	26	typedef volatile uint16_t IOREG16;
	27	typedef volatile uint32_t IOREG32;
	28
	29	/*
	30	* System.
	31	*/
	32	#define MEMMAP (((IOREG32 )0xE01FC040))
	33	#define PCON (((IOREG32 )0xE01FC0C0))
	34	#define PCONP (((IOREG32 )0xE01FC0C4))
	35	#define VPBDIV (((IOREG32 )0xE01FC100))
	36	#define EXTINT (((IOREG32 )0xE01FC140))
	37	#define INTWAKE (((IOREG32 )0xE01FC144))
	38	#define EXTMODE (((IOREG32 )0xE01FC148))
	39	#define EXTPOLAR (((IOREG32 )0xE01FC14C))
	40	#define RSID (((IOREG32 )0xE01FC180))
	41	#define CSPR (((IOREG32 )0xE01FC184))
	42	#define SCS (((IOREG32 )0xE01FC1A0))
	43
	44	#define VPD_D4 0
	45	#define VPD_D1 1
	46	#define VPD_D2 2
	47	#define VPD_RESERVED 3
	48
	49	#define PCTIM0 (1 << 1)
	50	#define PCTIM1 (1 << 2)
	51	#define PCUART0 (1 << 3)
	52	#define PCUART1 (1 << 4)
	53	#define PCPWM0 (1 << 5)
	54	#define PCI2C0 (1 << 7)
	55	#define PCSPI0 (1 << 8)
	56	#define PCRTC (1 << 9)
	57	#define PCSPI1 (1 << 10)
	58	#define PCAD0 (1 << 12)
	59	#define PCI2C1 (1 << 19)
	60	#define PCAD1 (1 << 20)
	61	#define PCUSB (1 << 31)
	62	#define PCALL (PCTIM0 \| PCTIM1 \| PCUART0 \| PCUART1 \| \
	63	PCPWM0 \| PCI2C0 \| PCSPI0 \| PCRTC \| PCSPI1 \| \
	64	PCAD0 \| PCI2C1 \| PCAD1 \| PCUSB)
	65
	66	#define EINT0 1
	67	#define EINT1 2
	68	#define EINT2 4
	69	#define EINT3 8
	70
	71	#define EXTWAKE0 1
	72	#define EXTWAKE1 2
	73	#define EXTWAKE2 4
	74	#define EXTWAKE3 8
	75	#define USBWAKE 0x20
	76	#define BODWAKE 0x4000
	77	#define RTCWAKE 0x8000
	78
	79	#define EXTMODE0 1
	80	#define EXTMODE1 2
	81	#define EXTMODE2 4
	82	#define EXTMODE3 8
	83
	84	#define EXTPOLAR0 1
	85	#define EXTPOLAR1 2
	86	#define EXTPOLAR2 4
	87	#define EXTPOLAR3 8
	88
	89	typedef struct {
	90	IOREG32 PLL_CON;
	91	IOREG32 PLL_CFG;
	92	IOREG32 PLL_STAT;
	93	IOREG32 PLL_FEED;
	94	} PLL;
	95
	96	#define PLL0Base ((PLL *)0xE01FC080)
	97	#define PLL1Base ((PLL *)0xE01FC0A0)
	98	#define PLL0CON (PLL0Base->PLL_CON)
	99	#define PLL0CFG (PLL0Base->PLL_CFG)
	100	#define PLL0STAT (PLL0Base->PLL_STAT)
	101	#define PLL0FEED (PLL0Base->PLL_FEED)
	102	#define PLL1CON (PLL1Base->PLL_CON)
	103	#define PLL1CFG (PLL1Base->PLL_CFG)
	104	#define PLL1STAT (PLL1Base->PLL_STAT)
	105	#define PLL1FEED (PLL1Base->PLL_FEED)
	106
	107	/*
	108	* Pins.
	109	*/
	110	typedef struct {
	111	IOREG32 PS_SEL0;
	112	IOREG32 PS_SEL1;
	113	IOREG32 _dummy[3];
	114	IOREG32 PS_SEL2;
	115	} PS;
	116
	117	#define PSBase ((PS *)0xE002C000)
	118	#define PINSEL0 (PSBase->PS_SEL0)
	119	#define PINSEL1 (PSBase->PS_SEL1)
	120	#define PINSEL2 (PSBase->PS_SEL2)
	121
	122	/*
	123	* VIC
	124	*/
	125	#define SOURCE_WDT 0
	126	#define SOURCE_ARMCore0 2
	127	#define SOURCE_ARMCore1 3
	128	#define SOURCE_Timer0 4
	129	#define SOURCE_Timer1 5
	130	#define SOURCE_UART0 6
	131	#define SOURCE_UART1 7
	132	#define SOURCE_PWM0 8
	133	#define SOURCE_I2C0 9
	134	#define SOURCE_SPI0 10
	135	#define SOURCE_SPI1 11
	136	#define SOURCE_PLL 12
	137	#define SOURCE_RTC 13
	138	#define SOURCE_EINT0 14
	139	#define SOURCE_EINT1 15
	140	#define SOURCE_EINT2 16
	141	#define SOURCE_EINT3 17
	142	#define SOURCE_ADC0 18
	143	#define SOURCE_I2C1 19
	144	#define SOURCE_BOD 20
	145	#define SOURCE_ADC1 21
	146	#define SOURCE_USB 22
	147
	148	#define INTMASK(n) (1 << (n))
	149	#define ALLINTMASK (INTMASK(SOURCE_WDT) \| INTMASK(SOURCE_ARMCore0) \| \
	150	INTMASK(SOURCE_ARMCore1) \| INTMASK(SOURCE_Timer0) \| \
	151	INTMASK(SOURCE_Timer1) \| INTMASK(SOURCE_UART0) \| \
	152	INTMASK(SOURCE_UART1) \| INTMASK(SOURCE_PWM0) \| \
	153	INTMASK(SOURCE_I2C0) \| INTMASK(SOURCE_SPI0) \| \
	154	INTMASK(SOURCE_SPI1) \| INTMASK(SOURCE_PLL) \| \
	155	INTMASK(SOURCE_RTC) \| INTMASK(SOURCE_EINT0) \| \
	156	INTMASK(SOURCE_EINT1) \| INTMASK(SOURCE_EINT2) \| \
	157	INTMASK(SOURCE_EINT3) \| INTMASK(SOURCE_ADC0) \| \
	158	INTMASK(SOURCE_I2C1) \| INTMASK(SOURCE_BOD) \| \
	159	INTMASK(SOURCE_ADC1) \| INTMASK(SOURCE_USB))
	160
	161	typedef struct {
	162	IOREG32 VIC_IRQStatus;
	163	IOREG32 VIC_FIQStatus;
	164	IOREG32 VIC_RawIntr;
	165	IOREG32 VIC_IntSelect;
	166	IOREG32 VIC_IntEnable;
	167	IOREG32 VIC_IntEnClear;
	168	IOREG32 VIC_SoftInt;
	169	IOREG32 VIC_SoftIntClear;
	170	IOREG32 VIC_Protection;
	171	IOREG32 unused1[3];
	172	IOREG32 VIC_VectAddr;
	173	IOREG32 VIC_DefVectAddr;
	174	IOREG32 unused2[50];
	175	IOREG32 VIC_VectAddrs[16];
	176	IOREG32 unused3[48];
	177	IOREG32 VIC_VectCntls[16];
	178	} VIC;
	179
	180	#define VICBase ((VIC *)0xFFFFF000)
	181	#define VICVectorsBase ((IOREG32 *)0xFFFFF100)
	182	#define VICControlsBase ((IOREG32 *)0xFFFFF200)
	183
	184	#define VICIRQStatus (VICBase->VIC_IRQStatus)
	185	#define VICFIQStatus (VICBase->VIC_FIQStatus)
	186	#define VICRawIntr (VICBase->VIC_RawIntr)
	187	#define VICIntSelect (VICBase->VIC_IntSelect)
	188	#define VICIntEnable (VICBase->VIC_IntEnable)
	189	#define VICIntEnClear (VICBase->VIC_IntEnClear)
	190	#define VICSoftInt (VICBase->VIC_SoftInt)
	191	#define VICSoftIntClear (VICBase->VIC_SoftIntClear)
	192	#define VICProtection (VICBase->VIC_Protection)
	193	#define VICVectAddr (VICBase->VIC_VectAddr)
	194	#define VICDefVectAddr (VICBase->VIC_DefVectAddr)
	195
	196	#define VICVectAddrs(n) (VICBase->VIC_VectAddrs[n])
	197	#define VICVectCntls(n) (VICBase->VIC_VectCntls[n])
	198
	199	/*
	200	* MAM.
	201	*/
	202	typedef struct {
	203	IOREG32 MAM_Control;
	204	IOREG32 MAM_Timing;
	205	} MAM;
	206
	207	#define MAMBase ((MAM *)0xE01FC000)
	208	#define MAMCR (MAMBase->MAM_Control)
	209	#define MAMTIM (MAMBase->MAM_Timing)
	210
	211	/*
	212	* GPIO - FIO.
	213	*/
	214	typedef struct {
	215	IOREG32 IO_PIN;
	216	IOREG32 IO_SET;
	217	IOREG32 IO_DIR;
	218	IOREG32 IO_CLR;
	219	} GPIO;
	220
	221	#define GPIO0Base ((GPIO *)0xE0028000)
	222	#define IO0PIN (GPIO0Base->IO_PIN)
	223	#define IO0SET (GPIO0Base->IO_SET)
	224	#define IO0DIR (GPIO0Base->IO_DIR)
	225	#define IO0CLR (GPIO0Base->IO_CLR)
	226
	227	#define GPIO1Base ((GPIO *)0xE0028010)
	228	#define IO1PIN (GPIO1Base->IO_PIN)
	229	#define IO1SET (GPIO1Base->IO_SET)
	230	#define IO1DIR (GPIO1Base->IO_DIR)
	231	#define IO1CLR (GPIO1Base->IO_CLR)
	232
	233	typedef struct {
	234	IOREG32 FIO_DIR;
	235	IOREG32 unused1;
	236	IOREG32 unused2;
	237	IOREG32 unused3;
	238	IOREG32 FIO_MASK;
	239	IOREG32 FIO_PIN;
	240	IOREG32 FIO_SET;
	241	IOREG32 FIO_CLR;
	242	} FIO;
	243
	244	#define FIO0Base ((FIO *)0x3FFFC000)
	245	#define FIO0DIR (FIO0Base->FIO_DIR)
	246	#define FIO0MASK (FIO0Base->FIO_MASK)
	247	#define FIO0PIN (FIO0Base->FIO_PIN)
	248	#define FIO0SET (FIO0Base->FIO_SET)
	249	#define FIO0CLR (FIO0Base->FIO_CLR)
	250
	251	#define FIO1Base ((FIO *)0x3FFFC020)
	252	#define FIO1DIR (FIO1Base->FIO_DIR)
	253	#define FIO1MASK (FIO1Base->FIO_MASK)
	254	#define FIO1PIN (FIO1Base->FIO_PIN)
	255	#define FIO1SET (FIO1Base->FIO_SET)
	256	#define FIO1CLR (FIO1Base->FIO_CLR)
	257
	258	/*
	259	* UART.
	260	*/
	261	typedef struct {
	262	union {
	263	IOREG32 UART_RBR;
	264	IOREG32 UART_THR;
	265	IOREG32 UART_DLL;
	266	};
	267	union {
	268	IOREG32 UART_IER;
	269	IOREG32 UART_DLM;
	270	};
	271	union {
	272	IOREG32 UART_IIR;
	273	IOREG32 UART_FCR;
	274	};
	275	IOREG32 UART_LCR;
	276	IOREG32 UART_MCR;
	277	IOREG32 UART_LSR;
	278	IOREG32 unused18;
	279	IOREG32 UART_SCR;
	280	IOREG32 UART_ACR;
	281	IOREG32 unused24;
	282	IOREG32 UART_FDR;
	283	IOREG32 unused2C;
	284	IOREG32 UART_TER;
	285	} UART;
	286
	287	#define U0Base ((UART *)0xE000C000)
	288	#define U0RBR (U0Base->UART_RBR)
	289	#define U0THR (U0Base->UART_THR)
	290	#define U0DLL (U0Base->UART_DLL)
	291	#define U0IER (U0Base->UART_IER)
	292	#define U0DLM (U0Base->UART_DLM)
	293	#define U0IIR (U0Base->UART_IIR)
	294	#define U0FCR (U0Base->UART_FCR)
	295	#define U0LCR (U0Base->UART_LCR)
	296	#define U0LSR (U0Base->UART_LSR)
	297	#define U0SCR (U0Base->UART_SCR)
	298	#define U0ACR (U0Base->UART_ACR)
	299	#define U0FDR (U0Base->UART_FDR)
	300	#define U0TER (U0Base->UART_TER)
	301
	302	#define U1Base ((UART *)0xE0010000)
	303	#define U1RBR (U1Base->UART_RBR)
	304	#define U1THR (U1Base->UART_THR)
	305	#define U1DLL (U1Base->UART_DLL)
	306	#define U1IER (U1Base->UART_IER)
	307	#define U1DLM (U1Base->UART_DLM)
	308	#define U1IIR (U1Base->UART_IIR)
	309	#define U1FCR (U1Base->UART_FCR)
	310	#define U1MCR (U1Base->UART_MCR)
	311	#define U1LCR (U1Base->UART_LCR)
	312	#define U1LSR (U1Base->UART_LSR)
	313	#define U1SCR (U1Base->UART_SCR)
	314	#define U1ACR (U1Base->UART_ACR)
	315	#define U1FDR (U1Base->UART_FDR)
	316	#define U1TER (U1Base->UART_TER)
	317
	318	#define IIR_SRC_MASK 0x0F
	319	#define IIR_SRC_NONE 0x01
	320	#define IIR_SRC_TX 0x02
	321	#define IIR_SRC_RX 0x04
	322	#define IIR_SRC_ERROR 0x06
	323	#define IIR_SRC_TIMEOUT 0x0C
	324
	325	#define IER_RBR 1
	326	#define IER_THRE 2
	327	#define IER_STATUS 4
	328
	329	#define IIR_INT_PENDING 1
	330
	331	#define LCR_WL5 0
	332	#define LCR_WL6 1
	333	#define LCR_WL7 2
	334	#define LCR_WL8 3
	335	#define LCR_STOP1 0
	336	#define LCR_STOP2 4
	337	#define LCR_NOPARITY 0
	338	#define LCR_PARITYODD 0x08
	339	#define LCR_PARITYEVEN 0x18
	340	#define LCR_PARITYONE 0x28
	341	#define LCR_PARITYZERO 0x38
	342	#define LCR_BREAK_ON 0x40
	343	#define LCR_DLAB 0x80
	344
	345	#define FCR_ENABLE 1
	346	#define FCR_RXRESET 2
	347	#define FCR_TXRESET 4
	348	#define FCR_TRIGGER0 0
	349	#define FCR_TRIGGER1 0x40
	350	#define FCR_TRIGGER2 0x80
	351	#define FCR_TRIGGER3 0xC0
	352
	353	#define LSR_RBR_FULL 1
	354	#define LSR_OVERRUN 2
	355	#define LSR_PARITY 4
	356	#define LSR_FRAMING 8
	357	#define LSR_BREAK 0x10
	358	#define LSR_THRE 0x20
	359	#define LSR_TEMT 0x40
	360	#define LSR_RXFE 0x80
	361
	362	#define TER_ENABLE 0x80
	363
	364	/*
	365	* SSP.
	366	*/
	367	typedef struct {
	368	IOREG32 SSP_CR0;
	369	IOREG32 SSP_CR1;
	370	IOREG32 SSP_DR;
	371	IOREG32 SSP_SR;
	372	IOREG32 SSP_CPSR;
	373	IOREG32 SSP_IMSC;
	374	IOREG32 SSP_RIS;
	375	IOREG32 SSP_MIS;
	376	IOREG32 SSP_ICR;
	377	} SSP;
	378
	379	#define SSPBase ((SSP *)0xE0068000)
	380	#define SSPCR0 (SSPBase->SSP_CR0)
	381	#define SSPCR1 (SSPBase->SSP_CR1)
	382	#define SSPDR (SSPBase->SSP_DR)
	383	#define SSPSR (SSPBase->SSP_SR)
	384	#define SSPCPSR (SSPBase->SSP_CPSR)
	385	#define SSPIMSC (SSPBase->SSP_IMSC)
	386	#define SSPRIS (SSPBase->SSP_RIS)
	387	#define SSPMIS (SSPBase->SSP_MIS)
	388	#define SSPICR (SSPBase->SSP_ICR)
	389
	390	#define CR0_DSSMASK 0x0F
	391	#define CR0_DSS4BIT 3
	392	#define CR0_DSS5BIT 4
	393	#define CR0_DSS6BIT 5
	394	#define CR0_DSS7BIT 6
	395	#define CR0_DSS8BIT 7
	396	#define CR0_DSS9BIT 8
	397	#define CR0_DSS10BIT 9
	398	#define CR0_DSS11BIT 0xA
	399	#define CR0_DSS12BIT 0xB
	400	#define CR0_DSS13BIT 0xC
	401	#define CR0_DSS14BIT 0xD
	402	#define CR0_DSS15BIT 0xE
	403	#define CR0_DSS16BIT 0xF
	404	#define CR0_FRFSPI 0
	405	#define CR0_FRFSSI 0x10
	406	#define CR0_FRFMW 0x20
	407	#define CR0_CPOL 0x40
	408	#define CR0_CPHA 0x80
	409	#define CR0_CLOCKRATE(n) ((n) << 8)
	410
	411	#define CR1_LBM 1
	412	#define CR1_SSE 2
	413	#define CR1_MS 4
	414	#define CR1_SOD 8
	415
	416	#define SR_TFE 1
	417	#define SR_TNF 2
	418	#define SR_RNE 4
	419	#define SR_RFF 8
	420	#define SR_BSY 0x10
	421
	422	#define IMSC_ROR 1
	423	#define IMSC_RT 2
	424	#define IMSC_RX 4
	425	#define IMSC_TX 8
	426
	427	#define RIS_ROR 1
	428	#define RIS_RT 2
	429	#define RIS_RX 4
	430	#define RIS_TX 8
	431
	432	#define MIS_ROR 1
	433	#define MIS_RT 2
	434	#define MIS_RX 4
	435	#define MIS_TX 8
	436
	437	#define ICR_ROR 1
	438	#define ICR_RT 2
	439
	440	/*
	441	* Timers/Counters.
	442	*/
	443	typedef struct {
	444	IOREG32 TC_IR;
	445	IOREG32 TC_TCR;
	446	IOREG32 TC_TC;
	447	IOREG32 TC_PR;
	448	IOREG32 TC_PC;
	449	IOREG32 TC_MCR;
	450	IOREG32 TC_MR0;
	451	IOREG32 TC_MR1;
	452	IOREG32 TC_MR2;
	453	IOREG32 TC_MR3;
	454	IOREG32 TC_CCR;
	455	IOREG32 TC_CR0;
	456	IOREG32 TC_CR1;
	457	IOREG32 TC_CR2;
	458	IOREG32 TC_CR3;
	459	IOREG32 TC_EMR;
	460	IOREG32 TC_CTCR;
	461	} TC;
	462
	463	#define T0Base ((TC *)0xE0004000)
	464	#define T0IR (T0Base->TC_IR)
	465	#define T0TCR (T0Base->TC_TCR)
	466	#define T0TC (T0Base->TC_TC)
	467	#define T0PR (T0Base->TC_PR)
	468	#define T0PC (T0Base->TC_PC)
	469	#define T0MCR (T0Base->TC_MCR)
	470	#define T0MR0 (T0Base->TC_MR0)
	471	#define T0MR1 (T0Base->TC_MR1)
	472	#define T0MR2 (T0Base->TC_MR2)
	473	#define T0MR3 (T0Base->TC_MR3)
	474	#define T0CCR (T0Base->TC_CCR)
	475	#define T0CR0 (T0Base->TC_CR0)
	476	#define T0CR1 (T0Base->TC_CR1)
	477	#define T0CR2 (T0Base->TC_CR2)
	478	#define T0CR3 (T0Base->TC_CR3)
	479	#define T0EMR (T0Base->TC_EMR)
	480	#define T0CTCR (T0Base->TC_CTCR)
	481
	482	#define T1Base ((TC *)0xE0008000)
	483	#define T1IR (T1Base->TC_IR)
	484	#define T1TCR (T1Base->TC_TCR)
	485	#define T1TC (T1Base->TC_TC)
	486	#define T1PR (T1Base->TC_PR)
	487	#define T1PC (T1Base->TC_PC)
	488	#define T1MCR (T1Base->TC_MCR)
	489	#define T1MR0 (T1Base->TC_MR0)
	490	#define T1MR1 (T1Base->TC_MR1)
	491	#define T1MR2 (T1Base->TC_MR2)
	492	#define T1MR3 (T1Base->TC_MR3)
	493	#define T1CCR (T1Base->TC_CCR)
	494	#define T1CR0 (T1Base->TC_CR0)
	495	#define T1CR1 (T1Base->TC_CR1)
	496	#define T1CR2 (T1Base->TC_CR2)
	497	#define T1CR3 (T1Base->TC_CR3)
	498	#define T1EMR (T1Base->TC_EMR)
	499	#define T1CTCR (T1Base->TC_CTCR)
	500
	501	/*
	502	* Watchdog.
	503	*/
	504	typedef struct {
	505	IOREG32 WD_MOD;
	506	IOREG32 WD_TC;
	507	IOREG32 WD_FEED;
	508	IOREG32 WD_TV;
	509	} WD;
	510
	511	#define WDBase ((WD *)0xE0000000)
	512	#define WDMOD (WDBase->WD_MOD)
	513	#define WDTC (WDBase->WD_TC)
	514	#define WDFEED (WDBase->WD_FEED)
	515	#define WDTV (WDBase->WD_TV)
	516
	517	/*
	518	* DAC.
	519	*/
	520	#define DACR (((IOREG32 )0xE006C000))
	521
	522	#endif /* LPC214X_H */
	523