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-rw-r--r--lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560B50.ld165
-rw-r--r--lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560B60.ld165
-rw-r--r--lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560B64.ld165
-rw-r--r--lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560D40.ld165
-rw-r--r--lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560P50.ld165
-rw-r--r--lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC56EC74.ld159
6 files changed, 984 insertions, 0 deletions
diff --git a/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560B50.ld b/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560B50.ld
new file mode 100644
index 000000000..52d6fe834
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560B50.ld
@@ -0,0 +1,165 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * SPC560B50 memory setup.
19 */
20MEMORY
21{
22 flash : org = 0x00000000, len = 512k
23 dataflash : org = 0x00800000, len = 64k
24 ram : org = 0x40000000, len = 32k
25}
26
27OPTION ("-e=_reset_address")
28
29SECTIONS
30{
31 .boot0 ALIGN(16) :
32 {
33 *(.boot)
34 *(.handlers)
35 *(.crt0)
36 } > flash
37
38 .vectors ALIGN(0x800) :
39 {
40 /* The vectors table requires a 2kB alignment.*/
41 *(.vectors)
42 } > flash
43
44 .ivors ALIGN(0x1000) :
45 {
46 /* The IVORs table requires a 4kB alignment.*/
47 __ivpr_base__ = .;
48 *(.ivors)
49 } > flash
50
51 constructors ALIGN(4) :
52 {
53 PROVIDE(__init_array_start = .);
54 "*(.init_array.*)"
55 *(.init_array)
56 PROVIDE(__init_array_end = .);
57 } > flash
58
59 destructors ALIGN(4) :
60 {
61 PROVIDE(__fini_array_start = .);
62 *(.fini_array)
63 "*(.fini_array.*)"
64 PROVIDE(__fini_array_end = .);
65 } > flash
66
67 .vletext ALIGN(16) :
68 {
69 *(.vletext)
70 "*(.vletext.*)"
71 } > flash
72
73 .text ALIGN(16) :
74 {
75 *(.text)
76 "*(.text.*)"
77 } > flash
78
79 .rodata ALIGN(16) :
80 {
81 *(.rodata)
82 "*(.rodata.*)"
83 *(.rodata1)
84 } > flash
85
86 .sdata2 ALIGN(16) :
87 {
88 __sdata2_start__ = . + 0x8000;
89 *(.sdata2)
90 "*(.sdata2.*)"
91 *(.sbss2)
92 "*(.sbss2.*)"
93 } > flash
94
95 .stacks ALIGN(16) :
96 {
97 . = ALIGN(8);
98 __irq_stack_base__ = .;
99 . += __irq_stack_size__;
100 . = ALIGN(8);
101 __irq_stack_end__ = .;
102 __process_stack_base__ = .;
103 __main_thread_stack_base__ = .;
104 . += __process_stack_size__;
105 . = ALIGN(8);
106 __process_stack_end__ = .;
107 __main_thread_stack_end__ = .;
108 } > ram
109
110 .romdatastart ALIGN(16) :
111 {
112 __romdata_start__ = .;
113 } > flash
114
115 .data ALIGN(4) : AT(__romdata_start__)
116 {
117 __data_start__ = .;
118 *(.data)
119 "*(.data.*)"
120 . = ALIGN(4);
121 *(.ramtext)
122 . = ALIGN(4);
123 __data_end__ = .;
124 } > ram
125
126 __romsdata_start__ = (__data_end__ - __data_start__) + __romdata_start__;
127
128 .sdata ALIGN(4) : AT(__romsdata_start__)
129 {
130 __sdata_start__ = . + 0x8000;
131 *(.sdata)
132 "*(.sdata.*)"
133 } > ram
134
135 .sbss ALIGN(4) :
136 {
137 __bss_start__ = .;
138 *(.sbss)
139 "*(.sbss.*)"
140 *(.scommon)
141 } > ram
142
143 .bss ALIGN(4) :
144 {
145 *(.bss)
146 "*(.bss.*)"
147 *(COMMON)
148 __bss_end__ = .;
149 } > ram
150
151 __flash_size__ = SIZEOF(flash);
152 __flash_start__ = ADDR(flash);
153 __flash_end__ = ENDADDR(flash);
154
155 __dataflash_size__ = SIZEOF(dataflash);
156 __dataflash_start__ = ADDR(dataflash);
157 __dataflash_end__ = ENDADDR(dataflash);
158
159 __ram_size__ = SIZEOF(ram);
160 __ram_start__ = ADDR(ram);
161 __ram_end__ = ENDADDR(ram);
162
163 __heap_base__ = __bss_end__;
164 __heap_end__ = __ram_end__;
165}
diff --git a/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560B60.ld b/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560B60.ld
new file mode 100644
index 000000000..b74fb0624
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560B60.ld
@@ -0,0 +1,165 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * SPC560B60 memory setup.
19 */
20MEMORY
21{
22 flash : org = 0x00000000, len = 1024k
23 dataflash : org = 0x00800000, len = 64k
24 ram : org = 0x40000000, len = 80k
25}
26
27OPTION ("-e=_reset_address")
28
29SECTIONS
30{
31 .boot0 ALIGN(16) :
32 {
33 *(.boot)
34 *(.handlers)
35 *(.crt0)
36 } > flash
37
38 .vectors ALIGN(0x800) :
39 {
40 /* The vectors table requires a 2kB alignment.*/
41 *(.vectors)
42 } > flash
43
44 .ivors ALIGN(0x1000) :
45 {
46 /* The IVORs table requires a 4kB alignment.*/
47 __ivpr_base__ = .;
48 *(.ivors)
49 } > flash
50
51 constructors ALIGN(4) :
52 {
53 PROVIDE(__init_array_start = .);
54 "*(.init_array.*)"
55 *(.init_array)
56 PROVIDE(__init_array_end = .);
57 } > flash
58
59 destructors ALIGN(4) :
60 {
61 PROVIDE(__fini_array_start = .);
62 *(.fini_array)
63 "*(.fini_array.*)"
64 PROVIDE(__fini_array_end = .);
65 } > flash
66
67 .vletext ALIGN(16) :
68 {
69 *(.vletext)
70 "*(.vletext.*)"
71 } > flash
72
73 .text ALIGN(16) :
74 {
75 *(.text)
76 "*(.text.*)"
77 } > flash
78
79 .rodata ALIGN(16) :
80 {
81 *(.rodata)
82 "*(.rodata.*)"
83 *(.rodata1)
84 } > flash
85
86 .sdata2 ALIGN(16) :
87 {
88 __sdata2_start__ = . + 0x8000;
89 *(.sdata2)
90 "*(.sdata2.*)"
91 *(.sbss2)
92 "*(.sbss2.*)"
93 } > flash
94
95 .stacks ALIGN(16) :
96 {
97 . = ALIGN(8);
98 __irq_stack_base__ = .;
99 . += __irq_stack_size__;
100 . = ALIGN(8);
101 __irq_stack_end__ = .;
102 __process_stack_base__ = .;
103 __main_thread_stack_base__ = .;
104 . += __process_stack_size__;
105 . = ALIGN(8);
106 __process_stack_end__ = .;
107 __main_thread_stack_end__ = .;
108 } > ram
109
110 .romdatastart ALIGN(16) :
111 {
112 __romdata_start__ = .;
113 } > flash
114
115 .data ALIGN(4) : AT(__romdata_start__)
116 {
117 __data_start__ = .;
118 *(.data)
119 "*(.data.*)"
120 . = ALIGN(4);
121 *(.ramtext)
122 . = ALIGN(4);
123 __data_end__ = .;
124 } > ram
125
126 __romsdata_start__ = (__data_end__ - __data_start__) + __romdata_start__;
127
128 .sdata ALIGN(4) : AT(__romsdata_start__)
129 {
130 __sdata_start__ = . + 0x8000;
131 *(.sdata)
132 "*(.sdata.*)"
133 } > ram
134
135 .sbss ALIGN(4) :
136 {
137 __bss_start__ = .;
138 *(.sbss)
139 "*(.sbss.*)"
140 *(.scommon)
141 } > ram
142
143 .bss ALIGN(4) :
144 {
145 *(.bss)
146 "*(.bss.*)"
147 *(COMMON)
148 __bss_end__ = .;
149 } > ram
150
151 __flash_size__ = SIZEOF(flash);
152 __flash_start__ = ADDR(flash);
153 __flash_end__ = ENDADDR(flash);
154
155 __dataflash_size__ = SIZEOF(dataflash);
156 __dataflash_start__ = ADDR(dataflash);
157 __dataflash_end__ = ENDADDR(dataflash);
158
159 __ram_size__ = SIZEOF(ram);
160 __ram_start__ = ADDR(ram);
161 __ram_end__ = ENDADDR(ram);
162
163 __heap_base__ = __bss_end__;
164 __heap_end__ = __ram_end__;
165}
diff --git a/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560B64.ld b/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560B64.ld
new file mode 100644
index 000000000..8d6f08247
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560B64.ld
@@ -0,0 +1,165 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * SPC560B64 memory setup.
19 */
20MEMORY
21{
22 flash : org = 0x00000000, len = 1536k
23 dataflash : org = 0x00800000, len = 64k
24 ram : org = 0x40000000, len = 96k
25}
26
27OPTION ("-e=_reset_address")
28
29SECTIONS
30{
31 .boot0 ALIGN(16) :
32 {
33 *(.boot)
34 *(.handlers)
35 *(.crt0)
36 } > flash
37
38 .vectors ALIGN(0x800) :
39 {
40 /* The vectors table requires a 2kB alignment.*/
41 *(.vectors)
42 } > flash
43
44 .ivors ALIGN(0x1000) :
45 {
46 /* The IVORs table requires a 4kB alignment.*/
47 __ivpr_base__ = .;
48 *(.ivors)
49 } > flash
50
51 constructors ALIGN(4) :
52 {
53 PROVIDE(__init_array_start = .);
54 "*(.init_array.*)"
55 *(.init_array)
56 PROVIDE(__init_array_end = .);
57 } > flash
58
59 destructors ALIGN(4) :
60 {
61 PROVIDE(__fini_array_start = .);
62 *(.fini_array)
63 "*(.fini_array.*)"
64 PROVIDE(__fini_array_end = .);
65 } > flash
66
67 .vletext ALIGN(16) :
68 {
69 *(.vletext)
70 "*(.vletext.*)"
71 } > flash
72
73 .text ALIGN(16) :
74 {
75 *(.text)
76 "*(.text.*)"
77 } > flash
78
79 .rodata ALIGN(16) :
80 {
81 *(.rodata)
82 "*(.rodata.*)"
83 *(.rodata1)
84 } > flash
85
86 .sdata2 ALIGN(16) :
87 {
88 __sdata2_start__ = . + 0x8000;
89 *(.sdata2)
90 "*(.sdata2.*)"
91 *(.sbss2)
92 "*(.sbss2.*)"
93 } > flash
94
95 .stacks ALIGN(16) :
96 {
97 . = ALIGN(8);
98 __irq_stack_base__ = .;
99 . += __irq_stack_size__;
100 . = ALIGN(8);
101 __irq_stack_end__ = .;
102 __process_stack_base__ = .;
103 __main_thread_stack_base__ = .;
104 . += __process_stack_size__;
105 . = ALIGN(8);
106 __process_stack_end__ = .;
107 __main_thread_stack_end__ = .;
108 } > ram
109
110 .romdatastart ALIGN(16) :
111 {
112 __romdata_start__ = .;
113 } > flash
114
115 .data ALIGN(4) : AT(__romdata_start__)
116 {
117 __data_start__ = .;
118 *(.data)
119 "*(.data.*)"
120 . = ALIGN(4);
121 *(.ramtext)
122 . = ALIGN(4);
123 __data_end__ = .;
124 } > ram
125
126 __romsdata_start__ = (__data_end__ - __data_start__) + __romdata_start__;
127
128 .sdata ALIGN(4) : AT(__romsdata_start__)
129 {
130 __sdata_start__ = . + 0x8000;
131 *(.sdata)
132 "*(.sdata.*)"
133 } > ram
134
135 .sbss ALIGN(4) :
136 {
137 __bss_start__ = .;
138 *(.sbss)
139 "*(.sbss.*)"
140 *(.scommon)
141 } > ram
142
143 .bss ALIGN(4) :
144 {
145 *(.bss)
146 "*(.bss.*)"
147 *(COMMON)
148 __bss_end__ = .;
149 } > ram
150
151 __flash_size__ = SIZEOF(flash);
152 __flash_start__ = ADDR(flash);
153 __flash_end__ = ENDADDR(flash);
154
155 __dataflash_size__ = SIZEOF(dataflash);
156 __dataflash_start__ = ADDR(dataflash);
157 __dataflash_end__ = ENDADDR(dataflash);
158
159 __ram_size__ = SIZEOF(ram);
160 __ram_start__ = ADDR(ram);
161 __ram_end__ = ENDADDR(ram);
162
163 __heap_base__ = __bss_end__;
164 __heap_end__ = __ram_end__;
165}
diff --git a/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560D40.ld b/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560D40.ld
new file mode 100644
index 000000000..c6af24b2c
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560D40.ld
@@ -0,0 +1,165 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * SPC560D40 memory setup.
19 */
20MEMORY
21{
22 flash : org = 0x00000000, len = 256k
23 dataflash : org = 0x00800000, len = 64k
24 ram : org = 0x40000000, len = 16k
25}
26
27OPTION ("-e=_reset_address")
28
29SECTIONS
30{
31 .boot0 ALIGN(16) :
32 {
33 *(.boot)
34 *(.handlers)
35 *(.crt0)
36 } > flash
37
38 .vectors ALIGN(0x800) :
39 {
40 /* The vectors table requires a 2kB alignment.*/
41 *(.vectors)
42 } > flash
43
44 .ivors ALIGN(0x1000) :
45 {
46 /* The IVORs table requires a 4kB alignment.*/
47 __ivpr_base__ = .;
48 *(.ivors)
49 } > flash
50
51 constructors ALIGN(4) :
52 {
53 PROVIDE(__init_array_start = .);
54 "*(.init_array.*)"
55 *(.init_array)
56 PROVIDE(__init_array_end = .);
57 } > flash
58
59 destructors ALIGN(4) :
60 {
61 PROVIDE(__fini_array_start = .);
62 *(.fini_array)
63 "*(.fini_array.*)"
64 PROVIDE(__fini_array_end = .);
65 } > flash
66
67 .vletext ALIGN(16) :
68 {
69 *(.vletext)
70 "*(.vletext.*)"
71 } > flash
72
73 .text ALIGN(16) :
74 {
75 *(.text)
76 "*(.text.*)"
77 } > flash
78
79 .rodata ALIGN(16) :
80 {
81 *(.rodata)
82 "*(.rodata.*)"
83 *(.rodata1)
84 } > flash
85
86 .sdata2 ALIGN(16) :
87 {
88 __sdata2_start__ = . + 0x8000;
89 *(.sdata2)
90 "*(.sdata2.*)"
91 *(.sbss2)
92 "*(.sbss2.*)"
93 } > flash
94
95 .stacks ALIGN(16) :
96 {
97 . = ALIGN(8);
98 __irq_stack_base__ = .;
99 . += __irq_stack_size__;
100 . = ALIGN(8);
101 __irq_stack_end__ = .;
102 __process_stack_base__ = .;
103 __main_thread_stack_base__ = .;
104 . += __process_stack_size__;
105 . = ALIGN(8);
106 __process_stack_end__ = .;
107 __main_thread_stack_end__ = .;
108 } > ram
109
110 .romdatastart ALIGN(16) :
111 {
112 __romdata_start__ = .;
113 } > flash
114
115 .data ALIGN(4) : AT(__romdata_start__)
116 {
117 __data_start__ = .;
118 *(.data)
119 "*(.data.*)"
120 . = ALIGN(4);
121 *(.ramtext)
122 . = ALIGN(4);
123 __data_end__ = .;
124 } > ram
125
126 __romsdata_start__ = (__data_end__ - __data_start__) + __romdata_start__;
127
128 .sdata ALIGN(4) : AT(__romsdata_start__)
129 {
130 __sdata_start__ = . + 0x8000;
131 *(.sdata)
132 "*(.sdata.*)"
133 } > ram
134
135 .sbss ALIGN(4) :
136 {
137 __bss_start__ = .;
138 *(.sbss)
139 "*(.sbss.*)"
140 *(.scommon)
141 } > ram
142
143 .bss ALIGN(4) :
144 {
145 *(.bss)
146 "*(.bss.*)"
147 *(COMMON)
148 __bss_end__ = .;
149 } > ram
150
151 __flash_size__ = SIZEOF(flash);
152 __flash_start__ = ADDR(flash);
153 __flash_end__ = ENDADDR(flash);
154
155 __dataflash_size__ = SIZEOF(dataflash);
156 __dataflash_start__ = ADDR(dataflash);
157 __dataflash_end__ = ENDADDR(dataflash);
158
159 __ram_size__ = SIZEOF(ram);
160 __ram_start__ = ADDR(ram);
161 __ram_end__ = ENDADDR(ram);
162
163 __heap_base__ = __bss_end__;
164 __heap_end__ = __ram_end__;
165}
diff --git a/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560P50.ld b/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560P50.ld
new file mode 100644
index 000000000..9b5dcd85a
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC560P50.ld
@@ -0,0 +1,165 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * SPC560P50 memory setup.
19 */
20MEMORY
21{
22 flash : org = 0x00000000, len = 512k
23 dataflash : org = 0x00800000, len = 64k
24 ram : org = 0x40000000, len = 40k
25}
26
27OPTION ("-e=_reset_address")
28
29SECTIONS
30{
31 .boot0 ALIGN(16) :
32 {
33 *(.boot)
34 *(.handlers)
35 *(.crt0)
36 } > flash
37
38 .vectors ALIGN(0x800) :
39 {
40 /* The vectors table requires a 2kB alignment.*/
41 *(.vectors)
42 } > flash
43
44 .ivors ALIGN(0x1000) :
45 {
46 /* The IVORs table requires a 4kB alignment.*/
47 __ivpr_base__ = .;
48 *(.ivors)
49 } > flash
50
51 constructors ALIGN(4) :
52 {
53 PROVIDE(__init_array_start = .);
54 "*(.init_array.*)"
55 *(.init_array)
56 PROVIDE(__init_array_end = .);
57 } > flash
58
59 destructors ALIGN(4) :
60 {
61 PROVIDE(__fini_array_start = .);
62 *(.fini_array)
63 "*(.fini_array.*)"
64 PROVIDE(__fini_array_end = .);
65 } > flash
66
67 .vletext ALIGN(16) :
68 {
69 *(.vletext)
70 "*(.vletext.*)"
71 } > flash
72
73 .text ALIGN(16) :
74 {
75 *(.text)
76 "*(.text.*)"
77 } > flash
78
79 .rodata ALIGN(16) :
80 {
81 *(.rodata)
82 "*(.rodata.*)"
83 *(.rodata1)
84 } > flash
85
86 .sdata2 ALIGN(16) :
87 {
88 __sdata2_start__ = . + 0x8000;
89 *(.sdata2)
90 "*(.sdata2.*)"
91 *(.sbss2)
92 "*(.sbss2.*)"
93 } > flash
94
95 .stacks ALIGN(16) :
96 {
97 . = ALIGN(8);
98 __irq_stack_base__ = .;
99 . += __irq_stack_size__;
100 . = ALIGN(8);
101 __irq_stack_end__ = .;
102 __process_stack_base__ = .;
103 __main_thread_stack_base__ = .;
104 . += __process_stack_size__;
105 . = ALIGN(8);
106 __process_stack_end__ = .;
107 __main_thread_stack_end__ = .;
108 } > ram
109
110 .romdatastart ALIGN(16) :
111 {
112 __romdata_start__ = .;
113 } > flash
114
115 .data ALIGN(4) : AT(__romdata_start__)
116 {
117 __data_start__ = .;
118 *(.data)
119 "*(.data.*)"
120 . = ALIGN(4);
121 *(.ramtext)
122 . = ALIGN(4);
123 __data_end__ = .;
124 } > ram
125
126 __romsdata_start__ = (__data_end__ - __data_start__) + __romdata_start__;
127
128 .sdata ALIGN(4) : AT(__romsdata_start__)
129 {
130 __sdata_start__ = . + 0x8000;
131 *(.sdata)
132 "*(.sdata.*)"
133 } > ram
134
135 .sbss ALIGN(4) :
136 {
137 __bss_start__ = .;
138 *(.sbss)
139 "*(.sbss.*)"
140 *(.scommon)
141 } > ram
142
143 .bss ALIGN(4) :
144 {
145 *(.bss)
146 "*(.bss.*)"
147 *(COMMON)
148 __bss_end__ = .;
149 } > ram
150
151 __flash_size__ = SIZEOF(flash);
152 __flash_start__ = ADDR(flash);
153 __flash_end__ = ENDADDR(flash);
154
155 __dataflash_size__ = SIZEOF(dataflash);
156 __dataflash_start__ = ADDR(dataflash);
157 __dataflash_end__ = ENDADDR(dataflash);
158
159 __ram_size__ = SIZEOF(ram);
160 __ram_start__ = ADDR(ram);
161 __ram_end__ = ENDADDR(ram);
162
163 __heap_base__ = __bss_end__;
164 __heap_end__ = __ram_end__;
165}
diff --git a/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC56EC74.ld b/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC56EC74.ld
new file mode 100644
index 000000000..730500512
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/compilers/GHS/ld/SPC56EC74.ld
@@ -0,0 +1,159 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * SPC56EC74 memory setup.
19 */
20MEMORY
21{
22 flash : org = 0x00000000, len = 3M
23 dataflash : org = 0x00800000, len = 64k
24 ram : org = 0x40000000, len = 256k
25}
26
27OPTION ("-e=_reset_address")
28
29SECTIONS
30{
31 .boot0 ALIGN(16) :
32 {
33 __ivpr_base__ = .;
34 *(.boot)
35 *(.handlers)
36 *(.crt0)
37 } > flash
38
39 .vectors ALIGN(0x800) :
40 {
41 /* The vectors table requires a 2kB alignment.*/
42 *(.vectors)
43 } > flash
44
45 constructors ALIGN(4) :
46 {
47 PROVIDE(__init_array_start = .);
48 "*(.init_array.*)"
49 *(.init_array)
50 PROVIDE(__init_array_end = .);
51 } > flash
52
53 destructors ALIGN(4) :
54 {
55 PROVIDE(__fini_array_start = .);
56 *(.fini_array)
57 "*(.fini_array.*)"
58 PROVIDE(__fini_array_end = .);
59 } > flash
60
61 .vletext ALIGN(16) :
62 {
63 *(.vletext)
64 "*(.vletext.*)"
65 } > flash
66
67 .text ALIGN(16) :
68 {
69 *(.text)
70 "*(.text.*)"
71 } > flash
72
73 .rodata ALIGN(16) :
74 {
75 *(.rodata)
76 "*(.rodata.*)"
77 *(.rodata1)
78 } > flash
79
80 .sdata2 ALIGN(16) :
81 {
82 __sdata2_start__ = . + 0x8000;
83 *(.sdata2)
84 "*(.sdata2.*)"
85 *(.sbss2)
86 "*(.sbss2.*)"
87 } > flash
88
89 .stacks ALIGN(16) :
90 {
91 . = ALIGN(8);
92 __irq_stack_base__ = .;
93 . += __irq_stack_size__;
94 . = ALIGN(8);
95 __irq_stack_end__ = .;
96 __process_stack_base__ = .;
97 __main_thread_stack_base__ = .;
98 . += __process_stack_size__;
99 . = ALIGN(8);
100 __process_stack_end__ = .;
101 __main_thread_stack_end__ = .;
102 } > ram
103
104 .romdatastart ALIGN(16) :
105 {
106 __romdata_start__ = .;
107 } > flash
108
109 .data ALIGN(4) : AT(__romdata_start__)
110 {
111 __data_start__ = .;
112 *(.data)
113 "*(.data.*)"
114 . = ALIGN(4);
115 *(.ramtext)
116 . = ALIGN(4);
117 __data_end__ = .;
118 } > ram
119
120 __romsdata_start__ = (__data_end__ - __data_start__) + __romdata_start__;
121
122 .sdata ALIGN(4) : AT(__romsdata_start__)
123 {
124 __sdata_start__ = . + 0x8000;
125 *(.sdata)
126 "*(.sdata.*)"
127 } > ram
128
129 .sbss ALIGN(4) :
130 {
131 __bss_start__ = .;
132 *(.sbss)
133 "*(.sbss.*)"
134 *(.scommon)
135 } > ram
136
137 .bss ALIGN(4) :
138 {
139 *(.bss)
140 "*(.bss.*)"
141 *(COMMON)
142 __bss_end__ = .;
143 } > ram
144
145 __flash_size__ = SIZEOF(flash);
146 __flash_start__ = ADDR(flash);
147 __flash_end__ = ENDADDR(flash);
148
149 __dataflash_size__ = SIZEOF(dataflash);
150 __dataflash_start__ = ADDR(dataflash);
151 __dataflash_end__ = ENDADDR(dataflash);
152
153 __ram_size__ = SIZEOF(ram);
154 __ram_start__ = ADDR(ram);
155 __ram_end__ = ENDADDR(ram);
156
157 __heap_base__ = __bss_end__;
158 __heap_end__ = __ram_end__;
159}
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 18:51:53 +0100