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diff --git a/lib/chibios/os/hal/ports/SPC5/SPC560Dxx/xpc560d.h b/lib/chibios/os/hal/ports/SPC5/SPC560Dxx/xpc560d.h
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1/****************************************************************************
2 * PROJECT : MPC5602Dx
3 *
4 * FILE : MPC5602Dx_2.03.h
5 *
6 * DESCRIPTION : This is the header file describing the register
7 * set for MPC560xBx family of MCUs. It supports the following devices:
8 *
9 * - MPC5602D
10 *
11 *
12 * COPYRIGHT :(c) 2012, Freescale
13 *
14 * VERSION : 2.03
15 * DATE : 06.05.2012
16 * AUTHOR : r23668
17 * HISTORY : New header Based Upon MPC5607B and MPC5606BK. Version 1.04
18 * 0.12 Oct 2011: MPC5606BK
19 * 1.0 Alpha Nov 2011 : MPC560xBx combined header file. Out for Review and comments.
20 * 1.01 Jan 2012: Checked with both MPC5607x and MPC5606Bx, no comments recieved.
21 * 1.04 Mar 2012: Supersedes MPC5607B ver 1.03 and becomes Ver 1.04.
22 * 2.01 Added missing ADC registers CIMR1, CIMR2, PSR1, NCMR1, NCMR2
23 * 2.02 Added more missing ADC registers CEOCFR2, DMAR1/2, PSR1, DSDR, CDR, CWSEL8-11, CWENR2, AWORR2, NCMR2, JCMR2
24 * 2.03 Corrected RM discrepancies.
25 *****************************************************************
26 * Copyright:
27 * Freescale Semiconductor, INC. All Rights Reserved.
28 * You are hereby granted a copyright license to use, modify, and
29 * distribute the SOFTWARE so long as this entire notice is
30 * retained without alteration in any modified and/or redistributed
31 * versions, and that such modified versions are clearly identified
32 * as such. No licenses are granted by implication, estoppel or
33 * otherwise under any patents or trademarks of Freescale
34 * Semiconductor, Inc. This software is provided on an "AS IS"
35 * basis and without warranty.
36 *
37 * To the maximum extent permitted by applicable law, Freescale
38 * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
39 * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
40 * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
41 * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
42 * AND ANY ACCOMPANYING WRITTEN MATERIALS.
43 *
44 * To the maximum extent permitted by applicable law, IN NO EVENT
45 * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
46 * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
47 * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
48 * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
49 *
50 * Freescale Semiconductor assumes no responsibility for the
51 * maintenance and support of this software
52 *
53 ******************************************************************/
54
55/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
56
57/*****************************************************************
58* Example instantiation and use:
59*
60* <MODULE>.<REGISTER>.B.<BIT> = 1;
61* <MODULE>.<REGISTER>.R = 0x10000000;
62*
63******************************************************************/
64
65#ifndef _JDP_H_
66#define _JDP_H_
67
68#include "typedefs.h"
69
70#ifdef __cplusplus
71extern "C" {
72#endif
73
74#ifdef __MWERKS__
75#pragma push
76#pragma ANSI_strict off
77#endif
78
79/****************************************************************************/
80/* MODULE : CFLASH (base address - 0xC3F8_8000) */
81/****************************************************************************/
82 struct CFLASH_tag {
83 union { /* Module Configuration (Base+0x0000) */
84 vuint32_t R;
85 struct {
86 vuint32_t EDC:1;
87 vuint32_t:4;
88 vuint32_t SIZE:3;
89 vuint32_t:1;
90 vuint32_t LAS:3;
91 vuint32_t:3;
92 vuint32_t MAS:1;
93 vuint32_t EER:1;
94 vuint32_t RWE:1;
95 vuint32_t:2;
96 vuint32_t PEAS:1;
97 vuint32_t DONE:1;
98 vuint32_t PEG:1;
99 vuint32_t:4;
100 vuint32_t PGM:1;
101 vuint32_t PSUS:1;
102 vuint32_t ERS:1;
103 vuint32_t ESUS:1;
104 vuint32_t EHV:1;
105 } B;
106 } MCR;
107
108 union { /* Low/Mid address block locking (Base+0x0004) */
109 vuint32_t R;
110 struct {
111 vuint32_t LME:1;
112 vuint32_t:10;
113 vuint32_t TSLK:1;
114 vuint32_t:2;
115 vuint32_t MLK:2;
116 vuint32_t:10;
117 vuint32_t LLK:6;
118 } B;
119 } LML;
120
121 union { /* High address space block locking (Base+0x0008)*/
122 vuint32_t R;
123 struct {
124 vuint32_t HBE:1;
125 vuint32_t :27;
126 vuint32_t HLK:4;
127 } B;
128 } HBL;
129
130 union { /* Secondary Low/Mid block lock (Base+0x000C)*/
131 vuint32_t R;
132 struct {
133 vuint32_t SLE:1;
134 vuint32_t:10;
135 vuint32_t STSLK:1;
136 vuint32_t:2;
137 vuint32_t SMK:2;
138 vuint32_t:10;
139 vuint32_t SLK:6;
140 } B;
141 } SLL;
142
143 union { /* Low/Mid address space block sel (Base+0x0010)*/
144 vuint32_t R;
145 struct {
146 vuint32_t:14;
147 vuint32_t MSL:2;
148 vuint32_t:10;
149 vuint32_t LSL:6;
150 } B;
151 } LMS;
152
153 union { /* High address Space block select (Base+0x0014)*/
154 vuint32_t R;
155 struct {
156 vuint32_t:28;
157 vuint32_t HSL:4;
158 } B;
159 } HBS;
160
161 union { /* Address Register (Base+0x0018) */
162 vuint32_t R;
163 struct {
164 vuint32_t:9;
165 vuint32_t ADD:20;
166 vuint32_t:3;
167 } B;
168 } ADR;
169
170 /* Note the following 3 registers, BIU[0..2] are mirrored to */
171 /* the code flash configuraiton PFCR[0..2] registers */
172 /* To make it easier to code, the BIU registers have been */
173 /* replaced with the PFCR registers in this header file! */
174 /* A commented out BIU register is shown for reference! */
175
176
177 union { /* CFLASH Configuration 0 (Base+0x001C) */
178 vuint32_t R;
179 struct {
180 vuint32_t BK0_APC:5;
181 vuint32_t BK0_WWSC:5;
182 vuint32_t BK0_RWSC:5;
183 vuint32_t BK0_RWWC2:1;
184 vuint32_t BK0_RWWC1:1;
185 vuint32_t :7;
186 vuint32_t BK0_RWWC0:1;
187 vuint32_t B0_P0_BCFG:2;
188 vuint32_t B0_P0_DPFE:1;
189 vuint32_t B0_P0_IPFE:1;
190 vuint32_t B0_P0_PFLM:2;
191 vuint32_t B0_P0_BFE:1;
192 } B;
193 } PFCR0;
194
195 /* Commented out Bus Interface Unit 0 (Base+0x001C) */
196 /*union {
197
198 vuint32_t R;
199
200 struct {
201
202 vuint32_t BI0:32;
203
204 } B;
205
206 } BIU0; */
207 union { /* CFLASH Configuration Register 1 (Base+0x0020)*/
208 vuint32_t R;
209 struct {
210 vuint32_t BK1_APC:5;
211 vuint32_t BK1_WWSC:5;
212 vuint32_t BK1_RWSC:5;
213 vuint32_t BK1_RWWC2:1;
214 vuint32_t BK1_RWWC1:1;
215 vuint32_t:7;
216 vuint32_t BK1_RWWC0:1;
217 vuint32_t:6;
218 vuint32_t B1_P0_BFE:1;
219 } B;
220 } PFCR1;
221 /* Commented out Bus Interface Unit 1 (Base+0x0020) */
222 /*union {
223
224 vuint32_t R;
225
226 struct {
227
228 vuint32_t BI1:32;
229
230 } B;
231
232 } BIU1; */
233
234
235 union { /* CFLASH Access Protection (Base+0x0024) */
236 vuint32_t R;
237 struct {
238 vuint32_t:13;
239 vuint32_t M2PFD:1;
240 vuint32_t:1;
241 vuint32_t M0PFD:1;
242 vuint32_t:10;
243 vuint32_t M2AP:2;
244 vuint32_t:2;
245 vuint32_t M0AP:2;
246 } B;
247 } PFAPR;
248 /* Commented out Bus Interface Unit 2 (Base+0x0024) */
249 /*union {
250
251 vuint32_t R;
252
253 struct {
254
255 vuint32_t BI2:32;
256
257 } B;
258
259 } BIU2; */
260
261
262 vuint8_t CFLASH_reserved0[20]; /* Reserved 20 Bytes (Base+0x0028-0x003B) */
263
264 union { /* User Test 0 (Base+0x003C) */
265 vuint32_t R;
266 struct {
267 vuint32_t UTE:1;
268 vuint32_t:7;
269 vuint32_t DSI:8;
270 vuint32_t:10;
271 vuint32_t MRE:1;
272 vuint32_t MRV:1;
273 vuint32_t EIE:1;
274 vuint32_t AIS:1;
275 vuint32_t AIE:1;
276 vuint32_t AID:1;
277 } B;
278 } UT0;
279
280 union { /* User Test 1 (Base+0x0040) */
281 vuint32_t R;
282 struct {
283 vuint32_t DAI:32;
284 } B;
285 } UT1;
286
287 union { /* User Test 2 (Base+0x0044) */
288 vuint32_t R;
289 struct {
290 vuint32_t DAI:32;
291 } B;
292 } UT2;
293
294 union { /* User Multiple Input Sig 0..4 (Base+0x0048-0x005B) */
295 vuint32_t R;
296 struct {
297 vuint32_t MS:32;
298 } B;
299 } UMISR[5];
300
301 vuint8_t CFLASH_reserved1[16292]; /* Reserved 16292 (Base+0x005C-0x3FFF)*/
302
303 }; /* end of CFLASH_tag */
304
305/****************************************************************************/
306/* MODULE : DFLASH (base address - 0xC3F8C000) */
307/****************************************************************************/
308 struct DFLASH_tag {
309 union { /* Module Configuration (Base+0x0000) */
310 vuint32_t R;
311 struct {
312 vuint32_t EDC:1;
313 vuint32_t:4;
314 vuint32_t SIZE:3;
315 vuint32_t:1;
316 vuint32_t LAS:3;
317 vuint32_t:3;
318 vuint32_t MAS:1;
319 vuint32_t EER:1;
320 vuint32_t RWE:1;
321 vuint32_t:2;
322 vuint32_t PEAS:1;
323 vuint32_t DONE:1;
324 vuint32_t PEG:1;
325 vuint32_t:4;
326 vuint32_t PGM:1;
327 vuint32_t PSUS:1;
328 vuint32_t ERS:1;
329 vuint32_t ESUS:1;
330 vuint32_t EHV:1;
331 } B;
332 } MCR;
333
334 union { /* Low/Mid address block locking (Base+0x0004) */
335 vuint32_t R;
336 struct {
337 vuint32_t LME:1;
338 vuint32_t:10;
339 vuint32_t TSLK:1;
340 vuint32_t:16;
341 vuint32_t LLK:4;
342 } B;
343 } LML;
344
345 vuint8_t DFLASH_reserved0[4]; /* Reserved 4 Bytes (+0x0008-0x000B) */
346
347
348 union { /* Secondary Low/mid block locking (Base+0x000C)*/
349 vuint32_t R;
350 struct {
351 vuint32_t SLE:1;
352 vuint32_t:10;
353 vuint32_t STSLK:1;
354 vuint32_t:16;
355 vuint32_t SLK:4;
356 } B;
357 } SLL;
358
359 union { /* Low/Mid address space block sel (Base+0x0010)*/
360 vuint32_t R;
361 struct {
362 vuint32_t:28;
363 vuint32_t LSL:4;
364 } B;
365 } LMS;
366
367 vuint8_t DFLASH_reserved1[4]; /* Reserved 4 Bytes (+0x0014-0x0017)*/
368
369 union { /* Address Register (Base+0x0018) */
370 vuint32_t R;
371 struct {
372 vuint32_t:9;
373 vuint32_t ADD:20;
374 vuint32_t:3;
375 } B;
376 } ADR;
377
378 vuint8_t DFLASH_reserved2[32]; /* Reserved 32 Bytes (+0x001C-0x003B) */
379
380 union { /* User Test 0 (Base+0x003C) */
381 vuint32_t R;
382 struct {
383 vuint32_t UTE:1;
384 vuint32_t:7;
385 vuint32_t DSI:8;
386 vuint32_t:10;
387 vuint32_t MRE:1;
388 vuint32_t MRV:1;
389 vuint32_t EIE:1;
390 vuint32_t AIS:1;
391 vuint32_t AIE:1;
392 vuint32_t AID:1;
393 } B;
394 } UT0;
395
396 union { /* User Test 1 (Base+0x0040) */
397 vuint32_t R;
398 struct {
399 vuint32_t DAI:32;
400 } B;
401 } UT1;
402
403 union { /* User Test 2 (Base+0x0044) */
404 vuint32_t R;
405 struct {
406 vuint32_t DAI:32;
407 } B;
408 } UT2;
409
410 union { /* User Multiple Input sig 0..1 (+0x0048-0x004F)*/
411 vuint32_t R;
412 struct {
413 vuint32_t MS:32;
414 } B;
415 } UMISR[5];
416
417 }; /* end of Dflash_tag */
418
419/****************************************************************************/
420/* MODULE : SIU Lite (tagged as SIU for compatibility) */
421/****************************************************************************/
422struct SIU_tag {
423
424 vuint8_t SIU_reserved0[4]; /* Reserved 4 Bytes (Base+0x0) */
425
426 union { /* MCU ID1 (Base+0x0004) */
427 vuint32_t R;
428 struct {
429 vuint32_t PARTNUM:16;
430 vuint32_t CSP:1;
431 vuint32_t PKG:5;
432 vuint32_t :2;
433 vuint32_t MAJOR_MASK:4;
434 vuint32_t MINOR_MASK:4;
435 } B;
436 } MIDR1;
437
438 union { /* MCU ID2 (Base+0x0008) */
439 vuint32_t R;
440 struct {
441 vuint32_t SF:1;
442 vuint32_t FLASH_SIZE_1:4;
443 vuint32_t FLASH_SIZE_2:4;
444 vuint32_t :7;
445 vuint32_t PARTNUM:8;
446 vuint32_t :3;
447 vuint32_t EE:1;
448 vuint32_t :3;
449 vuint32_t FR:1;
450 } B;
451 } MIDR2;
452
453 vuint8_t SIU_reserved1[8]; /* Reserved 8 Bytes (Base+(0x000C--0x0013)) */
454
455 union { /* Interrupt Status Flag (Base+0x0014)*/
456 vuint32_t R;
457 struct {
458 vuint32_t :8;
459 vuint32_t EIF23:1;
460 vuint32_t EIF22:1;
461 vuint32_t EIF21:1;
462 vuint32_t EIF20:1;
463 vuint32_t EIF19:1;
464 vuint32_t EIF18:1;
465 vuint32_t EIF17:1;
466 vuint32_t EIF16:1;
467 vuint32_t EIF15:1;
468 vuint32_t EIF14:1;
469 vuint32_t EIF13:1;
470 vuint32_t EIF12:1;
471 vuint32_t EIF11:1;
472 vuint32_t EIF10:1;
473 vuint32_t EIF9:1;
474 vuint32_t EIF8:1;
475 vuint32_t EIF7:1;
476 vuint32_t EIF6:1;
477 vuint32_t EIF5:1;
478 vuint32_t EIF4:1;
479 vuint32_t EIF3:1;
480 vuint32_t EIF2:1;
481 vuint32_t EIF1:1;
482 vuint32_t EIF0:1;
483 } B;
484 } ISR;
485
486 union { /* Interrupt Request Enable (Base+0x0018) */
487 vuint32_t R;
488 struct {
489 vuint32_t :8;
490 vuint32_t IRE23:1;
491 vuint32_t IRE22:1;
492 vuint32_t IRE21:1;
493 vuint32_t IRE20:1;
494 vuint32_t IRE19:1;
495 vuint32_t IRE18:1;
496 vuint32_t IRE17:1;
497 vuint32_t IRE16:1;
498 vuint32_t IRE15:1;
499 vuint32_t IRE14:1;
500 vuint32_t IRE13:1;
501 vuint32_t IRE12:1;
502 vuint32_t IRE11:1;
503 vuint32_t IRE10:1;
504 vuint32_t IRE9:1;
505 vuint32_t IRE8:1;
506 vuint32_t IRE7:1;
507 vuint32_t IRE6:1;
508 vuint32_t IRE5:1;
509 vuint32_t IRE4:1;
510 vuint32_t IRE3:1;
511 vuint32_t IRE2:1;
512 vuint32_t IRE1:1;
513 vuint32_t IRE0:1;
514 } B;
515 } IRER;
516
517 vuint8_t SIU_reserved2[12]; /* Reserved 12 Bytes (Base+0x001C-0x0027) */
518
519 union { /* Interrupt Rising-Edge Event Enable (+0x0028) */
520 vuint32_t R;
521 struct {
522 vuint32_t :8;
523 vuint32_t IREE23:1;
524 vuint32_t IREE22:1;
525 vuint32_t IREE21:1;
526 vuint32_t IREE20:1;
527 vuint32_t IREE19:1;
528 vuint32_t IREE18:1;
529 vuint32_t IREE17:1;
530 vuint32_t IREE16:1;
531 vuint32_t IREE15:1;
532 vuint32_t IREE14:1;
533 vuint32_t IREE13:1;
534 vuint32_t IREE12:1;
535 vuint32_t IREE11:1;
536 vuint32_t IREE10:1;
537 vuint32_t IREE9:1;
538 vuint32_t IREE8:1;
539 vuint32_t IREE7:1;
540 vuint32_t IREE6:1;
541 vuint32_t IREE5:1;
542 vuint32_t IREE4:1;
543 vuint32_t IREE3:1;
544 vuint32_t IREE2:1;
545 vuint32_t IREE1:1;
546 vuint32_t IREE0:1;
547 } B;
548 } IREER;
549
550 union { /* Interrupt Falling-Edge Event Enable (+0x002C)*/
551 vuint32_t R;
552 struct {
553 vuint32_t :8;
554 vuint32_t IFEE23:1;
555 vuint32_t IFEE22:1;
556 vuint32_t IFEE21:1;
557 vuint32_t IFEE20:1;
558 vuint32_t IFEE19:1;
559 vuint32_t IFEE18:1;
560 vuint32_t IFEE17:1;
561 vuint32_t IFEE16:1;
562 vuint32_t IFEE15:1;
563 vuint32_t IFEE14:1;
564 vuint32_t IFEE13:1;
565 vuint32_t IFEE12:1;
566 vuint32_t IFEE11:1;
567 vuint32_t IFEE10:1;
568 vuint32_t IFEE9:1;
569 vuint32_t IFEE8:1;
570 vuint32_t IFEE7:1;
571 vuint32_t IFEE6:1;
572 vuint32_t IFEE5:1;
573 vuint32_t IFEE4:1;
574 vuint32_t IFEE3:1;
575 vuint32_t IFEE2:1;
576 vuint32_t IFEE1:1;
577 vuint32_t IFEE0:1;
578 } B;
579 } IFEER;
580
581 union { /* Interrupt Filter Enable (Base+0x0030) */
582 vuint32_t R;
583 struct {
584 vuint32_t :8;
585 vuint32_t IFE23:1;
586 vuint32_t IFE22:1;
587 vuint32_t IFE21:1;
588 vuint32_t IFE20:1;
589 vuint32_t IFE19:1;
590 vuint32_t IFE18:1;
591 vuint32_t IFE17:1;
592 vuint32_t IFE16:1;
593 vuint32_t IFE15:1;
594 vuint32_t IFE14:1;
595 vuint32_t IFE13:1;
596 vuint32_t IFE12:1;
597 vuint32_t IFE11:1;
598 vuint32_t IFE10:1;
599 vuint32_t IFE9:1;
600 vuint32_t IFE8:1;
601 vuint32_t IFE7:1;
602 vuint32_t IFE6:1;
603 vuint32_t IFE5:1;
604 vuint32_t IFE4:1;
605 vuint32_t IFE3:1;
606 vuint32_t IFE2:1;
607 vuint32_t IFE1:1;
608 vuint32_t IFE0:1;
609 } B;
610 } IFER;
611
612 vuint8_t SIU_reserved3[12]; /* Reserved 12 Bytes (Base+0x0034-0x003F) */
613
614 union { /* Pad Configuration 0..148 (Base+0x0040-0x0168)*/
615 vuint16_t R;
616 struct {
617 vuint16_t:1;
618 vuint16_t SMC:1;
619 vuint16_t APC:1;
620 vuint16_t:1;
621 vuint16_t PA:2;
622 vuint16_t OBE:1;
623 vuint16_t IBE:1;
624 vuint16_t:2;
625 vuint16_t ODE:1;
626 vuint16_t:2;
627 vuint16_t SRC:1;
628 vuint16_t WPE:1;
629 vuint16_t WPS:1;
630 } B;
631 } PCR[149];
632
633 vuint8_t SIU_reserved4[918]; /*Reserved 918 Bytes (Base+0x016A-0x04FF) */
634
635 union { /* Pad Selection for Mux Input (0x0500-0x53C) */
636 vuint8_t R;
637 struct {
638 vuint8_t :4;
639 vuint8_t PADSEL:4;
640 } B;
641 } PSMI[64];
642
643 vuint8_t SIU_reserved5[192]; /*Reserved 192 Bytes (Base+0x0540-0x05FF) */
644
645 union { /* GPIO Pad Data Output (Base+0x0600-0x06A0) */
646 vuint8_t R;
647 struct {
648 vuint8_t :7;
649 vuint8_t PDO:1;
650 } B;
651 } GPDO[124]; // only 124 GPD0 registers
652
653 vuint8_t SIU_reserved6[388]; /*Reserved 388 Bytes 512-124=388 */
654
655 union { /* GPIO Pad Data Input (Base+0x0800-0x08A0) */
656 vuint8_t R;
657 struct {
658 vuint8_t :7;
659 vuint8_t PDI:1;
660 } B;
661 } GPDI[124]; // only 152 GPD0 registers
662
663 vuint8_t SIU_reserved7[900]; /*Reserved 900 Bytes 1024-124=900 */
664
665 union { /* Parallel GPIO Pad Data Out 0-4 (0x0C00-0xC010) */
666 vuint32_t R;
667 struct {
668 vuint32_t PPD0:32;
669 } B;
670 } PGPDO[5];
671
672 vuint8_t SIU_reserved8[44]; /* Reserved 44 Bytes (Base+0x0C14-0x0C3F) */
673
674 union { /* Parallel GPIO Pad Data In 0-4 (0x0C40-0x0C50) */
675 vuint32_t R;
676 struct {
677 vuint32_t PPDI:32;
678 } B;
679 } PGPDI[5];
680
681 vuint8_t SIU_reserved9[44]; /* Reserved 44 Bytes (Base+0x0C54-0x0C7F) */
682
683 union { /* Masked Parallel GPIO Pad Data Out 0-9 (0x0C80-0x0CA4) */
684 vuint32_t R;
685 struct {
686 vuint32_t MASK:16;
687 vuint32_t MPPDO:16;
688 } B;
689 } MPGPDO[10];
690
691 vuint8_t SIU_reserved10[856]; /*Reserved 844 Bytes (Base+0x0CA8-0x0FFF)*/
692
693 union { /* Interrupt Filter Max Counter 0..23 (+0x1000-0x105C) */
694 vuint32_t R;
695 struct {
696 vuint32_t :28;
697 vuint32_t MAXCNT:4;
698 } B;
699 } IFMC[24];
700
701 vuint8_t SIU_reserved11[32]; /* Reserved 32 Bytes (Base+0x1060-0x107F)*/
702
703 union { /* Interrupt Filter Clock Prescaler (Base+0x1080) */
704 vuint32_t R;
705 struct {
706 vuint32_t :28;
707 vuint32_t IFCP:4;
708 } B;
709 } IFCPR;
710
711 vuint8_t SIU_reserved12[12156]; /* Reserved 12156 Bytes (+0x1084-0x3FFF)*/
712
713}; /* end of SIU_tag */
714
715/****************************************************************************/
716/* MODULE : WKUP */
717/****************************************************************************/
718struct WKUP_tag{
719
720 union { /* NMI Status Flag (Base+0x0000) */
721 vuint32_t R;
722 struct {
723 vuint32_t NIF0:1;
724 vuint32_t NOVF0:1;
725 vuint32_t :30;
726 } B;
727 } NSR;
728
729 vuint8_t WKUP_reserved0[4]; /* Reserved 4 Bytes (Base+0x0004-0x0007) */
730
731 union { /* NMI Configuration (Base+0x0008) */
732 vuint32_t R;
733 struct {
734 vuint32_t NLOCK0:1;
735 vuint32_t NDSS0:2;
736 vuint32_t NWRE0:1;
737 vuint32_t :1;
738 vuint32_t NREE0:1;
739 vuint32_t NFEE0:1;
740 vuint32_t NFE0:1;
741 vuint32_t :24;
742 } B;
743 } NCR;
744
745 vuint8_t WKUP_reserved1[8]; /* Reserved 8 Bytes (Base+0x000C-0x0013) */
746
747 union { /* Wakeup/Interrup status flag (Base+0x0014) */
748 vuint32_t R;
749 struct {
750 vuint32_t :3;
751 vuint32_t EIF:29;
752 } B;
753 } WISR;
754
755 union { /* Interrupt Request Enable (Base+0x0018) */
756 vuint32_t R;
757 struct {
758 vuint32_t :3;
759 vuint32_t EIRE:29;
760 } B;
761 } IRER;
762
763 union { /* Wakeup Request Enable (Base+0x001C) */
764 vuint32_t R;
765 struct {
766 vuint32_t :3;
767 vuint32_t WRE:29;
768 } B;
769 } WRER;
770
771 vuint8_t WKUP_reserved2[8]; /* Reserved 8 Bytes (Base+0x0020-0x0027) */
772
773 union { /* Wakeup/Interrupt Rising-Edge (Base+0x0028) */
774 vuint32_t R;
775 struct {
776 vuint32_t :3;
777 vuint32_t IREE:29;
778 } B;
779 } WIREER;
780
781 union { /* Wakeup/Interrupt Falling-Edge (Base+0x002C) */
782 vuint32_t R;
783 struct {
784 vuint32_t :3;
785 vuint32_t IFEE:29;
786 } B;
787 } WIFEER;
788
789 union { /* Wakeup/Interrupt Filter Enable (Base+0x0030) */
790 vuint32_t R;
791 struct {
792 vuint32_t :3;
793 vuint32_t IFE:29;
794 } B;
795 } WIFER;
796
797 union { /* Wakeup/Interrupt Pullup Enable (Base+0x0034) */
798 vuint32_t R;
799 struct {
800 vuint32_t :3;
801 vuint32_t IPUE:29;
802 } B;
803 } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */
804
805 vuint8_t WKUP_reserved3[16328]; /* Reserved 16328 (Base+0x0038-0x3FFF) */
806
807}; /* end of WKUP_tag */
808
809/****************************************************************************/
810/* MODULE : EMIOS (base address - eMIOS0 0xC3FA_0000; eMIOS1 0xC3FA_4000) */
811/****************************************************************************/
812
813struct EMIOS_CHANNEL_tag{
814
815 union { /* Channel A Data (UCn Base+0x0000) */
816 vuint32_t R;
817 struct {
818 vuint32_t :16;
819 vuint32_t A:16;
820 } B;
821 } CADR;
822
823 union { /* Channel B Data (UCn Base+0x0004) */
824 vuint32_t R;
825 struct {
826 vuint32_t :16;
827 vuint32_t B:16;
828 } B;
829 } CBDR;
830
831 union { /* Channel Counter (UCn Base+0x0008) */
832 vuint32_t R;
833 struct {
834 vuint32_t :16;
835 vuint32_t C:16;
836 } B;
837 } CCNTR;
838
839 union { /* Channel Control (UCn Base+0x000C) */
840 vuint32_t R;
841 struct {
842 vuint32_t FREN:1;
843 vuint32_t :3;
844 vuint32_t UCPRE:2;
845 vuint32_t UCPEN:1;
846 vuint32_t DMA:1;
847 vuint32_t :1;
848 vuint32_t IF:4;
849 vuint32_t FCK:1;
850 vuint32_t FEN:1;
851 vuint32_t :3;
852 vuint32_t FORCMA:1;
853 vuint32_t FORCMB:1;
854 vuint32_t :1;
855 vuint32_t BSL:2;
856 vuint32_t EDSEL:1;
857 vuint32_t EDPOL:1;
858 vuint32_t MODE:7;
859 } B;
860 } CCR;
861
862 union { /* Channel Status (UCn Base+0x0010) */
863 vuint32_t R;
864 struct {
865 vuint32_t OVR:1;
866 vuint32_t :15;
867 vuint32_t OVFL:1;
868 vuint32_t :12;
869 vuint32_t UCIN:1;
870 vuint32_t UCOUT:1;
871 vuint32_t FLAG:1;
872 } B;
873 } CSR;
874
875 union { /* Alternate Channel A Data (UCn Base+0x0014) */
876 vuint32_t R;
877 struct {
878 vuint32_t :16;
879 vuint32_t ALTA:16;
880 } B;
881 } ALTCADR;
882
883 vuint8_t EMIOS_CHANNEL_reserved0[8]; /* (UCn Base + (0x0018-0x001F) */
884
885}; /* end of EMIOS_CHANNEL_tag */
886
887
888struct EMIOS_tag{
889
890 union { /* Module Configuration (Base+0x0000) */
891 vuint32_t R;
892 struct {
893 vuint32_t :1;
894 vuint32_t MDIS:1;
895 vuint32_t FRZ:1;
896 vuint32_t GTBE:1;
897 vuint32_t :1;
898 vuint32_t GPREN:1;
899 vuint32_t :10;
900 vuint32_t GPRE:8;
901 vuint32_t :8;
902 } B;
903 } MCR;
904
905 union { /* Global Flag (Base+0x0004) */
906 vuint32_t R;
907 struct {
908 vuint32_t F31:1;
909 vuint32_t F30:1;
910 vuint32_t F29:1;
911 vuint32_t F28:1;
912 vuint32_t F27:1;
913 vuint32_t F26:1;
914 vuint32_t F25:1;
915 vuint32_t F24:1;
916 vuint32_t F23:1;
917 vuint32_t F22:1;
918 vuint32_t F21:1;
919 vuint32_t F20:1;
920 vuint32_t F19:1;
921 vuint32_t F18:1;
922 vuint32_t F17:1;
923 vuint32_t F16:1;
924 vuint32_t F15:1;
925 vuint32_t F14:1;
926 vuint32_t F13:1;
927 vuint32_t F12:1;
928 vuint32_t F11:1;
929 vuint32_t F10:1;
930 vuint32_t F9:1;
931 vuint32_t F8:1;
932 vuint32_t F7:1;
933 vuint32_t F6:1;
934 vuint32_t F5:1;
935 vuint32_t F4:1;
936 vuint32_t F3:1;
937 vuint32_t F2:1;
938 vuint32_t F1:1;
939 vuint32_t F0:1;
940 } B;
941 } GFR;
942
943 union { /* Output Update Disable (Base+0x0008) */
944 vuint32_t R;
945 struct {
946 vuint32_t OU31:1;
947 vuint32_t OU30:1;
948 vuint32_t OU29:1;
949 vuint32_t OU28:1;
950 vuint32_t OU27:1;
951 vuint32_t OU26:1;
952 vuint32_t OU25:1;
953 vuint32_t OU24:1;
954 vuint32_t OU23:1;
955 vuint32_t OU22:1;
956 vuint32_t OU21:1;
957 vuint32_t OU20:1;
958 vuint32_t OU19:1;
959 vuint32_t OU18:1;
960 vuint32_t OU17:1;
961 vuint32_t OU16:1;
962 vuint32_t OU15:1;
963 vuint32_t OU14:1;
964 vuint32_t OU13:1;
965 vuint32_t OU12:1;
966 vuint32_t OU11:1;
967 vuint32_t OU10:1;
968 vuint32_t OU9:1;
969 vuint32_t OU8:1;
970 vuint32_t OU7:1;
971 vuint32_t OU6:1;
972 vuint32_t OU5:1;
973 vuint32_t OU4:1;
974 vuint32_t OU3:1;
975 vuint32_t OU2:1;
976 vuint32_t OU1:1;
977 vuint32_t OU0:1;
978 } B;
979 } OUDR;
980
981 union { /* Disable Channel (Base+0x000F) */
982 vuint32_t R;
983 struct {
984 vuint32_t CHDIS31:1;
985 vuint32_t CHDIS30:1;
986 vuint32_t CHDIS29:1;
987 vuint32_t CHDIS28:1;
988 vuint32_t CHDIS27:1;
989 vuint32_t CHDIS26:1;
990 vuint32_t CHDIS25:1;
991 vuint32_t CHDIS24:1;
992 vuint32_t CHDIS23:1;
993 vuint32_t CHDIS22:1;
994 vuint32_t CHDIS21:1;
995 vuint32_t CHDIS20:1;
996 vuint32_t CHDIS19:1;
997 vuint32_t CHDIS18:1;
998 vuint32_t CHDIS17:1;
999 vuint32_t CHDIS16:1;
1000 vuint32_t CHDIS15:1;
1001 vuint32_t CHDIS14:1;
1002 vuint32_t CHDIS13:1;
1003 vuint32_t CHDIS12:1;
1004 vuint32_t CHDIS11:1;
1005 vuint32_t CHDIS10:1;
1006 vuint32_t CHDIS9:1;
1007 vuint32_t CHDIS8:1;
1008 vuint32_t CHDIS7:1;
1009 vuint32_t CHDIS6:1;
1010 vuint32_t CHDIS5:1;
1011 vuint32_t CHDIS4:1;
1012 vuint32_t CHDIS3:1;
1013 vuint32_t CHDIS2:1;
1014 vuint32_t CHDIS1:1;
1015 vuint32_t CHDIS0:1;
1016 } B;
1017 } UCDIS;
1018
1019 vuint8_t EMIOS_reserved0[16]; /* Reserved 16 Bytes (Base+0x0010-0x001F) */
1020
1021 struct EMIOS_CHANNEL_tag CH[32]; /* Add in 32 unified channels */
1022
1023 vuint8_t EMIOS_reserved1[3040]; /* 3040 bytes (Base+0x0420-0x0FFF) */
1024
1025}; /* end of EMIOS_tag */
1026
1027/****************************************************************************/
1028/* MODULE : SSCM */
1029/****************************************************************************/
1030struct SSCM_tag{
1031
1032 union { /* Status (Base+0x0000) */
1033 vuint16_t R;
1034 struct {
1035 vuint16_t:5;
1036 vuint16_t PUB:1;
1037 vuint16_t SEC:1;
1038 vuint16_t:1;
1039 vuint16_t BMODE:3;
1040 vuint16_t:5;
1041 } B;
1042 } STATUS;
1043
1044 union { /* System Memory Configuration (Base+0x002) */
1045 vuint16_t R;
1046 struct {
1047 vuint16_t:5;
1048 vuint16_t PRSZ:5;
1049 vuint16_t PVLB:1;
1050 vuint16_t DTSZ:4;
1051 vuint16_t DVLD:1;
1052 } B;
1053 } MEMCONFIG;
1054
1055 vuint8_t SSCM_reserved0[2]; /* Reserved 2 bytes (Base+0x0004-0x0005) */
1056
1057 union { /* Error Configuration (Base+0x0006) */
1058 vuint16_t R;
1059 struct {
1060 vuint16_t :14;
1061 vuint16_t PAE:1;
1062 vuint16_t RAE:1;
1063 } B;
1064 } ERROR;
1065
1066 union { /* Debug Status Port (Base+0x0008) */
1067 vuint16_t R;
1068 struct {
1069 vuint16_t :13;
1070 vuint16_t DEBUG_MODE:3;
1071 } B;
1072 } DEBUGPORT;
1073
1074 vuint8_t SSCM_reserved1[2]; /* Reserved 2 bytes (Base+0x000A-0x000B) */
1075
1076 union { /* Password Comparison High Word (Base+0x000C) */
1077 vuint32_t R;
1078 struct {
1079 vuint32_t PWD_HI:32;
1080 } B;
1081 } PWCMPH;
1082
1083 union { /* Password Comparison Low Word (Base+0x0010)*/
1084 vuint32_t R;
1085 struct {
1086 vuint32_t PWD_LO:32;
1087 } B;
1088 } PWCMPL;
1089
1090}; /* end of SSCM_tag */
1091
1092/****************************************************************************/
1093/* MODULE : ME */
1094/****************************************************************************/
1095struct ME_tag{
1096
1097 union { /* Global Status (Base+0x0000) */
1098 vuint32_t R;
1099 struct {
1100 vuint32_t S_CURRENTMODE:4;
1101 vuint32_t S_MTRANS:1;
1102 vuint32_t S_DC:1;
1103 vuint32_t :2;
1104 vuint32_t S_PDO:1;
1105 vuint32_t :2;
1106 vuint32_t S_MVR:1;
1107 vuint32_t S_DFLA:2;
1108 vuint32_t S_CFLA:2;
1109 vuint32_t :9;
1110 vuint32_t S_FMPLL:1;
1111 vuint32_t S_FXOSC:1;
1112 vuint32_t S_FIRC:1;
1113 vuint32_t S_SYSCLK:4;
1114 } B;
1115 } GS;
1116
1117 union { /* Mode Control (Base+0x004) */
1118 vuint32_t R;
1119 struct {
1120 vuint32_t TARGET_MODE:4;
1121 vuint32_t :12;
1122 vuint32_t KEY:16;
1123 } B;
1124 } MCTL;
1125
1126 union { /* Mode Enable (Base+0x0008) */
1127 vuint32_t R;
1128 struct {
1129 vuint32_t :18;
1130 vuint32_t STANDBY:1;
1131 vuint32_t :2;
1132 vuint32_t STOP:1;
1133 vuint32_t :1;
1134 vuint32_t HALT:1;
1135 vuint32_t RUN3:1;
1136 vuint32_t RUN2:1;
1137 vuint32_t RUN1:1;
1138 vuint32_t RUN:1;
1139 vuint32_t DRUN:1;
1140 vuint32_t SAFE:1;
1141 vuint32_t TEST:1;
1142 vuint32_t RESET:1;
1143 } B;
1144 } MER;
1145
1146 union { /* Interrupt Status (Base+0x000C) */
1147 vuint32_t R;
1148 struct {
1149 vuint32_t :28;
1150 vuint32_t I_ICONF:1;
1151 vuint32_t I_IMODE:1;
1152 vuint32_t I_SAFE:1;
1153 vuint32_t I_MTC:1;
1154 } B;
1155 } IS;
1156
1157 union { /* Interrupt Mask (Base+0x0010) */
1158 vuint32_t R;
1159 struct {
1160 vuint32_t :28;
1161 vuint32_t M_ICONF:1;
1162 vuint32_t M_IMODE:1;
1163 vuint32_t M_SAFE:1;
1164 vuint32_t M_MTC:1;
1165 } B;
1166 } IM;
1167
1168 union { /* Invalid Mode Transition Status (Base+0x0014) */
1169 vuint32_t R;
1170 struct {
1171 vuint32_t :27;
1172 vuint32_t S_MTI:1;
1173 vuint32_t S_MRI:1;
1174 vuint32_t S_DMA:1;
1175 vuint32_t S_NMA:1;
1176 vuint32_t S_SEA:1;
1177 } B;
1178 } IMTS;
1179
1180 union { /* Debug Mode Transition Status (Base+0x0018) */
1181 vuint32_t R;
1182 struct {
1183 vuint32_t :8;
1184 vuint32_t MPH_BUSY:1;
1185 vuint32_t :2;
1186 vuint32_t PMC_PROG:1;
1187 vuint32_t CORE_DBG:1;
1188 vuint32_t :2;
1189 vuint32_t SMR:1;
1190 vuint32_t :1;
1191 vuint32_t FMPLL_SC:1;
1192 vuint32_t FXOSC_SC:1;
1193 vuint32_t FIRC_SC:1;
1194 vuint32_t :1;
1195 vuint32_t SYSCLK_SW:1;
1196 vuint32_t DFLASH_SC:1;
1197 vuint32_t CFLASH_SC:1;
1198 vuint32_t CDP_PRPH_0_143:1;
1199 vuint32_t :3;
1200 vuint32_t CDP_PRPH_96_127:1;
1201 vuint32_t CDP_PRPH_64_95:1;
1202 vuint32_t CDP_PRPH_32_63:1;
1203 vuint32_t CDP_PRPH_0_31:1;
1204 } B;
1205 } DMTS;
1206
1207 vuint8_t ME_reserved0[4]; /* reserved 4 bytes (Base+0x001C-0x001F) */
1208
1209 union { /* Reset Mode Configuration (Base+0x0020) */
1210 vuint32_t R;
1211 struct {
1212 vuint32_t :8;
1213 vuint32_t PDO:1;
1214 vuint32_t :2;
1215 vuint32_t MVRON:1;
1216 vuint32_t DFLAON:2;
1217 vuint32_t CFLAON:2;
1218 vuint32_t :9;
1219 vuint32_t FMPLLON:1;
1220 vuint32_t FXOSCON:1;
1221 vuint32_t FIRCON:1;
1222 vuint32_t SYSCLK:4;
1223 } B;
1224 } RESET;
1225
1226 union { /* Test Mode Configuration (Base+0x0024) */
1227 vuint32_t R;
1228 struct {
1229 vuint32_t :8;
1230 vuint32_t PDO:1;
1231 vuint32_t :2;
1232 vuint32_t MVRON:1;
1233 vuint32_t DFLAON:2;
1234 vuint32_t CFLAON:2;
1235 vuint32_t :9;
1236 vuint32_t FMPLLON:1;
1237 vuint32_t FXOSCON:1;
1238 vuint32_t FIRCON:1;
1239 vuint32_t SYSCLK:4;
1240 } B;
1241 } TEST;
1242
1243 union { /* Safe Mode Configuration (Base+0x0028) */
1244 vuint32_t R;
1245 struct {
1246 vuint32_t :8;
1247 vuint32_t PDO:1;
1248 vuint32_t :2;
1249 vuint32_t MVRON:1;
1250 vuint32_t DFLAON:2;
1251 vuint32_t CFLAON:2;
1252 vuint32_t :9;
1253 vuint32_t FMPLLON:1;
1254 vuint32_t FXOSCON:1;
1255 vuint32_t FIRCON:1;
1256 vuint32_t SYSCLK:4;
1257 } B;
1258 } SAFE;
1259
1260 union { /* DRUN Mode Configuration (Base+0x002C) */
1261 vuint32_t R;
1262 struct {
1263 vuint32_t :8;
1264 vuint32_t PDO:1;
1265 vuint32_t :2;
1266 vuint32_t MVRON:1;
1267 vuint32_t DFLAON:2;
1268 vuint32_t CFLAON:2;
1269 vuint32_t :9;
1270 vuint32_t FMPLLON:1;
1271 vuint32_t FXOSCON:1;
1272 vuint32_t FIRCON:1;
1273 vuint32_t SYSCLK:4;
1274 } B;
1275 } DRUN;
1276
1277 union { /* RUN 0->4 Mode Configuration (+0x0030-0x003C) */
1278 vuint32_t R;
1279 struct {
1280 vuint32_t :8;
1281 vuint32_t PDO:1;
1282 vuint32_t :2;
1283 vuint32_t MVRON:1;
1284 vuint32_t DFLAON:2;
1285 vuint32_t CFLAON:2;
1286 vuint32_t :9;
1287 vuint32_t FMPLLON:1;
1288 vuint32_t FXOSCON:1;
1289 vuint32_t FIRCON:1;
1290 vuint32_t SYSCLK:4;
1291 } B;
1292 } RUN[4];
1293
1294 union { /* HALT Mode Configuration (Base+0x0040) */
1295 vuint32_t R;
1296 struct {
1297 vuint32_t :8;
1298 vuint32_t PDO:1;
1299 vuint32_t :2;
1300 vuint32_t MVRON:1;
1301 vuint32_t DFLAON:2;
1302 vuint32_t CFLAON:2;
1303 vuint32_t :9;
1304 vuint32_t FMPLLON:1;
1305 vuint32_t FXOSCON:1;
1306 vuint32_t FIRCON:1;
1307 vuint32_t SYSCLK:4;
1308 } B;
1309 } HALT;
1310
1311 vuint8_t ME_reserved1[4]; /* reserved 4 bytes (Base+0x0044-0x0047) */
1312
1313 union { /* STOP Mode Configuration (Base+0x0048) */
1314 vuint32_t R;
1315 struct {
1316 vuint32_t :8;
1317 vuint32_t PDO:1;
1318 vuint32_t :2;
1319 vuint32_t MVRON:1;
1320 vuint32_t DFLAON:2;
1321 vuint32_t CFLAON:2;
1322 vuint32_t :9;
1323 vuint32_t FMPLLON:1;
1324 vuint32_t FXOSCON:1;
1325 vuint32_t FIRCON:1;
1326 vuint32_t SYSCLK:4;
1327 } B;
1328 } STOP;
1329
1330 vuint8_t ME_reserved2[8]; /* reserved 8 bytes (Base+0x004C-0x0053) */
1331
1332 union { /* STANDBY Mode Configuration (Base+0x0054) */
1333 vuint32_t R;
1334 struct {
1335 vuint32_t :8;
1336 vuint32_t PDO:1;
1337 vuint32_t :2;
1338 vuint32_t MVRON:1;
1339 vuint32_t DFLAON:2;
1340 vuint32_t CFLAON:2;
1341 vuint32_t :9;
1342 vuint32_t FMPLLON:1;
1343 vuint32_t FXOSCON:1;
1344 vuint32_t FIRCON:1;
1345 vuint32_t SYSCLK:4;
1346 } B;
1347 } STANDBY;
1348
1349 vuint8_t ME_reserved3[8]; /* reserved 8 bytes (Base+0x0058-0x005F) */
1350
1351 union {
1352 vuint32_t R;
1353 struct { /* Peripheral Status 0 (Base+0x0060) */
1354 vuint32_t :8;
1355 vuint32_t S_DMA_CH_MUX:1;
1356 vuint32_t :6;
1357 vuint32_t S_FLEXCAN0:1;
1358 vuint32_t :10;
1359 vuint32_t S_DSPI1:1;
1360 vuint32_t S_DSPI0:1;
1361 vuint32_t :4;
1362 } B;
1363 } PS0;
1364
1365 union { /* Peripheral Status 1 (Base+0x0064)*/
1366 vuint32_t R;
1367 struct {
1368 vuint32_t :6;
1369 vuint32_t S_CTU:1;
1370 vuint32_t :6;
1371 vuint32_t S_LINFLEX2:1;
1372 vuint32_t S_LINFLEX1:1;
1373 vuint32_t S_LINFLEX0:1;
1374 vuint32_t :14;
1375 vuint32_t S_ADC1:1;
1376 vuint32_t :1;
1377 } B;
1378 } PS1;
1379
1380 union { /* Peripheral Status 2 (Base+0x0068) */
1381 vuint32_t R;
1382 struct {
1383 vuint32_t :3;
1384 vuint32_t S_PIT_RTI:1;
1385 vuint32_t S_RTC_API:1;
1386 vuint32_t :18;
1387 vuint32_t S_EMIOS0:1;
1388 vuint32_t :2;
1389 vuint32_t S_WKPU:1;
1390 vuint32_t S_SIUL:1;
1391 vuint32_t :4;
1392 } B;
1393 } PS2;
1394
1395 union { /* Peripheral Status 3 (Base+0x006C) */
1396 vuint32_t R;
1397 struct {
1398 vuint32_t :23;
1399 vuint32_t S_CMU:1;
1400 vuint32_t :8;
1401 } B;
1402 } PS3;
1403
1404 vuint8_t ME_reserved4[16]; /* reserved 16 bytes (Base+0x0070-0x007F) */
1405
1406 union { /* RUN Peripheral Config 0..7 (+0x0080-009C) */
1407 vuint32_t R;
1408 struct {
1409 vuint32_t :24;
1410 vuint32_t RUN3:1;
1411 vuint32_t RUN2:1;
1412 vuint32_t RUN1:1;
1413 vuint32_t RUN0:1;
1414 vuint32_t DRUN:1;
1415 vuint32_t SAFE:1;
1416 vuint32_t TEST:1;
1417 vuint32_t RESET:1;
1418 } B;
1419 } RUNPC[8];
1420
1421 union { /* Low Pwr Periph Config 0..7 (+0x00A0-0x00BC) */
1422 vuint32_t R;
1423 struct {
1424 vuint32_t :18;
1425 vuint32_t STANDBY:1;
1426 vuint32_t :2;
1427 vuint32_t STOP:1;
1428 vuint32_t :1;
1429 vuint32_t HALT:1;
1430 vuint32_t :8;
1431 } B;
1432 } LPPC[8];
1433
1434
1435 /* Note on PCTL registers: There are only some PCTL implemented in */
1436 /* Bolero 1.5M/1M. In order to make the PCTL easily addressable, these */
1437 /* are defined as an array (ie ME.PCTL[x].R). This means you have */
1438 /* to be careful when addressing these registers in order not to */
1439 /* access a PCTL that is not implemented. Following are available: */
1440 /* 104, 92, 91, 73, 72, 69, 68, 60, 57, 55, 53, 52, 51, 50, 49,48, */
1441 /* 44, 33, 32, 23, 21-16, 9-4 */
1442
1443 union { /* Peripheral Control 0..143 (+0x00C0-0x014F) */
1444 vuint8_t R;
1445 struct {
1446 vuint8_t :1;
1447 vuint8_t DBG_F:1;
1448 vuint8_t LP_CFG:3;
1449 vuint8_t RUN_CFG:3;
1450 } B;
1451 } PCTL[105];
1452
1453}; /* end of ME_tag */
1454
1455/****************************************************************************/
1456/* MODULE : CGM */
1457/****************************************************************************/
1458struct CGM_tag{
1459 /*
1460 The "CGM" has fairly wide coverage and essentially includes everything in
1461
1462 chapter 6/7 of the Bolero Reference Manual:
1463
1464 Base Address | Clock Sources
1465
1466 -----------------------------
1467
1468 0xC3FE0000 | FXOSC_CTL
1469
1470 0xC3FE0040 | SXOSC_CTL
1471
1472 0xC3FE0060 | FIRC_CTL
1473
1474 0xC3FE0080 | SIRC_CTL
1475
1476 0xC3FE00A0 | FMPLL
1477
1478 0xC3FE00C0 | CGM Block 1
1479
1480 0xC3FE0100 | CMU
1481
1482 0xC3FE0120 | CGM Block 2
1483
1484
1485
1486 In this header file, "Base" referrs to the 1st address, 0xC3FE_0000
1487
1488 */
1489 /* FXOSC - 0xC3FE_0000*/
1490 union { /* Fast OSC Control (Base+0x0000) */
1491 vuint32_t R;
1492 struct {
1493 vuint32_t OSCBYP:1;
1494 vuint32_t :7;
1495 vuint32_t EOCV:8;
1496 vuint32_t M_OSC:1;
1497 vuint32_t :2;
1498 vuint32_t OSCDIV:5;
1499 vuint32_t I_OSC:1;
1500 vuint32_t:7;
1501 } B;
1502 } FXOSC_CTL;
1503
1504
1505 /* Reserved Space between end of FXOSC and start SXOSC */
1506 vuint8_t CGM_reserved0[60]; /* Reserved 60 bytes (Base+0x0004-0x003F) */
1507
1508
1509 /* SXOSC - 0xC3FE_0040*/
1510 union { /* Slow Osc Control (Base+0x0040) */
1511 vuint32_t R;
1512 struct {
1513 vuint32_t OSCBYP:1;
1514 vuint32_t :7;
1515 vuint32_t EOCV:8;
1516 vuint32_t M_OSC:1;
1517 vuint32_t :2;
1518 vuint32_t OSCDIV:5;
1519 vuint32_t I_OSC:1;
1520 vuint32_t :5;
1521 vuint32_t S_OSC:1;
1522 vuint32_t OSCON:1;
1523 } B;
1524 } SXOSC_CTL;
1525
1526
1527 /* Reserved space between end of SXOSC and start of FIRC */
1528 vuint8_t CGM_reserved1[28]; /*Reserved 28 bytes (Base+0x0044-0x005F) */
1529
1530
1531 /* FIRC - 0xC3FE_0060 */
1532 union { /* Fast IRC Control (Base+0x0060) */
1533 vuint32_t R;
1534 struct {
1535 vuint32_t :10;
1536 vuint32_t RCTRIM:6;
1537 vuint32_t :3;
1538 vuint32_t RCDIV:5;
1539 vuint32_t :2;
1540 vuint32_t FIRCON_STDBY:1;
1541 vuint32_t :5;
1542 } B;
1543 } FIRC_CTL;
1544
1545
1546 /* Reserved space between end of FIRC and start of SIRC */
1547 vuint8_t CGM_reserved2[28]; /*Reserved 28 bytes (Base+0x0064-0x007F) */
1548
1549
1550 /* SIRC - 0xC3FE_0080 */
1551 union { /* Slow IRC Control (Base+0x0080) */
1552 vuint32_t R;
1553 struct {
1554 vuint32_t :11;
1555 vuint32_t SIRCTRIM:5;
1556 vuint32_t :3;
1557 vuint32_t SIRCDIV:5;
1558 vuint32_t :3;
1559 vuint32_t S_SIRC:1;
1560 vuint32_t :3;
1561 vuint32_t SIRCON_STDBY:1;
1562 } B;
1563 } SIRC_CTL;
1564
1565
1566 /* Reserved space between end of SIRC and start of FMPLL */
1567 vuint8_t CGM_reserved3[28]; /*Reserved 28 bytes (Base+0x0084-0x009F) */
1568
1569
1570 /* FMPLL - 0xC3FE_00A0 */
1571 union { /* FMPLL Control (Base+0x00A0) */
1572 vuint32_t R;
1573 struct {
1574 vuint32_t:2;
1575 vuint32_t IDF:4;
1576 vuint32_t ODF:2;
1577 vuint32_t:1;
1578 vuint32_t NDIV:7;
1579 vuint32_t:7;
1580 vuint32_t EN_PLL_SW:1;
1581 vuint32_t MODE:1;
1582 vuint32_t UNLOCK_ONCE:1;
1583 vuint32_t:1;
1584 vuint32_t I_LOCK:1;
1585 vuint32_t S_LOCK:1;
1586 vuint32_t PLL_FAIL_MASK:1;
1587 vuint32_t PLL_FAIL_FLAG:1;
1588 vuint32_t:1;
1589 } B;
1590 } FMPLL_CR;
1591
1592 union { /* FMPLL Modulation (Base+0x00A4) */
1593 vuint32_t R;
1594 struct {
1595 vuint32_t STRB_BYPASS:1;
1596 vuint32_t :1;
1597 vuint32_t SPRD_SEL:1;
1598 vuint32_t MOD_PERIOD:13;
1599 vuint32_t FM_EN:1;
1600 vuint32_t INC_STEP:15;
1601 } B;
1602 } FMPLL_MR;
1603
1604
1605 /* Reserved space between end of FMPLL and start of CGM Block 1 */
1606 vuint8_t CGM_reserved4[88]; /*Reserved 88 bytes (Base+0x00A8-0x00FF) */
1607
1608 /* CMU - 0xC3FE_0100 */
1609 union { /* CMU Control Status (Base+0x0100) */
1610 vuint32_t R;
1611 struct {
1612 vuint32_t :8;
1613 vuint32_t SFM:1;
1614 vuint32_t :13;
1615 vuint32_t CLKSEL1:2;
1616 vuint32_t :5;
1617 vuint32_t RCDIV:2;
1618 vuint32_t CME_A:1;
1619 } B;
1620 } CMU_CSR;
1621
1622 union { /* CMU Frequency Display (Base+0x0104) */
1623 vuint32_t R;
1624 struct {
1625 vuint32_t :12;
1626 vuint32_t FD:20;
1627 } B;
1628 } CMU_FDR;
1629
1630 union { /* CMU High Freq Reference FMPLL (Base+0x0108) */
1631 vuint32_t R;
1632 struct {
1633 vuint32_t :20;
1634 vuint32_t HFREF:12;
1635 } B;
1636 } CMU_HFREFR;
1637
1638 union { /* CMU Low Freq Reference FMPLL (Base+0x010C) */
1639 vuint32_t R;
1640 struct {
1641 vuint32_t :20;
1642 vuint32_t LFREF:12;
1643 } B;
1644 } CMU_LFREFR;
1645
1646 union { /* CMU Interrupt Status (Base+0x0110) */
1647 vuint32_t R;
1648 struct {
1649 vuint32_t :29;
1650 vuint32_t FHHI:1; // *_A not present in RM
1651 vuint32_t FLLI:1; // *_A not present in RM
1652 vuint32_t OLRI:1;
1653 } B;
1654 } CMU_ISR;
1655
1656 /* Reserved space where IMR was previously positioned */
1657 vuint8_t CGM_reserved5[4]; /*Reserved 4 bytes (Base+0x0114-0x0117) */
1658
1659 union { /* CMU Measurement Duration (Base+0x0118) */
1660 vuint32_t R;
1661 struct {
1662 vuint32_t :12;
1663 vuint32_t MD:20;
1664 } B;
1665 } CMU_MDR;
1666
1667
1668 /* Reserved space between end of CMU and start of CGM Block 2 */
1669 vuint8_t CGM_reserved6[596]; /*Reserved 596 bytes (Base+0x011C-0x036F) */
1670
1671 union { /* GCM Output Clock Enable (Base+0x0370) */
1672 vuint32_t R;
1673 struct {
1674 vuint32_t :31;
1675 vuint32_t EN:1;
1676 } B;
1677 } OC_EN;
1678
1679 union { /* CGM Output Clock Division Sel (Base+0x0374) */
1680 vuint32_t R;
1681 struct {
1682 vuint32_t :2;
1683 vuint32_t SELDIV:2;
1684 vuint32_t SELCTL:4;
1685 vuint32_t :24;
1686 } B;
1687 } OCDS_SC;
1688
1689 union { /* CGM System Clock Select Status (Base+0x0378) */
1690 vuint32_t R;
1691 struct {
1692 vuint32_t :4;
1693 vuint32_t SELSTAT:4;
1694 vuint32_t :24;
1695 } B;
1696 } SC_SS;
1697
1698 union { /* CGM Sys Clk Div Config0 (Base+0x037C) */
1699 vuint8_t R;
1700 struct {
1701 vuint8_t DE0:1;
1702 vuint8_t :3;
1703 vuint8_t DIV0:4;
1704 } B;
1705 } SC_DC0;
1706
1707 union { /* CGM Sys Clk Div Config1 (Base+0x037D) */
1708 vuint8_t R;
1709 struct {
1710 vuint8_t DE1:1;
1711 vuint8_t :3;
1712 vuint8_t DIV1:4;
1713 } B;
1714 } SC_DC1;
1715
1716 union { /* CGM Sys Clk Div Config1 (Base+0x037E) */
1717 vuint8_t R;
1718 struct {
1719 vuint8_t DE2:1;
1720 vuint8_t :3;
1721 vuint8_t DIV2:4;
1722 } B;
1723 } SC_DC2;
1724
1725 vuint8_t CGM_reserved7[1]; /*Reserved 1 byte (Base+0x037F) */
1726
1727 union { /* CGM Aux clock select control register (Base+0x0380) */
1728 vuint32_t R;
1729 struct {
1730 vuint32_t :4;
1731 vuint32_t SELCTL:4;
1732 vuint32_t :24;
1733 } B;
1734 } AC0_SC;
1735
1736
1737
1738}; /* end of CGM_tag */
1739
1740/****************************************************************************/
1741/* MODULE : RGM base address - 0xC3FE_4000 */
1742/****************************************************************************/
1743struct RGM_tag{
1744
1745 union { /* Functional Event Status (Base+0x0000) */
1746 vuint16_t R;
1747 struct {
1748 vuint16_t F_EXR:1;
1749 vuint16_t :6;
1750 vuint16_t F_FLASH:1;
1751 vuint16_t F_LVD45:1;
1752 vuint16_t F_CMU_FHL:1;
1753 vuint16_t F_CMU_OLR:1;
1754 vuint16_t F_FMPLL:1;
1755 vuint16_t F_CHKSTOP:1;
1756 vuint16_t F_SOFT_FUNC :1;
1757 vuint16_t F_CORE:1;
1758 vuint16_t F_JTAG:1;
1759 } B;
1760 } FES;
1761
1762 union { /* Destructive Event Status (Base+0x0002) */
1763 vuint16_t R;
1764 struct {
1765 vuint16_t F_POR:1;
1766 vuint16_t :10;
1767 vuint16_t F_LVD27_VREG:1;
1768 vuint16_t F_LVD27:1;
1769 vuint16_t F_SWT:1;
1770 vuint16_t F_LVD12_PD1:1;
1771 vuint16_t F_LVD12_PD0:1;
1772 } B;
1773 } DES;
1774
1775 union { /* Functional Event Reset Disable (+0x0004) */
1776 vuint16_t R;
1777 struct {
1778 vuint16_t D_EXR:1;
1779 vuint16_t :6;
1780 vuint16_t D_FLASH:1;
1781 vuint16_t D_LVD45:1;
1782 vuint16_t D_CMU_FHL:1;
1783 vuint16_t D_CMU_OLR:1;
1784 vuint16_t D_FMPLL:1;
1785 vuint16_t D_CHKSTOP:1;
1786 vuint16_t D_SOFT_FUNC:1;
1787 vuint16_t D_CORE:1;
1788 vuint16_t D_JTAG:1;
1789 } B;
1790 } FERD;
1791
1792 union { /* Destructive Event Reset Disable (Base+0x0006)*/
1793 vuint16_t R;
1794 struct {
1795 vuint16_t :11;
1796 vuint16_t D_LVD27_VREG:1;
1797 vuint16_t D_LVD27:1;
1798 vuint16_t D_SWT:1;
1799 vuint16_t D_LVD12_PD1:1;
1800 vuint16_t D_LVD12_PD0:1;
1801 } B;
1802 } DERD;
1803
1804 vuint8_t RGM_reserved0[8]; /*Reserved 8 bytes (Base+0x008-0x000F) */
1805
1806 union { /* Functional Event Alt Request (Base+0x0010) */
1807 vuint16_t R;
1808 struct {
1809 vuint16_t AR_EXR:1;
1810 vuint16_t:6;
1811 vuint16_t AR_FLASH:1;
1812 vuint16_t AR_LVD45:1;
1813 vuint16_t AR_CMU_FHL:1;
1814 vuint16_t AR_CMU_OLR:1;
1815 vuint16_t AR_FMPLL:1;
1816 vuint16_t AR_CHKSTOP:1;
1817 vuint16_t AR_SOFT_FUNC:1;
1818 vuint16_t AR_CORE:1;
1819 vuint16_t AR_JTAG:1;
1820 } B;
1821 } FEAR;
1822
1823 union { /* Destructive Event Alt Request (Base+0x0012) */
1824 vuint16_t R;
1825 struct {
1826 vuint16_t:11;
1827 vuint16_t AR_LVD27_VREG:1;
1828 vuint16_t AR_LVD27:1;
1829 vuint16_t AR_SWT:1;
1830 vuint16_t AR_LVD12_PD1:1;
1831 vuint16_t AR_LVD12_PD0:1;
1832 } B;
1833 } DEAR; /* Destructive Event Alternate Request */
1834
1835 vuint8_t RGM_reserved1[4]; /*Reserved 4 bytes (Base+0x0014-0x0017) */
1836
1837 union { /* Functional Event Short Sequence (+0x0018) */
1838 vuint16_t R;
1839 struct {
1840 vuint16_t SS_EXR:1;
1841 vuint16_t :6;
1842 vuint16_t SS_FLASH:1;
1843 vuint16_t SS_LVD45:1;
1844 vuint16_t SS_CMU_FHL:1;
1845 vuint16_t SS_CMU_OLR:1;
1846 vuint16_t SS_FMPLL:1;
1847 vuint16_t SS_CHKSTOP:1;
1848 vuint16_t SS_SOFT_FUNC:1;
1849 vuint16_t SS_CORE:1;
1850 vuint16_t SS_JTAG:1;
1851 } B;
1852 } FESS;
1853
1854 union { /* STANDBY reset sequence (Base+0x001A) */
1855 vuint16_t R;
1856 struct {
1857 vuint16_t :8;
1858 vuint16_t BOOT_FROM_BKP_RAM:1;
1859 vuint16_t :7;
1860 } B;
1861 } STDBY;
1862
1863 union { /* Functional Bidirectional Reset En (+0x001C) */
1864 vuint16_t R;
1865 struct {
1866 vuint16_t BE_EXR:1;
1867 vuint16_t :6;
1868 vuint16_t BE_FLASH:1;
1869 vuint16_t BE_LVD45:1;
1870 vuint16_t BE_CMU_FHL:1;
1871 vuint16_t BE_CMU_OLR:1;
1872 vuint16_t BE_FMPLL:1;
1873 vuint16_t BE_CHKSTOP:1;
1874 vuint16_t BE_SOFT_FUNC:1;
1875 vuint16_t BE_CORE:1;
1876 vuint16_t BE_JTAG:1;
1877 } B;
1878 } FBRE;
1879
1880}; /* end of RGM_tag */
1881/****************************************************************************/
1882/* MODULE : PCU (base address 0xC3FE_8000) */
1883/****************************************************************************/
1884struct PCU_tag{
1885
1886 union { /* PCU Power domain 0-3 config (+0x0000-0x000C) */
1887 vuint32_t R;
1888 struct {
1889 vuint32_t :18;
1890 vuint32_t STBY:1;
1891 vuint32_t :2;
1892 vuint32_t STOP:1;
1893 vuint32_t :1;
1894 vuint32_t HALT:1;
1895 vuint32_t RUN3:1;
1896 vuint32_t RUN2:1;
1897 vuint32_t RUN1:1;
1898 vuint32_t RUN0:1;
1899 vuint32_t DRUN:1;
1900 vuint32_t SAFE:1;
1901 vuint32_t TEST:1;
1902 vuint32_t RST:1;
1903 } B;
1904 } PCONF[4];
1905
1906 vuint8_t PCU_reserved0[48]; /* Reserved 48 bytes (Base+0x0010-0x003F) */
1907
1908 union { /* PCU Power Domain Status (Base+0x0040) */
1909 vuint32_t R;
1910 struct {
1911 vuint32_t :28;
1912 vuint32_t PD3:1;
1913 vuint32_t PD2:1;
1914 vuint32_t PD1:1;
1915 vuint32_t PD0:1;
1916 } B;
1917 } PSTAT;
1918
1919 vuint8_t PCU_reserved1[60]; /* Reserved 60 bytes (Base+0x0044-0x007F) */
1920
1921
1922 /* Following register is from Voltage Regulators chapter of RM */
1923
1924 union { /* PCU Voltage Regulator Control (Base+0x0080) */
1925 vuint32_t R;
1926 struct {
1927 vuint32_t :31;
1928 vuint32_t MASK_LVDHV5:1;
1929 } B;
1930 } VREG_CTL; /* Changed from VCTL for consistency with other regs here */
1931
1932 }; /* end of PCU_tag */
1933/****************************************************************************/
1934/* MODULE : RTC/API */
1935/****************************************************************************/
1936struct RTC_tag{
1937
1938 union { /* RTC Supervisor Control (Base+0x0000) */
1939 vuint32_t R;
1940 struct {
1941 vuint32_t SUPV:1;
1942 vuint32_t :31;
1943 } B;
1944 } RTCSUPV ;
1945
1946 union { /* RTC Control (Base+0x0004) */
1947 vuint32_t R;
1948 struct {
1949 vuint32_t CNTEN:1;
1950 vuint32_t RTCIE:1;
1951 vuint32_t FRZEN:1;
1952 vuint32_t ROVREN:1;
1953 vuint32_t RTCVAL:12;
1954 vuint32_t APIEN:1;
1955 vuint32_t APIIE:1;
1956 vuint32_t CLKSEL:2;
1957 vuint32_t DIV512EN:1;
1958 vuint32_t DIV32EN:1;
1959 vuint32_t APIVAL:10;
1960 } B;
1961 } RTCC;
1962
1963 union { /* RTC Status (Base+0x0008) */
1964 vuint32_t R;
1965 struct {
1966 vuint32_t :2;
1967 vuint32_t RTCF:1;
1968 vuint32_t :15;
1969 vuint32_t APIF:1;
1970 vuint32_t :2;
1971 vuint32_t ROVRF:1;
1972 vuint32_t :10;
1973 } B;
1974 } RTCS;
1975
1976 union { /* RTC Counter (Base+0x000C) */
1977 vuint32_t R;
1978 struct {
1979 vuint32_t RTCCNT:32;
1980 } B;
1981 } RTCCNT;
1982
1983}; /* end of RTC_tag */
1984
1985/****************************************************************************/
1986/* MODULE : PIT (base address - 0xC3FF_FFFF) */
1987/****************************************************************************/
1988 struct PIT_tag {
1989
1990 union { /* PIT Module Control (Base+0x0000) */
1991 vuint32_t R;
1992 struct {
1993 vuint32_t:30;
1994 vuint32_t MDIS:1;
1995 vuint32_t FRZ:1;
1996 } B;
1997 } PITMCR;
1998
1999 vuint8_t PIT_reserved0[252]; /* Reserved 252 Bytes (Base+0x0004-0x00FF) */
2000
2001 /* PIT Timer Channels 0..7 (Base+0x0100-0x017C) */
2002 struct {
2003
2004 union { /* PIT Timer Load Value (Offset+0x0000) */
2005 vuint32_t R;
2006 struct {
2007 vuint32_t TSV:32;
2008 } B;
2009 } LDVAL;
2010
2011 union { /* PIT Current Timer Value (Offset+0x0004) */
2012 vuint32_t R;
2013 struct {
2014 vuint32_t TVL:32;
2015 } B;
2016 } CVAL;
2017
2018 union { /* PIT Timer Control (Offset+0x0008) */
2019 vuint32_t R;
2020 struct {
2021 vuint32_t :30;
2022 vuint32_t TIE:1;
2023 vuint32_t TEN:1;
2024 } B;
2025 } TCTRL;
2026
2027 union { /* PIT Timer Control (Offset+0x0008) */
2028 vuint32_t R;
2029 struct {
2030 vuint32_t :31;
2031 vuint32_t TIF:1;
2032 } B;
2033 } TFLG;
2034
2035 }CH[8]; /* End of PIT Timer Channels */
2036
2037}; /* end of PIT_tag */
2038
2039/****************************************************************************/
2040/* MODULE : ADC1 (12 Bit) */
2041/****************************************************************************/
2042struct ADC1_tag {
2043
2044 union { /* ADC1 Main Configuration (Base+0x0000) */
2045 vuint32_t R;
2046 struct {
2047 vuint32_t OWREN:1;
2048 vuint32_t WLSIDE:1;
2049 vuint32_t MODE:1;
2050 vuint32_t:4;
2051 vuint32_t NSTART:1;
2052 vuint32_t:1;
2053 vuint32_t JTRGEN:1;
2054 vuint32_t JEDGE:1;
2055 vuint32_t JSTART:1;
2056 vuint32_t:2;
2057 vuint32_t CTUEN:1;
2058 vuint32_t:8;
2059 vuint32_t ADCLKSEL:1;
2060 vuint32_t ABORTCHAIN:1;
2061 vuint32_t ABORT:1;
2062 vuint32_t ACKO:1;
2063 vuint32_t:4;
2064 vuint32_t PWDN:1;
2065 } B;
2066 } MCR;
2067
2068 union { /* ADC1 Main Status (Base+0x0004) */
2069 vuint32_t R;
2070 struct {
2071 vuint32_t:7;
2072 vuint32_t NSTART:1;
2073 vuint32_t JABORT:1;
2074 vuint32_t:2;
2075 vuint32_t JSTART:1;
2076 vuint32_t:3;
2077 vuint32_t CTUSTART:1;
2078 vuint32_t CHADDR:7;
2079 vuint32_t:3;
2080 vuint32_t ACKO:1;
2081 vuint32_t:2;
2082 vuint32_t ADCSTATUS:3;
2083 } B;
2084 } MSR;
2085
2086 vuint8_t ADC1_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
2087
2088 union { /* ADC1 Interrupt Status (Base+0x0010) */
2089 vuint32_t R;
2090 struct {
2091 vuint32_t:27;
2092 vuint32_t EOCTU:1;
2093 vuint32_t JEOC:1;
2094 vuint32_t JECH:1;
2095 vuint32_t EOC:1;
2096 vuint32_t ECH:1;
2097 } B;
2098 } ISR;
2099
2100 union { /* ADC1 Channel Pending 0 (Base+0x0014) */
2101 vuint32_t R; /* (For precision channels) */
2102 struct {
2103 vuint32_t :16;
2104 vuint32_t EOC_CH15:1;
2105 vuint32_t EOC_CH14:1;
2106 vuint32_t EOC_CH13:1;
2107 vuint32_t EOC_CH12:1;
2108 vuint32_t EOC_CH11:1;
2109 vuint32_t EOC_CH10:1;
2110 vuint32_t EOC_CH9:1;
2111 vuint32_t EOC_CH8:1;
2112 vuint32_t EOC_CH7:1;
2113 vuint32_t EOC_CH6:1;
2114 vuint32_t EOC_CH5:1;
2115 vuint32_t EOC_CH4:1;
2116 vuint32_t EOC_CH3:1;
2117 vuint32_t EOC_CH2:1;
2118 vuint32_t EOC_CH1:1;
2119 vuint32_t EOC_CH0:1;
2120 } B;
2121 } CEOCFR0;
2122
2123 union { /* ADC1 Channel Pending 1 (Base+0x0018) */
2124 vuint32_t R; /* (For standard Channels) */
2125 struct {
2126 vuint32_t:19;
2127 vuint32_t EOC_CH44:1;
2128 vuint32_t EOC_CH43:1;
2129 vuint32_t EOC_CH42:1;
2130 vuint32_t EOC_CH41:1;
2131 vuint32_t EOC_CH40:1;
2132 vuint32_t EOC_CH39:1;
2133 vuint32_t EOC_CH38:1;
2134 vuint32_t EOC_CH37:1;
2135 vuint32_t EOC_CH36:1;
2136 vuint32_t EOC_CH35:1;
2137 vuint32_t EOC_CH34:1;
2138 vuint32_t EOC_CH33:1;
2139 vuint32_t EOC_CH32:1;
2140 } B;
2141 } CEOCFR1;
2142
2143 union { /* ADC1 Channel Pending 2 (Base+0x001C) */
2144 vuint32_t R; /* (For External Channels) */
2145 struct {
2146 vuint32_t EOC_CH95:1;
2147 vuint32_t EOC_CH94:1;
2148 vuint32_t EOC_CH93:1;
2149 vuint32_t EOC_CH92:1;
2150 vuint32_t EOC_CH91:1;
2151 vuint32_t EOC_CH90:1;
2152 vuint32_t EOC_CH89:1;
2153 vuint32_t EOC_CH88:1;
2154 vuint32_t EOC_CH87:1;
2155 vuint32_t EOC_CH86:1;
2156 vuint32_t EOC_CH85:1;
2157 vuint32_t EOC_CH84:1;
2158 vuint32_t EOC_CH83:1;
2159 vuint32_t EOC_CH82:1;
2160 vuint32_t EOC_CH81:1;
2161 vuint32_t EOC_CH80:1;
2162 vuint32_t EOC_CH79:1;
2163 vuint32_t EOC_CH78:1;
2164 vuint32_t EOC_CH77:1;
2165 vuint32_t EOC_CH76:1;
2166 vuint32_t EOC_CH75:1;
2167 vuint32_t EOC_CH74:1;
2168 vuint32_t EOC_CH73:1;
2169 vuint32_t EOC_CH72:1;
2170 vuint32_t EOC_CH71:1;
2171 vuint32_t EOC_CH70:1;
2172 vuint32_t EOC_CH69:1;
2173 vuint32_t EOC_CH68:1;
2174 vuint32_t EOC_CH67:1;
2175 vuint32_t EOC_CH66:1;
2176 vuint32_t EOC_CH65:1;
2177 vuint32_t EOC_CH64:1;
2178 } B;
2179 } CEOCFR2;
2180
2181
2182 union { /* ADC1 Interrupt Mask (Base+0020) */
2183 vuint32_t R;
2184 struct {
2185 vuint32_t:27;
2186 vuint32_t MSKEOCTU:1;
2187 vuint32_t MSKJEOC:1;
2188 vuint32_t MSKJECH:1;
2189 vuint32_t MSKEOC:1;
2190 vuint32_t MSKECH:1;
2191 } B;
2192 } IMR;
2193
2194 union { /* ADC1 Channel Interrupt Mask 0 (Base+0x0024) */
2195 vuint32_t R; /* (For Precision Channels) */
2196 struct {
2197 vuint32_t:16;
2198 vuint32_t CIM15:1;
2199 vuint32_t CIM14:1;
2200 vuint32_t CIM13:1;
2201 vuint32_t CIM12:1;
2202 vuint32_t CIM11:1;
2203 vuint32_t CIM10:1;
2204 vuint32_t CIM9:1;
2205 vuint32_t CIM8:1;
2206 vuint32_t CIM7:1;
2207 vuint32_t CIM6:1;
2208 vuint32_t CIM5:1;
2209 vuint32_t CIM4:1;
2210 vuint32_t CIM3:1;
2211 vuint32_t CIM2:1;
2212 vuint32_t CIM1:1;
2213 vuint32_t CIM0:1;
2214 } B;
2215 } CIMR0;
2216
2217 union { /* ADC1 Channel Interrupt Mask 1 (+0x0028) */
2218 vuint32_t R; /* (For Standard Channels) */
2219 struct {
2220 vuint32_t:19;
2221 vuint32_t CIM44:1;
2222 vuint32_t CIM43:1;
2223 vuint32_t CIM42:1;
2224 vuint32_t CIM41:1;
2225 vuint32_t CIM40:1;
2226 vuint32_t CIM39:1;
2227 vuint32_t CIM38:1;
2228 vuint32_t CIM37:1;
2229 vuint32_t CIM36:1;
2230 vuint32_t CIM35:1;
2231 vuint32_t CIM34:1;
2232 vuint32_t CIM33:1;
2233 vuint32_t CIM32:1;
2234 } B;
2235 } CIMR1;
2236
2237 union { /* ADC1 Channel Interrupt Mask 2 (Base+0x002C) */
2238 vuint32_t R; /* (For External Mux'd Channels) */
2239 struct {
2240 vuint32_t CIM95:1;
2241 vuint32_t CIM94:1;
2242 vuint32_t CIM93:1;
2243 vuint32_t CIM92:1;
2244 vuint32_t CIM91:1;
2245 vuint32_t CIM90:1;
2246 vuint32_t CIM89:1;
2247 vuint32_t CIM88:1;
2248 vuint32_t CIM87:1;
2249 vuint32_t CIM86:1;
2250 vuint32_t CIM85:1;
2251 vuint32_t CIM84:1;
2252 vuint32_t CIM83:1;
2253 vuint32_t CIM82:1;
2254 vuint32_t CIM81:1;
2255 vuint32_t CIM80:1;
2256 vuint32_t CIM79:1;
2257 vuint32_t CIM78:1;
2258 vuint32_t CIM77:1;
2259 vuint32_t CIM76:1;
2260 vuint32_t CIM75:1;
2261 vuint32_t CIM74:1;
2262 vuint32_t CIM73:1;
2263 vuint32_t CIM72:1;
2264 vuint32_t CIM71:1;
2265 vuint32_t CIM70:1;
2266 vuint32_t CIM69:1;
2267 vuint32_t CIM68:1;
2268 vuint32_t CIM67:1;
2269 vuint32_t CIM66:1;
2270 vuint32_t CIM65:1;
2271 vuint32_t CIM64:1;
2272 } B;
2273 } CIMR2;
2274
2275
2276 union { /* ADC1 Watchdog Threshold Interrupt Status (+0x0030)*/
2277 vuint32_t R;
2278 struct {
2279 vuint32_t:26;
2280 vuint32_t WDG2H:1;
2281 vuint32_t WDG2L:1;
2282 vuint32_t WDG1H:1;
2283 vuint32_t WDG1L:1;
2284 vuint32_t WDG0H:1;
2285 vuint32_t WDG0L:1;
2286 } B;
2287 } WTISR;
2288
2289 union { /* ADC1 Watchdog Threshold Interrupt Mask (+0x0034) */
2290 vuint32_t R;
2291 struct {
2292 vuint32_t:26;
2293 vuint32_t MSKWDG2H:1;
2294 vuint32_t MSKWDG2L:1;
2295 vuint32_t MSKWDG1H:1;
2296 vuint32_t MSKWDG1L:1;
2297 vuint32_t MSKWDG0H:1;
2298 vuint32_t MSKWDG0L:1;
2299 } B;
2300 } WTIMR;
2301
2302 vuint8_t ADC1_reserved3[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */
2303
2304 union { /* ADC1 DMA Enable (Base+0x0040) */
2305 vuint32_t R;
2306 struct {
2307 vuint32_t:30;
2308 vuint32_t DCLR:1;
2309 vuint32_t DMAEN:1;
2310 } B;
2311 } DMAE;
2312
2313 union { /* ADC1 DMA Channel Select 0 (Base+0x0044) */
2314 vuint32_t R; /* (for precision channels) */
2315 struct {
2316 vuint32_t:16;
2317 vuint32_t DMA15:1;
2318 vuint32_t DMA14:1;
2319 vuint32_t DMA13:1;
2320 vuint32_t DMA12:1;
2321 vuint32_t DMA11:1;
2322 vuint32_t DMA10:1;
2323 vuint32_t DMA9:1;
2324 vuint32_t DMA8:1;
2325 vuint32_t DMA7:1;
2326 vuint32_t DMA6:1;
2327 vuint32_t DMA5:1;
2328 vuint32_t DMA4:1;
2329 vuint32_t DMA3:1;
2330 vuint32_t DMA2:1;
2331 vuint32_t DMA1:1;
2332 vuint32_t DMA0:1;
2333 } B;
2334 } DMAR0;
2335
2336 union { /* ADC1 DMA Channel Select 1 (Base+0x0048) */
2337 vuint32_t R; /* (for precision channels) */
2338 struct {
2339 vuint32_t:19;
2340 vuint32_t DMA44:1;
2341 vuint32_t DMA43:1;
2342 vuint32_t DMA42:1;
2343 vuint32_t DMA41:1;
2344 vuint32_t DMA40:1;
2345 vuint32_t DMA39:1;
2346 vuint32_t DMA38:1;
2347 vuint32_t DMA37:1;
2348 vuint32_t DMA36:1;
2349 vuint32_t DMA35:1;
2350 vuint32_t DMA34:1;
2351 vuint32_t DMA33:1;
2352 vuint32_t DMA32:1;
2353 } B;
2354 } DMAR1;
2355
2356 union { /* ADC1 DMA Channel Select 2 (Base+0x004C) */
2357 vuint32_t R; /* (for External channels) */
2358 struct {
2359 vuint32_t DMA95:1;
2360 vuint32_t DMA94:1;
2361 vuint32_t DMA93:1;
2362 vuint32_t DMA92:1;
2363 vuint32_t DMA91:1;
2364 vuint32_t DMA90:1;
2365 vuint32_t DMA89:1;
2366 vuint32_t DMA88:1;
2367 vuint32_t DMA87:1;
2368 vuint32_t DMA86:1;
2369 vuint32_t DMA85:1;
2370 vuint32_t DMA84:1;
2371 vuint32_t DMA83:1;
2372 vuint32_t DMA82:1;
2373 vuint32_t DMA81:1;
2374 vuint32_t DMA80:1;
2375 vuint32_t DMA79:1;
2376 vuint32_t DMA78:1;
2377 vuint32_t DMA77:1;
2378 vuint32_t DMA76:1;
2379 vuint32_t DMA75:1;
2380 vuint32_t DMA74:1;
2381 vuint32_t DMA73:1;
2382 vuint32_t DMA72:1;
2383 vuint32_t DMA71:1;
2384 vuint32_t DMA70:1;
2385 vuint32_t DMA69:1;
2386 vuint32_t DMA68:1;
2387 vuint32_t DMA67:1;
2388 vuint32_t DMA66:1;
2389 vuint32_t DMA65:1;
2390 vuint32_t DMA64:1;
2391 } B;
2392 } DMAR2;
2393
2394 vuint8_t ADC1_reserved4[16]; /* Reserved 16 bytes (Base+0x0048-0x005F) */
2395
2396 /* Note the threshold registers are not implemented as an array for */
2397 /* concistency with ADC0 header section */
2398
2399 union { /* ADC1 Threshold 0 (Base+0x0060) */
2400 vuint32_t R;
2401 struct {
2402 vuint32_t:4;
2403 vuint32_t THRH:12;
2404 vuint32_t:4;
2405 vuint32_t THRL:12;
2406 } B;
2407 } THRHLR0;
2408
2409 union { /* ADC1 Threshold 1 (Base+0x0064) */
2410 vuint32_t R;
2411 struct {
2412 vuint32_t:4;
2413 vuint32_t THRH:12;
2414 vuint32_t:4;
2415 vuint32_t THRL:12;
2416 } B;
2417 } THRHLR1;
2418
2419 union { /* ADC1 Threshold 2 (Base+0x0068) */
2420 vuint32_t R;
2421 struct {
2422 vuint32_t:4;
2423 vuint32_t THRH:12;
2424 vuint32_t:4;
2425 vuint32_t THRL:12;
2426 } B;
2427 } THRHLR2;
2428
2429 vuint8_t ADC1_reserved5[20]; /* Reserved 20 bytes (Base+0x006C-0x007F) */
2430
2431 union { /* ADC1 Presampling Control (Base+0x0080) */
2432 vuint32_t R;
2433 struct {
2434 vuint32_t:25;
2435 vuint32_t PREVAL2:2;
2436 vuint32_t PREVAL1:2;
2437 vuint32_t PREVAL0:2;
2438 vuint32_t PRECONV:1;
2439 } B;
2440 } PSCR;
2441
2442 union { /* ADC1 Presampling 0 (Base+0x0084) */
2443 vuint32_t R; /* (precision channels) */
2444 struct {
2445 vuint32_t:16;
2446 vuint32_t PRES15:1;
2447 vuint32_t PRES14:1;
2448 vuint32_t PRES13:1;
2449 vuint32_t PRES12:1;
2450 vuint32_t PRES11:1;
2451 vuint32_t PRES10:1;
2452 vuint32_t PRES9:1;
2453 vuint32_t PRES8:1;
2454 vuint32_t PRES7:1;
2455 vuint32_t PRES6:1;
2456 vuint32_t PRES5:1;
2457 vuint32_t PRES4:1;
2458 vuint32_t PRES3:1;
2459 vuint32_t PRES2:1;
2460 vuint32_t PRES1:1;
2461 vuint32_t PRES0:1;
2462 } B;
2463 } PSR0;
2464
2465 union { /* ADC1 Presampling 1 (Base+0x0088) */
2466 vuint32_t R; /* (standard channels) */
2467 struct {
2468 vuint32_t:19;
2469 vuint32_t PRES44:1;
2470 vuint32_t PRES43:1;
2471 vuint32_t PRES42:1;
2472 vuint32_t PRES41:1;
2473 vuint32_t PRES40:1;
2474 vuint32_t PRES39:1;
2475 vuint32_t PRES38:1;
2476 vuint32_t PRES37:1;
2477 vuint32_t PRES36:1;
2478 vuint32_t PRES35:1;
2479 vuint32_t PRES34:1;
2480 vuint32_t PRES33:1;
2481 vuint32_t PRES32:1;
2482 } B;
2483 } PSR1;
2484
2485
2486 union { /* ADC1 Presampling 2 (Base+0x008C) */
2487 vuint32_t R; /* (precision channels) */
2488 struct {
2489 vuint32_t PRES95:1;
2490 vuint32_t PRES94:1;
2491 vuint32_t PRES93:1;
2492 vuint32_t PRES92:1;
2493 vuint32_t PRES91:1;
2494 vuint32_t PRES90:1;
2495 vuint32_t PRES89:1;
2496 vuint32_t PRES88:1;
2497 vuint32_t PRES87:1;
2498 vuint32_t PRES86:1;
2499 vuint32_t PRES85:1;
2500 vuint32_t PRES84:1;
2501 vuint32_t PRES83:1;
2502 vuint32_t PRES82:1;
2503 vuint32_t PRES81:1;
2504 vuint32_t PRES80:1;
2505 vuint32_t PRES79:1;
2506 vuint32_t PRES78:1;
2507 vuint32_t PRES77:1;
2508 vuint32_t PRES76:1;
2509 vuint32_t PRES75:1;
2510 vuint32_t PRES74:1;
2511 vuint32_t PRES73:1;
2512 vuint32_t PRES72:1;
2513 vuint32_t PRES71:1;
2514 vuint32_t PRES70:1;
2515 vuint32_t PRES69:1;
2516 vuint32_t PRES68:1;
2517 vuint32_t PRES67:1;
2518 vuint32_t PRES66:1;
2519 vuint32_t PRES65:1;
2520 vuint32_t PRES64:1;
2521 } B;
2522 } PSR2;
2523
2524
2525 vuint8_t ADC1_reserved6[4]; /* Reserved 4 bytes (Base+0x0090-0x0093) */
2526
2527 /* Note the following CTR registers are NOT implemented as an array to */
2528 /* try and maintain some concistency through the header file */
2529 /* (The registers are however identical) */
2530
2531 union { /* ADC1 Conversion Timing 0 (Base+0x0094) */
2532 vuint32_t R; /* (precision channels) */
2533 struct {
2534 vuint32_t:16;
2535 vuint32_t INPLATCH:1;
2536 vuint32_t:1;
2537 vuint32_t OFFSHIFT:2;
2538 vuint32_t:1;
2539 vuint32_t INPCMP:2;
2540 vuint32_t:1;
2541 vuint32_t INPSAMP:8;
2542 } B;
2543 } CTR0;
2544
2545 union { /* ADC1 Conversion Timing 1 (Base+0x0098) */
2546 vuint32_t R; /* (standard channels) */
2547 struct {
2548 vuint32_t:16;
2549 vuint32_t INPLATCH:1;
2550 vuint32_t:4;
2551 vuint32_t INPCMP:2;
2552 vuint32_t:1;
2553 vuint32_t INPSAMP:8;
2554 } B;
2555 } CTR1;
2556
2557
2558 union { /* ADC1 Conversion Timing 2 (Base+0x009C) */
2559 vuint32_t R; /* (External channels) */
2560 struct {
2561 vuint32_t:16;
2562 vuint32_t INPLATCH:1;
2563 vuint32_t:4;
2564 vuint32_t INPCMP:2;
2565 vuint32_t:1;
2566 vuint32_t INPSAMP:8;
2567 } B;
2568 } CTR2;
2569
2570 vuint8_t ADC1_reserved7[4]; /* Reserved 4 bytes (Base+0x00A0-0x00A3) */
2571
2572 union { /* ADC1 Normal Conversion Mask 0 (Base+0x00A4) */
2573 vuint32_t R; /* (precision channels) */
2574 struct {
2575 vuint32_t :16;
2576 vuint32_t CH15:1;
2577 vuint32_t CH14:1;
2578 vuint32_t CH13:1;
2579 vuint32_t CH12:1;
2580 vuint32_t CH11:1;
2581 vuint32_t CH10:1;
2582 vuint32_t CH9:1;
2583 vuint32_t CH8:1;
2584 vuint32_t CH7:1;
2585 vuint32_t CH6:1;
2586 vuint32_t CH5:1;
2587 vuint32_t CH4:1;
2588 vuint32_t CH3:1;
2589 vuint32_t CH2:1;
2590 vuint32_t CH1:1;
2591 vuint32_t CH0:1;
2592 } B;
2593 } NCMR0;
2594
2595 union { /* ADC1 Normal Conversion Mask 1 (Base+0x00A8) */
2596 vuint32_t R; /* (standard channels) */
2597 struct {
2598 vuint32_t:19;
2599 vuint32_t CH44:1;
2600 vuint32_t CH43:1;
2601 vuint32_t CH42:1;
2602 vuint32_t CH41:1;
2603 vuint32_t CH40:1;
2604 vuint32_t CH39:1;
2605 vuint32_t CH38:1;
2606 vuint32_t CH37:1;
2607 vuint32_t CH36:1;
2608 vuint32_t CH35:1;
2609 vuint32_t CH34:1;
2610 vuint32_t CH33:1;
2611 vuint32_t CH32:1;
2612 } B;
2613 } NCMR1;
2614
2615
2616 union { /* ADC1 Normal Conversion Mask 2 (Base+0x00AC) */
2617 vuint32_t R; /* (External channels) */
2618 struct {
2619 vuint32_t CH95:1;
2620 vuint32_t CH94:1;
2621 vuint32_t CH93:1;
2622 vuint32_t CH92:1;
2623 vuint32_t CH91:1;
2624 vuint32_t CH90:1;
2625 vuint32_t CH89:1;
2626 vuint32_t CH88:1;
2627 vuint32_t CH87:1;
2628 vuint32_t CH86:1;
2629 vuint32_t CH85:1;
2630 vuint32_t CH84:1;
2631 vuint32_t CH83:1;
2632 vuint32_t CH82:1;
2633 vuint32_t CH81:1;
2634 vuint32_t CH80:1;
2635 vuint32_t CH79:1;
2636 vuint32_t CH78:1;
2637 vuint32_t CH77:1;
2638 vuint32_t CH76:1;
2639 vuint32_t CH75:1;
2640 vuint32_t CH74:1;
2641 vuint32_t CH73:1;
2642 vuint32_t CH72:1;
2643 vuint32_t CH71:1;
2644 vuint32_t CH70:1;
2645 vuint32_t CH69:1;
2646 vuint32_t CH68:1;
2647 vuint32_t CH67:1;
2648 vuint32_t CH66:1;
2649 vuint32_t CH65:1;
2650 vuint32_t CH64:1;
2651 } B;
2652 } NCMR2;
2653
2654 vuint8_t ADC1_reserved8[4]; /* Reserved 4 bytes (Base+0x00B0-0x00B4) */
2655
2656 union { /* ADC1 Injected Conversion Mask0 (Base+0x00B4) */
2657 vuint32_t R; /* (precision channels) */
2658 struct {
2659 vuint32_t :16;
2660 vuint32_t CH15:1;
2661 vuint32_t CH14:1;
2662 vuint32_t CH13:1;
2663 vuint32_t CH12:1;
2664 vuint32_t CH11:1;
2665 vuint32_t CH10:1;
2666 vuint32_t CH9:1;
2667 vuint32_t CH8:1;
2668 vuint32_t CH7:1;
2669 vuint32_t CH6:1;
2670 vuint32_t CH5:1;
2671 vuint32_t CH4:1;
2672 vuint32_t CH3:1;
2673 vuint32_t CH2:1;
2674 vuint32_t CH1:1;
2675 vuint32_t CH0:1;
2676 } B;
2677 } JCMR0;
2678
2679 union { /* ADC1 Injected Conversion Mask1 (Base+0x00B8) */
2680 vuint32_t R; /* (standard channels) */
2681 struct {
2682 vuint32_t :19;
2683 vuint32_t CH44:1;
2684 vuint32_t CH43:1;
2685 vuint32_t CH42:1;
2686 vuint32_t CH41:1;
2687 vuint32_t CH40:1;
2688 vuint32_t CH39:1;
2689 vuint32_t CH38:1;
2690 vuint32_t CH37:1;
2691 vuint32_t CH36:1;
2692 vuint32_t CH35:1;
2693 vuint32_t CH34:1;
2694 vuint32_t CH33:1;
2695 vuint32_t CH32:1;
2696 } B;
2697 } JCMR1;
2698
2699
2700 union { /* ADC1 Injected Conversion Mask 2 (Base+0x00BC) */
2701 vuint32_t R; /* (External channels) */
2702 struct {
2703 vuint32_t CH95:1;
2704 vuint32_t CH94:1;
2705 vuint32_t CH93:1;
2706 vuint32_t CH92:1;
2707 vuint32_t CH91:1;
2708 vuint32_t CH90:1;
2709 vuint32_t CH89:1;
2710 vuint32_t CH88:1;
2711 vuint32_t CH87:1;
2712 vuint32_t CH86:1;
2713 vuint32_t CH85:1;
2714 vuint32_t CH84:1;
2715 vuint32_t CH83:1;
2716 vuint32_t CH82:1;
2717 vuint32_t CH81:1;
2718 vuint32_t CH80:1;
2719 vuint32_t CH79:1;
2720 vuint32_t CH78:1;
2721 vuint32_t CH77:1;
2722 vuint32_t CH76:1;
2723 vuint32_t CH75:1;
2724 vuint32_t CH74:1;
2725 vuint32_t CH73:1;
2726 vuint32_t CH72:1;
2727 vuint32_t CH71:1;
2728 vuint32_t CH70:1;
2729 vuint32_t CH69:1;
2730 vuint32_t CH68:1;
2731 vuint32_t CH67:1;
2732 vuint32_t CH66:1;
2733 vuint32_t CH65:1;
2734 vuint32_t CH64:1;
2735 } B;
2736 } JCMR2;
2737
2738 vuint8_t ADC1_reserved9[4]; /* Reserved 4 bytes (Base+0x00C0=0x00C4) */
2739
2740 union { /* Decode Signals Delay Register (base+0x00C4)*/
2741 vuint32_t R;
2742 struct {
2743 vuint32_t:20;
2744 vuint32_t DSD:12;
2745 } B;
2746 } DSDR;
2747
2748
2749 union { /* Power Down Exit Delay Register (base+0x00C8)*/
2750 vuint32_t R;
2751 struct {
2752 vuint32_t:24;
2753 vuint32_t PDED:8;
2754 } B;
2755 } PDEDR;
2756
2757 vuint8_t ADC1_reserved10[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */
2758
2759 union { /* ADC1 Channel 0-39 Data (Base+0x0100-0x019C) */
2760 vuint32_t R; /* Note CDR[16..31] and [44..63] are reserved 0x0140-0x017F */
2761 struct {
2762 vuint32_t:12;
2763 vuint32_t VALID:1;
2764 vuint32_t OVERW:1;
2765 vuint32_t RESULT:2;
2766 vuint32_t:4;
2767 vuint32_t CDATA:12;
2768 } B;
2769 } CDR[96];
2770
2771 vuint8_t ADC1_reserved11[48]; /* Reserved 48 bytes (Base+0x0280-0x002B0) */
2772
2773 union { /* ADC1 Channel Watchdog Select 0 (Base+0x02B0) */
2774 vuint32_t R; /* (precision channels) */
2775 struct {
2776 vuint32_t WSEL_CH7:4;
2777 vuint32_t WSEL_CH6:4;
2778 vuint32_t WSEL_CH5:4;
2779 vuint32_t WSEL_CH4:4;
2780 vuint32_t WSEL_CH3:4;
2781 vuint32_t WSEL_CH2:4;
2782 vuint32_t WSEL_CH1:4;
2783 vuint32_t WSEL_CH0:4;
2784 } B;
2785 } CWSELR0;
2786
2787 union { /* ADC1 Channel Watchdog Select 1 (Base+0x02B4) */
2788 vuint32_t R; /* (precision channels) */
2789 struct {
2790 vuint32_t WSEL_CH15:4;
2791 vuint32_t WSEL_CH14:4;
2792 vuint32_t WSEL_CH13:4;
2793 vuint32_t WSEL_CH12:4;
2794 vuint32_t WSEL_CH11:4;
2795 vuint32_t WSEL_CH10:4;
2796 vuint32_t WSEL_CH9:4;
2797 vuint32_t WSEL_CH8:4;
2798 } B;
2799 } CWSELR1;
2800
2801 vuint8_t ADC1_reserved12[8]; /* Reserved 8 bytes (Base+0x02B8-0x02BF) */
2802
2803 union { /* ADC1 Channel Watchdog Select 4 (Base+0x02C0) */
2804 vuint32_t R; /* (standard channels) */
2805 struct {
2806 vuint32_t WSEL_CH39:4;
2807 vuint32_t WSEL_CH38:4;
2808 vuint32_t WSEL_CH37:4;
2809 vuint32_t WSEL_CH36:4;
2810 vuint32_t WSEL_CH35:4;
2811 vuint32_t WSEL_CH34:4;
2812 vuint32_t WSEL_CH33:4;
2813 vuint32_t WSEL_CH32:4;
2814 } B;
2815 } CWSELR4;
2816
2817 union { /* ADC1 Channel Watchdog Select 5 (Base+0x02C4) */
2818 vuint32_t R; /* (standard channels) */
2819 struct {
2820 vuint32_t:12;
2821 vuint32_t WSEL_CH44:4;
2822 vuint32_t WSEL_CH43:4;
2823 vuint32_t WSEL_CH42:4;
2824 vuint32_t WSEL_CH41:4;
2825 vuint32_t WSEL_CH40:4;
2826 } B;
2827 } CWSELR5;
2828
2829 vuint8_t ADC1_reserved42[8]; /* Reserved 8 bytes (Base+0x02C8-0x02D0) */
2830
2831 union { /* ADC1 Channel Watchdog Select 8 (Base+0x02D0) */
2832 vuint32_t R; /* (standard channels) */
2833 struct {
2834 vuint32_t WSEL_CH71:4;
2835 vuint32_t WSEL_CH70:4;
2836 vuint32_t WSEL_CH69:4;
2837 vuint32_t WSEL_CH68:4;
2838 vuint32_t WSEL_CH67:4;
2839 vuint32_t WSEL_CH66:4;
2840 vuint32_t WSEL_CH65:4;
2841 vuint32_t WSEL_CH64:4;
2842 } B;
2843 } CWSELR8;
2844
2845 union { /* ADC1 Channel Watchdog Select 9 (Base+0x02D4) */
2846 vuint32_t R; /* (standard channels) */
2847 struct {
2848 vuint32_t WSEL_CH79:4;
2849 vuint32_t WSEL_CH78:4;
2850 vuint32_t WSEL_CH77:4;
2851 vuint32_t WSEL_CH76:4;
2852 vuint32_t WSEL_CH75:4;
2853 vuint32_t WSEL_CH74:4;
2854 vuint32_t WSEL_CH73:4;
2855 vuint32_t WSEL_CH72:4;
2856 } B;
2857 } CWSELR9;
2858
2859 union { /* ADC1 Channel Watchdog Select 10 (Base+0x02D8) */
2860 vuint32_t R; /* (standard channels) */
2861 struct {
2862 vuint32_t WSEL_CH87:4;
2863 vuint32_t WSEL_CH86:4;
2864 vuint32_t WSEL_CH85:4;
2865 vuint32_t WSEL_CH84:4;
2866 vuint32_t WSEL_CH83:4;
2867 vuint32_t WSEL_CH82:4;
2868 vuint32_t WSEL_CH81:4;
2869 vuint32_t WSEL_CH80:4;
2870 } B;
2871 } CWSELR10;
2872
2873 union { /* ADC1 Channel Watchdog Select 11 (Base+0x02DC) */
2874 vuint32_t R; /* (standard channels) */
2875 struct {
2876 vuint32_t WSEL_CH95:4;
2877 vuint32_t WSEL_CH94:4;
2878 vuint32_t WSEL_CH93:4;
2879 vuint32_t WSEL_CH92:4;
2880 vuint32_t WSEL_CH91:4;
2881 vuint32_t WSEL_CH90:4;
2882 vuint32_t WSEL_CH89:4;
2883 vuint32_t WSEL_CH88:4;
2884 } B;
2885 } CWSELR11;
2886
2887
2888 union { /* ADC1 Channel Watchdog Enable0 (Base+0x02E0) */
2889 vuint32_t R; /* (precision channels) */
2890 struct {
2891 vuint32_t :16;
2892 vuint32_t CWEN15:1;
2893 vuint32_t CWEN14:1;
2894 vuint32_t CWEN13:1;
2895 vuint32_t CWEN12:1;
2896 vuint32_t CWEN11:1;
2897 vuint32_t CWEN10:1;
2898 vuint32_t CWEN9:1;
2899 vuint32_t CWEN8:1;
2900 vuint32_t CWEN7:1;
2901 vuint32_t CWEN6:1;
2902 vuint32_t CWEN5:1;
2903 vuint32_t CWEN4:1;
2904 vuint32_t CWEN3:1;
2905 vuint32_t CWEN2:1;
2906 vuint32_t CWEN1:1;
2907 vuint32_t CWEN0:1;
2908 } B;
2909 } CWENR0;
2910
2911 union { /* ADC1 Channel Watchdog Enable1 (Base++0x02E4) */
2912 vuint32_t R; /* (standard channels) */
2913 struct {
2914 vuint32_t :19;
2915 vuint32_t CWEN44:1;
2916 vuint32_t CWEN43:1;
2917 vuint32_t CWEN42:1;
2918 vuint32_t CWEN41:1;
2919 vuint32_t CWEN40:1;
2920 vuint32_t CWEN39:1;
2921 vuint32_t CWEN38:1;
2922 vuint32_t CWEN37:1;
2923 vuint32_t CWEN36:1;
2924 vuint32_t CWEN35:1;
2925 vuint32_t CWEN34:1;
2926 vuint32_t CWEN33:1;
2927 vuint32_t CWEN32:1;
2928 } B;
2929 } CWENR1;
2930
2931 union { /* ADC1 Channel Watchdog Enable2 (Base++0x02E8) */
2932 vuint32_t R; /* (External channels) */
2933 struct {
2934 vuint32_t CWEN95:1;
2935 vuint32_t CWEN94:1;
2936 vuint32_t CWEN93:1;
2937 vuint32_t CWEN92:1;
2938 vuint32_t CWEN91:1;
2939 vuint32_t CWEN90:1;
2940 vuint32_t CWEN89:1;
2941 vuint32_t CWEN88:1;
2942 vuint32_t CWEN87:1;
2943 vuint32_t CWEN86:1;
2944 vuint32_t CWEN85:1;
2945 vuint32_t CWEN84:1;
2946 vuint32_t CWEN83:1;
2947 vuint32_t CWEN82:1;
2948 vuint32_t CWEN81:1;
2949 vuint32_t CWEN80:1;
2950 vuint32_t CWEN79:1;
2951 vuint32_t CWEN78:1;
2952 vuint32_t CWEN77:1;
2953 vuint32_t CWEN76:1;
2954 vuint32_t CWEN75:1;
2955 vuint32_t CWEN74:1;
2956 vuint32_t CWEN73:1;
2957 vuint32_t CWEN72:1;
2958 vuint32_t CWEN71:1;
2959 vuint32_t CWEN70:1;
2960 vuint32_t CWEN69:1;
2961 vuint32_t CWEN68:1;
2962 vuint32_t CWEN67:1;
2963 vuint32_t CWEN66:1;
2964 vuint32_t CWEN65:1;
2965 vuint32_t CWEN64:1;
2966 } B;
2967 } CWENR2;
2968
2969 vuint8_t ADC1_reserved14[4]; /* Reserved 4 bytes (Base+0x02EC-0x02F0) */
2970
2971 union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */
2972 vuint32_t R;
2973 struct {
2974 vuint32_t :16;
2975 vuint32_t AWORR_CH15:1;
2976 vuint32_t AWORR_CH14:1;
2977 vuint32_t AWORR_CH13:1;
2978 vuint32_t AWORR_CH12:1;
2979 vuint32_t AWORR_CH11:1;
2980 vuint32_t AWORR_CH10:1;
2981 vuint32_t AWORR_CH9:1;
2982 vuint32_t AWORR_CH8:1;
2983 vuint32_t AWORR_CH7:1;
2984 vuint32_t AWORR_CH6:1;
2985 vuint32_t AWORR_CH5:1;
2986 vuint32_t AWORR_CH4:1;
2987 vuint32_t AWORR_CH3:1;
2988 vuint32_t AWORR_CH2:1;
2989 vuint32_t AWORR_CH1:1;
2990 vuint32_t AWORR_CH0:1;
2991 } B;
2992 } AWORR0;
2993
2994 union { /* ADC1 Watchdog out of range 1 (Base+0x02F4) */
2995 vuint32_t R;
2996 struct {
2997 vuint32_t :19;
2998 vuint32_t AWORR_CH44:1;
2999 vuint32_t AWORR_CH43:1;
3000 vuint32_t AWORR_CH42:1;
3001 vuint32_t AWORR_CH41:1;
3002 vuint32_t AWORR_CH40:1;
3003 vuint32_t AWORR_CH39:1;
3004 vuint32_t AWORR_CH38:1;
3005 vuint32_t AWORR_CH37:1;
3006 vuint32_t AWORR_CH36:1;
3007 vuint32_t AWORR_CH35:1;
3008 vuint32_t AWORR_CH34:1;
3009 vuint32_t AWORR_CH33:1;
3010 vuint32_t AWORR_CH32:1;
3011 } B;
3012 } AWORR1;
3013
3014 union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */
3015 vuint32_t R;
3016 struct {
3017 vuint32_t AWORR_CH95:1;
3018 vuint32_t AWORR_CH94:1;
3019 vuint32_t AWORR_CH93:1;
3020 vuint32_t AWORR_CH92:1;
3021 vuint32_t AWORR_CH91:1;
3022 vuint32_t AWORR_CH90:1;
3023 vuint32_t AWORR_CH89:1;
3024 vuint32_t AWORR_CH88:1;
3025 vuint32_t AWORR_CH87:1;
3026 vuint32_t AWORR_CH86:1;
3027 vuint32_t AWORR_CH85:1;
3028 vuint32_t AWORR_CH84:1;
3029 vuint32_t AWORR_CH83:1;
3030 vuint32_t AWORR_CH82:1;
3031 vuint32_t AWORR_CH81:1;
3032 vuint32_t AWORR_CH80:1;
3033 vuint32_t AWORR_CH79:1;
3034 vuint32_t AWORR_CH78:1;
3035 vuint32_t AWORR_CH77:1;
3036 vuint32_t AWORR_CH76:1;
3037 vuint32_t AWORR_CH75:1;
3038 vuint32_t AWORR_CH74:1;
3039 vuint32_t AWORR_CH73:1;
3040 vuint32_t AWORR_CH72:1;
3041 vuint32_t AWORR_CH71:1;
3042 vuint32_t AWORR_CH70:1;
3043 vuint32_t AWORR_CH69:1;
3044 vuint32_t AWORR_CH68:1;
3045 vuint32_t AWORR_CH67:1;
3046 vuint32_t AWORR_CH66:1;
3047 vuint32_t AWORR_CH65:1;
3048 vuint32_t AWORR_CH64:1;
3049 } B;
3050 } AWORR2;
3051
3052 vuint8_t ADC1_reserved15[8]; /* Reserved 8 bytes (Base+0x02F8-0x02FF) */
3053
3054}; /* end of ADC1_tag */
3055
3056/****************************************************************************/
3057/* MODULE : LINFLEX - non DMA master only */
3058/****************************************************************************/
3059struct LINFLEX_tag {
3060
3061 union { /* LINFLEX LIN Control 1 (Base+0x0000) */
3062 vuint32_t R;
3063 struct {
3064 vuint32_t :16;
3065 vuint32_t CCD:1;
3066 vuint32_t CFD:1;
3067 vuint32_t LASE:1;
3068 vuint32_t AWUM:1;
3069 vuint32_t MBL:4;
3070 vuint32_t BF:1;
3071 vuint32_t SFTM:1;
3072 vuint32_t LBKM:1;
3073 vuint32_t MME:1;
3074 vuint32_t SBDT:1;
3075 vuint32_t RBLM:1;
3076 vuint32_t SLEEP:1;
3077 vuint32_t INIT:1;
3078 } B;
3079 } LINCR1;
3080
3081 union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
3082 vuint32_t R;
3083 struct {
3084 vuint32_t :16;
3085 vuint32_t SZIE:1;
3086 vuint32_t OCIE:1;
3087 vuint32_t BEIE:1;
3088 vuint32_t CEIE:1;
3089 vuint32_t HEIE:1;
3090 vuint32_t :2;
3091 vuint32_t FEIE:1;
3092 vuint32_t BOIE:1;
3093 vuint32_t LSIE:1;
3094 vuint32_t WUIE:1;
3095 vuint32_t DBFIE:1;
3096 vuint32_t DBEIE:1;
3097 vuint32_t DRIE:1;
3098 vuint32_t DTIE:1;
3099 vuint32_t HRIE:1;
3100 } B;
3101 } LINIER;
3102
3103 union { /* LINFLEX LIN Status (Base+0x0008) */
3104 vuint32_t R;
3105 struct {
3106 vuint32_t :16;
3107 vuint32_t LINS:4;
3108 vuint32_t:2;
3109 vuint32_t RMB:1;
3110 vuint32_t:1;
3111 vuint32_t RBSY:1;
3112 vuint32_t RPS:1;
3113 vuint32_t WUF:1;
3114 vuint32_t DBFF:1;
3115 vuint32_t DBEF:1;
3116 vuint32_t DRF:1;
3117 vuint32_t DTF:1;
3118 vuint32_t HRF:1;
3119 } B;
3120 } LINSR;
3121
3122 union { /* LINFLEX LIN Error Status (Base+0x000C) */
3123 vuint32_t R;
3124 struct {
3125 vuint32_t :16;
3126 vuint32_t SZF:1;
3127 vuint32_t OCF:1;
3128 vuint32_t BEF:1;
3129 vuint32_t CEF:1;
3130 vuint32_t SFEF:1;
3131 vuint32_t BDEF:1;
3132 vuint32_t IDPEF:1;
3133 vuint32_t FEF:1;
3134 vuint32_t BOF:1;
3135 vuint32_t:6;
3136 vuint32_t NF:1;
3137 } B;
3138 } LINESR;
3139
3140 union { /* LINFLEX UART Mode Control (Base+0x0010) */
3141 vuint32_t R;
3142 struct {
3143 vuint32_t :16;
3144 vuint32_t:1;
3145 vuint32_t TDFL:2;
3146 vuint32_t:1;
3147 vuint32_t RDFL:2;
3148 vuint32_t:4;
3149 vuint32_t RXEN:1;
3150 vuint32_t TXEN:1;
3151 vuint32_t OP:1;
3152 vuint32_t PCE:1;
3153 vuint32_t WL:1;
3154 vuint32_t UART:1;
3155 } B;
3156 } UARTCR;
3157
3158 union { /* LINFLEX UART Mode Status (Base+0x0014) */
3159 vuint32_t R;
3160 struct {
3161 vuint32_t :16;
3162 vuint32_t SZF:1;
3163 vuint32_t OCF:1;
3164 vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
3165 vuint32_t RMB:1;
3166 vuint32_t FEF:1;
3167 vuint32_t BOF:1;
3168 vuint32_t RPS:1;
3169 vuint32_t WUF:1;
3170 vuint32_t :1;
3171 vuint32_t TO:1;
3172 vuint32_t DRF:1;
3173 vuint32_t DTF:1;
3174 vuint32_t NF:1;
3175 } B;
3176 } UARTSR;
3177
3178 union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
3179 vuint32_t R;
3180 struct {
3181 vuint32_t :16;
3182 vuint32_t:5;
3183 vuint32_t LTOM:1;
3184 vuint32_t IOT:1;
3185 vuint32_t TOCE:1;
3186 vuint32_t CNT:8;
3187 } B;
3188 } LINTCSR;
3189
3190 union { /* LINFLEX LIN Output Compare (Base+0x001C) */
3191 vuint32_t R;
3192 struct {
3193 vuint32_t :16;
3194 vuint32_t OC2:8;
3195 vuint32_t OC1:8;
3196 } B;
3197 } LINOCR;
3198
3199 union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
3200 vuint32_t R;
3201 struct {
3202 vuint32_t :20;
3203 vuint32_t RTO:4;
3204 vuint32_t:1;
3205 vuint32_t HTO:7;
3206 } B;
3207 } LINTOCR;
3208
3209 union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
3210 vuint32_t R;
3211 struct {
3212 vuint32_t:28;
3213 vuint32_t DIV_F:4;
3214 } B;
3215 } LINFBRR;
3216
3217 union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
3218 vuint32_t R;
3219 struct {
3220 vuint32_t:12;
3221 vuint32_t DIV_M:20;
3222 } B;
3223 } LINIBRR;
3224
3225 union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
3226 vuint32_t R;
3227 struct {
3228 vuint32_t:24;
3229 vuint32_t CF:8;
3230 } B;
3231 } LINCFR;
3232
3233 union { /* LINFLEX LIN Control 2 (Base+0x0030) */
3234 vuint32_t R;
3235 struct {
3236 vuint32_t:17;
3237 vuint32_t IOBE:1;
3238 vuint32_t IOPE:1;
3239 vuint32_t WURQ:1;
3240 vuint32_t DDRQ:1;
3241 vuint32_t DTRQ:1;
3242 vuint32_t ABRQ:1;
3243 vuint32_t HTRQ:1;
3244 vuint32_t:8;
3245 } B;
3246 } LINCR2;
3247
3248 union { /* LINFLEX Buffer Identifier (Base+0x0034) */
3249 vuint32_t R;
3250 struct {
3251 vuint32_t:16;
3252 vuint32_t DFL:6;
3253 vuint32_t DIR:1;
3254 vuint32_t CCS:1;
3255 vuint32_t:2;
3256 vuint32_t ID:6;
3257 } B;
3258 } BIDR;
3259
3260 union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
3261 vuint32_t R;
3262 struct {
3263 vuint32_t DATA3:8;
3264 vuint32_t DATA2:8;
3265 vuint32_t DATA1:8;
3266 vuint32_t DATA0:8;
3267 } B;
3268 } BDRL;
3269
3270 union { /* LINFLEX Buffer Data MSB (Base+0x003C */
3271 vuint32_t R;
3272 struct {
3273 vuint32_t DATA7:8;
3274 vuint32_t DATA6:8;
3275 vuint32_t DATA5:8;
3276 vuint32_t DATA4:8;
3277 } B;
3278 } BDRM;
3279
3280 union { /* LINFLEX Identifier Filter Enable (+0x0040) */
3281 vuint32_t R;
3282 struct {
3283 vuint32_t:24;
3284 vuint32_t FACT:8;
3285 } B;
3286 } IFER;
3287
3288 union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
3289 vuint32_t R;
3290 struct {
3291 vuint32_t:28;
3292 vuint32_t IFMI:4;
3293 } B;
3294 } IFMI;
3295
3296 union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
3297 vuint32_t R;
3298 struct {
3299 vuint32_t:27;
3300 vuint32_t IFM:5;
3301 } B;
3302 } IFMR;
3303
3304 union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/
3305 vuint32_t R;
3306 struct {
3307 vuint32_t:16;
3308 vuint32_t:3; /* for LINflexD no reseve here*/
3309 vuint32_t DFL:3; /* Linflex D - this field is 6 bits (0 and 1), Linflex - this field is 3 bits (2-9 B1.5M) (2-7 B1M) */
3310 vuint32_t DIR:1;
3311 vuint32_t CCS:1;
3312 vuint32_t:2;
3313 vuint32_t ID:6;
3314 } B;
3315 } IFCR[16];
3316
3317
3318}; /* end of LINFLEX_tag */
3319
3320
3321/****************************************************************************/
3322/* MODULE : LINFLEXD0 Master/Slave DMA Enabled */
3323/****************************************************************************/
3324struct LINFLEXD0_tag {
3325
3326 union { /* LINFLEX LIN Control 1 (Base+0x0000) */
3327 vuint32_t R;
3328 struct {
3329 vuint32_t :16;
3330 vuint32_t CCD:1;
3331 vuint32_t CFD:1;
3332 vuint32_t LASE:1;
3333 vuint32_t AWUM:1;
3334 vuint32_t MBL:4;
3335 vuint32_t BF:1;
3336 vuint32_t SFTM:1;
3337 vuint32_t LBKM:1;
3338 vuint32_t MME:1;
3339 vuint32_t SBDT:1;
3340 vuint32_t RBLM:1;
3341 vuint32_t SLEEP:1;
3342 vuint32_t INIT:1;
3343 } B;
3344 } LINCR1;
3345
3346 union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
3347 vuint32_t R;
3348 struct {
3349 vuint32_t :16;
3350 vuint32_t SZIE:1;
3351 vuint32_t OCIE:1;
3352 vuint32_t BEIE:1;
3353 vuint32_t CEIE:1;
3354 vuint32_t HEIE:1;
3355 vuint32_t :2;
3356 vuint32_t FEIE:1;
3357 vuint32_t BOIE:1;
3358 vuint32_t LSIE:1;
3359 vuint32_t WUIE:1;
3360 vuint32_t DBFIE:1;
3361 vuint32_t DBEIE:1;
3362 vuint32_t DRIE:1;
3363 vuint32_t DTIE:1;
3364 vuint32_t HRIE:1;
3365 } B;
3366 } LINIER;
3367
3368 union { /* LINFLEX LIN Status (Base+0x0008) */
3369 vuint32_t R;
3370 struct {
3371 vuint32_t :16;
3372 vuint32_t LINS:4;
3373 vuint32_t:2;
3374 vuint32_t RMB:1;
3375 vuint32_t:1;
3376 vuint32_t RBSY:1;
3377 vuint32_t RPS:1;
3378 vuint32_t WUF:1;
3379 vuint32_t DBFF:1;
3380 vuint32_t DBEF:1;
3381 vuint32_t DRF:1;
3382 vuint32_t DTF:1;
3383 vuint32_t HRF:1;
3384 } B;
3385 } LINSR;
3386
3387 union { /* LINFLEX LIN Error Status (Base+0x000C) */
3388 vuint32_t R;
3389 struct {
3390 vuint32_t :16;
3391 vuint32_t SZF:1;
3392 vuint32_t OCF:1;
3393 vuint32_t BEF:1;
3394 vuint32_t CEF:1;
3395 vuint32_t SFEF:1;
3396 vuint32_t BDEF:1;
3397 vuint32_t IDPEF:1;
3398 vuint32_t FEF:1;
3399 vuint32_t BOF:1;
3400 vuint32_t:6;
3401 vuint32_t NF:1;
3402 } B;
3403 } LINESR;
3404
3405 union { /* LINFLEX UART Mode Control (Base+0x0010) */
3406 vuint32_t R;
3407 struct {
3408 vuint32_t :16;
3409 vuint32_t TDFLTFC:3;
3410 vuint32_t RDFLTFC:3;
3411 vuint32_t RFBM:1;
3412 vuint32_t TFBM:1;
3413 vuint32_t WL1:1;
3414 vuint32_t PC1:1;
3415 vuint32_t RXEN:1;
3416 vuint32_t TXEN:1;
3417 vuint32_t PC0:1;
3418 vuint32_t PCE:1;
3419 vuint32_t WL0:1;
3420 vuint32_t UART:1;
3421 } B;
3422 } UARTCR;
3423
3424 union { /* LINFLEX UART Mode Status (Base+0x0014) */
3425 vuint32_t R;
3426 struct {
3427 vuint32_t :16;
3428 vuint32_t SZF:1;
3429 vuint32_t OCF:1;
3430 vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
3431 vuint32_t RMB:1;
3432 vuint32_t FEF:1;
3433 vuint32_t BOF:1;
3434 vuint32_t RPS:1;
3435 vuint32_t WUF:1;
3436 vuint32_t :1;
3437 vuint32_t TO:1;
3438 vuint32_t DRF:1;
3439 vuint32_t DTF:1;
3440 vuint32_t NF:1;
3441 } B;
3442 } UARTSR;
3443
3444 union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
3445 vuint32_t R;
3446 struct {
3447 vuint32_t :16;
3448 vuint32_t:5;
3449 vuint32_t LTOM:1;
3450 vuint32_t IOT:1;
3451 vuint32_t TOCE:1;
3452 vuint32_t CNT:8;
3453 } B;
3454 } LINTCSR;
3455
3456 union { /* LINFLEX LIN Output Compare (Base+0x001C) */
3457 vuint32_t R;
3458 struct {
3459 vuint32_t :16;
3460 vuint32_t OC2:8;
3461 vuint32_t OC1:8;
3462 } B;
3463 } LINOCR;
3464
3465 union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
3466 vuint32_t R;
3467 struct {
3468 vuint32_t :20;
3469 vuint32_t RTO:4;
3470 vuint32_t:1;
3471 vuint32_t HTO:7;
3472 } B;
3473 } LINTOCR;
3474
3475 union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
3476 vuint32_t R;
3477 struct {
3478 vuint32_t:28;
3479 vuint32_t DIV_F:4;
3480 } B;
3481 } LINFBRR;
3482
3483 union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
3484 vuint32_t R;
3485 struct {
3486 vuint32_t:12;
3487 vuint32_t DIV_M:20;
3488 } B;
3489 } LINIBRR;
3490
3491 union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
3492 vuint32_t R;
3493 struct {
3494 vuint32_t:24;
3495 vuint32_t CF:8;
3496 } B;
3497 } LINCFR;
3498
3499 union { /* LINFLEX LIN Control 2 (Base+0x0030) */
3500 vuint32_t R;
3501 struct {
3502 vuint32_t:17;
3503 vuint32_t IOBE:1;
3504 vuint32_t IOPE:1;
3505 vuint32_t WURQ:1;
3506 vuint32_t DDRQ:1;
3507 vuint32_t DTRQ:1;
3508 vuint32_t ABRQ:1;
3509 vuint32_t HTRQ:1;
3510 vuint32_t:8;
3511 } B;
3512 } LINCR2;
3513
3514 union { /* LINFLEX Buffer Identifier (Base+0x0034) */
3515 vuint32_t R;
3516 struct {
3517 vuint32_t:16;
3518 vuint32_t DFL:6;
3519 vuint32_t DIR:1;
3520 vuint32_t CCS:1;
3521 vuint32_t:2;
3522 vuint32_t ID:6;
3523 } B;
3524 } BIDR;
3525
3526 union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
3527 vuint32_t R;
3528 struct {
3529 vuint32_t DATA3:8;
3530 vuint32_t DATA2:8;
3531 vuint32_t DATA1:8;
3532 vuint32_t DATA0:8;
3533 } B;
3534 } BDRL;
3535
3536 union { /* LINFLEX Buffer Data MSB (Base+0x003C */
3537 vuint32_t R;
3538 struct {
3539 vuint32_t DATA7:8;
3540 vuint32_t DATA6:8;
3541 vuint32_t DATA5:8;
3542 vuint32_t DATA4:8;
3543 } B;
3544 } BDRM;
3545
3546 union { /* LINFLEX Identifier Filter Enable (+0x0040) */
3547 vuint32_t R;
3548 struct {
3549 vuint32_t:24;
3550 vuint32_t FACT:8;
3551 } B;
3552 } IFER;
3553
3554 union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
3555 vuint32_t R;
3556 struct {
3557 vuint32_t:27;
3558 vuint32_t IFMI:5;
3559 } B;
3560 } IFMI;
3561
3562 union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
3563 vuint32_t R;
3564 struct {
3565 vuint32_t:24;
3566 vuint32_t IFM:8;
3567 } B;
3568 } IFMR;
3569
3570 union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/
3571 vuint32_t R;
3572 struct {
3573 vuint32_t:16;
3574 vuint32_t DFL:6;
3575 vuint32_t DIR:1;
3576 vuint32_t CCS:1;
3577 vuint32_t:2;
3578 vuint32_t ID:6;
3579 } B;
3580 } IFCR[16];
3581
3582 union { /* LINFLEX Global Counter (+0x008C) */
3583 vuint32_t R;
3584 struct {
3585 vuint32_t:26;
3586 vuint32_t TDFBM:1;
3587 vuint32_t RDFBM:1;
3588 vuint32_t TDLIS:1;
3589 vuint32_t RDLIS:1;
3590 vuint32_t STOP:1;
3591 vuint32_t SR:1;
3592 } B;
3593 } GCR;
3594
3595 union { /* LINFLEX UART preset timeout (+0x0090) */
3596 vuint32_t R;
3597 struct {
3598 vuint32_t:20;
3599 vuint32_t PTO:12;
3600 } B;
3601 } UARTPTO;
3602
3603 union { /* LINFLEX UART current timeout (+0x0094) */
3604 vuint32_t R;
3605 struct {
3606 vuint32_t:20;
3607 vuint32_t CTO:12;
3608 } B;
3609 } UARTCTO;
3610
3611 union { /* LINFLEX DMA Tx Enable (+0x0098) */
3612 vuint32_t R;
3613 struct {
3614 vuint32_t:16;
3615 vuint32_t DTE15:1;
3616 vuint32_t DTE14:1;
3617 vuint32_t DTE13:1;
3618 vuint32_t DTE12:1;
3619 vuint32_t DTE11:1;
3620 vuint32_t DTE10:1;
3621 vuint32_t DTE9:1;
3622 vuint32_t DTE8:1;
3623 vuint32_t DTE7:1;
3624 vuint32_t DTE6:1;
3625 vuint32_t DTE5:1;
3626 vuint32_t DTE4:1;
3627 vuint32_t DTE3:1;
3628 vuint32_t DTE2:1;
3629 vuint32_t DTE1:1;
3630 vuint32_t DTE0:1;
3631 } B;
3632 } DMATXE;
3633
3634 union { /* LINFLEX DMA RX Enable (+0x009C) */
3635 vuint32_t R;
3636 struct {
3637 vuint32_t:16;
3638 vuint32_t DRE15:1;
3639 vuint32_t DRE14:1;
3640 vuint32_t DRE13:1;
3641 vuint32_t DRE12:1;
3642 vuint32_t DRE11:1;
3643 vuint32_t DRE10:1;
3644 vuint32_t DRE9:1;
3645 vuint32_t DRE8:1;
3646 vuint32_t DRE7:1;
3647 vuint32_t DRE6:1;
3648 vuint32_t DRE5:1;
3649 vuint32_t DRE4:1;
3650 vuint32_t DRE3:1;
3651 vuint32_t DRE2:1;
3652 vuint32_t DRE1:1;
3653 vuint32_t DRE0:1;
3654 } B;
3655 } DMARXE;
3656}; /* end of LINFLEXD0_tag */
3657/****************************************************************************/
3658/* MODULE : LINFLEXD1 Master only DMA enable */
3659/****************************************************************************/
3660struct LINFLEXD1_tag {
3661
3662 union { /* LINFLEX LIN Control 1 (Base+0x0000) */
3663 vuint32_t R;
3664 struct {
3665 vuint32_t :16;
3666 vuint32_t CCD:1;
3667 vuint32_t CFD:1;
3668 vuint32_t LASE:1;
3669 vuint32_t AWUM:1;
3670 vuint32_t MBL:4;
3671 vuint32_t BF:1;
3672 vuint32_t SFTM:1;
3673 vuint32_t LBKM:1;
3674 vuint32_t MME:1;
3675 vuint32_t SBDT:1;
3676 vuint32_t RBLM:1;
3677 vuint32_t SLEEP:1;
3678 vuint32_t INIT:1;
3679 } B;
3680 } LINCR1;
3681
3682 union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
3683 vuint32_t R;
3684 struct {
3685 vuint32_t :16;
3686 vuint32_t SZIE:1;
3687 vuint32_t OCIE:1;
3688 vuint32_t BEIE:1;
3689 vuint32_t CEIE:1;
3690 vuint32_t HEIE:1;
3691 vuint32_t :2;
3692 vuint32_t FEIE:1;
3693 vuint32_t BOIE:1;
3694 vuint32_t LSIE:1;
3695 vuint32_t WUIE:1;
3696 vuint32_t DBFIE:1;
3697 vuint32_t DBEIE:1;
3698 vuint32_t DRIE:1;
3699 vuint32_t DTIE:1;
3700 vuint32_t HRIE:1;
3701 } B;
3702 } LINIER;
3703
3704 union { /* LINFLEX LIN Status (Base+0x0008) */
3705 vuint32_t R;
3706 struct {
3707 vuint32_t :16;
3708 vuint32_t LINS:4;
3709 vuint32_t:2;
3710 vuint32_t RMB:1;
3711 vuint32_t:1;
3712 vuint32_t RBSY:1;
3713 vuint32_t RPS:1;
3714 vuint32_t WUF:1;
3715 vuint32_t DBFF:1;
3716 vuint32_t DBEF:1;
3717 vuint32_t DRF:1;
3718 vuint32_t DTF:1;
3719 vuint32_t HRF:1;
3720 } B;
3721 } LINSR;
3722
3723 union { /* LINFLEX LIN Error Status (Base+0x000C) */
3724 vuint32_t R;
3725 struct {
3726 vuint32_t :16;
3727 vuint32_t SZF:1;
3728 vuint32_t OCF:1;
3729 vuint32_t BEF:1;
3730 vuint32_t CEF:1;
3731 vuint32_t SFEF:1;
3732 vuint32_t BDEF:1;
3733 vuint32_t IDPEF:1;
3734 vuint32_t FEF:1;
3735 vuint32_t BOF:1;
3736 vuint32_t:6;
3737 vuint32_t NF:1;
3738 } B;
3739 } LINESR;
3740
3741 union { /* LINFLEX UART Mode Control (Base+0x0010) */
3742 vuint32_t R;
3743 struct {
3744 vuint32_t :16;
3745 vuint32_t TDFLTFC:3;
3746 vuint32_t RDFLTFC:3;
3747 vuint32_t RFBM:1;
3748 vuint32_t TFBM:1;
3749 vuint32_t WL1:1;
3750 vuint32_t PC1:1;
3751 vuint32_t RXEN:1;
3752 vuint32_t TXEN:1;
3753 vuint32_t PC0:1;
3754 vuint32_t PCE:1;
3755 vuint32_t WL0:1;
3756 vuint32_t UART:1;
3757 } B;
3758 } UARTCR;
3759
3760 union { /* LINFLEX UART Mode Status (Base+0x0014) */
3761 vuint32_t R;
3762 struct {
3763 vuint32_t :16;
3764 vuint32_t SZF:1;
3765 vuint32_t OCF:1;
3766 vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
3767 vuint32_t RMB:1;
3768 vuint32_t FEF:1;
3769 vuint32_t BOF:1;
3770 vuint32_t RPS:1;
3771 vuint32_t WUF:1;
3772 vuint32_t:2;
3773 vuint32_t DRF:1;
3774 vuint32_t DTF:1;
3775 vuint32_t NF:1;
3776 } B;
3777 } UARTSR;
3778
3779 union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
3780 vuint32_t R;
3781 struct {
3782 vuint32_t :16;
3783 vuint32_t:5;
3784 vuint32_t LTOM:1;
3785 vuint32_t IOT:1;
3786 vuint32_t TOCE:1;
3787 vuint32_t CNT:8;
3788 } B;
3789 } LINTCSR;
3790
3791 union { /* LINFLEX LIN Output Compare (Base+0x001C) */
3792 vuint32_t R;
3793 struct {
3794 vuint32_t :16;
3795 vuint32_t OC2:8;
3796 vuint32_t OC1:8;
3797 } B;
3798 } LINOCR;
3799
3800 union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
3801 vuint32_t R;
3802 struct {
3803 vuint32_t :20;
3804 vuint32_t RTO:4;
3805 vuint32_t:1;
3806 vuint32_t HTO:7;
3807 } B;
3808 } LINTOCR;
3809
3810 union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
3811 vuint32_t R;
3812 struct {
3813 vuint32_t:28;
3814 vuint32_t DIV_F:4;
3815 } B;
3816 } LINFBRR;
3817
3818 union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
3819 vuint32_t R;
3820 struct {
3821 vuint32_t:12;
3822 vuint32_t DIV_M:20;
3823 } B;
3824 } LINIBRR;
3825
3826 union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
3827 vuint32_t R;
3828 struct {
3829 vuint32_t:24;
3830 vuint32_t CF:8;
3831 } B;
3832 } LINCFR;
3833
3834 union { /* LINFLEX LIN Control 2 (Base+0x0030) */
3835 vuint32_t R;
3836 struct {
3837 vuint32_t:17;
3838 vuint32_t IOBE:1;
3839 vuint32_t IOPE:1;
3840 vuint32_t WURQ:1;
3841 vuint32_t DDRQ:1;
3842 vuint32_t DTRQ:1;
3843 vuint32_t ABRQ:1;
3844 vuint32_t HTRQ:1;
3845 vuint32_t:8;
3846 } B;
3847 } LINCR2;
3848
3849 union { /* LINFLEX Buffer Identifier (Base+0x0034) */
3850 vuint32_t R;
3851 struct {
3852 vuint32_t:16;
3853 vuint32_t DFL:6;
3854 vuint32_t DIR:1;
3855 vuint32_t CCS:1;
3856 vuint32_t:2;
3857 vuint32_t ID:6;
3858 } B;
3859 } BIDR;
3860
3861 union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
3862 vuint32_t R;
3863 struct {
3864 vuint32_t DATA3:8;
3865 vuint32_t DATA2:8;
3866 vuint32_t DATA1:8;
3867 vuint32_t DATA0:8;
3868 } B;
3869 } BDRL;
3870
3871 union { /* LINFLEX Buffer Data MSB (Base+0x003C */
3872 vuint32_t R;
3873 struct {
3874 vuint32_t DATA7:8;
3875 vuint32_t DATA6:8;
3876 vuint32_t DATA5:8;
3877 vuint32_t DATA4:8;
3878 } B;
3879 } BDRM;
3880
3881 union { /* LINFLEX Identifier Filter Enable (+0x0040) */
3882 vuint32_t R;
3883 struct {
3884 vuint32_t:24;
3885 vuint32_t FACT:8;
3886 } B;
3887 } IFER;
3888
3889 union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
3890 vuint32_t R;
3891 struct {
3892 vuint32_t:27;
3893 vuint32_t IFMI:5;
3894 } B;
3895 } IFMI;
3896
3897 union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
3898 vuint32_t R;
3899 struct {
3900 vuint32_t:24;
3901 vuint32_t IFM:8;
3902 } B;
3903 } IFMR;
3904
3905/* No IFCR registers on LinFlexD_1 */
3906
3907 union { /* LINFLEX Global Counter (+0x004C) */
3908 vuint32_t R;
3909 struct {
3910 vuint32_t:26;
3911 vuint32_t TDFBM:1;
3912 vuint32_t RDFBM:1;
3913 vuint32_t TDLIS:1;
3914 vuint32_t RDLIS:1;
3915 vuint32_t STOP:1;
3916 vuint32_t SR:1;
3917 } B;
3918 } GCR;
3919
3920 union { /* LINFLEX UART preset timeout (+0x0050) */
3921 vuint32_t R;
3922 struct {
3923 vuint32_t:20;
3924 vuint32_t PTO:12;
3925 } B;
3926 } UARTPTO;
3927
3928 union { /* LINFLEX UART current timeout (+0x0054) */
3929 vuint32_t R;
3930 struct {
3931 vuint32_t:20;
3932 vuint32_t CTO:12;
3933 } B;
3934 } UARTCTO;
3935
3936 union { /* LINFLEX DMA Tx Enable (+0x0058) */
3937 vuint32_t R;
3938 struct {
3939 vuint32_t:16;
3940 vuint32_t DTE15:1;
3941 vuint32_t DTE14:1;
3942 vuint32_t DTE13:1;
3943 vuint32_t DTE12:1;
3944 vuint32_t DTE11:1;
3945 vuint32_t DTE10:1;
3946 vuint32_t DTE9:1;
3947 vuint32_t DTE8:1;
3948 vuint32_t DTE7:1;
3949 vuint32_t DTE6:1;
3950 vuint32_t DTE5:1;
3951 vuint32_t DTE4:1;
3952 vuint32_t DTE3:1;
3953 vuint32_t DTE2:1;
3954 vuint32_t DTE1:1;
3955 vuint32_t DTE0:1;
3956 } B;
3957 } DMATXE;
3958
3959 union { /* LINFLEX DMA RX Enable (+0x005C) */
3960 vuint32_t R;
3961 struct {
3962 vuint32_t:16;
3963 vuint32_t DRE15:1;
3964 vuint32_t DRE14:1;
3965 vuint32_t DRE13:1;
3966 vuint32_t DRE12:1;
3967 vuint32_t DRE11:1;
3968 vuint32_t DRE10:1;
3969 vuint32_t DRE9:1;
3970 vuint32_t DRE8:1;
3971 vuint32_t DRE7:1;
3972 vuint32_t DRE6:1;
3973 vuint32_t DRE5:1;
3974 vuint32_t DRE4:1;
3975 vuint32_t DRE3:1;
3976 vuint32_t DRE2:1;
3977 vuint32_t DRE1:1;
3978 vuint32_t DRE0:1;
3979 } B;
3980 } DMARXE;
3981}; /* end of LINFLEXD1_tag */
3982 /****************************************************************************/
3983/* MODULE : CTU Lite(base address - 0xFFE6_4000) */
3984/****************************************************************************/
3985struct CTU_tag{
3986
3987 vuint8_t CTU_reserved[48]; /* Reserved 48 bytes (Base+0x0000-0x002F) */
3988
3989 union { /* Event Config 0..63 (Base+0x0030-0x012C) */
3990 vuint32_t R;
3991 struct {
3992 vuint32_t :16;
3993 vuint32_t TM:1;
3994 vuint32_t CLR_FLAG:1;
3995 vuint32_t :5;
3996 vuint32_t ADC_SEL:1;
3997 vuint32_t :1;
3998 vuint32_t CHANNEL_VALUE:7;
3999 } B;
4000 } EVTCFGR[64];
4001
4002
4003}; /* end of CTU_tag */
4004
4005
4006/****************************************************************************/
4007/* MODULE : MPU (base address - 0xFFF1_0000) */
4008/****************************************************************************/
4009 struct MPU_tag {
4010
4011 union { /* Control/Error Status (Base+0x0000) */
4012 vuint32_t R;
4013 struct {
4014 vuint32_t SPERR:3;
4015 vuint32_t:9;
4016 vuint32_t HRL:4;
4017 vuint32_t NSP:4;
4018 vuint32_t NGRD:4;
4019 vuint32_t :7;
4020 vuint32_t VLD:1;
4021 } B;
4022 } CESR;
4023
4024 vuint8_t MPU_reserved0[12]; /* Reserved 12 Bytes (Base+0x0004-0x000F) */
4025
4026
4027 union { /* Error Address Slave Port0 (Base+0x0010) */
4028 vuint32_t R;
4029 struct {
4030 vuint32_t EADDR:32;
4031 } B;
4032 } EAR0;
4033
4034 union { /* Error Detail Slave Port0 (Base+0x0014) */
4035 vuint32_t R;
4036 struct {
4037 vuint32_t EACD:8;
4038 vuint32_t:8;
4039 vuint32_t EPID:8;
4040 vuint32_t EMN:4;
4041 vuint32_t EATTR:3;
4042 vuint32_t ERW:1;
4043 } B;
4044 } EDR0;
4045
4046
4047 union { /* Error Address Slave Port1 (Base+0x0018) */
4048 vuint32_t R;
4049 struct {
4050 vuint32_t EADDR:32;
4051 } B;
4052 } EAR1;
4053
4054 union { /* Error Detail Slave Port1 (Base+0x001C) */
4055 vuint32_t R;
4056 struct {
4057 vuint32_t EACD:8;
4058 vuint32_t:8;
4059 vuint32_t EPID:8;
4060 vuint32_t EMN:4;
4061 vuint32_t EATTR:3;
4062 vuint32_t ERW:1;
4063 } B;
4064 } EDR1;
4065
4066
4067 union { /* Error Address Slave Port2 (Base+0x0020) */
4068 vuint32_t R;
4069 struct {
4070 vuint32_t EADDR:32;
4071 } B;
4072 } EAR2;
4073
4074 union { /* Error Detail Slave Port2 (Base+0x0024) */
4075 vuint32_t R;
4076 struct {
4077 vuint32_t EACD:8;
4078 vuint32_t:8;
4079 vuint32_t EPID:8;
4080 vuint32_t EMN:4;
4081 vuint32_t EATTR:3;
4082 vuint32_t ERW:1;
4083 } B;
4084 } EDR2;
4085
4086 vuint8_t MPU_reserved1[984]; /* Reserved 984 Bytes (Base+0x0028-0x03FF) */
4087
4088 struct { /* Region Descriptor 0..15 (Base+0x0400-0x0470) */
4089
4090 union { /* - Word 0 */
4091 vuint32_t R;
4092 struct {
4093 vuint32_t SRTADDR:27;
4094 vuint32_t :5;
4095 } B;
4096 } WORD0;
4097
4098 union { /* - Word 1 */
4099 vuint32_t R;
4100 struct {
4101 vuint32_t ENDADDR:27;
4102 vuint32_t :5;
4103 } B;
4104 } WORD1;
4105
4106 union { /* - Word 2 */
4107 vuint32_t R;
4108 struct {
4109 vuint32_t M7RE:1;
4110 vuint32_t M7WE:1;
4111 vuint32_t M6RE:1;
4112 vuint32_t M6WE:1;
4113 vuint32_t M5RE:1;
4114 vuint32_t M5WE:1;
4115 vuint32_t M4RE:1;
4116 vuint32_t M4WE:1;
4117 vuint32_t M3PE:1;
4118 vuint32_t M3SM:2;
4119 vuint32_t M3UM:3;
4120 vuint32_t M2PE:1;
4121 vuint32_t M2SM:2;
4122 vuint32_t M2UM:2;
4123 vuint32_t :7;
4124 vuint32_t M0PE:1;
4125 vuint32_t M0SM:2;
4126 vuint32_t M0UM:3;
4127 } B;
4128 } WORD2;
4129
4130 union { /* - Word 3 */
4131 vuint32_t R;
4132 struct {
4133 vuint32_t PID:8;
4134 vuint32_t PIDMASK:8;
4135 vuint32_t :15;
4136 vuint32_t VLD:1;
4137 } B;
4138 } WORD3;
4139
4140 }RGD[8]; /* End of Region Descriptor Structure) */
4141
4142 vuint8_t MPU_reserved2[896]; /* Reserved 896 Bytes (Base+0x0480-0x07FF) */
4143
4144 union { /* Region Descriptor Alt 0..15 (0x0800-0x081C) */
4145 vuint32_t R;
4146 struct {
4147 vuint32_t M7RE:1;
4148 vuint32_t M7WE:1;
4149 vuint32_t M6RE:1;
4150 vuint32_t M6WE:1;
4151 vuint32_t M5RE:1;
4152 vuint32_t M5WE:1;
4153 vuint32_t M4RE:1;
4154 vuint32_t M4WE:1;
4155 vuint32_t M3PE:1;
4156 vuint32_t M3SM:2;
4157 vuint32_t M3UM:3;
4158 vuint32_t M2PE:1;
4159 vuint32_t M2SM:2;
4160 vuint32_t M2UM:2;
4161 vuint32_t :7;
4162 vuint32_t M0PE:1;
4163 vuint32_t M0SM:2;
4164 vuint32_t M0UM:3;
4165 } B;
4166 } RGDAAC[8];
4167
4168 vuint8_t MPU_reserved3[14304]; /* Reserved 14304 Bytes (+0x0820-0x03FFF) */
4169
4170}; /* end of MPU_tag */
4171
4172/****************************************************************************/
4173/* MODULE : SWT */
4174/****************************************************************************/
4175struct SWT_tag{
4176
4177 union { /* SWT Control (Base+0x0000) */
4178 vuint32_t R;
4179 struct {
4180 vuint32_t MAP0:1;
4181 vuint32_t MAP1:1;
4182 vuint32_t MAP2:1;
4183 vuint32_t MAP3:1;
4184 vuint32_t MAP4:1;
4185 vuint32_t MAP5:1;
4186 vuint32_t MAP6:1;
4187 vuint32_t MAP7:1;
4188 vuint32_t :14;
4189 vuint32_t KEY:1;
4190 vuint32_t RIA:1;
4191 vuint32_t WND:1;
4192 vuint32_t ITR:1;
4193 vuint32_t HLK:1;
4194 vuint32_t SLK:1;
4195 vuint32_t CSL:1;
4196 vuint32_t STP:1;
4197 vuint32_t FRZ:1;
4198 vuint32_t WEN:1;
4199 } B;
4200 } CR;
4201
4202 union { /* SWT Interrupt (Base+0x0004) */
4203 vuint32_t R;
4204 struct {
4205 vuint32_t :31;
4206 vuint32_t TIF:1;
4207 } B;
4208 } IR;
4209
4210 union { /* SWT Time-Out (Base+0x0008) */
4211 vuint32_t R;
4212 struct {
4213 vuint32_t WTO:32;
4214 } B;
4215 } TO;
4216
4217 union { /* SWT Window (Base+0x000C) */
4218 vuint32_t R;
4219 struct {
4220 vuint32_t WST:32;
4221 } B;
4222 } WN;
4223
4224 union { /* SWT Service (Base+0x0010) */
4225 vuint32_t R;
4226 struct {
4227 vuint32_t :16;
4228 vuint32_t WSC:16;
4229 } B;
4230 } SR;
4231
4232 union { /* SWT Counter Output (Base+0x0014) */
4233 vuint32_t R;
4234 struct {
4235 vuint32_t CNT:32;
4236 } B;
4237 } CO;
4238
4239}; /* end of SWT_tag */
4240
4241/****************************************************************************/
4242/* MODULE : STM */
4243/****************************************************************************/
4244 struct STM_CHANNEL_tag{
4245
4246 union { /* STM Channel Control 0..3 */
4247 vuint32_t R;
4248 struct {
4249 vuint32_t :31;
4250 vuint32_t CEN:1;
4251 } B;
4252 } CCR;
4253
4254 union { /* STM Channel Interrupt 0..3 */
4255 vuint32_t R;
4256 struct {
4257 vuint32_t :31;
4258 vuint32_t CIF:1;
4259 } B;
4260 } CIR;
4261
4262 union { /* STM Channel Compare 0..3 */
4263 vuint32_t R;
4264 struct {
4265 vuint32_t CMP:32;
4266 } B;
4267 } CMP;
4268
4269 vuint8_t STM_CHANNEL_reserved0[4]; /* Reserved 4 bytes between ch reg's */
4270
4271 }; /* end of STM_CHANNEL_tag */
4272
4273
4274struct STM_tag{
4275
4276 union { /* STM Control (Base+0x0000) */
4277 vuint32_t R;
4278 struct {
4279 vuint32_t :16;
4280 vuint32_t CPS:8;
4281 vuint32_t :6;
4282 vuint32_t FRZ:1;
4283 vuint32_t TEN:1;
4284 } B;
4285 } CR;
4286
4287 union { /* STM Count (Base+0x0004) */
4288 vuint32_t R;
4289 } CNT;
4290
4291 vuint8_t STM_reserved1[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
4292
4293 struct STM_CHANNEL_tag CH[4]; /*STM Channels 0..3 (Base+0x0010-0x0048) */
4294
4295}; /* end of STM_tag */
4296
4297/****************************************************************************/
4298/* MODULE : ECSM */
4299/****************************************************************************/
4300struct ECSM_tag{
4301
4302 union { /* ECSM Processor Core Type (Base+0x0000) */
4303 vuint16_t R;
4304 } PCT;
4305
4306 union { /* ECSM Revision (Base+0x0002) */
4307 vuint16_t R;
4308 } REV;
4309
4310 vuint8_t ECSM_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */
4311
4312 union { /* ECSM IPS Module Configuration (Base+0x0008) */
4313 vuint32_t R;
4314 } IMC;
4315
4316 vuint8_t ECSM_reserved1[7]; /* Reserved 7 bytes (Base+0x000C-0x0012) */
4317
4318 union { /* ECSM Miscellaneous Wakeup Control (+0x0013) */
4319 vuint8_t R;
4320 struct {
4321 vuint8_t ENBWCR:1;
4322 vuint8_t :3;
4323 vuint8_t PRILVL:4;
4324 } B;
4325 } MWCR;
4326
4327 vuint8_t ECSM_reserved2[11]; /* Reserved 11 bytes (Base+0x0014-0x001E) */
4328
4329 union { /* ECSM Miscellaneous Interrupt (Base+0x001F) */
4330 vuint8_t R;
4331 struct {
4332 vuint8_t FB0AI:1;
4333 vuint8_t FB0SI:1;
4334 vuint8_t FB1AI:1;
4335 vuint8_t FB1SI:1;
4336 vuint8_t :4;
4337 } B;
4338 } MIR;
4339
4340 vuint8_t ECSM_reserved3[4]; /* Reserved 4 bytes (Base+0x0020-0x0023) */
4341
4342 union { /*ECSM Miscellaneous User-Defined Control (+0x0024)*/
4343 vuint32_t R;
4344 } MUDCR; /* ECSM Miscellaneous User-Defined Control Register */
4345
4346 vuint8_t ECSM_reserved4[27]; /* Reserved 27 bytes (Base+0x0028-0x0042) */
4347
4348 union { /* ECSM ECC Configuration (Base+0x0043) */
4349 vuint8_t R;
4350 struct {
4351 vuint8_t :2;
4352 vuint8_t ER1BR:1;
4353 vuint8_t EF1BR:1;
4354 vuint8_t :2;
4355 vuint8_t ERNCR:1;
4356 vuint8_t EFNCR:1;
4357 } B;
4358 } ECR;
4359
4360 vuint8_t ECSM_reserved5[3]; /* Reserved 3 bytes (Base+0x0044-0x0046) */
4361
4362 union { /* ECSM ECC Status (Base+0x0047) */
4363 vuint8_t R;
4364 struct {
4365 vuint8_t :2;
4366 vuint8_t R1BC:1;
4367 vuint8_t F1BC:1;
4368 vuint8_t :2;
4369 vuint8_t RNCE:1;
4370 vuint8_t FNCE:1;
4371 } B;
4372 } ESR;
4373
4374 vuint8_t ECSM_reserved6[2]; /* Reserved 2 bytes (Base+0x0048-0x0049) */
4375
4376 union { /* ECSM ECC Error Generation (Base+0x004A) */
4377 vuint16_t R;
4378 struct {
4379 vuint16_t :2;
4380 vuint16_t FRC1BI:1;
4381 vuint16_t FR11BI:1;
4382 vuint16_t :2;
4383 vuint16_t FRCNCI:1;
4384 vuint16_t FR1NCI:1;
4385 vuint16_t :1;
4386 vuint16_t ERRBIT:7;
4387 } B;
4388 } EEGR;
4389
4390 vuint8_t ECSM_reserved7[4]; /* Reserved 4 bytes (Base+0x004C-0x004F) */
4391
4392 union { /* ECSM Flash ECC Address(Base+0x0050) */
4393 vuint32_t R;
4394 } FEAR;
4395
4396 vuint8_t ECSM_reserved8[2]; /* Reserved 2 bytes (Base+0x0054-0x0055) */
4397
4398 union { /* ECSM Flash ECC Master Number (Base+0x0056) */
4399 vuint8_t R;
4400 struct {
4401 vuint8_t :4;
4402 vuint8_t FEMR:4;
4403 } B;
4404 } FEMR;
4405
4406 union { /* ECSM Flash ECC Attributes (Base+0x0057) */
4407 vuint8_t R;
4408 struct {
4409 vuint8_t WRITE:1;
4410 vuint8_t SIZE:3;
4411 vuint8_t PROTECTION:4;
4412 } B;
4413 } FEAT;
4414
4415 vuint8_t ECSM_reserved9[4]; /* Reserved 4 bytes (Base+0x0058-0x005B) */
4416
4417 union { /* ECSM Flash ECC Data (Base+0x005C) */
4418 vuint32_t R;
4419 } FEDR;
4420
4421 union { /* ECSM RAM ECC Address (Base+0x0060) */
4422 vuint32_t R;
4423 } REAR;
4424
4425 vuint8_t ECSM_reserved10[1]; /* Reserved 1 bytes (Base+0x0064) */
4426
4427 union { /* ECSM RAM ECC Address (Base+0x0065) */
4428 vuint8_t R;
4429 } RESR;
4430
4431 union { /* ECSM RAM ECC Master Number (Base+0x0066) */
4432 vuint8_t R;
4433 struct {
4434 vuint8_t :4;
4435 vuint8_t REMR:4;
4436 } B;
4437 } REMR;
4438
4439 union { /* ECSM RAM ECC Attributes (Base+0x0067) */
4440 vuint8_t R;
4441 struct {
4442 vuint8_t WRITE:1;
4443 vuint8_t SIZE:3;
4444 vuint8_t PROTECTION:4;
4445 } B;
4446 } REAT;
4447
4448 vuint8_t ECSM_reserved11[4]; /* Reserved 4 bytes (Base+0x0068-0x006B) */
4449
4450 union { /* ECSM RAM ECC Data (Base+0x006C) */
4451 vuint32_t R;
4452 } REDR;
4453
4454}; /* end of ECSM_tag */
4455
4456/****************************************************************************/
4457/* MODULE : eDMA (base address - 0xFFF4_4000) */
4458/****************************************************************************/
4459
4460 /* There are 4 different TCD structures which should be used based on */
4461 /* how the DMA is configured as below. CAUTION - Do not mix TCD's */
4462 /* */
4463 /* Channel Linking Minor Loop Mapping Addressing TCD */
4464 /* OFF OFF XBAR.TCD[x] */
4465 /* OFF ON XBAR.ML_TCD[x] */
4466 /* ON OFF XBAR.CL_TCD[X] */
4467 /* ON ON XBAR.MLCL_TCD[X] */
4468 /* */
4469
4470 /*for "standard" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=0) */
4471 /* (1) - Standard TCD (Channel Linking OFF, Minor Loop mapping OFF */
4472 struct EDMA_TCD_STD_tag {
4473
4474 vuint32_t SADDR; /* Source address */
4475
4476 vuint16_t SMOD:5; /* Source address modulo */
4477 vuint16_t SSIZE:3; /* Source data transfer size */
4478 vuint16_t DMOD:5; /* Destination address modulo */
4479 vuint16_t DSIZE:3; /* Destination data transfer size */
4480 vint16_t SOFF; /* Source address signed offset */
4481
4482 vuint32_t NBYTES; /* Inner "minor" byte transfer count */
4483
4484 vint32_t SLAST; /* Last source address adjustment */
4485
4486 vuint32_t DADDR; /* Destination address */
4487
4488 vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
4489 vuint16_t CITER:15; /* Current Major iteration count */
4490 vint16_t DOFF; /* Destination address signed offset */
4491
4492 vint32_t DLAST_SGA; /* Last desitination address adjustment */
4493
4494 vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
4495 vuint16_t BITER:15; /* Starting major iteration count */
4496 vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
4497 vuint16_t MAJORLINKCH:6; /* Link channel number */
4498 vuint16_t DONE:1; /* Channel done */
4499 vuint16_t ACTIVE:1; /* Channel active */
4500 vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
4501 vuint16_t E_SG:1; /* Enable scatter/gather processing */
4502 vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
4503 vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
4504 vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
4505 vuint16_t START:1; /* Chanel start */
4506
4507 }; /* End of Standard TCD tag */
4508
4509
4510 /* (2) - ML_TCD (Channel Linking OFF, Minor Loop mapping Enabled */
4511 /* (EMLM = 1) */
4512 struct EDMA_TCD_MLMIRROR_tag {
4513
4514 vuint32_t SADDR; /* Source address */
4515
4516 vuint16_t SMOD:5; /* Source address modulo */
4517 vuint16_t SSIZE:3; /* Source data transfer size */
4518 vuint16_t DMOD:5; /* Destination address modulo */
4519 vuint16_t DSIZE:3; /* Destination data transfer size */
4520 vint16_t SOFF; /* Source address signed offset */
4521
4522 vuint32_t SMLOE:1; /* Source minor loop offset enabled */
4523 vuint32_t DMLOE:1; /* Destination minor loop offset enable */
4524 vuint32_t MLOFF:20; /* Minor loop offset */
4525 vuint32_t NBYTES:10; /* Inner "minor" byte transfer count */
4526
4527 vint32_t SLAST; /* Last source address adjustment */
4528
4529 vuint32_t DADDR; /* Destination address */
4530
4531 vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
4532 vuint16_t CITER:15; /* Current Major iteration count */
4533 vint16_t DOFF; /* Destination address signed offset */
4534
4535 vint32_t DLAST_SGA; /* Last desitination address adjustment */
4536
4537 vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
4538 vuint16_t BITER:15; /* Starting major iteration count */
4539 vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
4540 vuint16_t MAJORLINKCH:6; /* Link channel number */
4541 vuint16_t DONE:1; /* Channel done */
4542 vuint16_t ACTIVE:1; /* Channel active */
4543 vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
4544 vuint16_t E_SG:1; /* Enable scatter/gather processing */
4545 vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
4546 vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
4547 vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
4548 vuint16_t START:1; /* Chanel start */
4549
4550 }; /* End of EDMA_TCD_MLMIRROR_tag */
4551
4552 /*for "channel link" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=1)*/
4553 /* (3) - CL_TCD (Channel Linking Enabled, Minor Loop mapping OFF */
4554 /* (CITERE_LINK = BITERE_LINK = 1) */
4555 struct EDMA_TCD_CHLINK_tag {
4556
4557 vuint32_t SADDR; /* Source address */
4558
4559 vuint16_t SMOD:5; /* Source address modulo */
4560 vuint16_t SSIZE:3; /* Source data transfer size */
4561 vuint16_t DMOD:5; /* Destination address modulo */
4562 vuint16_t DSIZE:3; /* Destination data transfer size */
4563 vint16_t SOFF; /* Source address signed offset */
4564
4565 vuint32_t NBYTES; /* Inner "minor" byte transfer count */
4566
4567 vint32_t SLAST; /* Last source address adjustment */
4568
4569 vuint32_t DADDR; /* Destination address */
4570
4571 vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
4572 vuint16_t CITERLINKCH:6; /* Link channel number */
4573 vuint16_t CITER:9; /* Current Major iteration count */
4574 vint16_t DOFF; /* Destination address signed offset */
4575
4576 vint32_t DLAST_SGA; /* Last desitination address adjustment */
4577
4578 vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
4579 vuint16_t BITERLINKCH:6; /* Link channel number */
4580 vuint16_t BITER:9; /* Starting Major iteration count */
4581 vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
4582 vuint16_t MAJORLINKCH:6; /* Link channel number */
4583 vuint16_t DONE:1; /* Channel done */
4584 vuint16_t ACTIVE:1; /* Channel active */
4585 vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
4586 vuint16_t E_SG:1; /* Enable scatter/gather processing */
4587 vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
4588 vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
4589 vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
4590 vuint16_t START:1; /* Chanel start */
4591
4592 }; /* end of EDMA_TCD_CHLINK_tag */
4593
4594 /* (4) - CL_TCD (Channel Linking Enabled, Minor Loop mapping Enabled */
4595 /* (CITERE_LINK = BITERE_LINK = 1, EMLM = 1) */
4596 struct EDMA_TCD_MLMIRROR_CHLINK_tag {
4597
4598 vuint32_t SADDR; /* Source address */
4599
4600 vuint16_t SMOD:5; /* Source address modulo */
4601 vuint16_t SSIZE:3; /* Source data transfer size */
4602 vuint16_t DMOD:5; /* Destination address modulo */
4603 vuint16_t DSIZE:3; /* Destination data transfer size */
4604 vint16_t SOFF; /* Source address signed offset */
4605
4606 vuint32_t SMLOE:1; /* Source minor loop offset enabled */
4607 vuint32_t DMLOE:1; /* Destination minor loop offset enable */
4608 vuint32_t MLOFF:20; /* Minor loop offset */
4609 vuint32_t NBYTES:10; /* Inner "minor" byte transfer count */
4610
4611 vint32_t SLAST; /* Last source address adjustment */
4612
4613 vuint32_t DADDR; /* Destination address */
4614
4615 vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
4616 vuint16_t CITERLINKCH:6; /* Link channel number */
4617 vuint16_t CITER:9; /* Current Major iteration count */
4618 vint16_t DOFF; /* Destination address signed offset */
4619
4620 vint32_t DLAST_SGA; /* Last desitination address adjustment */
4621
4622 vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
4623 vuint16_t BITERLINKCH:6; /* Link channel number */
4624 vuint16_t BITER:9; /* Starting Major iteration count */
4625 vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
4626 vuint16_t MAJORLINKCH:6; /* Link channel number */
4627 vuint16_t DONE:1; /* Channel done */
4628 vuint16_t ACTIVE:1; /* Channel active */
4629 vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
4630 vuint16_t E_SG:1; /* Enable scatter/gather processing */
4631 vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
4632 vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
4633 vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
4634 vuint16_t START:1; /* Chanel start */
4635
4636 }; /* end of EDMA_TCD_MLMIRROR_CHLINK_tag */
4637
4638struct EDMA_tag {
4639
4640 union { /* Control (Base+0x0000) */
4641 vuint32_t R;
4642 struct {
4643 vuint32_t :14;
4644 vuint32_t CX:1;
4645 vuint32_t ECX:1;
4646 vuint32_t :6;
4647 vuint32_t GRP0PRI:2;
4648 vuint32_t EMLM:1;
4649 vuint32_t CLM:1;
4650 vuint32_t HALT:1;
4651 vuint32_t HOE:1;
4652 vuint32_t ERGA:1;
4653 vuint32_t ERCA:1;
4654 vuint32_t EDBG:1;
4655 vuint32_t EBW:1;
4656 } B;
4657 } CR;
4658
4659 union { /* Error Status (Base+0x0004) */
4660 vuint32_t R;
4661 struct {
4662 vuint32_t VLD:1;
4663 vuint32_t :16;
4664 vuint32_t CPE:1;
4665 vuint32_t ERRCHN:6;
4666 vuint32_t SAE:1;
4667 vuint32_t SOE:1;
4668 vuint32_t DAE:1;
4669 vuint32_t DOE:1;
4670 vuint32_t NCE:1;
4671 vuint32_t SGE:1;
4672 vuint32_t SBE:1;
4673 vuint32_t DBE:1;
4674 } B;
4675 } ESR;
4676
4677 vuint8_t eDMA_reserved0[4]; /* Reserved 4 bytes (Base+0x0008-0x000B)*/
4678
4679 union { /* Enable Request Low Ch15..0 (Base+0x000C) */
4680 vuint32_t R;
4681 struct {
4682 vuint32_t :16;
4683 vuint32_t ERQ15:1;
4684 vuint32_t ERQ14:1;
4685 vuint32_t ERQ13:1;
4686 vuint32_t ERQ12:1;
4687 vuint32_t ERQ11:1;
4688 vuint32_t ERQ10:1;
4689 vuint32_t ERQ09:1;
4690 vuint32_t ERQ08:1;
4691 vuint32_t ERQ07:1;
4692 vuint32_t ERQ06:1;
4693 vuint32_t ERQ05:1;
4694 vuint32_t ERQ04:1;
4695 vuint32_t ERQ03:1;
4696 vuint32_t ERQ02:1;
4697 vuint32_t ERQ01:1;
4698 vuint32_t ERQ00:1;
4699 } B;
4700 } ERQRL;
4701
4702 vuint8_t eDMA_reserved1[4]; /* Reserved 4 bytes (Base+0x0010-0x0013)*/
4703
4704 union { /* Enable Error Interrupt Low (Base+0x0014) */
4705 vuint32_t R;
4706 struct {
4707 vuint32_t :16;
4708 vuint32_t EEI15:1;
4709 vuint32_t EEI14:1;
4710 vuint32_t EEI13:1;
4711 vuint32_t EEI12:1;
4712 vuint32_t EEI11:1;
4713 vuint32_t EEI10:1;
4714 vuint32_t EEI09:1;
4715 vuint32_t EEI08:1;
4716 vuint32_t EEI07:1;
4717 vuint32_t EEI06:1;
4718 vuint32_t EEI05:1;
4719 vuint32_t EEI04:1;
4720 vuint32_t EEI03:1;
4721 vuint32_t EEI02:1;
4722 vuint32_t EEI01:1;
4723 vuint32_t EEI00:1;
4724 } B;
4725 } EEIRL;
4726
4727 union { /* DMA Set Enable Request (Base+0x0018) */
4728 vuint8_t R;
4729 struct {
4730 vuint8_t :1;
4731 vuint8_t SERQ:7;
4732 } B;
4733 } SERQR;
4734
4735 union { /* DMA Clear Enable Request (Base+0x0019) */
4736 vuint8_t R;
4737 struct {
4738 vuint8_t :1;
4739 vuint8_t CERQ:7;
4740 } B;
4741 } CERQR;
4742
4743 union { /* DMA Set Enable Error Interrupt (Base+0x001A) */
4744 vuint8_t R;
4745 struct {
4746 vuint8_t :1;
4747 vuint8_t SEEI:7;
4748 } B;
4749 } SEEIR;
4750
4751 union { /* DMA Clr Enable Error Interrupt (Base+0x001B) */
4752 vuint8_t R;
4753 struct {
4754 vuint8_t:1;
4755 vuint8_t CEEI:7;
4756 } B;
4757 } CEEIR;
4758
4759 union { /* DMA Clear Interrupt Request (Base+0x001C) */
4760 vuint8_t R;
4761 struct {
4762 vuint8_t :1;
4763 vuint8_t CINT:7;
4764 } B;
4765 } CIRQR;
4766
4767 union { /* DMA Clear error (Base+0x001D) */
4768 vuint8_t R;
4769 struct {
4770 vuint8_t :1;
4771 vuint8_t CERR:7;
4772 } B;
4773 } CER;
4774
4775 union { /* DMA Set Start Bit (Base+0x001E) */
4776 vuint8_t R;
4777 struct {
4778 vuint8_t :1;
4779 vuint8_t SSB:7;
4780 } B;
4781 } SSBR;
4782
4783 union { /* DMA Clear Done Status Bit (Base+0x001F) */
4784 vuint8_t R;
4785 struct {
4786 vuint8_t :1;
4787 vuint8_t CDSB:7;
4788 } B;
4789 } CDSBR;
4790
4791 vuint8_t eDMA_reserved2[4]; /* Reserved 4 bytes (Base+0x0020-0x0023)*/
4792
4793 union { /* DMA Interrupt Req Low Ch15..0 (+0x0024) */
4794 vuint32_t R;
4795 struct {
4796 vuint32_t :16;
4797 vuint32_t INT15:1;
4798 vuint32_t INT14:1;
4799 vuint32_t INT13:1;
4800 vuint32_t INT12:1;
4801 vuint32_t INT11:1;
4802 vuint32_t INT10:1;
4803 vuint32_t INT09:1;
4804 vuint32_t INT08:1;
4805 vuint32_t INT07:1;
4806 vuint32_t INT06:1;
4807 vuint32_t INT05:1;
4808 vuint32_t INT04:1;
4809 vuint32_t INT03:1;
4810 vuint32_t INT02:1;
4811 vuint32_t INT01:1;
4812 vuint32_t INT00:1;
4813 } B;
4814 } IRQRL;
4815
4816 vuint8_t eDMA_reserved3[4]; /* Reserved 4 bytes (Base+0x0028-0x002B)*/
4817
4818 union { /* DMA Error Low Ch15..0 (Base+0x002C)*/
4819 vuint32_t R;
4820 struct {
4821 vuint32_t :16;
4822 vuint32_t ERR15:1;
4823 vuint32_t ERR14:1;
4824 vuint32_t ERR13:1;
4825 vuint32_t ERR12:1;
4826 vuint32_t ERR11:1;
4827 vuint32_t ERR10:1;
4828 vuint32_t ERR09:1;
4829 vuint32_t ERR08:1;
4830 vuint32_t ERR07:1;
4831 vuint32_t ERR06:1;
4832 vuint32_t ERR05:1;
4833 vuint32_t ERR04:1;
4834 vuint32_t ERR03:1;
4835 vuint32_t ERR02:1;
4836 vuint32_t ERR01:1;
4837 vuint32_t ERR00:1;
4838 } B;
4839 } ERL;
4840
4841 vuint8_t eDMA_reserved4[4]; /* Reserved 4 bytes (Base+0x0030-0x0033)*/
4842
4843 union { /* DMA Hardware Request Stat Low (Base+0x0034) */
4844 vuint32_t R;
4845 struct {
4846 vuint32_t :16;
4847 vuint32_t HRS15:1;
4848 vuint32_t HRS14:1;
4849 vuint32_t HRS13:1;
4850 vuint32_t HRS12:1;
4851 vuint32_t HRS11:1;
4852 vuint32_t HRS10:1;
4853 vuint32_t HRS09:1;
4854 vuint32_t HRS08:1;
4855 vuint32_t HRS07:1;
4856 vuint32_t HRS06:1;
4857 vuint32_t HRS05:1;
4858 vuint32_t HRS04:1;
4859 vuint32_t HRS03:1;
4860 vuint32_t HRS02:1;
4861 vuint32_t HRS01:1;
4862 vuint32_t HRS00:1;
4863 } B;
4864 } HRSL;
4865
4866 vuint8_t eDMA_reserved5[200]; /* Reserved 200 bytes (Base+0x0038-0x00FF)*/
4867
4868 union { /* Channel n Priority (Base+0x0100-0x010F)*/
4869 vuint8_t R;
4870 struct {
4871 vuint8_t ECP:1;
4872 vuint8_t DPA:1;
4873 vuint8_t GRPPRI:2;
4874 vuint8_t CHPRI:4;
4875 } B;
4876 } CPR[16];
4877
4878 vuint8_t eDMA_reserved6[3824]; /* Reserved 3808 bytes (+0x0110-0x0FFF) */
4879
4880
4881union { /* 4 different TCD definitions depending on operating mode */
4882
4883 /* Default TCD (Channel Linking and Minor Loop Maping disabled) */
4884 struct EDMA_TCD_STD_tag TCD[16];
4885
4886 /* ML_TCD (Channel Linking disabled, Minor Loop Mapping enabled) */
4887 struct EDMA_TCD_MLMIRROR_tag ML_TCD[16];
4888
4889 /* CL_TCD (Channel Linking enabled, Minor Loop Mapping disabled) */
4890 struct EDMA_TCD_CHLINK_tag CL_TCD[16];
4891
4892 /* MLCL_TCD (Channel Linking enabled, Minor Loop Mapping enabled) */
4893 struct EDMA_TCD_MLMIRROR_CHLINK_tag MLCL_TCD[16];
4894 };
4895
4896
4897 vuint8_t eDMA_reserved7[28160]; /* Reserved 28160 bytes (+0x1200-0x7FFF) */
4898
4899}; /* end of EDMA_tag */
4900/*************************************************************************/
4901/* MODULE : INTC (base address - 0xFFF4_8000) */
4902/*************************************************************************/
4903struct INTC_tag {
4904
4905 union { /* INTC Module Configuration (Base+0x0000) */
4906 vuint32_t R;
4907 struct {
4908 vuint32_t:26;
4909 vuint32_t VTES:1;
4910 vuint32_t:4;
4911 vuint32_t HVEN:1;
4912 } B;
4913 } MCR;
4914
4915 vuint8_t INTC_reserved0[4]; /* reserved 4 bytes (Base+0x0004-0x0007) */
4916
4917 union { /* INTC Current Priority (Base+0x0008) */
4918 vuint32_t R;
4919 struct {
4920 vuint32_t:28;
4921 vuint32_t PRI:4;
4922 } B;
4923 } CPR;
4924
4925 vuint8_t INTC_reserved1[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */
4926
4927 union { /* INTC Interrupt Acknowledge (Base+0x0010) */
4928 vuint32_t R;
4929 struct {
4930 vuint32_t VTBA_PRC0:21;
4931 vuint32_t INTVEC_PRC0:9;
4932 vuint32_t:2;
4933 } B;
4934 } IACKR;
4935
4936 vuint8_t INTC_reserved2[4]; /* Reserved 4 bytes (Base+0x0014-0x0017) */
4937
4938 union { /* INTC End Of Interrupt (Base+0x0018) */
4939 vuint32_t R;
4940 } EOIR;
4941
4942 vuint8_t INTC_reserved3[4]; /* reserved 4 bytes (Base+0x001C-0x0019) */
4943
4944 union { /* INTC Software Set/Clear Interrupt0-7 (+0x0020-0x0027) */
4945 vuint8_t R;
4946 struct {
4947 vuint8_t:6;
4948 vuint8_t SET:1;
4949 vuint8_t CLR:1;
4950 } B;
4951 } SSCIR[8];
4952
4953 vuint8_t INTC_reserved4[24]; /* Reserved 24 bytes (Base+0x0028-0x003F) */
4954
4955 union { /* INTC Priority Select (Base+0x0040-0x0128) */
4956 vuint8_t R;
4957 struct {
4958 vuint8_t:4;
4959 vuint8_t PRI:4;
4960 } B;
4961 } PSR[234];
4962
4963}; /* end of INTC_tag */
4964/****************************************************************************/
4965/* MODULE : DSPI */
4966/* Base Addresses: */
4967/* DSPI_0 - 0xFFF9_0000 */
4968/* DSPI_1 - 0xFFF9_4000 */
4969/* DSPI_2 - 0xFFF9_8000 */
4970/* DSPI_3 - 0xFFF9_C000 */
4971/* DSPI_4 - 0xFFFA_0000 */
4972/* DSPI_5 - 0xFFFA_4000 */
4973/****************************************************************************/
4974struct DSPI_tag{
4975
4976 union { /* DSPI Module Configuraiton (Base+0x0000) */
4977 vuint32_t R;
4978 struct {
4979 vuint32_t MSTR:1;
4980 vuint32_t CONT_SCKE:1;
4981 vuint32_t DCONF:2;
4982 vuint32_t FRZ:1;
4983 vuint32_t MTFE:1;
4984 vuint32_t PCSSE:1;
4985 vuint32_t ROOE:1;
4986 vuint32_t :2;
4987 vuint32_t PCSIS5:1;
4988 vuint32_t PCSIS4:1;
4989 vuint32_t PCSIS3:1;
4990 vuint32_t PCSIS2:1;
4991 vuint32_t PCSIS1:1;
4992 vuint32_t PCSIS0:1;
4993 vuint32_t :1;
4994 vuint32_t MDIS:1;
4995 vuint32_t DIS_TXF:1;
4996 vuint32_t DIS_RXF:1;
4997 vuint32_t CLR_TXF:1;
4998 vuint32_t CLR_RXF:1;
4999 vuint32_t SMPL_PT:2;
5000 vuint32_t :7;
5001 vuint32_t HALT:1;
5002 } B;
5003 } MCR;
5004
5005 vuint8_t DSPI_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */
5006
5007 union { /* DSPI Transfer Count (Base+0x0008) */
5008 vuint32_t R;
5009 struct {
5010 vuint32_t TCNT:16;
5011 vuint32_t :16;
5012 } B;
5013 } TCR;
5014
5015 union { /* DSPI Clock & Tranfer Attrib 0-5 (+0x000C-0x0020) */
5016 vuint32_t R;
5017 struct {
5018 vuint32_t DBR:1;
5019 vuint32_t FMSZ:4;
5020 vuint32_t CPOL:1;
5021 vuint32_t CPHA:1;
5022 vuint32_t LSBFE:1;
5023 vuint32_t PCSSCK:2;
5024 vuint32_t PASC:2;
5025 vuint32_t PDT:2;
5026 vuint32_t PBR:2;
5027 vuint32_t CSSCK:4;
5028 vuint32_t ASC:4;
5029 vuint32_t DT:4;
5030 vuint32_t BR:4;
5031 } B;
5032 } CTAR[6];
5033
5034 vuint8_t DSPI_reserved1[8]; /* Reserved 4 bytes (Base+0x0024-0x002B) */
5035
5036 union { /* DSPI Status (Base+0x002C) */
5037 vuint32_t R;
5038 struct {
5039 vuint32_t TCF:1;
5040 vuint32_t TXRXS:1;
5041 vuint32_t :1;
5042 vuint32_t EOQF:1;
5043 vuint32_t TFUF:1;
5044 vuint32_t :1;
5045 vuint32_t TFFF:1;
5046 vuint32_t :5;
5047 vuint32_t RFOF:1;
5048 vuint32_t :1;
5049 vuint32_t RFDF:1;
5050 vuint32_t :1;
5051 vuint32_t TXCTR:4;
5052 vuint32_t TXNXTPTR:4;
5053 vuint32_t RXCTR:4;
5054 vuint32_t POPNXTPTR:4;
5055 } B;
5056 } SR;
5057
5058 union { /* DSPI DMA/Int Request Select & Enable (+0x0030) */
5059 vuint32_t R;
5060 struct {
5061 vuint32_t TCFRE:1;
5062 vuint32_t :2;
5063 vuint32_t EOQFRE:1;
5064 vuint32_t TFUFRE:1;
5065 vuint32_t :1;
5066 vuint32_t TFFFRE:1;
5067 vuint32_t TFFFDIRS:1;
5068 vuint32_t :4;
5069 vuint32_t RFOFRE:1;
5070 vuint32_t :1;
5071 vuint32_t RFDFRE:1;
5072 vuint32_t RFDFDIRS:1;
5073 vuint32_t :16;
5074 } B;
5075 } RSER;
5076
5077 union { /* DSPI Push TX FIFO (Base+0x0034) */
5078 vuint32_t R;
5079 struct {
5080 vuint32_t CONT:1;
5081 vuint32_t CTAS:3;
5082 vuint32_t EOQ:1;
5083 vuint32_t CTCNT:1;
5084 vuint32_t :4;
5085 vuint32_t PCS5:1;
5086 vuint32_t PCS4:1;
5087 vuint32_t PCS3:1;
5088 vuint32_t PCS2:1;
5089 vuint32_t PCS1:1;
5090 vuint32_t PCS0:1;
5091 vuint32_t TXDATA:16;
5092 } B;
5093 } PUSHR;
5094
5095 union { /* DSPI Pop RX FIFO (Base+0x0038) */
5096 vuint32_t R;
5097 struct {
5098 vuint32_t :16;
5099 vuint32_t RXDATA:16;
5100 } B;
5101 } POPR;
5102
5103 union { /* DSPI Transmit FIFO 0-3 (Base+0x003C-0x0048)*/
5104 vuint32_t R;
5105 struct {
5106 vuint32_t TXCMD:16;
5107 vuint32_t TXDATA:16;
5108 } B;
5109 } TXFR[4];
5110
5111 vuint8_t DSPI_reserved2[48]; /* Reserved 48 bytes (Base+0x004C-0x007B) */
5112
5113 union { /* DSPI Receive FIFO 0-3 (Base+0x007C-0x0088) */
5114 vuint32_t R;
5115 struct {
5116 vuint32_t :16;
5117 vuint32_t RXDATA:16;
5118 } B;
5119 } RXFR[4];
5120 }; /* end of DSPI_tag */
5121 /****************************************************************************/
5122/* MODULE : FlexCAN */
5123/* Base Addresses: */
5124/* FlexCAN_0 - 0xFFFC_0000 */
5125/****************************************************************************/
5126struct FLEXCAN_BUF_t{
5127
5128 union { /* FLEXCAN MBx Control & Status (Offset+0x0080) */
5129 vuint32_t R;
5130 struct {
5131 vuint32_t :4;
5132 vuint32_t CODE:4;
5133 vuint32_t :1;
5134 vuint32_t SRR:1;
5135 vuint32_t IDE:1;
5136 vuint32_t RTR:1;
5137 vuint32_t LENGTH:4;
5138 vuint32_t TIMESTAMP:16;
5139 } B;
5140 } CS;
5141
5142 union { /* FLEXCAN MBx Identifier (Offset+0x0084) */
5143 vuint32_t R;
5144 struct {
5145 vuint32_t PRIO:3;
5146 vuint32_t STD_ID:11;
5147 vuint32_t EXT_ID:18;
5148 } B;
5149 } ID;
5150
5151 union { /* FLEXCAN MBx Data 0..7 (Offset+0x0088) */
5152 vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
5153 vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
5154 vuint32_t W[2]; /* Data buffer in words (32 bits) */
5155 vuint32_t R[2]; /* Data buffer in words (32 bits) */
5156 } DATA;
5157
5158}; /* end of FLEXCAN_BUF_t */
5159
5160
5161struct FLEXCAN_RXFIFO_t{ /* RxFIFO Configuration */
5162
5163 union { /* RxFIFO Control & Status (Offset+0x0080) */
5164 vuint32_t R;
5165 struct {
5166 vuint32_t :9;
5167 vuint32_t SRR:1;
5168 vuint32_t IDE:1;
5169 vuint32_t RTR:1;
5170 vuint32_t LENGTH:4;
5171 vuint32_t TIMESTAMP:16;
5172 } B;
5173 } CS;
5174
5175 union { /* RxFIFO Identifier (Offset+0x0084) */
5176 vuint32_t R;
5177 struct {
5178 vuint32_t :3;
5179 vuint32_t STD_ID:11;
5180 vuint32_t EXT_ID:18;
5181 } B;
5182 } ID;
5183
5184 union { /* RxFIFO Data 0..7 (Offset+0x0088) */
5185 vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
5186 vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
5187 vuint32_t W[2]; /* Data buffer in words (32 bits) */
5188 vuint32_t R[2]; /* Data buffer in words (32 bits) */
5189 } DATA;
5190
5191 vuint8_t FLEXCAN_RX_reserved0[80]; /* Reserved 80 bytes (+0x0090-0x00DF)*/
5192
5193 union { /* RxFIFO ID Table 0..7 (+0x00E0-0x00FC) */
5194 vuint32_t R;
5195 } IDTABLE[8];
5196
5197}; /* end of FLEXCAN_RXFIFO_t */
5198
5199
5200struct FLEXCAN_tag{
5201
5202 union { /* FLEXCAN Module Configuration (Base+0x0000) */
5203 vuint32_t R;
5204 struct {
5205 vuint32_t MDIS:1;
5206 vuint32_t FRZ:1;
5207 vuint32_t FEN:1;
5208 vuint32_t HALT:1;
5209 vuint32_t NOTRDY:1;
5210 vuint32_t WAKMSK:1;
5211 vuint32_t SOFTRST:1;
5212 vuint32_t FRZACK:1;
5213 vuint32_t SUPV:1;
5214 vuint32_t :1;
5215 vuint32_t WRNEN:1;
5216 vuint32_t LPMACK:1;
5217 vuint32_t WAKSRC:1;
5218 vuint32_t :1;
5219 vuint32_t SRXDIS:1;
5220 vuint32_t BCC:1;
5221 vuint32_t:2;
5222 vuint32_t LPRIO_EN:1;
5223 vuint32_t AEN:1;
5224 vuint32_t:2;
5225 vuint32_t IDAM:2;
5226 vuint32_t:2;
5227 vuint32_t MAXMB:6;
5228 } B;
5229 } MCR;
5230
5231 union { /* FLEXCAN Control (Base+0x0004) */
5232 vuint32_t R;
5233 struct {
5234 vuint32_t PRESDIV:8;
5235 vuint32_t RJW:2;
5236 vuint32_t PSEG1:3;
5237 vuint32_t PSEG2:3;
5238 vuint32_t BOFFMSK:1;
5239 vuint32_t ERRMSK:1;
5240 vuint32_t CLKSRC:1;
5241 vuint32_t LPB:1;
5242 vuint32_t TWRNMSK:1;
5243 vuint32_t RWRNMSK:1;
5244 vuint32_t :2;
5245 vuint32_t SMP:1;
5246 vuint32_t BOFFREC:1;
5247 vuint32_t TSYN:1;
5248 vuint32_t LBUF:1;
5249 vuint32_t LOM:1;
5250 vuint32_t PROPSEG:3;
5251 } B;
5252 } CR;
5253
5254 union { /* FLEXCAN Free Running Timer (Base+0x0008) */
5255 vuint32_t R;
5256 struct {
5257 vuint32_t :16;
5258 vuint32_t TIMER:16;
5259 } B;
5260 } TIMER;
5261
5262 vuint8_t FLEXCAN_reserved0[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */
5263
5264 union { /* FLEXCAN RX Global Mask (Base+0x0010) */
5265 vuint32_t R;
5266 struct {
5267 vuint32_t MI:32;
5268 } B;
5269 } RXGMASK;
5270
5271 /* --- Following 2 registers are included for legacy purposes only --- */
5272
5273 union { /* FLEXCAN RX 14 Mask (Base+0x0014) */
5274 vuint32_t R;
5275 struct {
5276 vuint32_t MI:32;
5277 } B;
5278 } RX14MASK;
5279
5280 union { /* FLEXCAN RX 15 Mask (Base+0x0018) */
5281 vuint32_t R;
5282 struct {
5283 vuint32_t MI:32;
5284 } B;
5285 } RX15MASK;
5286
5287 /* --- */
5288
5289 union { /* FLEXCAN Error Counter (Base+0x001C) */
5290 vuint32_t R;
5291 struct {
5292 vuint32_t :16;
5293 vuint32_t RXECNT:8;
5294 vuint32_t TXECNT:8;
5295 } B;
5296 } ECR;
5297
5298 union { /* FLEXCAN Error & Status (Base+0x0020) */
5299 vuint32_t R;
5300 struct {
5301 vuint32_t :14;
5302 vuint32_t TWRNINT:1;
5303 vuint32_t RWRNINT:1;
5304 vuint32_t BIT1ERR:1;
5305 vuint32_t BIT0ERR:1;
5306 vuint32_t ACKERR:1;
5307 vuint32_t CRCERR:1;
5308 vuint32_t FRMERR:1;
5309 vuint32_t STFERR:1;
5310 vuint32_t TXWRN:1;
5311 vuint32_t RXWRN:1;
5312 vuint32_t IDLE:1;
5313 vuint32_t TXRX:1;
5314 vuint32_t FLTCONF:2;
5315 vuint32_t :1;
5316 vuint32_t BOFFINT:1;
5317 vuint32_t ERRINT:1;
5318 vuint32_t :1;
5319 } B;
5320 } ESR;
5321
5322 union { /* FLEXCAN Interruput Masks H (Base+0x0024) */
5323 vuint32_t R;
5324 struct {
5325 vuint32_t BUF63M:1;
5326 vuint32_t BUF62M:1;
5327 vuint32_t BUF61M:1;
5328 vuint32_t BUF60M:1;
5329 vuint32_t BUF59M:1;
5330 vuint32_t BUF58M:1;
5331 vuint32_t BUF57M:1;
5332 vuint32_t BUF56M:1;
5333 vuint32_t BUF55M:1;
5334 vuint32_t BUF54M:1;
5335 vuint32_t BUF53M:1;
5336 vuint32_t BUF52M:1;
5337 vuint32_t BUF51M:1;
5338 vuint32_t BUF50M:1;
5339 vuint32_t BUF49M:1;
5340 vuint32_t BUF48M:1;
5341 vuint32_t BUF47M:1;
5342 vuint32_t BUF46M:1;
5343 vuint32_t BUF45M:1;
5344 vuint32_t BUF44M:1;
5345 vuint32_t BUF43M:1;
5346 vuint32_t BUF42M:1;
5347 vuint32_t BUF41M:1;
5348 vuint32_t BUF40M:1;
5349 vuint32_t BUF39M:1;
5350 vuint32_t BUF38M:1;
5351 vuint32_t BUF37M:1;
5352 vuint32_t BUF36M:1;
5353 vuint32_t BUF35M:1;
5354 vuint32_t BUF34M:1;
5355 vuint32_t BUF33M:1;
5356 vuint32_t BUF32M:1;
5357 } B;
5358 } IMRH;
5359
5360 union { /* FLEXCAN Interruput Masks L (Base+0x0028) */
5361 vuint32_t R;
5362 struct {
5363 vuint32_t BUF31M:1;
5364 vuint32_t BUF30M:1;
5365 vuint32_t BUF29M:1;
5366 vuint32_t BUF28M:1;
5367 vuint32_t BUF27M:1;
5368 vuint32_t BUF26M:1;
5369 vuint32_t BUF25M:1;
5370 vuint32_t BUF24M:1;
5371 vuint32_t BUF23M:1;
5372 vuint32_t BUF22M:1;
5373 vuint32_t BUF21M:1;
5374 vuint32_t BUF20M:1;
5375 vuint32_t BUF19M:1;
5376 vuint32_t BUF18M:1;
5377 vuint32_t BUF17M:1;
5378 vuint32_t BUF16M:1;
5379 vuint32_t BUF15M:1;
5380 vuint32_t BUF14M:1;
5381 vuint32_t BUF13M:1;
5382 vuint32_t BUF12M:1;
5383 vuint32_t BUF11M:1;
5384 vuint32_t BUF10M:1;
5385 vuint32_t BUF09M:1;
5386 vuint32_t BUF08M:1;
5387 vuint32_t BUF07M:1;
5388 vuint32_t BUF06M:1;
5389 vuint32_t BUF05M:1;
5390 vuint32_t BUF04M:1;
5391 vuint32_t BUF03M:1;
5392 vuint32_t BUF02M:1;
5393 vuint32_t BUF01M:1;
5394 vuint32_t BUF00M:1;
5395 } B;
5396 } IMRL;
5397
5398 union { /* FLEXCAN Interruput Flag H (Base+0x002C) */
5399 vuint32_t R;
5400 struct {
5401 vuint32_t BUF63I:1;
5402 vuint32_t BUF62I:1;
5403 vuint32_t BUF61I:1;
5404 vuint32_t BUF60I:1;
5405 vuint32_t BUF59I:1;
5406 vuint32_t BUF58I:1;
5407 vuint32_t BUF57I:1;
5408 vuint32_t BUF56I:1;
5409 vuint32_t BUF55I:1;
5410 vuint32_t BUF54I:1;
5411 vuint32_t BUF53I:1;
5412 vuint32_t BUF52I:1;
5413 vuint32_t BUF51I:1;
5414 vuint32_t BUF50I:1;
5415 vuint32_t BUF49I:1;
5416 vuint32_t BUF48I:1;
5417 vuint32_t BUF47I:1;
5418 vuint32_t BUF46I:1;
5419 vuint32_t BUF45I:1;
5420 vuint32_t BUF44I:1;
5421 vuint32_t BUF43I:1;
5422 vuint32_t BUF42I:1;
5423 vuint32_t BUF41I:1;
5424 vuint32_t BUF40I:1;
5425 vuint32_t BUF39I:1;
5426 vuint32_t BUF38I:1;
5427 vuint32_t BUF37I:1;
5428 vuint32_t BUF36I:1;
5429 vuint32_t BUF35I:1;
5430 vuint32_t BUF34I:1;
5431 vuint32_t BUF33I:1;
5432 vuint32_t BUF32I:1;
5433 } B;
5434 } IFRH;
5435
5436 union { /* FLEXCAN Interruput Flag l (Base+0x0030) */
5437 vuint32_t R;
5438 struct {
5439 vuint32_t BUF31I:1;
5440 vuint32_t BUF30I:1;
5441 vuint32_t BUF29I:1;
5442 vuint32_t BUF28I:1;
5443 vuint32_t BUF27I:1;
5444 vuint32_t BUF26I:1;
5445 vuint32_t BUF25I:1;
5446 vuint32_t BUF24I:1;
5447 vuint32_t BUF23I:1;
5448 vuint32_t BUF22I:1;
5449 vuint32_t BUF21I:1;
5450 vuint32_t BUF20I:1;
5451 vuint32_t BUF19I:1;
5452 vuint32_t BUF18I:1;
5453 vuint32_t BUF17I:1;
5454 vuint32_t BUF16I:1;
5455 vuint32_t BUF15I:1;
5456 vuint32_t BUF14I:1;
5457 vuint32_t BUF13I:1;
5458 vuint32_t BUF12I:1;
5459 vuint32_t BUF11I:1;
5460 vuint32_t BUF10I:1;
5461 vuint32_t BUF09I:1;
5462 vuint32_t BUF08I:1;
5463 vuint32_t BUF07I:1;
5464 vuint32_t BUF06I:1;
5465 vuint32_t BUF05I:1;
5466 vuint32_t BUF04I:1;
5467 vuint32_t BUF03I:1;
5468 vuint32_t BUF02I:1;
5469 vuint32_t BUF01I:1;
5470 vuint32_t BUF00I:1;
5471 } B;
5472 } IFRL; /* Interruput Flag Register */
5473
5474 vuint8_t FLEXCAN_reserved1[76]; /*Reserved 76 bytes (Base+0x0034-0x007F)*/
5475
5476/****************************************************************************/
5477/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */
5478/****************************************************************************/
5479 /* Standard Buffer Structure */
5480 struct FLEXCAN_BUF_t BUF[64];
5481
5482 /* RX FIFO and Buffer Structure */
5483 /*struct FLEXCAN_RXFIFO_t RXFIFO; */
5484 /*struct FLEXCAN_BUF_t BUF[56]; */
5485/****************************************************************************/
5486
5487 vuint8_t FLEXCAN_reserved2[1024]; /*Reserved 1024 (Base+0x0480-0x087F)*/
5488
5489 union { /* FLEXCAN RX Individual Mask (Base+0x0880-0x097F) */
5490 vuint32_t R;
5491 struct {
5492 vuint32_t MI:32;
5493 } B;
5494 } RXIMR[64];
5495
5496}; /* end of FLEXCAN_tag */
5497/****************************************************************************/
5498/* MODULE : DMAMUX (base address - 0xFFFD_C000) */
5499/****************************************************************************/
5500 struct DMAMUX_tag {
5501 union { /* DMAMUX Channel Configuration (Base+0x0000-0x000F) */
5502 vuint8_t R;
5503 struct {
5504 vuint8_t ENBL:1;
5505 vuint8_t TRIG:1;
5506 vuint8_t SOURCE:6;
5507 } B;
5508 } CHCONFIG[16];
5509
5510 }; /* end of DMAMUX_tag */
5511
5512/******************************************************************
5513| defines and macros (scope: module-local)
5514|-----------------------------------------------------------------*/
5515/* Define instances of modules */
5516
5517#define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL)
5518#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)
5519#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)
5520#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)
5521#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)
5522#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)
5523#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)
5524#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)
5525#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)
5526#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)
5527#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)
5528#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)
5529#define ADC_1 (*(volatile struct ADC1_tag *) 0xFFE04000UL)
5530#define LINFLEX_0 (*(volatile struct LINFLEXD0_tag *) 0xFFE40000UL)
5531#define LINFLEX_1 (*(volatile struct LINFLEXD1_tag *) 0xFFE44000UL)
5532#define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL)
5533#define CTU (*(volatile struct CTU_tag *) 0xFFE64000UL)
5534#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)
5535#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)
5536#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)
5537#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)
5538#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL)
5539#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
5540#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)
5541#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)
5542#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
5543#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)
5544
5545
5546#ifdef __MWERKS__
5547#pragma pop
5548#endif
5549
5550#ifdef __cplusplus
5551}
5552#endif
5553#endif
5554/* End of file */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 08:38:15 +0100