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1/*
2 SPC5 HAL - Copyright (C) 2013 STMicroelectronics
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC564Axx/hal_lld.h
19 * @brief SPC564Axx HAL subsystem low level driver header.
20 * @pre This module requires the following macros to be defined in the
21 * @p board.h file:
22 * - SPC5_XOSC_CLK.
23 * .
24 *
25 * @addtogroup HAL
26 * @{
27 */
28
29#ifndef HAL_LLD_H
30#define HAL_LLD_H
31
32#include "registers.h"
33#include "spc5_registry.h"
34
35/*===========================================================================*/
36/* Driver constants. */
37/*===========================================================================*/
38
39/**
40 * @brief Defines the support for realtime counters in the HAL.
41 */
42#define HAL_IMPLEMENTS_COUNTERS FALSE
43
44/**
45 * @brief Platform name.
46 */
47#define PLATFORM_NAME "SPC564Axx Powertrain"
48
49/**
50 * @name ESYNCR2 register definitions
51 * @{
52 */
53#define SPC5_RFD_DIV2 0 /**< Divide VCO frequency by 2. */
54#define SPC5_RFD_DIV4 1 /**< Divide VCO frequency by 4. */
55#define SPC5_RFD_DIV8 2 /**< Divide VCO frequency by 8. */
56#define SPC5_RFD_DIV16 3 /**< Divide VCO frequency by 16.*/
57/** @} */
58
59/**
60 * @name BIUCR register definitions
61 * @{
62 */
63#define BIUCR_BANK1_TOO 0x01000000 /**< Use settings for bank1 too.*/
64#define BIUCR_MASTER7_PREFETCH 0x00800000 /**< Enable master 7 prefetch. */
65#define BIUCR_MASTER6_PREFETCH 0x00400000 /**< Enable master 6 prefetch. */
66#define BIUCR_MASTER5_PREFETCH 0x00200000 /**< Enable master 5 prefetch. */
67#define BIUCR_MASTER4_PREFETCH 0x00100000 /**< Enable master 4 prefetch. */
68#define BIUCR_MASTER3_PREFETCH 0x00080000 /**< Enable master 3 prefetch. */
69#define BIUCR_MASTER2_PREFETCH 0x00040000 /**< Enable master 2 prefetch. */
70#define BIUCR_MASTER1_PREFETCH 0x00020000 /**< Enable master 1 prefetch. */
71#define BIUCR_MASTER0_PREFETCH 0x00010000 /**< Enable master 0 prefetch. */
72#define BIUCR_APC_MASK 0x0000E000 /**< APC field mask. */
73#define BIUCR_APC_0 (0 << 13) /**< No additional hold cycles. */
74#define BIUCR_APC_1 (1 << 13) /**< 1 additional hold cycle. */
75#define BIUCR_APC_2 (2 << 13) /**< 2 additional hold cycles. */
76#define BIUCR_APC_3 (3 << 13) /**< 3 additional hold cycles. */
77#define BIUCR_APC_4 (4 << 13) /**< 4 additional hold cycles. */
78#define BIUCR_APC_5 (5 << 13) /**< 5 additional hold cycles. */
79#define BIUCR_APC_6 (6 << 13) /**< 6 additional hold cycles. */
80#define BIUCR_WWSC_MASK 0x00001800 /**< WWSC field mask. */
81#define BIUCR_WWSC_0 (0 << 11) /**< No write wait states. */
82#define BIUCR_WWSC_1 (1 << 11) /**< 1 write wait state. */
83#define BIUCR_WWSC_2 (2 << 11) /**< 2 write wait states. */
84#define BIUCR_WWSC_3 (3 << 11) /**< 3 write wait states. */
85#define BIUCR_RWSC_MASK 0x00001800 /**< RWSC field mask. */
86#define BIUCR_RWSC_0 (0 << 8) /**< No read wait states. */
87#define BIUCR_RWSC_1 (1 << 8) /**< 1 read wait state. */
88#define BIUCR_RWSC_2 (2 << 8) /**< 2 read wait states. */
89#define BIUCR_RWSC_3 (3 << 8) /**< 3 read wait states. */
90#define BIUCR_RWSC_4 (4 << 8) /**< 4 read wait states. */
91#define BIUCR_RWSC_5 (5 << 8) /**< 5 read wait states. */
92#define BIUCR_RWSC_6 (6 << 8) /**< 6 read wait states. */
93#define BIUCR_RWSC_7 (7 << 8) /**< 7 read wait states. */
94#define BIUCR_DPFEN 0x00000040 /**< Data prefetch enable. */
95#define BIUCR_IPFEN 0x00000010 /**< Instr. prefetch enable. */
96#define BIUCR_PFLIM_MASK 0x00000060 /**< PFLIM field mask. */
97#define BIUCR_PFLIM_NO (0 << 1) /**< No prefetching. */
98#define BIUCR_PFLIM_ON_MISS (1 << 1) /**< Prefetch on miss. */
99#define BIUCR_PFLIM_ON_HITMISS (2 << 1) /**< Prefetch on hit and miss. */
100#define BIUCR_BFEN 0x00000001 /**< Flash buffering enable. */
101/** @} */
102
103/*===========================================================================*/
104/* Driver pre-compile time settings. */
105/*===========================================================================*/
106
107/**
108 * @brief Disables the clocks initialization in the HAL.
109 */
110#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
111#define SPC5_NO_INIT FALSE
112#endif
113
114/**
115 * @brief Clock bypass.
116 * @note If set to @p TRUE then the PLL is not started and initialized, the
117 * external clock is used as-is and the other clock-related settings
118 * are ignored.
119 */
120#if !defined(SPC5_CLK_BYPASS) || defined(__DOXYGEN__)
121#define SPC5_CLK_BYPASS FALSE
122#endif
123
124/**
125 * @brief Disables the overclock checks.
126 */
127#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
128#define SPC5_ALLOW_OVERCLOCK FALSE
129#endif
130
131/**
132 * @brief External clock pre-divider.
133 * @note Must be in range 1...15.
134 */
135#if !defined(SPC5_CLK_PREDIV_VALUE) || defined(__DOXYGEN__)
136#define SPC5_CLK_PREDIV_VALUE 2
137#endif
138
139/**
140 * @brief Multiplication factor divider.
141 * @note Must be in range 32...96.
142 */
143#if !defined(SPC5_CLK_MFD_VALUE) || defined(__DOXYGEN__)
144#define SPC5_CLK_MFD_VALUE 75
145#endif
146
147/**
148 * @brief Reduced frequency divider.
149 */
150#if !defined(SPC5_CLK_RFD) || defined(__DOXYGEN__)
151#define SPC5_CLK_RFD RFD_DIV2
152#endif
153
154/**
155 * @brief Flash buffer and prefetching settings.
156 * @note Please refer to the SPC564Axx reference manual about the meaning
157 * of the following bits, if in doubt DO NOT MODIFY IT.
158 * @note Do not specify the APC, WWSC, RWSC bits in this value because
159 * those are calculated from the system clock and ORed with this
160 * value.
161 */
162#if !defined(SPC5_FLASH_BIUCR) || defined(__DOXYGEN__)
163#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \
164 BIUCR_MASTER4_PREFETCH | \
165 BIUCR_MASTER0_PREFETCH | \
166 BIUCR_DPFEN | \
167 BIUCR_IPFEN | \
168 BIUCR_PFLIM_ON_MISS | \
169 BIUCR_BFEN)
170#endif
171
172/**
173 * @brief eMIOS global prescaler value.
174 */
175#if !defined(SPC5_EMIOS_GPRE_VALUE) || defined(__DOXYGEN__)
176#define SPC5_EMIOS_GPRE_VALUE 20
177#endif
178
179/*===========================================================================*/
180/* Derived constants and error checks. */
181/*===========================================================================*/
182
183/*
184 * Configuration-related checks.
185 */
186#if !defined(SPC564Axx_MCUCONF)
187#error "Using a wrong mcuconf.h file, SPC564Axx_MCUCONF not defined"
188#endif
189
190#if (SPC5_CLK_PREDIV_VALUE < 1) || (SPC5_CLK_PREDIV_VALUE > 15)
191#error "invalid SPC5_CLK_PREDIV_VALUE value specified"
192#endif
193
194#if (SPC5_CLK_MFD_VALUE < 32) || (SPC5_CLK_MFD_VALUE > 96)
195#error "invalid SPC5_CLK_MFD_VALUE value specified"
196#endif
197
198#if (SPC5_CLK_RFD != SPC5_RFD_DIV2) && (SPC5_CLK_RFD != SPC5_RFD_DIV4) && \
199 (SPC5_CLK_RFD != SPC5_RFD_DIV8) && (SPC5_CLK_RFD != SPC5_RFD_DIV16)
200#error "invalid SPC5_CLK_RFD value specified"
201#endif
202
203#if (SPC5_EMIOS_GPRE_VALUE < 1) || (SPC5_EMIOS_GPRE_VALUE > 256)
204#error "invalid SPC5_EMIOS_GPRE_VALUE value specified"
205#endif
206
207/**
208 * @brief PLL input divider.
209 */
210#define SPC5_CLK_PREDIV (SPC5_CLK_PREDIV_VALUE - 1)
211
212/**
213 * @brief PLL multiplier.
214 */
215#define SPC5_CLK_MFD (SPC5_CLK_MFD_VALUE)
216
217/**
218 * @brief PLL output clock.
219 */
220#define SPC5_PLLCLK ((SPC5_XOSC_CLK / SPC5_CLK_PREDIV_VALUE) * \
221 SPC5_CLK_MFD_VALUE)
222
223#if (SPC5_PLLCLK < 256000000) || (SPC5_PLLCLK > 512000000)
224#error "VCO frequency out of the acceptable range (256...512)"
225#endif
226
227/**
228 * @brief PLL output clock.
229 */
230#if !SPC5_CLK_BYPASS || defined(__DOXYGEN__)
231#define SPC5_SYSCLK (SPC5_PLLCLK / (1 << (SPC5_CLK_RFD + 1)))
232#else
233#define SPC5_SYSCLK SPC5_XOSC_CLK
234#endif
235
236#if (SPC5_SYSCLK > 150000000) && !SPC5_ALLOW_OVERCLOCK
237#error "System clock above maximum rated frequency (150MHz)"
238#endif
239
240/**
241 * @brief Flash wait states are a function of the system clock.
242 */
243#if (SPC5_SYSCLK <= 20000000) || defined(__DOXYGEN__)
244#define SPC5_FLASH_WS (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_3)
245#elif SPC5_SYSCLK <= 61000000
246#define SPC5_FLASH_WS (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_3)
247#elif SPC5_SYSCLK <= 90000000
248#define SPC5_FLASH_WS (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_3)
249#elif SPC5_SYSCLK <= 123000000
250#define SPC5_FLASH_WS (BIUCR_APC_3 | BIUCR_RWSC_3 | BIUCR_WWSC_3)
251#else
252#define SPC5_FLASH_WS (BIUCR_APC_4 | BIUCR_RWSC_4 | BIUCR_WWSC_3)
253#endif
254
255/**
256 * @brief RAM wait states are a function of the system clock.
257 */
258#if (SPC5_SYSCLK <= 98000000) || defined(__DOXYGEN__)
259#define SPC5_RAM_WS 0
260#else
261#define SPC5_RAM_WS 0x40000000
262#endif
263
264/**
265 * @brief eMIOS global prescaler setting.
266 */
267#define SPC5_EMIOS_GPRE (SPC5_EMIOS_GPRE_VALUE << 8)
268
269/*===========================================================================*/
270/* Driver data structures and types. */
271/*===========================================================================*/
272
273/*===========================================================================*/
274/* Driver macros. */
275/*===========================================================================*/
276
277/*===========================================================================*/
278/* External declarations. */
279/*===========================================================================*/
280
281#include "spc5_edma.h"
282
283#ifdef __cplusplus
284extern "C" {
285#endif
286 void hal_lld_init(void);
287 void spc_clock_init(void);
288#ifdef __cplusplus
289}
290#endif
291
292#endif /* HAL_LLD_H */
293
294/** @} */
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