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diff --git a/lib/chibios/os/hal/ports/SPC5/SPC56ECxx/cfg/mcuconf.h.ftl b/lib/chibios/os/hal/ports/SPC5/SPC56ECxx/cfg/mcuconf.h.ftl
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+++ b/lib/chibios/os/hal/ports/SPC5/SPC56ECxx/cfg/mcuconf.h.ftl
@@ -0,0 +1,369 @@
1[#ftl]
2[@pp.dropOutputFile /]
3[@pp.changeOutputFile name="mcuconf.h" /]
4/*
5 SPC5 HAL - Copyright (C) 2013 STMicroelectronics
6
7 Licensed under the Apache License, Version 2.0 (the "License");
8 you may not use this file except in compliance with the License.
9 You may obtain a copy of the License at
10
11 http://www.apache.org/licenses/LICENSE-2.0
12
13 Unless required by applicable law or agreed to in writing, software
14 distributed under the License is distributed on an "AS IS" BASIS,
15 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 See the License for the specific language governing permissions and
17 limitations under the License.
18*/
19
20#ifndef _MCUCONF_H_
21#define _MCUCONF_H_
22
23/*
24 * SPC56ECxx drivers configuration.
25 * The following settings override the default settings present in
26 * the various device driver implementation headers.
27 * Note that the settings for each driver only have effect if the whole
28 * driver is enabled in halconf.h.
29 *
30 * IRQ priorities:
31 * 1...15 Lowest...Highest.
32 * DMA priorities:
33 * 0...15 Highest...Lowest.
34 */
35
36#define SPC56ECxx_MCUCONF
37
38/*
39 * HAL driver system settings.
40 */
41#define SPC5_NO_INIT ${conf.instance.initialization_settings.do_not_init.value[0]?upper_case}
42#define SPC5_ALLOW_OVERCLOCK ${conf.instance.initialization_settings.allow_overclocking.value[0]?upper_case}
43#define SPC5_DISABLE_WATCHDOG ${conf.instance.initialization_settings.disable_watchdog.value[0]?upper_case}
44#define SPC5_FMPLL0_IDF_VALUE ${conf.instance.initialization_settings.fmpll0_settings.idf_value.value[0]}
45#define SPC5_FMPLL0_NDIV_VALUE ${conf.instance.initialization_settings.fmpll0_settings.ndiv_value.value[0]}
46#define SPC5_FMPLL0_ODF ${conf.instance.initialization_settings.fmpll0_settings.odf_value.value[0]}
47#define SPC5_XOSCDIV_VALUE ${conf.instance.initialization_settings.clocks.fxosc_divider.value[0]}
48#define SPC5_IRCDIV_VALUE ${conf.instance.initialization_settings.clocks.firc_divider.value[0]}
49#define SPC5_PERIPHERAL1_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_1_clock_divider.value[0]}
50#define SPC5_PERIPHERAL2_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_2_clock_divider.value[0]}
51#define SPC5_PERIPHERAL3_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_3_clock_divider.value[0]}
52#define SPC5_Z0_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.z0_core_clock_divider.value[0]}
53#define SPC5_FEC_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.fec_clock_divider.value[0]}
54#define SPC5_FLASH_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.flash_controller_clock_divider.value[0]}
55#define SPC5_CLOCK_FAILURE_HOOK() ${conf.instance.initialization_settings.clocks.clock_failure_hook.value[0]}
56
57#define SPC5_EMIOS0_GPRE_VALUE ${conf.instance.initialization_settings.clocks.emios0_global_prescaler.value[0]?number}
58#define SPC5_EMIOS1_GPRE_VALUE ${conf.instance.initialization_settings.clocks.emios1_global_prescaler.value[0]?number}
59
60/*
61* for the unexpected Reset on "Load from RAM" Issue,
62* This switch has to be activated.
63*/
64#define SPC56ECXX_FMPLL_CLOCK_ERRATA_WORKAROUND FALSE
65
66/*
67 * EDMA driver settings.
68 */
69#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP1PRI(1) | \
70 EDMA_CR_GRP0PRI(0) | \
71 EDMA_CR_EMLM | \
72 EDMA_CR_ERGA)
73#define SPC5_EDMA_GROUP0_PRIORITIES [#rt/]
74[#list conf.instance.edma_settings.group_0_channels_priorities.* as channel]
75 [#if channel_has_next]
76${channel.value[0]}, [#rt/]
77 [#else]
78${channel.value[0]}
79 [/#if]
80[/#list]
81#define SPC5_EDMA_GROUP1_PRIORITIES [#rt/]
82[#list conf.instance.edma_settings.group_1_channels_priorities.* as channel]
83 [#if channel_has_next]
84${channel.value[0]}, [#rt/]
85 [#else]
86${channel.value[0]}
87 [/#if]
88[/#list]
89#define SPC5_EDMA_ERROR_IRQ_PRIO 12
90#define SPC5_EDMA_ERROR_HANDLER() osalSysHalt("DMA failure")
91
92/*
93 * SERIAL driver system settings.
94 */
95#define SPC5_SERIAL_USE_LINFLEX0 ${(conf.instance.linflex_settings.linflex0.value[0] == "Serial")?string?upper_case}
96#define SPC5_SERIAL_USE_LINFLEX1 ${(conf.instance.linflex_settings.linflex1.value[0] == "Serial")?string?upper_case}
97#define SPC5_SERIAL_USE_LINFLEX2 ${(conf.instance.linflex_settings.linflex2.value[0] == "Serial")?string?upper_case}
98#define SPC5_SERIAL_USE_LINFLEX3 ${(conf.instance.linflex_settings.linflex3.value[0] == "Serial")?string?upper_case}
99#define SPC5_SERIAL_USE_LINFLEX4 ${(conf.instance.linflex_settings.linflex4.value[0] == "Serial")?string?upper_case}
100#define SPC5_SERIAL_USE_LINFLEX5 ${(conf.instance.linflex_settings.linflex5.value[0] == "Serial")?string?upper_case}
101#define SPC5_SERIAL_USE_LINFLEX6 ${(conf.instance.linflex_settings.linflex6.value[0] == "Serial")?string?upper_case}
102#define SPC5_SERIAL_USE_LINFLEX7 ${(conf.instance.linflex_settings.linflex7.value[0] == "Serial")?string?upper_case}
103#define SPC5_SERIAL_USE_LINFLEX8 ${(conf.instance.linflex_settings.linflex8.value[0] == "Serial")?string?upper_case}
104#define SPC5_SERIAL_USE_LINFLEX9 ${(conf.instance.linflex_settings.linflex9.value[0] == "Serial")?string?upper_case}
105#define SPC5_SERIAL_LINFLEX0_PRIORITY ${conf.instance.irq_priority_settings.linflex0.value[0]}
106#define SPC5_SERIAL_LINFLEX1_PRIORITY ${conf.instance.irq_priority_settings.linflex1.value[0]}
107#define SPC5_SERIAL_LINFLEX2_PRIORITY ${conf.instance.irq_priority_settings.linflex2.value[0]}
108#define SPC5_SERIAL_LINFLEX3_PRIORITY ${conf.instance.irq_priority_settings.linflex3.value[0]}
109#define SPC5_SERIAL_LINFLEX4_PRIORITY ${conf.instance.irq_priority_settings.linflex4.value[0]}
110#define SPC5_SERIAL_LINFLEX5_PRIORITY ${conf.instance.irq_priority_settings.linflex5.value[0]}
111#define SPC5_SERIAL_LINFLEX6_PRIORITY ${conf.instance.irq_priority_settings.linflex6.value[0]}
112#define SPC5_SERIAL_LINFLEX7_PRIORITY ${conf.instance.irq_priority_settings.linflex7.value[0]}
113#define SPC5_SERIAL_LINFLEX8_PRIORITY ${conf.instance.irq_priority_settings.linflex8.value[0]}
114#define SPC5_SERIAL_LINFLEX9_PRIORITY ${conf.instance.irq_priority_settings.linflex9.value[0]}
115
116/*
117 * SPI driver system settings.
118 */
119#define SPC5_SPI_USE_DSPI0 ${conf.instance.dspi_settings.dspi_0.value[0]?upper_case}
120#define SPC5_SPI_USE_DSPI1 ${conf.instance.dspi_settings.dspi_1.value[0]?upper_case}
121#define SPC5_SPI_USE_DSPI2 ${conf.instance.dspi_settings.dspi_2.value[0]?upper_case}
122#define SPC5_SPI_USE_DSPI3 ${conf.instance.dspi_settings.dspi_3.value[0]?upper_case}
123#define SPC5_SPI_USE_DSPI4 ${conf.instance.dspi_settings.dspi_4.value[0]?upper_case}
124#define SPC5_SPI_USE_DSPI5 ${conf.instance.dspi_settings.dspi_5.value[0]?upper_case}
125#define SPC5_SPI_USE_DSPI6 ${conf.instance.dspi_settings.dspi_6.value[0]?upper_case}
126#define SPC5_SPI_USE_DSPI7 ${conf.instance.dspi_settings.dspi_7.value[0]?upper_case}
127#define SPC5_SPI_DMA_MODE SPC5_SPI_DMA_${conf.instance.dspi_settings.dma_mode.value[0]?upper_case?replace(" ", "_")}
128[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs0[0].@index[0]?trim?number] /]
129[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs1[0].@index[0]?trim?number] /]
130[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs2[0].@index[0]?trim?number] /]
131[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs3[0].@index[0]?trim?number] /]
132[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs4[0].@index[0]?trim?number] /]
133[#assign s5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs5[0].@index[0]?trim?number] /]
134#define SPC5_SPI_DSPI0_MCR (0${s0 + s1 + s2 + s3 + s4 + s5})
135[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs0[0].@index[0]?trim?number] /]
136[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs1[0].@index[0]?trim?number] /]
137[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs2[0].@index[0]?trim?number] /]
138[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs3[0].@index[0]?trim?number] /]
139[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs4[0].@index[0]?trim?number] /]
140#define SPC5_SPI_DSPI1_MCR (0${s0 + s1 + s2 + s3 + s4})
141[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs0[0].@index[0]?trim?number] /]
142[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs1[0].@index[0]?trim?number] /]
143[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs2[0].@index[0]?trim?number] /]
144[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs3[0].@index[0]?trim?number] /]
145#define SPC5_SPI_DSPI2_MCR (0${s0 + s1 + s2 + s3})
146[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs0[0].@index[0]?trim?number] /]
147[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs1[0].@index[0]?trim?number] /]
148#define SPC5_SPI_DSPI3_MCR (0${s0 + s1})
149[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs0[0].@index[0]?trim?number] /]
150[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs1[0].@index[0]?trim?number] /]
151#define SPC5_SPI_DSPI4_MCR (0${s0 + s1})
152[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_5___pcs0[0].@index[0]?trim?number] /]
153[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_5___pcs1[0].@index[0]?trim?number] /]
154[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_5___pcs2[0].@index[0]?trim?number] /]
155#define SPC5_SPI_DSPI5_MCR (0${s0 + s1 + s2})
156[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_6___pcs0[0].@index[0]?trim?number] /]
157[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_6___pcs1[0].@index[0]?trim?number] /]
158[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_6___pcs2[0].@index[0]?trim?number] /]
159[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_6___pcs3[0].@index[0]?trim?number] /]
160#define SPC5_SPI_DSPI6_MCR (0${s0 + s1 + s2 + s3})
161[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_7___pcs0[0].@index[0]?trim?number] /]
162[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_7___pcs1[0].@index[0]?trim?number] /]
163[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_7___pcs2[0].@index[0]?trim?number] /]
164[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_7___pcs3[0].@index[0]?trim?number] /]
165#define SPC5_SPI_DSPI7_MCR (0${s0 + s1 + s2 + s3})
166#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx1.value[0]}
167#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx2.value[0]}
168#define SPC5_SPI_DSPI0_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_rx.value[0]}
169#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx1.value[0]}
170#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx2.value[0]}
171#define SPC5_SPI_DSPI1_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_rx.value[0]}
172#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_tx1.value[0]}
173#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_tx2.value[0]}
174#define SPC5_SPI_DSPI2_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_rx.value[0]}
175#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_tx1.value[0]}
176#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_tx2.value[0]}
177#define SPC5_SPI_DSPI3_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_rx.value[0]}
178#define SPC5_SPI_DSPI4_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_tx1.value[0]}
179#define SPC5_SPI_DSPI4_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_tx2.value[0]}
180#define SPC5_SPI_DSPI4_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_rx.value[0]}
181#define SPC5_SPI_DSPI5_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi5_tx1.value[0]}
182#define SPC5_SPI_DSPI5_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi5_tx2.value[0]}
183#define SPC5_SPI_DSPI5_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi5_rx.value[0]}
184#define SPC5_SPI_DSPI6_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi6_tx1.value[0]}
185#define SPC5_SPI_DSPI6_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi6_tx2.value[0]}
186#define SPC5_SPI_DSPI6_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi6_rx.value[0]}
187#define SPC5_SPI_DSPI7_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi7_tx1.value[0]}
188#define SPC5_SPI_DSPI7_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi7_tx2.value[0]}
189#define SPC5_SPI_DSPI7_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi7_rx.value[0]}
190#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
191#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
192#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_2.value[0]}
193#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_3.value[0]}
194#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_4.value[0]}
195#define SPC5_SPI_DSPI5_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_5.value[0]}
196#define SPC5_SPI_DSPI6_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_6.value[0]}
197#define SPC5_SPI_DSPI7_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_7.value[0]}
198#define SPC5_SPI_DSPI0_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
199#define SPC5_SPI_DSPI1_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
200#define SPC5_SPI_DSPI2_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_2.value[0]}
201#define SPC5_SPI_DSPI3_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_3.value[0]}
202#define SPC5_SPI_DSPI4_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_4.value[0]}
203#define SPC5_SPI_DSPI5_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_5.value[0]}
204#define SPC5_SPI_DSPI6_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_6.value[0]}
205#define SPC5_SPI_DSPI7_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_7.value[0]}
206#define SPC5_SPI_DMA_ERROR_HOOK(spip) ${conf.instance.dspi_settings.dma_error_hook.value[0]}
207
208/*
209 * ICU-PWM driver system settings.
210 */
211#define SPC5_ICU_USE_EMIOS0_CH0 ${conf.instance.emios_settings.emios0_ch0.value[0]?upper_case}
212#define SPC5_ICU_USE_EMIOS0_CH1 ${conf.instance.emios_settings.emios0_ch1.value[0]?upper_case}
213#define SPC5_ICU_USE_EMIOS0_CH2 ${conf.instance.emios_settings.emios0_ch2.value[0]?upper_case}
214#define SPC5_ICU_USE_EMIOS0_CH3 ${conf.instance.emios_settings.emios0_ch3.value[0]?upper_case}
215#define SPC5_ICU_USE_EMIOS0_CH4 ${conf.instance.emios_settings.emios0_ch4.value[0]?upper_case}
216#define SPC5_ICU_USE_EMIOS0_CH5 ${conf.instance.emios_settings.emios0_ch5.value[0]?upper_case}
217#define SPC5_ICU_USE_EMIOS0_CH6 ${conf.instance.emios_settings.emios0_ch6.value[0]?upper_case}
218#define SPC5_ICU_USE_EMIOS0_CH7 ${conf.instance.emios_settings.emios0_ch7.value[0]?upper_case}
219#define SPC5_ICU_USE_EMIOS0_CH24 ${conf.instance.emios_settings.emios0_ch24.value[0]?upper_case}
220
221#define SPC5_PWM_USE_EMIOS0_GROUP0 ${conf.instance.emios_settings.emios0_group0.value[0]?upper_case}
222#define SPC5_PWM_USE_EMIOS0_GROUP1 ${conf.instance.emios_settings.emios0_group1.value[0]?upper_case}
223
224#define SPC5_EMIOS0_GFR_F0F1_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc0.value[0]}
225#define SPC5_EMIOS0_GFR_F2F3_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc1.value[0]}
226#define SPC5_EMIOS0_GFR_F4F5_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc2.value[0]}
227#define SPC5_EMIOS0_GFR_F6F7_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc3.value[0]}
228#define SPC5_EMIOS0_GFR_F8F9_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc4.value[0]}
229#define SPC5_EMIOS0_GFR_F10F11_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc5.value[0]}
230#define SPC5_EMIOS0_GFR_F12F13_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc6.value[0]}
231#define SPC5_EMIOS0_GFR_F14F15_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc7.value[0]}
232#define SPC5_EMIOS0_GFR_F16F17_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc8.value[0]}
233#define SPC5_EMIOS0_GFR_F18F19_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc9.value[0]}
234#define SPC5_EMIOS0_GFR_F20F21_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc10.value[0]}
235#define SPC5_EMIOS0_GFR_F22F23_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc11.value[0]}
236#define SPC5_EMIOS0_GFR_F24F25_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc12.value[0]}
237
238#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
239 SPC5_ME_PCTL_LP(2))
240#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
241 SPC5_ME_PCTL_LP(0))
242
243#define SPC5_ICU_USE_EMIOS1_CH24 ${conf.instance.emios_settings.emios1_ch24.value[0]?upper_case}
244
245#define SPC5_PWM_USE_EMIOS1_GROUP0 ${conf.instance.emios_settings.emios1_group0.value[0]?upper_case}
246#define SPC5_PWM_USE_EMIOS1_GROUP1 ${conf.instance.emios_settings.emios1_group1.value[0]?upper_case}
247#define SPC5_PWM_USE_EMIOS1_GROUP2 ${conf.instance.emios_settings.emios1_group2.value[0]?upper_case}
248
249#define SPC5_EMIOS1_GFR_F0F1_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc0.value[0]}
250#define SPC5_EMIOS1_GFR_F2F3_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc1.value[0]}
251#define SPC5_EMIOS1_GFR_F4F5_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc2.value[0]}
252#define SPC5_EMIOS1_GFR_F6F7_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc3.value[0]}
253#define SPC5_EMIOS1_GFR_F8F9_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc4.value[0]}
254#define SPC5_EMIOS1_GFR_F10F11_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc5.value[0]}
255#define SPC5_EMIOS1_GFR_F12F13_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc6.value[0]}
256#define SPC5_EMIOS1_GFR_F14F15_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc7.value[0]}
257#define SPC5_EMIOS1_GFR_F16F17_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc8.value[0]}
258#define SPC5_EMIOS1_GFR_F18F19_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc9.value[0]}
259#define SPC5_EMIOS1_GFR_F20F21_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc10.value[0]}
260#define SPC5_EMIOS1_GFR_F22F23_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc11.value[0]}
261#define SPC5_EMIOS1_GFR_F24F25_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc12.value[0]}
262
263#define SPC5_EMIOS1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
264 SPC5_ME_PCTL_LP(2))
265#define SPC5_EMIOS1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
266 SPC5_ME_PCTL_LP(0))
267
268/*
269 * CAN driver system settings.
270 */
271#define SPC5_CAN_USE_FILTERS ${conf.instance.flexcan_settings.flexcan_enable_filters.value[0]?upper_case}
272
273#define SPC5_CAN_USE_FLEXCAN0 ${conf.instance.flexcan_settings.flexcan0.value[0]?upper_case}
274#define SPC5_CAN_FLEXCAN0_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan0_use_external_clock.value[0]?upper_case}
275#define SPC5_CAN_FLEXCAN0_PRIORITY ${conf.instance.irq_priority_settings.flexcan0.value[0]}
276#define SPC5_CAN_NUM_RX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_rx_mailboxes.value[0]}
277#define SPC5_CAN_NUM_TX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_tx_mailboxes.value[0]}
278#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
279 SPC5_ME_PCTL_LP(2))
280#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
281 SPC5_ME_PCTL_LP(0))
282
283#define SPC5_CAN_USE_FLEXCAN1 ${conf.instance.flexcan_settings.flexcan1.value[0]?upper_case}
284#define SPC5_CAN_FLEXCAN1_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan1_use_external_clock.value[0]?upper_case}
285#define SPC5_CAN_FLEXCAN1_PRIORITY ${conf.instance.irq_priority_settings.flexcan1.value[0]}
286#define SPC5_CAN_FLEXCAN1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
287 SPC5_ME_PCTL_LP(2))
288#define SPC5_CAN_FLEXCAN1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
289 SPC5_ME_PCTL_LP(0))
290
291#define SPC5_CAN_USE_FLEXCAN2 ${conf.instance.flexcan_settings.flexcan2.value[0]?upper_case}
292#define SPC5_CAN_FLEXCAN2_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan2_use_external_clock.value[0]?upper_case}
293#define SPC5_CAN_FLEXCAN2_PRIORITY ${conf.instance.irq_priority_settings.flexcan2.value[0]}
294#define SPC5_CAN_FLEXCAN2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
295 SPC5_ME_PCTL_LP(2))
296#define SPC5_CAN_FLEXCAN2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
297 SPC5_ME_PCTL_LP(0))
298
299#define SPC5_CAN_USE_FLEXCAN3 ${conf.instance.flexcan_settings.flexcan3.value[0]?upper_case}
300#define SPC5_CAN_FLEXCAN3_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan3_use_external_clock.value[0]?upper_case}
301#define SPC5_CAN_FLEXCAN3_PRIORITY ${conf.instance.irq_priority_settings.flexcan3.value[0]}
302#define SPC5_CAN_FLEXCAN3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
303 SPC5_ME_PCTL_LP(2))
304#define SPC5_CAN_FLEXCAN3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
305 SPC5_ME_PCTL_LP(0))
306
307#define SPC5_CAN_USE_FLEXCAN4 ${conf.instance.flexcan_settings.flexcan4.value[0]?upper_case}
308#define SPC5_CAN_FLEXCAN4_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan4_use_external_clock.value[0]?upper_case}
309#define SPC5_CAN_FLEXCAN4_PRIORITY ${conf.instance.irq_priority_settings.flexcan4.value[0]}
310#define SPC5_CAN_FLEXCAN4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
311 SPC5_ME_PCTL_LP(2))
312#define SPC5_CAN_FLEXCAN4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
313 SPC5_ME_PCTL_LP(0))
314
315#define SPC5_CAN_USE_FLEXCAN5 ${conf.instance.flexcan_settings.flexcan5.value[0]?upper_case}
316#define SPC5_CAN_FLEXCAN5_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan5_use_external_clock.value[0]?upper_case}
317#define SPC5_CAN_FLEXCAN5_PRIORITY ${conf.instance.irq_priority_settings.flexcan5.value[0]}
318#define SPC5_CAN_FLEXCAN5_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
319 SPC5_ME_PCTL_LP(2))
320#define SPC5_CAN_FLEXCAN5_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
321 SPC5_ME_PCTL_LP(0))
322
323/*
324* ADC driver system settings.
325*/
326[#if conf.instance.adc_settings.adc0_clock_divider.value[0] == "Peripheral clock frequency"]
327 [#assign clk_f0 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
328[#else]
329 [#assign clk_f0 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
330[/#if]
331
332[#if conf.instance.adc_settings.dma_mode.value[0] == "true" ]
333 [#assign dma_mode = "SPC5_ADC_DMA_ON"]
334[#else]
335 [#assign dma_mode = "SPC5_ADC_DMA_OFF"]
336[/#if]
337
338#define SPC5_ADC_DMA_MODE ${dma_mode}
339
340#define SPC5_ADC_USE_ADC0 ${conf.instance.adc_settings.adc0.value[0]?upper_case}
341#define SPC5_ADC_ADC0_CLK_FREQUENCY ${clk_f0}
342#define SPC5_ADC_ADC0_AUTO_CLOCK_OFF ${conf.instance.adc_settings.adc0_auto_clock_off_mode.value[0]?upper_case}
343#define SPC5_ADC_ADC0_WD_PRIORITY ${conf.instance.irq_priority_settings.adc0.value[0]}
344#define SPC5_ADC_ADC0_EOC_PRIORITY SPC5_ADC_ADC0_WD_PRIORITY
345#define SPC5_ADC_ADC0_DMA_CH_ID ${conf.instance.edma_mux_settings.adc_channels.adc0.value[0]}
346#define SPC5_ADC_ADC0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.adc0.value[0]}
347#define SPC5_ADC_ADC0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
348 SPC5_ME_PCTL_LP(2))
349#define SPC5_ADC_ADC0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
350 SPC5_ME_PCTL_LP(0))
351
352[#if conf.instance.adc_settings.adc1_clock_divider.value[0] == "Peripheral clock frequency"]
353 [#assign clk_f1 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
354[#else]
355 [#assign clk_f1 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
356[/#if]
357#define SPC5_ADC_USE_ADC1 ${conf.instance.adc_settings.adc1.value[0]?upper_case}
358#define SPC5_ADC_ADC1_CLK_FREQUENCY ${clk_f1}
359#define SPC5_ADC_ADC1_AUTO_CLOCK_OFF ${conf.instance.adc_settings.adc1_auto_clock_off_mode.value[0]?upper_case}
360#define SPC5_ADC_ADC1_WD_PRIORITY ${conf.instance.irq_priority_settings.adc1.value[0]}
361#define SPC5_ADC_ADC1_EOC_PRIORITY SPC5_ADC_ADC1_WD_PRIORITY
362#define SPC5_ADC_ADC1_DMA_CH_ID ${conf.instance.edma_mux_settings.adc_channels.adc1.value[0]}
363#define SPC5_ADC_ADC1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.adc1.value[0]}
364#define SPC5_ADC_ADC1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
365 SPC5_ME_PCTL_LP(2))
366#define SPC5_ADC_ADC1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
367 SPC5_ME_PCTL_LP(0))
368
369#endif /* _MCUCONF_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 14:05:02 +0100