aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios/os/hal/ports/SPC5/SPC56ECxx/xpc56ec.h
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios/os/hal/ports/SPC5/SPC56ECxx/xpc56ec.h')
-rw-r--r--lib/chibios/os/hal/ports/SPC5/SPC56ECxx/xpc56ec.h8475
1 files changed, 8475 insertions, 0 deletions
diff --git a/lib/chibios/os/hal/ports/SPC5/SPC56ECxx/xpc56ec.h b/lib/chibios/os/hal/ports/SPC5/SPC56ECxx/xpc56ec.h
new file mode 100644
index 000000000..7c7e6a68a
--- /dev/null
+++ b/lib/chibios/os/hal/ports/SPC5/SPC56ECxx/xpc56ec.h
@@ -0,0 +1,8475 @@
1/*****************************************************************
2 *
3 * FILE : MPC564xBC_V1.0.h
4 *
5 * DESCRIPTION : This is the header file describing the register
6 * set for the MPC564xB/C family of devices
7 *
8 * COPYRIGHT :(c) 2011, Freescale & STMicroelectronics
9 *
10 * VERSION : 1.0 (Based on RM Rev2 RC)
11 * DATE : April 2011
12 * AUTHOR : r19325
13 * HISTORY : Based on MPC5604B, MPC5607B and MPC5668
14 * 0.1 Jun10 : Initial release based on RM RevA, Ver 0.1
15 * 0.2 Jul10 : Corrections based on RM Rev1 Draft D
16 * 0.3 Feb11 : Corrections based on MPC5607B header and RM R2 DraftB
17 * 1.0 Mar11 : 1st official release based on RM Rev2 RC
18 *
19 *
20 * Implementation comments:
21 * -----------------------
22 *
23 * The header file does not include definitions for flexray as the
24 * expectation is that flexray will be used with drivers
25 *
26 * DSPI implementation supports master mode only
27 *
28 * The register protection registers are not included. These can
29 * be easily addressed using a macro to reference the existing
30 * registers which simplifies the protection process.
31 *
32 * Please report any comments or feedback via the "technical service
33 * request" tool listed under the support tab at www.freescale.com
34 *
35 *
36 *****************************************************************
37 * Copyright:
38 * Freescale Semiconductor, INC. All Rights Reserved.
39 * You are hereby granted a copyright license to use, modify, and
40 * distribute the SOFTWARE so long as this entire notice is
41 * retained without alteration in any modified and/or redistributed
42 * versions, and that such modified versions are clearly identified
43 * as such. No licenses are granted by implication, estoppel or
44 * otherwise under any patents or trademarks of Freescale
45 * Semiconductor, Inc. This software is provided on an "AS IS"
46 * basis and without warranty.
47 *
48 * To the maximum extent permitted by applicable law, Freescale
49 * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
50 * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
51 * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
52 * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
53 * AND ANY ACCOMPANYING WRITTEN MATERIALS.
54 *
55 * To the maximum extent permitted by applicable law, IN NO EVENT
56 * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
57 * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
58 * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
59 * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
60 *
61 * Freescale Semiconductor assumes no responsibility for the
62 * maintenance and support of this software
63 *
64 ******************************************************************/
65
66/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
67
68/*****************************************************************
69* Example instantiation and use:
70*
71* <MODULE>.<REGISTER>.B.<BIT> = 1;
72* <MODULE>.<REGISTER>.R = 0x10000000;
73*
74******************************************************************/
75
76#ifndef _MPC5646x_H_
77#define _MPC5646x_H_
78
79#include "typedefs.h"
80
81#ifdef __cplusplus
82extern "C" {
83#endif
84
85#ifdef __MWERKS__
86#pragma push
87#pragma ANSI_strict off
88#endif
89/****************************************************************************/
90/* MODULE : CFLASH */
91/****************************************************************************/
92struct CFLASH_tag {
93
94 union { /* Module Configuration (Base+0x0000) */
95 vuint32_t R;
96 struct {
97 vuint32_t EDC:1;
98 vuint32_t :4;
99 vuint32_t SIZE:3;
100 vuint32_t :1;
101 vuint32_t LAS:3;
102 vuint32_t :3;
103 vuint32_t MAS:1;
104 vuint32_t EER:1;
105 vuint32_t RWE:1;
106 vuint32_t :2;
107 vuint32_t PEAS:1;
108 vuint32_t DONE:1;
109 vuint32_t PEG:1;
110 vuint32_t :4;
111 vuint32_t PGM:1;
112 vuint32_t PSUS:1;
113 vuint32_t ERS:1;
114 vuint32_t ESUS:1;
115 vuint32_t EHV:1;
116 } B;
117 } MCR;
118
119 union { /* Low/Mid address block locking (Base+0x0004) */
120 vuint32_t R;
121 struct {
122 vuint32_t LME:1;
123 vuint32_t :10;
124 vuint32_t TSLK:1;
125 vuint32_t :2;
126 vuint32_t MLK:2;
127 vuint32_t LLK:16;
128 } B;
129 } LML;
130
131 union { /* High address space block locking (Base+0x0008)*/
132 vuint32_t R;
133 struct {
134 vuint32_t HBE:1;
135 vuint32_t :19;
136 vuint32_t HLK:12;
137 } B;
138 } HBL;
139
140 union { /* Secondary Low/Mid block lock (Base+0x000C)*/
141 vuint32_t R;
142 struct {
143 vuint32_t SLE:1;
144 vuint32_t :10;
145 vuint32_t STSLK:1;
146 vuint32_t :2;
147 vuint32_t SMK:2;
148 vuint32_t SLK:16;
149 } B;
150 } SLL;
151
152 union { /* Low/Mid address space block sel (Base+0x0010)*/
153 vuint32_t R;
154 struct {
155 vuint32_t:14;
156 vuint32_t MSL:2;
157 vuint32_t LSL:16;
158 } B;
159 } LMS;
160
161 union { /* High address Space block select (Base+0x0014)*/
162 vuint32_t R;
163 struct {
164 vuint32_t :20;
165 vuint32_t HSL:12;
166 } B;
167 } HBS;
168
169 union { /* Address (Base+0x0018) */
170 vuint32_t R; /* Can't put ADD in array as it runs [3..22] */
171 struct {
172 vuint32_t :9;
173 vuint32_t ADD:20;
174 vuint32_t :3;
175 } B;
176 } ADR;
177
178
179 /* Note the following 3 registers, BIU[0..2] are mirrored to */
180 /* the code flash configuraiton PFCR[0..2] registers */
181 /* To make it easier to code, the BIU registers have been */
182 /* replaced with the PFCR registers in this header file! */
183 /* A commented out BIU register is shown for reference! */
184
185
186 union { /* CFLASH Configuration 0 (Base+0x001C) */
187 vuint32_t R;
188 struct {
189 vuint32_t B02_APC:5;
190 vuint32_t :5; /* vuint32_t B02_WWSC:5; (removed RevD) */
191 vuint32_t B02_RWSC:5;
192 vuint32_t B02_RWWC2:1;
193 vuint32_t B02_RWWC1:1;
194 vuint32_t B02_P1_BCFG:2;
195 vuint32_t B02_P1_DPFE:1;
196 vuint32_t B02_P1_IPFE:1;
197 vuint32_t B02_P1_PFLM:2;
198 vuint32_t B02_P1_BFE:1;
199 vuint32_t B02_RWWC0:1;
200 vuint32_t B02_P0_BCFG:2;
201 vuint32_t B02_P0_DPFE:1;
202 vuint32_t B02_P0_IPFE:1;
203 vuint32_t B02_P0_PFLM:2;
204 vuint32_t B02_P0_BFE:1;
205 } B;
206 } PFCR0;
207 /* Commented out Bus Interface Unit 0 (Base+0x001C) */
208 /*union {
209
210 vuint32_t R;
211
212 struct {
213
214 vuint32_t BI0:32;
215
216 } B;
217
218 } BIU0; */
219 union { /* CFLASH Configuration 1 (Base+0x0020) */
220 vuint32_t R;
221 struct {
222 vuint32_t B1_APC:5;
223 vuint32_t B1_WWSC:5;
224 vuint32_t B1_RWSC:5;
225 vuint32_t B1_RWWC2:1;
226 vuint32_t B1_RWWC1:1;
227 vuint32_t :6;
228 vuint32_t B1_P1_BFE:1;
229 vuint32_t B1_RWWC0:1;
230 vuint32_t :6;
231 vuint32_t B1_P0_BFE:1;
232 } B;
233 } PFCR1;
234 /* Commented out Bus Interface Unit 1 (Base+0x0020) */
235 /*union {
236
237 vuint32_t R;
238
239 struct {
240
241 vuint32_t BI1:32;
242
243 } B;
244
245 } BIU1; */
246 union { /* CFLASH Access Protection (Base+0x0024) */
247 vuint32_t R;
248 struct {
249 vuint32_t :6;
250 vuint32_t ARBM:2;
251 vuint32_t M7PFD:1;
252 vuint32_t M6PFD:1;
253 vuint32_t M5PFD:1;
254 vuint32_t M4PFD:1;
255 vuint32_t M3PFD:1;
256 vuint32_t M2PFD:1;
257 vuint32_t M1PFD:1;
258 vuint32_t M0PFD:1;
259 vuint32_t M7AP:2;
260 vuint32_t M6AP:2;
261 vuint32_t M5AP:2;
262 vuint32_t M4AP:2;
263 vuint32_t M3AP:2;
264 vuint32_t M2AP:2;
265 vuint32_t M1AP:2;
266 vuint32_t M0AP:2;
267 } B;
268 } PFAPR;
269 /* Commented out Bus Interface Unit 2 (Base+0x0024) */
270 /*union {
271
272 vuint32_t R;
273
274 struct {
275
276 vuint32_t BI2:32;
277
278 } B;
279
280 } BIU2; */
281 vuint8_t CFLASH_reserved0[20]; /* Reserved 20 Bytes (Base+0x0028-0x003B) */
282
283 union { /* User Test 0 (Base+0x003C) */
284 vuint32_t R;
285 struct {
286 vuint32_t UTE:1;
287 vuint32_t :7;
288 vuint32_t DSI:8;
289 vuint32_t :10;
290 vuint32_t MRE:1;
291 vuint32_t MRV:1;
292 vuint32_t EIE:1;
293 vuint32_t AIS:1;
294 vuint32_t AIE:1;
295 vuint32_t AID:1;
296 } B;
297 } UT0;
298
299 union { /* User Test 1 (Base+0x0040) */
300 vuint32_t R;
301 struct {
302 vuint32_t DAI:32;
303 } B;
304 } UT1;
305
306 union { /* User Test 2 (Base+0x0044) */
307 vuint32_t R;
308 struct {
309 vuint32_t DAI:32;
310 } B;
311 } UT2;
312
313 union { /* User Multiple Input Sig 0..4 (Base+0x0048-0x005B) */
314 vuint32_t R;
315 struct {
316 vuint32_t MS:32;
317 } B;
318 } UMISR[5];
319
320 vuint8_t CFLASH_reserved1[16292]; /* Reserved 16292 (Base+0x005C-0x3FFF)*/
321
322}; /* end of CFLASH_tag */
323/****************************************************************************/
324/* MODULE : DFLASH */
325/****************************************************************************/
326struct DFLASH_tag {
327
328 union { /* Module Configuration (Base+0x0000) */
329 vuint32_t R;
330 struct {
331 vuint32_t EDC:1;
332 vuint32_t :4;
333 vuint32_t SIZE:3;
334 vuint32_t :1;
335 vuint32_t LAS:3;
336 vuint32_t :1;
337 vuint32_t MAS:3;
338 vuint32_t EER:1;
339 vuint32_t RWE:1;
340 vuint32_t :2;
341 vuint32_t PEAS:1;
342 vuint32_t DONE:1;
343 vuint32_t PEG:1;
344 vuint32_t :4;
345 vuint32_t PGM:1;
346 vuint32_t PSUS:1;
347 vuint32_t ERS:1;
348 vuint32_t ESUS:1;
349 vuint32_t EHV:1;
350 } B;
351 } MCR;
352
353 union { /* Low/Mid address block locking (Base+0x0004) */
354 vuint32_t R;
355 struct {
356 vuint32_t LME:1;
357 vuint32_t :10;
358 vuint32_t TSLK:1;
359 vuint32_t :16;
360 vuint32_t LLK:4;
361 } B;
362 } LML;
363
364 vuint8_t DFLASH_reserved0[4]; /* Reserved 4 Bytes (+0x0008-0x000B) */
365
366 union { /* Secondary Low/mid block locking (Base+0x000C)*/
367 vuint32_t R;
368 struct {
369 vuint32_t SLE:1;
370 vuint32_t :10;
371 vuint32_t STSLK:1;
372 vuint32_t :16;
373 vuint32_t SLK:4;
374 } B;
375 } SLL;
376
377 union { /* Low/Mid address space block sel (Base+0x0010)*/
378 vuint32_t R;
379 struct {
380 vuint32_t:28;
381 vuint32_t LSL:4;
382 } B;
383 } LMS;
384
385 vuint8_t DFLASH_reserved1[4]; /* Reserved 4 Bytes (+0x0014-0x0017) */
386
387 union { /* Address (Base+0x0018) */
388 vuint32_t R; /* Can't put ADD in array as it runs [2..22] */
389 struct {
390 vuint32_t :9;
391 vuint32_t ADD:21;
392 vuint32_t :2;
393 } B;
394 } ADR;
395
396 vuint8_t DFLASH_reserved2[32]; /* Reserved 32 Bytes (+0x001C-0x003B) */
397
398 union { /* User Test 0 (Base+0x003C) */
399 vuint32_t R;
400 struct {
401 vuint32_t UTE:1;
402 vuint32_t :8;
403 vuint32_t DSI:7;
404 vuint32_t :10;
405 vuint32_t MRE:1;
406 vuint32_t MRV:1;
407 vuint32_t EIE:1;
408 vuint32_t AIS:1;
409 vuint32_t AIE:1;
410 vuint32_t AID:1;
411 } B;
412 } UT0;
413
414 union { /* User Test 1 (Base+0x0040) */
415 vuint32_t R;
416 struct {
417 vuint32_t DAI:32;
418 } B;
419 } UT1;
420
421 vuint8_t DFLASH_reserved3[4]; /* Reserved 4 Bytes (+0x0044-0x0047) */
422
423 union { /* User Multiple Input sig 0..1 (+0x0048-0x004F)*/
424 vuint32_t R;
425 struct {
426 vuint32_t MS:32;
427 } B;
428 } UMISR[2];
429
430}; /* end of DFLASH_tag */
431/****************************************************************************/
432/* MODULE : SIU Lite (tagged as SIU for compatibility) */
433/****************************************************************************/
434struct SIU_tag {
435
436 vuint8_t SIU_reserved0[4]; /* Reserved 4 Bytes (Base+0x0) */
437
438 union { /* MCU ID1 (Base+0x0004) */
439 vuint32_t R;
440 struct {
441 vuint32_t PARTNUM:16;
442 vuint32_t CSP:1;
443 vuint32_t PKG:5;
444 vuint32_t :2;
445 vuint32_t MAJOR_MASK:4;
446 vuint32_t MINOR_MASK:4;
447 } B;
448 } MIDR1;
449
450 union { /* MCU ID2 (Base+0x0008) */
451 vuint32_t R;
452 struct {
453 vuint32_t SF:1;
454 vuint32_t FLASH_SIZE_1:4;
455 vuint32_t FLASH_SIZE_2:4;
456 vuint32_t :7;
457 vuint32_t PARTNUM:8;
458 vuint32_t :3;
459 vuint32_t EE:1;
460 vuint32_t :3;
461 vuint32_t FR:1;
462 } B;
463 } MIDR2;
464
465 vuint8_t SIU_reserved1[8]; /* Reserved 8 Bytes (Base+(0x000C--0x0013)) */
466
467 union { /* Interrupt Status Flag (Base+0x0014)*/
468 vuint32_t R;
469 struct {
470 vuint32_t :8;
471 vuint32_t EIF23:1;
472 vuint32_t EIF22:1;
473 vuint32_t EIF21:1;
474 vuint32_t EIF20:1;
475 vuint32_t EIF19:1;
476 vuint32_t EIF18:1;
477 vuint32_t EIF17:1;
478 vuint32_t EIF16:1;
479 vuint32_t EIF15:1;
480 vuint32_t EIF14:1;
481 vuint32_t EIF13:1;
482 vuint32_t EIF12:1;
483 vuint32_t EIF11:1;
484 vuint32_t EIF10:1;
485 vuint32_t EIF9:1;
486 vuint32_t EIF8:1;
487 vuint32_t EIF7:1;
488 vuint32_t EIF6:1;
489 vuint32_t EIF5:1;
490 vuint32_t EIF4:1;
491 vuint32_t EIF3:1;
492 vuint32_t EIF2:1;
493 vuint32_t EIF1:1;
494 vuint32_t EIF0:1;
495 } B;
496 } ISR;
497
498 union { /* Interrupt Request Enable (Base+0x0018) */
499 vuint32_t R;
500 struct {
501 vuint32_t :8;
502 vuint32_t EIRE23:1;
503 vuint32_t EIRE22:1;
504 vuint32_t EIRE21:1;
505 vuint32_t EIRE20:1;
506 vuint32_t EIRE19:1;
507 vuint32_t EIRE18:1;
508 vuint32_t EIRE17:1;
509 vuint32_t EIRE16:1;
510 vuint32_t EIRE15:1;
511 vuint32_t EIRE14:1;
512 vuint32_t EIRE13:1;
513 vuint32_t EIRE12:1;
514 vuint32_t EIRE11:1;
515 vuint32_t EIRE10:1;
516 vuint32_t EIRE9:1;
517 vuint32_t EIRE8:1;
518 vuint32_t EIRE7:1;
519 vuint32_t EIRE6:1;
520 vuint32_t EIRE5:1;
521 vuint32_t EIRE4:1;
522 vuint32_t EIRE3:1;
523 vuint32_t EIRE2:1;
524 vuint32_t EIRE1:1;
525 vuint32_t EIRE0:1;
526 } B;
527 } IRER;
528
529 vuint8_t SIU_reserved2[12]; /* Reserved 12 Bytes (Base+0x001C-0x0027) */
530
531 union { /* Interrupt Rising-Edge Event Enable (+0x0028) */
532 vuint32_t R;
533 struct {
534 vuint32_t :8;
535 vuint32_t IREE23:1;
536 vuint32_t IREE22:1;
537 vuint32_t IREE21:1;
538 vuint32_t IREE20:1;
539 vuint32_t IREE19:1;
540 vuint32_t IREE18:1;
541 vuint32_t IREE17:1;
542 vuint32_t IREE16:1;
543 vuint32_t IREE15:1;
544 vuint32_t IREE14:1;
545 vuint32_t IREE13:1;
546 vuint32_t IREE12:1;
547 vuint32_t IREE11:1;
548 vuint32_t IREE10:1;
549 vuint32_t IREE9:1;
550 vuint32_t IREE8:1;
551 vuint32_t IREE7:1;
552 vuint32_t IREE6:1;
553 vuint32_t IREE5:1;
554 vuint32_t IREE4:1;
555 vuint32_t IREE3:1;
556 vuint32_t IREE2:1;
557 vuint32_t IREE1:1;
558 vuint32_t IREE0:1;
559 } B;
560 } IREER;
561
562 union { /* Interrupt Falling-Edge Event Enable (+0x002C)*/
563 vuint32_t R;
564 struct {
565 vuint32_t :8;
566 vuint32_t IFEE23:1;
567 vuint32_t IFEE22:1;
568 vuint32_t IFEE21:1;
569 vuint32_t IFEE20:1;
570 vuint32_t IFEE19:1;
571 vuint32_t IFEE18:1;
572 vuint32_t IFEE17:1;
573 vuint32_t IFEE16:1;
574 vuint32_t IFEE15:1;
575 vuint32_t IFEE14:1;
576 vuint32_t IFEE13:1;
577 vuint32_t IFEE12:1;
578 vuint32_t IFEE11:1;
579 vuint32_t IFEE10:1;
580 vuint32_t IFEE9:1;
581 vuint32_t IFEE8:1;
582 vuint32_t IFEE7:1;
583 vuint32_t IFEE6:1;
584 vuint32_t IFEE5:1;
585 vuint32_t IFEE4:1;
586 vuint32_t IFEE3:1;
587 vuint32_t IFEE2:1;
588 vuint32_t IFEE1:1;
589 vuint32_t IFEE0:1;
590 } B;
591 } IFEER;
592
593 union { /* Interrupt Filter Enable (Base+0x0030) */
594 vuint32_t R;
595 struct {
596 vuint32_t :8;
597 vuint32_t IFE23:1;
598 vuint32_t IFE22:1;
599 vuint32_t IFE21:1;
600 vuint32_t IFE20:1;
601 vuint32_t IFE19:1;
602 vuint32_t IFE18:1;
603 vuint32_t IFE17:1;
604 vuint32_t IFE16:1;
605 vuint32_t IFE15:1;
606 vuint32_t IFE14:1;
607 vuint32_t IFE13:1;
608 vuint32_t IFE12:1;
609 vuint32_t IFE11:1;
610 vuint32_t IFE10:1;
611 vuint32_t IFE9:1;
612 vuint32_t IFE8:1;
613 vuint32_t IFE7:1;
614 vuint32_t IFE6:1;
615 vuint32_t IFE5:1;
616 vuint32_t IFE4:1;
617 vuint32_t IFE3:1;
618 vuint32_t IFE2:1;
619 vuint32_t IFE1:1;
620 vuint32_t IFE0:1;
621 } B;
622 } IFER;
623
624 vuint8_t SIU_reserved3[12]; /* Reserved 12 Bytes (Base+0x0034-0x003F) */
625
626 union { /* Pad Configuration 0..198 (Base+0x0040-0x01CD)*/
627 vuint16_t R;
628 struct {
629 vuint16_t :1;
630 vuint16_t SMC:1;
631 vuint16_t APC:1;
632 vuint16_t PA:3;
633 vuint16_t OBE:1;
634 vuint16_t IBE:1;
635 vuint16_t :2; /* vuint16_t DSC:2; */
636 vuint16_t ODE:1;
637 vuint16_t :2; /* vuint16_t HYS:1; */
638 vuint16_t SRC:1;
639 vuint16_t WPE:1;
640 vuint16_t WPS:1;
641 } B;
642 } PCR[199];
643
644 vuint8_t SIU_reserved4[818]; /*Reserved 818 Bytes (Base+0x01CE-0x04FF) */
645
646 union { /* Pad Selection for Mux Input (0x0500-0x543) */
647 vuint8_t R;
648 struct {
649 vuint8_t :4;
650 vuint8_t PADSEL:4;
651 } B;
652 } PSMI[68];
653
654 vuint8_t SIU_reserved5[188]; /*Reserved 188 Bytes (Base+0x0544-0x05FF) */
655
656 union { /* GPIO Pad Data Output (Base+0x0600-0x06C7) */
657 vuint8_t R;
658 struct {
659 vuint8_t :7;
660 vuint8_t PDO:1;
661 } B;
662 } GPDO[200];
663
664 vuint8_t SIU_reserved6[312]; /*Reserved 312 Bytes (Base+0x06C8-0x07FF) */
665
666 union { /* GPIO Pad Data Input (Base+0x0800-0x08C7) */
667 vuint8_t R;
668 struct {
669 vuint8_t :7;
670 vuint8_t PDI:1;
671 } B;
672 } GPDI[200];
673
674 vuint8_t SIU_reserved7[824]; /*Reserved 824 Bytes (Base+0x08C8-0x0BFF) */
675
676 union { /* Parallel GPIO Pad Data Out 0-6 (0x0C00-0xC018) */
677 vuint32_t R;
678 struct {
679 vuint32_t PPDO:32;
680 } B;
681 } PGPDO[7];
682
683 vuint8_t SIU_reserved8[36]; /* Reserved 36 Bytes (Base+0x0C1C-0x0C3F) */
684
685 union { /* Parallel GPIO Pad Data In 0-6 (0x0C40-0x0C58) */
686 vuint32_t R;
687 struct {
688 vuint32_t PPDI:32;
689 } B;
690 } PGPDI[7];
691
692 vuint8_t SIU_reserved9[36]; /* Reserved 36 Bytes (Base+0x0C5C-0x0C7F) */
693
694 union { /* Masked Parallel GPIO Pad Data Out 0-12 (0x0C80-0x0CB0) */
695 vuint32_t R;
696 struct {
697 vuint32_t MASK:16;
698 vuint32_t MPPDO:16;
699 } B;
700 } MPGPDO[13];
701
702 vuint8_t SIU_reserved10[844]; /*Reserved 844 Bytes (Base+0x0CB4-0x0FFF)*/
703
704 union { /* Interrupt Filter Max Counter 0..23 (+0x1000-0x105C) */
705 vuint32_t R;
706 struct {
707 vuint32_t :28;
708 vuint32_t MAXCNT:4;
709 } B;
710 } IFMC[24];
711
712 vuint8_t SIU_reserved11[32]; /* Reserved 32 Bytes (Base+0x1060-0x107F) */
713
714 union { /* Interrupt Filter Clock Prescaler (Base+0x1080) */
715 vuint32_t R;
716 struct {
717 vuint32_t :28;
718 vuint32_t IFCP:4;
719 } B;
720 } IFCPR;
721
722 vuint8_t SIU_reserved12[124]; /* Reserved 124 Bytes (+0x1084-0x10FF) */
723
724
725 /* PISR group 1 (eMIOS 0 to DSPI 0) */
726
727 union { /* Parallel Input Select 0 (Base+0x1100) */
728 vuint32_t R;
729 struct {
730 vuint32_t IPS0:4;
731 vuint32_t IPS1:4;
732 vuint32_t IPS2:4;
733 vuint32_t IPS3:4;
734 vuint32_t IPS4:4;
735 vuint32_t IPS5:4;
736 vuint32_t IPS6:4;
737 vuint32_t IPS7:4;
738 } B;
739 } PISR0;
740
741 union { /* Parallel Input Select 1 (Base+0x1104) */
742 vuint32_t R;
743 struct {
744 vuint32_t IPS8:4;
745 vuint32_t IPS9:4;
746 vuint32_t IPS10:4;
747 vuint32_t IPS11:4;
748 vuint32_t IPS12:4;
749 vuint32_t IPS13:4;
750 vuint32_t IPS14:4;
751 vuint32_t IPS15:4;
752 } B;
753 } PISR1;
754
755 union { /* Parallel Input Select 2 (Base+0x1108) */
756 vuint32_t R;
757 struct {
758 vuint32_t IPS16:4;
759 vuint32_t IPS17:4;
760 vuint32_t IPS18:4;
761 vuint32_t IPS19:4;
762 vuint32_t IPS20:4;
763 vuint32_t IPS21:4;
764 vuint32_t IPS22:4;
765 vuint32_t IPS23:4;
766 } B;
767 } PISR2;
768
769 union { /* Parallel Input Select 3 (Base+0x110C) */
770 vuint32_t R;
771 struct {
772 vuint32_t IPS24:4;
773 vuint32_t IPS25:4;
774 vuint32_t IPS26:4;
775 vuint32_t IPS27:4;
776 vuint32_t IPS28:4;
777 vuint32_t IPS29:4;
778 vuint32_t IPS30:4;
779 vuint32_t IPS31:4;
780 } B;
781 } PISR3;
782
783 /* PISR group 2 (eMIOS 1 to DSPI 1) */
784
785 union { /* Parallel Input Select 4 (Base+0x1110) */
786 vuint32_t R;
787 struct {
788 vuint32_t IPS0:4;
789 vuint32_t IPS1:4;
790 vuint32_t IPS2:4;
791 vuint32_t IPS3:4;
792 vuint32_t IPS4:4;
793 vuint32_t IPS5:4;
794 vuint32_t IPS6:4;
795 vuint32_t IPS7:4;
796 } B;
797 } PISR4;
798
799 union { /* Parallel Input Select 5 (Base+0x1114) */
800 vuint32_t R;
801 struct {
802 vuint32_t IPS8:4;
803 vuint32_t IPS9:4;
804 vuint32_t IPS10:4;
805 vuint32_t IPS11:4;
806 vuint32_t IPS12:4;
807 vuint32_t IPS13:4;
808 vuint32_t IPS14:4;
809 vuint32_t IPS15:4;
810 } B;
811 } PISR5;
812
813 union { /* Parallel Input Select 6 (Base+0x1118) */
814 vuint32_t R;
815 struct {
816 vuint32_t IPS16:4;
817 vuint32_t IPS17:4;
818 vuint32_t IPS18:4;
819 vuint32_t IPS19:4;
820 vuint32_t IPS20:4;
821 vuint32_t IPS21:4;
822 vuint32_t IPS22:4;
823 vuint32_t IPS23:4;
824 } B;
825 } PISR6;
826
827 union { /* Parallel Input Select 7 (Base+0x111C) */
828 vuint32_t R;
829 struct {
830 vuint32_t IPS24:4;
831 vuint32_t IPS25:4;
832 vuint32_t IPS26:4;
833 vuint32_t IPS27:4;
834 vuint32_t IPS28:4;
835 vuint32_t IPS29:4;
836 vuint32_t IPS30:4;
837 vuint32_t IPS31:4;
838 } B;
839 } PISR7;
840
841 /* PISR group 3 (eMIOS 0 to DSPI 3) */
842
843 union { /* Parallel Input Select 8 (Base+0x1120) */
844 vuint32_t R;
845 struct {
846 vuint32_t IPS0:4;
847 vuint32_t IPS1:4;
848 vuint32_t IPS2:4;
849 vuint32_t IPS3:4;
850 vuint32_t IPS4:4;
851 vuint32_t IPS5:4;
852 vuint32_t IPS6:4;
853 vuint32_t IPS7:4;
854 } B;
855 } PISR8;
856
857 union { /* Parallel Input Select 9 (Base+0x1124) */
858 vuint32_t R;
859 struct {
860 vuint32_t IPS8:4;
861 vuint32_t IPS9:4;
862 vuint32_t IPS10:4;
863 vuint32_t IPS11:4;
864 vuint32_t IPS12:4;
865 vuint32_t IPS13:4;
866 vuint32_t IPS14:4;
867 vuint32_t IPS15:4;
868 } B;
869 } PISR9;
870
871 union { /* Parallel Input Select 10 (Base+0x1128) */
872 vuint32_t R;
873 struct {
874 vuint32_t IPS16:4;
875 vuint32_t IPS17:4;
876 vuint32_t IPS18:4;
877 vuint32_t IPS19:4;
878 vuint32_t IPS20:4;
879 vuint32_t IPS21:4;
880 vuint32_t IPS22:4;
881 vuint32_t IPS23:4;
882 } B;
883 } PISR10;
884
885 union { /* Parallel Input Select 11 (Base+0x112C) */
886 vuint32_t R;
887 struct {
888 vuint32_t IPS24:4;
889 vuint32_t IPS25:4;
890 vuint32_t IPS26:4;
891 vuint32_t IPS27:4;
892 vuint32_t IPS28:4;
893 vuint32_t IPS29:4;
894 vuint32_t IPS30:4;
895 vuint32_t IPS31:4;
896 } B;
897 } PISR11;
898
899 /* PISR group 4 (eMIOS 1 to DSPI 4) */
900
901 union { /* Parallel Input Select 12 (Base+0x1130) */
902 vuint32_t R;
903 struct {
904 vuint32_t IPS0:4;
905 vuint32_t IPS1:4;
906 vuint32_t IPS2:4;
907 vuint32_t IPS3:4;
908 vuint32_t IPS4:4;
909 vuint32_t IPS5:4;
910 vuint32_t IPS6:4;
911 vuint32_t IPS7:4;
912 } B;
913 } PISR12;
914
915 union { /* Parallel Input Select 13 (Base+0x1134) */
916 vuint32_t R;
917 struct {
918 vuint32_t IPS8:4;
919 vuint32_t IPS9:4;
920 vuint32_t IPS10:4;
921 vuint32_t IPS11:4;
922 vuint32_t IPS12:4;
923 vuint32_t IPS13:4;
924 vuint32_t IPS14:4;
925 vuint32_t IPS15:4;
926 } B;
927 } PISR13;
928
929 union { /* Parallel Input Select 14 (Base+0x1138) */
930 vuint32_t R;
931 struct {
932 vuint32_t IPS16:4;
933 vuint32_t IPS17:4;
934 vuint32_t IPS18:4;
935 vuint32_t IPS19:4;
936 vuint32_t IPS20:4;
937 vuint32_t IPS21:4;
938 vuint32_t IPS22:4;
939 vuint32_t IPS23:4;
940 } B;
941 } PISR14;
942
943 union { /* Parallel Input Select 15 (Base+0x113C) */
944 vuint32_t R;
945 struct {
946 vuint32_t IPS24:4;
947 vuint32_t IPS25:4;
948 vuint32_t IPS26:4;
949 vuint32_t IPS27:4;
950 vuint32_t IPS28:4;
951 vuint32_t IPS29:4;
952 vuint32_t IPS30:4;
953 vuint32_t IPS31:4;
954 } B;
955 } PISR15;
956
957
958 vuint8_t SIU_reserved13[192]; /*Reserved 192 Bytes (Base+0x1140-0x11FF)*/
959
960 union { /* DSPI Input Select (Base+0x1200) */
961 vuint32_t R;
962 struct {
963 vuint32_t SINSEL0:2;
964 vuint32_t SSSSEL0:2;
965 vuint32_t SCKSEL0:2;
966 vuint32_t TRIGSEL0:2;
967 vuint32_t SINSEL1:2;
968 vuint32_t SSSSEL1:2;
969 vuint32_t SCKSEL1:2;
970 vuint32_t TRIGSEL1:2;
971 vuint32_t SINSEL2:2;
972 vuint32_t SSSSEL2:2;
973 vuint32_t SCKSEL2:2;
974 vuint32_t TRIGSEL2:2;
975 vuint32_t SINSEL3:2;
976 vuint32_t SSSSEL3:2;
977 vuint32_t SCKSEL3:2;
978 vuint32_t TRIGSEL3:2;
979 } B;
980 } DISR;
981
982}; /* end of SIU_tag */
983/****************************************************************************/
984/* MODULE : WKUP */
985/****************************************************************************/
986struct WKUP_tag{
987
988 union { /* NMI Status Flag (Base+0x0000) */
989 vuint32_t R;
990 struct {
991 vuint32_t NIF0:1;
992 vuint32_t NOVF0:1;
993 vuint32_t :6;
994 vuint32_t NIF1:1;
995 vuint32_t NOVF1:1;
996 vuint32_t :22;
997 } B;
998 } NSR;
999
1000 vuint8_t WKUP_reserved0[4]; /* Reserved 4 Bytes (Base+0x0004-0x0007) */
1001
1002 union { /* NMI Configuration (Base+0x0008) */
1003 vuint32_t R;
1004 struct {
1005 vuint32_t NLOCK0:1;
1006 vuint32_t NDSS0:2;
1007 vuint32_t NWRE0:1;
1008 vuint32_t :1;
1009 vuint32_t NREE0:1;
1010 vuint32_t NFEE0:1;
1011 vuint32_t NFE0:1;
1012 vuint32_t NLOCK1:1;
1013 vuint32_t NDSS1:2;
1014 vuint32_t NWRE1:1;
1015 vuint32_t :1;
1016 vuint32_t NREE1:1;
1017 vuint32_t NFEE1:1;
1018 vuint32_t NFE1:1;
1019 vuint32_t :16;
1020 } B;
1021 } NCR;
1022
1023 vuint8_t WKUP_reserved1[8]; /* Reserved 8 Bytes (Base+0x000C-0x0013) */
1024
1025 union { /* Wakeup/Interrup status flag (Base+0x0014) */
1026 vuint32_t R;
1027 struct {
1028 vuint32_t EIF:32;
1029 } B;
1030 } WISR;
1031
1032 union { /* Interrupt Request Enable (Base+0x0018) */
1033 vuint32_t R;
1034 struct {
1035 vuint32_t EIRE:32;
1036 } B;
1037 } IRER;
1038
1039 union { /* Wakeup Request Enable (Base+0x001C) */
1040 vuint32_t R;
1041 struct {
1042 vuint32_t WRE:32;
1043 } B;
1044 } WRER;
1045
1046 vuint8_t WKUP_reserved2[8]; /* Reserved 8 Bytes (Base+0x0020-0x0027) */
1047
1048 union { /* Wakeup/Interrupt Rising-Edge (Base+0x0028) */
1049 vuint32_t R;
1050 struct {
1051 vuint32_t IREE:32;
1052 } B;
1053 } WIREER;
1054
1055 union { /* Wakeup/Interrupt Falling-Edge (Base+0x002C) */
1056 vuint32_t R;
1057 struct {
1058 vuint32_t IFEE:32;
1059 } B;
1060 } WIFEER;
1061
1062 union { /* Wakeup/Interrupt Filter Enable (Base+0x0030) */
1063 vuint32_t R;
1064 struct {
1065 vuint32_t IFE:32;
1066 } B;
1067 } WIFER;
1068
1069 union { /* Wakeup/Interrupt Pullup Enable (Base+0x0034) */
1070 vuint32_t R;
1071 struct {
1072 vuint32_t IPUE:32;
1073 } B;
1074 } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */
1075
1076 vuint8_t WKUP_reserved3[16328]; /* Reserved 16328 (Base+0x0038-0x3FFF) */
1077
1078}; /* end of WKUP_tag */
1079/****************************************************************************/
1080/* MODULE : EMIOS */
1081/****************************************************************************/
1082
1083struct EMIOS_CHANNEL_tag{
1084
1085 union { /* Channel A Data (UCn Base+0x0000) */
1086 vuint32_t R;
1087 struct {
1088 vuint32_t :16;
1089 vuint32_t A:16;
1090 } B;
1091 } CADR;
1092
1093 union { /* Channel B Data (UCn Base+0x0004) */
1094 vuint32_t R;
1095 struct {
1096 vuint32_t :16;
1097 vuint32_t B:16;
1098 } B;
1099 } CBDR;
1100
1101 union { /* Channel Counter (UCn Base+0x0008) */
1102 vuint32_t R;
1103 struct {
1104 vuint32_t :16;
1105 vuint32_t C:16;
1106 } B;
1107 } CCNTR;
1108
1109 union { /* Channel Control (UCn Base+0x000C) */
1110 vuint32_t R;
1111 struct {
1112 vuint32_t FREN:1;
1113 vuint32_t :3;
1114 vuint32_t UCPRE:2;
1115 vuint32_t UCPEN:1;
1116 vuint32_t DMA:1;
1117 vuint32_t :1;
1118 vuint32_t IF:4;
1119 vuint32_t FCK:1;
1120 vuint32_t FEN:1;
1121 vuint32_t :3;
1122 vuint32_t FORCMA:1;
1123 vuint32_t FORCMB:1;
1124 vuint32_t :1;
1125 vuint32_t BSL:2;
1126 vuint32_t EDSEL:1;
1127 vuint32_t EDPOL:1;
1128 vuint32_t MODE:7;
1129 } B;
1130 } CCR;
1131
1132 union { /* Channel Status (UCn Base+0x0010) */
1133 vuint32_t R;
1134 struct {
1135 vuint32_t OVR:1;
1136 vuint32_t :15;
1137 vuint32_t OVFL:1;
1138 vuint32_t :12;
1139 vuint32_t UCIN:1;
1140 vuint32_t UCOUT:1;
1141 vuint32_t FLAG:1;
1142 } B;
1143 } CSR;
1144
1145 union { /* Alternate Channel A Data (UCn Base+0x0014) */
1146 vuint32_t R;
1147 struct {
1148 vuint32_t :16;
1149 vuint32_t ALTA:16;
1150 } B;
1151 } ALTCADR;
1152
1153 vuint8_t EMIOS_CHANNEL_reserved0[8]; /* (UCn Base + (0x0018-0x001F) */
1154
1155}; /* end of EMIOS_CHANNEL_tag */
1156
1157
1158struct EMIOS_tag{
1159
1160 union { /* Module Configuration (Base+0x0000) */
1161 vuint32_t R;
1162 struct {
1163 vuint32_t :1;
1164 vuint32_t MDIS:1;
1165 vuint32_t FRZ:1;
1166 vuint32_t GTBE:1;
1167 vuint32_t :1;
1168 vuint32_t GPREN:1;
1169 vuint32_t :10;
1170 vuint32_t GPRE:8;
1171 vuint32_t :8;
1172 } B;
1173 } MCR;
1174
1175 union { /* Global Flag (Base+0x0004) */
1176 vuint32_t R;
1177 struct {
1178 vuint32_t F31:1;
1179 vuint32_t F30:1;
1180 vuint32_t F29:1;
1181 vuint32_t F28:1;
1182 vuint32_t F27:1;
1183 vuint32_t F26:1;
1184 vuint32_t F25:1;
1185 vuint32_t F24:1;
1186 vuint32_t F23:1;
1187 vuint32_t F22:1;
1188 vuint32_t F21:1;
1189 vuint32_t F20:1;
1190 vuint32_t F19:1;
1191 vuint32_t F18:1;
1192 vuint32_t F17:1;
1193 vuint32_t F16:1;
1194 vuint32_t F15:1;
1195 vuint32_t F14:1;
1196 vuint32_t F13:1;
1197 vuint32_t F12:1;
1198 vuint32_t F11:1;
1199 vuint32_t F10:1;
1200 vuint32_t F9:1;
1201 vuint32_t F8:1;
1202 vuint32_t F7:1;
1203 vuint32_t F6:1;
1204 vuint32_t F5:1;
1205 vuint32_t F4:1;
1206 vuint32_t F3:1;
1207 vuint32_t F2:1;
1208 vuint32_t F1:1;
1209 vuint32_t F0:1;
1210 } B;
1211 } GFR;
1212
1213 union { /* Output Update Disable (Base+0x0008) */
1214 vuint32_t R;
1215 struct {
1216 vuint32_t OU31:1;
1217 vuint32_t OU30:1;
1218 vuint32_t OU29:1;
1219 vuint32_t OU28:1;
1220 vuint32_t OU27:1;
1221 vuint32_t OU26:1;
1222 vuint32_t OU25:1;
1223 vuint32_t OU24:1;
1224 vuint32_t OU23:1;
1225 vuint32_t OU22:1;
1226 vuint32_t OU21:1;
1227 vuint32_t OU20:1;
1228 vuint32_t OU19:1;
1229 vuint32_t OU18:1;
1230 vuint32_t OU17:1;
1231 vuint32_t OU16:1;
1232 vuint32_t OU15:1;
1233 vuint32_t OU14:1;
1234 vuint32_t OU13:1;
1235 vuint32_t OU12:1;
1236 vuint32_t OU11:1;
1237 vuint32_t OU10:1;
1238 vuint32_t OU9:1;
1239 vuint32_t OU8:1;
1240 vuint32_t OU7:1;
1241 vuint32_t OU6:1;
1242 vuint32_t OU5:1;
1243 vuint32_t OU4:1;
1244 vuint32_t OU3:1;
1245 vuint32_t OU2:1;
1246 vuint32_t OU1:1;
1247 vuint32_t OU0:1;
1248 } B;
1249 } OUDR;
1250
1251 union { /* Disable Channel (Base+0x000F) */
1252 vuint32_t R;
1253 struct {
1254 vuint32_t CHDIS31:1;
1255 vuint32_t CHDIS30:1;
1256 vuint32_t CHDIS29:1;
1257 vuint32_t CHDIS28:1;
1258 vuint32_t CHDIS27:1;
1259 vuint32_t CHDIS26:1;
1260 vuint32_t CHDIS25:1;
1261 vuint32_t CHDIS24:1;
1262 vuint32_t CHDIS23:1;
1263 vuint32_t CHDIS22:1;
1264 vuint32_t CHDIS21:1;
1265 vuint32_t CHDIS20:1;
1266 vuint32_t CHDIS19:1;
1267 vuint32_t CHDIS18:1;
1268 vuint32_t CHDIS17:1;
1269 vuint32_t CHDIS16:1;
1270 vuint32_t CHDIS15:1;
1271 vuint32_t CHDIS14:1;
1272 vuint32_t CHDIS13:1;
1273 vuint32_t CHDIS12:1;
1274 vuint32_t CHDIS11:1;
1275 vuint32_t CHDIS10:1;
1276 vuint32_t CHDIS9:1;
1277 vuint32_t CHDIS8:1;
1278 vuint32_t CHDIS7:1;
1279 vuint32_t CHDIS6:1;
1280 vuint32_t CHDIS5:1;
1281 vuint32_t CHDIS4:1;
1282 vuint32_t CHDIS3:1;
1283 vuint32_t CHDIS2:1;
1284 vuint32_t CHDIS1:1;
1285 vuint32_t CHDIS0:1;
1286 } B;
1287 } UCDIS;
1288
1289 vuint8_t EMIOS_reserved0[16]; /* Reserved 16 Bytes (Base+0x0010-0x001F) */
1290
1291 struct EMIOS_CHANNEL_tag CH[32]; /* Add in 32 unified channels */
1292
1293 vuint8_t EMIOS_reserved1[3040]; /* 3040 bytes (Base+0x0420-0x0FFF) */
1294
1295}; /* end of EMIOS_tag */
1296/****************************************************************************/
1297/* MODULE : SSCM */
1298/****************************************************************************/
1299struct SSCM_tag{
1300
1301 union { /* Status (Base+0x0000) */
1302 vuint16_t R;
1303 struct {
1304 vuint16_t :1;
1305 vuint16_t CER:1;
1306 vuint16_t :1;
1307 vuint16_t Z4_NXEN:1;
1308 vuint16_t Z0_NXEN:1;
1309 vuint16_t PUB:1;
1310 vuint16_t SEC:1;
1311 vuint16_t :1;
1312 vuint16_t BMODE:3;
1313 vuint16_t VLE:1;
1314 vuint16_t :4;
1315 } B;
1316 } STATUS;
1317
1318 union { /* System Memory Configuration (Base+0x002) */
1319 vuint16_t R;
1320 struct {
1321 vuint16_t JPIN:10;
1322 vuint16_t ILVD:1;
1323 vuint16_t MREV:4;
1324 vuint16_t DVLD:1;
1325 } B;
1326 } MEMCONFIG;
1327
1328 vuint8_t SSCM_reserved0[2]; /* Reserved 2 bytes (Base+0x0004-0x0005) */
1329
1330 union { /* Error Configuration (Base+0x0006) */
1331 vuint16_t R;
1332 struct {
1333 vuint16_t :14;
1334 vuint16_t PAE:1;
1335 vuint16_t RAE:1;
1336 } B;
1337 } ERROR;
1338
1339 union { /* Debug Status Port (Base+0x0008) */
1340 vuint16_t R;
1341 struct {
1342 vuint16_t :13;
1343 vuint16_t DEBUG_MODE:3;
1344 } B;
1345 } DEBUGPORT;
1346
1347 vuint8_t SSCM_reserved1[2]; /* Reserved 2 bytes (Base+0x000A-0x000B) */
1348
1349 union { /* Password Comparison High Word (Base+0x000C) */
1350 vuint32_t R;
1351 struct {
1352 vuint32_t PWD_HI:32;
1353 } B;
1354 } PWCMPH;
1355
1356 union { /* Password Comparison Low Word (Base+0x0010)*/
1357 vuint32_t R;
1358 struct {
1359 vuint32_t PWD_LO:32;
1360 } B;
1361 } PWCMPL;
1362
1363 vuint8_t SSCM_reserved2[4]; /* Reserved 4 bytes (Base+0x0014-0x0017) */
1364
1365 union { /* DPM Boot (Base+0x0018)*/
1366 vuint32_t R;
1367 struct {
1368 vuint32_t PBOOT:30;
1369 vuint32_t DVLE:1;
1370 vuint32_t :1;
1371 } B;
1372 } DPMBOOT;
1373
1374 union { /* DPM Boot Key (Base+0x001C)*/
1375 vuint32_t R;
1376 struct {
1377 vuint32_t :16;
1378 vuint32_t KEY:16;
1379 } B;
1380 } DPMKEY;
1381
1382 union { /* User option status (Base+0x0020)*/
1383 vuint32_t R;
1384 struct {
1385 vuint32_t UOPT:32;
1386 } B;
1387 } UOPS;
1388
1389 vuint8_t SSCM_reserved3[4]; /* Reserved 4 bytes (Base+0x0024-0x0027) */
1390
1391 union { /* Processor Start Address (Base+0x0028)*/
1392 vuint32_t R;
1393 struct {
1394 vuint32_t SADR:32;
1395 } B;
1396 } PSA;
1397
1398 union { /* Code Length (Base+0x002C)*/
1399 vuint32_t R;
1400 struct {
1401 vuint32_t CL:32;
1402 } B;
1403 } CLEN;
1404
1405
1406
1407}; /* end of SSCM_tag */
1408/****************************************************************************/
1409/* MODULE : ME */
1410/****************************************************************************/
1411struct ME_tag{
1412
1413 union { /* Global Status (Base+0x0000) */
1414 vuint32_t R;
1415 struct {
1416 vuint32_t S_CURRENTMODE:4;
1417 vuint32_t S_MTRANS:1;
1418 vuint32_t :1; /* vuint32_t S_DC:1; (Not on B3M) */
1419 vuint32_t :2;
1420 vuint32_t S_PDO:1;
1421 vuint32_t :2;
1422 vuint32_t S_MVR:1;
1423 vuint32_t S_DFLA:2;
1424 vuint32_t S_CFLA:2;
1425 vuint32_t :9;
1426 vuint32_t S_FMPLL:1;
1427 vuint32_t S_FXOSC:1;
1428 vuint32_t S_FIRC:1;
1429 vuint32_t S_SYSCLK:4;
1430 } B;
1431 } GS;
1432
1433 union { /* Mode Control (Base+0x004) */
1434 vuint32_t R;
1435 struct {
1436 vuint32_t TARGET_MODE:4;
1437 vuint32_t :12;
1438 vuint32_t KEY:16;
1439 } B;
1440 } MCTL;
1441
1442 union { /* Mode Enable (Base+0x0008) */
1443 vuint32_t R;
1444 struct {
1445 vuint32_t :16;
1446 vuint32_t RESET_DEST:1;
1447 vuint32_t :1;
1448 vuint32_t STANDBY:1;
1449 vuint32_t :2;
1450 vuint32_t STOP:1;
1451 vuint32_t :1;
1452 vuint32_t HALT:1;
1453 vuint32_t RUN3:1;
1454 vuint32_t RUN2:1;
1455 vuint32_t RUN1:1;
1456 vuint32_t RUN0:1;
1457 vuint32_t DRUN:1;
1458 vuint32_t SAFE:1;
1459 vuint32_t TEST:1;
1460 vuint32_t RESET:1;
1461 } B;
1462 } MER;
1463
1464 union { /* Interrupt Status (Base+0x000C) */
1465 vuint32_t R;
1466 struct {
1467 vuint32_t :28;
1468 vuint32_t I_ICONF:1;
1469 vuint32_t I_IMODE:1;
1470 vuint32_t I_SAFE:1;
1471 vuint32_t I_MTC:1;
1472 } B;
1473 } IS;
1474
1475 union { /* Interrupt Mask (Base+0x0010) */
1476 vuint32_t R;
1477 struct {
1478 vuint32_t :27;
1479 vuint32_t M_ICONF_CU:1;
1480 vuint32_t M_ICONF:1;
1481 vuint32_t M_IMODE:1;
1482 vuint32_t M_SAFE:1;
1483 vuint32_t M_MTC:1;
1484 } B;
1485 } IM;
1486
1487 union { /* Invalid Mode Transition Status (Base+0x0014) */
1488 vuint32_t R;
1489 struct {
1490 vuint32_t :27;
1491 vuint32_t S_MTI:1;
1492 vuint32_t S_MRI:1;
1493 vuint32_t S_DMA:1;
1494 vuint32_t S_NMA:1;
1495 vuint32_t S_SEA:1;
1496 } B;
1497 } IMTS;
1498
1499 union { /* Debug Mode Transition Status (Base+0x0018) */
1500 vuint32_t R;
1501 struct {
1502 vuint32_t PREVIOUS_MODE:4;
1503 vuint32_t :4;
1504 vuint32_t MPH_BUSY:1;
1505 vuint32_t :2;
1506 vuint32_t PMC_PROG:1;
1507 vuint32_t CORE_DBG:1;
1508 vuint32_t :2;
1509 vuint32_t SMR:1;
1510 vuint32_t :1;
1511 vuint32_t VREG_CSRC_SC:1;
1512 vuint32_t CSRC_CSRC_SC:1;
1513 vuint32_t FIRC_SC:1;
1514 vuint32_t SCSRC_SC:1;
1515 vuint32_t SYSCLK_SW:1;
1516 vuint32_t DFLASH_SC:1;
1517 vuint32_t CFLASH_SC:1;
1518 vuint32_t CDP_PRPH_0_143:1;
1519 vuint32_t :3;
1520 vuint32_t CDP_PRPH_96_127:1;
1521 vuint32_t CDP_PRPH_64_95:1;
1522 vuint32_t CDP_PRPH_32_63:1;
1523 vuint32_t CDP_PRPH_0_31:1;
1524 } B;
1525 } DMTS;
1526
1527 vuint8_t ME_reserved0[4]; /* reserved 4 bytes (Base+0x001C-0x001F) */
1528
1529 union { /* Reset Mode Configuration (Base+0x0020) */
1530 vuint32_t R;
1531 struct {
1532 vuint32_t :8;
1533 vuint32_t PDO:1;
1534 vuint32_t :2;
1535 vuint32_t MVRON:1;
1536 vuint32_t DFLAON:2;
1537 vuint32_t CFLAON:2;
1538 vuint32_t :9;
1539 vuint32_t FMPLLON:1;
1540 vuint32_t FXOSC0ON:1;
1541 vuint32_t FIRCON:1;
1542 vuint32_t SYSCLK:4;
1543 } B;
1544 } RESET;
1545
1546 union { /* Test Mode Configuration (Base+0x0024) */
1547 vuint32_t R;
1548 struct {
1549 vuint32_t :8;
1550 vuint32_t PDO:1;
1551 vuint32_t :2;
1552 vuint32_t MVRON:1;
1553 vuint32_t DFLAON:2;
1554 vuint32_t CFLAON:2;
1555 vuint32_t :9;
1556 vuint32_t FMPLLON:1;
1557 vuint32_t FXOSC0ON:1;
1558 vuint32_t FIRCON:1;
1559 vuint32_t SYSCLK:4;
1560 } B;
1561 } TEST;
1562
1563 union { /* Safe Mode Configuration (Base+0x0028) */
1564 vuint32_t R;
1565 struct {
1566 vuint32_t :8;
1567 vuint32_t PDO:1;
1568 vuint32_t :2;
1569 vuint32_t MVRON:1;
1570 vuint32_t DFLAON:2;
1571 vuint32_t CFLAON:2;
1572 vuint32_t :9;
1573 vuint32_t FMPLLON:1;
1574 vuint32_t FXOSC0ON:1;
1575 vuint32_t FIRCON:1;
1576 vuint32_t SYSCLK:4;
1577 } B;
1578 } SAFE;
1579
1580 union { /* DRUN Mode Configuration (Base+0x002C) */
1581 vuint32_t R;
1582 struct {
1583 vuint32_t :8;
1584 vuint32_t PDO:1;
1585 vuint32_t :2;
1586 vuint32_t MVRON:1;
1587 vuint32_t DFLAON:2;
1588 vuint32_t CFLAON:2;
1589 vuint32_t :9;
1590 vuint32_t FMPLLON:1;
1591 vuint32_t FXOSC0ON:1;
1592 vuint32_t FIRCON:1;
1593 vuint32_t SYSCLK:4;
1594 } B;
1595 } DRUN;
1596
1597 union { /* RUN 0->4 Mode Configuration (+0x0030-0x003C) */
1598 vuint32_t R;
1599 struct {
1600 vuint32_t :8;
1601 vuint32_t PDO:1;
1602 vuint32_t :2;
1603 vuint32_t MVRON:1;
1604 vuint32_t DFLAON:2;
1605 vuint32_t CFLAON:2;
1606 vuint32_t :9;
1607 vuint32_t FMPLLON:1;
1608 vuint32_t FXOSC0ON:1;
1609 vuint32_t FIRCON:1;
1610 vuint32_t SYSCLK:4;
1611 } B;
1612 } RUN[4];
1613
1614 union { /* HALT Mode Configuration (Base+0x0040) */
1615 vuint32_t R;
1616 struct {
1617 vuint32_t :8;
1618 vuint32_t PDO:1;
1619 vuint32_t :2;
1620 vuint32_t MVRON:1;
1621 vuint32_t DFLAON:2;
1622 vuint32_t CFLAON:2;
1623 vuint32_t :9;
1624 vuint32_t FMPLLON:1;
1625 vuint32_t FXOSC0ON:1;
1626 vuint32_t FIRCON:1;
1627 vuint32_t SYSCLK:4;
1628 } B;
1629 } HALT;
1630
1631 vuint8_t ME_reserved1[4]; /* reserved 4 bytes (Base+0x0044-0x0047) */
1632
1633 union { /* STOP Mode Configuration (Base+0x0048) */
1634 vuint32_t R;
1635 struct {
1636 vuint32_t :8;
1637 vuint32_t PDO:1;
1638 vuint32_t :2;
1639 vuint32_t MVRON:1;
1640 vuint32_t DFLAON:2;
1641 vuint32_t CFLAON:2;
1642 vuint32_t :9;
1643 vuint32_t FMPLLON:1;
1644 vuint32_t FXOSC0ON:1;
1645 vuint32_t FIRCON:1;
1646 vuint32_t SYSCLK:4;
1647 } B;
1648 } STOP;
1649
1650 vuint8_t ME_reserved2[8]; /* reserved 8 bytes (Base+0x004C-0x0053) */
1651
1652 union { /* STANDBY Mode Configuration (Base+0x0054) */
1653 vuint32_t R;
1654 struct {
1655 vuint32_t :8;
1656 vuint32_t PDO:1;
1657 vuint32_t :2;
1658 vuint32_t MVRON:1;
1659 vuint32_t DFLAON:2;
1660 vuint32_t CFLAON:2;
1661 vuint32_t :9;
1662 vuint32_t FMPLLON:1;
1663 vuint32_t FXOSC0ON:1;
1664 vuint32_t FIRCON:1;
1665 vuint32_t SYSCLK:4;
1666 } B;
1667 } STANDBY;
1668
1669 vuint8_t ME_reserved3[8]; /* reserved 8 bytes (Base+0x0058-0x005F) */
1670
1671 union {
1672 vuint32_t R;
1673 struct { /* Peripheral Status 0 (Base+0x0060) */
1674 vuint32_t :7;
1675 vuint32_t S_FLEXRAY:1;
1676 vuint32_t S_DMA_CH_MUX:1;
1677 vuint32_t :1;
1678 vuint32_t S_FLEXCAN5:1;
1679 vuint32_t S_FLEXCAN4:1;
1680 vuint32_t S_FLEXCAN3:1;
1681 vuint32_t S_FLEXCAN2:1;
1682 vuint32_t S_FLEXCAN1:1;
1683 vuint32_t S_FLEXCAN0:1;
1684 vuint32_t :2;
1685 vuint32_t S_LINFLEX9:1;
1686 vuint32_t S_LINFLEX8:1;
1687 vuint32_t S_DSPI7:1;
1688 vuint32_t S_DSPI6:1;
1689 vuint32_t S_DSPI5:1;
1690 vuint32_t S_DSPI4:1;
1691 vuint32_t S_DSPI3:1;
1692 vuint32_t S_DSPI2:1;
1693 vuint32_t S_DSPI1:1;
1694 vuint32_t S_DSPI0:1;
1695 vuint32_t :4;
1696 } B;
1697 } PS0;
1698
1699 union { /* Peripheral Status 1 (Base+0x0064)*/
1700 vuint32_t R;
1701 struct {
1702 vuint32_t :3;
1703 vuint32_t S_CANSAMPLER:1;
1704 vuint32_t :2;
1705 vuint32_t S_CTUL:1;
1706 vuint32_t :1;
1707 vuint32_t S_LINFLEX7:1;
1708 vuint32_t S_LINFLEX6:1;
1709 vuint32_t S_LINFLEX5:1;
1710 vuint32_t S_LINFLEX4:1;
1711 vuint32_t S_LINFLEX3:1;
1712 vuint32_t S_LINFLEX2:1;
1713 vuint32_t S_LINFLEX1:1;
1714 vuint32_t S_LINFLEX0:1;
1715 vuint32_t :3;
1716 vuint32_t S_I2C:1;
1717 vuint32_t :10;
1718 vuint32_t S_ADC1:1;
1719 vuint32_t S_ADC0:1;
1720 } B;
1721 } PS1;
1722
1723 union { /* Peripheral Status 2 (Base+0x0068) */
1724 vuint32_t R;
1725 struct {
1726 vuint32_t :3;
1727 vuint32_t S_PIT_RTI:1;
1728 vuint32_t S_RTC_API:1;
1729 vuint32_t :16;
1730 vuint32_t S_EMIOS1:1;
1731 vuint32_t S_EMIOS0:1;
1732 vuint32_t :2;
1733 vuint32_t S_WKUP:1; /* Also called S_WKPU on B3M RM */
1734 vuint32_t S_SIUL:1;
1735 vuint32_t :4;
1736 } B;
1737 } PS2;
1738
1739 union { /* Peripheral Status 3 (Base+0x006C) */
1740 vuint32_t R;
1741 struct {
1742 vuint32_t :23;
1743 vuint32_t S_CMU:1;
1744 vuint32_t :8;
1745 } B;
1746 } PS3;
1747
1748 vuint8_t ME_reserved4[16]; /* reserved 16 bytes (Base+0x0070-0x007F) */
1749
1750 union { /* RUN Peripheral Config 0..7 (+0x0080-009C) */
1751 vuint32_t R;
1752 struct {
1753 vuint32_t :24;
1754 vuint32_t RUN3:1;
1755 vuint32_t RUN2:1;
1756 vuint32_t RUN1:1;
1757 vuint32_t RUN0:1;
1758 vuint32_t DRUN:1;
1759 vuint32_t SAFE:1;
1760 vuint32_t TEST:1;
1761 vuint32_t RESET:1;
1762 } B;
1763 } RUNPC[8];
1764
1765 union { /* Low Pwr Periph Config 0..7 (+0x00A0-0x00BC) */
1766 vuint32_t R;
1767 struct {
1768 vuint32_t :18;
1769 vuint32_t STANDBY:1;
1770 vuint32_t :2;
1771 vuint32_t STOP:1;
1772 vuint32_t :1;
1773 vuint32_t HALT:1;
1774 vuint32_t :8;
1775 } B;
1776 } LPPC[8];
1777
1778
1779 /* Note on PCTL registers: There are only some PCTL implemented in */
1780 /* Bolero 3M. In order to make the PCTL easily addressable, these */
1781 /* are defined as an array (ie ME.PCTL[x].R). This means you have */
1782 /* to be careful when addressing these registers in order not to */
1783 /* access a PCTL that is not implemented. Following are available: */
1784 /* 104, 92, 91, 73, 72, 69, 68, 60, 57, 44, 33, 32, 24, 23, 21-16, 13-4*/
1785
1786 union { /* Peripheral Control 0..143 (+0x00C0-0x0128) */
1787 vuint8_t R;
1788 struct {
1789 vuint8_t :1;
1790 vuint8_t DBG_F:1;
1791 vuint8_t LP_CFG:3;
1792 vuint8_t RUN_CFG:3;
1793 } B;
1794 } PCTL[105];
1795
1796}; /* end of ME_tag */
1797/****************************************************************************/
1798/* MODULE : CGM */
1799/****************************************************************************/
1800struct CGM_tag{
1801
1802
1803 /*
1804
1805 The "CGM" has fairly wide coverage and essentially includes everything in
1806
1807 chapter 3 of the Bolero 3M Reference Manual:
1808
1809
1810
1811 Base Address | Clock Sources
1812
1813 -----------------------------
1814
1815 0xC3FE0000 | FXOSC_CTL
1816
1817 0xC3FE0040 | SXOSC_CTL
1818
1819 0xC3FE0060 | FIRC_CTL
1820
1821 0xC3FE0080 | SIRC_CTL
1822
1823 0xC3FE00A0 | FMPLL
1824
1825 0xC3FE00C0 | CGM Block 1
1826
1827 0xC3FE0100 | CMU
1828
1829 0xC3FE0120 | CGM Block 2
1830
1831
1832
1833 In this header file, "Base" referrs to the 1st address, 0xC3FE_0000
1834
1835 */
1836 /* FXOSC - 0xC3FE_0000*/
1837 union { /* Fast OSC Control (Base+0x0000) */
1838 vuint32_t R;
1839 struct {
1840 vuint32_t OSCBYP:1;
1841 vuint32_t :7;
1842 vuint32_t EOCV:8;
1843 vuint32_t M_OSC:1;
1844 vuint32_t :2;
1845 vuint32_t OSCDIV:5;
1846 vuint32_t I_OSC:1;
1847 vuint32_t:7;
1848 } B;
1849 } FXOSC_CTL;
1850
1851
1852 /* Reserved Space between end of FXOSC and start SXOSC */
1853 vuint8_t CGM_reserved0[60]; /* Reserved 60 bytes (Base+0x0004-0x003F) */
1854
1855
1856 /* SXOSC - 0xC3FE_0040*/
1857 union { /* Slow Osc Control (Base+0x0040) */
1858 vuint32_t R;
1859 struct {
1860 vuint32_t OSCBYP:1;
1861 vuint32_t :7;
1862 vuint32_t EOCV:8;
1863 vuint32_t M_OSC:1;
1864 vuint32_t :2;
1865 vuint32_t OSCDIV:5;
1866 vuint32_t I_OSC:1;
1867 vuint32_t :5;
1868 vuint32_t S_OSC:1;
1869 vuint32_t OSCON:1;
1870 } B;
1871 } SXOSC_CTL;
1872
1873
1874 /* Reserved space between end of SXOSC and start of FIRC */
1875 vuint8_t CGM_reserved1[28]; /*Reserved 28 bytes (Base+0x0044-0x005F) */
1876
1877
1878 /* FIRC - 0x3CFE_0060 */
1879 union { /* Fast IRC Control (Base+0x0060) */
1880 vuint32_t R;
1881 struct {
1882 vuint32_t :10;
1883 vuint32_t RCTRIM:6;
1884 vuint32_t :3;
1885 vuint32_t RCDIV:5;
1886 vuint32_t :8;
1887 } B;
1888 } FIRC_CTL;
1889
1890
1891 /* Reserved space between end of FIRC and start of SIRC */
1892 vuint8_t CGM_reserved2[28]; /*Reserved 28 bytes (Base+0x0064-0x007F) */
1893
1894
1895 /* SIRC - 0x3FE_0080 */
1896 union { /* Slow IRC Control (Base+0x0080) */
1897 vuint32_t R;
1898 struct {
1899 vuint32_t :11;
1900 vuint32_t SIRCTRIM:5;
1901 vuint32_t :3;
1902 vuint32_t SIRCDIV:5;
1903 vuint32_t :3;
1904 vuint32_t S_SIRC:1;
1905 vuint32_t :3;
1906 vuint32_t SIRCON_STDBY:1;
1907 } B;
1908 } SIRC_CTL;
1909
1910
1911 /* Reserved space between end of SIRC and start of FMPLL */
1912 vuint8_t CGM_reserved3[28]; /*Reserved 28 bytes (Base+0x0084-0x009F) */
1913
1914
1915 /* FMPLL - 0xC3FE_00A0 */
1916 union { /* FMPLL Control (Base+0x00A0) */
1917 vuint32_t R;
1918 struct {
1919 vuint32_t :2;
1920 vuint32_t IDF:4;
1921 vuint32_t ODF:2;
1922 vuint32_t :1;
1923 vuint32_t NDIV:7;
1924 vuint32_t :7;
1925 vuint32_t EN_PLL_SW:1;
1926 vuint32_t MODE:1;
1927 vuint32_t UNLOCK_ONCE:1;
1928 vuint32_t :1;
1929 vuint32_t I_LOCK:1;
1930 vuint32_t S_LOCK:1;
1931 vuint32_t PLL_FAIL_MASK:1;
1932 vuint32_t PLL_FAIL_FLAG:1;
1933 vuint32_t :1;
1934 } B;
1935 } FMPLL_CR;
1936
1937 union { /* FMPLL Modulation (Base+0x00A4) */
1938 vuint32_t R;
1939 struct {
1940 vuint32_t STRB_BYPASS:1;
1941 vuint32_t :1;
1942 vuint32_t SPRD_SEL:1;
1943 vuint32_t MOD_PERIOD:13;
1944 vuint32_t FM_EN:1;
1945 vuint32_t INC_STEP:15;
1946 } B;
1947 } FMPLL_MR;
1948
1949
1950 /* Reserved space between end of FMPLL and start of CGM Block 1 */
1951 vuint8_t CGM_reserved4[24]; /*Reserved 24 bytes (Base+0x00A8-0x00BF) */
1952
1953
1954 /* CGM Block 1 - 0xC3FE_00C0 */
1955 union { /* CMU Z0 Clock Divider Config (Base+0x00C0) */
1956 vuint8_t R;
1957 struct {
1958 vuint8_t :7;
1959 vuint8_t DIV:1;
1960 } B;
1961 } Z0_DCR;
1962
1963 vuint8_t CGM_reserved5[31]; /*Reserved 31 bytes (Base+0x00C1-0x00DF) */
1964
1965 union { /* CMU FEC Clock Divider Config (Base+0x00E0) */
1966 vuint8_t R;
1967 struct {
1968 vuint8_t :7;
1969 vuint8_t DIV:1;
1970 } B;
1971 } FEC_DCR;
1972
1973
1974 /* Reserved space between end of CGM Block1 and start of CMU */
1975 vuint8_t CGM_reserved6[31]; /*Reserved 31 bytes (Base+0x00E1-0x00FF) */
1976
1977
1978 /* CMU - 0xC3FE_0100 */
1979 union { /* CMU Control Status (Base+0x0100) */
1980 vuint32_t R;
1981 struct {
1982 vuint32_t :8;
1983 vuint32_t SFM:1;
1984 vuint32_t :13;
1985 vuint32_t CLKSEL1:2;
1986 vuint32_t :5;
1987 vuint32_t RCDIV:2;
1988 vuint32_t CME_A:1;
1989 } B;
1990 } CMU_CSR;
1991
1992 union { /* CMU Frequency Display (Base+0x0104) */
1993 vuint32_t R;
1994 struct {
1995 vuint32_t :12;
1996 vuint32_t FD:20;
1997 } B;
1998 } CMU_FDR;
1999
2000 union { /* CMU High Freq Reference FMPLL (Base+0x0108) */
2001 vuint32_t R;
2002 struct {
2003 vuint32_t :20;
2004 vuint32_t HFREF:12;
2005 } B;
2006 } CMU_HFREFR;
2007
2008 union { /* CMU Low Freq Reference FMPLL (Base+0x010C) */
2009 vuint32_t R;
2010 struct {
2011 vuint32_t :20;
2012 vuint32_t LFREF:12;
2013 } B;
2014 } CMU_LFREFR;
2015
2016 union { /* CMU Interrupt Status (Base+0x0110) */
2017 vuint32_t R;
2018 struct {
2019 vuint32_t :29;
2020 vuint32_t FHHI:1;
2021 vuint32_t FLLI:1;
2022 vuint32_t OLRI:1;
2023 } B;
2024 } CMU_ISR;
2025
2026
2027 /* Note about CMU_IMR: On Bolero 3M this register will always read as 0 */
2028 /* Commented out register definition is below but this register should */
2029 /* not be accessed in Bolero 3M */
2030
2031 /* Reserved space where IMR was previously positioned */
2032 vuint8_t CGM_reserved7[4]; /*Reserved 4 bytes (Base+0x0114-0x0117) */
2033
2034 /*union { Interrupt Mask Register Removed from Bolero3M (Read 0)
2035
2036 vuint32_t R;
2037
2038 struct {
2039
2040 vuint32_t :32;
2041
2042 } B;
2043
2044 } CMU_IMR; */
2045 union { /* CMU Measurement Duration (Base+0x0118) */
2046 vuint32_t R;
2047 struct {
2048 vuint32_t :12;
2049 vuint32_t MD:20;
2050 } B;
2051 } CMU_MDR;
2052
2053
2054 /* Reserved space between end of CMU and start of CGM Block 2 */
2055 vuint8_t CGM_reserved8[4]; /*Reserved 4 bytes (Base+0x011C-0x011F) */
2056
2057
2058 /* CGM - 0xC3FE0120 */
2059 union { /* CGM Flash Clock Divider Config (Base+0x0120) */
2060 vuint8_t R;
2061 struct {
2062 vuint8_t :7;
2063 vuint8_t DIV:1;
2064 } B;
2065 } FLASH_DCR;
2066
2067 vuint8_t CGM_reserved9[591]; /*Reserved 591 bytes (Base+0x0121-0x036F) */
2068
2069 union { /* GCM Output Clock Enable (Base+0x0370) */
2070 vuint32_t R;
2071 struct {
2072 vuint32_t :31;
2073 vuint32_t EN:1;
2074 } B;
2075 } OC_EN;
2076
2077 union { /* CGM Output Clock Division Sel (Base+0x0374) */
2078 vuint8_t R;
2079 struct {
2080 vuint8_t :2;
2081 vuint8_t SELDIV:2;
2082 vuint8_t SELCTL:4;
2083 } B;
2084 } OCDS_SC;
2085
2086 vuint8_t CGM_reserved10[3]; /*Reserved 3 bytes (Base+0x0375-0x0377) */
2087
2088 union { /* CGM System Clock Select Status (Base+0x0378) */
2089 vuint32_t R;
2090 struct {
2091 vuint32_t :4;
2092 vuint32_t SELSTAT:4;
2093 vuint32_t :24;
2094 } B;
2095 } SC_SS;
2096
2097 union { /* CGM Sys Clk Div Config0 (Base+0x037C) */
2098 vuint8_t R;
2099 struct {
2100 vuint8_t DE0:1;
2101 vuint8_t :3;
2102 vuint8_t DIV0:4;
2103 } B;
2104 } SC_DC0;
2105
2106 union { /* CGM Sys Clk Div Config1 (Base+0x037D) */
2107 vuint8_t R;
2108 struct {
2109 vuint8_t DE1:1;
2110 vuint8_t :3;
2111 vuint8_t DIV1:4;
2112 } B;
2113 } SC_DC1;
2114
2115 union { /* CGM Sys Clk Div Config1 (Base+0x037E) */
2116 vuint8_t R;
2117 struct {
2118 vuint8_t DE2:1;
2119 vuint8_t :3;
2120 vuint8_t DIV2:4;
2121 } B;
2122 } SC_DC2;
2123
2124 vuint8_t CGM_reserved11[1]; /*Reserved 1 byte (Base+0x037F) */
2125
2126 union { /* CGM Aux Clock0 Select Control (+0x0380-0x383) */
2127 vuint32_t R;
2128 struct {
2129 vuint32_t :4;
2130 vuint32_t SELCTL:4;
2131 vuint32_t :24;
2132 } B;
2133 } AC0_SC;
2134
2135 vuint8_t CGM_reserved12[4]; /*Reserved 4 bytes (Base+0x0384-0x0387) */
2136
2137 union { /* CGM Aux Clock1 Select Control (Base+0x0388) */
2138 vuint32_t R;
2139 struct {
2140 vuint32_t :4;
2141 vuint32_t SELCTL:4;
2142 vuint32_t :24;
2143 } B;
2144 } AC1_SC;
2145
2146 union { /* CGM Aux Clock1 Divider 0 Config (Base+0x038C) */
2147 vuint8_t R;
2148 struct {
2149 vuint8_t DE0:1;
2150 vuint8_t :3;
2151 vuint8_t DIV0:4;
2152 } B;
2153 } AC1_DC0;
2154
2155}; /* end of CGM_tag */
2156/****************************************************************************/
2157/* MODULE : RGM */
2158/****************************************************************************/
2159struct RGM_tag{
2160
2161 union { /* Functional Event Status (Base+0x0000) */
2162 vuint16_t R;
2163 struct {
2164 vuint16_t F_EXR:1;
2165 vuint16_t F_ST_NCF:1;
2166 vuint16_t F_ST_CF:1;
2167 vuint16_t F_ST_DONE:1;
2168 vuint16_t :1;
2169 vuint16_t F_Z4CORE:1;
2170 vuint16_t :1;
2171 vuint16_t F_FLASH:1;
2172 vuint16_t F_LVD45:1;
2173 vuint16_t F_CMU_FHL:1;
2174 vuint16_t F_CMU_OLR:1;
2175 vuint16_t F_FMPLL:1;
2176 vuint16_t F_CHKSTOP:1;
2177 vuint16_t F_SOFT_FUNC:1;
2178 vuint16_t F_Z0CORE:1;
2179 vuint16_t F_JTAG:1;
2180 } B;
2181 } FES;
2182
2183 union { /* Destructive Event Status (Base+0x0002) */
2184 vuint16_t R;
2185 struct {
2186 vuint16_t F_POR:1;
2187 vuint16_t F_SOFT_DEST:1;
2188 vuint16_t :10;
2189 vuint16_t F_LVD27:1;
2190 vuint16_t F_SWT:1;
2191 vuint16_t F_LVD12_PD1:1;
2192 vuint16_t F_LVD12_PD0:1;
2193 } B;
2194 } DES;
2195
2196 union { /* Functional Event Reset Disable (+0x0004) */
2197 vuint16_t R;
2198 struct {
2199 vuint16_t D_EXR:1;
2200 vuint16_t D_ST_NCF:1;
2201 vuint16_t D_ST_CF:1;
2202 vuint16_t D_ST_DONE:1;
2203 vuint16_t :1;
2204 vuint16_t D_Z4CORE:1;
2205 vuint16_t :1;
2206 vuint16_t D_FLASH:1;
2207 vuint16_t D_LVD45:1;
2208 vuint16_t D_CMU_FHL:1;
2209 vuint16_t D_CMU_OLR:1;
2210 vuint16_t D_FMPLL:1;
2211 vuint16_t D_CHKSTOP:1;
2212 vuint16_t D_SOFT_FUNC:1;
2213 vuint16_t D_Z0CORE:1;
2214 vuint16_t D_JTAG:1;
2215 } B;
2216 } FERD;
2217
2218 union { /* Destructive Event Reset Disable (Base+0x0006)*/
2219 vuint16_t R;
2220 struct {
2221 vuint16_t :1;
2222 vuint16_t D_SOFT_DEST:1;
2223 vuint16_t :10;
2224 vuint16_t D_LVD27:1;
2225 vuint16_t D_SWT:1;
2226 vuint16_t D_LVD12_PD1:1;
2227 vuint16_t D_LVD12_PD0:1;
2228 } B;
2229 } DERD;
2230
2231 vuint8_t RGM_reserved0[8]; /*Reserved 8 bytes (Base+0x008-0x000F) */
2232
2233 union { /* Functional Event Alt Request (Base+0x0010) */
2234 vuint16_t R;
2235 struct {
2236 vuint16_t :1;
2237 vuint16_t AR_ST_NCF:1;
2238 vuint16_t AR_ST_CF:1;
2239 vuint16_t :2;
2240 vuint16_t AR_Z4CORE:1;
2241 vuint16_t :2;
2242 vuint16_t AR_LVD45:1;
2243 vuint16_t AR_CMU_FHL:1;
2244 vuint16_t AR_CMU_OLR:1;
2245 vuint16_t AR_FMPLL:1;
2246 vuint16_t :2;
2247 vuint16_t AR_Z0CORE:1;
2248 vuint16_t AR_JTAG:1;
2249 } B;
2250 } FEAR;
2251
2252 vuint8_t RGM_reserved1[6]; /*Reserved 6 bytes (Base+0x0012-0x0017) */
2253
2254 union { /* Functional Event Short Sequence (+0x0018) */
2255 vuint16_t R;
2256 struct {
2257 vuint16_t SS_EXR:1;
2258 vuint16_t :2;
2259 vuint16_t SS_ST_DONE:1;
2260 vuint16_t :1;
2261 vuint16_t SS_Z4CORE:1;
2262 vuint16_t :1;
2263 vuint16_t SS_FLASH:1;
2264 vuint16_t SS_LVD45:1;
2265 vuint16_t SS_CMU_FHL:1;
2266 vuint16_t SS_CMU_OLR:1;
2267 vuint16_t SS_FMPLL:1;
2268 vuint16_t SS_CHKSTOP:1;
2269 vuint16_t SS_SOFT_FUNC:1;
2270 vuint16_t SS_Z0CORE:1;
2271 vuint16_t SS_JTAG:1;
2272 } B;
2273 } FESS;
2274
2275 union { /* STANDBY reset sequence (Base+0x001A) */
2276 vuint16_t R;
2277 struct {
2278 vuint16_t :7;
2279 vuint16_t SB_CPU:1;
2280 vuint16_t BOOT_FROM_BKP_RAM:1;
2281 vuint16_t :7;
2282 } B;
2283 } STDBY;
2284
2285 union { /* Functional Bidirectional Reset En (+0x001C) */
2286 vuint16_t R;
2287 struct {
2288 vuint16_t BE_EXR:1;
2289 vuint16_t :2;
2290 vuint16_t BE_ST_DONE:1;
2291 vuint16_t :1;
2292 vuint16_t BE_Z4CORE:1;
2293 vuint16_t :1;
2294 vuint16_t BE_FLASH:1;
2295 vuint16_t BE_LVD45:1;
2296 vuint16_t BE_CMU_FHL:1;
2297 vuint16_t BE_CMU_OLR:1;
2298 vuint16_t BE_FMPLL:1;
2299 vuint16_t BE_CHKSTOP:1;
2300 vuint16_t BE_SOFT_FUNC:1;
2301 vuint16_t BE_Z0CORE:1;
2302 vuint16_t BE_JTAG:1;
2303 } B;
2304 } FBRE;
2305
2306}; /* end of RGM_tag */
2307/****************************************************************************/
2308/* MODULE : PCU */
2309/****************************************************************************/
2310struct PCU_tag{
2311
2312 union { /* PCU Power domain 0-3 config (+0x0000-0x000C) */
2313 vuint32_t R;
2314 struct {
2315 vuint32_t :18;
2316 vuint32_t STBY:1;
2317 vuint32_t :2;
2318 vuint32_t STOP:1;
2319 vuint32_t :1;
2320 vuint32_t HALT:1;
2321 vuint32_t RUN3:1;
2322 vuint32_t RUN2:1;
2323 vuint32_t RUN1:1;
2324 vuint32_t RUN0:1;
2325 vuint32_t DRUN:1;
2326 vuint32_t SAFE:1;
2327 vuint32_t TEST:1;
2328 vuint32_t RST:1;
2329 } B;
2330 } PCONF[4];
2331
2332 vuint8_t PCU_reserved0[48]; /* Reserved 48 bytes (Base+0x0010-0x003F) */
2333
2334 union { /* PCU Power Domain Status (Base+0x0040) */
2335 vuint32_t R;
2336 struct {
2337 vuint32_t :28;
2338 vuint32_t PD3:1;
2339 vuint32_t PD2:1;
2340 vuint32_t PD1:1;
2341 vuint32_t PD0:1;
2342 } B;
2343 } PSTAT;
2344
2345 vuint8_t PCU_reserved1[60]; /* Reserved 60 bytes (Base+0x0044-0x007F) */
2346
2347
2348 /* Following registers are from Voltage Regulators chapter of RM */
2349
2350 union { /* PCU Voltage Regulator Control (Base+0x0080) */
2351 vuint32_t R;
2352 struct {
2353 vuint32_t :31;
2354 vuint32_t MASK_LVDHV5:1;
2355 } B;
2356 } VREG_CTL; /* Changed from VCTL for consistency with other regs here */
2357
2358 union { /* PCU PDMODE (Base+0x0084) */
2359 vuint32_t R;
2360 struct {
2361 vuint32_t :15;
2362 vuint32_t PORPU:1;
2363 vuint32_t :15;
2364 vuint32_t PDMODE:1;
2365 } B;
2366 } VREG_PDMODE;
2367
2368
2369}; /* end of PCU_tag */
2370/****************************************************************************/
2371/* MODULE : RTC/API */
2372/****************************************************************************/
2373struct RTC_tag{
2374
2375 union { /* RTC Supervisor Control (Base+0x0000) */
2376 vuint32_t R;
2377 struct {
2378 vuint32_t SUPV:1;
2379 vuint32_t :31;
2380 } B;
2381 } RTCSUPV ;
2382
2383 union { /* RTC Control (Base+0x0004) */
2384 vuint32_t R;
2385 struct {
2386 vuint32_t CNTEN:1;
2387 vuint32_t RTCIE:1;
2388 vuint32_t FRZEN:1;
2389 vuint32_t ROVREN:1;
2390 vuint32_t RTCVAL:12;
2391 vuint32_t APIEN:1;
2392 vuint32_t APIIE:1;
2393 vuint32_t CLKSEL:2;
2394 vuint32_t DIV512EN:1;
2395 vuint32_t DIV32EN:1;
2396 vuint32_t APIVAL:10;
2397 } B;
2398 } RTCC;
2399
2400 union { /* RTC Status (Base+0x0008) */
2401 vuint32_t R;
2402 struct {
2403 vuint32_t :2;
2404 vuint32_t RTCF:1;
2405 vuint32_t :15;
2406 vuint32_t APIF:1;
2407 vuint32_t :2;
2408 vuint32_t ROVRF:1;
2409 vuint32_t :10;
2410 } B;
2411 } RTCS;
2412
2413 union { /* RTC Counter (Base+0x000C) */
2414 vuint32_t R;
2415 struct {
2416 vuint32_t RTCCNT:32;
2417 } B;
2418 } RTCCNT;
2419
2420}; /* end of RTC_tag */
2421/****************************************************************************/
2422/* MODULE : pit */
2423/****************************************************************************/
2424struct PIT_tag {
2425
2426 union { /* PIT Module Control (Base+0x0000) */
2427 vuint32_t R;
2428 struct {
2429 vuint32_t:29;
2430 vuint32_t MDIS_RTI:1;
2431 vuint32_t MDIS:1;
2432 vuint32_t FRZ:1;
2433 } B;
2434 } PITMCR;
2435
2436 vuint8_t PIT_reserved0[236]; /* Reserved 236 Bytes (Base+0x0004-0x00EF) */
2437
2438
2439 /* RTI Config Registers (Base + 0x00F0-0x00FF) */
2440 struct {
2441
2442 union { /* RTI Timer Load Value (Offset+0x0000) */
2443 vuint32_t R;
2444 struct {
2445 vuint32_t TSV:32;
2446 } B;
2447 } LDVAL;
2448
2449 union { /* RTI Current Timer Value (Offset+0x0004) */
2450 vuint32_t R;
2451 struct {
2452 vuint32_t TVL:32;
2453 } B;
2454 } CVAL;
2455
2456 union { /* RTI Timer Control (Offset+0x0008) */
2457 vuint32_t R;
2458 struct {
2459 vuint32_t :30;
2460 vuint32_t TIE:1;
2461 vuint32_t TEN:1;
2462 } B;
2463 } TCTRL;
2464
2465 union { /* RTI Timer Flag (Offset+0x000C) */
2466 vuint32_t R;
2467 struct {
2468 vuint32_t :31;
2469 vuint32_t TIF:1;
2470 } B;
2471 } TFLG;
2472
2473 }RTI; /* End of RTI registers */
2474
2475
2476 /* PIT Timer Channels 0..7 (Base+0x0100-0x017C) */
2477 struct {
2478
2479 union { /* PIT Timer Load Value (Offset+0x0000) */
2480 vuint32_t R;
2481 struct {
2482 vuint32_t TSV:32;
2483 } B;
2484 } LDVAL;
2485
2486 union { /* PIT Current Timer Value (Offset+0x0004) */
2487 vuint32_t R;
2488 struct {
2489 vuint32_t TVL:32;
2490 } B;
2491 } CVAL;
2492
2493 union { /* PIT Timer Control (Offset+0x0008) */
2494 vuint32_t R;
2495 struct {
2496 vuint32_t :30;
2497 vuint32_t TIE:1;
2498 vuint32_t TEN:1;
2499 } B;
2500 } TCTRL;
2501
2502 union { /* PIT Timer Flag (Offset+0x000C) */
2503 vuint32_t R;
2504 struct {
2505 vuint32_t :31;
2506 vuint32_t TIF:1;
2507 } B;
2508 } TFLG;
2509
2510 }CH[8]; /* End of PIT Timer Channels */
2511
2512}; /* end of PIT_tag */
2513/****************************************************************************/
2514/* MODULE : STCU (Self-Test Control Unit) */
2515/****************************************************************************/
2516struct STCU_tag {
2517
2518 union { /* STCU Run (Base+0x0000) */
2519 vuint32_t R;
2520 struct {
2521 vuint32_t :31;
2522 vuint32_t RUN:1;
2523 } B;
2524 } RUN;
2525
2526 vuint8_t STCU_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */
2527
2528 union { /* STCU SK Code (Base+0x0008) */
2529 vuint32_t R;
2530 struct {
2531 vuint32_t SKC:32;
2532 } B;
2533 } SKC;
2534
2535 union { /* STCU Config (Base+0x000C) */
2536 vuint32_t R;
2537 struct {
2538 vuint32_t :1;
2539 vuint32_t PTR:7;
2540 vuint32_t :20;
2541 vuint32_t CLK_CFG:4;
2542 } B;
2543 } CFG;
2544
2545 union { /* STCU Watchdog Granularity (Base+0x0010) */
2546 vuint32_t R;
2547 struct {
2548 vuint32_t :29;
2549 vuint32_t GMBIST:3;
2550 } B;
2551 } WDGG;
2552
2553 union { /* STCU CRC Expected Status (Base+0x0014) */
2554 vuint32_t R;
2555 struct {
2556 vuint32_t CRCE:32;
2557 } B;
2558 } CRCE;
2559
2560 union { /* STCU CRC Read Status (Base+0x0018) */
2561 vuint32_t R;
2562 struct {
2563 vuint32_t CRCR:32;
2564 } B;
2565 } CRCR;
2566
2567 union { /* STCU Error (Base+0x001C) */
2568 vuint32_t R;
2569 struct {
2570 vuint32_t :4;
2571 vuint32_t WDTOSFM:1;
2572 vuint32_t CRCSSFM:1;
2573 vuint32_t ENGESFM:1;
2574 vuint32_t INVPSFM:1;
2575 vuint32_t :4;
2576 vuint32_t WDTOCFM:1;
2577 vuint32_t CRCSCFM:1;
2578 vuint32_t ENGECFM:1;
2579 vuint32_t INVPCFM:1;
2580 vuint32_t :5;
2581 vuint32_t CFSF:1;
2582 vuint32_t NCFSF:1;
2583 vuint32_t SIRSF:1;
2584 vuint32_t :4;
2585 vuint32_t WDTO:1;
2586 vuint32_t CRCS:1;
2587 vuint32_t ENGE:1;
2588 vuint32_t INVP:1;
2589 } B;
2590 } ERR;
2591
2592 union { /* STCU Error Key (Base+0x0020) */
2593 vuint32_t R;
2594 struct {
2595 vuint32_t ERR_SK:32;
2596 } B;
2597 } ERRK;
2598
2599 vuint8_t STCU_reserved1[24]; /* Reserved 24 bytes (Base+0x0024-0x003B) */
2600
2601 union { /* STCU MBIST Status Low (Base+0x003C) */
2602 vuint32_t R;
2603 struct {
2604 vuint32_t MBS31:1;
2605 vuint32_t MBS30:1;
2606 vuint32_t MBS29:1;
2607 vuint32_t MBS28:1;
2608 vuint32_t MBS27:1;
2609 vuint32_t MBS26:1;
2610 vuint32_t MBS25:1;
2611 vuint32_t MBS24:1;
2612 vuint32_t MBS23:1;
2613 vuint32_t MBS22:1;
2614 vuint32_t MBS21:1;
2615 vuint32_t MBS20:1;
2616 vuint32_t MBS19:1;
2617 vuint32_t MBS18:1;
2618 vuint32_t MBS17:1;
2619 vuint32_t MBS16:1;
2620 vuint32_t MBS15:1;
2621 vuint32_t MBS14:1;
2622 vuint32_t MBS13:1;
2623 vuint32_t MBS12:1;
2624 vuint32_t MBS11:1;
2625 vuint32_t MBS10:1;
2626 vuint32_t MBS9:1;
2627 vuint32_t MBS8:1;
2628 vuint32_t MBS7:1;
2629 vuint32_t MBS6:1;
2630 vuint32_t MBS5:1;
2631 vuint32_t MBS4:1;
2632 vuint32_t MBS3:1;
2633 vuint32_t MBS2:1;
2634 vuint32_t MBS1:1;
2635 vuint32_t MBS0:1;
2636 } B;
2637 } MBSL;
2638
2639 union { /* STCU MBIST Status High (Base+0x0040) */
2640 vuint32_t R;
2641 struct {
2642 vuint32_t :23;
2643 vuint32_t MBS40:1;
2644 vuint32_t MBS39:1;
2645 vuint32_t MBS38:1;
2646 vuint32_t MBS37:1;
2647 vuint32_t MBS36:1;
2648 vuint32_t MBS35:1;
2649 vuint32_t MBS34:1;
2650 vuint32_t MBS33:1;
2651 vuint32_t MBS32:1;
2652 } B;
2653 } MBSH;
2654
2655 union { /* STCU MBIST End Flag Low (Base+0x0044) */
2656 vuint32_t R;
2657 struct {
2658 vuint32_t MBE31:1;
2659 vuint32_t MBE30:1;
2660 vuint32_t MBE29:1;
2661 vuint32_t MBE28:1;
2662 vuint32_t MBE27:1;
2663 vuint32_t MBE26:1;
2664 vuint32_t MBE25:1;
2665 vuint32_t MBE24:1;
2666 vuint32_t MBE23:1;
2667 vuint32_t MBE22:1;
2668 vuint32_t MBE21:1;
2669 vuint32_t MBE20:1;
2670 vuint32_t MBE19:1;
2671 vuint32_t MBE18:1;
2672 vuint32_t MBE17:1;
2673 vuint32_t MBE16:1;
2674 vuint32_t MBE15:1;
2675 vuint32_t MBE14:1;
2676 vuint32_t MBE13:1;
2677 vuint32_t MBE12:1;
2678 vuint32_t MBE11:1;
2679 vuint32_t MBE10:1;
2680 vuint32_t MBE9:1;
2681 vuint32_t MBE8:1;
2682 vuint32_t MBE7:1;
2683 vuint32_t MBE6:1;
2684 vuint32_t MBE5:1;
2685 vuint32_t MBE4:1;
2686 vuint32_t MBE3:1;
2687 vuint32_t MBE2:1;
2688 vuint32_t MBE1:1;
2689 vuint32_t MBE0:1;
2690 } B;
2691 } MBEL;
2692
2693 union { /* STCU MBIST End Flag High (Base+0x0048) */
2694 vuint32_t R;
2695 struct {
2696 vuint32_t :23;
2697 vuint32_t MBE40:1;
2698 vuint32_t MBE39:1;
2699 vuint32_t MBE38:1;
2700 vuint32_t MBE37:1;
2701 vuint32_t MBE36:1;
2702 vuint32_t MBE35:1;
2703 vuint32_t MBE34:1;
2704 vuint32_t MBE33:1;
2705 vuint32_t MBE32:1;
2706 } B;
2707 } MBEH;
2708
2709 union { /* STCU MBIST Status End Key (Base+0x004C) */
2710 vuint32_t R;
2711 struct {
2712 vuint32_t MBSEK:32;
2713 } B;
2714 } MBSEK;
2715
2716 union { /* STCU MBIST Critical FM Low (Base+0x0050) */
2717 vuint32_t R;
2718 struct {
2719 vuint32_t MBCFM31:1;
2720 vuint32_t MBCFM30:1;
2721 vuint32_t MBCFM29:1;
2722 vuint32_t MBCFM28:1;
2723 vuint32_t MBCFM27:1;
2724 vuint32_t MBCFM26:1;
2725 vuint32_t MBCFM25:1;
2726 vuint32_t MBCFM24:1;
2727 vuint32_t MBCFM23:1;
2728 vuint32_t MBCFM22:1;
2729 vuint32_t MBCFM21:1;
2730 vuint32_t MBCFM20:1;
2731 vuint32_t MBCFM19:1;
2732 vuint32_t MBCFM18:1;
2733 vuint32_t MBCFM17:1;
2734 vuint32_t MBCFM16:1;
2735 vuint32_t MBCFM15:1;
2736 vuint32_t MBCFM14:1;
2737 vuint32_t MBCFM13:1;
2738 vuint32_t MBCFM12:1;
2739 vuint32_t MBCFM11:1;
2740 vuint32_t MBCFM10:1;
2741 vuint32_t MBCFM9:1;
2742 vuint32_t MBCFM8:1;
2743 vuint32_t MBCFM7:1;
2744 vuint32_t MBCFM6:1;
2745 vuint32_t MBCFM5:1;
2746 vuint32_t MBCFM4:1;
2747 vuint32_t MBCFM3:1;
2748 vuint32_t MBCFM2:1;
2749 vuint32_t MBCFM1:1;
2750 vuint32_t MBCFM0:1;
2751 } B;
2752 } MBCFML;
2753
2754 union { /* STCU MBIST Critical FM High (Base+0x0054) */
2755 vuint32_t R;
2756 struct {
2757 vuint32_t :23;
2758 vuint32_t MBCFM40:1;
2759 vuint32_t MBCFM39:1;
2760 vuint32_t MBCFM38:1;
2761 vuint32_t MBCFM37:1;
2762 vuint32_t MBCFM36:1;
2763 vuint32_t MBCFM35:1;
2764 vuint32_t MBCFM34:1;
2765 vuint32_t MBCFM33:1;
2766 vuint32_t MBCFM32:1;
2767 } B;
2768 } MBCFMH;
2769
2770 union { /* STCU MBIST Stay-In-Reset FM Low (Base+0x0058)*/
2771 vuint32_t R;
2772 struct {
2773 vuint32_t MBSFM31:1;
2774 vuint32_t MBSFM30:1;
2775 vuint32_t MBSFM29:1;
2776 vuint32_t MBSFM28:1;
2777 vuint32_t MBSFM27:1;
2778 vuint32_t MBSFM26:1;
2779 vuint32_t MBSFM25:1;
2780 vuint32_t MBSFM24:1;
2781 vuint32_t MBSFM23:1;
2782 vuint32_t MBSFM22:1;
2783 vuint32_t MBSFM21:1;
2784 vuint32_t MBSFM20:1;
2785 vuint32_t MBSFM19:1;
2786 vuint32_t MBSFM18:1;
2787 vuint32_t MBSFM17:1;
2788 vuint32_t MBSFM16:1;
2789 vuint32_t MBSFM15:1;
2790 vuint32_t MBSFM14:1;
2791 vuint32_t MBSFM13:1;
2792 vuint32_t MBSFM12:1;
2793 vuint32_t MBSFM11:1;
2794 vuint32_t MBSFM10:1;
2795 vuint32_t MBSFM9:1;
2796 vuint32_t MBSFM8:1;
2797 vuint32_t MBSFM7:1;
2798 vuint32_t MBSFM6:1;
2799 vuint32_t MBSFM5:1;
2800 vuint32_t MBSFM4:1;
2801 vuint32_t MBSFM3:1;
2802 vuint32_t MBSFM2:1;
2803 vuint32_t MBSFM1:1;
2804 vuint32_t MBSFM0:1;
2805 } B;
2806 } MBSFML;
2807
2808 union { /* STCU MBIST Stay-In-Reset FM High (Base+0x005C) */
2809 vuint32_t R;
2810 struct {
2811 vuint32_t :23;
2812 vuint32_t MBSFM40:1;
2813 vuint32_t MBSFM39:1;
2814 vuint32_t MBSFM38:1;
2815 vuint32_t MBSFM37:1;
2816 vuint32_t MBSFM36:1;
2817 vuint32_t MBSFM35:1;
2818 vuint32_t MBSFM34:1;
2819 vuint32_t MBSFM33:1;
2820 vuint32_t MBSFM32:1;
2821 } B;
2822 } MBSFMH;
2823
2824 union { /* STCU MBIST FM Key (Base+0x0060) */
2825 vuint32_t R;
2826 struct {
2827 vuint32_t MBFMK:32;
2828 } B;
2829 } MBFMK;
2830
2831 vuint8_t STCU_reserved2[668]; /*Reserved 668 bytes (Base+0x0064-0x02FF) */
2832
2833 union { /* STCU MBIST Comtrol (Base+0x0300) */
2834 vuint32_t R;
2835 struct {
2836 vuint32_t :1;
2837 vuint32_t PTR:7;
2838 vuint32_t :2;
2839 vuint32_t MB_TIME:6;
2840 vuint32_t :16;
2841 } B;
2842 } MBCTRL[41];
2843
2844
2845}; /* end of STCU_tag */
2846/****************************************************************************/
2847/* MODULE : ADC0 (10 Bit) */
2848/* CH[0..15], CH[32..95] */
2849/****************************************************************************/
2850struct ADC0_tag {
2851
2852 union { /* ADC0 Main Configuration (Base+0x0000) */
2853 vuint32_t R;
2854 struct {
2855 vuint32_t OWREN:1;
2856 vuint32_t WLSIDE:1;
2857 vuint32_t MODE:1;
2858 vuint32_t EDGLEV:1;
2859 vuint32_t TRGEN:1;
2860 vuint32_t EDGE:1;
2861 vuint32_t XSTRTEN:1;
2862 vuint32_t NSTART:1;
2863 vuint32_t:1;
2864 vuint32_t JTRGEN:1;
2865 vuint32_t JEDGE:1;
2866 vuint32_t JSTART:1;
2867 vuint32_t:2;
2868 vuint32_t CTUEN:1;
2869 vuint32_t:9;
2870 vuint32_t ABORT_CHAIN:1;
2871 vuint32_t ABORT:1;
2872 vuint32_t ACKO:1;
2873 vuint32_t:2;
2874 vuint32_t:2;
2875 vuint32_t PWDN:1;
2876 } B;
2877 } MCR;
2878
2879 union { /* ADC0 Main Status (Base+0x0004) */
2880 vuint32_t R;
2881 struct {
2882 vuint32_t:7;
2883 vuint32_t NSTART:1;
2884 vuint32_t JABORT:1;
2885 vuint32_t:2;
2886 vuint32_t JSTART:1;
2887 vuint32_t:3;
2888 vuint32_t CTUSTART:1;
2889 vuint32_t CHADDR:7;
2890 vuint32_t:3;
2891 vuint32_t ACKO:1;
2892 vuint32_t:2;
2893 vuint32_t ADCSTATUS:3;
2894 } B;
2895 } MSR;
2896
2897 vuint8_t ADC0_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
2898
2899 union { /* ADC0 Interrupt Status (Base+0x0010) */
2900 vuint32_t R;
2901 struct {
2902 vuint32_t:27;
2903 //vuint32_t OFFCANCOVR:1;
2904 //vuint32_t EOFFSET:1;
2905 vuint32_t EOCTU:1;
2906 vuint32_t JEOC:1;
2907 vuint32_t JECH:1;
2908 vuint32_t EOC:1;
2909 vuint32_t ECH:1;
2910 } B;
2911 } ISR;
2912
2913 union { /* ADC0 Channel Pending 0 (Base+0x0014) */
2914 vuint32_t R; /* (For precision channels) */
2915 struct {
2916 vuint32_t :16;
2917 vuint32_t EOC_CH15:1;
2918 vuint32_t EOC_CH14:1;
2919 vuint32_t EOC_CH13:1;
2920 vuint32_t EOC_CH12:1;
2921 vuint32_t EOC_CH11:1;
2922 vuint32_t EOC_CH10:1;
2923 vuint32_t EOC_CH9:1;
2924 vuint32_t EOC_CH8:1;
2925 vuint32_t EOC_CH7:1;
2926 vuint32_t EOC_CH6:1;
2927 vuint32_t EOC_CH5:1;
2928 vuint32_t EOC_CH4:1;
2929 vuint32_t EOC_CH3:1;
2930 vuint32_t EOC_CH2:1;
2931 vuint32_t EOC_CH1:1;
2932 vuint32_t EOC_CH0:1;
2933 } B;
2934 } CE0CFR0;
2935
2936 union { /* ADC0 Channel Pending 1 (Base+0x0018) */
2937 vuint32_t R; /* (For standard Channels) */
2938 struct {
2939 vuint32_t EOC_CH63:1;
2940 vuint32_t EOC_CH62:1;
2941 vuint32_t EOC_CH61:1;
2942 vuint32_t EOC_CH60:1;
2943 vuint32_t EOC_CH59:1;
2944 vuint32_t EOC_CH58:1;
2945 vuint32_t EOC_CH57:1;
2946 vuint32_t EOC_CH56:1;
2947 vuint32_t EOC_CH55:1;
2948 vuint32_t EOC_CH54:1;
2949 vuint32_t EOC_CH53:1;
2950 vuint32_t EOC_CH52:1;
2951 vuint32_t EOC_CH51:1;
2952 vuint32_t EOC_CH50:1;
2953 vuint32_t EOC_CH49:1;
2954 vuint32_t EOC_CH48:1;
2955 vuint32_t EOC_CH47:1;
2956 vuint32_t EOC_CH46:1;
2957 vuint32_t EOC_CH45:1;
2958 vuint32_t EOC_CH44:1;
2959 vuint32_t EOC_CH43:1;
2960 vuint32_t EOC_CH42:1;
2961 vuint32_t EOC_CH41:1;
2962 vuint32_t EOC_CH40:1;
2963 vuint32_t EOC_CH39:1;
2964 vuint32_t EOC_CH38:1;
2965 vuint32_t EOC_CH37:1;
2966 vuint32_t EOC_CH36:1;
2967 vuint32_t EOC_CH35:1;
2968 vuint32_t EOC_CH34:1;
2969 vuint32_t EOC_CH33:1;
2970 vuint32_t EOC_CH32:1;
2971 } B;
2972 } CE0CFR1;
2973
2974 union { /* ADC0 Channel Pending 2 (Base+0x001C) */
2975 vuint32_t R; /* (For external mux'd Channels) */
2976 struct {
2977 vuint32_t EOC_CH95:1;
2978 vuint32_t EOC_CH94:1;
2979 vuint32_t EOC_CH93:1;
2980 vuint32_t EOC_CH92:1;
2981 vuint32_t EOC_CH91:1;
2982 vuint32_t EOC_CH90:1;
2983 vuint32_t EOC_CH89:1;
2984 vuint32_t EOC_CH88:1;
2985 vuint32_t EOC_CH87:1;
2986 vuint32_t EOC_CH86:1;
2987 vuint32_t EOC_CH85:1;
2988 vuint32_t EOC_CH84:1;
2989 vuint32_t EOC_CH83:1;
2990 vuint32_t EOC_CH82:1;
2991 vuint32_t EOC_CH81:1;
2992 vuint32_t EOC_CH80:1;
2993 vuint32_t EOC_CH79:1;
2994 vuint32_t EOC_CH78:1;
2995 vuint32_t EOC_CH77:1;
2996 vuint32_t EOC_CH76:1;
2997 vuint32_t EOC_CH75:1;
2998 vuint32_t EOC_CH74:1;
2999 vuint32_t EOC_CH73:1;
3000 vuint32_t EOC_CH72:1;
3001 vuint32_t EOC_CH71:1;
3002 vuint32_t EOC_CH70:1;
3003 vuint32_t EOC_CH69:1;
3004 vuint32_t EOC_CH68:1;
3005 vuint32_t EOC_CH67:1;
3006 vuint32_t EOC_CH66:1;
3007 vuint32_t EOC_CH65:1;
3008 vuint32_t EOC_CH64:1;
3009 } B;
3010 } CE0CFR2;
3011
3012 union { /* ADC0 Interrupt Mask (Base+0020) */
3013 vuint32_t R;
3014 struct {
3015 vuint32_t:27;
3016 vuint32_t MSKEOCTU:1;
3017 vuint32_t MSKJEOC:1;
3018 vuint32_t MSKJECH:1;
3019 vuint32_t MSKEOC:1;
3020 vuint32_t MSKECH:1;
3021 } B;
3022 } IMR;
3023
3024 union { /* ADC0 Channel Interrupt Mask 0 (Base+0x0024) */
3025 vuint32_t R; /* (For Precision Channels) */
3026 struct {
3027 vuint32_t:16;
3028 vuint32_t CIM15:1;
3029 vuint32_t CIM14:1;
3030 vuint32_t CIM13:1;
3031 vuint32_t CIM12:1;
3032 vuint32_t CIM11:1;
3033 vuint32_t CIM10:1;
3034 vuint32_t CIM9:1;
3035 vuint32_t CIM8:1;
3036 vuint32_t CIM7:1;
3037 vuint32_t CIM6:1;
3038 vuint32_t CIM5:1;
3039 vuint32_t CIM4:1;
3040 vuint32_t CIM3:1;
3041 vuint32_t CIM2:1;
3042 vuint32_t CIM1:1;
3043 vuint32_t CIM0:1;
3044 } B;
3045 } CIMR0;
3046
3047 union { /* ADC0 Channel Interrupt Mask 1 (+0x0028) */
3048 vuint32_t R; /* (For Standard Channels) */
3049 struct {
3050 vuint32_t CIM63:1;
3051 vuint32_t CIM62:1;
3052 vuint32_t CIM61:1;
3053 vuint32_t CIM60:1;
3054 vuint32_t CIM59:1;
3055 vuint32_t CIM58:1;
3056 vuint32_t CIM57:1;
3057 vuint32_t CIM56:1;
3058 vuint32_t CIM55:1;
3059 vuint32_t CIM54:1;
3060 vuint32_t CIM53:1;
3061 vuint32_t CIM52:1;
3062 vuint32_t CIM51:1;
3063 vuint32_t CIM50:1;
3064 vuint32_t CIM49:1;
3065 vuint32_t CIM48:1;
3066 vuint32_t CIM47:1;
3067 vuint32_t CIM46:1;
3068 vuint32_t CIM45:1;
3069 vuint32_t CIM44:1;
3070 vuint32_t CIM43:1;
3071 vuint32_t CIM42:1;
3072 vuint32_t CIM41:1;
3073 vuint32_t CIM40:1;
3074 vuint32_t CIM39:1;
3075 vuint32_t CIM38:1;
3076 vuint32_t CIM37:1;
3077 vuint32_t CIM36:1;
3078 vuint32_t CIM35:1;
3079 vuint32_t CIM34:1;
3080 vuint32_t CIM33:1;
3081 vuint32_t CIM32:1;
3082 } B;
3083 } CIMR1;
3084
3085 union { /* ADC0 Channel Interrupt Mask 2 (+0x002C) */
3086 vuint32_t R; /* (For PExternal Mux'd Channels) */
3087 struct {
3088 vuint32_t CIM95:1;
3089 vuint32_t CIM94:1;
3090 vuint32_t CIM93:1;
3091 vuint32_t CIM92:1;
3092 vuint32_t CIM91:1;
3093 vuint32_t CIM90:1;
3094 vuint32_t CIM89:1;
3095 vuint32_t CIM88:1;
3096 vuint32_t CIM87:1;
3097 vuint32_t CIM86:1;
3098 vuint32_t CIM85:1;
3099 vuint32_t CIM84:1;
3100 vuint32_t CIM83:1;
3101 vuint32_t CIM82:1;
3102 vuint32_t CIM81:1;
3103 vuint32_t CIM80:1;
3104 vuint32_t CIM79:1;
3105 vuint32_t CIM78:1;
3106 vuint32_t CIM77:1;
3107 vuint32_t CIM76:1;
3108 vuint32_t CIM75:1;
3109 vuint32_t CIM74:1;
3110 vuint32_t CIM73:1;
3111 vuint32_t CIM72:1;
3112 vuint32_t CIM71:1;
3113 vuint32_t CIM70:1;
3114 vuint32_t CIM69:1;
3115 vuint32_t CIM68:1;
3116 vuint32_t CIM67:1;
3117 vuint32_t CIM66:1;
3118 vuint32_t CIM65:1;
3119 vuint32_t CIM64:1;
3120 } B;
3121 } CIMR2;
3122
3123 union { /* ADC0 Watchdog Threshold Interrupt Status (+0x0030)*/
3124 vuint32_t R;
3125 struct {
3126 vuint32_t:20;
3127 vuint32_t WDG5H:1;
3128 vuint32_t WDG5L:1;
3129 vuint32_t WDG4H:1;
3130 vuint32_t WDG4L:1;
3131 vuint32_t WDG3H:1;
3132 vuint32_t WDG3L:1;
3133 vuint32_t WDG2H:1;
3134 vuint32_t WDG2L:1;
3135 vuint32_t WDG1H:1;
3136 vuint32_t WDG1L:1;
3137 vuint32_t WDG0H:1;
3138 vuint32_t WDG0L:1;
3139 } B;
3140 } WTISR;
3141
3142 union { /* ADC0 Watchdog Threshold Interrupt Mask (+0x0034) */
3143 vuint32_t R;
3144 struct {
3145 vuint32_t:20;
3146 vuint32_t MSKWDG5H:1;
3147 vuint32_t MSKWDG5L:1;
3148 vuint32_t MSKWDG4H:1;
3149 vuint32_t MSKWDG4L:1;
3150 vuint32_t MSKWDG3H:1;
3151 vuint32_t MSKWDG3L:1;
3152 vuint32_t MSKWDG2H:1;
3153 vuint32_t MSKWDG2L:1;
3154 vuint32_t MSKWDG1H:1;
3155 vuint32_t MSKWDG1L:1;
3156 vuint32_t MSKWDG0H:1;
3157 vuint32_t MSKWDG0L:1;
3158 } B;
3159 } WTIMR;
3160
3161 vuint8_t ADC0_reserved1[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */
3162
3163 union { /* ADC0 DMA Enable (Base+0x0040) */
3164 vuint32_t R;
3165 struct {
3166 vuint32_t:30;
3167 vuint32_t DCLR:1;
3168 vuint32_t DMAEN:1;
3169 } B;
3170 } DMAE;
3171
3172 union { /* ADC0 DMA Channel Select 0 (Base+0x0044) */
3173 vuint32_t R; /* (for precision channels) */
3174 struct {
3175 vuint32_t:16;
3176 vuint32_t DMA15:1;
3177 vuint32_t DMA14:1;
3178 vuint32_t DMA13:1;
3179 vuint32_t DMA12:1;
3180 vuint32_t DMA11:1;
3181 vuint32_t DMA10:1;
3182 vuint32_t DMA9:1;
3183 vuint32_t DMA8:1;
3184 vuint32_t DMA7:1;
3185 vuint32_t DMA6:1;
3186 vuint32_t DMA5:1;
3187 vuint32_t DMA4:1;
3188 vuint32_t DMA3:1;
3189 vuint32_t DMA2:1;
3190 vuint32_t DMA1:1;
3191 vuint32_t DMA0:1;
3192 } B;
3193 } DMAR0;
3194
3195 union { /* ADC0 DMA Channel Select 1 (Base+0x0048) */
3196 vuint32_t R; /* (for standard channels) */
3197 struct {
3198 vuint32_t DMA63:1;
3199 vuint32_t DMA62:1;
3200 vuint32_t DMA61:1;
3201 vuint32_t DMA60:1;
3202 vuint32_t DMA59:1;
3203 vuint32_t DMA58:1;
3204 vuint32_t DMA57:1;
3205 vuint32_t DMA56:1;
3206 vuint32_t DMA55:1;
3207 vuint32_t DMA54:1;
3208 vuint32_t DMA53:1;
3209 vuint32_t DMA52:1;
3210 vuint32_t DMA51:1;
3211 vuint32_t DMA50:1;
3212 vuint32_t DMA49:1;
3213 vuint32_t DMA48:1;
3214 vuint32_t DMA47:1;
3215 vuint32_t DMA46:1;
3216 vuint32_t DMA45:1;
3217 vuint32_t DMA44:1;
3218 vuint32_t DMA43:1;
3219 vuint32_t DMA42:1;
3220 vuint32_t DMA41:1;
3221 vuint32_t DMA40:1;
3222 vuint32_t DMA39:1;
3223 vuint32_t DMA38:1;
3224 vuint32_t DMA37:1;
3225 vuint32_t DMA36:1;
3226 vuint32_t DMA35:1;
3227 vuint32_t DMA34:1;
3228 vuint32_t DMA33:1;
3229 vuint32_t DMA32:1;
3230 } B;
3231 } DMAR1;
3232
3233 union { /* ADC0 DMA Channel Select 2 (Base+0x004C) */
3234 vuint32_t R; /* (for external mux'd channels) */
3235 struct {
3236 vuint32_t DMA95:1;
3237 vuint32_t DMA94:1;
3238 vuint32_t DMA93:1;
3239 vuint32_t DMA92:1;
3240 vuint32_t DMA91:1;
3241 vuint32_t DMA90:1;
3242 vuint32_t DMA89:1;
3243 vuint32_t DMA88:1;
3244 vuint32_t DMA87:1;
3245 vuint32_t DMA86:1;
3246 vuint32_t DMA85:1;
3247 vuint32_t DMA84:1;
3248 vuint32_t DMA83:1;
3249 vuint32_t DMA82:1;
3250 vuint32_t DMA81:1;
3251 vuint32_t DMA80:1;
3252 vuint32_t DMA79:1;
3253 vuint32_t DMA78:1;
3254 vuint32_t DMA77:1;
3255 vuint32_t DMA76:1;
3256 vuint32_t DMA75:1;
3257 vuint32_t DMA74:1;
3258 vuint32_t DMA73:1;
3259 vuint32_t DMA72:1;
3260 vuint32_t DMA71:1;
3261 vuint32_t DMA70:1;
3262 vuint32_t DMA69:1;
3263 vuint32_t DMA68:1;
3264 vuint32_t DMA67:1;
3265 vuint32_t DMA66:1;
3266 vuint32_t DMA65:1;
3267 vuint32_t DMA64:1;
3268 } B;
3269 } DMAR2;
3270
3271 vuint8_t ADC0_reserved2[16]; /* Reserved 16 bytes (Base+0x0050-0x005F) */
3272
3273 /* Note the threshold registers are split [0..3] then [4..5]. For this */
3274 /* reason thay are NOT implemented as an array in order to maintain */
3275 /* concistency through all THRHLR registers */
3276
3277 union { /* ADC0 Threshold 0 (Base+0x0060) */
3278 vuint32_t R;
3279 struct {
3280 vuint32_t:6;
3281 vuint32_t THRH:10;
3282 vuint32_t:6;
3283 vuint32_t THRL:10;
3284 } B;
3285 } THRHLR0;
3286
3287 union { /* ADC0 Threshold 1 (Base+0x0064) */
3288 vuint32_t R;
3289 struct {
3290 vuint32_t:6;
3291 vuint32_t THRH:10;
3292 vuint32_t:6;
3293 vuint32_t THRL:10;
3294 } B;
3295 } THRHLR1;
3296
3297 union { /* ADC0 Threshold 2 (Base+0x0068) */
3298 vuint32_t R;
3299 struct {
3300 vuint32_t:6;
3301 vuint32_t THRH:10;
3302 vuint32_t:6;
3303 vuint32_t THRL:10;
3304 } B;
3305 } THRHLR2;
3306
3307 union { /* ADC0 Threshold 3 (Base+0x006C) */
3308 vuint32_t R;
3309 struct {
3310 vuint32_t:6;
3311 vuint32_t THRH:10;
3312 vuint32_t:6;
3313 vuint32_t THRL:10;
3314 } B;
3315 } THRHLR3;
3316
3317 vuint8_t ADC0_reserved3[16]; /* Reserved 16 bytes (Base+0x0070-0x007F) */
3318
3319 union { /* ADC0 Presampling Control (Base+0x0080) */
3320 vuint32_t R;
3321 struct {
3322 vuint32_t:25;
3323 vuint32_t PREVAL2:2;
3324 vuint32_t PREVAL1:2;
3325 vuint32_t PREVAL0:2;
3326 vuint32_t PRECONV:1;
3327 } B;
3328 } PSCR;
3329
3330 union { /* ADC0 Presampling 0 (Base+0x0084) */
3331 vuint32_t R; /* (precision channels) */
3332 struct {
3333 vuint32_t:16;
3334 vuint32_t PRES15:1;
3335 vuint32_t PRES14:1;
3336 vuint32_t PRES13:1;
3337 vuint32_t PRES12:1;
3338 vuint32_t PRES11:1;
3339 vuint32_t PRES10:1;
3340 vuint32_t PRES9:1;
3341 vuint32_t PRES8:1;
3342 vuint32_t PRES7:1;
3343 vuint32_t PRES6:1;
3344 vuint32_t PRES5:1;
3345 vuint32_t PRES4:1;
3346 vuint32_t PRES3:1;
3347 vuint32_t PRES2:1;
3348 vuint32_t PRES1:1;
3349 vuint32_t PRES0:1;
3350 } B;
3351 } PSR0;
3352
3353 union { /* ADC0 Presampling 1 (Base+0x0088) */
3354 vuint32_t R; /* (standard channels) */
3355 struct {
3356 vuint32_t PRES63:1;
3357 vuint32_t PRES62:1;
3358 vuint32_t PRES61:1;
3359 vuint32_t PRES60:1;
3360 vuint32_t PRES59:1;
3361 vuint32_t PRES58:1;
3362 vuint32_t PRES57:1;
3363 vuint32_t PRES56:1;
3364 vuint32_t PRES55:1;
3365 vuint32_t PRES54:1;
3366 vuint32_t PRES53:1;
3367 vuint32_t PRES52:1;
3368 vuint32_t PRES51:1;
3369 vuint32_t PRES50:1;
3370 vuint32_t PRES49:1;
3371 vuint32_t PRES48:1;
3372 vuint32_t PRES47:1;
3373 vuint32_t PRES46:1;
3374 vuint32_t PRES45:1;
3375 vuint32_t PRES44:1;
3376 vuint32_t PRES43:1;
3377 vuint32_t PRES42:1;
3378 vuint32_t PRES41:1;
3379 vuint32_t PRES40:1;
3380 vuint32_t PRES39:1;
3381 vuint32_t PRES38:1;
3382 vuint32_t PRES37:1;
3383 vuint32_t PRES36:1;
3384 vuint32_t PRES35:1;
3385 vuint32_t PRES34:1;
3386 vuint32_t PRES33:1;
3387 vuint32_t PRES32:1;
3388 } B;
3389 } PSR1;
3390
3391 union { /* ADC0 Presampling 2 (Base+0x008C) */
3392 vuint32_t R; /* (external mux'd channels) */
3393 struct {
3394 vuint32_t PRES95:1;
3395 vuint32_t PRES94:1;
3396 vuint32_t PRES93:1;
3397 vuint32_t PRES92:1;
3398 vuint32_t PRES91:1;
3399 vuint32_t PRES90:1;
3400 vuint32_t PRES89:1;
3401 vuint32_t PRES88:1;
3402 vuint32_t PRES87:1;
3403 vuint32_t PRES86:1;
3404 vuint32_t PRES85:1;
3405 vuint32_t PRES84:1;
3406 vuint32_t PRES83:1;
3407 vuint32_t PRES82:1;
3408 vuint32_t PRES81:1;
3409 vuint32_t PRES80:1;
3410 vuint32_t PRES79:1;
3411 vuint32_t PRES78:1;
3412 vuint32_t PRES77:1;
3413 vuint32_t PRES76:1;
3414 vuint32_t PRES75:1;
3415 vuint32_t PRES74:1;
3416 vuint32_t PRES73:1;
3417 vuint32_t PRES72:1;
3418 vuint32_t PRES71:1;
3419 vuint32_t PRES70:1;
3420 vuint32_t PRES69:1;
3421 vuint32_t PRES68:1;
3422 vuint32_t PRES67:1;
3423 vuint32_t PRES66:1;
3424 vuint32_t PRES65:1;
3425 vuint32_t PRES64:1;
3426 } B;
3427 } PSR2;
3428
3429 vuint8_t ADC0_reserved4[4]; /* Reserved 4 bytes (Base+0x0090-0x0093) */
3430
3431 /* Note the following CTR registers are NOT implemented as an array to */
3432 /* try and maintain some concistency through the header file */
3433 /* (The registers are however identical) */
3434
3435 union { /* ADC0 Conversion Timing 0 (Base+0x0094) */
3436 vuint32_t R; /* (precision channels) */
3437 struct {
3438 vuint32_t:16;
3439 vuint32_t INPLATCH:1;
3440 vuint32_t:1;
3441 vuint32_t OFFSHIFT:2;
3442 vuint32_t:1;
3443 vuint32_t INPCMP:2;
3444 vuint32_t:1;
3445 vuint32_t INPSAMP:8;
3446 } B;
3447 } CTR0;
3448
3449 union { /* ADC0 Conversion Timing 1 (Base+0x0098) */
3450 vuint32_t R; /* (standard channels) */
3451 struct {
3452 vuint32_t:16;
3453 vuint32_t INPLATCH:1;
3454 vuint32_t:1;
3455 vuint32_t OFFSHIFT:2;
3456 vuint32_t:1;
3457 vuint32_t INPCMP:2;
3458 vuint32_t:1;
3459 vuint32_t INPSAMP:8;
3460 } B;
3461 } CTR1;
3462
3463 union { /* ADC0 Conversion Timing 2 (Base+0x009C) */
3464 vuint32_t R; /* (precision channels) */
3465 struct {
3466 vuint32_t:16;
3467 vuint32_t INPLATCH:1;
3468 vuint32_t:1;
3469 vuint32_t OFFSHIFT:2;
3470 vuint32_t:1;
3471 vuint32_t INPCMP:2;
3472 vuint32_t:1;
3473 vuint32_t INPSAMP:8;
3474 } B;
3475 } CTR2;
3476
3477 vuint8_t ADC0_reserved5[4]; /* Reserved 4 bytes (Base+0x00A0-0x00A3) */
3478
3479 union { /* ADC0 Normal Conversion Mask 0 (Base+0x00A4) */
3480 vuint32_t R; /* (precision channels) */
3481 struct {
3482 vuint32_t :16;
3483 vuint32_t CH15:1;
3484 vuint32_t CH14:1;
3485 vuint32_t CH13:1;
3486 vuint32_t CH12:1;
3487 vuint32_t CH11:1;
3488 vuint32_t CH10:1;
3489 vuint32_t CH9:1;
3490 vuint32_t CH8:1;
3491 vuint32_t CH7:1;
3492 vuint32_t CH6:1;
3493 vuint32_t CH5:1;
3494 vuint32_t CH4:1;
3495 vuint32_t CH3:1;
3496 vuint32_t CH2:1;
3497 vuint32_t CH1:1;
3498 vuint32_t CH0:1;
3499 } B;
3500 } NCMR0;
3501
3502 union { /* ADC0 Normal Conversion Mask 1 (Base+0x00A8) */
3503 vuint32_t R; /* (standard channels) */
3504 struct {
3505 vuint32_t CH63:1;
3506 vuint32_t CH62:1;
3507 vuint32_t CH61:1;
3508 vuint32_t CH60:1;
3509 vuint32_t CH59:1;
3510 vuint32_t CH58:1;
3511 vuint32_t CH57:1;
3512 vuint32_t CH56:1;
3513 vuint32_t CH55:1;
3514 vuint32_t CH54:1;
3515 vuint32_t CH53:1;
3516 vuint32_t CH52:1;
3517 vuint32_t CH51:1;
3518 vuint32_t CH50:1;
3519 vuint32_t CH49:1;
3520 vuint32_t CH48:1;
3521 vuint32_t CH47:1;
3522 vuint32_t CH46:1;
3523 vuint32_t CH45:1;
3524 vuint32_t CH44:1;
3525 vuint32_t CH43:1;
3526 vuint32_t CH42:1;
3527 vuint32_t CH41:1;
3528 vuint32_t CH40:1;
3529 vuint32_t CH39:1;
3530 vuint32_t CH38:1;
3531 vuint32_t CH37:1;
3532 vuint32_t CH36:1;
3533 vuint32_t CH35:1;
3534 vuint32_t CH34:1;
3535 vuint32_t CH33:1;
3536 vuint32_t CH32:1;
3537 } B;
3538 } NCMR1;
3539
3540 union { /* ADC0 Normal Conversion Mask 2 (Base+0x00AC) */
3541 vuint32_t R; /* (For external mux'd channels) */
3542 struct {
3543 vuint32_t CH95:1;
3544 vuint32_t CH94:1;
3545 vuint32_t CH93:1;
3546 vuint32_t CH92:1;
3547 vuint32_t CH91:1;
3548 vuint32_t CH90:1;
3549 vuint32_t CH89:1;
3550 vuint32_t CH88:1;
3551 vuint32_t CH87:1;
3552 vuint32_t CH86:1;
3553 vuint32_t CH85:1;
3554 vuint32_t CH84:1;
3555 vuint32_t CH83:1;
3556 vuint32_t CH82:1;
3557 vuint32_t CH81:1;
3558 vuint32_t CH80:1;
3559 vuint32_t CH79:1;
3560 vuint32_t CH78:1;
3561 vuint32_t CH77:1;
3562 vuint32_t CH76:1;
3563 vuint32_t CH75:1;
3564 vuint32_t CH74:1;
3565 vuint32_t CH73:1;
3566 vuint32_t CH72:1;
3567 vuint32_t CH71:1;
3568 vuint32_t CH70:1;
3569 vuint32_t CH69:1;
3570 vuint32_t CH68:1;
3571 vuint32_t CH67:1;
3572 vuint32_t CH66:1;
3573 vuint32_t CH65:1;
3574 vuint32_t CH64:1;
3575 } B;
3576 } NCMR2;
3577
3578 vuint8_t ADC0_reserved6[4]; /* Reserved 4 bytes (Base+0x00B0-0x00B3) */
3579
3580 union { /* ADC0 Injected Conversion Mask0 (Base+0x00B4) */
3581 vuint32_t R; /* (precision channels) */
3582 struct {
3583 vuint32_t :16;
3584 vuint32_t CH15:1;
3585 vuint32_t CH14:1;
3586 vuint32_t CH13:1;
3587 vuint32_t CH12:1;
3588 vuint32_t CH11:1;
3589 vuint32_t CH10:1;
3590 vuint32_t CH9:1;
3591 vuint32_t CH8:1;
3592 vuint32_t CH7:1;
3593 vuint32_t CH6:1;
3594 vuint32_t CH5:1;
3595 vuint32_t CH4:1;
3596 vuint32_t CH3:1;
3597 vuint32_t CH2:1;
3598 vuint32_t CH1:1;
3599 vuint32_t CH0:1;
3600 } B;
3601 } JCMR0;
3602
3603 union { /* ADC0 Injected Conversion Mask1 (Base+0x00B8) */
3604 vuint32_t R; /* (standard channels) */
3605 struct {
3606 vuint32_t CH63:1;
3607 vuint32_t CH62:1;
3608 vuint32_t CH61:1;
3609 vuint32_t CH60:1;
3610 vuint32_t CH59:1;
3611 vuint32_t CH58:1;
3612 vuint32_t CH57:1;
3613 vuint32_t CH56:1;
3614 vuint32_t CH55:1;
3615 vuint32_t CH54:1;
3616 vuint32_t CH53:1;
3617 vuint32_t CH52:1;
3618 vuint32_t CH51:1;
3619 vuint32_t CH50:1;
3620 vuint32_t CH49:1;
3621 vuint32_t CH48:1;
3622 vuint32_t CH47:1;
3623 vuint32_t CH46:1;
3624 vuint32_t CH45:1;
3625 vuint32_t CH44:1;
3626 vuint32_t CH43:1;
3627 vuint32_t CH42:1;
3628 vuint32_t CH41:1;
3629 vuint32_t CH40:1;
3630 vuint32_t CH39:1;
3631 vuint32_t CH38:1;
3632 vuint32_t CH37:1;
3633 vuint32_t CH36:1;
3634 vuint32_t CH35:1;
3635 vuint32_t CH34:1;
3636 vuint32_t CH33:1;
3637 vuint32_t CH32:1;
3638 } B;
3639 } JCMR1;
3640
3641 union { /* ADC0 Injected Conversion Mask2 (Base+0x00BC) */
3642 vuint32_t R; /* (external mux'd channels) */
3643 struct {
3644 vuint32_t CH95:1;
3645 vuint32_t CH94:1;
3646 vuint32_t CH93:1;
3647 vuint32_t CH92:1;
3648 vuint32_t CH91:1;
3649 vuint32_t CH90:1;
3650 vuint32_t CH89:1;
3651 vuint32_t CH88:1;
3652 vuint32_t CH87:1;
3653 vuint32_t CH86:1;
3654 vuint32_t CH85:1;
3655 vuint32_t CH84:1;
3656 vuint32_t CH83:1;
3657 vuint32_t CH82:1;
3658 vuint32_t CH81:1;
3659 vuint32_t CH80:1;
3660 vuint32_t CH79:1;
3661 vuint32_t CH78:1;
3662 vuint32_t CH77:1;
3663 vuint32_t CH76:1;
3664 vuint32_t CH75:1;
3665 vuint32_t CH74:1;
3666 vuint32_t CH73:1;
3667 vuint32_t CH72:1;
3668 vuint32_t CH71:1;
3669 vuint32_t CH70:1;
3670 vuint32_t CH69:1;
3671 vuint32_t CH68:1;
3672 vuint32_t CH67:1;
3673 vuint32_t CH66:1;
3674 vuint32_t CH65:1;
3675 vuint32_t CH64:1;
3676 } B;
3677 } JCMR2;
3678
3679 vuint8_t ADC0_reserved7[4]; /* Reserved 4 bytes (Base+0x00C0-0x00C3) */
3680
3681 union { /* ADC0 Decode Signals Delay (Base+0x00C4) */
3682 vuint32_t R;
3683 struct {
3684 vuint32_t:20;
3685 vuint32_t DSD:12;
3686 } B;
3687 } DSDR;
3688
3689 union { /* ADC0 Power-Down exit Delay (Base+0x00C8) */
3690 vuint32_t R;
3691 struct {
3692 vuint32_t:24;
3693 vuint32_t PDED:8;
3694 } B;
3695 } PDEDR;
3696
3697 vuint8_t ADC0_reserved8[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */
3698
3699 union { /* ADC0 Channel 0-95 Data (Base+0x0100-0x027C) */
3700 vuint32_t R; /* Note CDR[16..31] are reserved */
3701 struct {
3702 vuint32_t:12;
3703 vuint32_t VALID:1;
3704 vuint32_t OVERW:1;
3705 vuint32_t RESULT:2;
3706 vuint32_t:6;
3707 vuint32_t CDATA:10;
3708 } B;
3709 } CDR[96];
3710
3711 union { /* ADC0 Threshold 4 (Base+0x0280) */
3712 vuint32_t R;
3713 struct {
3714 vuint32_t:6;
3715 vuint32_t THRH:10;
3716 vuint32_t:6;
3717 vuint32_t THRL:10;
3718 } B;
3719 } THRHLR4;
3720
3721 union { /* ADC0 Threshold 5 (Base+0x0284) */
3722 vuint32_t R;
3723 struct {
3724 vuint32_t:6;
3725 vuint32_t THRH:10;
3726 vuint32_t:6;
3727 vuint32_t THRL:10;
3728 } B;
3729 } THRHLR5;
3730
3731 vuint8_t ADC0_reserved10[40]; /* Reserved 40 bytes (Base+0x0288-0x02AF) */
3732
3733 union { /* ADC0 Channel Watchdog Select 0 (Base+0x02B0) */
3734 vuint32_t R; /* (precision channels) */
3735 struct {
3736 vuint32_t:1;
3737 vuint32_t WSEL_CH7:3;
3738 vuint32_t:1;
3739 vuint32_t WSEL_CH6:3;
3740 vuint32_t:1;
3741 vuint32_t WSEL_CH5:3;
3742 vuint32_t:1;
3743 vuint32_t WSEL_CH4:3;
3744 vuint32_t:1;
3745 vuint32_t WSEL_CH3:3;
3746 vuint32_t:1;
3747 vuint32_t WSEL_CH2:3;
3748 vuint32_t:1;
3749 vuint32_t WSEL_CH1:3;
3750 vuint32_t:1;
3751 vuint32_t WSEL_CH0:3;
3752 } B;
3753 } CWSELR0;
3754
3755 union { /* ADC0 Channel Watchdog Select 1 (Base+0x02B4) */
3756 vuint32_t R; /* (precision channels) */
3757 struct {
3758 vuint32_t:1;
3759 vuint32_t WSEL_CH15:3;
3760 vuint32_t:1;
3761 vuint32_t WSEL_CH14:3;
3762 vuint32_t:1;
3763 vuint32_t WSEL_CH13:3;
3764 vuint32_t:1;
3765 vuint32_t WSEL_CH12:3;
3766 vuint32_t:1;
3767 vuint32_t WSEL_CH11:3;
3768 vuint32_t:1;
3769 vuint32_t WSEL_CH10:3;
3770 vuint32_t:1;
3771 vuint32_t WSEL_CH9:3;
3772 vuint32_t:1;
3773 vuint32_t WSEL_CH8:3;
3774 } B;
3775 } CWSELR1;
3776
3777 vuint8_t ADC0_reserved11[8]; /* Reserved 8 bytes (Base+0x02B8-0x02BF) */
3778
3779 union { /* ADC0 Channel Watchdog Select 4 (Base+0x02C0) */
3780 vuint32_t R; /* (standard channels) */
3781 struct {
3782 vuint32_t:1;
3783 vuint32_t WSEL_CH39:3;
3784 vuint32_t:1;
3785 vuint32_t WSEL_CH38:3;
3786 vuint32_t:1;
3787 vuint32_t WSEL_CH37:3;
3788 vuint32_t:1;
3789 vuint32_t WSEL_CH36:3;
3790 vuint32_t:1;
3791 vuint32_t WSEL_CH35:3;
3792 vuint32_t:1;
3793 vuint32_t WSEL_CH34:3;
3794 vuint32_t:1;
3795 vuint32_t WSEL_CH33:3;
3796 vuint32_t:1;
3797 vuint32_t WSEL_CH32:3;
3798 } B;
3799 } CWSELR4;
3800
3801 union { /* ADC0 Channel Watchdog Select 5 (Base+0x02C4) */
3802 vuint32_t R; /* (standard channels) */
3803 struct {
3804 vuint32_t:1;
3805 vuint32_t WSEL_CH47:3;
3806 vuint32_t:1;
3807 vuint32_t WSEL_CH46:3;
3808 vuint32_t:1;
3809 vuint32_t WSEL_CH45:3;
3810 vuint32_t:1;
3811 vuint32_t WSEL_CH44:3;
3812 vuint32_t:1;
3813 vuint32_t WSEL_CH43:3;
3814 vuint32_t:1;
3815 vuint32_t WSEL_CH42:3;
3816 vuint32_t:1;
3817 vuint32_t WSEL_CH41:3;
3818 vuint32_t:1;
3819 vuint32_t WSEL_CH40:3;
3820 } B;
3821 } CWSELR5;
3822
3823 union { /* ADC0 Channel Watchdog Select 6 (Base+0x02C8) */
3824 vuint32_t R; /* (standard channels) */
3825 struct {
3826 vuint32_t:1;
3827 vuint32_t WSEL_CH55:3;
3828 vuint32_t:1;
3829 vuint32_t WSEL_CH54:3;
3830 vuint32_t:1;
3831 vuint32_t WSEL_CH53:3;
3832 vuint32_t:1;
3833 vuint32_t WSEL_CH52:3;
3834 vuint32_t:1;
3835 vuint32_t WSEL_CH51:3;
3836 vuint32_t:1;
3837 vuint32_t WSEL_CH50:3;
3838 vuint32_t:1;
3839 vuint32_t WSEL_CH49:3;
3840 vuint32_t:1;
3841 vuint32_t WSEL_CH48:3;
3842 } B;
3843 } CWSELR6;
3844
3845 union { /* ADC0 Channel Watchdog Select 7 (Base+0x02CC) */
3846 vuint32_t R; /* (standard channels) */
3847 struct {
3848 vuint32_t:1;
3849 vuint32_t WSEL_CH63:3;
3850 vuint32_t:1;
3851 vuint32_t WSEL_CH62:3;
3852 vuint32_t:1;
3853 vuint32_t WSEL_CH61:3;
3854 vuint32_t:1;
3855 vuint32_t WSEL_CH60:3;
3856 vuint32_t:1;
3857 vuint32_t WSEL_CH59:3;
3858 vuint32_t:1;
3859 vuint32_t WSEL_CH58:3;
3860 vuint32_t:1;
3861 vuint32_t WSEL_CH57:3;
3862 vuint32_t:1;
3863 vuint32_t WSEL_CH56:3;
3864 } B;
3865 } CWSELR7;
3866
3867 union { /* ADC0 Channel Watchdog Select 8 (Base+0x02D0) */
3868 vuint32_t R; /* (external mux'd channels) */
3869 struct {
3870 vuint32_t:1;
3871 vuint32_t WSEL_CH71:3;
3872 vuint32_t:1;
3873 vuint32_t WSEL_CH70:3;
3874 vuint32_t:1;
3875 vuint32_t WSEL_CH69:3;
3876 vuint32_t:1;
3877 vuint32_t WSEL_CH68:3;
3878 vuint32_t:1;
3879 vuint32_t WSEL_CH67:3;
3880 vuint32_t:1;
3881 vuint32_t WSEL_CH66:3;
3882 vuint32_t:1;
3883 vuint32_t WSEL_CH65:3;
3884 vuint32_t:1;
3885 vuint32_t WSEL_CH64:3;
3886 } B;
3887 } CWSELR8;
3888
3889 union { /* ADC0 Channel Watchdog Select 9 (Base+0x02D4) */
3890 vuint32_t R; /* (external mux'd channels) */
3891 struct {
3892 vuint32_t:1;
3893 vuint32_t WSEL_CH79:3;
3894 vuint32_t:1;
3895 vuint32_t WSEL_CH78:3;
3896 vuint32_t:1;
3897 vuint32_t WSEL_CH77:3;
3898 vuint32_t:1;
3899 vuint32_t WSEL_CH76:3;
3900 vuint32_t:1;
3901 vuint32_t WSEL_CH75:3;
3902 vuint32_t:1;
3903 vuint32_t WSEL_CH74:3;
3904 vuint32_t:1;
3905 vuint32_t WSEL_CH73:3;
3906 vuint32_t:1;
3907 vuint32_t WSEL_CH72:3;
3908 } B;
3909 } CWSELR9;
3910
3911 union { /* ADC0 Channel Watchdog Select 10 (Base+0x02D8)*/
3912 vuint32_t R; /* (external mux'd channels) */
3913 struct {
3914 vuint32_t:1;
3915 vuint32_t WSEL_CH87:3;
3916 vuint32_t:1;
3917 vuint32_t WSEL_CH86:3;
3918 vuint32_t:1;
3919 vuint32_t WSEL_CH85:3;
3920 vuint32_t:1;
3921 vuint32_t WSEL_CH84:3;
3922 vuint32_t:1;
3923 vuint32_t WSEL_CH83:3;
3924 vuint32_t:1;
3925 vuint32_t WSEL_CH82:3;
3926 vuint32_t:1;
3927 vuint32_t WSEL_CH81:3;
3928 vuint32_t:1;
3929 vuint32_t WSEL_CH80:3;
3930 } B;
3931 } CWSELR10;
3932
3933 union { /* ADC0 Channel Watchdog Select 11 (Base+0x02DC)*/
3934 vuint32_t R; /* (external mux'd channels) */
3935 struct {
3936 vuint32_t:1;
3937 vuint32_t WSEL_CH95:3;
3938 vuint32_t:1;
3939 vuint32_t WSEL_CH94:3;
3940 vuint32_t:1;
3941 vuint32_t WSEL_CH93:3;
3942 vuint32_t:1;
3943 vuint32_t WSEL_CH92:3;
3944 vuint32_t:1;
3945 vuint32_t WSEL_CH91:3;
3946 vuint32_t:1;
3947 vuint32_t WSEL_CH90:3;
3948 vuint32_t:1;
3949 vuint32_t WSEL_CH89:3;
3950 vuint32_t:1;
3951 vuint32_t WSEL_CH88:3;
3952 } B;
3953 } CWSELR11;
3954
3955 union { /* ADC0 Channel Watchdog Enable0 (Base++0x02E0) */
3956 vuint32_t R; /* (precision channels) */
3957 struct {
3958 vuint32_t :16;
3959 vuint32_t CWEN15:1;
3960 vuint32_t CWEN14:1;
3961 vuint32_t CWEN13:1;
3962 vuint32_t CWEN12:1;
3963 vuint32_t CWEN11:1;
3964 vuint32_t CWEN10:1;
3965 vuint32_t CWEN9:1;
3966 vuint32_t CWEN8:1;
3967 vuint32_t CWEN7:1;
3968 vuint32_t CWEN6:1;
3969 vuint32_t CWEN5:1;
3970 vuint32_t CWEN4:1;
3971 vuint32_t CWEN3:1;
3972 vuint32_t CWEN2:1;
3973 vuint32_t CWEN1:1;
3974 vuint32_t CWEN0:1;
3975 } B;
3976 } CWENR0;
3977
3978 union { /* ADC0 Channel Watchdog Enable1 (Base++0x02E4) */
3979 vuint32_t R; /* (standard channels) */
3980 struct {
3981 vuint32_t CWEN63:1;
3982 vuint32_t CWEN62:1;
3983 vuint32_t CWEN61:1;
3984 vuint32_t CWEN60:1;
3985 vuint32_t CWEN59:1;
3986 vuint32_t CWEN58:1;
3987 vuint32_t CWEN57:1;
3988 vuint32_t CWEN56:1;
3989 vuint32_t CWEN55:1;
3990 vuint32_t CWEN54:1;
3991 vuint32_t CWEN53:1;
3992 vuint32_t CWEN52:1;
3993 vuint32_t CWEN51:1;
3994 vuint32_t CWEN50:1;
3995 vuint32_t CWEN49:1;
3996 vuint32_t CWEN48:1;
3997 vuint32_t CWEN47:1;
3998 vuint32_t CWEN46:1;
3999 vuint32_t CWEN45:1;
4000 vuint32_t CWEN44:1;
4001 vuint32_t CWEN43:1;
4002 vuint32_t CWEN42:1;
4003 vuint32_t CWEN41:1;
4004 vuint32_t CWEN40:1;
4005 vuint32_t CWEN39:1;
4006 vuint32_t CWEN38:1;
4007 vuint32_t CWEN37:1;
4008 vuint32_t CWEN36:1;
4009 vuint32_t CWEN35:1;
4010 vuint32_t CWEN34:1;
4011 vuint32_t CWEN33:1;
4012 vuint32_t CWEN32:1;
4013 } B;
4014 } CWENR1;
4015
4016 union { /* ADC0 Channel Watchdog Enable2 (Base++0x02E8) */
4017 vuint32_t R; /* (external mux'd channels) */
4018 struct {
4019 vuint32_t CWEN95:1;
4020 vuint32_t CWEN94:1;
4021 vuint32_t CWEN93:1;
4022 vuint32_t CWEN92:1;
4023 vuint32_t CWEN91:1;
4024 vuint32_t CWEN90:1;
4025 vuint32_t CWEN89:1;
4026 vuint32_t CWEN88:1;
4027 vuint32_t CWEN87:1;
4028 vuint32_t CWEN86:1;
4029 vuint32_t CWEN85:1;
4030 vuint32_t CWEN84:1;
4031 vuint32_t CWEN83:1;
4032 vuint32_t CWEN82:1;
4033 vuint32_t CWEN81:1;
4034 vuint32_t CWEN80:1;
4035 vuint32_t CWEN79:1;
4036 vuint32_t CWEN78:1;
4037 vuint32_t CWEN77:1;
4038 vuint32_t CWEN76:1;
4039 vuint32_t CWEN75:1;
4040 vuint32_t CWEN74:1;
4041 vuint32_t CWEN73:1;
4042 vuint32_t CWEN72:1;
4043 vuint32_t CWEN71:1;
4044 vuint32_t CWEN70:1;
4045 vuint32_t CWEN69:1;
4046 vuint32_t CWEN68:1;
4047 vuint32_t CWEN67:1;
4048 vuint32_t CWEN66:1;
4049 vuint32_t CWEN65:1;
4050 vuint32_t CWEN64:1;
4051 } B;
4052 } CWENR2;
4053
4054 vuint8_t ADC0_reserved12[4]; /* Reserved 4 bytes (Base+0x02EC-0x02EF) */
4055
4056 union { /* ADC0 Watchdog out of range 0 (Base+0x02F0) */
4057 vuint32_t R;
4058 struct {
4059 vuint32_t :16;
4060 vuint32_t AWOR_CH15:1;
4061 vuint32_t AWOR_CH14:1;
4062 vuint32_t AWOR_CH13:1;
4063 vuint32_t AWOR_CH12:1;
4064 vuint32_t AWOR_CH11:1;
4065 vuint32_t AWOR_CH10:1;
4066 vuint32_t AWOR_CH9:1;
4067 vuint32_t AWOR_CH8:1;
4068 vuint32_t AWOR_CH7:1;
4069 vuint32_t AWOR_CH6:1;
4070 vuint32_t AWOR_CH5:1;
4071 vuint32_t AWOR_CH4:1;
4072 vuint32_t AWOR_CH3:1;
4073 vuint32_t AWOR_CH2:1;
4074 vuint32_t AWOR_CH1:1;
4075 vuint32_t AWOR_CH0:1;
4076 } B;
4077 } AWORR0;
4078
4079 union { /* ADC0 Watchdog out of range 1 (Base+0x02F4) */
4080 vuint32_t R;
4081 struct {
4082 vuint32_t AWORR_CH63:1;
4083 vuint32_t AWORR_CH62:1;
4084 vuint32_t AWORR_CH61:1;
4085 vuint32_t AWOR_CH60:1;
4086 vuint32_t AWOR_CH59:1;
4087 vuint32_t AWOR_CH58:1;
4088 vuint32_t AWOR_CH57:1;
4089 vuint32_t AWOR_CH56:1;
4090 vuint32_t AWOR_CH55:1;
4091 vuint32_t AWOR_CH54:1;
4092 vuint32_t AWOR_CH53:1;
4093 vuint32_t AWOR_CH52:1;
4094 vuint32_t AWOR_CH51:1;
4095 vuint32_t AWOR_CH50:1;
4096 vuint32_t AWOR_CH49:1;
4097 vuint32_t AWOR_CH48:1;
4098 vuint32_t AWOR_CH47:1;
4099 vuint32_t AWOR_CH46:1;
4100 vuint32_t AWOR_CH45:1;
4101 vuint32_t AWOR_CH44:1;
4102 vuint32_t AWOR_CH43:1;
4103 vuint32_t AWOR_CH42:1;
4104 vuint32_t AWOR_CH41:1;
4105 vuint32_t AWOR_CH40:1;
4106 vuint32_t AWOR_CH39:1;
4107 vuint32_t AWOR_CH38:1;
4108 vuint32_t AWOR_CH37:1;
4109 vuint32_t AWOR_CH36:1;
4110 vuint32_t AWOR_CH35:1;
4111 vuint32_t AWOR_CH34:1;
4112 vuint32_t AWOR_CH33:1;
4113 vuint32_t AWOR_CH32:1;
4114 } B;
4115 } AWORR1;
4116
4117 union { /* ADC0 Watchdog out of range 2 (Base+0x02F8) */
4118 vuint32_t R;
4119 struct {
4120 vuint32_t AWOR_CH95:1;
4121 vuint32_t AWOR_CH94:1;
4122 vuint32_t AWOR_CH93:1;
4123 vuint32_t AWOR_CH92:1;
4124 vuint32_t AWOR_CH91:1;
4125 vuint32_t AWOR_CH90:1;
4126 vuint32_t AWOR_CH89:1;
4127 vuint32_t AWOR_CH88:1;
4128 vuint32_t AWOR_CH87:1;
4129 vuint32_t AWOR_CH86:1;
4130 vuint32_t AWOR_CH85:1;
4131 vuint32_t AWOR_CH84:1;
4132 vuint32_t AWOR_CH83:1;
4133 vuint32_t AWOR_CH82:1;
4134 vuint32_t AWOR_CH81:1;
4135 vuint32_t AWOR_CH80:1;
4136 vuint32_t AWOR_CH79:1;
4137 vuint32_t AWOR_CH78:1;
4138 vuint32_t AWOR_CH77:1;
4139 vuint32_t AWOR_CH76:1;
4140 vuint32_t AWOR_CH75:1;
4141 vuint32_t AWOR_CH74:1;
4142 vuint32_t AWOR_CH73:1;
4143 vuint32_t AWOR_CH72:1;
4144 vuint32_t AWOR_CH71:1;
4145 vuint32_t AWOR_CH70:1;
4146 vuint32_t AWOR_CH69:1;
4147 vuint32_t AWOR_CH68:1;
4148 vuint32_t AWOR_CH67:1;
4149 vuint32_t AWOR_CH66:1;
4150 vuint32_t AWOR_CH65:1;
4151 vuint32_t AWOR_CH64:1;
4152 } B;
4153 } AWORR2;
4154
4155 vuint8_t ADC0_reserved13[4]; /* Reserved 4 bytes (Base+0x02FC-0x02FF) */
4156
4157}; /* end of ADC0_tag */
4158/****************************************************************************/
4159/* MODULE : ADC1 (12 Bit) */
4160/* CH[0..15], CH[32..44] */
4161/****************************************************************************/
4162struct ADC1_tag {
4163
4164 union { /* ADC1 Main Configuration (Base+0x0000) */
4165 vuint32_t R;
4166 struct {
4167 vuint32_t OWREN:1;
4168 vuint32_t WLSIDE:1;
4169 vuint32_t MODE:1;
4170 vuint32_t:4;
4171 vuint32_t NSTART:1;
4172 vuint32_t:1;
4173 vuint32_t JTRGEN:1;
4174 vuint32_t JEDGE:1;
4175 vuint32_t JSTART:1;
4176 vuint32_t:2;
4177 vuint32_t CTUEN:1;
4178 vuint32_t:9;
4179 vuint32_t ABORT_CHAIN:1;
4180 vuint32_t ABORT:1;
4181 vuint32_t ACKO:1;
4182 vuint32_t:4;
4183 vuint32_t PWDN:1;
4184 } B;
4185 } MCR;
4186
4187 union { /* ADC1 Main Status (Base+0x0004) */
4188 vuint32_t R;
4189 struct {
4190 vuint32_t:7;
4191 vuint32_t NSTART:1;
4192 vuint32_t JABORT:1;
4193 vuint32_t:2;
4194 vuint32_t JSTART:1;
4195 vuint32_t:3;
4196 vuint32_t CTUSTART:1;
4197 vuint32_t CHADDR:7;
4198 vuint32_t:3;
4199 vuint32_t ACKO:1;
4200 vuint32_t:2;
4201 vuint32_t ADCSTATUS:3;
4202 } B;
4203 } MSR;
4204
4205 vuint8_t ADC1_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
4206
4207 union { /* ADC1 Interrupt Status (Base+0x0010) */
4208 vuint32_t R;
4209 struct {
4210 vuint32_t:27;
4211 vuint32_t EOCTU:1;
4212 vuint32_t JEOC:1;
4213 vuint32_t JECH:1;
4214 vuint32_t EOC:1;
4215 vuint32_t ECH:1;
4216 } B;
4217 } ISR;
4218
4219 union { /* ADC1 Channel Pending 0 (Base+0x0014) */
4220 vuint32_t R; /* (For precision channels) */
4221 struct {
4222 vuint32_t :16;
4223 vuint32_t EOC_CH15:1;
4224 vuint32_t EOC_CH14:1;
4225 vuint32_t EOC_CH13:1;
4226 vuint32_t EOC_CH12:1;
4227 vuint32_t EOC_CH11:1;
4228 vuint32_t EOC_CH10:1;
4229 vuint32_t EOC_CH9:1;
4230 vuint32_t EOC_CH8:1;
4231 vuint32_t EOC_CH7:1;
4232 vuint32_t EOC_CH6:1;
4233 vuint32_t EOC_CH5:1;
4234 vuint32_t EOC_CH4:1;
4235 vuint32_t EOC_CH3:1;
4236 vuint32_t EOC_CH2:1;
4237 vuint32_t EOC_CH1:1;
4238 vuint32_t EOC_CH0:1;
4239 } B;
4240 } CE0CFR0;
4241
4242 union { /* ADC1 Channel Pending 1 (Base+0x0018) */
4243 vuint32_t R; /* (For standard Channels) */
4244 struct {
4245 vuint32_t:19;
4246 vuint32_t EOC_CH44:1;
4247 vuint32_t EOC_CH43:1;
4248 vuint32_t EOC_CH42:1;
4249 vuint32_t EOC_CH41:1;
4250 vuint32_t EOC_CH40:1;
4251 vuint32_t EOC_CH39:1;
4252 vuint32_t EOC_CH38:1;
4253 vuint32_t EOC_CH37:1;
4254 vuint32_t EOC_CH36:1;
4255 vuint32_t EOC_CH35:1;
4256 vuint32_t EOC_CH34:1;
4257 vuint32_t EOC_CH33:1;
4258 vuint32_t EOC_CH32:1;
4259 } B;
4260 } CE0CFR1;
4261
4262 vuint8_t ADC1_reserved1[4]; /* Reserved 4 bytes (Base+0x001C-0x001F) */
4263
4264 union { /* ADC1 Interrupt Mask (Base+0020) */
4265 vuint32_t R;
4266 struct {
4267 vuint32_t:27;
4268 vuint32_t MSKEOCTU:1;
4269 vuint32_t MSKJEOC:1;
4270 vuint32_t MSKJECH:1;
4271 vuint32_t MSKEOC:1;
4272 vuint32_t MSKECH:1;
4273 } B;
4274 } IMR;
4275
4276 union { /* ADC1 Channel Interrupt Mask 0 (Base+0x0024) */
4277 vuint32_t R; /* (For Precision Channels) */
4278 struct {
4279 vuint32_t:16;
4280 vuint32_t CIM15:1;
4281 vuint32_t CIM14:1;
4282 vuint32_t CIM13:1;
4283 vuint32_t CIM12:1;
4284 vuint32_t CIM11:1;
4285 vuint32_t CIM10:1;
4286 vuint32_t CIM9:1;
4287 vuint32_t CIM8:1;
4288 vuint32_t CIM7:1;
4289 vuint32_t CIM6:1;
4290 vuint32_t CIM5:1;
4291 vuint32_t CIM4:1;
4292 vuint32_t CIM3:1;
4293 vuint32_t CIM2:1;
4294 vuint32_t CIM1:1;
4295 vuint32_t CIM0:1;
4296 } B;
4297 } CIMR0;
4298
4299 union { /* ADC1 Channel Interrupt Mask 1 (+0x0028) */
4300 vuint32_t R; /* (For Standard Channels) */
4301 struct {
4302 vuint32_t:19;
4303 vuint32_t CIM44:1;
4304 vuint32_t CIM43:1;
4305 vuint32_t CIM42:1;
4306 vuint32_t CIM41:1;
4307 vuint32_t CIM40:1;
4308 vuint32_t CIM39:1;
4309 vuint32_t CIM38:1;
4310 vuint32_t CIM37:1;
4311 vuint32_t CIM36:1;
4312 vuint32_t CIM35:1;
4313 vuint32_t CIM34:1;
4314 vuint32_t CIM33:1;
4315 vuint32_t CIM32:1;
4316 } B;
4317 } CIMR1;
4318
4319 vuint8_t ADC1_reserved2[4]; /* Reserved 4 bytes (Base+0x002C-0x002F) */
4320
4321 union { /* ADC1 Watchdog Threshold Interrupt Status (+0x0030)*/
4322 vuint32_t R;
4323 struct {
4324 vuint32_t:26;
4325 vuint32_t WDG2H:1;
4326 vuint32_t WDG2L:1;
4327 vuint32_t WDG1H:1;
4328 vuint32_t WDG1L:1;
4329 vuint32_t WDG0H:1;
4330 vuint32_t WDG0L:1;
4331 } B;
4332 } WTISR;
4333
4334 union { /* ADC1 Watchdog Threshold Interrupt Mask (+0x0034) */
4335 vuint32_t R;
4336 struct {
4337 vuint32_t:26;
4338 vuint32_t MSKWDG2H:1;
4339 vuint32_t MSKWDG2L:1;
4340 vuint32_t MSKWDG1H:1;
4341 vuint32_t MSKWDG1L:1;
4342 vuint32_t MSKWDG0H:1;
4343 vuint32_t MSKWDG0L:1;
4344 } B;
4345 } WTIMR;
4346
4347 vuint8_t ADC1_reserved3[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */
4348
4349 union { /* ADC1 DMA Enable (Base+0x0040) */
4350 vuint32_t R;
4351 struct {
4352 vuint32_t:30;
4353 vuint32_t DCLR:1;
4354 vuint32_t DMAEN:1;
4355 } B;
4356 } DMAE;
4357
4358 union { /* ADC1 DMA Channel Select 0 (Base+0x0044) */
4359 vuint32_t R; /* (for precision channels) */
4360 struct {
4361 vuint32_t:16;
4362 vuint32_t DMA15:1;
4363 vuint32_t DMA14:1;
4364 vuint32_t DMA13:1;
4365 vuint32_t DMA12:1;
4366 vuint32_t DMA11:1;
4367 vuint32_t DMA10:1;
4368 vuint32_t DMA9:1;
4369 vuint32_t DMA8:1;
4370 vuint32_t DMA7:1;
4371 vuint32_t DMA6:1;
4372 vuint32_t DMA5:1;
4373 vuint32_t DMA4:1;
4374 vuint32_t DMA3:1;
4375 vuint32_t DMA2:1;
4376 vuint32_t DMA1:1;
4377 vuint32_t DMA0:1;
4378 } B;
4379 } DMAR0;
4380
4381 union { /* ADC1 DMA Channel Select 1 (Base+0x0048) */
4382 vuint32_t R; /* (for standard channels) */
4383 struct {
4384 vuint32_t:19;
4385 vuint32_t DMA44:1;
4386 vuint32_t DMA43:1;
4387 vuint32_t DMA42:1;
4388 vuint32_t DMA41:1;
4389 vuint32_t DMA40:1;
4390 vuint32_t DMA39:1;
4391 vuint32_t DMA38:1;
4392 vuint32_t DMA37:1;
4393 vuint32_t DMA36:1;
4394 vuint32_t DMA35:1;
4395 vuint32_t DMA34:1;
4396 vuint32_t DMA33:1;
4397 vuint32_t DMA32:1;
4398 } B;
4399 } DMAR1;
4400
4401 vuint8_t ADC1_reserved4[20]; /* Reserved 20 bytes (Base+0x004C-0x005F) */
4402
4403 /* Note the threshold registers are not implemented as an array for */
4404 /* concistency with ADC0 header section */
4405
4406 union { /* ADC1 Threshold 0 (Base+0x0060) */
4407 vuint32_t R;
4408 struct {
4409 vuint32_t:4;
4410 vuint32_t THRH:12;
4411 vuint32_t:4;
4412 vuint32_t THRL:12;
4413 } B;
4414 } THRHLR0;
4415
4416 union { /* ADC1 Threshold 1 (Base+0x0064) */
4417 vuint32_t R;
4418 struct {
4419 vuint32_t:4;
4420 vuint32_t THRH:12;
4421 vuint32_t:4;
4422 vuint32_t THRL:12;
4423 } B;
4424 } THRHLR1;
4425
4426 union { /* ADC1 Threshold 2 (Base+0x0068) */
4427 vuint32_t R;
4428 struct {
4429 vuint32_t:4;
4430 vuint32_t THRH:12;
4431 vuint32_t:4;
4432 vuint32_t THRL:12;
4433 } B;
4434 } THRHLR2;
4435
4436 vuint8_t ADC1_reserved5[20]; /* Reserved 20 bytes (Base+0x006C-0x007F) */
4437
4438 union { /* ADC1 Presampling Control (Base+0x0080) */
4439 vuint32_t R;
4440 struct {
4441 vuint32_t:25;
4442 vuint32_t PREVAL2:2;
4443 vuint32_t PREVAL1:2;
4444 vuint32_t PREVAL0:2;
4445 vuint32_t PRECONV:1;
4446 } B;
4447 } PSCR;
4448
4449 union { /* ADC1 Presampling 0 (Base+0x0084) */
4450 vuint32_t R; /* (precision channels) */
4451 struct {
4452 vuint32_t:16;
4453 vuint32_t PRES15:1;
4454 vuint32_t PRES14:1;
4455 vuint32_t PRES13:1;
4456 vuint32_t PRES12:1;
4457 vuint32_t PRES11:1;
4458 vuint32_t PRES10:1;
4459 vuint32_t PRES9:1;
4460 vuint32_t PRES8:1;
4461 vuint32_t PRES7:1;
4462 vuint32_t PRES6:1;
4463 vuint32_t PRES5:1;
4464 vuint32_t PRES4:1;
4465 vuint32_t PRES3:1;
4466 vuint32_t PRES2:1;
4467 vuint32_t PRES1:1;
4468 vuint32_t PRES0:1;
4469 } B;
4470 } PSR0;
4471
4472 union { /* ADC1 Presampling 1 (Base+0x0088) */
4473 vuint32_t R; /* (standard channels) */
4474 struct {
4475 vuint32_t:19;
4476 vuint32_t PRES44:1;
4477 vuint32_t PRES43:1;
4478 vuint32_t PRES42:1;
4479 vuint32_t PRES41:1;
4480 vuint32_t PRES40:1;
4481 vuint32_t PRES39:1;
4482 vuint32_t PRES38:1;
4483 vuint32_t PRES37:1;
4484 vuint32_t PRES36:1;
4485 vuint32_t PRES35:1;
4486 vuint32_t PRES34:1;
4487 vuint32_t PRES33:1;
4488 vuint32_t PRES32:1;
4489 } B;
4490 } PSR1;
4491
4492 vuint8_t ADC1_reserved6[8]; /* Reserved 8 bytes (Base+0x008C-0x0093) */
4493
4494 /* Note the following CTR registers are NOT implemented as an array to */
4495 /* try and maintain some concistency through the header file */
4496 /* (The registers are however identical) */
4497
4498 union { /* ADC1 Conversion Timing 0 (Base+0x0094) */
4499 vuint32_t R; /* (precision channels) */
4500 struct {
4501 vuint32_t:16;
4502 vuint32_t INPLATCH:1;
4503 vuint32_t:1;
4504 vuint32_t OFFSHIFT:2;
4505 vuint32_t:1;
4506 vuint32_t INPCMP:2;
4507 vuint32_t:1;
4508 vuint32_t INPSAMP:8;
4509 } B;
4510 } CTR0;
4511
4512 union { /* ADC1 Conversion Timing 1 (Base+0x0098) */
4513 vuint32_t R; /* (standard channels) */
4514 struct {
4515 vuint32_t:16;
4516 vuint32_t INPLATCH:1;
4517 vuint32_t:1;
4518 vuint32_t OFFSHIFT:2;
4519 vuint32_t:1;
4520 vuint32_t INPCMP:2;
4521 vuint32_t:1;
4522 vuint32_t INPSAMP:8;
4523 } B;
4524 } CTR1;
4525
4526 vuint8_t ADC1_reserved7[8]; /* Reserved 8 bytes (Base+0x009C-0x00A3) */
4527
4528 union { /* ADC1 Normal Conversion Mask 0 (Base+0x00A4) */
4529 vuint32_t R; /* (precision channels) */
4530 struct {
4531 vuint32_t :16;
4532 vuint32_t CH15:1;
4533 vuint32_t CH14:1;
4534 vuint32_t CH13:1;
4535 vuint32_t CH12:1;
4536 vuint32_t CH11:1;
4537 vuint32_t CH10:1;
4538 vuint32_t CH9:1;
4539 vuint32_t CH8:1;
4540 vuint32_t CH7:1;
4541 vuint32_t CH6:1;
4542 vuint32_t CH5:1;
4543 vuint32_t CH4:1;
4544 vuint32_t CH3:1;
4545 vuint32_t CH2:1;
4546 vuint32_t CH1:1;
4547 vuint32_t CH0:1;
4548 } B;
4549 } NCMR0;
4550
4551 union { /* ADC1 Normal Conversion Mask 1 (Base+0x00A8) */
4552 vuint32_t R; /* (standard channels) */
4553 struct {
4554 vuint32_t:19;
4555 vuint32_t CH44:1;
4556 vuint32_t CH43:1;
4557 vuint32_t CH42:1;
4558 vuint32_t CH41:1;
4559 vuint32_t CH40:1;
4560 vuint32_t CH39:1;
4561 vuint32_t CH38:1;
4562 vuint32_t CH37:1;
4563 vuint32_t CH36:1;
4564 vuint32_t CH35:1;
4565 vuint32_t CH34:1;
4566 vuint32_t CH33:1;
4567 vuint32_t CH32:1;
4568 } B;
4569 } NCMR1;
4570
4571 vuint8_t ADC1_reserved8[8]; /* Reserved 8 bytes (Base+0x00AC-0x00B3) */
4572
4573 union { /* ADC1 Injected Conversion Mask0 (Base+0x00B4) */
4574 vuint32_t R; /* (precision channels) */
4575 struct {
4576 vuint32_t :16;
4577 vuint32_t CH15:1;
4578 vuint32_t CH14:1;
4579 vuint32_t CH13:1;
4580 vuint32_t CH12:1;
4581 vuint32_t CH11:1;
4582 vuint32_t CH10:1;
4583 vuint32_t CH9:1;
4584 vuint32_t CH8:1;
4585 vuint32_t CH7:1;
4586 vuint32_t CH6:1;
4587 vuint32_t CH5:1;
4588 vuint32_t CH4:1;
4589 vuint32_t CH3:1;
4590 vuint32_t CH2:1;
4591 vuint32_t CH1:1;
4592 vuint32_t CH0:1;
4593 } B;
4594 } JCMR0;
4595
4596 union { /* ADC1 Injected Conversion Mask1 (Base+0x00B8) */
4597 vuint32_t R; /* (standard channels) */
4598 struct {
4599 vuint32_t :19;
4600 vuint32_t CH44:1;
4601 vuint32_t CH43:1;
4602 vuint32_t CH42:1;
4603 vuint32_t CH41:1;
4604 vuint32_t CH40:1;
4605 vuint32_t CH39:1;
4606 vuint32_t CH38:1;
4607 vuint32_t CH37:1;
4608 vuint32_t CH36:1;
4609 vuint32_t CH35:1;
4610 vuint32_t CH34:1;
4611 vuint32_t CH33:1;
4612 vuint32_t CH32:1;
4613 } B;
4614 } JCMR1;
4615
4616 vuint8_t ADC1_reserved9[68]; /* Reserved 68 bytes (Base+0x00BC-0x00FF) */
4617
4618 union { /* ADC1 Channel 0-44 Data (Base+0x0100-0x01B0) */
4619 vuint32_t R; /* Note CDR[16..31] are reserved */
4620 struct {
4621 vuint32_t:12;
4622 vuint32_t VALID:1;
4623 vuint32_t OVERW:1;
4624 vuint32_t RESULT:2;
4625 vuint32_t:4;
4626 vuint32_t CDATA:12;
4627 } B;
4628 } CDR[45];
4629
4630 vuint8_t ADC1_reserved10[252]; /* Reserved 252 bytes (Base+0x01B4-0x002AF) */
4631
4632 union { /* ADC1 Channel Watchdog Select 0 (Base+0x02B0) */
4633 vuint32_t R; /* (precision channels) */
4634 struct {
4635 vuint32_t:2;
4636 vuint32_t WSEL_CH7:2;
4637 vuint32_t:2;
4638 vuint32_t WSEL_CH6:2;
4639 vuint32_t:2;
4640 vuint32_t WSEL_CH5:2;
4641 vuint32_t:2;
4642 vuint32_t WSEL_CH4:2;
4643 vuint32_t:2;
4644 vuint32_t WSEL_CH3:2;
4645 vuint32_t:2;
4646 vuint32_t WSEL_CH2:2;
4647 vuint32_t:2;
4648 vuint32_t WSEL_CH1:2;
4649 vuint32_t:2;
4650 vuint32_t WSEL_CH0:2;
4651 } B;
4652 } CWSELR0;
4653
4654 union { /* ADC1 Channel Watchdog Select 1 (Base+0x02B4) */
4655 vuint32_t R; /* (precision channels) */
4656 struct {
4657 vuint32_t:2;
4658 vuint32_t WSEL_CH15:2;
4659 vuint32_t:2;
4660 vuint32_t WSEL_CH14:2;
4661 vuint32_t:2;
4662 vuint32_t WSEL_CH13:2;
4663 vuint32_t:2;
4664 vuint32_t WSEL_CH12:2;
4665 vuint32_t:2;
4666 vuint32_t WSEL_CH11:2;
4667 vuint32_t:2;
4668 vuint32_t WSEL_CH10:2;
4669 vuint32_t:2;
4670 vuint32_t WSEL_CH9:2;
4671 vuint32_t:2;
4672 vuint32_t WSEL_CH8:2;
4673 } B;
4674 } CWSELR1;
4675
4676 vuint8_t ADC1_reserved11[8]; /* Reserved 8 bytes (Base+0x02B8-0x02BF) */
4677
4678 union { /* ADC1 Channel Watchdog Select 4 (Base+0x02C0) */
4679 vuint32_t R; /* (standard channels) */
4680 struct {
4681 vuint32_t:2;
4682 vuint32_t WSEL_CH39:2;
4683 vuint32_t:2;
4684 vuint32_t WSEL_CH38:2;
4685 vuint32_t:2;
4686 vuint32_t WSEL_CH37:2;
4687 vuint32_t:2;
4688 vuint32_t WSEL_CH36:2;
4689 vuint32_t:2;
4690 vuint32_t WSEL_CH35:2;
4691 vuint32_t:2;
4692 vuint32_t WSEL_CH34:2;
4693 vuint32_t:2;
4694 vuint32_t WSEL_CH33:2;
4695 vuint32_t:2;
4696 vuint32_t WSEL_CH32:2;
4697 } B;
4698 } CWSELR4;
4699
4700 union { /* ADC1 Channel Watchdog Select 5 (Base+0x02C4) */
4701 vuint32_t R; /* (standard channels) */
4702 struct {
4703 vuint32_t:14;
4704 vuint32_t WSEL_CH44:2;
4705 vuint32_t:2;
4706 vuint32_t WSEL_CH43:2;
4707 vuint32_t:2;
4708 vuint32_t WSEL_CH42:2;
4709 vuint32_t:2;
4710 vuint32_t WSEL_CH41:2;
4711 vuint32_t:2;
4712 vuint32_t WSEL_CH40:2;
4713 } B;
4714 } CWSELR5;
4715
4716 vuint8_t ADC1_reserved12[24]; /* Reserved 24 bytes (Base+0x02C8-0x02DF) */
4717
4718 union { /* ADC1 Channel Watchdog Enable0 (Base++0x02E0) */
4719 vuint32_t R; /* (precision channels) */
4720 struct {
4721 vuint32_t :16;
4722 vuint32_t CWEN15:1;
4723 vuint32_t CWEN14:1;
4724 vuint32_t CWEN13:1;
4725 vuint32_t CWEN12:1;
4726 vuint32_t CWEN11:1;
4727 vuint32_t CWEN10:1;
4728 vuint32_t CWEN9:1;
4729 vuint32_t CWEN8:1;
4730 vuint32_t CWEN7:1;
4731 vuint32_t CWEN6:1;
4732 vuint32_t CWEN5:1;
4733 vuint32_t CWEN4:1;
4734 vuint32_t CWEN3:1;
4735 vuint32_t CWEN2:1;
4736 vuint32_t CWEN1:1;
4737 vuint32_t CWEN0:1;
4738 } B;
4739 } CWENR0;
4740
4741 union { /* ADC1 Channel Watchdog Enable1 (Base++0x02E4) */
4742 vuint32_t R; /* (standard channels) */
4743 struct {
4744 vuint32_t :19;
4745 vuint32_t CWEN44:1;
4746 vuint32_t CWEN43:1;
4747 vuint32_t CWEN42:1;
4748 vuint32_t CWEN41:1;
4749 vuint32_t CWEN40:1;
4750 vuint32_t CWEN39:1;
4751 vuint32_t CWEN38:1;
4752 vuint32_t CWEN37:1;
4753 vuint32_t CWEN36:1;
4754 vuint32_t CWEN35:1;
4755 vuint32_t CWEN34:1;
4756 vuint32_t CWEN33:1;
4757 vuint32_t CWEN32:1;
4758 } B;
4759 } CWENR1;
4760
4761 vuint8_t ADC1_reserved13[8]; /* Reserved 8 bytes (Base+0x02E8-0x02EF) */
4762
4763 union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */
4764 vuint32_t R;
4765 struct {
4766 vuint32_t :16;
4767 vuint32_t AWOR_CH15:1;
4768 vuint32_t AWOR_CH14:1;
4769 vuint32_t AWOR_CH13:1;
4770 vuint32_t AWOR_CH12:1;
4771 vuint32_t AWOR_CH11:1;
4772 vuint32_t AWOR_CH10:1;
4773 vuint32_t AWOR_CH9:1;
4774 vuint32_t AWOR_CH8:1;
4775 vuint32_t AWOR_CH7:1;
4776 vuint32_t AWOR_CH6:1;
4777 vuint32_t AWOR_CH5:1;
4778 vuint32_t AWOR_CH4:1;
4779 vuint32_t AWOR_CH3:1;
4780 vuint32_t AWOR_CH2:1;
4781 vuint32_t AWOR_CH1:1;
4782 vuint32_t AWOR_CH0:1;
4783 } B;
4784 } AWORR0;
4785
4786 union { /* ADC1 Watchdog out of range 1 (Base+0x02F4) */
4787 vuint32_t R;
4788 struct {
4789 vuint32_t :19;
4790 vuint32_t AWOR_CH44:1;
4791 vuint32_t AWOR_CH43:1;
4792 vuint32_t AWOR_CH42:1;
4793 vuint32_t AWOR_CH41:1;
4794 vuint32_t AWOR_CH40:1;
4795 vuint32_t AWOR_CH39:1;
4796 vuint32_t AWOR_CH38:1;
4797 vuint32_t AWOR_CH37:1;
4798 vuint32_t AWOR_CH36:1;
4799 vuint32_t AWOR_CH35:1;
4800 vuint32_t AWOR_CH34:1;
4801 vuint32_t AWOR_CH33:1;
4802 vuint32_t AWOR_CH32:1;
4803 } B;
4804 } AWORR1;
4805
4806 vuint8_t ADC1_reserved14[8]; /* Reserved 8 bytes (Base+0x02F8-0x02FF) */
4807
4808}; /* end of ADC1_tag */
4809/****************************************************************************/
4810/* MODULE : I2C */
4811/****************************************************************************/
4812struct I2C_tag{
4813
4814 union { /* I2C Bus Address (Base+0x0000) */
4815 vuint8_t R;
4816 struct {
4817 vuint8_t ADR:7;
4818 vuint8_t :1;
4819 } B;
4820 } IBAD;
4821
4822 union { /* I2C Bus Frequency Divider (Base+0x0001) */
4823 vuint8_t R;
4824 struct {
4825 vuint8_t IBC:8;
4826 } B;
4827 } IBFD;
4828
4829 union { /* I2C Bus Control (Base+0x0002) */
4830 vuint8_t R;
4831 struct {
4832 vuint8_t MDIS:1;
4833 vuint8_t IBIE:1;
4834 vuint8_t MS:1;
4835 vuint8_t TX:1;
4836 vuint8_t NOACK:1;
4837 vuint8_t RSTA:1;
4838 vuint8_t DMAEN:1;
4839 vuint8_t IBDOZE:1;
4840 } B;
4841 } IBCR;
4842
4843 union { /* I2C Bus Status (Base+0x0003) */
4844 vuint8_t R;
4845 struct {
4846 vuint8_t TCF:1;
4847 vuint8_t IAAS:1;
4848 vuint8_t IBB:1;
4849 vuint8_t IBAL:1;
4850 vuint8_t :1;
4851 vuint8_t SRW:1;
4852 vuint8_t IBIF:1;
4853 vuint8_t RXAK:1;
4854 } B;
4855 } IBSR;
4856
4857 union { /* I2C Bus Data I/O (Base+0x0004) */
4858 vuint8_t R;
4859 struct {
4860 vuint8_t DATA:8;
4861 } B;
4862 } IBDR;
4863
4864 union { /* I2C Interrupt Configuration (Base+0x0005) */
4865 vuint8_t R;
4866 struct {
4867 vuint8_t BIIE:1;
4868 vuint8_t :7;
4869 } B;
4870 } IBIC;
4871
4872 vuint8_t I2C_reserved0[16378]; /* Reserved 16378 (Base+0x0006-0x3FFF) */
4873
4874}; /* end of i2c_tag */
4875/****************************************************************************/
4876/* MODULE : LINFLEX (Master/Slave with DMA) */
4877/****************************************************************************/
4878
4879struct LINFLEX_MS_tag {
4880
4881 union { /* LINFLEX LIN Control 1 (Base+0x0000) */
4882 vuint32_t R;
4883 struct {
4884 vuint32_t :16;
4885 vuint32_t CCD:1;
4886 vuint32_t CFD:1;
4887 vuint32_t LASE:1;
4888 vuint32_t AWUM:1;
4889 vuint32_t MBL:4;
4890 vuint32_t BF:1;
4891 vuint32_t SFTM:1;
4892 vuint32_t LBKM:1;
4893 vuint32_t MME:1;
4894 vuint32_t SBDT:1;
4895 vuint32_t RBLM:1;
4896 vuint32_t SLEEP:1;
4897 vuint32_t INIT:1;
4898 } B;
4899 } LINCR1;
4900
4901 union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
4902 vuint32_t R;
4903 struct {
4904 vuint32_t :16;
4905 vuint32_t SZIE:1;
4906 vuint32_t OCIE:1;
4907 vuint32_t BEIE:1;
4908 vuint32_t CEIE:1;
4909 vuint32_t HEIE:1;
4910 vuint32_t:2;
4911 vuint32_t FEIE:1;
4912 vuint32_t BOIE:1;
4913 vuint32_t LSIE:1;
4914 vuint32_t WUIE:1;
4915 vuint32_t DBFIE:1;
4916 vuint32_t DBEIE:1;
4917 vuint32_t DRIE:1;
4918 vuint32_t DTIE:1;
4919 vuint32_t HRIE:1;
4920 } B;
4921 } LINIER;
4922
4923 union { /* LINFLEX LIN Status (Base+0x0008) */
4924 vuint32_t R;
4925 struct {
4926 vuint32_t :16;
4927 vuint32_t LINS:4;
4928 vuint32_t:2;
4929 vuint32_t RMB:1;
4930 vuint32_t:1;
4931 vuint32_t RBSY:1;
4932 vuint32_t RPS:1;
4933 vuint32_t WUF:1;
4934 vuint32_t DBFF:1;
4935 vuint32_t DBEF:1;
4936 vuint32_t DRF:1;
4937 vuint32_t DTF:1;
4938 vuint32_t HRF:1;
4939 } B;
4940 } LINSR;
4941
4942 union { /* LINFLEX LIN Error Status (Base+0x000C) */
4943 vuint32_t R;
4944 struct {
4945 vuint32_t :16;
4946 vuint32_t SZF:1;
4947 vuint32_t OCF:1;
4948 vuint32_t BEF:1;
4949 vuint32_t CEF:1;
4950 vuint32_t SFEF:1;
4951 vuint32_t BDEF:1;
4952 vuint32_t IDPEF:1;
4953 vuint32_t FEF:1;
4954 vuint32_t BOF:1;
4955 vuint32_t:6;
4956 vuint32_t NF:1;
4957 } B;
4958 } LINESR;
4959
4960 union { /* LINFLEX UART Mode Control (Base+0x0010) */
4961 vuint32_t R;
4962 struct {
4963 vuint32_t :16;
4964 vuint32_t TDFL:3;
4965 vuint32_t RDFL:3;
4966 vuint32_t RFBM:1;
4967 vuint32_t TFBM:1;
4968 vuint32_t WL1:1;
4969 vuint32_t PC1:1;
4970 vuint32_t RXEN:1;
4971 vuint32_t TXEN:1;
4972 vuint32_t PC0:1;
4973 vuint32_t PCE:1;
4974 vuint32_t WL0:1;
4975 vuint32_t UART:1;
4976 } B;
4977 } UARTCR;
4978
4979 union { /* LINFLEX UART Mode Status (Base+0x0014) */
4980 vuint32_t R;
4981 struct {
4982 vuint32_t :16;
4983 vuint32_t SZF:1;
4984 vuint32_t OCF:1;
4985 vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
4986 vuint32_t RMB:1;
4987 vuint32_t FEF:1;
4988 vuint32_t BOF:1;
4989 vuint32_t RPS:1;
4990 vuint32_t WUF:1;
4991 vuint32_t:2;
4992 vuint32_t DRF:1;
4993 vuint32_t DTF:1;
4994 vuint32_t NF:1;
4995 } B;
4996 } UARTSR;
4997
4998 union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
4999 vuint32_t R;
5000 struct {
5001 vuint32_t :16;
5002 vuint32_t:5;
5003 vuint32_t LTOM:1;
5004 vuint32_t IOT:1;
5005 vuint32_t TOCE:1;
5006 vuint32_t CNT:8;
5007 } B;
5008 } LINTCSR;
5009
5010 union { /* LINFLEX LIN Output Compare (Base+0x001C) */
5011 vuint32_t R;
5012 struct {
5013 vuint32_t :16;
5014 vuint32_t OC2:8;
5015 vuint32_t OC1:8;
5016 } B;
5017 } LINOCR;
5018
5019 union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
5020 vuint32_t R;
5021 struct {
5022 vuint32_t :20;
5023 vuint32_t RTO:4;
5024 vuint32_t:1;
5025 vuint32_t HTO:7;
5026 } B;
5027 } LINTOCR;
5028
5029 union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
5030 vuint32_t R;
5031 struct {
5032 vuint32_t:28;
5033 vuint32_t DIV_F:4;
5034 } B;
5035 } LINFBRR;
5036
5037 union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
5038 vuint32_t R;
5039 struct {
5040 vuint32_t:19;
5041 vuint32_t DIV_M:13;
5042 } B;
5043 } LINIBRR;
5044
5045 union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
5046 vuint32_t R;
5047 struct {
5048 vuint32_t:24;
5049 vuint32_t CF:8;
5050 } B;
5051 } LINCFR;
5052
5053 union { /* LINFLEX LIN Control 2 (Base+0x0030) */
5054 vuint32_t R;
5055 struct {
5056 vuint32_t:17;
5057 vuint32_t IOBE:1;
5058 vuint32_t IOPE:1;
5059 vuint32_t WURQ:1;
5060 vuint32_t DDRQ:1;
5061 vuint32_t DTRQ:1;
5062 vuint32_t ABRQ:1;
5063 vuint32_t HTRQ:1;
5064 vuint32_t:8;
5065 } B;
5066 } LINCR2;
5067
5068 union { /* LINFLEX Buffer Identifier (Base+0x0034) */
5069 vuint32_t R;
5070 struct {
5071 vuint32_t:16;
5072 vuint32_t DFL:6;
5073 vuint32_t DIR:1;
5074 vuint32_t CCS:1;
5075 vuint32_t:2;
5076 vuint32_t ID:6;
5077 } B;
5078 } BIDR;
5079
5080 union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
5081 vuint32_t R;
5082 struct {
5083 vuint32_t DATA3:8;
5084 vuint32_t DATA2:8;
5085 vuint32_t DATA1:8;
5086 vuint32_t DATA0:8;
5087 } B;
5088 } BDRL;
5089
5090 union { /* LINFLEX Buffer Data MSB (Base+0x003C */
5091 vuint32_t R;
5092 struct {
5093 vuint32_t DATA7:8;
5094 vuint32_t DATA6:8;
5095 vuint32_t DATA5:8;
5096 vuint32_t DATA4:8;
5097 } B;
5098 } BDRM;
5099
5100 union { /* LINFLEX Identifier Filter Enable (+0x0040) */
5101 vuint32_t R;
5102 struct {
5103 vuint32_t:24;
5104 vuint32_t FACT:8;
5105 } B;
5106 } IFER;
5107
5108 union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
5109 vuint32_t R;
5110 struct {
5111 vuint32_t:28;
5112 vuint32_t IFMI:4;
5113 } B;
5114 } IFMI;
5115
5116 union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
5117 vuint32_t R;
5118 struct {
5119 vuint32_t:28;
5120 vuint32_t IFM:4;
5121 } B;
5122 } IFMR;
5123
5124 union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/
5125 vuint32_t R;
5126 struct {
5127 vuint32_t:16;
5128 vuint32_t DFL:6;
5129 vuint32_t DIR:1;
5130 vuint32_t CCS:1;
5131 vuint32_t:2;
5132 vuint32_t ID:6;
5133 } B;
5134 } IFCR[16];
5135
5136 union { /* LINFLEX Global Counter (+0x008C) */
5137 vuint32_t R;
5138 struct {
5139 vuint32_t:26;
5140 vuint32_t TDFBM:1;
5141 vuint32_t RDFBM:1;
5142 vuint32_t TDLIS:1;
5143 vuint32_t RDLIS:1;
5144 vuint32_t STOP:1;
5145 vuint32_t SR:1;
5146 } B;
5147 } GCR;
5148
5149 union { /* LINFLEX UART preset timeout (+0x0090) */
5150 vuint32_t R;
5151 struct {
5152 vuint32_t:20;
5153 vuint32_t PTO:12;
5154 } B;
5155 } UARTPTO;
5156
5157 union { /* LINFLEX UART current timeout (+0x0094) */
5158 vuint32_t R;
5159 struct {
5160 vuint32_t:20;
5161 vuint32_t CTO:12;
5162 } B;
5163 } UARTCTO;
5164
5165 union { /* LINFLEX DMA Tx Enable (+0x0098) */
5166 vuint32_t R;
5167 struct {
5168 vuint32_t:16;
5169 vuint32_t DTE15:1;
5170 vuint32_t DTE14:1;
5171 vuint32_t DTE13:1;
5172 vuint32_t DTE12:1;
5173 vuint32_t DTE11:1;
5174 vuint32_t DTE10:1;
5175 vuint32_t DTE9:1;
5176 vuint32_t DTE8:1;
5177 vuint32_t DTE7:1;
5178 vuint32_t DTE6:1;
5179 vuint32_t DTE5:1;
5180 vuint32_t DTE4:1;
5181 vuint32_t DTE3:1;
5182 vuint32_t DTE2:1;
5183 vuint32_t DTE1:1;
5184 vuint32_t DTE0:1;
5185 } B;
5186 } DMATXE;
5187
5188 union { /* LINFLEX DMA RX Enable (+0x009C) */
5189 vuint32_t R;
5190 struct {
5191 vuint32_t:16;
5192 vuint32_t DRE15:1;
5193 vuint32_t DRE14:1;
5194 vuint32_t DRE13:1;
5195 vuint32_t DRE12:1;
5196 vuint32_t DRE11:1;
5197 vuint32_t DRE10:1;
5198 vuint32_t DRE9:1;
5199 vuint32_t DRE8:1;
5200 vuint32_t DRE7:1;
5201 vuint32_t DRE6:1;
5202 vuint32_t DRE5:1;
5203 vuint32_t DRE4:1;
5204 vuint32_t DRE3:1;
5205 vuint32_t DRE2:1;
5206 vuint32_t DRE1:1;
5207 vuint32_t DRE0:1;
5208 } B;
5209 } DMARXE;
5210
5211
5212
5213}; /* end of LINFLEX_tag */
5214/****************************************************************************/
5215/* MODULE : LINFLEX (Master with DMA) */
5216/****************************************************************************/
5217
5218struct LINFLEX_M_tag {
5219
5220 union { /* LINFLEX LIN Control 1 (Base+0x0000) */
5221 vuint32_t R;
5222 struct {
5223 vuint32_t :16;
5224 vuint32_t CCD:1;
5225 vuint32_t CFD:1;
5226 vuint32_t LASE:1;
5227 vuint32_t AWUM:1;
5228 vuint32_t MBL:4;
5229 vuint32_t BF:1;
5230 vuint32_t SFTM:1;
5231 vuint32_t LBKM:1;
5232 vuint32_t MME:1;
5233 vuint32_t SBDT:1;
5234 vuint32_t RBLM:1;
5235 vuint32_t SLEEP:1;
5236 vuint32_t INIT:1;
5237 } B;
5238 } LINCR1;
5239
5240 union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
5241 vuint32_t R;
5242 struct {
5243 vuint32_t :16;
5244 vuint32_t SZIE:1;
5245 vuint32_t OCIE:1;
5246 vuint32_t BEIE:1;
5247 vuint32_t CEIE:1;
5248 vuint32_t HEIE:1;
5249 vuint32_t:2;
5250 vuint32_t FEIE:1;
5251 vuint32_t BOIE:1;
5252 vuint32_t LSIE:1;
5253 vuint32_t WUIE:1;
5254 vuint32_t DBFIE:1;
5255 vuint32_t DBEIE:1;
5256 vuint32_t DRIE:1;
5257 vuint32_t DTIE:1;
5258 vuint32_t HRIE:1;
5259 } B;
5260 } LINIER;
5261
5262 union { /* LINFLEX LIN Status (Base+0x0008) */
5263 vuint32_t R;
5264 struct {
5265 vuint32_t :16;
5266 vuint32_t LINS:4;
5267 vuint32_t:2;
5268 vuint32_t RMB:1;
5269 vuint32_t:1;
5270 vuint32_t RBSY:1;
5271 vuint32_t RPS:1;
5272 vuint32_t WUF:1;
5273 vuint32_t DBFF:1;
5274 vuint32_t DBEF:1;
5275 vuint32_t DRF:1;
5276 vuint32_t DTF:1;
5277 vuint32_t HRF:1;
5278 } B;
5279 } LINSR;
5280
5281 union { /* LINFLEX LIN Error Status (Base+0x000C) */
5282 vuint32_t R;
5283 struct {
5284 vuint32_t :16;
5285 vuint32_t SZF:1;
5286 vuint32_t OCF:1;
5287 vuint32_t BEF:1;
5288 vuint32_t CEF:1;
5289 vuint32_t SFEF:1;
5290 vuint32_t BDEF:1;
5291 vuint32_t IDPEF:1;
5292 vuint32_t FEF:1;
5293 vuint32_t BOF:1;
5294 vuint32_t:6;
5295 vuint32_t NF:1;
5296 } B;
5297 } LINESR;
5298
5299 union { /* LINFLEX UART Mode Control (Base+0x0010) */
5300 vuint32_t R;
5301 struct {
5302 vuint32_t :16;
5303 vuint32_t TDFL:3;
5304 vuint32_t RDFL:3;
5305 vuint32_t RFBM:1;
5306 vuint32_t TFBM:1;
5307 vuint32_t WL1:1;
5308 vuint32_t PC1:1;
5309 vuint32_t RXEN:1;
5310 vuint32_t TXEN:1;
5311 vuint32_t PC0:1;
5312 vuint32_t PCE:1;
5313 vuint32_t WL0:1;
5314 vuint32_t UART:1;
5315 } B;
5316 } UARTCR;
5317
5318 union { /* LINFLEX UART Mode Status (Base+0x0014) */
5319 vuint32_t R;
5320 struct {
5321 vuint32_t :16;
5322 vuint32_t SZF:1;
5323 vuint32_t OCF:1;
5324 vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
5325 vuint32_t RMB:1;
5326 vuint32_t FEF:1;
5327 vuint32_t BOF:1;
5328 vuint32_t RPS:1;
5329 vuint32_t WUF:1;
5330 vuint32_t:2;
5331 vuint32_t DRF:1;
5332 vuint32_t DTF:1;
5333 vuint32_t NF:1;
5334 } B;
5335 } UARTSR;
5336
5337 union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
5338 vuint32_t R;
5339 struct {
5340 vuint32_t :16;
5341 vuint32_t:5;
5342 vuint32_t LTOM:1;
5343 vuint32_t IOT:1;
5344 vuint32_t TOCE:1;
5345 vuint32_t CNT:8;
5346 } B;
5347 } LINTCSR;
5348
5349 union { /* LINFLEX LIN Output Compare (Base+0x001C) */
5350 vuint32_t R;
5351 struct {
5352 vuint32_t :16;
5353 vuint32_t OC2:8;
5354 vuint32_t OC1:8;
5355 } B;
5356 } LINOCR;
5357
5358 union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
5359 vuint32_t R;
5360 struct {
5361 vuint32_t :20;
5362 vuint32_t RTO:4;
5363 vuint32_t:1;
5364 vuint32_t HTO:7;
5365 } B;
5366 } LINTOCR;
5367
5368 union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
5369 vuint32_t R;
5370 struct {
5371 vuint32_t:28;
5372 vuint32_t DIV_F:4;
5373 } B;
5374 } LINFBRR;
5375
5376 union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
5377 vuint32_t R;
5378 struct {
5379 vuint32_t:19;
5380 vuint32_t DIV_M:13;
5381 } B;
5382 } LINIBRR;
5383
5384 union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
5385 vuint32_t R;
5386 struct {
5387 vuint32_t:24;
5388 vuint32_t CF:8;
5389 } B;
5390 } LINCFR;
5391
5392 union { /* LINFLEX LIN Control 2 (Base+0x0030) */
5393 vuint32_t R;
5394 struct {
5395 vuint32_t:17;
5396 vuint32_t IOBE:1;
5397 vuint32_t IOPE:1;
5398 vuint32_t WURQ:1;
5399 vuint32_t DDRQ:1;
5400 vuint32_t DTRQ:1;
5401 vuint32_t ABRQ:1;
5402 vuint32_t HTRQ:1;
5403 vuint32_t:8;
5404 } B;
5405 } LINCR2;
5406
5407 union { /* LINFLEX Buffer Identifier (Base+0x0034) */
5408 vuint32_t R;
5409 struct {
5410 vuint32_t:16;
5411 vuint32_t DFL:6;
5412 vuint32_t DIR:1;
5413 vuint32_t CCS:1;
5414 vuint32_t:2;
5415 vuint32_t ID:6;
5416 } B;
5417 } BIDR;
5418
5419 union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
5420 vuint32_t R;
5421 struct {
5422 vuint32_t DATA3:8;
5423 vuint32_t DATA2:8;
5424 vuint32_t DATA1:8;
5425 vuint32_t DATA0:8;
5426 } B;
5427 } BDRL;
5428
5429 union { /* LINFLEX Buffer Data MSB (Base+0x003C */
5430 vuint32_t R;
5431 struct {
5432 vuint32_t DATA7:8;
5433 vuint32_t DATA6:8;
5434 vuint32_t DATA5:8;
5435 vuint32_t DATA4:8;
5436 } B;
5437 } BDRM;
5438
5439 union { /* LINFLEX Identifier Filter Enable (+0x0040) */
5440 vuint32_t R;
5441 struct {
5442 vuint32_t:24;
5443 vuint32_t FACT:8;
5444 } B;
5445 } IFER;
5446
5447 union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
5448 vuint32_t R;
5449 struct {
5450 vuint32_t:28;
5451 vuint32_t IFMI:4;
5452 } B;
5453 } IFMI;
5454
5455 union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
5456 vuint32_t R;
5457 struct {
5458 vuint32_t:28;
5459 vuint32_t IFM:4;
5460 } B;
5461 } IFMR;
5462
5463 /* ---------------- */
5464 /* For Master-Only LINFLEX, this is where the memory map changes! */
5465 /* ---------------- */
5466
5467 union { /* LINFLEX Global Counter (+0x004C) */
5468 vuint32_t R;
5469 struct {
5470 vuint32_t:26;
5471 vuint32_t TDFBM:1;
5472 vuint32_t RDFBM:1;
5473 vuint32_t TDLIS:1;
5474 vuint32_t RDLIS:1;
5475 vuint32_t STOP:1;
5476 vuint32_t SR:1;
5477 } B;
5478 } GCR;
5479
5480 union { /* LINFLEX UART preset timeout (+0x0050) */
5481 vuint32_t R;
5482 struct {
5483 vuint32_t:20;
5484 vuint32_t PTO:12;
5485 } B;
5486 } UARTPTO;
5487
5488 union { /* LINFLEX UART current timeout (+0x0054) */
5489 vuint32_t R;
5490 struct {
5491 vuint32_t:20;
5492 vuint32_t CTO:12;
5493 } B;
5494 } UARTCTO;
5495
5496 union { /* LINFLEX DMA Tx Enable (+0x0058) */
5497 vuint32_t R;
5498 struct {
5499 vuint32_t:16;
5500 vuint32_t DTE15:1;
5501 vuint32_t DTE14:1;
5502 vuint32_t DTE13:1;
5503 vuint32_t DTE12:1;
5504 vuint32_t DTE11:1;
5505 vuint32_t DTE10:1;
5506 vuint32_t DTE9:1;
5507 vuint32_t DTE8:1;
5508 vuint32_t DTE7:1;
5509 vuint32_t DTE6:1;
5510 vuint32_t DTE5:1;
5511 vuint32_t DTE4:1;
5512 vuint32_t DTE3:1;
5513 vuint32_t DTE2:1;
5514 vuint32_t DTE1:1;
5515 vuint32_t DTE0:1;
5516 } B;
5517 } DMATXE;
5518
5519 union { /* LINFLEX DMA RX Enable (+0x005C) */
5520 vuint32_t R;
5521 struct {
5522 vuint32_t:16;
5523 vuint32_t DRE15:1;
5524 vuint32_t DRE14:1;
5525 vuint32_t DRE13:1;
5526 vuint32_t DRE12:1;
5527 vuint32_t DRE11:1;
5528 vuint32_t DRE10:1;
5529 vuint32_t DRE9:1;
5530 vuint32_t DRE8:1;
5531 vuint32_t DRE7:1;
5532 vuint32_t DRE6:1;
5533 vuint32_t DRE5:1;
5534 vuint32_t DRE4:1;
5535 vuint32_t DRE3:1;
5536 vuint32_t DRE2:1;
5537 vuint32_t DRE1:1;
5538 vuint32_t DRE0:1;
5539 } B;
5540 } DMARXE;
5541
5542
5543
5544}; /* end of LINFLEX_tag */
5545/****************************************************************************/
5546/* MODULE : CTU Lite */
5547/****************************************************************************/
5548struct CTU_tag{
5549
5550 vuint8_t CTU_reserved[48]; /* Reserved 48 bytes (Base+0x0000-0x002F) */
5551
5552 union { /* Event Config 0..63 (Base+0x0030-0x012C) */
5553 vuint32_t R;
5554 struct {
5555 vuint32_t :16;
5556 vuint32_t TM:1;
5557 vuint32_t CLR_FLAG:1;
5558 vuint32_t :5;
5559 vuint32_t ADC_SEL:1;
5560 vuint32_t :1;
5561 vuint32_t CHANNEL_VALUE:7;
5562 } B;
5563 } EVTCFGR[64];
5564
5565
5566}; /* end of CTU_tag */
5567/****************************************************************************/
5568/* MODULE : CANSP */
5569/****************************************************************************/
5570struct CANSP_tag{
5571
5572 union { /* CANSP Control (Base+0x0000) */
5573 vuint32_t R;
5574 struct {
5575 vuint32_t :16;
5576 vuint32_t RX_COMPLETE:1;
5577 vuint32_t BUSY:1;
5578 vuint32_t ACTIVE_CK:1;
5579 vuint32_t :3;
5580 vuint32_t MODE:1;
5581 vuint32_t CAN_RX_SEL:3;
5582 vuint32_t BRP:5;
5583 vuint32_t CAN_SMPLR_EN:1;
5584 } B;
5585 } CR;
5586
5587 union { /* CANSP Sample 0..11 (Base+0x0000-0x0030)*/
5588 vuint32_t R;
5589 } SR[12];
5590
5591}; /* end of CANSP_tag */
5592/****************************************************************************/
5593/* MODULE : XBAR */
5594/****************************************************************************/
5595struct XBAR_tag{
5596
5597 union { /* XBAR Master Priority Slave Port 0 (+0x0000) */
5598 vuint32_t R;
5599 struct {
5600 vuint32_t:1;
5601 vuint32_t MSTR_7:3;
5602 vuint32_t:1;
5603 vuint32_t MSTR_6:3;
5604 vuint32_t:1;
5605 vuint32_t MSTR_5:3;
5606 vuint32_t:1;
5607 vuint32_t MSTR_4:3;
5608 vuint32_t:1;
5609 vuint32_t MSTR_3:3;
5610 vuint32_t:1;
5611 vuint32_t MSTR_2:3;
5612 vuint32_t:1;
5613 vuint32_t MSTR_1:3;
5614 vuint32_t:1;
5615 vuint32_t MSTR_0:3;
5616 } B;
5617 } MPR0;
5618
5619 vuint8_t XBAR_reserved0[12]; /* Reserved 12 bytes (Base+0x0004-0x000F)*/
5620
5621 union { /* XBAR General Purpose Control Slave 0 (+0x0010) */
5622 vuint32_t R;
5623 struct {
5624 vuint32_t RO:1;
5625 vuint32_t HLP:1;
5626 vuint32_t:6;
5627 vuint32_t HPE7:1;
5628 vuint32_t HPE6:1;
5629 vuint32_t HPE5:1;
5630 vuint32_t HPE4:1;
5631 vuint32_t HPE3:1;
5632 vuint32_t HPE2:1;
5633 vuint32_t HPE1:1;
5634 vuint32_t HPE0:1;
5635 vuint32_t:6;
5636 vuint32_t ARB:2;
5637 vuint32_t:2;
5638 vuint32_t PCTL:2;
5639 vuint32_t:1;
5640 vuint32_t PARK:3;
5641 } B;
5642 } SGPCR0;
5643
5644 vuint8_t XBAR_reserved1[236]; /*Reserved 236 bytes (Base+0x0014-0x00FF)*/
5645
5646 union { /* XBAR Master Priority Slave Port 1 (+0x0100) */
5647 vuint32_t R;
5648 struct {
5649 vuint32_t:1;
5650 vuint32_t MSTR_7:3;
5651 vuint32_t:1;
5652 vuint32_t MSTR_6:3;
5653 vuint32_t:1;
5654 vuint32_t MSTR_5:3;
5655 vuint32_t:1;
5656 vuint32_t MSTR_4:3;
5657 vuint32_t:1;
5658 vuint32_t MSTR_3:3;
5659 vuint32_t:1;
5660 vuint32_t MSTR_2:3;
5661 vuint32_t:1;
5662 vuint32_t MSTR_1:3;
5663 vuint32_t:1;
5664 vuint32_t MSTR_0:3;
5665 } B;
5666 } MPR1;
5667
5668 vuint8_t XBAR_reserved2[12]; /* Reserved 12 bytes (Base+0x0104-0x010F)*/
5669
5670 union { /* XBAR General Purpose Control Slave 1 (+0x0110) */
5671 vuint32_t R;
5672 struct {
5673 vuint32_t RO:1;
5674 vuint32_t HLP:1;
5675 vuint32_t:6;
5676 vuint32_t HPE7:1;
5677 vuint32_t HPE6:1;
5678 vuint32_t HPE5:1;
5679 vuint32_t HPE4:1;
5680 vuint32_t HPE3:1;
5681 vuint32_t HPE2:1;
5682 vuint32_t HPE1:1;
5683 vuint32_t HPE0:1;
5684 vuint32_t:6;
5685 vuint32_t ARB:2;
5686 vuint32_t:2;
5687 vuint32_t PCTL:2;
5688 vuint32_t:1;
5689 vuint32_t PARK:3;
5690 } B;
5691 } SGPCR1;
5692
5693 vuint8_t XBAR_reserved3[236]; /*Reserved 236 bytes (Base+0x0114-0x01FF)*/
5694
5695 union { /* XBAR Master Priority Slave Port 2 (+0x0200) */
5696 vuint32_t R;
5697 struct {
5698 vuint32_t:1;
5699 vuint32_t MSTR_7:3;
5700 vuint32_t:1;
5701 vuint32_t MSTR_6:3;
5702 vuint32_t:1;
5703 vuint32_t MSTR_5:3;
5704 vuint32_t:1;
5705 vuint32_t MSTR_4:3;
5706 vuint32_t:1;
5707 vuint32_t MSTR_3:3;
5708 vuint32_t:1;
5709 vuint32_t MSTR_2:3;
5710 vuint32_t:1;
5711 vuint32_t MSTR_1:3;
5712 vuint32_t:1;
5713 vuint32_t MSTR_0:3;
5714 } B;
5715 } MPR2;
5716
5717 vuint8_t XBAR_reserved4[12]; /* Reserved 12 bytes (Base+0x0204-0x020F)*/
5718
5719 union { /* XBAR General Purpose Control Slave 2 (+0x0210) */
5720 vuint32_t R;
5721 struct {
5722 vuint32_t RO:1;
5723 vuint32_t HLP:1;
5724 vuint32_t:6;
5725 vuint32_t HPE7:1;
5726 vuint32_t HPE6:1;
5727 vuint32_t HPE5:1;
5728 vuint32_t HPE4:1;
5729 vuint32_t HPE3:1;
5730 vuint32_t HPE2:1;
5731 vuint32_t HPE1:1;
5732 vuint32_t HPE0:1;
5733 vuint32_t:6;
5734 vuint32_t ARB:2;
5735 vuint32_t:2;
5736 vuint32_t PCTL:2;
5737 vuint32_t:1;
5738 vuint32_t PARK:3;
5739 } B;
5740 } SGPCR2;
5741
5742 vuint8_t XBAR_reserved5[236]; /*Reserved 236 bytes (Base+0x0214-0x02FF)*/
5743
5744 union { /* XBAR Master Priority Slave Port 3 (+0x0300) */
5745 vuint32_t R;
5746 struct {
5747 vuint32_t:1;
5748 vuint32_t MSTR_7:3;
5749 vuint32_t:1;
5750 vuint32_t MSTR_6:3;
5751 vuint32_t:1;
5752 vuint32_t MSTR_5:3;
5753 vuint32_t:1;
5754 vuint32_t MSTR_4:3;
5755 vuint32_t:1;
5756 vuint32_t MSTR_3:3;
5757 vuint32_t:1;
5758 vuint32_t MSTR_2:3;
5759 vuint32_t:1;
5760 vuint32_t MSTR_1:3;
5761 vuint32_t:1;
5762 vuint32_t MSTR_0:3;
5763 } B;
5764 } MPR3;
5765
5766 vuint8_t XBAR_reserved6[12]; /* Reserved 12 bytes (Base+0x0304-0x030F)*/
5767
5768 union { /* XBAR General Purpose Control Slave 3 (+0x0310) */
5769 vuint32_t R;
5770 struct {
5771 vuint32_t RO:1;
5772 vuint32_t HLP:1;
5773 vuint32_t:6;
5774 vuint32_t HPE7:1;
5775 vuint32_t HPE6:1;
5776 vuint32_t HPE5:1;
5777 vuint32_t HPE4:1;
5778 vuint32_t HPE3:1;
5779 vuint32_t HPE2:1;
5780 vuint32_t HPE1:1;
5781 vuint32_t HPE0:1;
5782 vuint32_t:6;
5783 vuint32_t ARB:2;
5784 vuint32_t:2;
5785 vuint32_t PCTL:2;
5786 vuint32_t:1;
5787 vuint32_t PARK:3;
5788 } B;
5789 } SGPCR3;
5790
5791 vuint8_t XBAR_reserved7[1004]; /*Reserved 1004 bytes (Base+0x0314-0x06FF)*/
5792
5793 union { /* XBAR Master Priority Slave Port 7 (+0x0700) */
5794 vuint32_t R;
5795 struct {
5796 vuint32_t:1;
5797 vuint32_t MSTR_7:3;
5798 vuint32_t:1;
5799 vuint32_t MSTR_6:3;
5800 vuint32_t:1;
5801 vuint32_t MSTR_5:3;
5802 vuint32_t:1;
5803 vuint32_t MSTR_4:3;
5804 vuint32_t:1;
5805 vuint32_t MSTR_3:3;
5806 vuint32_t:1;
5807 vuint32_t MSTR_2:3;
5808 vuint32_t:1;
5809 vuint32_t MSTR_1:3;
5810 vuint32_t:1;
5811 vuint32_t MSTR_0:3;
5812 } B;
5813 } MPR7;
5814
5815 vuint8_t XBAR_reserved8[12]; /* Reserved 12 bytes (Base+0x0704-0x070F)*/
5816
5817 union { /* XBAR General Purpose Control Slave 7 (+0x0710) */
5818 vuint32_t R;
5819 struct {
5820 vuint32_t RO:1;
5821 vuint32_t HLP:1;
5822 vuint32_t:6;
5823 vuint32_t HPE7:1;
5824 vuint32_t HPE6:1;
5825 vuint32_t HPE5:1;
5826 vuint32_t HPE4:1;
5827 vuint32_t HPE3:1;
5828 vuint32_t HPE2:1;
5829 vuint32_t HPE1:1;
5830 vuint32_t HPE0:1;
5831 vuint32_t:6;
5832 vuint32_t ARB:2;
5833 vuint32_t:2;
5834 vuint32_t PCTL:2;
5835 vuint32_t:1;
5836 vuint32_t PARK:3;
5837 } B;
5838 } SGPCR7;
5839
5840 vuint8_t XBAR_reserved9[236]; /*Reserved 236 bytes (Base+0x0714-0x07FF)*/
5841
5842 union { /* XBAR General Purpose Control Master 0 (+0x0800) */
5843 vuint32_t R;
5844 struct {
5845 vuint32_t:29;
5846 vuint32_t AULB:3;
5847 } B;
5848 } MGPCR0;
5849
5850 vuint8_t XBAR_reserved10[252]; /*Reserved 252 bytes (Base+0x0804-0x08FF)*/
5851
5852 union { /* XBAR General Purpose Control Master 1 (+0x0900) */
5853 vuint32_t R;
5854 struct {
5855 vuint32_t:29;
5856 vuint32_t AULB:3;
5857 } B;
5858 } MGPCR1;
5859
5860 vuint8_t XBAR_reserved11[252]; /*Reserved 252 bytes (Base+0x0904-0x09FF)*/
5861
5862 union { /* XBAR General Purpose Control Master 2 (+0x0A00) */
5863 vuint32_t R;
5864 struct {
5865 vuint32_t:29;
5866 vuint32_t AULB:3;
5867 } B;
5868 } MGPCR2;
5869
5870 vuint8_t XBAR_reserved12[252]; /*Reserved 252 bytes (Base+0x0A04-0x0AFF)*/
5871
5872 union { /* XBAR General Purpose Control Master 3 (+0x0B00) */
5873 vuint32_t R;
5874 struct {
5875 vuint32_t:29;
5876 vuint32_t AULB:3;
5877 } B;
5878 } MGPCR3;
5879
5880 vuint8_t XBAR_reserved13[252]; /*Reserved 252 bytes (Base+0x0B04-0x0BFF)*/
5881
5882 union { /* XBAR General Purpose Control Master 4 (+0x0C00) */
5883 vuint32_t R;
5884 struct {
5885 vuint32_t:29;
5886 vuint32_t AULB:3;
5887 } B;
5888 } MGPCR4;
5889
5890 vuint8_t XBAR_reserved14[252]; /*Reserved 252 bytes (Base+0x0C04-0x0CFF)*/
5891
5892 union { /* XBAR General Purpose Control Master 5 (+0x0D00) */
5893 vuint32_t R;
5894 struct {
5895 vuint32_t:29;
5896 vuint32_t AULB:3;
5897 } B;
5898 } MGPCR5;
5899
5900 vuint8_t XBAR_reserved15[252]; /*Reserved 252 bytes (Base+0x0D04-0x0DFF)*/
5901
5902 union { /* XBAR General Purpose Control Master 6 (+0x0E00) */
5903 vuint32_t R;
5904 struct {
5905 vuint32_t:29;
5906 vuint32_t AULB:3;
5907 } B;
5908 } MGPCR6;
5909
5910 vuint8_t XBAR_reserved16[252]; /*Reserved 252 bytes (Base+0x0E04-0x0EFF)*/
5911
5912 union { /* XBAR General Purpose Control Master 7 (+0x0F00) */
5913 vuint32_t R;
5914 struct {
5915 vuint32_t:29;
5916 vuint32_t AULB:3;
5917 } B;
5918 } MGPCR7;
5919
5920
5921}; /* end of XBAR_tag */
5922/****************************************************************************/
5923/* MODULE : MPU (Memory Protection Unit) */
5924/****************************************************************************/
5925struct MPU_tag {
5926
5927 union { /* Control/Error Status (Base+0x0000) */
5928 vuint32_t R;
5929 struct {
5930 vuint32_t SPERR:8;
5931 vuint32_t :4;
5932 vuint32_t HRL:4;
5933 vuint32_t NSP:4;
5934 vuint32_t NGRD:4;
5935 vuint32_t :7;
5936 vuint32_t VLD:1;
5937 } B;
5938 } CESR;
5939
5940 vuint8_t MPU_reserved0[12]; /* Reserved 12 Bytes (Base+0x0004-0x000F) */
5941
5942
5943 union { /* Error Address Slave Port0 (Base+0x0010) */
5944 vuint32_t R;
5945 struct {
5946 vuint32_t EADDR:32;
5947 } B;
5948 } EAR0;
5949
5950 union { /* Error Detail Slave Port0 (Base+0x0014) */
5951 vuint32_t R;
5952 struct {
5953 vuint32_t EACD:16;
5954 vuint32_t EPID:8;
5955 vuint32_t EMN:4;
5956 vuint32_t EATTR:3;
5957 vuint32_t ERW:1;
5958 } B;
5959 } EDR0;
5960
5961
5962 union { /* Error Address Slave Port1 (Base+0x0018) */
5963 vuint32_t R;
5964 struct {
5965 vuint32_t EADDR:32;
5966 } B;
5967 } EAR1;
5968
5969 union { /* Error Detail Slave Port1 (Base+0x001C) */
5970 vuint32_t R;
5971 struct {
5972 vuint32_t EACD:16;
5973 vuint32_t EPID:8;
5974 vuint32_t EMN:4;
5975 vuint32_t EATTR:3;
5976 vuint32_t ERW:1;
5977 } B;
5978 } EDR1;
5979
5980
5981 union { /* Error Address Slave Port2 (Base+0x0020) */
5982 vuint32_t R;
5983 struct {
5984 vuint32_t EADDR:32;
5985 } B;
5986 } EAR2;
5987
5988 union { /* Error Detail Slave Port2 (Base+0x0024) */
5989 vuint32_t R;
5990 struct {
5991 vuint32_t EACD:16;
5992 vuint32_t EPID:8;
5993 vuint32_t EMN:4;
5994 vuint32_t EATTR:3;
5995 vuint32_t ERW:1;
5996 } B;
5997 } EDR2;
5998
5999
6000 union { /* Error Address Slave Port3 (Base+0x0028) */
6001 vuint32_t R;
6002 struct {
6003 vuint32_t EADDR:32;
6004 } B;
6005 } EAR3;
6006
6007 union { /* Error Detail Slave Port3 (Base+0x002C) */
6008 vuint32_t R;
6009 struct {
6010 vuint32_t EACD:16;
6011 vuint32_t EPID:8;
6012 vuint32_t EMN:4;
6013 vuint32_t EATTR:3;
6014 vuint32_t ERW:1;
6015 } B;
6016 } EDR3;
6017
6018
6019 union { /* Error Address Slave Port4 (Base+0x0030) */
6020 vuint32_t R;
6021 struct {
6022 vuint32_t EADDR:32;
6023 } B;
6024 } EAR4;
6025
6026 union { /* Error Detail Slave Port4 (Base+0x0034) */
6027 vuint32_t R;
6028 struct {
6029 vuint32_t EACD:16;
6030 vuint32_t EPID:8;
6031 vuint32_t EMN:4;
6032 vuint32_t EATTR:3;
6033 vuint32_t ERW:1;
6034 } B;
6035 } EDR4;
6036
6037 vuint8_t MPU_reserved1[968]; /* Reserved 968 Bytes (Base+0x0038-0x03FF) */
6038
6039 struct { /* Region Descriptor 0..15 (Base+0x0400-0x04F0) */
6040
6041 union { /* - Word 0 */
6042 vuint32_t R;
6043 struct {
6044 vuint32_t SRTADDR:27;
6045 vuint32_t :5;
6046 } B;
6047 } WORD0;
6048
6049 union { /* - Word 1 */
6050 vuint32_t R;
6051 struct {
6052 vuint32_t ENDADDR:27;
6053 vuint32_t :5;
6054 } B;
6055 } WORD1;
6056
6057 union { /* - Word 2 */
6058 vuint32_t R;
6059 struct {
6060 vuint32_t M7RE:1;
6061 vuint32_t M7WE:1;
6062 vuint32_t M6RE:1;
6063 vuint32_t M6WE:1;
6064 vuint32_t M5RE:1;
6065 vuint32_t M5WE:1;
6066 vuint32_t M4RE:1;
6067 vuint32_t M4WE:1;
6068 vuint32_t M3PE:1;
6069 vuint32_t M3SM:2;
6070 vuint32_t M3UM:3;
6071 vuint32_t M2PE:1;
6072 vuint32_t M2SM:2;
6073 vuint32_t M2UM:3;
6074 vuint32_t M1PE:1;
6075 vuint32_t M1SM:2;
6076 vuint32_t M1UM:3;
6077 vuint32_t M0PE:1;
6078 vuint32_t M0SM:2;
6079 vuint32_t M0UM:3;
6080 } B;
6081 } WORD2;
6082
6083 union { /* - Word 3 */
6084 vuint32_t R;
6085 struct {
6086 vuint32_t PID:8;
6087 vuint32_t PIDMASK:8;
6088 vuint32_t :15;
6089 vuint32_t VLD:1;
6090 } B;
6091 } WORD3;
6092
6093 }RGD[16]; /* End of Region Descriptor Structure) */
6094
6095 vuint8_t MPU_reserved2[768]; /* Reserved 768 Bytes (Base+0x0500-0x07FF) */
6096
6097 union { /* Region Descriptor Alt 0..15 (0x0800-0x083F) */
6098 vuint32_t R;
6099 struct {
6100 vuint32_t M7RE:1;
6101 vuint32_t M7WE:1;
6102 vuint32_t M6RE:1;
6103 vuint32_t M6WE:1;
6104 vuint32_t M5RE:1;
6105 vuint32_t M5WE:1;
6106 vuint32_t M4RE:1;
6107 vuint32_t M4WE:1;
6108 vuint32_t M3PE:1;
6109 vuint32_t M3SM:2;
6110 vuint32_t M3UM:3;
6111 vuint32_t M2PE:1;
6112 vuint32_t M2SM:2;
6113 vuint32_t M2UM:3;
6114 vuint32_t M1PE:1;
6115 vuint32_t M1SM:2;
6116 vuint32_t M1UM:3;
6117 vuint32_t M0PE:1;
6118 vuint32_t M0SM:2;
6119 vuint32_t M0UM:3;
6120 } B;
6121 } RGDAAC[16];
6122
6123 vuint8_t MPU_reserved3[14242]; /* Reserved 14242 Bytes (+0x0840-0x03FFF) */
6124
6125}; /* end of MPU_tag */
6126/****************************************************************************/
6127/* MODULE : CSE (Cryptographic Security Engine) */
6128/****************************************************************************/
6129struct CSE_tag {
6130
6131 union { /* CSE Control (Base+0x0000) */
6132 vuint32_t R;
6133 struct {
6134 vuint32_t :16;
6135 vuint32_t DIV:8;
6136 vuint32_t :4;
6137 vuint32_t MDIS:1;
6138 vuint32_t SUS:1;
6139 vuint32_t :1; /* vuint32_t DRE:1; removed RevD */
6140 vuint32_t CIE:1;
6141 } B;
6142 } CR;
6143
6144 union { /* CSE Status (Read Only) (Base+0x0004) */
6145 vuint32_t R;
6146 struct {
6147 vuint32_t :23;
6148 vuint32_t EX:1;
6149 vuint32_t IDB:1;
6150 vuint32_t EDB:1;
6151 vuint32_t RIN:1;
6152 vuint32_t BOK:1;
6153 vuint32_t BFN:1;
6154 vuint32_t BIN:1;
6155 vuint32_t SB:1;
6156 vuint32_t BSY:1;
6157 } B;
6158 } SR;
6159
6160 union { /* CSE Interrupt (Base+0x0008) */
6161 vuint32_t R;
6162 struct {
6163 vuint32_t :31;
6164 vuint32_t CIF:1;
6165 } B;
6166 } IR;
6167
6168 union { /* CSE Error Code (Base+0x000C) */
6169 vuint32_t R;
6170 struct {
6171 vuint32_t :27;
6172 vuint32_t EC:5;
6173 } B;
6174 } ECR;
6175
6176 vuint8_t CSE_reserved0[13]; /* Reserved 13 Bytes (Base+0x0010-0x001C) */
6177
6178 union { /* CSE Command (Base+0x0020) */
6179 vuint32_t R;
6180 struct {
6181 vuint32_t :27;
6182 vuint32_t CMD:5;
6183 } B;
6184 } CMD;
6185
6186
6187 /*-- Note parameter registers cannot be array since no P0 (SHE spec) --*/
6188
6189 union { /* CSE Paramter 1 (Base+0x0024) */
6190 vuint32_t R;
6191 struct {
6192 vuint32_t PARM:32;
6193 } B;
6194 } P1;
6195
6196 union { /* CSE Paramter 2 (Base+0x0028) */
6197 vuint32_t R;
6198 struct {
6199 vuint32_t PARM:32;
6200 } B;
6201 } P2;
6202
6203 union { /* CSE Paramter 3 (Base+0x002C) */
6204 vuint32_t R;
6205 struct {
6206 vuint32_t PARM:32;
6207 } B;
6208 } P3;
6209
6210 union { /* CSE Paramter 4 (Base+0x0030) */
6211 vuint32_t R;
6212 struct {
6213 vuint32_t PARM:32;
6214 } B;
6215 } P4;
6216
6217 union { /* CSE Paramter 5 (Base+0x0034) */
6218 vuint32_t R;
6219 struct {
6220 vuint32_t PARM:32;
6221 } B;
6222 } P5;
6223
6224 vuint8_t CSE_reserved1[16328]; /* Reserved 16328 Bytes (0x0038-0x3FFF) */
6225
6226}; /* end of CSE_tag */
6227/****************************************************************************/
6228/* MODULE : SEMA4 (Semaphores) */
6229/****************************************************************************/
6230 struct SEMA4_tag {
6231
6232 union { /* Gate 0..15 (Base+0x0000-0x000F) */
6233 vuint8_t R;
6234 struct {
6235 vuint8_t:6;
6236 vuint8_t GTFSM:2;
6237 } B;
6238 } GATE[16];
6239
6240 vuint8_t SEMA4_reserved0[48]; /* Reserved 48 Bytes (Base+0x0010-0x003F) */
6241
6242 union { /* CP0 IRQ Notification enable (Base+0x0040) */
6243 vuint16_t R;
6244 struct {
6245 vuint16_t INE0:1;
6246 vuint16_t INE1:1;
6247 vuint16_t INE2:1;
6248 vuint16_t INE3:1;
6249 vuint16_t INE4:1;
6250 vuint16_t INE5:1;
6251 vuint16_t INE6:1;
6252 vuint16_t INE7:1;
6253 vuint16_t INE8:1;
6254 vuint16_t INE9:1;
6255 vuint16_t INE10:1;
6256 vuint16_t INE11:1;
6257 vuint16_t INE12:1;
6258 vuint16_t INE13:1;
6259 vuint16_t INE14:1;
6260 vuint16_t INE15:1;
6261 } B;
6262 } CP0INE;
6263
6264 vuint8_t SEMA4_reserved1[6]; /* Reserved 6 Bytes (Base+0x0042-0x0047) */
6265
6266 union { /* CP1 IRQ Notification enable (Base+0x0048) */
6267 vuint16_t R;
6268 struct {
6269 vuint16_t INE0:1;
6270 vuint16_t INE1:1;
6271 vuint16_t INE2:1;
6272 vuint16_t INE3:1;
6273 vuint16_t INE4:1;
6274 vuint16_t INE5:1;
6275 vuint16_t INE6:1;
6276 vuint16_t INE7:1;
6277 vuint16_t INE8:1;
6278 vuint16_t INE9:1;
6279 vuint16_t INE10:1;
6280 vuint16_t INE11:1;
6281 vuint16_t INE12:1;
6282 vuint16_t INE13:1;
6283 vuint16_t INE14:1;
6284 vuint16_t INE15:1;
6285 } B;
6286 } CP1INE;
6287
6288 vuint8_t SEMA4_reserved2[54]; /* Reserved 54 Bytes (Base+0x004A-0x007F) */
6289
6290 union { /* CP0 IRQ Notification (Base+0x0080) */
6291 vuint16_t R;
6292 struct {
6293 vuint16_t GN0:1;
6294 vuint16_t GN1:1;
6295 vuint16_t GN2:1;
6296 vuint16_t GN3:1;
6297 vuint16_t GN4:1;
6298 vuint16_t GN5:1;
6299 vuint16_t GN6:1;
6300 vuint16_t GN7:1;
6301 vuint16_t GN8:1;
6302 vuint16_t GN9:1;
6303 vuint16_t GN10:1;
6304 vuint16_t GN11:1;
6305 vuint16_t GN12:1;
6306 vuint16_t GN13:1;
6307 vuint16_t GN14:1;
6308 vuint16_t GN15:1;
6309 } B;
6310 } CP0NTF;
6311
6312 vuint8_t SEMA4_reserved3[6]; /* Reserved 6 Bytes (Base+0x0082-0x0087) */
6313
6314 union { /* CP1 IRQ Notification (Base+0x0088) */
6315 vuint16_t R;
6316 struct {
6317 vuint16_t GN0:1;
6318 vuint16_t GN1:1;
6319 vuint16_t GN2:1;
6320 vuint16_t GN3:1;
6321 vuint16_t GN4:1;
6322 vuint16_t GN5:1;
6323 vuint16_t GN6:1;
6324 vuint16_t GN7:1;
6325 vuint16_t GN8:1;
6326 vuint16_t GN9:1;
6327 vuint16_t GN10:1;
6328 vuint16_t GN11:1;
6329 vuint16_t GN12:1;
6330 vuint16_t GN13:1;
6331 vuint16_t GN14:1;
6332 vuint16_t GN15:1;
6333 } B;
6334 } CP1NTF;
6335
6336 vuint8_t SEMA4_reserved4[118]; /* Reserved 118 Bytes (+0x008A-0x00FF) */
6337
6338 union { /* Reset gate (Base+0x0100) */
6339 vuint16_t R;
6340 struct {
6341 vuint16_t:2;
6342 vuint16_t RSTGSM:2;
6343 vuint16_t:1;
6344 vuint16_t RSTGMS:3;
6345 vuint16_t RSTGTN:8;
6346 } B;
6347 } RSTGT;
6348
6349 vuint8_t SEMA4_reserved5[2]; /* Reserved 2 Bytes (Base+0x0102-0x0103) */
6350
6351 union {
6352 vuint16_t R;
6353 struct {
6354 vuint16_t:2;
6355 vuint16_t RSTNSM:2;
6356 vuint16_t:1;
6357 vuint16_t RSTNMS:3;
6358 vuint16_t RSTNTN:8;
6359 } B;
6360 } RSTNTF;
6361
6362 vuint8_t SEMA4_reserved6[16122]; /* Reserved 16122 (Base+0x0106-0x3FFF) */
6363
6364 }; /* end of SEMA4_tag */
6365/****************************************************************************/
6366/* MODULE : SWT */
6367/****************************************************************************/
6368struct SWT_tag{
6369
6370 union { /* SWT Control (Base+0x0000) */
6371 vuint32_t R;
6372 struct {
6373 vuint32_t MAP0:1;
6374 vuint32_t MAP1:1;
6375 vuint32_t MAP2:1;
6376 vuint32_t MAP3:1;
6377 vuint32_t MAP4:1;
6378 vuint32_t MAP5:1;
6379 vuint32_t MAP6:1;
6380 vuint32_t MAP7:1;
6381 vuint32_t :14;
6382 vuint32_t KEY:1;
6383 vuint32_t RIA:1;
6384 vuint32_t WND:1;
6385 vuint32_t ITR:1;
6386 vuint32_t HLK:1;
6387 vuint32_t SLK:1;
6388 vuint32_t CSL:1;
6389 vuint32_t STP:1;
6390 vuint32_t FRZ:1;
6391 vuint32_t WEN:1;
6392 } B;
6393 } CR;
6394
6395 union { /* SWT Interrupt (Base+0x0004) */
6396 vuint32_t R;
6397 struct {
6398 vuint32_t :31;
6399 vuint32_t TIF:1;
6400 } B;
6401 } IR;
6402
6403 union { /* SWT Time-Out (Base+0x0008) */
6404 vuint32_t R;
6405 struct {
6406 vuint32_t WTO:32;
6407 } B;
6408 } TO;
6409
6410 union { /* SWT Window (Base+0x000C) */
6411 vuint32_t R;
6412 struct {
6413 vuint32_t WST:32;
6414 } B;
6415 } WN;
6416
6417 union { /* SWT Service (Base+0x0010) */
6418 vuint32_t R;
6419 struct {
6420 vuint32_t :16;
6421 vuint32_t WSC:16;
6422 } B;
6423 } SR;
6424
6425 union { /* SWT Counter Output (Base+0x0014) */
6426 vuint32_t R;
6427 struct {
6428 vuint32_t CNT:32;
6429 } B;
6430 } CO;
6431
6432 union { /* SWT Service Key (Base+0x0018) */
6433 vuint32_t R; /* New for Bolero 3M */
6434 struct {
6435 vuint32_t :16;
6436 vuint32_t SK:16;
6437 } B;
6438 } SK;
6439
6440}; /* end of SWT_tag */
6441/****************************************************************************/
6442/* MODULE : STM */
6443/****************************************************************************/
6444 struct STM_CHANNEL_tag{
6445
6446 union { /* STM Channel Control 0..3 */
6447 vuint32_t R;
6448 struct {
6449 vuint32_t :31;
6450 vuint32_t CEN:1;
6451 } B;
6452 } CCR;
6453
6454 union { /* STM Channel Interrupt 0..3 */
6455 vuint32_t R;
6456 struct {
6457 vuint32_t :31;
6458 vuint32_t CIF:1;
6459 } B;
6460 } CIR;
6461
6462 union { /* STM Channel Compare 0..3 */
6463 vuint32_t R;
6464 struct {
6465 vuint32_t CMP:32;
6466 } B;
6467 } CMP;
6468
6469 vuint8_t STM_CHANNEL_reserved[4]; /* Reserved 4 bytes between ch reg's */
6470
6471 }; /* end of STM_CHANNEL_tag */
6472
6473
6474struct STM_tag{
6475
6476 union { /* STM Control (Base+0x0000) */
6477 vuint32_t R;
6478 struct {
6479 vuint32_t :16;
6480 vuint32_t CPS:8;
6481 vuint32_t :6;
6482 vuint32_t FRZ:1;
6483 vuint32_t TEN:1;
6484 } B;
6485 } CR;
6486
6487 union { /* STM Count (Base+0x0004) */
6488 vuint32_t R;
6489 } CNT;
6490
6491 vuint8_t STM_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
6492
6493 struct STM_CHANNEL_tag CH[4]; /*STM Channels 0..3 (Base+0x0010-0x0048) */
6494
6495}; /* end of STM_tag */
6496/****************************************************************************/
6497/* MODULE : ECSM */
6498/****************************************************************************/
6499struct ECSM_tag{
6500
6501 union { /* ECSM Processor Core Type (Base+0x0000) */
6502 vuint16_t R;
6503 } PCT;
6504
6505 union { /* ECSM Revision (Base+0x0002) */
6506 vuint16_t R;
6507 } REV;
6508
6509 vuint8_t ECSM_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */
6510
6511 union { /* ECSM IPS Module Configuration (Base+0x0008) */
6512 vuint32_t R;
6513 } IMC;
6514
6515 vuint8_t ECSM_reserved1[19]; /* Reserved 19 bytes (Base+0x000C-0x001E) */
6516
6517 union { /* ECSM Miscellaneous Interrupt (Base+0x001F) */
6518 vuint8_t R;
6519 struct {
6520 vuint8_t FB0AI:1;
6521 vuint8_t FB0SI:1;
6522 vuint8_t FB1AI:1;
6523 vuint8_t FB1SI:1;
6524 vuint8_t :4;
6525 } B;
6526 } MIR;
6527
6528 vuint8_t ECSM_reserved3[4]; /* Reserved 4 bytes (Base+0x0020-0x0023) */
6529
6530 union { /*ECSM Miscellaneous User-Defined Control (+0x0024)*/
6531 vuint32_t R;
6532 struct {
6533 vuint32_t XBAR_ARB:1;
6534 vuint32_t RAM_WS:1;
6535 vuint32_t :19;
6536 vuint32_t MUDCR:11;
6537 } B;
6538 } MUDCR;
6539
6540 vuint8_t ECSM_reserved4[27]; /* Reserved 27 bytes (Base+0x0028-0x0042) */
6541
6542 union { /* ECSM ECC Configuration (Base+0x0043) */
6543 vuint8_t R;
6544 struct {
6545 vuint8_t :2;
6546 vuint8_t ER1BR:1;
6547 vuint8_t EF1BR:1;
6548 vuint8_t :2;
6549 vuint8_t ERNCR:1;
6550 vuint8_t EFNCR:1;
6551 } B;
6552 } ECR;
6553
6554 vuint8_t ECSM_reserved5[3]; /* Reserved 3 bytes (Base+0x0044-0x0046) */
6555
6556 union { /* ECSM ECC Status (Base+0x0047) */
6557 vuint8_t R;
6558 struct {
6559 vuint8_t :2;
6560 vuint8_t R1BC:1;
6561 vuint8_t F1BC:1;
6562 vuint8_t :2;
6563 vuint8_t RNCE:1;
6564 vuint8_t FNCE:1;
6565 } B;
6566 } ESR;
6567
6568 vuint8_t ECSM_reserved6[2]; /* Reserved 2 bytes (Base+0x0048-0x0049) */
6569
6570 union { /* ECSM ECC Error Generation (Base+0x004A) */
6571 vuint16_t R;
6572 struct {
6573 vuint16_t :2;
6574 vuint16_t FRC1BI:1;
6575 vuint16_t FR11BI:1;
6576 vuint16_t :2;
6577 vuint16_t FRCNCI:1;
6578 vuint16_t FR1NCI:1;
6579 vuint16_t :1;
6580 vuint16_t ERRBIT:7;
6581 } B;
6582 } EEGR;
6583
6584 vuint8_t ECSM_reserved7[4]; /* Reserved 4 bytes (Base+0x004C-0x004F) */
6585
6586 union { /* ECSM Flash ECC Address(Base+0x0050) */
6587 vuint32_t R;
6588 } FEAR;
6589
6590 vuint8_t ECSM_reserved8[2]; /* Reserved 2 bytes (Base+0x0054-0x0055) */
6591
6592 union { /* ECSM Flash ECC Master Number (Base+0x0056) */
6593 vuint8_t R;
6594 struct {
6595 vuint8_t :4;
6596 vuint8_t FEMR:4;
6597 } B;
6598 } FEMR;
6599
6600 union { /* ECSM Flash ECC Attributes (Base+0x0057) */
6601 vuint8_t R;
6602 struct {
6603 vuint8_t WRITE:1;
6604 vuint8_t SIZE:3;
6605 vuint8_t PROTECTION:4;
6606 } B;
6607 } FEAT;
6608
6609 vuint8_t ECSM_reserved9[4]; /* Reserved 4 bytes (Base+0x0058-0x005B) */
6610
6611 union { /* ECSM Flash ECC Data (Base+0x005C) */
6612 vuint32_t R;
6613 } FEDR;
6614
6615 union { /* ECSM RAM ECC Address (Base+0x0060) */
6616 vuint32_t R;
6617 } REAR;
6618
6619 vuint8_t ECSM_reserved10[1]; /* Reserved 1 bytes (Base+0x0064) */
6620
6621 union { /* ECSM RAM ECC Address (Base+0x0065) */
6622 vuint8_t R;
6623 } RESR;
6624
6625 union { /* ECSM RAM ECC Master Number (Base+0x0066) */
6626 vuint8_t R;
6627 struct {
6628 vuint8_t :4;
6629 vuint8_t REMR:4;
6630 } B;
6631 } REMR;
6632
6633 union { /* ECSM RAM ECC Attributes (Base+0x0067) */
6634 vuint8_t R;
6635 struct {
6636 vuint8_t WRITE:1;
6637 vuint8_t SIZE:3;
6638 vuint8_t PROTECTION:4;
6639 } B;
6640 } REAT;
6641
6642 vuint8_t ECSM_reserved11[4]; /* Reserved 4 bytes (Base+0x0068-0x006B) */
6643
6644 union { /* ECSM RAM ECC Data (Base+0x006C) */
6645 vuint32_t R;
6646 } REDR;
6647
6648}; /* end of ECSM_tag */
6649/****************************************************************************/
6650/* MODULE : eDMA */
6651/****************************************************************************/
6652
6653 /* There are 4 different TCD structures which should be used based on */
6654 /* how the DMA is configured as below. CAUTION - Do not mix TCD's */
6655 /* */
6656 /* Channel Linking Minor Loop Mapping Addressing TCD */
6657 /* OFF OFF XBAR.TCD[x] */
6658 /* OFF ON XBAR.ML_TCD[x] */
6659 /* ON OFF XBAR.CL_TCD[X] */
6660 /* ON ON XBAR.MLCL_TCD[X] */
6661 /* */
6662
6663
6664 /* (1) - Standard TCD (Channel Linking OFF, Minor Loop mapping OFF */
6665 struct EDMA_TCD_STD_tag {
6666
6667 vuint32_t SADDR; /* Source address */
6668
6669 vuint16_t SMOD:5; /* Source address modulo */
6670 vuint16_t SSIZE:3; /* Source data transfer size */
6671 vuint16_t DMOD:5; /* Destination address modulo */
6672 vuint16_t DSIZE:3; /* Destination data transfer size */
6673 vint16_t SOFF; /* Source address signed offset */
6674
6675 vuint32_t NBYTES; /* Inner "minor" byte transfer count */
6676
6677 vint32_t SLAST; /* Last source address adjustment */
6678
6679 vuint32_t DADDR; /* Destination address */
6680
6681 vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
6682 vuint16_t CITER:15; /* Current Major iteration count */
6683 vint16_t DOFF; /* Destination address signed offset */
6684
6685 vint32_t DLAST_SGA; /* Last desitination address adjustment */
6686
6687 vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
6688 vuint16_t BITER:15; /* Starting major iteration count */
6689 vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
6690 vuint16_t MAJORLINKCH:6; /* Link channel number */
6691 vuint16_t DONE:1; /* Channel done */
6692 vuint16_t ACTIVE:1; /* Channel active */
6693 vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
6694 vuint16_t E_SG:1; /* Enable scatter/gather processing */
6695 vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
6696 vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
6697 vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
6698 vuint16_t START:1; /* Chanel start */
6699
6700 }; /* End of Standard TCD tag */
6701
6702
6703
6704 /* (2) - ML_TCD (Channel Linking OFF, Minor Loop mapping Enabled */
6705 /* (EMLM = 1) */
6706 struct EDMA_TCD_MLMIRROR_tag {
6707
6708 vuint32_t SADDR; /* Source address */
6709
6710 vuint16_t SMOD:5; /* Source address modulo */
6711 vuint16_t SSIZE:3; /* Source data transfer size */
6712 vuint16_t DMOD:5; /* Destination address modulo */
6713 vuint16_t DSIZE:3; /* Destination data transfer size */
6714 vint16_t SOFF; /* Source address signed offset */
6715
6716 vuint32_t SMLOE:1; /* Source minor loop offset enabled */
6717 vuint32_t DMLOE:1; /* Destination minor loop offset enable */
6718 vuint32_t MLOFF:20; /* Minor loop offset */
6719 vuint32_t NBYTES:10; /* Inner "minor" byte transfer count */
6720
6721 vint32_t SLAST; /* Last source address adjustment */
6722
6723 vuint32_t DADDR; /* Destination address */
6724
6725 vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
6726 vuint16_t CITER:15; /* Current Major iteration count */
6727 vint16_t DOFF; /* Destination address signed offset */
6728
6729 vint32_t DLAST_SGA; /* Last desitination address adjustment */
6730
6731 vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
6732 vuint16_t BITER:15; /* Starting major iteration count */
6733 vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
6734 vuint16_t MAJORLINKCH:6; /* Link channel number */
6735 vuint16_t DONE:1; /* Channel done */
6736 vuint16_t ACTIVE:1; /* Channel active */
6737 vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
6738 vuint16_t E_SG:1; /* Enable scatter/gather processing */
6739 vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
6740 vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
6741 vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
6742 vuint16_t START:1; /* Chanel start */
6743
6744 }; /* End of EDMA_TCD_MLMIRROR_tag */
6745
6746
6747
6748 /* (3) - CL_TCD (Channel Linking Enabled, Minor Loop mapping OFF */
6749 /* (CITERE_LINK = BITERE_LINK = 1) */
6750 struct EDMA_TCD_CHLINK_tag {
6751
6752 vuint32_t SADDR; /* Source address */
6753
6754 vuint16_t SMOD:5; /* Source address modulo */
6755 vuint16_t SSIZE:3; /* Source data transfer size */
6756 vuint16_t DMOD:5; /* Destination address modulo */
6757 vuint16_t DSIZE:3; /* Destination data transfer size */
6758 vint16_t SOFF; /* Source address signed offset */
6759
6760 vuint32_t NBYTES; /* Inner "minor" byte transfer count */
6761
6762 vint32_t SLAST; /* Last source address adjustment */
6763
6764 vuint32_t DADDR; /* Destination address */
6765
6766 vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
6767 vuint16_t CITERLINKCH:6; /* Link channel number */
6768 vuint16_t CITER:9; /* Current Major iteration count */
6769 vint16_t DOFF; /* Destination address signed offset */
6770
6771 vint32_t DLAST_SGA; /* Last desitination address adjustment */
6772
6773 vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
6774 vuint16_t BITERLINKCH:6; /* Link channel number */
6775 vuint16_t BITER:9; /* Starting Major iteration count */
6776 vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
6777 vuint16_t MAJORLINKCH:6; /* Link channel number */
6778 vuint16_t DONE:1; /* Channel done */
6779 vuint16_t ACTIVE:1; /* Channel active */
6780 vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
6781 vuint16_t E_SG:1; /* Enable scatter/gather processing */
6782 vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
6783 vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
6784 vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
6785 vuint16_t START:1; /* Chanel start */
6786
6787 }; /* end of EDMA_TCD_CHLINK_tag */
6788
6789
6790
6791 /* (4) - CL_TCD (Channel Linking Enabled, Minor Loop mapping Enabled */
6792 /* (CITERE_LINK = BITERE_LINK = 1, EMLM = 1) */
6793 struct EDMA_TCD_MLMIRROR_CHLINK_tag {
6794
6795 vuint32_t SADDR; /* Source address */
6796
6797 vuint16_t SMOD:5; /* Source address modulo */
6798 vuint16_t SSIZE:3; /* Source data transfer size */
6799 vuint16_t DMOD:5; /* Destination address modulo */
6800 vuint16_t DSIZE:3; /* Destination data transfer size */
6801 vint16_t SOFF; /* Source address signed offset */
6802
6803 vuint32_t SMLOE:1; /* Source minor loop offset enabled */
6804 vuint32_t DMLOE:1; /* Destination minor loop offset enable */
6805 vuint32_t MLOFF:20; /* Minor loop offset */
6806 vuint32_t NBYTES:10; /* Inner "minor" byte transfer count */
6807
6808 vint32_t SLAST; /* Last source address adjustment */
6809
6810 vuint32_t DADDR; /* Destination address */
6811
6812 vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
6813 vuint16_t CITERLINKCH:6; /* Link channel number */
6814 vuint16_t CITER:9; /* Current Major iteration count */
6815 vint16_t DOFF; /* Destination address signed offset */
6816
6817 vint32_t DLAST_SGA; /* Last desitination address adjustment */
6818
6819 vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
6820 vuint16_t BITERLINKCH:6; /* Link channel number */
6821 vuint16_t BITER:9; /* Starting Major iteration count */
6822 vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
6823 vuint16_t MAJORLINKCH:6; /* Link channel number */
6824 vuint16_t DONE:1; /* Channel done */
6825 vuint16_t ACTIVE:1; /* Channel active */
6826 vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
6827 vuint16_t E_SG:1; /* Enable scatter/gather processing */
6828 vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
6829 vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
6830 vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
6831 vuint16_t START:1; /* Chanel start */
6832
6833 }; /* end of EDMA_TCD_MLMIRROR_CHLINK_tag */
6834
6835
6836
6837
6838struct EDMA_tag {
6839
6840 union { /* Control (Base+0x0000) */
6841 vuint32_t R;
6842 struct {
6843 vuint32_t:14;
6844 vuint32_t CX:1;
6845 vuint32_t ECX:1;
6846 vuint32_t:2; /* vuint32_t GRP3PRI:2; (Not implemented B3M) */
6847 vuint32_t:2; /* vuint32_t GRP2PRI:2; (Not implemented B3M) */
6848 vuint32_t:2; /* vuint32_t GRP1PRI:2; (Not implemented B3M) */
6849 vuint32_t GRP0PRI:2;
6850 vuint32_t EMLM:1;
6851 vuint32_t CLM:1;
6852 vuint32_t HALT:1;
6853 vuint32_t HOE:1;
6854 vuint32_t ERGA:1;
6855 vuint32_t ERCA:1;
6856 vuint32_t EDBG:1;
6857 vuint32_t EBW:1;
6858 } B;
6859 } CR;
6860
6861 union { /* Error Status (Base+0x0004) */
6862 vuint32_t R;
6863 struct {
6864 vuint32_t VLD:1;
6865 vuint32_t:14;
6866 vuint32_t:1; /* vuint32_t ECX:1; (Not implemented B3M) */
6867 vuint32_t:1; /* vuint32_t GPE:1; (Not implemented B3M) */
6868 vuint32_t CPE:1;
6869 vuint32_t ERRCHN:6;
6870 vuint32_t SAE:1;
6871 vuint32_t SOE:1;
6872 vuint32_t DAE:1;
6873 vuint32_t DOE:1;
6874 vuint32_t NCE:1;
6875 vuint32_t SGE:1;
6876 vuint32_t SBE:1;
6877 vuint32_t DBE:1;
6878 } B;
6879 } ESR;
6880
6881 vuint8_t eDMA_reserved0[4]; /* Reserved 4 bytes (Base+0x0008-0x000B) */
6882
6883 union { /* Enable Request Low Ch31..0 (Base+0x000C) */
6884 vuint32_t R;
6885 struct {
6886 vuint32_t ERQ31:1;
6887 vuint32_t ERQ30:1;
6888 vuint32_t ERQ29:1;
6889 vuint32_t ERQ28:1;
6890 vuint32_t ERQ27:1;
6891 vuint32_t ERQ26:1;
6892 vuint32_t ERQ25:1;
6893 vuint32_t ERQ24:1;
6894 vuint32_t ERQ23:1;
6895 vuint32_t ERQ22:1;
6896 vuint32_t ERQ21:1;
6897 vuint32_t ERQ20:1;
6898 vuint32_t ERQ19:1;
6899 vuint32_t ERQ18:1;
6900 vuint32_t ERQ17:1;
6901 vuint32_t ERQ16:1;
6902 vuint32_t ERQ15:1;
6903 vuint32_t ERQ14:1;
6904 vuint32_t ERQ13:1;
6905 vuint32_t ERQ12:1;
6906 vuint32_t ERQ11:1;
6907 vuint32_t ERQ10:1;
6908 vuint32_t ERQ09:1;
6909 vuint32_t ERQ08:1;
6910 vuint32_t ERQ07:1;
6911 vuint32_t ERQ06:1;
6912 vuint32_t ERQ05:1;
6913 vuint32_t ERQ04:1;
6914 vuint32_t ERQ03:1;
6915 vuint32_t ERQ02:1;
6916 vuint32_t ERQ01:1;
6917 vuint32_t ERQ00:1;
6918 } B;
6919 } ERQRL;
6920
6921 vuint8_t eDMA_reserved1[4]; /* Reserved 4 bytes (Base+0x0010-0x0013) */
6922
6923 union { /* nable Error Interrupt Low (Base+0x0014) */
6924 vuint16_t R;
6925 struct {
6926 vuint32_t EEI31:1;
6927 vuint32_t EEI30:1;
6928 vuint32_t EEI29:1;
6929 vuint32_t EEI28:1;
6930 vuint32_t EEI27:1;
6931 vuint32_t EEI26:1;
6932 vuint32_t EEI25:1;
6933 vuint32_t EEI24:1;
6934 vuint32_t EEI23:1;
6935 vuint32_t EEI22:1;
6936 vuint32_t EEI21:1;
6937 vuint32_t EEI20:1;
6938 vuint32_t EEI19:1;
6939 vuint32_t EEI18:1;
6940 vuint32_t EEI17:1;
6941 vuint32_t EEI16:1;
6942 vuint32_t EEI15:1;
6943 vuint32_t EEI14:1;
6944 vuint32_t EEI13:1;
6945 vuint32_t EEI12:1;
6946 vuint32_t EEI11:1;
6947 vuint32_t EEI10:1;
6948 vuint32_t EEI09:1;
6949 vuint32_t EEI08:1;
6950 vuint32_t EEI07:1;
6951 vuint32_t EEI06:1;
6952 vuint32_t EEI05:1;
6953 vuint32_t EEI04:1;
6954 vuint32_t EEI03:1;
6955 vuint32_t EEI02:1;
6956 vuint32_t EEI01:1;
6957 vuint32_t EEI00:1;
6958 } B;
6959 } EEIRL;
6960
6961 union { /* DMA Set Enable Request (Base+0x0018) */
6962 vuint8_t R;
6963 struct {
6964 vuint8_t NOP:1;
6965 vuint8_t SERQ:7;
6966 } B;
6967 } SERQR;
6968
6969 union { /* DMA Clear Enable Request (Base+0x0019) */
6970 vuint8_t R;
6971 struct {
6972 vuint8_t:1; /* vuint8_t NOP:1; */
6973 vuint8_t CERQ:7;
6974 } B;
6975 } CERQR;
6976
6977 union { /* DMA Set Enable Error Interrupt (Base+0x001A) */
6978 vuint8_t R;
6979 struct {
6980 vuint8_t:1; /* vuint8_t NOP:1; */
6981 vuint8_t SEEI:7;
6982 } B;
6983 } SEEIR;
6984
6985 union { /* DMA Clr Enable Error Interrupt (Base+0x001B) */
6986 vuint8_t R;
6987 struct {
6988 vuint8_t:1;
6989 vuint8_t CEEI:7;
6990 } B;
6991 } CEEIR;
6992
6993 union { /* DMA Clear Interrupt Request (Base+0x001C) */
6994 vuint8_t R;
6995 struct {
6996 vuint8_t:1; /* vuint8_t NOP:1; */
6997 vuint8_t CINT:7;
6998 } B;
6999 } CIRQR;
7000
7001 union { /* DMA Clear error (Base+0x001D) */
7002 vuint8_t R;
7003 struct {
7004 vuint8_t:1; /* vuint8_t NOP:1; */
7005 vuint8_t CERR:7;
7006 } B;
7007 } CERR;
7008
7009 union { /* DMA Set Start Bit (Base+0x001E) */
7010 vuint8_t R;
7011 struct {
7012 vuint8_t:1; /* vuint8_t NOP:1; */
7013 vuint8_t SSB:7;
7014 } B;
7015 } SSBR;
7016
7017 union { /* DMA Clear Done Status Bit (Base+0x001F) */
7018 vuint8_t R;
7019 struct {
7020 vuint8_t:1; /* vuint8_t NOP:1; */
7021 vuint8_t CDSB:7;
7022 } B;
7023 } CDSBR;
7024
7025 vuint8_t eDMA_reserved2[4]; /* Reserved 4 bytes (Base+0x0020-0x0023) */
7026
7027 union { /* DMA Interrupt Req Low Ch31..0 (+0x0024) */
7028 vuint32_t R;
7029 struct {
7030 vuint32_t INT31:1;
7031 vuint32_t INT30:1;
7032 vuint32_t INT29:1;
7033 vuint32_t INT28:1;
7034 vuint32_t INT27:1;
7035 vuint32_t INT26:1;
7036 vuint32_t INT25:1;
7037 vuint32_t INT24:1;
7038 vuint32_t INT23:1;
7039 vuint32_t INT22:1;
7040 vuint32_t INT21:1;
7041 vuint32_t INT20:1;
7042 vuint32_t INT19:1;
7043 vuint32_t INT18:1;
7044 vuint32_t INT17:1;
7045 vuint32_t INT16:1;
7046 vuint32_t INT15:1;
7047 vuint32_t INT14:1;
7048 vuint32_t INT13:1;
7049 vuint32_t INT12:1;
7050 vuint32_t INT11:1;
7051 vuint32_t INT10:1;
7052 vuint32_t INT09:1;
7053 vuint32_t INT08:1;
7054 vuint32_t INT07:1;
7055 vuint32_t INT06:1;
7056 vuint32_t INT05:1;
7057 vuint32_t INT04:1;
7058 vuint32_t INT03:1;
7059 vuint32_t INT02:1;
7060 vuint32_t INT01:1;
7061 vuint32_t INT00:1;
7062 } B;
7063 } IRQRL;
7064
7065 vuint8_t eDMA_reserved3[4]; /* Reserved 4 bytes (Base+0x0028-0x002B) */
7066
7067 union { /* DMA Error Low Ch31..0 (Base+0x002C) */
7068 vuint32_t R;
7069 struct {
7070 vuint32_t ERR31:1;
7071 vuint32_t ERR30:1;
7072 vuint32_t ERR29:1;
7073 vuint32_t ERR28:1;
7074 vuint32_t ERR27:1;
7075 vuint32_t ERR26:1;
7076 vuint32_t ERR25:1;
7077 vuint32_t ERR24:1;
7078 vuint32_t ERR23:1;
7079 vuint32_t ERR22:1;
7080 vuint32_t ERR21:1;
7081 vuint32_t ERR20:1;
7082 vuint32_t ERR19:1;
7083 vuint32_t ERR18:1;
7084 vuint32_t ERR17:1;
7085 vuint32_t ERR16:1;
7086 vuint32_t ERR15:1;
7087 vuint32_t ERR14:1;
7088 vuint32_t ERR13:1;
7089 vuint32_t ERR12:1;
7090 vuint32_t ERR11:1;
7091 vuint32_t ERR10:1;
7092 vuint32_t ERR09:1;
7093 vuint32_t ERR08:1;
7094 vuint32_t ERR07:1;
7095 vuint32_t ERR06:1;
7096 vuint32_t ERR05:1;
7097 vuint32_t ERR04:1;
7098 vuint32_t ERR03:1;
7099 vuint32_t ERR02:1;
7100 vuint32_t ERR01:1;
7101 vuint32_t ERR00:1;
7102 } B;
7103 } ERL;
7104
7105 vuint8_t eDMA_reserved4[4]; /* Reserved 4 bytes (Base+0x0030-0x0033) */
7106
7107 union { /* DMA Hardware Request Stat Low (Base+0x0034) */
7108 vuint32_t R;
7109 struct {
7110 vuint32_t HRS31:1;
7111 vuint32_t HRS30:1;
7112 vuint32_t HRS29:1;
7113 vuint32_t HRS28:1;
7114 vuint32_t HRS27:1;
7115 vuint32_t HRS26:1;
7116 vuint32_t HRS25:1;
7117 vuint32_t HRS24:1;
7118 vuint32_t HRS23:1;
7119 vuint32_t HRS22:1;
7120 vuint32_t HRS21:1;
7121 vuint32_t HRS20:1;
7122 vuint32_t HRS19:1;
7123 vuint32_t HRS18:1;
7124 vuint32_t HRS17:1;
7125 vuint32_t HRS16:1;
7126 vuint32_t HRS15:1;
7127 vuint32_t HRS14:1;
7128 vuint32_t HRS13:1;
7129 vuint32_t HRS12:1;
7130 vuint32_t HRS11:1;
7131 vuint32_t HRS10:1;
7132 vuint32_t HRS09:1;
7133 vuint32_t HRS08:1;
7134 vuint32_t HRS07:1;
7135 vuint32_t HRS06:1;
7136 vuint32_t HRS05:1;
7137 vuint32_t HRS04:1;
7138 vuint32_t HRS03:1;
7139 vuint32_t HRS02:1;
7140 vuint32_t HRS01:1;
7141 vuint32_t HRS00:1;
7142 } B;
7143 } HRSL;
7144
7145 vuint8_t eDMA_reserved5[200]; /* Reserved 200 bytes (Base+0x0038-0x00FF)*/
7146
7147 union { /* Channel n Priority (Base+0x0100-0x011F) */
7148 vuint8_t R;
7149 struct {
7150 vuint8_t ECP:1;
7151 vuint8_t DPA:1;
7152 vuint8_t GRPPRI:2;
7153 vuint8_t CHPRI:4;
7154 } B;
7155 } CPR[32];
7156
7157 vuint8_t eDMA_reserved6[3808]; /* Reserved 3808 bytes (+0x0120-0x0FFF) */
7158
7159
7160 union { /* 4 different TCD definitions depending on operating mode */
7161
7162 /* Default TCD (Channel Linking and Minor Loop Maping disabled) */
7163 struct EDMA_TCD_STD_tag TCD[32];
7164
7165 /* ML_TCD (Channel Linking disabled, Minor Loop Mapping enabled) */
7166 struct EDMA_TCD_MLMIRROR_tag ML_TCD[32];
7167
7168 /* CL_TCD (Channel Linking enabled, Minor Loop Mapping disabled) */
7169 struct EDMA_TCD_CHLINK_tag CL_TCD[32];
7170
7171 /* MLCL_TCD (Channel Linking enabled, Minor Loop Mapping enabled) */
7172 struct EDMA_TCD_MLMIRROR_CHLINK_tag MLCL_TCD[32];
7173 };
7174
7175}; /* end of EDMA_tag */
7176/*************************************************************************/
7177/* MODULE : INTC */
7178/*************************************************************************/
7179
7180struct INTC_tag {
7181
7182 union { /* INTC Module Configuration (Base+0x0000) */
7183 vuint32_t R;
7184 struct {
7185 vuint32_t:18;
7186 vuint32_t VTES_PRC1:1;
7187 vuint32_t:4;
7188 vuint32_t HVEN_PRC1:1;
7189 vuint32_t:2;
7190 vuint32_t VTES_PRC0:1;
7191 vuint32_t:4;
7192 vuint32_t HVEN_PRC0:1;
7193 } B;
7194 } MCR;
7195
7196 vuint8_t INTC_reserved0[4]; /* reserved 4 bytes (Base+0x0004-0x0007) */
7197
7198 union { /* INTC Current Priority Proc0 (Z4) (Base+0x0008) */
7199 vuint32_t R;
7200 struct {
7201 vuint32_t:28;
7202 vuint32_t PRI:4;
7203 } B;
7204 } CPR_PRC0;
7205
7206 union { /* INTC Current Priority Proc1 (Z0) (Base+0x000C) */
7207 vuint32_t R;
7208 struct {
7209 vuint32_t:28;
7210 vuint32_t PRI:4;
7211 } B;
7212 } CPR_PRC1;
7213
7214 union { /* INTC Interrupt Acknowledge Proc0 (Z4) (Base+0x0010) */
7215 vuint32_t R;
7216 struct {
7217 vuint32_t VTBA_PRC0:21;
7218 vuint32_t INTVEC_PRC0:9;
7219 vuint32_t:2;
7220 } B;
7221 } IACKR_PRC0;
7222
7223 union { /* INTC Interrupt Acknowledge Proc1 (Z0) (Base+0x0014) */
7224 vuint32_t R;
7225 struct {
7226 vuint32_t VTBA_PRC1:21;
7227 vuint32_t INTVEC_PRC1:9;
7228 vuint32_t:2;
7229 } B;
7230 } IACKR_PRC1;
7231
7232 union { /* INTC End Of Interrupt Proc0 (Z4) (Base+0x0018) */
7233 vuint32_t R;
7234 /* CHIBIOS FIX
7235 struct {
7236 vuint32_t:32;
7237 } B;*/
7238 } EOIR_PRC0;
7239
7240 union { /* INTC End Of Interrupt Proc1 (Z0) (Base+0x001C) */
7241 vuint32_t R;
7242 /* CHIBIOS FIX
7243 struct {
7244 vuint32_t:32;
7245 } B;*/
7246 } EOIR_PRC1;
7247
7248 union { /* INTC Software Set/Clear Interrupt0-7 (+0x0020-0x0027) */
7249 vuint8_t R;
7250 struct {
7251 vuint8_t:6;
7252 vuint8_t SET:1;
7253 vuint8_t CLR:1;
7254 } B;
7255 } SSCIR[8];
7256
7257 vuint8_t INTC_reserved1[24]; /* Reserved 24 bytes (Base+0x0028-0x003F) */
7258
7259 union { /* INTC Priority Select (Base+0x0040-0x0157) */
7260 vuint8_t R;
7261 struct {
7262 vuint8_t PRC_SEL:2;
7263 vuint8_t:2;
7264 vuint8_t PRI:4;
7265 } B;
7266 } PSR[279];
7267
7268}; /* end of INTC_tag */
7269/****************************************************************************/
7270/* MODULE : FEC (Fast Ethernet Controller) */
7271/****************************************************************************/
7272struct FEC_tag {
7273
7274 vuint8_t FEC_reserved0[4100]; /*Reserved 4100 bytes (Base+0x0000-0x0103)*/
7275
7276 union { /* FEC Interrupt Event (Base+0x1004) */
7277 vuint32_t R;
7278 struct {
7279 vuint32_t HBERR:1;
7280 vuint32_t BABR:1;
7281 vuint32_t BABT:1;
7282 vuint32_t GRA:1;
7283 vuint32_t TXF:1;
7284 vuint32_t TXB:1;
7285 vuint32_t RXF:1;
7286 vuint32_t RXB:1;
7287 vuint32_t MII:1;
7288 vuint32_t EBERR:1;
7289 vuint32_t LC:1;
7290 vuint32_t RL:1;
7291 vuint32_t UN:1;
7292 vuint32_t:19;
7293 } B;
7294 } EIR;
7295
7296 union { /* Interrupt Mask (Base+0x1008) */
7297 vuint32_t R;
7298 struct {
7299 vuint32_t HBERR:1;
7300 vuint32_t BABR:1;
7301 vuint32_t BABT:1;
7302 vuint32_t GRA:1;
7303 vuint32_t TXF:1;
7304 vuint32_t TXB:1;
7305 vuint32_t RXF:1;
7306 vuint32_t RXB:1;
7307 vuint32_t MII:1;
7308 vuint32_t EBERR:1;
7309 vuint32_t LC:1;
7310 vuint32_t RL:1;
7311 vuint32_t UN:1;
7312 vuint32_t:19;
7313 } B;
7314 } EIMR;
7315
7316 vuint8_t FEC_reserved1[4]; /* Reserved 4 Bytes (Base+0x100C-0x100F) */
7317
7318 union { /* FEC Receive Descriptor Active (Base+0x1010) */
7319 vuint32_t R;
7320 struct {
7321 vuint32_t:7;
7322 vuint32_t R_DES_ACTIVE:1;
7323 vuint32_t:24;
7324 } B;
7325 } RDAR;
7326
7327 union { /* FEC TX Descriptor Active (Base+0x1014) */
7328 vuint32_t R;
7329 struct {
7330 vuint32_t:7;
7331 vuint32_t X_DES_ACTIVE:1;
7332 vuint32_t:24;
7333 } B;
7334 } TDAR;
7335
7336 vuint8_t FEC_reserved2[12]; /* Reserved 12 Bytes (Base+0x1018-0x1023) */
7337
7338 union { /* FEC Ethernet Control (Base+0x1024) */
7339 vuint32_t R;
7340 struct {
7341 vuint32_t:30;
7342 vuint32_t ETHER_EN:1;
7343 vuint32_t RESET:1;
7344 } B;
7345 } ECR;
7346
7347 vuint8_t FEC_reserved3[24]; /* Reserved 24 Bytes (Base+0x1028-0x103F) */
7348
7349 union { /* FEC Management Frame (Base+0x1040) */
7350 vuint32_t R;
7351 struct {
7352 vuint32_t ST:2;
7353 vuint32_t OP:2;
7354 vuint32_t PA:5;
7355 vuint32_t RA:5;
7356 vuint32_t TA:2;
7357 vuint32_t DATA:16;
7358 } B;
7359 } MDATA;
7360
7361 union { /* FEC MII Speed Control (Base+0x1044) */
7362 vuint32_t R;
7363 struct {
7364 vuint32_t:24;
7365 vuint32_t DIS_PREAMBLE:1;
7366 vuint32_t MII_SPEED:6;
7367 vuint32_t:1;
7368 } B;
7369 } MSCR;
7370
7371 vuint8_t FEC_reserved4[28]; /* Reserved 28 Bytes (Base+0x1048-0x1063) */
7372
7373 union { /* FEC MIB Control (Base+0x1064) */
7374 vuint32_t R;
7375 struct {
7376 vuint32_t MIB_DISABLE:1;
7377 vuint32_t MIB_IDLE:1;
7378 vuint32_t:30;
7379 } B;
7380 } MIBC;
7381
7382 vuint8_t FEC_reserved5[28]; /* Reserved 28 Bytes (Base+0x1068-0x1083) */
7383
7384 union { /* FEC Receive Control (Base+0x1084) */
7385 vuint32_t R;
7386 struct {
7387 vuint32_t:5;
7388 vuint32_t MAX_FL:11;
7389 vuint32_t:10;
7390 vuint32_t FCE:1;
7391 vuint32_t BC_REJ:1;
7392 vuint32_t PROM:1;
7393 vuint32_t MII_MODE:1;
7394 vuint32_t DRT:1;
7395 vuint32_t LOOP:1;
7396 } B;
7397 } RCR;
7398
7399 vuint8_t FEC_reserved6[60]; /* Reserved 60 Bytes (Base+0x1088-0x10C3) */
7400
7401 union { /* FEC Transmit Control (Base+0x10C4) */
7402 vuint32_t R;
7403 struct {
7404 vuint32_t:27;
7405 vuint32_t RFC_PAUSE:1;
7406 vuint32_t TFC_PAUSE:1;
7407 vuint32_t FDEN:1;
7408 vuint32_t HBC:1;
7409 vuint32_t GTS:1;
7410 } B;
7411 } TCR;
7412
7413 vuint8_t FEC_reserved7[28]; /* Reserved 28 Bytes (Base+0x10C8-0x10E3) */
7414
7415 union { /* FEC Physical Address Low (Base+0x10E4) */
7416 vuint32_t R;
7417 struct {
7418 vuint32_t PADDR1:32;
7419 } B;
7420 } PALR;
7421
7422 union { /* FEC Physical Address High (Base+0x10E8) */
7423 vuint32_t R;
7424 struct {
7425 vuint32_t PADDR2:16;
7426 vuint32_t TYPE:16;
7427 } B;
7428 } PAUR;
7429
7430 union { /* Opcode/Pause Duration (Base+0x10EC) */
7431 vuint32_t R;
7432 struct {
7433 vuint32_t OPCODE:16;
7434 vuint32_t PAUSE_DUR:16;
7435 } B;
7436 } OPD;
7437
7438 vuint8_t FEC_reserved8[40]; /* Reserved 40 Bytes (Base+0x10F0-0x1117) */
7439
7440 union { /*FEC Descriptor Individual Upper Addr (+0x1118)*/
7441 vuint32_t R;
7442 struct {
7443 vuint32_t IADDR1:32;
7444 } B;
7445 } IAUR;
7446
7447 union { /*FEC Descriptor Individual Lower Addr (+0x111C)*/
7448 vuint32_t R;
7449 struct {
7450 vuint32_t IADDR2:32;
7451 } B;
7452 } IALR;
7453
7454 union { /* FEC Descriptor Group Upper Addr (Base+0x1120)*/
7455 vuint32_t R;
7456 struct {
7457 vuint32_t GADDR1:32;
7458 } B;
7459 } GAUR;
7460
7461 union { /* FEC Descriptor Group Lower Addr (Base+0x1124)*/
7462 vuint32_t R;
7463 struct {
7464 vuint32_t GADDR2:32;
7465 } B;
7466 } GALR;
7467
7468 vuint8_t FEC_reserved9[28]; /* Reserved 28 Bytes (Base+0x1128-0x1143) */
7469
7470 union { /* FEC FIFO Transmit FIFO Watermark (+0x1144) */
7471 vuint32_t R;
7472 struct {
7473 vuint32_t:30;
7474 vuint32_t X_WMRK:2;
7475 } B;
7476 } TFWR;
7477
7478 vuint8_t FEC_reserved10[4]; /* Reserved 4 Bytes (Base+0x1148-0x114B) */
7479
7480 union { /* FEC FIFO Receive Bound (Base+0x114C) */
7481 vuint32_t R;
7482 struct {
7483 vuint32_t:22;
7484 vuint32_t R_BOUND:8;
7485 vuint32_t:2;
7486 } B;
7487 } FRBR;
7488
7489 union { /* FEC FIFO Receive FIFO Start (Base+0x1150) */
7490 vuint32_t R;
7491 struct {
7492 vuint32_t:22;
7493 vuint32_t R_FSTART:8;
7494 vuint32_t:2;
7495 } B;
7496 } FRSR;
7497
7498 vuint8_t FEC_reserved11[44]; /* Reserved 44 Bytes (Base+0x1154-0x117F) */
7499
7500 union { /* FEC Receive Descriptor Ring Start (+0x1180) */
7501 vuint32_t R;
7502 struct {
7503 vuint32_t R_DES_START:30;
7504 vuint32_t:2;
7505 } B;
7506 } ERDSR;
7507
7508 union { /* FEC Transmit Descriptor Ring Start (+0x1184) */
7509 vuint32_t R;
7510 struct {
7511 vuint32_t X_DES_START:30;
7512 vuint32_t:2;
7513 } B;
7514 } ETDSR;
7515
7516 union { /* FEC Max Receive Buffer Size (Base+0x1188) */
7517 vuint32_t R;
7518 struct {
7519 vuint32_t:21;
7520 vuint32_t R_BUF_SIZE:7;
7521 vuint32_t:4;
7522 } B;
7523 } EMRBR;
7524
7525 vuint8_t FEC_reserved12[116]; /*Reserved 116 Bytes (Base+0x118C-0x11FF) */
7526
7527
7528 /* --- FEC MIB Counters Registers Below (Base+0x12000) --- */
7529
7530 union { /* MIB Count frames not counted correctly (Base+0x1200)*/
7531 vuint32_t R;
7532 } RMON_T_DROP;
7533
7534 union { /* MIB RMON Tx packet count (Base+0x1204) */
7535 vuint32_t R;
7536 } RMON_T_PACKETS;
7537
7538 union { /* MIB RMON Tx Broadcast Packets (Base+0x1208) */
7539 vuint32_t R;
7540 } RMON_T_BC_PKT;
7541
7542 union { /* MIB RMON Tx Multicast Packets (Base+0x120C) */
7543 vuint32_t R;
7544 } RMON_T_MC_PKT;
7545
7546 union { /* MIB RMON Tx Packets w CRC/Align err (+0x1210)*/
7547 vuint32_t R;
7548 } RMON_T_CRC_ALIGN;
7549
7550 union { /* MIB RMON Tx Packets < 64 bytes, good crc (+0x1214)*/
7551 vuint32_t R;
7552 } RMON_T_UNDERSIZE;
7553
7554 union { /* RMON Tx Packets > MAX_FL bytes, good crc (+0x1218) */
7555 vuint32_t R;
7556 } RMON_T_OVERSIZE;
7557
7558 union { /* MIB RMON Tx Packets < 64 bytes, bad crc (+0x121C) */
7559 vuint32_t R;
7560 } RMON_T_FRAG;
7561
7562 union { /* MIB RMON Tx Packets > MAX_FL bytes, bad crc (+0x1220) */
7563 vuint32_t R;
7564 } RMON_T_JAB;
7565
7566 union { /* MIB RMON Tx collision count (Base+0x1224)*/
7567 vuint32_t R;
7568 } RMON_T_COL;
7569
7570 union { /* MIB RMON Tx 64 byte packets (Base+0x1228) */
7571 vuint32_t R;
7572 } RMON_T_P64;
7573
7574 union { /* MIB RMON Tx 65 to 127 byte packets (+0x122C) */
7575 vuint32_t R;
7576 } RMON_T_P65TO127;
7577
7578 union { /* MIB RMON Tx 128 to 255 byte packets (+0x1230)*/
7579 vuint32_t R;
7580 } RMON_T_P128TO255;
7581
7582 union { /* MIB RMON Tx 256 to 511 byte packets (+0x1234)*/
7583 vuint32_t R;
7584 } RMON_T_P256TO511;
7585
7586 union { /* MIB RMON Tx 512 to 1023 byte packets (+0x1238)*/
7587 vuint32_t R;
7588 } RMON_T_P512TO1023;
7589
7590 union { /* MIB RMON Tx 1024 to 2047 byte packets (+0x123C)*/
7591 vuint32_t R;
7592 } RMON_T_P1024TO2047;
7593
7594 union { /* MIB RMON Tx packets w > 2048 bytes (+0x1240) */
7595 vuint32_t R;
7596 } RMON_T_P_GTE2048;
7597
7598 union { /* MIB RMON Tx Octets (Base+0x1244) */
7599 vuint32_t R;
7600 } RMON_T_OCTETS;
7601
7602 union { /* MIB Count of frames not counted correct (+0x1248)*/
7603 vuint32_t R;
7604 } IEEE_T_DROP;
7605
7606 union { /* MIB Frames Transmitted OK (Base+124C) */
7607 vuint32_t R;
7608 } IEEE_T_FRAME_OK;
7609
7610 union { /* MIB Frames Tx'd with Single Collision (+0x1250)*/
7611 vuint32_t R;
7612 } IEEE_T_1COL;
7613
7614 union { /* MIB Frames Tx'd with mult Collision (+0x1254)*/
7615 vuint32_t R;
7616 } IEEE_T_MCOL;
7617
7618 union { /* MIB Frames Tx'd after Deferral Delay (+0x1258)*/
7619 vuint32_t R;
7620 } IEEE_T_DEF;
7621
7622 union { /* MIB Frames Tx'd with Late Collision (+0x125C)*/
7623 vuint32_t R;
7624 } IEEE_T_LCOL;
7625
7626 union { /* MIB Frames Tx'd with Excessive Collisions (+0x1260)*/
7627 vuint32_t R;
7628 } IEEE_T_EXCOL;
7629
7630 union { /* MIB Frames Tx'd with Tx FIFO Underrun (+0x1264)*/
7631 vuint32_t R;
7632 } IEEE_T_MACERR;
7633
7634 union { /* MIB Frames Tx'd with Carrier Sense Error (+0x1268) */
7635 vuint32_t R;
7636 } IEEE_T_CSERR;
7637
7638 union { /* MIB Frames Tx'd with SQE Error (Base+0x126C) */
7639 vuint32_t R;
7640 } IEEE_T_SQE;
7641
7642 union { /* MIB Flow Control Pause frames tx'd (+0x1270) */
7643 vuint32_t R;
7644 } IEEE_T_FDXFC;
7645
7646 union { /* MIB Octet count for Frames Tx'd w/o Error (+0x1274)*/
7647 vuint32_t R;
7648 } IEEE_T_OCTETS_OK;
7649
7650 vuint8_t FEC_reserved13[8]; /*Reserved 12 Bytes (Base+0x1278-0x127F) */
7651
7652 union { /* MIB RMON # frames not counted correct (+0x1280) */
7653 vuint32_t R;
7654 } RMON_R_DROP;
7655
7656 union { /* MIB RMON Rx packet count (Base+0x1284) */
7657 vuint32_t R;
7658 } RMON_R_PACKETS;
7659
7660 union { /* MIB RMON Rx Broadcast Packets (Base+0x1288) */
7661 vuint32_t R;
7662 } RMON_R_BC_PKT;
7663
7664 union { /* MIB RMON Rx Multicast Packets (Base+0x128C) */
7665 vuint32_t R;
7666 } RMON_R_MC_PKT;
7667
7668 union { /* MIB RMON Rx Packets w CRC/Align error (+0x1290)*/
7669 vuint32_t R;
7670 } RMON_R_CRC_ALIGN;
7671
7672 union { /* MIB RMON Rx Packets < 64 bytes, good crc (+0x1294)*/
7673 vuint32_t R;
7674 } RMON_R_UNDERSIZE;
7675
7676 union { /* MIB RMON Rx Packets > MAX_FL bytes, good crc (+0x1298)*/
7677 vuint32_t R;
7678 } RMON_R_OVERSIZE;
7679
7680 union { /* MIB RMON Rx Packets < 64 bytes, bad crc (+0x129C)*/
7681 vuint32_t R;
7682 } RMON_R_FRAG;
7683
7684 union { /* MIB RMON Rx Packets > MAX_FL bytes, bad crc (0x12A0)*/
7685 vuint32_t R;
7686 } RMON_R_JAB;
7687
7688 vuint8_t FEC_reserved14[4]; /*Reserved 4 Bytes (Base+0x12A4-0x12A7) */
7689
7690 union { /* MIB RMON Rx 64 byte packets (Base+0x12A8) */
7691 vuint32_t R;
7692 } RMON_R_P64;
7693
7694 union { /* MIB RMON Rx 65 to 127 byte packets (+0x12AC) */
7695 vuint32_t R;
7696 } RMON_R_P65TO127;
7697
7698 union { /* MIB RMON Rx 128 to 255 byte packets (+0x12B0)*/
7699 vuint32_t R;
7700 } RMON_R_P128TO255;
7701
7702 union { /* MIB RMON Rx 256 to 511 byte packets (+0x12B4)*/
7703 vuint32_t R;
7704 } RMON_R_P256TO511;
7705
7706 union { /* MIB RMON Rx 512 to 1023 byte packets (+0x12B8)*/
7707 vuint32_t R;
7708 } RMON_R_P512TO1023;
7709
7710 union { /* MIB RMON Rx 1024 to 2047 byte packets (+0x12BC)*/
7711 vuint32_t R;
7712 } RMON_R_P1024TO2047;
7713
7714 union { /* MIB RMON Rx packets w > 2048 bytes (+0x12C0) */
7715 vuint32_t R;
7716 } RMON_R_P_GTE2048;
7717
7718 union { /* MIB RMON Rx Octets (Base+0x12C4) */
7719 vuint32_t R;
7720 } RMON_R_OCTETS;
7721
7722 union { /* MIB Count of frames not counted correctly (+0x12C8)*/
7723 vuint32_t R;
7724 } IEEE_R_DROP;
7725
7726 union { /* MIB Frames Received OK (Base+0x12CC) */
7727 vuint32_t R;
7728 } IEEE_R_FRAME_OK;
7729
7730 union { /* MIB Frames Received with CRC Error (+0x12D0) */
7731 vuint32_t R;
7732 } IEEE_R_CRC;
7733
7734 union { /* MIB Frames Received Alignment Error (+0x12D4)*/
7735 vuint32_t R;
7736 } IEEE_R_ALIGN;
7737
7738 union { /* MIB Receive Fifo Overflow count (+0x12D8) */
7739 vuint32_t R;
7740 } IEEE_R_MACERR;
7741
7742 union { /* MIB Flow Control Pause frames Rx'd (+0x12DC) */
7743 vuint32_t R;
7744 } IEEE_R_FDXFC;
7745
7746 union { /* MIB Octet count for Frames Rcvd w/o Error (+0x12E0)*/
7747 vuint32_t R;
7748 } IEEE_R_OCTETS_OK;
7749
7750
7751}; /* end of FEC_tag */
7752/****************************************************************************/
7753/* MODULE : DSPI */
7754/****************************************************************************/
7755struct DSPI_tag{
7756
7757 union { /* DSPI Module Configuraiton (Base+0x0000) */
7758 vuint32_t R;
7759 struct {
7760 vuint32_t MSTR:1;
7761 vuint32_t CONT_SCKE:1;
7762 vuint32_t DCONF:2;
7763 vuint32_t FRZ:1;
7764 vuint32_t MTFE:1;
7765 vuint32_t PCSSE:1;
7766 vuint32_t ROOE:1;
7767 vuint32_t :2; /* Chip selects 6,7 not bonded out on B3M */
7768 vuint32_t PCSIS5:1;
7769 vuint32_t PCSIS4:1;
7770 vuint32_t PCSIS3:1;
7771 vuint32_t PCSIS2:1;
7772 vuint32_t PCSIS1:1;
7773 vuint32_t PCSIS0:1;
7774 vuint32_t :1;
7775 vuint32_t MDIS:1;
7776 vuint32_t DIS_TXF:1;
7777 vuint32_t DIS_RXF:1;
7778 vuint32_t CLR_TXF:1;
7779 vuint32_t CLR_RXF:1;
7780 vuint32_t SMPL_PT:2;
7781 vuint32_t :6;
7782 vuint32_t PES:1;
7783 vuint32_t HALT:1;
7784 } B;
7785 } MCR;
7786
7787 vuint8_t DSPI_reserved00[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */
7788
7789 union { /* DSPI Transfer Count (Base+0x0008) */
7790 vuint32_t R;
7791 struct {
7792 vuint32_t TCNT:16;
7793 vuint32_t :16;
7794 } B;
7795 } TCR;
7796
7797 union { /* DSPI Clock & Tranfer Attrib 0-5 (+0x000C-0x0020) */
7798 vuint32_t R;
7799 struct {
7800 vuint32_t DBR:1;
7801 vuint32_t FMSZ:4;
7802 vuint32_t CPOL:1;
7803 vuint32_t CPHA:1;
7804 vuint32_t LSBFE:1;
7805 vuint32_t PCSSCK:2;
7806 vuint32_t PASC:2;
7807 vuint32_t PDT:2;
7808 vuint32_t PBR:2;
7809 vuint32_t CSSCK:4;
7810 vuint32_t ASC:4;
7811 vuint32_t DT:4;
7812 vuint32_t BR:4;
7813 } B;
7814 } CTAR[6];
7815
7816 vuint8_t DSPI_reserved0[8]; /* Reserved 8 bytes (Base+0x0024-0x002B) */
7817
7818 union { /* DSPI Status (Base+0x002C) */
7819 vuint32_t R;
7820 struct {
7821 vuint32_t TCF:1;
7822 vuint32_t TXRXS:1;
7823 vuint32_t :1;
7824 vuint32_t EOQF:1;
7825 vuint32_t TFUF:1;
7826 vuint32_t :1;
7827 vuint32_t TFFF:1;
7828 vuint32_t :2;
7829 vuint32_t DPEF:1; /* New on Bolero 3M */
7830 vuint32_t SPEF:1; /* New on Bolero 3M */
7831 vuint32_t DDIF:1; /* New on Bolero 3M */
7832 vuint32_t RFOF:1;
7833 vuint32_t :1;
7834 vuint32_t RFDF:1;
7835 vuint32_t :1;
7836 vuint32_t TXCTR:4;
7837 vuint32_t TXNXTPTR:4;
7838 vuint32_t RXCTR:4;
7839 vuint32_t POPNXTPTR:4;
7840 } B;
7841 } SR;
7842
7843 union { /* DSPI DMA/Int Request Select & Enable (+0x0030) */
7844 vuint32_t R;
7845 struct {
7846 vuint32_t TCFRE:1;
7847 vuint32_t :2;
7848 vuint32_t EOQFRE:1;
7849 vuint32_t TFUFRE:1;
7850 vuint32_t :1;
7851 vuint32_t TFFFRE:1;
7852 vuint32_t TFFFDIRS:1;
7853 vuint32_t :1;
7854 vuint32_t DPEFRE:1; /* New on Bolero 3M */
7855 vuint32_t SPEFRE:1; /* New on Bolero 3M */
7856 vuint32_t DDIFRE:1; /* New on Bolero 3M */
7857 vuint32_t RFOFRE:1;
7858 vuint32_t :1;
7859 vuint32_t RFDFRE:1;
7860 vuint32_t RFDFDIRS:1;
7861 vuint32_t :16;
7862 } B;
7863 } RSER;
7864
7865 union { /* DSPI Push TX FIFO (Base+0x0034) */
7866 vuint32_t R;
7867 struct {
7868 vuint32_t CONT:1;
7869 vuint32_t CTAS:3;
7870 vuint32_t EOQ:1;
7871 vuint32_t CTCNT:1;
7872 vuint32_t PE:1; /* New on Bolero 3M */
7873 vuint32_t PP:1; /* New on Bolero 3M */
7874 vuint32_t :2; /* PCS 7..6 not implemented on B3M */
7875 vuint32_t PCS5:1;
7876 vuint32_t PCS4:1;
7877 vuint32_t PCS3:1;
7878 vuint32_t PCS2:1;
7879 vuint32_t PCS1:1;
7880 vuint32_t PCS0:1;
7881 vuint32_t TXDATA:16;
7882 } B;
7883 } PUSHR;
7884
7885 union { /* DSPI Pop RX FIFO (Base+0x0038) */
7886 vuint32_t R;
7887 struct {
7888 vuint32_t RXDATA:32; /* Changed t0 32-bit data on B3M */
7889 } B;
7890 } POPR;
7891
7892 union { /* DSPI Transmit FIFO 0-3 (Base+0x003C-0x0048)*/
7893 vuint32_t R;
7894 struct { /* This is MASTER mode config for B3M */
7895 vuint32_t TXCMD:16; /* replace with TXDATA for B3M slave mode*/
7896 vuint32_t TXDATA:16;
7897 } B;
7898 } TXFR[4];
7899
7900 vuint8_t DSPI_reserved1[48]; /* Reserved 48 bytes (Base+0x004C-0x007B) */
7901
7902 union { /* DSPI Receive FIFO 0-3 (Base+0x007C-0x0088) */
7903 vuint32_t R;
7904 struct {
7905 vuint32_t RXDATA:32; /* Changed to 32-bit data on B3M */
7906 } B;
7907 } RXFR[4];
7908
7909 vuint8_t DSPI_reserved2[48]; /* Reserved 48 bytes (Base+0x008C-0x00BB) */
7910
7911 union { /* DSPI DSI Configuration (Base+0x00BC) */
7912 vuint32_t R;
7913 struct {
7914 vuint32_t MTOE:1;
7915 vuint32_t FMSZ4:1; /* New on Bolero 3M */
7916 vuint32_t MTOCNT:6;
7917 vuint32_t :3;
7918 vuint32_t TSBC:1; /* New on Bolero 3M */
7919 vuint32_t TXSS:1;
7920 vuint32_t TPOL:1;
7921 vuint32_t TRRE:1;
7922 vuint32_t CID:1;
7923 vuint32_t DCONT:1;
7924 vuint32_t DSICTAS:3;
7925 vuint32_t DMS:1; /* New on Bolero 3M */
7926 vuint32_t PES:1; /* New on Bolero 3M */
7927 vuint32_t PE:1; /* New on Bolero 3M */
7928 vuint32_t PP:1; /* New on Bolero 3M */
7929 vuint32_t :2; /* PCS 7..6 not implemented on B3M */
7930 vuint32_t DPCS5:1;
7931 vuint32_t DPCS4:1;
7932 vuint32_t DPCS3:1;
7933 vuint32_t DPCS2:1;
7934 vuint32_t DPCS1:1;
7935 vuint32_t DPCS0:1;
7936 } B;
7937 } DSICR;
7938
7939 union { /* DSPI DSI Serialization Data (Base+0x00C0) */
7940 vuint32_t R;
7941 struct {
7942 vuint32_t SER_DATA:32; /* Changed to 32-bit data on B3M */
7943 } B;
7944 } SDR;
7945
7946 union { /* DSPI ALT DSI Serialization Data (Base+0x00C4) */
7947 vuint32_t R;
7948 struct {
7949 vuint32_t ASER_DATA:32; /* Changed to 32-bit data on B3M */
7950 } B;
7951 } ASDR;
7952
7953 union { /* DSPI DSI Transmit Comparison (Base+0x00C8) */
7954 vuint32_t R;
7955 struct {
7956 vuint32_t COMP_DATA:32; /* Changed to 32-bit data on B3M */
7957 } B;
7958 } COMPR;
7959
7960 union { /* DSPI DSI Deserialization Data (Base+0x00CC) */
7961 vuint32_t R;
7962 struct {
7963 vuint32_t DESER_DATA:32; /* Changed to 32-bit data on B3M */
7964 } B;
7965 } DDR;
7966
7967 union { /* DSPI DSI Configuration 1 (Base+0x00D0) */
7968 vuint32_t R; /* NB this reg was missing from 1.5M header! */
7969 struct {
7970 vuint32_t :3;
7971 vuint32_t TSBCNT:5;
7972 vuint32_t :6;
7973 vuint32_t DSE1:1;
7974 vuint32_t DSE0:1;
7975 vuint32_t :8;
7976 vuint32_t :1; /* vuint32_t DPCS1_7:1; (Not implemented on B3m)*/
7977 vuint32_t :1; /* vuint32_t DPCS1_6:1; (Not implemented on B3m)*/
7978 vuint32_t DPCS1_5:1;
7979 vuint32_t DPCS1_4:1;
7980 vuint32_t DPCS1_3:1;
7981 vuint32_t DPCS1_2:1;
7982 vuint32_t DPCS1_1:1;
7983 vuint32_t DPCS1_0:1;
7984 } B;
7985 } DSICR1;
7986
7987 union { /* DSPI DSI Serialisation Source (Base+0x00D4) */
7988 vuint32_t R;
7989 struct {
7990 vuint32_t SS:32; /* All bits avail for B3M */
7991 } B;
7992 } SSR;
7993
7994 vuint8_t DSPI_reserved4[16]; /* Reserved 16 bytes (Base+0x00D8-0x00E7) */
7995
7996 union { /* DSPI DSI Deserialised Data Interrupt Mask (+0x00E8) */
7997 vuint32_t R;
7998 struct {
7999 vuint32_t MASK:32; /* 32-bit for B3M */
8000 } B;
8001 } DIMR;
8002
8003 union { /* DSPI DSI Deserialised Data Poloarity Int (+0x00E8) */
8004 vuint32_t R;
8005 struct {
8006 vuint32_t DP:32; /* 32-bit for B3M */
8007 } B;
8008 } DPIR;
8009
8010}; /* end of DSPI_tag */
8011/****************************************************************************/
8012/* MODULE : FlexCAN */
8013/****************************************************************************/
8014struct FLEXCAN_BUF_t{
8015
8016 union { /* FLEXCAN MBx Control & Status (Offset+0x0080) */
8017 vuint32_t R;
8018 struct {
8019 vuint32_t :4;
8020 vuint32_t CODE:4;
8021 vuint32_t :1;
8022 vuint32_t SRR:1;
8023 vuint32_t IDE:1;
8024 vuint32_t RTR:1;
8025 vuint32_t LENGTH:4;
8026 vuint32_t TIMESTAMP:16;
8027 } B;
8028 } CS;
8029
8030 union { /* FLEXCAN MBx Identifier (Offset+0x0084) */
8031 vuint32_t R;
8032 struct {
8033 vuint32_t PRIO:3;
8034 vuint32_t STD_ID:11;
8035 vuint32_t EXT_ID:18;
8036 } B;
8037 } ID;
8038
8039 union { /* FLEXCAN MBx Data 0..7 (Offset+0x0088) */
8040 vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
8041 vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
8042 vuint32_t W[2]; /* Data buffer in words (32 bits) */
8043 vuint32_t R[2]; /* Data buffer in words (32 bits) */
8044 } DATA;
8045
8046}; /* end of FLEXCAN_BUF_t */
8047
8048
8049struct FLEXCAN_RXFIFO_t{ /* RxFIFO Configuration */
8050
8051 union { /* RxFIFO Control & Status (Offset+0x0080) */
8052 vuint32_t R;
8053 struct {
8054 vuint32_t :9;
8055 vuint32_t SRR:1;
8056 vuint32_t IDE:1;
8057 vuint32_t RTR:1;
8058 vuint32_t LENGTH:4;
8059 vuint32_t TIMESTAMP:16;
8060 } B;
8061 } CS;
8062
8063 union { /* RxFIFO Identifier (Offset+0x0084) */
8064 vuint32_t R;
8065 struct {
8066 vuint32_t :3;
8067 vuint32_t STD_ID:11;
8068 vuint32_t EXT_ID:18;
8069 } B;
8070 } ID;
8071
8072 union { /* RxFIFO Data 0..7 (Offset+0x0088) */
8073 vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
8074 vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
8075 vuint32_t W[2]; /* Data buffer in words (32 bits) */
8076 vuint32_t R[2]; /* Data buffer in words (32 bits) */
8077 } DATA;
8078
8079 vuint8_t FLEXCAN_RX_reserved0[80]; /* Reserved 80 bytes (+0x0090-0x00DF)*/
8080
8081 union { /* RxFIFO ID Table 0..7 (+0x00E0-0x00FC) */
8082 vuint32_t R;
8083 } IDTABLE[8];
8084
8085}; /* end of FLEXCAN_RXFIFO_t */
8086
8087
8088struct FLEXCAN_tag{
8089
8090 union { /* FLEXCAN Module Configuration (Base+0x0000) */
8091 vuint32_t R;
8092 struct {
8093 vuint32_t MDIS:1;
8094 vuint32_t FRZ:1;
8095 vuint32_t FEN:1;
8096 vuint32_t HALT:1;
8097 vuint32_t NOTRDY:1;
8098 vuint32_t WAKMSK:1;
8099 vuint32_t SOFTRST:1;
8100 vuint32_t FRZACK:1;
8101 vuint32_t SUPV:1;
8102 vuint32_t SLFWAK:1;
8103 vuint32_t WRNEN:1;
8104 vuint32_t LPMACK:1;
8105 vuint32_t WAKSRC:1;
8106 vuint32_t DOZE:1;
8107 vuint32_t SRXDIS:1;
8108 vuint32_t BCC:1;
8109 vuint32_t :2;
8110 vuint32_t LPRIO_EN:1;
8111 vuint32_t AEN:1;
8112 vuint32_t :2;
8113 vuint32_t IDAM:2;
8114 vuint32_t :2;
8115 vuint32_t MAXMB:6;
8116 } B;
8117 } MCR;
8118
8119 union { /* FLEXCAN Control (Base+0x0004) */
8120 vuint32_t R;
8121 struct {
8122 vuint32_t PRESDIV:8;
8123 vuint32_t RJW:2;
8124 vuint32_t PSEG1:3;
8125 vuint32_t PSEG2:3;
8126 vuint32_t BOFFMSK:1;
8127 vuint32_t ERRMSK:1;
8128 vuint32_t CLKSRC:1;
8129 vuint32_t LPB:1;
8130 vuint32_t TWRNMSK:1;
8131 vuint32_t RWRNMSK:1;
8132 vuint32_t :2;
8133 vuint32_t SMP:1;
8134 vuint32_t BOFFREC:1;
8135 vuint32_t TSYN:1;
8136 vuint32_t LBUF:1;
8137 vuint32_t LOM:1;
8138 vuint32_t PROPSEG:3;
8139 } B;
8140 } CR;
8141
8142 union { /* FLEXCAN Free Running Timer (Base+0x0008) */
8143 vuint32_t R;
8144 struct {
8145 vuint32_t :16;
8146 vuint32_t TIMER:16;
8147 } B;
8148 } TIMER;
8149
8150 vuint8_t FLEXCAN_reserved0[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */
8151
8152 union { /* FLEXCAN RX Global Mask (Base+0x0010) */
8153 vuint32_t R;
8154 struct {
8155 vuint32_t MI:32;
8156 } B;
8157 } RXGMASK;
8158
8159 /* --- Following 2 registers are included for legacy purposes only --- */
8160
8161 union { /* FLEXCAN RX 14 Mask (Base+0x0014) */
8162 vuint32_t R;
8163 struct {
8164 vuint32_t MI:32;
8165 } B;
8166 } RX14MASK;
8167
8168 union { /* FLEXCAN RX 15 Mask (Base+0x0018) */
8169 vuint32_t R;
8170 struct {
8171 vuint32_t MI:32;
8172 } B;
8173 } RX15MASK;
8174
8175 /* --- */
8176
8177 union { /* FLEXCAN Error Counter (Base+0x001C) */
8178 vuint32_t R;
8179 struct {
8180 vuint32_t :16;
8181 vuint32_t RXECNT:8;
8182 vuint32_t TXECNT:8;
8183 } B;
8184 } ECR;
8185
8186 union { /* FLEXCAN Error & Status (Base+0x0020) */
8187 vuint32_t R;
8188 struct {
8189 vuint32_t :14;
8190 vuint32_t TWRNINT:1;
8191 vuint32_t RWRNINT:1;
8192 vuint32_t BIT1ERR:1;
8193 vuint32_t BIT0ERR:1;
8194 vuint32_t ACKERR:1;
8195 vuint32_t CRCERR:1;
8196 vuint32_t FRMERR:1;
8197 vuint32_t STFERR:1;
8198 vuint32_t TXWRN:1;
8199 vuint32_t RXWRN:1;
8200 vuint32_t IDLE:1;
8201 vuint32_t TXRX:1;
8202 vuint32_t FLTCONF:2;
8203 vuint32_t :1;
8204 vuint32_t BOFFINT:1;
8205 vuint32_t ERRINT:1;
8206 vuint32_t WAKINT:1;
8207 } B;
8208 } ESR;
8209
8210 union { /* FLEXCAN Interruput Masks H (Base+0x0024) */
8211 vuint32_t R;
8212 struct {
8213 vuint32_t BUF63M:1;
8214 vuint32_t BUF62M:1;
8215 vuint32_t BUF61M:1;
8216 vuint32_t BUF60M:1;
8217 vuint32_t BUF59M:1;
8218 vuint32_t BUF58M:1;
8219 vuint32_t BUF57M:1;
8220 vuint32_t BUF56M:1;
8221 vuint32_t BUF55M:1;
8222 vuint32_t BUF54M:1;
8223 vuint32_t BUF53M:1;
8224 vuint32_t BUF52M:1;
8225 vuint32_t BUF51M:1;
8226 vuint32_t BUF50M:1;
8227 vuint32_t BUF49M:1;
8228 vuint32_t BUF48M:1;
8229 vuint32_t BUF47M:1;
8230 vuint32_t BUF46M:1;
8231 vuint32_t BUF45M:1;
8232 vuint32_t BUF44M:1;
8233 vuint32_t BUF43M:1;
8234 vuint32_t BUF42M:1;
8235 vuint32_t BUF41M:1;
8236 vuint32_t BUF40M:1;
8237 vuint32_t BUF39M:1;
8238 vuint32_t BUF38M:1;
8239 vuint32_t BUF37M:1;
8240 vuint32_t BUF36M:1;
8241 vuint32_t BUF35M:1;
8242 vuint32_t BUF34M:1;
8243 vuint32_t BUF33M:1;
8244 vuint32_t BUF32M:1;
8245 } B;
8246 } IMRH;
8247
8248 union { /* FLEXCAN Interruput Masks L (Base+0x0028) */
8249 vuint32_t R;
8250 struct {
8251 vuint32_t BUF31M:1;
8252 vuint32_t BUF30M:1;
8253 vuint32_t BUF29M:1;
8254 vuint32_t BUF28M:1;
8255 vuint32_t BUF27M:1;
8256 vuint32_t BUF26M:1;
8257 vuint32_t BUF25M:1;
8258 vuint32_t BUF24M:1;
8259 vuint32_t BUF23M:1;
8260 vuint32_t BUF22M:1;
8261 vuint32_t BUF21M:1;
8262 vuint32_t BUF20M:1;
8263 vuint32_t BUF19M:1;
8264 vuint32_t BUF18M:1;
8265 vuint32_t BUF17M:1;
8266 vuint32_t BUF16M:1;
8267 vuint32_t BUF15M:1;
8268 vuint32_t BUF14M:1;
8269 vuint32_t BUF13M:1;
8270 vuint32_t BUF12M:1;
8271 vuint32_t BUF11M:1;
8272 vuint32_t BUF10M:1;
8273 vuint32_t BUF09M:1;
8274 vuint32_t BUF08M:1;
8275 vuint32_t BUF07M:1;
8276 vuint32_t BUF06M:1;
8277 vuint32_t BUF05M:1;
8278 vuint32_t BUF04M:1;
8279 vuint32_t BUF03M:1;
8280 vuint32_t BUF02M:1;
8281 vuint32_t BUF01M:1;
8282 vuint32_t BUF00M:1;
8283 } B;
8284 } IMRL;
8285
8286 union { /* FLEXCAN Interruput Flag H (Base+0x002C) */
8287 vuint32_t R;
8288 struct {
8289 vuint32_t BUF63I:1;
8290 vuint32_t BUF62I:1;
8291 vuint32_t BUF61I:1;
8292 vuint32_t BUF60I:1;
8293 vuint32_t BUF59I:1;
8294 vuint32_t BUF58I:1;
8295 vuint32_t BUF57I:1;
8296 vuint32_t BUF56I:1;
8297 vuint32_t BUF55I:1;
8298 vuint32_t BUF54I:1;
8299 vuint32_t BUF53I:1;
8300 vuint32_t BUF52I:1;
8301 vuint32_t BUF51I:1;
8302 vuint32_t BUF50I:1;
8303 vuint32_t BUF49I:1;
8304 vuint32_t BUF48I:1;
8305 vuint32_t BUF47I:1;
8306 vuint32_t BUF46I:1;
8307 vuint32_t BUF45I:1;
8308 vuint32_t BUF44I:1;
8309 vuint32_t BUF43I:1;
8310 vuint32_t BUF42I:1;
8311 vuint32_t BUF41I:1;
8312 vuint32_t BUF40I:1;
8313 vuint32_t BUF39I:1;
8314 vuint32_t BUF38I:1;
8315 vuint32_t BUF37I:1;
8316 vuint32_t BUF36I:1;
8317 vuint32_t BUF35I:1;
8318 vuint32_t BUF34I:1;
8319 vuint32_t BUF33I:1;
8320 vuint32_t BUF32I:1;
8321 } B;
8322 } IFRH;
8323
8324 union { /* FLEXCAN Interruput Flag l (Base+0x0030) */
8325 vuint32_t R;
8326 struct {
8327 vuint32_t BUF31I:1;
8328 vuint32_t BUF30I:1;
8329 vuint32_t BUF29I:1;
8330 vuint32_t BUF28I:1;
8331 vuint32_t BUF27I:1;
8332 vuint32_t BUF26I:1;
8333 vuint32_t BUF25I:1;
8334 vuint32_t BUF24I:1;
8335 vuint32_t BUF23I:1;
8336 vuint32_t BUF22I:1;
8337 vuint32_t BUF21I:1;
8338 vuint32_t BUF20I:1;
8339 vuint32_t BUF19I:1;
8340 vuint32_t BUF18I:1;
8341 vuint32_t BUF17I:1;
8342 vuint32_t BUF16I:1;
8343 vuint32_t BUF15I:1;
8344 vuint32_t BUF14I:1;
8345 vuint32_t BUF13I:1;
8346 vuint32_t BUF12I:1;
8347 vuint32_t BUF11I:1;
8348 vuint32_t BUF10I:1;
8349 vuint32_t BUF09I:1;
8350 vuint32_t BUF08I:1;
8351 vuint32_t BUF07I:1;
8352 vuint32_t BUF06I:1;
8353 vuint32_t BUF05I:1;
8354 vuint32_t BUF04I:1;
8355 vuint32_t BUF03I:1;
8356 vuint32_t BUF02I:1;
8357 vuint32_t BUF01I:1;
8358 vuint32_t BUF00I:1;
8359 } B;
8360 } IFRL; /* Interruput Flag Register */
8361
8362 vuint8_t FLEXCAN_reserved1[76]; /*Reserved 76 bytes (Base+0x0034-0x007F)*/
8363
8364/****************************************************************************/
8365/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */
8366/****************************************************************************/
8367 /* Standard Buffer Structure */
8368 struct FLEXCAN_BUF_t BUF[64];
8369
8370 /* RX FIFO and Buffer Structure */
8371 /*struct FLEXCAN_RXFIFO_t RXFIFO; */
8372 /*struct FLEXCAN_BUF_t BUF[56]; */
8373/****************************************************************************/
8374
8375 vuint8_t FLEXCAN_reserved2[1024]; /*Reserved 1024 (Base+0x0480-0x087F)*/
8376
8377 union { /* FLEXCAN RX Individual Mask (Base+0x0880-0x097F) */
8378 vuint32_t R;
8379 struct {
8380 vuint32_t MI:32;
8381 } B;
8382 } RXIMR[64];
8383
8384}; /* end of FLEXCAN_tag */
8385/****************************************************************************/
8386/* MODULE : DMAMUX */
8387/****************************************************************************/
8388struct DMAMUX_tag {
8389
8390 union { /* DMAMUX Channel Configuration (Base+0x0000-0x000F) */
8391 vuint8_t R;
8392 struct {
8393 vuint8_t ENBL:1;
8394 vuint8_t TRIG:1;
8395 vuint8_t SOURCE:6;
8396 } B;
8397 } CHCONFIG[32];
8398
8399}; /* end of DMAMUX_tag */
8400/******************************************************************
8401| defines and macros (scope: module-local)
8402|-----------------------------------------------------------------*/
8403/* Define instances of modules (in address order) */
8404
8405#define CFLASH_0 (*(volatile struct CFLASH_tag *) 0xC3F88000UL)
8406#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)
8407#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)
8408#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)
8409#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)
8410#define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL)
8411#define CFLASH_1 (*(volatile struct CFLASH_tag *) 0xC3FB0000UL)
8412#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)
8413#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)
8414#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)
8415#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)
8416#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)
8417#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)
8418#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)
8419#define STCU (*(volatile struct STCU_tag *) 0xC3FF4000UL)
8420#define ADC_0 (*(volatile struct ADC0_tag *) 0xFFE00000UL)
8421#define ADC_1 (*(volatile struct ADC1_tag *) 0xFFE04000UL)
8422#define I2C (*(volatile struct I2C_tag *) 0xFFE30000UL)
8423#define LINFLEX_0 (*(volatile struct LINFLEX_MS_tag *) 0xFFE40000UL)
8424#define LINFLEX_1 (*(volatile struct LINFLEX_M_tag *) 0xFFE44000UL)
8425#define LINFLEX_2 (*(volatile struct LINFLEX_M_tag *) 0xFFE48000UL)
8426#define LINFLEX_3 (*(volatile struct LINFLEX_M_tag *) 0xFFE4C000UL)
8427#define LINFLEX_4 (*(volatile struct LINFLEX_M_tag *) 0xFFE50000UL)
8428#define LINFLEX_5 (*(volatile struct LINFLEX_M_tag *) 0xFFE54000UL)
8429#define LINFLEX_6 (*(volatile struct LINFLEX_M_tag *) 0xFFE58000UL)
8430#define LINFLEX_7 (*(volatile struct LINFLEX_M_tag *) 0xFFE5C000UL)
8431#define CTU (*(volatile struct CTU_tag *) 0xFFE64000UL)
8432#define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL)
8433#define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000UL)
8434#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)
8435#define CSE (*(volatile struct CSE_tag *) 0xFFF1C000UL)
8436#define SEMA4 (*(volatile struct SEMA4_tag *) 0xFFF24000UL)
8437#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)
8438#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)
8439#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)
8440#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL)
8441#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
8442#define FEC (*(volatile struct FEC_tag *) 0xFFF4C000UL)
8443#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)
8444#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)
8445#define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL)
8446#define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL)
8447#define DSPI_4 (*(volatile struct DSPI_tag *) 0xFFFA0000UL)
8448#define DSPI_5 (*(volatile struct DSPI_tag *) 0xFFFA4000UL)
8449#define DSPI_6 (*(volatile struct DSPI_tag *) 0xFFFA8000UL)
8450#define DSPI_7 (*(volatile struct DSPI_tag *) 0xFFFAC000UL)
8451#define LINFLEX_8 (*(volatile struct LINFLEX_M_tag *) 0xFFFB0000UL)
8452#define LINFLEX_9 (*(volatile struct LINFLEX_M_tag *) 0xFFFB4000UL)
8453#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
8454#define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)
8455#define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)
8456#define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)
8457#define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)
8458#define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)
8459#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)
8460
8461// Flexray is NOT added to this header. Expected use is that Flexray is used with drivers.
8462
8463
8464
8465#ifdef __MWERKS__
8466#pragma pop
8467#endif
8468
8469#ifdef __cplusplus
8470}
8471#endif
8472
8473#endif
8474
8475/* End of file */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 16:11:42 +0100