1 files changed, 566 insertions, 0 deletions
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h b/lib/chibios/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h
new file mode 100644
index 000000000..d15e600d2
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h
@@ -0,0 +1,566 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/**
+ * @file    TIMv1/stm32_tim.h
+ * @brief   STM32 TIM units common header.
+ * @note    This file requires definitions from the ST STM32 header file.
+ *
+ * @addtogroup STM32_TIMv1
+ * @{
+ */
+#ifndef STM32_TIM_H
+#define STM32_TIM_H
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+/**
+ * @name    TIM_CR1 register
+ * @{
+ */
+#define STM32_TIM_CR1_CEN                   (1U << 0)
+#define STM32_TIM_CR1_UDIS                  (1U << 1)
+#define STM32_TIM_CR1_URS                   (1U << 2)
+#define STM32_TIM_CR1_OPM                   (1U << 3)
+#define STM32_TIM_CR1_DIR                   (1U << 4)
+#define STM32_TIM_CR1_CMS_MASK              (3U << 5)
+#define STM32_TIM_CR1_CMS(n)                ((n) << 5)
+#define STM32_TIM_CR1_ARPE                  (1U << 7)
+#define STM32_TIM_CR1_CKD_MASK              (3U << 8)
+#define STM32_TIM_CR1_CKD(n)                ((n) << 8)
+#define STM32_TIM_CR1_UIFREMAP              (1U << 11)
+/** @} */
+/**
+ * @name    TIM_CR2 register
+ * @{
+ */
+#define STM32_TIM_CR2_CCPC                  (1U << 0)
+#define STM32_TIM_CR2_CCUS                  (1U << 2)
+#define STM32_TIM_CR2_CCDS                  (1U << 3)
+#define STM32_TIM_CR2_MMS_MASK              (7U << 4)
+#define STM32_TIM_CR2_MMS(n)                ((n) << 4)
+#define STM32_TIM_CR2_TI1S                  (1U << 7)
+#define STM32_TIM_CR2_OIS1                  (1U << 8)
+#define STM32_TIM_CR2_OIS1N                 (1U << 9)
+#define STM32_TIM_CR2_OIS2                  (1U << 10)
+#define STM32_TIM_CR2_OIS2N                 (1U << 11)
+#define STM32_TIM_CR2_OIS3                  (1U << 12)
+#define STM32_TIM_CR2_OIS3N                 (1U << 13)
+#define STM32_TIM_CR2_OIS4                  (1U << 14)
+#define STM32_TIM_CR2_OIS5                  (1U << 16)
+#define STM32_TIM_CR2_OIS6                  (1U << 18)
+#define STM32_TIM_CR2_MMS2_MASK             (15U << 20)
+#define STM32_TIM_CR2_MMS2(n)               ((n) << 20)
+/** @} */
+/**
+ * @name    TIM_SMCR register
+ * @{
+ */
+#define STM32_TIM_SMCR_SMS_MASK             ((7U << 0) | (1U << 16))
+#define STM32_TIM_SMCR_SMS(n)               ((((n) & 7) << 0) |             \
+                                             (((n) >> 3) << 16))
+#define STM32_TIM_SMCR_OCCS                 (1U << 3)
+#define STM32_TIM_SMCR_TS_MASK              (7U << 4)
+#define STM32_TIM_SMCR_TS(n)                ((n) << 4)
+#define STM32_TIM_SMCR_MSM                  (1U << 7)
+#define STM32_TIM_SMCR_ETF_MASK             (15U << 8)
+#define STM32_TIM_SMCR_ETF(n)               ((n) << 8)
+#define STM32_TIM_SMCR_ETPS_MASK            (3U << 12)
+#define STM32_TIM_SMCR_ETPS(n)              ((n) << 12)
+#define STM32_TIM_SMCR_ECE                  (1U << 14)
+#define STM32_TIM_SMCR_ETP                  (1U << 15)
+/** @} */
+/**
+ * @name    TIM_DIER register
+ * @{
+ */
+#define STM32_TIM_DIER_UIE                  (1U << 0)
+#define STM32_TIM_DIER_CC1IE                (1U << 1)
+#define STM32_TIM_DIER_CC2IE                (1U << 2)
+#define STM32_TIM_DIER_CC3IE                (1U << 3)
+#define STM32_TIM_DIER_CC4IE                (1U << 4)
+#define STM32_TIM_DIER_COMIE                (1U << 5)
+#define STM32_TIM_DIER_TIE                  (1U << 6)
+#define STM32_TIM_DIER_BIE                  (1U << 7)
+#define STM32_TIM_DIER_UDE                  (1U << 8)
+#define STM32_TIM_DIER_CC1DE                (1U << 9)
+#define STM32_TIM_DIER_CC2DE                (1U << 10)
+#define STM32_TIM_DIER_CC3DE                (1U << 11)
+#define STM32_TIM_DIER_CC4DE                (1U << 12)
+#define STM32_TIM_DIER_COMDE                (1U << 13)
+#define STM32_TIM_DIER_TDE                  (1U << 14)
+#define STM32_TIM_DIER_IRQ_MASK             (STM32_TIM_DIER_UIE   |         \
+                                             STM32_TIM_DIER_CC1IE |         \
+                                             STM32_TIM_DIER_CC2IE |         \
+                                             STM32_TIM_DIER_CC3IE |         \
+                                             STM32_TIM_DIER_CC4IE |         \
+                                             STM32_TIM_DIER_COMIE |         \
+                                             STM32_TIM_DIER_TIE   |         \
+                                             STM32_TIM_DIER_BIE)
+/** @} */
+/**
+ * @name    TIM_SR register
+ * @{
+ */
+#define STM32_TIM_SR_UIF                    (1U << 0)
+#define STM32_TIM_SR_CC1IF                  (1U << 1)
+#define STM32_TIM_SR_CC2IF                  (1U << 2)
+#define STM32_TIM_SR_CC3IF                  (1U << 3)
+#define STM32_TIM_SR_CC4IF                  (1U << 4)
+#define STM32_TIM_SR_COMIF                  (1U << 5)
+#define STM32_TIM_SR_TIF                    (1U << 6)
+#define STM32_TIM_SR_BIF                    (1U << 7)
+#define STM32_TIM_SR_B2IF                   (1U << 8)
+#define STM32_TIM_SR_CC1OF                  (1U << 9)
+#define STM32_TIM_SR_CC2OF                  (1U << 10)
+#define STM32_TIM_SR_CC3OF                  (1U << 11)
+#define STM32_TIM_SR_CC4OF                  (1U << 12)
+#define STM32_TIM_SR_CC5IF                  (1U << 16)
+#define STM32_TIM_SR_CC6IF                  (1U << 17)
+/** @} */
+/**
+ * @name    TIM_EGR register
+ * @{
+ */
+#define STM32_TIM_EGR_UG                    (1U << 0)
+#define STM32_TIM_EGR_CC1G                  (1U << 1)
+#define STM32_TIM_EGR_CC2G                  (1U << 2)
+#define STM32_TIM_EGR_CC3G                  (1U << 3)
+#define STM32_TIM_EGR_CC4G                  (1U << 4)
+#define STM32_TIM_EGR_COMG                  (1U << 5)
+#define STM32_TIM_EGR_TG                    (1U << 6)
+#define STM32_TIM_EGR_BG                    (1U << 7)
+#define STM32_TIM_EGR_B2G                   (1U << 8)
+/** @} */
+/**
+ * @name    TIM_CCMR1 register (output)
+ * @{
+ */
+#define STM32_TIM_CCMR1_CC1S_MASK           (3U << 0)
+#define STM32_TIM_CCMR1_CC1S(n)             ((n) << 0)
+#define STM32_TIM_CCMR1_OC1FE               (1U << 2)
+#define STM32_TIM_CCMR1_OC1PE               (1U << 3)
+#define STM32_TIM_CCMR1_OC1M_MASK           ((7U << 4) | (1U << 16))
+#define STM32_TIM_CCMR1_OC1M(n)             ((((n) & 7) << 4) |             \
+                                             (((n) >> 3) << 16))
+#define STM32_TIM_CCMR1_OC1CE               (1U << 7)
+#define STM32_TIM_CCMR1_CC2S_MASK           (3U << 8)
+#define STM32_TIM_CCMR1_CC2S(n)             ((n) << 8)
+#define STM32_TIM_CCMR1_OC2FE               (1U << 10)
+#define STM32_TIM_CCMR1_OC2PE               (1U << 11)
+#define STM32_TIM_CCMR1_OC2M_MASK           ((7U << 12) | (1U << 24))
+#define STM32_TIM_CCMR1_OC2M(n)             ((((n) & 7) << 12) |            \
+                                             (((n) >> 3) << 24))
+#define STM32_TIM_CCMR1_OC2CE               (1U << 15)
+/** @} */
+/**
+ * @name    CCMR1 register (input)
+ * @{
+ */
+#define STM32_TIM_CCMR1_IC1PSC_MASK         (3U << 2)
+#define STM32_TIM_CCMR1_IC1PSC(n)           ((n) << 2)
+#define STM32_TIM_CCMR1_IC1F_MASK           (15U << 4)
+#define STM32_TIM_CCMR1_IC1F(n)             ((n) << 4)
+#define STM32_TIM_CCMR1_IC2PSC_MASK         (3U << 10)
+#define STM32_TIM_CCMR1_IC2PSC(n)           ((n) << 10)
+#define STM32_TIM_CCMR1_IC2F_MASK           (15U << 12)
+#define STM32_TIM_CCMR1_IC2F(n)             ((n) << 12)
+/** @} */
+/**
+ * @name    TIM_CCMR2 register (output)
+ * @{
+ */
+#define STM32_TIM_CCMR2_CC3S_MASK           (3U << 0)
+#define STM32_TIM_CCMR2_CC3S(n)             ((n) << 0)
+#define STM32_TIM_CCMR2_OC3FE               (1U << 2)
+#define STM32_TIM_CCMR2_OC3PE               (1U << 3)
+#define STM32_TIM_CCMR2_OC3M_MASK           ((7U << 4) | (1U << 16))
+#define STM32_TIM_CCMR2_OC3M(n)             ((((n) & 7) << 4) |             \
+                                             (((n) >> 3) << 16))
+#define STM32_TIM_CCMR2_OC3CE               (1U << 7)
+#define STM32_TIM_CCMR2_CC4S_MASK           (3U << 8)
+#define STM32_TIM_CCMR2_CC4S(n)             ((n) << 8)
+#define STM32_TIM_CCMR2_OC4FE               (1U << 10)
+#define STM32_TIM_CCMR2_OC4PE               (1U << 11)
+#define STM32_TIM_CCMR2_OC4M_MASK           ((7U << 12) | (1U << 24))
+#define STM32_TIM_CCMR2_OC4M(n)             ((((n) & 7) << 12) |            \
+                                             (((n) >> 3) << 24))
+#define STM32_TIM_CCMR2_OC4CE               (1U << 15)
+/** @} */
+/**
+ * @name    TIM_CCMR2 register (input)
+ * @{
+ */
+#define STM32_TIM_CCMR2_IC3PSC_MASK         (3U << 2)
+#define STM32_TIM_CCMR2_IC3PSC(n)           ((n) << 2)
+#define STM32_TIM_CCMR2_IC3F_MASK           (15U << 4)
+#define STM32_TIM_CCMR2_IC3F(n)             ((n) << 4)
+#define STM32_TIM_CCMR2_IC4PSC_MASK         (3U << 10)
+#define STM32_TIM_CCMR2_IC4PSC(n)           ((n) << 10)
+#define STM32_TIM_CCMR2_IC4F_MASK           (15U << 12)
+#define STM32_TIM_CCMR2_IC4F(n)             ((n) << 12)
+/** @} */
+/**
+ * @name    TIM_CCER register
+ * @{
+ */
+#define STM32_TIM_CCER_CC1E                 (1U << 0)
+#define STM32_TIM_CCER_CC1P                 (1U << 1)
+#define STM32_TIM_CCER_CC1NE                (1U << 2)
+#define STM32_TIM_CCER_CC1NP                (1U << 3)
+#define STM32_TIM_CCER_CC2E                 (1U << 4)
+#define STM32_TIM_CCER_CC2P                 (1U << 5)
+#define STM32_TIM_CCER_CC2NE                (1U << 6)
+#define STM32_TIM_CCER_CC2NP                (1U << 7)
+#define STM32_TIM_CCER_CC3E                 (1U << 8)
+#define STM32_TIM_CCER_CC3P                 (1U << 9)
+#define STM32_TIM_CCER_CC3NE                (1U << 10)
+#define STM32_TIM_CCER_CC3NP                (1U << 11)
+#define STM32_TIM_CCER_CC4E                 (1U << 12)
+#define STM32_TIM_CCER_CC4P                 (1U << 13)
+#define STM32_TIM_CCER_CC4NE                (1U << 14)
+#define STM32_TIM_CCER_CC4NP                (1U << 15)
+#define STM32_TIM_CCER_CC5E                 (1U << 16)
+#define STM32_TIM_CCER_CC5P                 (1U << 17)
+#define STM32_TIM_CCER_CC6E                 (1U << 20)
+#define STM32_TIM_CCER_CC6P                 (1U << 21)
+/** @} */
+/**
+ * @name    TIM_CNT register
+ * @{
+ */
+#define STM32_TIM_CNT_UIFCPY                (1U << 31)
+/** @} */
+/**
+ * @name    TIM_BDTR register
+ * @{
+ */
+#define STM32_TIM_BDTR_DTG_MASK             (255U << 0)
+#define STM32_TIM_BDTR_DTG(n)               ((n) << 0)
+#define STM32_TIM_BDTR_LOCK_MASK            (3U << 8)
+#define STM32_TIM_BDTR_LOCK(n)              ((n) << 8)
+#define STM32_TIM_BDTR_OSSI                 (1U << 10)
+#define STM32_TIM_BDTR_OSSR                 (1U << 11)
+#define STM32_TIM_BDTR_BKE                  (1U << 12)
+#define STM32_TIM_BDTR_BKP                  (1U << 13)
+#define STM32_TIM_BDTR_AOE                  (1U << 14)
+#define STM32_TIM_BDTR_MOE                  (1U << 15)
+#define STM32_TIM_BDTR_BKF_MASK             (15U << 16)
+#define STM32_TIM_BDTR_BKF(n)               ((n) << 16)
+#define STM32_TIM_BDTR_BK2F_MASK            (15U << 20)
+#define STM32_TIM_BDTR_BK2F(n)              ((n) << 20)
+#define STM32_TIM_BDTR_BK2E                 (1U << 24)
+#define STM32_TIM_BDTR_BK2P                 (1U << 25)
+/** @} */
+/**
+ * @name    TIM_DCR register
+ * @{
+ */
+#define STM32_TIM_DCR_DBA_MASK              (31U << 0)
+#define STM32_TIM_DCR_DBA(n)                ((n) << 0)
+#define STM32_TIM_DCR_DBL_MASK              (31U << 8)
+#define STM32_TIM_DCR_DBL(n)                ((n) << 8)
+/** @} */
+/**
+ * @name    TIM16_OR register
+ * @{
+ */
+#define STM32_TIM16_OR_TI1_RMP_MASK         (3U << 6)
+#define STM32_TIM16_OR_TI1_RMP(n)           ((n) << 6)
+/** @} */
+/**
+ * @name    TIM_OR register
+ * @{
+ */
+#define STM32_TIM_OR_ETR_RMP_MASK           (15U << 0)
+#define STM32_TIM_OR_ETR_RMP(n)             ((n) << 0)
+/** @} */
+/**
+ * @name    TIM_CCMR3 register
+ * @{
+ */
+#define STM32_TIM_CCMR3_OC5FE               (1U << 2)
+#define STM32_TIM_CCMR3_OC5PE               (1U << 3)
+#define STM32_TIM_CCMR3_OC5M_MASK           ((7U << 4) | (1U << 16))
+#define STM32_TIM_CCMR3_OC5M(n)             ((((n) & 7) << 4) |             \
+                                             (((n) >> 2) << 16))
+#define STM32_TIM_CCMR3_OC5CE               (1U << 7)
+#define STM32_TIM_CCMR3_OC6FE               (1U << 10)
+#define STM32_TIM_CCMR3_OC6PE               (1U << 11)
+#define STM32_TIM_CCMR3_OC6M_MASK           ((7U << 12) | (1U << 24))
+#define STM32_TIM_CCMR3_OC6M(n)             ((((n) & 7) << 12) |            \
+                                             (((n) >> 2) << 24))
+#define STM32_TIM_CCMR3_OC6CE               (1U << 15)
+/** @} */
+/**
+ * @name    LPTIM_ISR register
+ * @{
+ */
+#define STM32_LPTIM_ISR_CMPM                (1U << 0)
+#define STM32_LPTIM_ISR_ARRM                (1U << 1)
+#define STM32_LPTIM_ISR_EXTTRIG             (1U << 2)
+#define STM32_LPTIM_ISR_CMPOK               (1U << 3)
+#define STM32_LPTIM_ISR_ARROK               (1U << 4)
+#define STM32_LPTIM_ISR_UP                  (1U << 5)
+#define STM32_LPTIM_ISR_DOWN                (1U << 6)
+/** @} */
+/**
+ * @name    LPTIM_ICR register
+ * @{
+ */
+#define STM32_LPTIM_ICR_CMPMCF              (1U << 0)
+#define STM32_LPTIM_ICR_ARRMCF              (1U << 1)
+#define STM32_LPTIM_ICR_EXTTRIGCF           (1U << 2)
+#define STM32_LPTIM_ICR_CMPOKCF             (1U << 3)
+#define STM32_LPTIM_ICR_ARROKCF             (1U << 4)
+#define STM32_LPTIM_ICR_UPCF                (1U << 5)
+#define STM32_LPTIM_ICR_DOWNCF              (1U << 6)
+/** @} */
+/**
+ * @name    LPTIM_IER register
+ * @{
+ */
+#define STM32_LPTIM_IER_CMPMIE              (1U << 0)
+#define STM32_LPTIM_IER_ARRMIE              (1U << 1)
+#define STM32_LPTIM_IER_EXTTRIGIE           (1U << 2)
+#define STM32_LPTIM_IER_CMPOKIE             (1U << 3)
+#define STM32_LPTIM_IER_ARROKIE             (1U << 4)
+#define STM32_LPTIM_IER_UPIE                (1U << 5)
+#define STM32_LPTIM_IER_DOWNIE              (1U << 6)
+/** @} */
+/**
+ * @name    LPTIM_CFGR register
+ * @{
+ */
+#define STM32_LPTIM_CFGR_CKSEL              (1U << 0)
+#define STM32_LPTIM_CFGR_CKPOL_MASK         (3U << 1)
+#define STM32_LPTIM_CFGR_CKPOL(n)           ((n) << 1)
+#define STM32_LPTIM_CFGR_CKFLT_MASK         (3U << 3)
+#define STM32_LPTIM_CFGR_CKFLT(n)           ((n) << 3)
+#define STM32_LPTIM_CFGR_TRGFLT_MASK        (3U << 6)
+#define STM32_LPTIM_CFGR_TRGFLT(n)          ((n) << 6)
+#define STM32_LPTIM_CFGR_PRESC_MASK         (7U << 9)
+#define STM32_LPTIM_CFGR_PRESC(n)           ((n) << 9)
+#define STM32_LPTIM_CFGR_TRIGSEL_MASK       (7U << 13)
+#define STM32_LPTIM_CFGR_TRIGSEL(n)         ((n) << 13)
+#define STM32_LPTIM_CFGR_TRIGEN_MASK        (3U << 17)
+#define STM32_LPTIM_CFGR_TRIGEN(n)          ((n) << 17)
+#define STM32_LPTIM_CFGR_TIMOUT             (1U << 19)
+#define STM32_LPTIM_CFGR_WAVE               (1U << 20)
+#define STM32_LPTIM_CFGR_WAVPOL             (1U << 21)
+#define STM32_LPTIM_CFGR_PRELOAD            (1U << 22)
+#define STM32_LPTIM_CFGR_COUNTMODE          (1U << 23)
+#define STM32_LPTIM_CFGR_ENC                (1U << 24)
+/** @} */
+/**
+ * @name    LPTIM_CR register
+ * @{
+ */
+#define STM32_LPTIM_CR_ENABLE               (1U << 0)
+#define STM32_LPTIM_CR_SNGSTRT              (1U << 1)
+#define STM32_LPTIM_CR_CNTSTRT              (1U << 2)
+/** @} */
+/**
+ * @name    LPTIM_OR register
+ * @{
+ */
+#define STM32_LPTIM_OR_0                    (1U << 0)
+#define STM32_LPTIM_OR_1                    (1U << 1)
+/** @} */
+/**
+ * @name    TIM units references
+ * @{
+ */
+#define STM32_TIM1      ((stm32_tim_t *)TIM1_BASE)
+#define STM32_TIM2      ((stm32_tim_t *)TIM2_BASE)
+#define STM32_TIM3      ((stm32_tim_t *)TIM3_BASE)
+#define STM32_TIM4      ((stm32_tim_t *)TIM4_BASE)
+#define STM32_TIM5      ((stm32_tim_t *)TIM5_BASE)
+#define STM32_TIM6      ((stm32_tim_t *)TIM6_BASE)
+#define STM32_TIM7      ((stm32_tim_t *)TIM7_BASE)
+#define STM32_TIM8      ((stm32_tim_t *)TIM8_BASE)
+#define STM32_TIM9      ((stm32_tim_t *)TIM9_BASE)
+#define STM32_TIM10     ((stm32_tim_t *)TIM10_BASE)
+#define STM32_TIM11     ((stm32_tim_t *)TIM11_BASE)
+#define STM32_TIM12     ((stm32_tim_t *)TIM12_BASE)
+#define STM32_TIM13     ((stm32_tim_t *)TIM13_BASE)
+#define STM32_TIM14     ((stm32_tim_t *)TIM14_BASE)
+#define STM32_TIM15     ((stm32_tim_t *)TIM15_BASE)
+#define STM32_TIM16     ((stm32_tim_t *)TIM16_BASE)
+#define STM32_TIM17     ((stm32_tim_t *)TIM17_BASE)
+#define STM32_TIM18     ((stm32_tim_t *)TIM18_BASE)
+#define STM32_TIM19     ((stm32_tim_t *)TIM19_BASE)
+#define STM32_TIM20     ((stm32_tim_t *)TIM20_BASE)
+#define STM32_TIM21     ((stm32_tim_t *)TIM21_BASE)
+#define STM32_TIM22     ((stm32_tim_t *)TIM22_BASE)
+#define STM32_LPTIM1    ((stm32_lptim_t *)LPTIM1_BASE)
+#define STM32_LPTIM2    ((stm32_lptim_t *)LPTIM2_BASE)
+/** @} */
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+/**
+ * @brief   STM32 TIM registers block.
+ * @note    This is the most general known form, not all timers have
+ *          necessarily all registers and bits.
+ */
+typedef struct {
+  volatile uint32_t     CR1;
+  volatile uint32_t     CR2;
+  volatile uint32_t     SMCR;
+  volatile uint32_t     DIER;
+  volatile uint32_t     SR;
+  volatile uint32_t     EGR;
+  volatile uint32_t     CCMR1;
+  volatile uint32_t     CCMR2;
+  volatile uint32_t     CCER;
+  volatile uint32_t     CNT;
+  volatile uint32_t     PSC;
+  volatile uint32_t     ARR;
+  volatile uint32_t     RCR;
+  volatile uint32_t     CCR[4];
+  volatile uint32_t     BDTR;
+#if defined(STM32G4)
+  volatile uint32_t     CCXR[2];
+  volatile uint32_t     CCMR3;
+  volatile uint32_t     DTR2;
+  volatile uint32_t     ECR;
+  volatile uint32_t     TISEL;
+  volatile uint32_t     AF1;
+  volatile uint32_t     AF2;
+  volatile uint32_t     OR;
+  volatile uint32_t     RESERVED0[220];
+  volatile uint32_t     DCR;
+  volatile uint32_t     DMAR;
+#else
+  volatile uint32_t     DCR;
+  volatile uint32_t     DMAR;
+  volatile uint32_t     OR;
+  volatile uint32_t     CCMR3;
+  volatile uint32_t     CCXR[2];
+#endif
+} stm32_tim_t;
+/**
+ * @brief   STM32 LPTIM registers block.
+ * @note    This is the most general known form, not all timers have
+ *          necessarily all registers and bits.
+ */
+typedef struct {
+  volatile uint32_t     ISR;
+  volatile uint32_t     ICR;
+  volatile uint32_t     IER;
+  volatile uint32_t     CFGR;
+  volatile uint32_t     CR;
+  volatile uint32_t     CMP;
+  volatile uint32_t     ARR;
+  volatile uint32_t     CNT;
+  volatile uint32_t     OR;
+} stm32_lptim_t;
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+#endif /* STM32_TIM_H */
+/** @} */

diff --git a/lib/chibios/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h b/lib/chibios/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h new file mode 100644 index 000000000..d15e600d2 --- /dev/null +++ b/lib/chibios/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h
@@ -0,0 +1,566 @@
	1	/*
	2	ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
	3
	4	Licensed under the Apache License, Version 2.0 (the "License");
	5	you may not use this file except in compliance with the License.
	6	You may obtain a copy of the License at
	7
	8	http://www.apache.org/licenses/LICENSE-2.0
	9
	10	Unless required by applicable law or agreed to in writing, software
	11	distributed under the License is distributed on an "AS IS" BASIS,
	12	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
	13	See the License for the specific language governing permissions and
	14	limitations under the License.
	15	*/
	16
	17	/**
	18	* @file TIMv1/stm32_tim.h
	19	* @brief STM32 TIM units common header.
	20	* @note This file requires definitions from the ST STM32 header file.
	21	*
	22	* @addtogroup STM32_TIMv1
	23	* @{
	24	*/
	25
	26	#ifndef STM32_TIM_H
	27	#define STM32_TIM_H
	28
	29	/===========================================================================/
	30	/* Driver constants. */
	31	/===========================================================================/
	32
	33	/**
	34	* @name TIM_CR1 register
	35	* @{
	36	*/
	37	#define STM32_TIM_CR1_CEN (1U << 0)
	38	#define STM32_TIM_CR1_UDIS (1U << 1)
	39	#define STM32_TIM_CR1_URS (1U << 2)
	40	#define STM32_TIM_CR1_OPM (1U << 3)
	41	#define STM32_TIM_CR1_DIR (1U << 4)
	42
	43	#define STM32_TIM_CR1_CMS_MASK (3U << 5)
	44	#define STM32_TIM_CR1_CMS(n) ((n) << 5)
	45
	46	#define STM32_TIM_CR1_ARPE (1U << 7)
	47
	48	#define STM32_TIM_CR1_CKD_MASK (3U << 8)
	49	#define STM32_TIM_CR1_CKD(n) ((n) << 8)
	50
	51	#define STM32_TIM_CR1_UIFREMAP (1U << 11)
	52	/** @} */
	53
	54	/**
	55	* @name TIM_CR2 register
	56	* @{
	57	*/
	58	#define STM32_TIM_CR2_CCPC (1U << 0)
	59	#define STM32_TIM_CR2_CCUS (1U << 2)
	60	#define STM32_TIM_CR2_CCDS (1U << 3)
	61
	62	#define STM32_TIM_CR2_MMS_MASK (7U << 4)
	63	#define STM32_TIM_CR2_MMS(n) ((n) << 4)
	64
	65	#define STM32_TIM_CR2_TI1S (1U << 7)
	66	#define STM32_TIM_CR2_OIS1 (1U << 8)
	67	#define STM32_TIM_CR2_OIS1N (1U << 9)
	68	#define STM32_TIM_CR2_OIS2 (1U << 10)
	69	#define STM32_TIM_CR2_OIS2N (1U << 11)
	70	#define STM32_TIM_CR2_OIS3 (1U << 12)
	71	#define STM32_TIM_CR2_OIS3N (1U << 13)
	72	#define STM32_TIM_CR2_OIS4 (1U << 14)
	73	#define STM32_TIM_CR2_OIS5 (1U << 16)
	74	#define STM32_TIM_CR2_OIS6 (1U << 18)
	75
	76	#define STM32_TIM_CR2_MMS2_MASK (15U << 20)
	77	#define STM32_TIM_CR2_MMS2(n) ((n) << 20)
	78	/** @} */
	79
	80	/**
	81	* @name TIM_SMCR register
	82	* @{
	83	*/
	84	#define STM32_TIM_SMCR_SMS_MASK ((7U << 0) \| (1U << 16))
	85	#define STM32_TIM_SMCR_SMS(n) ((((n) & 7) << 0) \| \
	86	(((n) >> 3) << 16))
	87
	88	#define STM32_TIM_SMCR_OCCS (1U << 3)
	89
	90	#define STM32_TIM_SMCR_TS_MASK (7U << 4)
	91	#define STM32_TIM_SMCR_TS(n) ((n) << 4)
	92
	93	#define STM32_TIM_SMCR_MSM (1U << 7)
	94
	95	#define STM32_TIM_SMCR_ETF_MASK (15U << 8)
	96	#define STM32_TIM_SMCR_ETF(n) ((n) << 8)
	97
	98	#define STM32_TIM_SMCR_ETPS_MASK (3U << 12)
	99	#define STM32_TIM_SMCR_ETPS(n) ((n) << 12)
	100
	101	#define STM32_TIM_SMCR_ECE (1U << 14)
	102	#define STM32_TIM_SMCR_ETP (1U << 15)
	103	/** @} */
	104
	105	/**
	106	* @name TIM_DIER register
	107	* @{
	108	*/
	109	#define STM32_TIM_DIER_UIE (1U << 0)
	110	#define STM32_TIM_DIER_CC1IE (1U << 1)
	111	#define STM32_TIM_DIER_CC2IE (1U << 2)
	112	#define STM32_TIM_DIER_CC3IE (1U << 3)
	113	#define STM32_TIM_DIER_CC4IE (1U << 4)
	114	#define STM32_TIM_DIER_COMIE (1U << 5)
	115	#define STM32_TIM_DIER_TIE (1U << 6)
	116	#define STM32_TIM_DIER_BIE (1U << 7)
	117	#define STM32_TIM_DIER_UDE (1U << 8)
	118	#define STM32_TIM_DIER_CC1DE (1U << 9)
	119	#define STM32_TIM_DIER_CC2DE (1U << 10)
	120	#define STM32_TIM_DIER_CC3DE (1U << 11)
	121	#define STM32_TIM_DIER_CC4DE (1U << 12)
	122	#define STM32_TIM_DIER_COMDE (1U << 13)
	123	#define STM32_TIM_DIER_TDE (1U << 14)
	124
	125	#define STM32_TIM_DIER_IRQ_MASK (STM32_TIM_DIER_UIE \| \
	126	STM32_TIM_DIER_CC1IE \| \
	127	STM32_TIM_DIER_CC2IE \| \
	128	STM32_TIM_DIER_CC3IE \| \
	129	STM32_TIM_DIER_CC4IE \| \
	130	STM32_TIM_DIER_COMIE \| \
	131	STM32_TIM_DIER_TIE \| \
	132	STM32_TIM_DIER_BIE)
	133
	134	/** @} */
	135
	136	/**
	137	* @name TIM_SR register
	138	* @{
	139	*/
	140	#define STM32_TIM_SR_UIF (1U << 0)
	141	#define STM32_TIM_SR_CC1IF (1U << 1)
	142	#define STM32_TIM_SR_CC2IF (1U << 2)
	143	#define STM32_TIM_SR_CC3IF (1U << 3)
	144	#define STM32_TIM_SR_CC4IF (1U << 4)
	145	#define STM32_TIM_SR_COMIF (1U << 5)
	146	#define STM32_TIM_SR_TIF (1U << 6)
	147	#define STM32_TIM_SR_BIF (1U << 7)
	148	#define STM32_TIM_SR_B2IF (1U << 8)
	149	#define STM32_TIM_SR_CC1OF (1U << 9)
	150	#define STM32_TIM_SR_CC2OF (1U << 10)
	151	#define STM32_TIM_SR_CC3OF (1U << 11)
	152	#define STM32_TIM_SR_CC4OF (1U << 12)
	153	#define STM32_TIM_SR_CC5IF (1U << 16)
	154	#define STM32_TIM_SR_CC6IF (1U << 17)
	155	/** @} */
	156
	157	/**
	158	* @name TIM_EGR register
	159	* @{
	160	*/
	161	#define STM32_TIM_EGR_UG (1U << 0)
	162	#define STM32_TIM_EGR_CC1G (1U << 1)
	163	#define STM32_TIM_EGR_CC2G (1U << 2)
	164	#define STM32_TIM_EGR_CC3G (1U << 3)
	165	#define STM32_TIM_EGR_CC4G (1U << 4)
	166	#define STM32_TIM_EGR_COMG (1U << 5)
	167	#define STM32_TIM_EGR_TG (1U << 6)
	168	#define STM32_TIM_EGR_BG (1U << 7)
	169	#define STM32_TIM_EGR_B2G (1U << 8)
	170	/** @} */
	171
	172	/**
	173	* @name TIM_CCMR1 register (output)
	174	* @{
	175	*/
	176	#define STM32_TIM_CCMR1_CC1S_MASK (3U << 0)
	177	#define STM32_TIM_CCMR1_CC1S(n) ((n) << 0)
	178
	179	#define STM32_TIM_CCMR1_OC1FE (1U << 2)
	180	#define STM32_TIM_CCMR1_OC1PE (1U << 3)
	181
	182	#define STM32_TIM_CCMR1_OC1M_MASK ((7U << 4) \| (1U << 16))
	183	#define STM32_TIM_CCMR1_OC1M(n) ((((n) & 7) << 4) \| \
	184	(((n) >> 3) << 16))
	185
	186	#define STM32_TIM_CCMR1_OC1CE (1U << 7)
	187
	188	#define STM32_TIM_CCMR1_CC2S_MASK (3U << 8)
	189	#define STM32_TIM_CCMR1_CC2S(n) ((n) << 8)
	190
	191	#define STM32_TIM_CCMR1_OC2FE (1U << 10)
	192	#define STM32_TIM_CCMR1_OC2PE (1U << 11)
	193
	194	#define STM32_TIM_CCMR1_OC2M_MASK ((7U << 12) \| (1U << 24))
	195	#define STM32_TIM_CCMR1_OC2M(n) ((((n) & 7) << 12) \| \
	196	(((n) >> 3) << 24))
	197
	198	#define STM32_TIM_CCMR1_OC2CE (1U << 15)
	199	/** @} */
	200
	201	/**
	202	* @name CCMR1 register (input)
	203	* @{
	204	*/
	205	#define STM32_TIM_CCMR1_IC1PSC_MASK (3U << 2)
	206	#define STM32_TIM_CCMR1_IC1PSC(n) ((n) << 2)
	207
	208	#define STM32_TIM_CCMR1_IC1F_MASK (15U << 4)
	209	#define STM32_TIM_CCMR1_IC1F(n) ((n) << 4)
	210
	211	#define STM32_TIM_CCMR1_IC2PSC_MASK (3U << 10)
	212	#define STM32_TIM_CCMR1_IC2PSC(n) ((n) << 10)
	213
	214	#define STM32_TIM_CCMR1_IC2F_MASK (15U << 12)
	215	#define STM32_TIM_CCMR1_IC2F(n) ((n) << 12)
	216	/** @} */
	217
	218	/**
	219	* @name TIM_CCMR2 register (output)
	220	* @{
	221	*/
	222	#define STM32_TIM_CCMR2_CC3S_MASK (3U << 0)
	223	#define STM32_TIM_CCMR2_CC3S(n) ((n) << 0)
	224
	225	#define STM32_TIM_CCMR2_OC3FE (1U << 2)
	226	#define STM32_TIM_CCMR2_OC3PE (1U << 3)
	227
	228	#define STM32_TIM_CCMR2_OC3M_MASK ((7U << 4) \| (1U << 16))
	229	#define STM32_TIM_CCMR2_OC3M(n) ((((n) & 7) << 4) \| \
	230	(((n) >> 3) << 16))
	231
	232	#define STM32_TIM_CCMR2_OC3CE (1U << 7)
	233
	234	#define STM32_TIM_CCMR2_CC4S_MASK (3U << 8)
	235	#define STM32_TIM_CCMR2_CC4S(n) ((n) << 8)
	236
	237	#define STM32_TIM_CCMR2_OC4FE (1U << 10)
	238	#define STM32_TIM_CCMR2_OC4PE (1U << 11)
	239
	240	#define STM32_TIM_CCMR2_OC4M_MASK ((7U << 12) \| (1U << 24))
	241	#define STM32_TIM_CCMR2_OC4M(n) ((((n) & 7) << 12) \| \
	242	(((n) >> 3) << 24))
	243
	244	#define STM32_TIM_CCMR2_OC4CE (1U << 15)
	245	/** @} */
	246
	247	/**
	248	* @name TIM_CCMR2 register (input)
	249	* @{
	250	*/
	251	#define STM32_TIM_CCMR2_IC3PSC_MASK (3U << 2)
	252	#define STM32_TIM_CCMR2_IC3PSC(n) ((n) << 2)
	253
	254	#define STM32_TIM_CCMR2_IC3F_MASK (15U << 4)
	255	#define STM32_TIM_CCMR2_IC3F(n) ((n) << 4)
	256
	257	#define STM32_TIM_CCMR2_IC4PSC_MASK (3U << 10)
	258	#define STM32_TIM_CCMR2_IC4PSC(n) ((n) << 10)
	259
	260	#define STM32_TIM_CCMR2_IC4F_MASK (15U << 12)
	261	#define STM32_TIM_CCMR2_IC4F(n) ((n) << 12)
	262	/** @} */
	263
	264	/**
	265	* @name TIM_CCER register
	266	* @{
	267	*/
	268	#define STM32_TIM_CCER_CC1E (1U << 0)
	269	#define STM32_TIM_CCER_CC1P (1U << 1)
	270	#define STM32_TIM_CCER_CC1NE (1U << 2)
	271	#define STM32_TIM_CCER_CC1NP (1U << 3)
	272	#define STM32_TIM_CCER_CC2E (1U << 4)
	273	#define STM32_TIM_CCER_CC2P (1U << 5)
	274	#define STM32_TIM_CCER_CC2NE (1U << 6)
	275	#define STM32_TIM_CCER_CC2NP (1U << 7)
	276	#define STM32_TIM_CCER_CC3E (1U << 8)
	277	#define STM32_TIM_CCER_CC3P (1U << 9)
	278	#define STM32_TIM_CCER_CC3NE (1U << 10)
	279	#define STM32_TIM_CCER_CC3NP (1U << 11)
	280	#define STM32_TIM_CCER_CC4E (1U << 12)
	281	#define STM32_TIM_CCER_CC4P (1U << 13)
	282	#define STM32_TIM_CCER_CC4NE (1U << 14)
	283	#define STM32_TIM_CCER_CC4NP (1U << 15)
	284	#define STM32_TIM_CCER_CC5E (1U << 16)
	285	#define STM32_TIM_CCER_CC5P (1U << 17)
	286	#define STM32_TIM_CCER_CC6E (1U << 20)
	287	#define STM32_TIM_CCER_CC6P (1U << 21)
	288	/** @} */
	289
	290	/**
	291	* @name TIM_CNT register
	292	* @{
	293	*/
	294	#define STM32_TIM_CNT_UIFCPY (1U << 31)
	295	/** @} */
	296
	297	/**
	298	* @name TIM_BDTR register
	299	* @{
	300	*/
	301	#define STM32_TIM_BDTR_DTG_MASK (255U << 0)
	302	#define STM32_TIM_BDTR_DTG(n) ((n) << 0)
	303
	304	#define STM32_TIM_BDTR_LOCK_MASK (3U << 8)
	305	#define STM32_TIM_BDTR_LOCK(n) ((n) << 8)
	306
	307	#define STM32_TIM_BDTR_OSSI (1U << 10)
	308	#define STM32_TIM_BDTR_OSSR (1U << 11)
	309	#define STM32_TIM_BDTR_BKE (1U << 12)
	310	#define STM32_TIM_BDTR_BKP (1U << 13)
	311	#define STM32_TIM_BDTR_AOE (1U << 14)
	312	#define STM32_TIM_BDTR_MOE (1U << 15)
	313
	314	#define STM32_TIM_BDTR_BKF_MASK (15U << 16)
	315	#define STM32_TIM_BDTR_BKF(n) ((n) << 16)
	316	#define STM32_TIM_BDTR_BK2F_MASK (15U << 20)
	317	#define STM32_TIM_BDTR_BK2F(n) ((n) << 20)
	318
	319	#define STM32_TIM_BDTR_BK2E (1U << 24)
	320	#define STM32_TIM_BDTR_BK2P (1U << 25)
	321	/** @} */
	322
	323	/**
	324	* @name TIM_DCR register
	325	* @{
	326	*/
	327	#define STM32_TIM_DCR_DBA_MASK (31U << 0)
	328	#define STM32_TIM_DCR_DBA(n) ((n) << 0)
	329
	330	#define STM32_TIM_DCR_DBL_MASK (31U << 8)
	331	#define STM32_TIM_DCR_DBL(n) ((n) << 8)
	332	/** @} */
	333
	334	/**
	335	* @name TIM16_OR register
	336	* @{
	337	*/
	338	#define STM32_TIM16_OR_TI1_RMP_MASK (3U << 6)
	339	#define STM32_TIM16_OR_TI1_RMP(n) ((n) << 6)
	340	/** @} */
	341
	342	/**
	343	* @name TIM_OR register
	344	* @{
	345	*/
	346	#define STM32_TIM_OR_ETR_RMP_MASK (15U << 0)
	347	#define STM32_TIM_OR_ETR_RMP(n) ((n) << 0)
	348	/** @} */
	349
	350	/**
	351	* @name TIM_CCMR3 register
	352	* @{
	353	*/
	354	#define STM32_TIM_CCMR3_OC5FE (1U << 2)
	355	#define STM32_TIM_CCMR3_OC5PE (1U << 3)
	356
	357	#define STM32_TIM_CCMR3_OC5M_MASK ((7U << 4) \| (1U << 16))
	358	#define STM32_TIM_CCMR3_OC5M(n) ((((n) & 7) << 4) \| \
	359	(((n) >> 2) << 16))
	360
	361	#define STM32_TIM_CCMR3_OC5CE (1U << 7)
	362
	363	#define STM32_TIM_CCMR3_OC6FE (1U << 10)
	364	#define STM32_TIM_CCMR3_OC6PE (1U << 11)
	365
	366	#define STM32_TIM_CCMR3_OC6M_MASK ((7U << 12) \| (1U << 24))
	367	#define STM32_TIM_CCMR3_OC6M(n) ((((n) & 7) << 12) \| \
	368	(((n) >> 2) << 24))
	369
	370	#define STM32_TIM_CCMR3_OC6CE (1U << 15)
	371	/** @} */
	372
	373	/**
	374	* @name LPTIM_ISR register
	375	* @{
	376	*/
	377	#define STM32_LPTIM_ISR_CMPM (1U << 0)
	378	#define STM32_LPTIM_ISR_ARRM (1U << 1)
	379	#define STM32_LPTIM_ISR_EXTTRIG (1U << 2)
	380	#define STM32_LPTIM_ISR_CMPOK (1U << 3)
	381	#define STM32_LPTIM_ISR_ARROK (1U << 4)
	382	#define STM32_LPTIM_ISR_UP (1U << 5)
	383	#define STM32_LPTIM_ISR_DOWN (1U << 6)
	384	/** @} */
	385
	386	/**
	387	* @name LPTIM_ICR register
	388	* @{
	389	*/
	390	#define STM32_LPTIM_ICR_CMPMCF (1U << 0)
	391	#define STM32_LPTIM_ICR_ARRMCF (1U << 1)
	392	#define STM32_LPTIM_ICR_EXTTRIGCF (1U << 2)
	393	#define STM32_LPTIM_ICR_CMPOKCF (1U << 3)
	394	#define STM32_LPTIM_ICR_ARROKCF (1U << 4)
	395	#define STM32_LPTIM_ICR_UPCF (1U << 5)
	396	#define STM32_LPTIM_ICR_DOWNCF (1U << 6)
	397	/** @} */
	398
	399	/**
	400	* @name LPTIM_IER register
	401	* @{
	402	*/
	403	#define STM32_LPTIM_IER_CMPMIE (1U << 0)
	404	#define STM32_LPTIM_IER_ARRMIE (1U << 1)
	405	#define STM32_LPTIM_IER_EXTTRIGIE (1U << 2)
	406	#define STM32_LPTIM_IER_CMPOKIE (1U << 3)
	407	#define STM32_LPTIM_IER_ARROKIE (1U << 4)
	408	#define STM32_LPTIM_IER_UPIE (1U << 5)
	409	#define STM32_LPTIM_IER_DOWNIE (1U << 6)
	410	/** @} */
	411
	412	/**
	413	* @name LPTIM_CFGR register
	414	* @{
	415	*/
	416	#define STM32_LPTIM_CFGR_CKSEL (1U << 0)
	417	#define STM32_LPTIM_CFGR_CKPOL_MASK (3U << 1)
	418	#define STM32_LPTIM_CFGR_CKPOL(n) ((n) << 1)
	419	#define STM32_LPTIM_CFGR_CKFLT_MASK (3U << 3)
	420	#define STM32_LPTIM_CFGR_CKFLT(n) ((n) << 3)
	421	#define STM32_LPTIM_CFGR_TRGFLT_MASK (3U << 6)
	422	#define STM32_LPTIM_CFGR_TRGFLT(n) ((n) << 6)
	423	#define STM32_LPTIM_CFGR_PRESC_MASK (7U << 9)
	424	#define STM32_LPTIM_CFGR_PRESC(n) ((n) << 9)
	425	#define STM32_LPTIM_CFGR_TRIGSEL_MASK (7U << 13)
	426	#define STM32_LPTIM_CFGR_TRIGSEL(n) ((n) << 13)
	427	#define STM32_LPTIM_CFGR_TRIGEN_MASK (3U << 17)
	428	#define STM32_LPTIM_CFGR_TRIGEN(n) ((n) << 17)
	429	#define STM32_LPTIM_CFGR_TIMOUT (1U << 19)
	430	#define STM32_LPTIM_CFGR_WAVE (1U << 20)
	431	#define STM32_LPTIM_CFGR_WAVPOL (1U << 21)
	432	#define STM32_LPTIM_CFGR_PRELOAD (1U << 22)
	433	#define STM32_LPTIM_CFGR_COUNTMODE (1U << 23)
	434	#define STM32_LPTIM_CFGR_ENC (1U << 24)
	435	/** @} */
	436
	437	/**
	438	* @name LPTIM_CR register
	439	* @{
	440	*/
	441	#define STM32_LPTIM_CR_ENABLE (1U << 0)
	442	#define STM32_LPTIM_CR_SNGSTRT (1U << 1)
	443	#define STM32_LPTIM_CR_CNTSTRT (1U << 2)
	444	/** @} */
	445
	446	/**
	447	* @name LPTIM_OR register
	448	* @{
	449	*/
	450	#define STM32_LPTIM_OR_0 (1U << 0)
	451	#define STM32_LPTIM_OR_1 (1U << 1)
	452	/** @} */
	453
	454	/**
	455	* @name TIM units references
	456	* @{
	457	*/
	458	#define STM32_TIM1 ((stm32_tim_t *)TIM1_BASE)
	459	#define STM32_TIM2 ((stm32_tim_t *)TIM2_BASE)
	460	#define STM32_TIM3 ((stm32_tim_t *)TIM3_BASE)
	461	#define STM32_TIM4 ((stm32_tim_t *)TIM4_BASE)
	462	#define STM32_TIM5 ((stm32_tim_t *)TIM5_BASE)
	463	#define STM32_TIM6 ((stm32_tim_t *)TIM6_BASE)
	464	#define STM32_TIM7 ((stm32_tim_t *)TIM7_BASE)
	465	#define STM32_TIM8 ((stm32_tim_t *)TIM8_BASE)
	466	#define STM32_TIM9 ((stm32_tim_t *)TIM9_BASE)
	467	#define STM32_TIM10 ((stm32_tim_t *)TIM10_BASE)
	468	#define STM32_TIM11 ((stm32_tim_t *)TIM11_BASE)
	469	#define STM32_TIM12 ((stm32_tim_t *)TIM12_BASE)
	470	#define STM32_TIM13 ((stm32_tim_t *)TIM13_BASE)
	471	#define STM32_TIM14 ((stm32_tim_t *)TIM14_BASE)
	472	#define STM32_TIM15 ((stm32_tim_t *)TIM15_BASE)
	473	#define STM32_TIM16 ((stm32_tim_t *)TIM16_BASE)
	474	#define STM32_TIM17 ((stm32_tim_t *)TIM17_BASE)
	475	#define STM32_TIM18 ((stm32_tim_t *)TIM18_BASE)
	476	#define STM32_TIM19 ((stm32_tim_t *)TIM19_BASE)
	477	#define STM32_TIM20 ((stm32_tim_t *)TIM20_BASE)
	478	#define STM32_TIM21 ((stm32_tim_t *)TIM21_BASE)
	479	#define STM32_TIM22 ((stm32_tim_t *)TIM22_BASE)
	480
	481	#define STM32_LPTIM1 ((stm32_lptim_t *)LPTIM1_BASE)
	482	#define STM32_LPTIM2 ((stm32_lptim_t *)LPTIM2_BASE)
	483	/** @} */
	484
	485	/===========================================================================/
	486	/* Driver pre-compile time settings. */
	487	/===========================================================================/
	488
	489	/===========================================================================/
	490	/* Derived constants and error checks. */
	491	/===========================================================================/
	492
	493	/===========================================================================/
	494	/* Driver data structures and types. */
	495	/===========================================================================/
	496
	497	/**
	498	* @brief STM32 TIM registers block.
	499	* @note This is the most general known form, not all timers have
	500	* necessarily all registers and bits.
	501	*/
	502	typedef struct {
	503	volatile uint32_t CR1;
	504	volatile uint32_t CR2;
	505	volatile uint32_t SMCR;
	506	volatile uint32_t DIER;
	507	volatile uint32_t SR;
	508	volatile uint32_t EGR;
	509	volatile uint32_t CCMR1;
	510	volatile uint32_t CCMR2;
	511	volatile uint32_t CCER;
	512	volatile uint32_t CNT;
	513	volatile uint32_t PSC;
	514	volatile uint32_t ARR;
	515	volatile uint32_t RCR;
	516	volatile uint32_t CCR[4];
	517	volatile uint32_t BDTR;
	518	#if defined(STM32G4)
	519	volatile uint32_t CCXR[2];
	520	volatile uint32_t CCMR3;
	521	volatile uint32_t DTR2;
	522	volatile uint32_t ECR;
	523	volatile uint32_t TISEL;
	524	volatile uint32_t AF1;
	525	volatile uint32_t AF2;
	526	volatile uint32_t OR;
	527	volatile uint32_t RESERVED0[220];
	528	volatile uint32_t DCR;
	529	volatile uint32_t DMAR;
	530	#else
	531	volatile uint32_t DCR;
	532	volatile uint32_t DMAR;
	533	volatile uint32_t OR;
	534	volatile uint32_t CCMR3;
	535	volatile uint32_t CCXR[2];
	536	#endif
	537	} stm32_tim_t;
	538
	539	/**
	540	* @brief STM32 LPTIM registers block.
	541	* @note This is the most general known form, not all timers have
	542	* necessarily all registers and bits.
	543	*/
	544	typedef struct {
	545	volatile uint32_t ISR;
	546	volatile uint32_t ICR;
	547	volatile uint32_t IER;
	548	volatile uint32_t CFGR;
	549	volatile uint32_t CR;
	550	volatile uint32_t CMP;
	551	volatile uint32_t ARR;
	552	volatile uint32_t CNT;
	553	volatile uint32_t OR;
	554	} stm32_lptim_t;
	555
	556	/===========================================================================/
	557	/* Driver macros. */
	558	/===========================================================================/
	559
	560	/===========================================================================/
	561	/* External declarations. */
	562	/===========================================================================/
	563
	564	#endif /* STM32_TIM_H */
	565
	566	/** @} */