diff options
Diffstat (limited to 'lib/chibios/os/hal/ports/STM32/LLD/TIMv1/stm32_tim5.inc')
-rw-r--r-- | lib/chibios/os/hal/ports/STM32/LLD/TIMv1/stm32_tim5.inc | 133 |
1 files changed, 133 insertions, 0 deletions
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/TIMv1/stm32_tim5.inc b/lib/chibios/os/hal/ports/STM32/LLD/TIMv1/stm32_tim5.inc new file mode 100644 index 000000000..35158b3c0 --- /dev/null +++ b/lib/chibios/os/hal/ports/STM32/LLD/TIMv1/stm32_tim5.inc | |||
@@ -0,0 +1,133 @@ | |||
1 | /* | ||
2 | ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio | ||
3 | |||
4 | Licensed under the Apache License, Version 2.0 (the "License"); | ||
5 | you may not use this file except in compliance with the License. | ||
6 | You may obtain a copy of the License at | ||
7 | |||
8 | http://www.apache.org/licenses/LICENSE-2.0 | ||
9 | |||
10 | Unless required by applicable law or agreed to in writing, software | ||
11 | distributed under the License is distributed on an "AS IS" BASIS, | ||
12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
13 | See the License for the specific language governing permissions and | ||
14 | limitations under the License. | ||
15 | */ | ||
16 | |||
17 | /** | ||
18 | * @file TIMv1/stm32_tim5.inc | ||
19 | * @brief Shared TIM5 handler. | ||
20 | * | ||
21 | * @addtogroup STM32_TIM5_HANDLER | ||
22 | * @{ | ||
23 | */ | ||
24 | |||
25 | /*===========================================================================*/ | ||
26 | /* Driver local definitions. */ | ||
27 | /*===========================================================================*/ | ||
28 | |||
29 | /*===========================================================================*/ | ||
30 | /* Derived constants and error checks. */ | ||
31 | /*===========================================================================*/ | ||
32 | |||
33 | /* Registry checks for robustness.*/ | ||
34 | #if !defined(STM32_HAS_TIM5) | ||
35 | #error "STM32_HAS_TIM5 not defined in registry" | ||
36 | #endif | ||
37 | |||
38 | /* Driver checks for robustness, undefined USE macros are defaulted to | ||
39 | FALSE. This makes this module independent from drivers implementation.*/ | ||
40 | #if !defined(STM32_GPT_USE_TIM5) | ||
41 | #define STM32_GPT_USE_TIM5 FALSE | ||
42 | #endif | ||
43 | #if !defined(STM32_ICU_USE_TIM5) | ||
44 | #define STM32_ICU_USE_TIM5 FALSE | ||
45 | #endif | ||
46 | #if !defined(STM32_PWM_USE_TIM5) | ||
47 | #define STM32_PWM_USE_TIM5 FALSE | ||
48 | #endif | ||
49 | #if !defined(STM32_ST_USE_TIM5) | ||
50 | #define STM32_ST_USE_TIM5 FALSE | ||
51 | #endif | ||
52 | |||
53 | #if STM32_HAS_TIM5 | ||
54 | |||
55 | /* Priority settings checks.*/ | ||
56 | #if !defined(STM32_IRQ_TIM5_PRIORITY) | ||
57 | #error "STM32_IRQ_TIM5_PRIORITY not defined in mcuconf.h" | ||
58 | #endif | ||
59 | |||
60 | #if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM5_PRIORITY) | ||
61 | #error "Invalid IRQ priority assigned to STM32_IRQ_TIM5_PRIORITY" | ||
62 | #endif | ||
63 | |||
64 | #endif /* STM32_HAS_TIM5 */ | ||
65 | |||
66 | /*===========================================================================*/ | ||
67 | /* Driver exported variables. */ | ||
68 | /*===========================================================================*/ | ||
69 | |||
70 | /*===========================================================================*/ | ||
71 | /* Driver local variables. */ | ||
72 | /*===========================================================================*/ | ||
73 | |||
74 | /*===========================================================================*/ | ||
75 | /* Driver local functions. */ | ||
76 | /*===========================================================================*/ | ||
77 | |||
78 | static inline void tim5_irq_init(void) { | ||
79 | #if defined(STM32_TIM5_IS_USED) | ||
80 | nvicEnableVector(STM32_TIM5_NUMBER, STM32_IRQ_TIM5_PRIORITY); | ||
81 | #endif | ||
82 | } | ||
83 | |||
84 | static inline void tim5_irq_deinit(void) { | ||
85 | #if defined(STM32_TIM5_IS_USED) | ||
86 | nvicDisableVector(STM32_TIM5_NUMBER); | ||
87 | #endif | ||
88 | } | ||
89 | |||
90 | /*===========================================================================*/ | ||
91 | /* Driver interrupt handlers. */ | ||
92 | /*===========================================================================*/ | ||
93 | |||
94 | #if defined(STM32_TIM5_IS_USED) || defined(__DOXYGEN__) | ||
95 | /** | ||
96 | * @brief TIM5 interrupt handler. | ||
97 | * | ||
98 | * @isr | ||
99 | */ | ||
100 | OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) { | ||
101 | |||
102 | OSAL_IRQ_PROLOGUE(); | ||
103 | |||
104 | #if HAL_USE_GPT | ||
105 | #if STM32_GPT_USE_TIM5 | ||
106 | gpt_lld_serve_interrupt(&GPTD5); | ||
107 | #endif | ||
108 | #endif | ||
109 | #if HAL_USE_ICU | ||
110 | #if STM32_ICU_USE_TIM5 | ||
111 | icu_lld_serve_interrupt(&ICUD5); | ||
112 | #endif | ||
113 | #endif | ||
114 | #if HAL_USE_PWM | ||
115 | #if STM32_PWM_USE_TIM5 | ||
116 | pwm_lld_serve_interrupt(&PWMD5); | ||
117 | #endif | ||
118 | #endif | ||
119 | #if 1 | ||
120 | #if STM32_ST_USE_TIM5 | ||
121 | st_lld_serve_interrupt(); | ||
122 | #endif | ||
123 | #endif | ||
124 | |||
125 | OSAL_IRQ_EPILOGUE(); | ||
126 | } | ||
127 | #endif | ||
128 | |||
129 | /*===========================================================================*/ | ||
130 | /* Driver exported functions. */ | ||
131 | /*===========================================================================*/ | ||
132 | |||
133 | /** @} */ | ||