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-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/driver.mk13
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c913
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h534
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c1075
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h842
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_lpuart1.inc110
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart4.inc121
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart5.inc121
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart7.inc121
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart8.inc121
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart1.inc121
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart2.inc121
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3.inc121
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3_4_lp1.inc157
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart4_5.inc144
-rw-r--r--lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart6.inc121
16 files changed, 4756 insertions, 0 deletions
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/driver.mk b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/driver.mk
new file mode 100644
index 000000000..6b614601d
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/driver.mk
@@ -0,0 +1,13 @@
1ifeq ($(USE_SMART_BUILD),yes)
2ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
3PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
4endif
5ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),)
6PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
7endif
8else
9PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
10PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
11endif
12
13PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
new file mode 100644
index 000000000..27b6a6404
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
@@ -0,0 +1,913 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/hal_serial_lld.c
19 * @brief STM32 low level serial driver code.
20 *
21 * @addtogroup SERIAL
22 * @{
23 */
24
25#include "hal.h"
26
27#if HAL_USE_SERIAL || defined(__DOXYGEN__)
28
29/*===========================================================================*/
30/* Driver local definitions. */
31/*===========================================================================*/
32
33/* For compatibility for those devices without LIN support in the USARTs.*/
34#if !defined(USART_ISR_LBDF)
35#define USART_ISR_LBDF 0
36#endif
37
38#if !defined(USART_CR2_LBDIE)
39#define USART_CR2_LBDIE 0
40#endif
41
42/* Differences in L4+ headers.*/
43#if !defined(USART_CR1_TXEIE)
44#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
45#endif
46
47#if !defined(USART_CR1_RXNEIE)
48#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
49#endif
50
51#if !defined(USART_ISR_TXE)
52#define USART_ISR_TXE USART_ISR_TXE_TXFNF
53#endif
54
55#if !defined(USART_ISR_RXNE)
56#define USART_ISR_RXNE USART_ISR_RXNE_RXFNE
57#endif
58
59/* STM32L0xx/STM32F7xx ST headers difference.*/
60#if !defined(USART_ISR_LBDF)
61#define USART_ISR_LBDF USART_ISR_LBD
62#endif
63
64/* Handling differences in frame size bits.*/
65#if !defined(USART_CR1_M_0)
66#define USART_CR1_M_0 (1 << 12)
67#endif
68
69#if !defined(USART_CR1_M_1)
70#define USART_CR1_M_1 (1 << 28)
71#endif
72
73/* Workarounds for those devices where UARTs are USARTs.*/
74#if defined(USART4)
75#define UART4 USART4
76#endif
77#if defined(USART5)
78#define UART5 USART5
79#endif
80#if defined(USART7)
81#define UART7 USART7
82#endif
83#if defined(USART8)
84#define UART8 USART8
85#endif
86
87/*===========================================================================*/
88/* Driver exported variables. */
89/*===========================================================================*/
90
91/** @brief USART1 serial driver identifier.*/
92#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
93SerialDriver SD1;
94#endif
95
96/** @brief USART2 serial driver identifier.*/
97#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
98SerialDriver SD2;
99#endif
100
101/** @brief USART3 serial driver identifier.*/
102#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
103SerialDriver SD3;
104#endif
105
106/** @brief UART4 serial driver identifier.*/
107#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
108SerialDriver SD4;
109#endif
110
111/** @brief UART5 serial driver identifier.*/
112#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
113SerialDriver SD5;
114#endif
115
116/** @brief USART6 serial driver identifier.*/
117#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
118SerialDriver SD6;
119#endif
120
121/** @brief UART7 serial driver identifier.*/
122#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
123SerialDriver SD7;
124#endif
125
126/** @brief UART8 serial driver identifier.*/
127#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
128SerialDriver SD8;
129#endif
130
131/** @brief LPUART1 serial driver identifier.*/
132#if STM32_SERIAL_USE_LPUART1 || defined(__DOXYGEN__)
133SerialDriver LPSD1;
134#endif
135
136/*===========================================================================*/
137/* Driver local variables and types. */
138/*===========================================================================*/
139
140/** @brief Driver default configuration.*/
141static const SerialConfig default_config =
142{
143 SERIAL_DEFAULT_BITRATE,
144 0,
145 USART_CR2_STOP1_BITS,
146 0
147};
148
149#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
150/** @brief Input buffer for SD1.*/
151static uint8_t sd_in_buf1[STM32_SERIAL_USART1_IN_BUF_SIZE];
152
153/** @brief Output buffer for SD1.*/
154static uint8_t sd_out_buf1[STM32_SERIAL_USART1_OUT_BUF_SIZE];
155#endif
156
157#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
158/** @brief Input buffer for SD2.*/
159static uint8_t sd_in_buf2[STM32_SERIAL_USART2_IN_BUF_SIZE];
160
161/** @brief Output buffer for SD2.*/
162static uint8_t sd_out_buf2[STM32_SERIAL_USART2_OUT_BUF_SIZE];
163#endif
164
165#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
166/** @brief Input buffer for SD3.*/
167static uint8_t sd_in_buf3[STM32_SERIAL_USART3_IN_BUF_SIZE];
168
169/** @brief Output buffer for SD3.*/
170static uint8_t sd_out_buf3[STM32_SERIAL_USART3_OUT_BUF_SIZE];
171#endif
172
173#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
174/** @brief Input buffer for SD4.*/
175static uint8_t sd_in_buf4[STM32_SERIAL_UART4_IN_BUF_SIZE];
176
177/** @brief Output buffer for SD4.*/
178static uint8_t sd_out_buf4[STM32_SERIAL_UART4_OUT_BUF_SIZE];
179#endif
180
181#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
182/** @brief Input buffer for SD5.*/
183static uint8_t sd_in_buf5[STM32_SERIAL_UART5_IN_BUF_SIZE];
184
185/** @brief Output buffer for SD5.*/
186static uint8_t sd_out_buf5[STM32_SERIAL_UART5_OUT_BUF_SIZE];
187#endif
188
189#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
190/** @brief Input buffer for SD6.*/
191static uint8_t sd_in_buf6[STM32_SERIAL_USART6_IN_BUF_SIZE];
192
193/** @brief Output buffer for SD6.*/
194static uint8_t sd_out_buf6[STM32_SERIAL_USART6_OUT_BUF_SIZE];
195#endif
196
197#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
198/** @brief Input buffer for SD7.*/
199static uint8_t sd_in_buf7[STM32_SERIAL_UART7_IN_BUF_SIZE];
200
201/** @brief Output buffer for SD7.*/
202static uint8_t sd_out_buf7[STM32_SERIAL_UART7_OUT_BUF_SIZE];
203#endif
204
205#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
206/** @brief Input buffer for SD8.*/
207static uint8_t sd_in_buf8[STM32_SERIAL_UART8_IN_BUF_SIZE];
208
209/** @brief Output buffer for SD8.*/
210static uint8_t sd_out_buf8[STM32_SERIAL_UART8_OUT_BUF_SIZE];
211#endif
212
213#if STM32_SERIAL_USE_LPUART1 || defined(__DOXYGEN__)
214/** @brief Input buffer for LPSD1.*/
215static uint8_t sd_in_buflp1[STM32_SERIAL_LPUART1_IN_BUF_SIZE];
216
217/** @brief Output buffer for LPSD1.*/
218static uint8_t sd_out_buflp1[STM32_SERIAL_LPUART1_OUT_BUF_SIZE];
219#endif
220
221/*===========================================================================*/
222/* Driver local functions. */
223/*===========================================================================*/
224
225/**
226 * @brief USART initialization.
227 * @details This function must be invoked with interrupts disabled.
228 *
229 * @param[in] sdp pointer to a @p SerialDriver object
230 * @param[in] config the architecture-dependent serial driver configuration
231 */
232static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
233 uint32_t brr;
234 USART_TypeDef *u = sdp->usart;
235
236 /* Baud rate setting.*/
237#if STM32_SERIAL_USE_LPUART1
238 if (sdp == &LPSD1) {
239 osalDbgAssert((sdp->clock >= config->speed * 3U) &&
240 (sdp->clock <= config->speed * 4096U),
241 "invalid baud rate vs input clock");
242
243 brr = (uint32_t)(((uint64_t)sdp->clock * 256) / config->speed);
244
245 osalDbgAssert((brr >= 0x300) && (brr < 0x100000), "invalid BRR value");
246 }
247 else
248#endif
249 {
250 brr = (uint32_t)(sdp->clock / config->speed);
251
252 /* Correcting BRR value when oversampling by 8 instead of 16.
253 Fraction is still 4 bits wide, but only lower 3 bits used.
254 Mantissa is doubled, but Fraction is left the same.*/
255 if (config->cr1 & USART_CR1_OVER8)
256 brr = ((brr & ~7) * 2) | (brr & 7);
257
258 osalDbgAssert(brr < 0x10000, "invalid BRR value");
259 }
260 u->BRR = brr;
261
262 /* Note that some bits are enforced.*/
263 u->CR2 = config->cr2 | USART_CR2_LBDIE;
264 u->CR3 = config->cr3 | USART_CR3_EIE;
265 u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE |
266 USART_CR1_RXNEIE | USART_CR1_TE |
267 USART_CR1_RE;
268 u->ICR = 0xFFFFFFFFU;
269
270 /* Deciding mask to be applied on the data register on receive, this is
271 required in order to mask out the parity bit.*/
272 if ((config->cr1 & USART_CR1_PCE) != 0U) {
273 switch (config->cr1 & (USART_CR1_M_1 | USART_CR1_M_0)) {
274 case 0:
275 sdp->rxmask = 0x7F;
276 break;
277 case USART_CR1_M_1:
278 sdp->rxmask = 0x3F;
279 break;
280 default:
281 sdp->rxmask = 0xFF;
282 }
283 }
284 else {
285 sdp->rxmask = 0xFF;
286 }
287}
288
289/**
290 * @brief USART de-initialization.
291 * @details This function must be invoked with interrupts disabled.
292 *
293 * @param[in] u pointer to an USART I/O block
294 */
295static void usart_deinit(USART_TypeDef *u) {
296
297 u->CR1 = 0;
298 u->CR2 = 0;
299 u->CR3 = 0;
300}
301
302/**
303 * @brief Error handling routine.
304 *
305 * @param[in] sdp pointer to a @p SerialDriver object
306 * @param[in] isr USART ISR register value
307 */
308static void set_error(SerialDriver *sdp, uint32_t isr) {
309 eventflags_t sts = 0;
310
311 if (isr & USART_ISR_ORE)
312 sts |= SD_OVERRUN_ERROR;
313 if (isr & USART_ISR_PE)
314 sts |= SD_PARITY_ERROR;
315 if (isr & USART_ISR_FE)
316 sts |= SD_FRAMING_ERROR;
317 if (isr & USART_ISR_NE)
318 sts |= SD_NOISE_ERROR;
319 osalSysLockFromISR();
320 chnAddFlagsI(sdp, sts);
321 osalSysUnlockFromISR();
322}
323
324#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
325static void notify1(io_queue_t *qp) {
326
327 (void)qp;
328 USART1->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
329}
330#endif
331
332#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
333static void notify2(io_queue_t *qp) {
334
335 (void)qp;
336 USART2->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
337}
338#endif
339
340#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
341static void notify3(io_queue_t *qp) {
342
343 (void)qp;
344 USART3->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
345}
346#endif
347
348#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
349static void notify4(io_queue_t *qp) {
350
351 (void)qp;
352 UART4->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
353}
354#endif
355
356#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
357static void notify5(io_queue_t *qp) {
358
359 (void)qp;
360 UART5->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
361}
362#endif
363
364#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
365static void notify6(io_queue_t *qp) {
366
367 (void)qp;
368 USART6->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
369}
370#endif
371
372#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
373static void notify7(io_queue_t *qp) {
374
375 (void)qp;
376 UART7->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
377}
378#endif
379
380#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
381static void notify8(io_queue_t *qp) {
382
383 (void)qp;
384 UART8->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
385}
386#endif
387
388#if STM32_SERIAL_USE_LPUART1 || defined(__DOXYGEN__)
389static void notifylp1(io_queue_t *qp) {
390
391 (void)qp;
392 LPUART1->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
393}
394#endif
395
396/*===========================================================================*/
397/* Driver interrupt handlers. */
398/*===========================================================================*/
399
400#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
401#if !defined(STM32_USART1_SUPPRESS_ISR)
402#if !defined(STM32_USART1_HANDLER)
403#error "STM32_USART1_HANDLER not defined"
404#endif
405/**
406 * @brief USART1 interrupt handler.
407 *
408 * @isr
409 */
410OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
411
412 OSAL_IRQ_PROLOGUE();
413
414 sd_lld_serve_interrupt(&SD1);
415
416 OSAL_IRQ_EPILOGUE();
417}
418#endif
419#endif
420
421#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
422#if !defined(STM32_USART2_SUPPRESS_ISR)
423#if !defined(STM32_USART2_HANDLER)
424#error "STM32_USART2_HANDLER not defined"
425#endif
426/**
427 * @brief USART2 interrupt handler.
428 *
429 * @isr
430 */
431OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
432
433 OSAL_IRQ_PROLOGUE();
434
435 sd_lld_serve_interrupt(&SD2);
436
437 OSAL_IRQ_EPILOGUE();
438}
439#endif
440#endif
441
442#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
443#if !defined(STM32_USART3_SUPPRESS_ISR)
444#if !defined(STM32_USART3_HANDLER)
445#error "STM32_USART3_HANDLER not defined"
446#endif
447/**
448 * @brief USART3 interrupt handler.
449 *
450 * @isr
451 */
452OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) {
453
454 OSAL_IRQ_PROLOGUE();
455
456 sd_lld_serve_interrupt(&SD3);
457
458 OSAL_IRQ_EPILOGUE();
459}
460#endif
461#endif
462
463#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
464#if !defined(STM32_UART4_SUPPRESS_ISR)
465#if !defined(STM32_UART4_HANDLER)
466#error "STM32_UART4_HANDLER not defined"
467#endif
468/**
469 * @brief UART4 interrupt handler.
470 *
471 * @isr
472 */
473OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) {
474
475 OSAL_IRQ_PROLOGUE();
476
477 sd_lld_serve_interrupt(&SD4);
478
479 OSAL_IRQ_EPILOGUE();
480}
481#endif
482#endif
483
484#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
485#if !defined(STM32_UART5_SUPPRESS_ISR)
486#if !defined(STM32_UART5_HANDLER)
487#error "STM32_UART5_HANDLER not defined"
488#endif
489/**
490 * @brief UART5 interrupt handler.
491 *
492 * @isr
493 */
494OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) {
495
496 OSAL_IRQ_PROLOGUE();
497
498 sd_lld_serve_interrupt(&SD5);
499
500 OSAL_IRQ_EPILOGUE();
501}
502#endif
503#endif
504
505#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
506#if !defined(STM32_USART6_SUPPRESS_ISR)
507#if !defined(STM32_USART6_HANDLER)
508#error "STM32_USART6_HANDLER not defined"
509#endif
510/**
511 * @brief USART6 interrupt handler.
512 *
513 * @isr
514 */
515OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) {
516
517 OSAL_IRQ_PROLOGUE();
518
519 sd_lld_serve_interrupt(&SD6);
520
521 OSAL_IRQ_EPILOGUE();
522}
523#endif
524#endif
525
526#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
527#if !defined(STM32_UART7_SUPPRESS_ISR)
528#if !defined(STM32_UART7_HANDLER)
529#error "STM32_UART7_HANDLER not defined"
530#endif
531/**
532 * @brief UART7 interrupt handler.
533 *
534 * @isr
535 */
536OSAL_IRQ_HANDLER(STM32_UART7_HANDLER) {
537
538 OSAL_IRQ_PROLOGUE();
539
540 sd_lld_serve_interrupt(&SD7);
541
542 OSAL_IRQ_EPILOGUE();
543}
544#endif
545#endif
546
547#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
548#if !defined(STM32_UART8_SUPPRESS_ISR)
549#if !defined(STM32_UART8_HANDLER)
550#error "STM32_UART8_HANDLER not defined"
551#endif
552/**
553 * @brief UART8 interrupt handler.
554 *
555 * @isr
556 */
557OSAL_IRQ_HANDLER(STM32_UART8_HANDLER) {
558
559 OSAL_IRQ_PROLOGUE();
560
561 sd_lld_serve_interrupt(&SD8);
562
563 OSAL_IRQ_EPILOGUE();
564}
565#endif
566#endif
567
568#if STM32_SERIAL_USE_LPUART1 || defined(__DOXYGEN__)
569#if !defined(STM32_LPUART1_SUPPRESS_ISR)
570#if !defined(STM32_LPUART1_HANDLER)
571#error "STM32_LPUART1_HANDLER not defined"
572#endif
573/**
574 * @brief LPUART1 interrupt handler.
575 *
576 * @isr
577 */
578OSAL_IRQ_HANDLER(STM32_LPUART1_HANDLER) {
579
580 OSAL_IRQ_PROLOGUE();
581
582 sd_lld_serve_interrupt(&LPSD1);
583
584 OSAL_IRQ_EPILOGUE();
585}
586#endif
587#endif
588
589/*===========================================================================*/
590/* Driver exported functions. */
591/*===========================================================================*/
592
593/**
594 * @brief Low level serial driver initialization.
595 *
596 * @notapi
597 */
598void sd_lld_init(void) {
599
600#if STM32_SERIAL_USE_USART1
601 sdObjectInit(&SD1);
602 iqObjectInit(&SD1.iqueue, sd_in_buf1, sizeof sd_in_buf1, NULL, &SD1);
603 oqObjectInit(&SD1.oqueue, sd_out_buf1, sizeof sd_out_buf1, notify1, &SD1);
604 SD1.usart = USART1;
605 SD1.clock = STM32_USART1CLK;
606#if !defined(STM32_USART1_SUPPRESS_ISR) && defined(STM32_USART1_NUMBER)
607 nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY);
608#endif
609#endif
610
611#if STM32_SERIAL_USE_USART2
612 sdObjectInit(&SD2);
613 iqObjectInit(&SD2.iqueue, sd_in_buf2, sizeof sd_in_buf2, NULL, &SD2);
614 oqObjectInit(&SD2.oqueue, sd_out_buf2, sizeof sd_out_buf2, notify2, &SD2);
615 SD2.usart = USART2;
616 SD2.clock = STM32_USART2CLK;
617#if !defined(STM32_USART2_SUPPRESS_ISR) && defined(STM32_USART2_NUMBER)
618 nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY);
619#endif
620#endif
621
622#if STM32_SERIAL_USE_USART3
623 sdObjectInit(&SD3);
624 iqObjectInit(&SD3.iqueue, sd_in_buf3, sizeof sd_in_buf3, NULL, &SD3);
625 oqObjectInit(&SD3.oqueue, sd_out_buf3, sizeof sd_out_buf3, notify3, &SD3);
626 SD3.usart = USART3;
627 SD3.clock = STM32_USART3CLK;
628#if !defined(STM32_USART3_SUPPRESS_ISR) && defined(STM32_USART3_NUMBER)
629 nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY);
630#endif
631#endif
632
633#if STM32_SERIAL_USE_UART4
634 sdObjectInit(&SD4);
635 iqObjectInit(&SD4.iqueue, sd_in_buf4, sizeof sd_in_buf4, NULL, &SD4);
636 oqObjectInit(&SD4.oqueue, sd_out_buf4, sizeof sd_out_buf4, notify4, &SD4);
637 SD4.usart = UART4;
638 SD4.clock = STM32_UART4CLK;
639#if !defined(STM32_UART4_SUPPRESS_ISR) && defined(STM32_UART4_NUMBER)
640 nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY);
641#endif
642#endif
643
644#if STM32_SERIAL_USE_UART5
645 sdObjectInit(&SD5);
646 iqObjectInit(&SD5.iqueue, sd_in_buf5, sizeof sd_in_buf5, NULL, &SD5);
647 oqObjectInit(&SD5.oqueue, sd_out_buf5, sizeof sd_out_buf5, notify5, &SD5);
648 SD5.usart = UART5;
649 SD5.clock = STM32_UART5CLK;
650#if !defined(STM32_UART5_SUPPRESS_ISR) && defined(STM32_UART5_NUMBER)
651 nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY);
652#endif
653#endif
654
655#if STM32_SERIAL_USE_USART6
656 sdObjectInit(&SD6);
657 iqObjectInit(&SD6.iqueue, sd_in_buf6, sizeof sd_in_buf6, NULL, &SD6);
658 oqObjectInit(&SD6.oqueue, sd_out_buf6, sizeof sd_out_buf6, notify6, &SD6);
659 SD6.usart = USART6;
660 SD6.clock = STM32_USART6CLK;
661#if !defined(STM32_USART6_SUPPRESS_ISR) && defined(STM32_USART6_NUMBER)
662 nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY);
663#endif
664#endif
665
666#if STM32_SERIAL_USE_UART7
667 sdObjectInit(&SD7);
668 iqObjectInit(&SD7.iqueue, sd_in_buf7, sizeof sd_in_buf7, NULL, &SD7);
669 oqObjectInit(&SD7.oqueue, sd_out_buf7, sizeof sd_out_buf7, notify7, &SD7);
670 SD7.usart = UART7;
671 SD7.clock = STM32_UART7CLK;
672#if !defined(STM32_UART7_SUPPRESS_ISR) && defined(STM32_UART7_NUMBER)
673 nvicEnableVector(STM32_UART7_NUMBER, STM32_SERIAL_UART7_PRIORITY);
674#endif
675#endif
676
677#if STM32_SERIAL_USE_UART8
678 sdObjectInit(&SD8);
679 iqObjectInit(&SD8.iqueue, sd_in_buf8, sizeof sd_in_buf8, NULL, &SD8);
680 oqObjectInit(&SD8.oqueue, sd_out_buf8, sizeof sd_out_buf8, notify8, &SD8);
681 SD8.usart = UART8;
682 SD8.clock = STM32_UART8CLK;
683#if !defined(STM32_UART8_SUPPRESS_ISR) && defined(STM32_UART8_NUMBER)
684 nvicEnableVector(STM32_UART8_NUMBER, STM32_SERIAL_UART8_PRIORITY);
685#endif
686#endif
687
688#if STM32_SERIAL_USE_LPUART1
689 sdObjectInit(&LPSD1);
690 iqObjectInit(&LPSD1.iqueue, sd_in_buflp1, sizeof sd_in_buflp1, NULL, &LPSD1);
691 oqObjectInit(&LPSD1.oqueue, sd_out_buflp1, sizeof sd_out_buflp1, notifylp1, &LPSD1);
692 LPSD1.usart = LPUART1;
693 LPSD1.clock = STM32_LPUART1CLK;
694#if !defined(STM32_LPUART1_SUPPRESS_ISR) && defined(STM32_LPUART1_NUMBER)
695 nvicEnableVector(STM32_LPUART1_NUMBER, STM32_SERIAL_LPUART1_PRIORITY);
696#endif
697#endif
698}
699
700/**
701 * @brief Low level serial driver configuration and (re)start.
702 *
703 * @param[in] sdp pointer to a @p SerialDriver object
704 * @param[in] config the architecture-dependent serial driver configuration.
705 * If this parameter is set to @p NULL then a default
706 * configuration is used.
707 *
708 * @notapi
709 */
710void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
711
712 if (config == NULL)
713 config = &default_config;
714
715 if (sdp->state == SD_STOP) {
716#if STM32_SERIAL_USE_USART1
717 if (&SD1 == sdp) {
718 rccEnableUSART1(true);
719 }
720#endif
721#if STM32_SERIAL_USE_USART2
722 if (&SD2 == sdp) {
723 rccEnableUSART2(true);
724 }
725#endif
726#if STM32_SERIAL_USE_USART3
727 if (&SD3 == sdp) {
728 rccEnableUSART3(true);
729 }
730#endif
731#if STM32_SERIAL_USE_UART4
732 if (&SD4 == sdp) {
733 rccEnableUART4(true);
734 }
735#endif
736#if STM32_SERIAL_USE_UART5
737 if (&SD5 == sdp) {
738 rccEnableUART5(true);
739 }
740#endif
741#if STM32_SERIAL_USE_USART6
742 if (&SD6 == sdp) {
743 rccEnableUSART6(true);
744 }
745#endif
746#if STM32_SERIAL_USE_UART7
747 if (&SD7 == sdp) {
748 rccEnableUART7(true);
749 }
750#endif
751#if STM32_SERIAL_USE_UART8
752 if (&SD8 == sdp) {
753 rccEnableUART8(true);
754 }
755#endif
756#if STM32_SERIAL_USE_LPUART1
757 if (&LPSD1 == sdp) {
758 rccEnableLPUART1(true);
759 }
760#endif
761 }
762 usart_init(sdp, config);
763}
764
765/**
766 * @brief Low level serial driver stop.
767 * @details De-initializes the USART, stops the associated clock, resets the
768 * interrupt vector.
769 *
770 * @param[in] sdp pointer to a @p SerialDriver object
771 *
772 * @notapi
773 */
774void sd_lld_stop(SerialDriver *sdp) {
775
776 if (sdp->state == SD_READY) {
777 /* UART is de-initialized then clocks are disabled.*/
778 usart_deinit(sdp->usart);
779
780#if STM32_SERIAL_USE_USART1
781 if (&SD1 == sdp) {
782 rccDisableUSART1();
783 return;
784 }
785#endif
786#if STM32_SERIAL_USE_USART2
787 if (&SD2 == sdp) {
788 rccDisableUSART2();
789 return;
790 }
791#endif
792#if STM32_SERIAL_USE_USART3
793 if (&SD3 == sdp) {
794 rccDisableUSART3();
795 return;
796 }
797#endif
798#if STM32_SERIAL_USE_UART4
799 if (&SD4 == sdp) {
800 rccDisableUART4();
801 return;
802 }
803#endif
804#if STM32_SERIAL_USE_UART5
805 if (&SD5 == sdp) {
806 rccDisableUART5();
807 return;
808 }
809#endif
810#if STM32_SERIAL_USE_USART6
811 if (&SD6 == sdp) {
812 rccDisableUSART6();
813 return;
814 }
815#endif
816#if STM32_SERIAL_USE_UART7
817 if (&SD7 == sdp) {
818 rccDisableUART7();
819 return;
820 }
821#endif
822#if STM32_SERIAL_USE_UART8
823 if (&SD8 == sdp) {
824 rccDisableUART8();
825 return;
826 }
827#endif
828#if STM32_SERIAL_USE_LPUART1
829 if (&LPSD1 == sdp) {
830 rccDisableLPUART1();
831 return;
832 }
833#endif
834 }
835}
836
837/**
838 * @brief Common IRQ handler.
839 *
840 * @param[in] sdp communication channel associated to the USART
841 */
842void sd_lld_serve_interrupt(SerialDriver *sdp) {
843 USART_TypeDef *u = sdp->usart;
844 uint32_t cr1 = u->CR1;
845 uint32_t isr;
846
847 /* Reading and clearing status.*/
848 isr = u->ISR;
849 u->ICR = isr;
850
851 /* Error condition detection.*/
852 if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE | USART_ISR_PE))
853 set_error(sdp, isr);
854
855 /* Special case, LIN break detection.*/
856 if (isr & USART_ISR_LBDF) {
857 osalSysLockFromISR();
858 chnAddFlagsI(sdp, SD_BREAK_DETECTED);
859 osalSysUnlockFromISR();
860 }
861
862 /* Data available, note it is a while in order to handle two situations:
863 1) Another byte arrived after removing the previous one, this would cause
864 an extra interrupt to serve.
865 2) FIFO mode is enabled on devices that support it, we need to empty
866 the FIFO.*/
867 while (isr & USART_ISR_RXNE) {
868 osalSysLockFromISR();
869 sdIncomingDataI(sdp, (uint8_t)u->RDR & sdp->rxmask);
870 osalSysUnlockFromISR();
871
872 isr = u->ISR;
873 }
874
875 /* Transmission buffer empty, note it is a while in order to handle two
876 situations:
877 1) The data registers has been emptied immediately after writing it, this
878 would cause an extra interrupt to serve.
879 2) FIFO mode is enabled on devices that support it, we need to fill
880 the FIFO.*/
881 if (cr1 & USART_CR1_TXEIE) {
882 while (isr & USART_ISR_TXE) {
883 msg_t b;
884
885 osalSysLockFromISR();
886 b = oqGetI(&sdp->oqueue);
887 if (b < MSG_OK) {
888 chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
889 u->CR1 = cr1 & ~USART_CR1_TXEIE;
890 osalSysUnlockFromISR();
891 break;
892 }
893 u->TDR = b;
894 osalSysUnlockFromISR();
895
896 isr = u->ISR;
897 }
898 }
899
900 /* Physical transmission end.*/
901 if ((cr1 & USART_CR1_TCIE) && (isr & USART_ISR_TC)) {
902 osalSysLockFromISR();
903 if (oqIsEmptyI(&sdp->oqueue)) {
904 chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
905 u->CR1 = cr1 & ~USART_CR1_TCIE;
906 }
907 osalSysUnlockFromISR();
908 }
909}
910
911#endif /* HAL_USE_SERIAL */
912
913/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h
new file mode 100644
index 000000000..2655d7ca2
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h
@@ -0,0 +1,534 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/hal_serial_lld.h
19 * @brief STM32 low level serial driver header.
20 *
21 * @addtogroup SERIAL
22 * @{
23 */
24
25#ifndef HAL_SERIAL_LLD_H
26#define HAL_SERIAL_LLD_H
27
28#if HAL_USE_SERIAL || defined(__DOXYGEN__)
29
30/*===========================================================================*/
31/* Driver constants. */
32/*===========================================================================*/
33
34/**
35 * @brief Advanced buffering support switch.
36 * @details This constants enables the advanced buffering support in the
37 * low level driver, the queue buffer is no more part of the
38 * @p SerialDriver structure, each driver can have a different
39 * queue size.
40 */
41#define SERIAL_ADVANCED_BUFFERING_SUPPORT TRUE
42
43/*===========================================================================*/
44/* Driver pre-compile time settings. */
45/*===========================================================================*/
46
47/**
48 * @name Configuration options
49 * @{
50 */
51/**
52 * @brief USART1 driver enable switch.
53 * @details If set to @p TRUE the support for USART1 is included.
54 * @note The default is @p FALSE.
55 */
56#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__)
57#define STM32_SERIAL_USE_USART1 FALSE
58#endif
59
60/**
61 * @brief USART2 driver enable switch.
62 * @details If set to @p TRUE the support for USART2 is included.
63 * @note The default is @p FALSE.
64 */
65#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__)
66#define STM32_SERIAL_USE_USART2 FALSE
67#endif
68
69/**
70 * @brief USART3 driver enable switch.
71 * @details If set to @p TRUE the support for USART3 is included.
72 * @note The default is @p FALSE.
73 */
74#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__)
75#define STM32_SERIAL_USE_USART3 FALSE
76#endif
77
78/**
79 * @brief UART4 driver enable switch.
80 * @details If set to @p TRUE the support for UART4 is included.
81 * @note The default is @p FALSE.
82 */
83#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__)
84#define STM32_SERIAL_USE_UART4 FALSE
85#endif
86
87/**
88 * @brief UART5 driver enable switch.
89 * @details If set to @p TRUE the support for UART5 is included.
90 * @note The default is @p FALSE.
91 */
92#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__)
93#define STM32_SERIAL_USE_UART5 FALSE
94#endif
95
96/**
97 * @brief USART6 driver enable switch.
98 * @details If set to @p TRUE the support for USART6 is included.
99 * @note The default is @p FALSE.
100 */
101#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__)
102#define STM32_SERIAL_USE_USART6 FALSE
103#endif
104
105/**
106 * @brief UART7 driver enable switch.
107 * @details If set to @p TRUE the support for UART7 is included.
108 * @note The default is @p FALSE.
109 */
110#if !defined(STM32_SERIAL_USE_UART7) || defined(__DOXYGEN__)
111#define STM32_SERIAL_USE_UART7 FALSE
112#endif
113
114/**
115 * @brief UART8 driver enable switch.
116 * @details If set to @p TRUE the support for UART8 is included.
117 * @note The default is @p FALSE.
118 */
119#if !defined(STM32_SERIAL_USE_UART8) || defined(__DOXYGEN__)
120#define STM32_SERIAL_USE_UART8 FALSE
121#endif
122
123/**
124 * @brief LPUART1 driver enable switch.
125 * @details If set to @p TRUE the support for LPUART is included.
126 * @note The default is @p FALSE.
127 */
128#if !defined(STM32_SERIAL_USE_LPUART1) || defined(__DOXYGEN__)
129#define STM32_SERIAL_USE_LPUART1 FALSE
130#endif
131
132/**
133 * @brief USART1 interrupt priority level setting.
134 */
135#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__)
136#define STM32_SERIAL_USART1_PRIORITY 12
137#endif
138
139/**
140 * @brief USART2 interrupt priority level setting.
141 */
142#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__)
143#define STM32_SERIAL_USART2_PRIORITY 12
144#endif
145
146/**
147 * @brief USART3 interrupt priority level setting.
148 */
149#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__)
150#define STM32_SERIAL_USART3_PRIORITY 12
151#endif
152
153/**
154 * @brief UART4 interrupt priority level setting.
155 */
156#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
157#define STM32_SERIAL_UART4_PRIORITY 12
158#endif
159
160/**
161 * @brief UART5 interrupt priority level setting.
162 */
163#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
164#define STM32_SERIAL_UART5_PRIORITY 12
165#endif
166
167/**
168 * @brief USART6 interrupt priority level setting.
169 */
170#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__)
171#define STM32_SERIAL_USART6_PRIORITY 12
172#endif
173
174/**
175 * @brief UART7 interrupt priority level setting.
176 */
177#if !defined(STM32_SERIAL_UART7_PRIORITY) || defined(__DOXYGEN__)
178#define STM32_SERIAL_UART7_PRIORITY 12
179#endif
180
181/**
182 * @brief UART8 interrupt priority level setting.
183 */
184#if !defined(STM32_SERIAL_UART8_PRIORITY) || defined(__DOXYGEN__)
185#define STM32_SERIAL_UART8_PRIORITY 12
186#endif
187
188/**
189 * @brief LPUART1 interrupt priority level setting.
190 */
191#if !defined(STM32_SERIAL_LPUART1_PRIORITY) || defined(__DOXYGEN__)
192#define STM32_SERIAL_LPUART1_PRIORITY 12
193#endif
194
195/**
196 * @brief Input buffer size for USART1.
197 */
198#if !defined(STM32_SERIAL_USART1_IN_BUF_SIZE) || defined(__DOXYGEN__)
199#define STM32_SERIAL_USART1_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
200#endif
201
202/**
203 * @brief Output buffer size for USART1.
204 */
205#if !defined(STM32_SERIAL_USART1_OUT_BUF_SIZE) || defined(__DOXYGEN__)
206#define STM32_SERIAL_USART1_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
207#endif
208
209/**
210 * @brief Input buffer size for USART2.
211 */
212#if !defined(STM32_SERIAL_USART2_IN_BUF_SIZE) || defined(__DOXYGEN__)
213#define STM32_SERIAL_USART2_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
214#endif
215
216/**
217 * @brief Output buffer size for USART2.
218 */
219#if !defined(STM32_SERIAL_USART2_OUT_BUF_SIZE) || defined(__DOXYGEN__)
220#define STM32_SERIAL_USART2_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
221#endif
222
223/**
224 * @brief Input buffer size for USART3.
225 */
226#if !defined(STM32_SERIAL_USART3_IN_BUF_SIZE) || defined(__DOXYGEN__)
227#define STM32_SERIAL_USART3_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
228#endif
229
230/**
231 * @brief Output buffer size for USART3.
232 */
233#if !defined(STM32_SERIAL_USART3_OUT_BUF_SIZE) || defined(__DOXYGEN__)
234#define STM32_SERIAL_USART3_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
235#endif
236
237/**
238 * @brief Input buffer size for UART4.
239 */
240#if !defined(STM32_SERIAL_UART4_IN_BUF_SIZE) || defined(__DOXYGEN__)
241#define STM32_SERIAL_UART4_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
242#endif
243
244/**
245 * @brief Output buffer size for UART4.
246 */
247#if !defined(STM32_SERIAL_UART4_OUT_BUF_SIZE) || defined(__DOXYGEN__)
248#define STM32_SERIAL_UART4_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
249#endif
250
251/**
252 * @brief Input buffer size for UART5.
253 */
254#if !defined(STM32_SERIAL_UART5_IN_BUF_SIZE) || defined(__DOXYGEN__)
255#define STM32_SERIAL_UART5_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
256#endif
257
258/**
259 * @brief Output buffer size for UART5.
260 */
261#if !defined(STM32_SERIAL_UART5_OUT_BUF_SIZE) || defined(__DOXYGEN__)
262#define STM32_SERIAL_UART5_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
263#endif
264
265/**
266 * @brief Input buffer size for USART6.
267 */
268#if !defined(STM32_SERIAL_USART6_IN_BUF_SIZE) || defined(__DOXYGEN__)
269#define STM32_SERIAL_USART6_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
270#endif
271
272/**
273 * @brief Output buffer size for USART6.
274 */
275#if !defined(STM32_SERIAL_USART6_OUT_BUF_SIZE) || defined(__DOXYGEN__)
276#define STM32_SERIAL_USART6_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
277#endif
278
279/**
280 * @brief Input buffer size for UART7.
281 */
282#if !defined(STM32_SERIAL_UART7_IN_BUF_SIZE) || defined(__DOXYGEN__)
283#define STM32_SERIAL_UART7_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
284#endif
285
286/**
287 * @brief Output buffer size for UART7.
288 */
289#if !defined(STM32_SERIAL_UART7_OUT_BUF_SIZE) || defined(__DOXYGEN__)
290#define STM32_SERIAL_UART7_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
291#endif
292
293/**
294 * @brief Input buffer size for UART8.
295 */
296#if !defined(STM32_SERIAL_UART8_IN_BUF_SIZE) || defined(__DOXYGEN__)
297#define STM32_SERIAL_UART8_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
298#endif
299
300/**
301 * @brief Output buffer size for UART8.
302 */
303#if !defined(STM32_SERIAL_UART8_OUT_BUF_SIZE) || defined(__DOXYGEN__)
304#define STM32_SERIAL_UART8_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
305#endif
306
307/**
308 * @brief Input buffer size for LPUART1.
309 */
310#if !defined(STM32_SERIAL_LPUART1_IN_BUF_SIZE) || defined(__DOXYGEN__)
311#define STM32_SERIAL_LPUART1_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
312#endif
313
314/**
315 * @brief Output buffer size for LPUART1.
316 */
317#if !defined(STM32_SERIAL_LPUART1_OUT_BUF_SIZE) || defined(__DOXYGEN__)
318#define STM32_SERIAL_LPUART1_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
319#endif
320/** @} */
321
322/*===========================================================================*/
323/* Derived constants and error checks. */
324/*===========================================================================*/
325
326#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1
327#error "USART1 not present in the selected device"
328#endif
329
330#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2
331#error "USART2 not present in the selected device"
332#endif
333
334#if STM32_SERIAL_USE_USART3 && !STM32_HAS_USART3
335#error "USART3 not present in the selected device"
336#endif
337
338#if STM32_SERIAL_USE_UART4 && !STM32_HAS_UART4
339#error "UART4 not present in the selected device"
340#endif
341
342#if STM32_SERIAL_USE_UART5 && !STM32_HAS_UART5
343#error "UART5 not present in the selected device"
344#endif
345
346#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6
347#error "USART6 not present in the selected device"
348#endif
349
350#if STM32_SERIAL_USE_UART7 && !STM32_HAS_UART7
351#error "UART7 not present in the selected device"
352#endif
353
354#if STM32_SERIAL_USE_UART8 && !STM32_HAS_UART8
355#error "UART8 not present in the selected device"
356#endif
357
358#if STM32_SERIAL_USE_LPUART1 && !STM32_HAS_LPUART1
359#error "LPUART1 not present in the selected device"
360#endif
361
362#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 && \
363 !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4 && \
364 !STM32_SERIAL_USE_UART5 && !STM32_SERIAL_USE_USART6 && \
365 !STM32_SERIAL_USE_UART7 && !STM32_SERIAL_USE_UART8 && \
366 !STM32_SERIAL_USE_LPUART1
367#error "SERIAL driver activated but no USART/UART peripheral assigned"
368#endif
369
370#if !defined(STM32_USART1_SUPPRESS_ISR) && \
371 STM32_SERIAL_USE_USART1 && \
372 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART1_PRIORITY)
373#error "Invalid IRQ priority assigned to USART1"
374#endif
375
376#if !defined(STM32_USART2_SUPPRESS_ISR) && \
377 STM32_SERIAL_USE_USART2 && \
378 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART2_PRIORITY)
379#error "Invalid IRQ priority assigned to USART2"
380#endif
381
382#if !defined(STM32_USART3_SUPPRESS_ISR) && \
383 STM32_SERIAL_USE_USART3 && \
384 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART3_PRIORITY)
385#error "Invalid IRQ priority assigned to USART3"
386#endif
387
388#if !defined(STM32_UART4_SUPPRESS_ISR) && \
389 STM32_SERIAL_USE_UART4 && \
390 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART4_PRIORITY)
391#error "Invalid IRQ priority assigned to UART4"
392#endif
393
394#if !defined(STM32_UART5_SUPPRESS_ISR) && \
395 STM32_SERIAL_USE_UART5 && \
396 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART5_PRIORITY)
397#error "Invalid IRQ priority assigned to UART5"
398#endif
399
400#if !defined(STM32_USART6_SUPPRESS_ISR) && \
401 STM32_SERIAL_USE_USART6 && \
402 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART6_PRIORITY)
403#error "Invalid IRQ priority assigned to USART6"
404#endif
405
406#if !defined(STM32_UART7_SUPPRESS_ISR) && \
407 STM32_SERIAL_USE_UART7 && \
408 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART7_PRIORITY)
409#error "Invalid IRQ priority assigned to UART7"
410#endif
411
412#if !defined(STM32_UART8_SUPPRESS_ISR) && \
413 STM32_SERIAL_USE_UART8 && \
414 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART8_PRIORITY)
415#error "Invalid IRQ priority assigned to UART8"
416#endif
417
418#if !defined(STM32_LPUART1_SUPPRESS_ISR) && \
419 STM32_SERIAL_USE_LPUART1 && \
420 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_LPUART1_PRIORITY)
421#error "Invalid IRQ priority assigned to LPUART1"
422#endif
423
424/*===========================================================================*/
425/* Driver data structures and types. */
426/*===========================================================================*/
427
428/**
429 * @brief STM32 Serial Driver configuration structure.
430 * @details An instance of this structure must be passed to @p sdStart()
431 * in order to configure and start a serial driver operations.
432 * @note This structure content is architecture dependent, each driver
433 * implementation defines its own version and the custom static
434 * initializers.
435 */
436typedef struct {
437 /**
438 * @brief Bit rate.
439 */
440 uint32_t speed;
441 /* End of the mandatory fields.*/
442 /**
443 * @brief Initialization value for the CR1 register.
444 */
445 uint32_t cr1;
446 /**
447 * @brief Initialization value for the CR2 register.
448 */
449 uint32_t cr2;
450 /**
451 * @brief Initialization value for the CR3 register.
452 */
453 uint32_t cr3;
454} SerialConfig;
455
456/**
457 * @brief @p SerialDriver specific data.
458 */
459#define _serial_driver_data \
460 _base_asynchronous_channel_data \
461 /* Driver state.*/ \
462 sdstate_t state; \
463 /* Input queue.*/ \
464 input_queue_t iqueue; \
465 /* Output queue.*/ \
466 output_queue_t oqueue; \
467 /* End of the mandatory fields.*/ \
468 /* Pointer to the USART registers block.*/ \
469 USART_TypeDef *usart; \
470 /* Clock frequency for the associated USART/UART.*/ \
471 uint32_t clock; \
472 /* Mask to be applied on received frames.*/ \
473 uint8_t rxmask;
474
475/*===========================================================================*/
476/* Driver macros. */
477/*===========================================================================*/
478
479/*
480 * Extra USARTs definitions here (missing from the ST header file).
481 */
482#define USART_CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/
483#define USART_CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/
484#define USART_CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/
485#define USART_CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/
486
487/*===========================================================================*/
488/* External declarations. */
489/*===========================================================================*/
490
491#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__)
492extern SerialDriver SD1;
493#endif
494#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__)
495extern SerialDriver SD2;
496#endif
497#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__)
498extern SerialDriver SD3;
499#endif
500#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
501extern SerialDriver SD4;
502#endif
503#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
504extern SerialDriver SD5;
505#endif
506#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__)
507extern SerialDriver SD6;
508#endif
509#if STM32_SERIAL_USE_UART7 && !defined(__DOXYGEN__)
510extern SerialDriver SD7;
511#endif
512#if STM32_SERIAL_USE_UART8 && !defined(__DOXYGEN__)
513extern SerialDriver SD8;
514#endif
515#if STM32_SERIAL_USE_LPUART1 && !defined(__DOXYGEN__)
516extern SerialDriver LPSD1;
517#endif
518
519#ifdef __cplusplus
520extern "C" {
521#endif
522 void sd_lld_init(void);
523 void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
524 void sd_lld_stop(SerialDriver *sdp);
525 void sd_lld_serve_interrupt(SerialDriver *sdp);
526#ifdef __cplusplus
527}
528#endif
529
530#endif /* HAL_USE_SERIAL */
531
532#endif /* HAL_SERIAL_LLD_H */
533
534/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
new file mode 100644
index 000000000..d28bc0e12
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
@@ -0,0 +1,1075 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/hal_uart_lld.c
19 * @brief STM32 low level UART driver code.
20 *
21 * @addtogroup UART
22 * @{
23 */
24
25#include "hal.h"
26
27#if HAL_USE_UART || defined(__DOXYGEN__)
28
29/*===========================================================================*/
30/* Driver local definitions. */
31/*===========================================================================*/
32
33/* For compatibility for those devices without LIN support in the USARTs.*/
34#if !defined(USART_ISR_LBDF)
35#define USART_ISR_LBDF 0
36#endif
37
38#if !defined(USART_CR2_LBDIE)
39#define USART_CR2_LBDIE 0
40#endif
41
42/* STM32L0xx/STM32F7xx ST headers difference.*/
43#if !defined(USART_ISR_LBDF)
44#define USART_ISR_LBDF USART_ISR_LBD
45#endif
46
47/* STM32L0xx/STM32F7xx ST headers difference.*/
48#if !defined(USART_ISR_LBDF)
49#define USART_ISR_LBDF USART_ISR_LBD
50#endif
51
52#define USART1_RX_DMA_CHANNEL \
53 STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM, \
54 STM32_USART1_RX_DMA_CHN)
55
56#define USART1_TX_DMA_CHANNEL \
57 STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM, \
58 STM32_USART1_TX_DMA_CHN)
59
60#define USART2_RX_DMA_CHANNEL \
61 STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM, \
62 STM32_USART2_RX_DMA_CHN)
63
64#define USART2_TX_DMA_CHANNEL \
65 STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM, \
66 STM32_USART2_TX_DMA_CHN)
67
68#define USART3_RX_DMA_CHANNEL \
69 STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM, \
70 STM32_USART3_RX_DMA_CHN)
71
72#define USART3_TX_DMA_CHANNEL \
73 STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \
74 STM32_USART3_TX_DMA_CHN)
75
76#define UART4_RX_DMA_CHANNEL \
77 STM32_DMA_GETCHANNEL(STM32_UART_UART4_RX_DMA_STREAM, \
78 STM32_UART4_RX_DMA_CHN)
79
80#define UART4_TX_DMA_CHANNEL \
81 STM32_DMA_GETCHANNEL(STM32_UART_UART4_TX_DMA_STREAM, \
82 STM32_UART4_TX_DMA_CHN)
83
84#define UART5_RX_DMA_CHANNEL \
85 STM32_DMA_GETCHANNEL(STM32_UART_UART5_RX_DMA_STREAM, \
86 STM32_UART5_RX_DMA_CHN)
87
88#define UART5_TX_DMA_CHANNEL \
89 STM32_DMA_GETCHANNEL(STM32_UART_UART5_TX_DMA_STREAM, \
90 STM32_UART5_TX_DMA_CHN)
91
92#define USART6_RX_DMA_CHANNEL \
93 STM32_DMA_GETCHANNEL(STM32_UART_USART6_RX_DMA_STREAM, \
94 STM32_USART6_RX_DMA_CHN)
95
96#define USART6_TX_DMA_CHANNEL \
97 STM32_DMA_GETCHANNEL(STM32_UART_USART6_TX_DMA_STREAM, \
98 STM32_USART6_TX_DMA_CHN)
99
100#define UART7_RX_DMA_CHANNEL \
101 STM32_DMA_GETCHANNEL(STM32_UART_UART7_RX_DMA_STREAM, \
102 STM32_UART7_RX_DMA_CHN)
103
104#define UART7_TX_DMA_CHANNEL \
105 STM32_DMA_GETCHANNEL(STM32_UART_UART7_TX_DMA_STREAM, \
106 STM32_UART7_TX_DMA_CHN)
107
108#define UART8_RX_DMA_CHANNEL \
109 STM32_DMA_GETCHANNEL(STM32_UART_UART8_RX_DMA_STREAM, \
110 STM32_UART8_RX_DMA_CHN)
111
112#define UART8_TX_DMA_CHANNEL \
113 STM32_DMA_GETCHANNEL(STM32_UART_UART8_TX_DMA_STREAM, \
114 STM32_UART8_TX_DMA_CHN)
115
116/* Workarounds for those devices where UARTs are USARTs.*/
117#if defined(USART4)
118#define UART4 USART4
119#endif
120#if defined(USART5)
121#define UART5 USART5
122#endif
123#if defined(USART7)
124#define UART7 USART7
125#endif
126#if defined(USART8)
127#define UART8 USART8
128#endif
129
130/* Workaround for more differences in headers.*/
131#if !defined(USART_CR1_M0)
132#define USART_CR1_M0 USART_CR1_M
133#endif
134
135/*===========================================================================*/
136/* Driver exported variables. */
137/*===========================================================================*/
138
139/** @brief USART1 UART driver identifier.*/
140#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
141UARTDriver UARTD1;
142#endif
143
144/** @brief USART2 UART driver identifier.*/
145#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
146UARTDriver UARTD2;
147#endif
148
149/** @brief USART3 UART driver identifier.*/
150#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
151UARTDriver UARTD3;
152#endif
153
154/** @brief UART4 UART driver identifier.*/
155#if STM32_UART_USE_UART4 || defined(__DOXYGEN__)
156UARTDriver UARTD4;
157#endif
158
159/** @brief UART5 UART driver identifier.*/
160#if STM32_UART_USE_UART5 || defined(__DOXYGEN__)
161UARTDriver UARTD5;
162#endif
163
164/** @brief USART6 UART driver identifier.*/
165#if STM32_UART_USE_USART6 || defined(__DOXYGEN__)
166UARTDriver UARTD6;
167#endif
168
169/** @brief UART7 UART driver identifier.*/
170#if STM32_UART_USE_UART7 || defined(__DOXYGEN__)
171UARTDriver UARTD7;
172#endif
173
174/** @brief UART8 UART driver identifier.*/
175#if STM32_UART_USE_UART8 || defined(__DOXYGEN__)
176UARTDriver UARTD8;
177#endif
178
179/*===========================================================================*/
180/* Driver local variables and types. */
181/*===========================================================================*/
182
183/*===========================================================================*/
184/* Driver local functions. */
185/*===========================================================================*/
186
187/**
188 * @brief Status bits translation.
189 *
190 * @param[in] isr USART SR register value
191 *
192 * @return The error flags.
193 */
194static uartflags_t translate_errors(uint32_t isr) {
195 uartflags_t sts = 0;
196
197 if (isr & USART_ISR_ORE)
198 sts |= UART_OVERRUN_ERROR;
199 if (isr & USART_ISR_PE)
200 sts |= UART_PARITY_ERROR;
201 if (isr & USART_ISR_FE)
202 sts |= UART_FRAMING_ERROR;
203 if (isr & USART_ISR_NE)
204 sts |= UART_NOISE_ERROR;
205 if (isr & USART_ISR_LBDF)
206 sts |= UART_BREAK_DETECTED;
207 return sts;
208}
209
210/**
211 * @brief Puts the receiver in the UART_RX_IDLE state.
212 *
213 * @param[in] uartp pointer to the @p UARTDriver object
214 */
215static void uart_enter_rx_idle_loop(UARTDriver *uartp) {
216 uint32_t mode;
217
218 /* RX DMA channel preparation, if the char callback is defined then the
219 TCIE interrupt is enabled too.*/
220 if (uartp->config->rxchar_cb == NULL)
221 mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC;
222 else
223 mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE;
224 dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf);
225 dmaStreamSetTransactionSize(uartp->dmarx, 1);
226 dmaStreamSetMode(uartp->dmarx, uartp->dmarxmode | mode);
227 dmaStreamEnable(uartp->dmarx);
228}
229
230/**
231 * @brief USART de-initialization.
232 * @details This function must be invoked with interrupts disabled.
233 *
234 * @param[in] uartp pointer to the @p UARTDriver object
235 */
236static void usart_stop(UARTDriver *uartp) {
237
238 /* Stops RX and TX DMA channels.*/
239 dmaStreamDisable(uartp->dmarx);
240 dmaStreamDisable(uartp->dmatx);
241
242 /* Stops USART operations.*/
243 uartp->usart->CR1 = 0;
244 uartp->usart->CR2 = 0;
245 uartp->usart->CR3 = 0;
246}
247
248/**
249 * @brief USART initialization.
250 * @details This function must be invoked with interrupts disabled.
251 *
252 * @param[in] uartp pointer to the @p UARTDriver object
253 */
254static void usart_start(UARTDriver *uartp) {
255 uint32_t fck;
256 uint32_t cr1;
257 const uint32_t tmo = uartp->config->timeout;
258 USART_TypeDef *u = uartp->usart;
259
260 /* Defensive programming, starting from a clean state.*/
261 usart_stop(uartp);
262
263 /* Baud rate setting.*/
264 fck = (uint32_t)(uartp->clock / uartp->config->speed);
265
266 /* Correcting USARTDIV when oversampling by 8 instead of 16.
267 Fraction is still 4 bits wide, but only lower 3 bits used.
268 Mantissa is doubled, but Fraction is left the same.*/
269 if (uartp->config->cr1 & USART_CR1_OVER8)
270 fck = ((fck & ~7) * 2) | (fck & 7);
271 u->BRR = fck;
272
273 /* Resetting eventual pending status flags.*/
274 u->ICR = 0xFFFFFFFFU;
275
276 /* Note that some bits are enforced because required for correct driver
277 operations.*/
278 u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE;
279 u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR |
280 USART_CR3_EIE;
281
282 /* Mustn't ever set TCIE here - if done, it causes an immediate
283 interrupt.*/
284 cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE;
285 u->CR1 = uartp->config->cr1 | cr1;
286
287 /* Set receive timeout and checks if it is really applied.*/
288 if (tmo > 0) {
289 osalDbgAssert(tmo <= USART_RTOR_RTO, "Timeout overflow");
290 u->RTOR = tmo;
291 osalDbgAssert(tmo == u->RTOR, "Timeout feature unsupported in this UART");
292 }
293
294 /* Starting the receiver idle loop.*/
295 uart_enter_rx_idle_loop(uartp);
296}
297
298/**
299 * @brief RX DMA common service routine.
300 *
301 * @param[in] uartp pointer to the @p UARTDriver object
302 * @param[in] flags pre-shifted content of the ISR register
303 */
304static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
305
306 /* DMA errors handling.*/
307#if defined(STM32_UART_DMA_ERROR_HOOK)
308 if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
309 STM32_UART_DMA_ERROR_HOOK(uartp);
310 }
311#else
312 (void)flags;
313#endif
314
315 if (uartp->rxstate == UART_RX_IDLE) {
316 /* Receiver in idle state, a callback is generated, if enabled, for each
317 received character and then the driver stays in the same state.*/
318 _uart_rx_idle_code(uartp);
319 }
320 else {
321 /* Receiver in active state, a callback is generated, if enabled, after
322 a completed transfer.*/
323 dmaStreamDisable(uartp->dmarx);
324 _uart_rx_complete_isr_code(uartp);
325 }
326}
327
328/**
329 * @brief TX DMA common service routine.
330 *
331 * @param[in] uartp pointer to the @p UARTDriver object
332 * @param[in] flags pre-shifted content of the ISR register
333 */
334static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
335
336 /* DMA errors handling.*/
337#if defined(STM32_UART_DMA_ERROR_HOOK)
338 if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
339 STM32_UART_DMA_ERROR_HOOK(uartp);
340 }
341#else
342 (void)flags;
343#endif
344
345 dmaStreamDisable(uartp->dmatx);
346
347 /* A callback is generated, if enabled, after a completed transfer.*/
348 _uart_tx1_isr_code(uartp);
349}
350
351/*===========================================================================*/
352/* Driver interrupt handlers. */
353/*===========================================================================*/
354
355#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
356#if !defined(STM32_USART1_SUPPRESS_ISR)
357#if !defined(STM32_USART1_HANDLER)
358#error "STM32_USART1_HANDLER not defined"
359#endif
360/**
361 * @brief USART1 IRQ handler.
362 *
363 * @isr
364 */
365OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
366
367 OSAL_IRQ_PROLOGUE();
368
369 uart_lld_serve_interrupt(&UARTD1);
370
371 OSAL_IRQ_EPILOGUE();
372}
373#endif
374#endif
375
376#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
377#if !defined(STM32_USART2_SUPPRESS_ISR)
378#if !defined(STM32_USART2_HANDLER)
379#error "STM32_USART2_HANDLER not defined"
380#endif
381/**
382 * @brief USART2 IRQ handler.
383 *
384 * @isr
385 */
386OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
387
388 OSAL_IRQ_PROLOGUE();
389
390 uart_lld_serve_interrupt(&UARTD2);
391
392 OSAL_IRQ_EPILOGUE();
393}
394#endif
395#endif
396
397#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
398#if !defined(STM32_USART3_SUPPRESS_ISR)
399#if !defined(STM32_USART3_HANDLER)
400#error "STM32_USART3_HANDLER not defined"
401#endif
402/**
403 * @brief USART3 IRQ handler.
404 *
405 * @isr
406 */
407OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) {
408
409 OSAL_IRQ_PROLOGUE();
410
411 uart_lld_serve_interrupt(&UARTD3);
412
413 OSAL_IRQ_EPILOGUE();
414}
415#endif
416#endif
417
418#if STM32_UART_USE_UART4 || defined(__DOXYGEN__)
419#if !defined(STM32_UART4_SUPPRESS_ISR)
420#if !defined(STM32_UART4_HANDLER)
421#error "STM32_UART4_HANDLER not defined"
422#endif
423/**
424 * @brief UART4 IRQ handler.
425 *
426 * @isr
427 */
428OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) {
429
430 OSAL_IRQ_PROLOGUE();
431
432 uart_lld_serve_interrupt(&UARTD4);
433
434 OSAL_IRQ_EPILOGUE();
435}
436#endif
437#endif
438
439#if STM32_UART_USE_UART5 || defined(__DOXYGEN__)
440#if !defined(STM32_UART5_SUPPRESS_ISR)
441#if !defined(STM32_UART5_HANDLER)
442#error "STM32_UART5_HANDLER not defined"
443#endif
444/**
445 * @brief UART5 IRQ handler.
446 *
447 * @isr
448 */
449OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) {
450
451 OSAL_IRQ_PROLOGUE();
452
453 uart_lld_serve_interrupt(&UARTD5);
454
455 OSAL_IRQ_EPILOGUE();
456}
457#endif
458#endif
459
460#if STM32_UART_USE_USART6 || defined(__DOXYGEN__)
461#if !defined(STM32_USART6_SUPPRESS_ISR)
462#if !defined(STM32_USART6_HANDLER)
463#error "STM32_USART6_HANDLER not defined"
464#endif
465/**
466 * @brief USART6 IRQ handler.
467 *
468 * @isr
469 */
470OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) {
471
472 OSAL_IRQ_PROLOGUE();
473
474 uart_lld_serve_interrupt(&UARTD6);
475
476 OSAL_IRQ_EPILOGUE();
477}
478#endif
479#endif
480
481#if STM32_UART_USE_UART7 || defined(__DOXYGEN__)
482#if !defined(STM32_UART7_SUPPRESS_ISR)
483#if !defined(STM32_UART7_HANDLER)
484#error "STM32_UART7_HANDLER not defined"
485#endif
486/**
487 * @brief UART7 IRQ handler.
488 *
489 * @isr
490 */
491OSAL_IRQ_HANDLER(STM32_UART7_HANDLER) {
492
493 OSAL_IRQ_PROLOGUE();
494
495 uart_lld_serve_interrupt(&UARTD7);
496
497 OSAL_IRQ_EPILOGUE();
498}
499#endif
500#endif
501
502#if STM32_UART_USE_UART8 || defined(__DOXYGEN__)
503#if !defined(STM32_UART8_SUPPRESS_ISR)
504#if !defined(STM32_UART8_HANDLER)
505#error "STM32_UART8_HANDLER not defined"
506#endif
507/**
508 * @brief UART8 IRQ handler.
509 *
510 * @isr
511 */
512OSAL_IRQ_HANDLER(STM32_UART8_HANDLER) {
513
514 OSAL_IRQ_PROLOGUE();
515
516 uart_lld_serve_interrupt(&UARTD8);
517
518 OSAL_IRQ_EPILOGUE();
519}
520#endif
521#endif
522
523/*===========================================================================*/
524/* Driver exported functions. */
525/*===========================================================================*/
526
527/**
528 * @brief Low level UART driver initialization.
529 *
530 * @notapi
531 */
532void uart_lld_init(void) {
533
534#if STM32_UART_USE_USART1
535 uartObjectInit(&UARTD1);
536 UARTD1.usart = USART1;
537 UARTD1.clock = STM32_USART1CLK;
538 UARTD1.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
539 UARTD1.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
540 UARTD1.dmarx = NULL;
541 UARTD1.dmatx = NULL;
542#if !defined(STM32_USART1_SUPPRESS_ISR) && defined(STM32_USART1_NUMBER)
543 nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY);
544#endif
545#endif
546
547#if STM32_UART_USE_USART2
548 uartObjectInit(&UARTD2);
549 UARTD2.usart = USART2;
550 UARTD2.clock = STM32_USART2CLK;
551 UARTD2.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
552 UARTD2.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
553 UARTD2.dmarx = NULL;
554 UARTD2.dmatx = NULL;
555#if !defined(STM32_USART2_SUPPRESS_ISR) && defined(STM32_USART2_NUMBER)
556 nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY);
557#endif
558#endif
559
560#if STM32_UART_USE_USART3
561 uartObjectInit(&UARTD3);
562 UARTD3.usart = USART3;
563 UARTD3.clock = STM32_USART3CLK;
564 UARTD3.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
565 UARTD3.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
566 UARTD3.dmarx = NULL;
567 UARTD3.dmatx = NULL;
568#if !defined(STM32_USART3_SUPPRESS_ISR) && defined(STM32_USART3_NUMBER)
569 nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY);
570#endif
571#endif
572
573#if STM32_UART_USE_UART4
574 uartObjectInit(&UARTD4);
575 UARTD4.usart = UART4;
576 UARTD4.clock = STM32_UART4CLK;
577 UARTD4.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
578 UARTD4.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
579 UARTD4.dmarx = NULL;
580 UARTD4.dmatx = NULL;
581#if !defined(STM32_UART4_SUPPRESS_ISR) && defined(STM32_UART4_NUMBER)
582 nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY);
583#endif
584#endif
585
586#if STM32_UART_USE_UART5
587 uartObjectInit(&UARTD5);
588 UARTD5.usart = UART5;
589 UARTD5.clock = STM32_UART5CLK;
590 UARTD5.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
591 UARTD5.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
592 UARTD5.dmarx = NULL;
593 UARTD5.dmatx = NULL;
594#if !defined(STM32_UART5_SUPPRESS_ISR) && defined(STM32_UART5_NUMBER)
595 nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY);
596#endif
597#endif
598
599#if STM32_UART_USE_USART6
600 uartObjectInit(&UARTD6);
601 UARTD6.usart = USART6;
602 UARTD6.clock = STM32_USART6CLK;
603 UARTD6.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
604 UARTD6.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
605 UARTD6.dmarx = NULL;
606 UARTD6.dmatx = NULL;
607#if !defined(STM32_USART6_SUPPRESS_ISR) && defined(STM32_USART6_NUMBER)
608 nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY);
609#endif
610#endif
611
612#if STM32_UART_USE_UART7
613 uartObjectInit(&UARTD7);
614 UARTD7.usart = UART7;
615 UARTD7.clock = STM32_UART7CLK;
616 UARTD7.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
617 UARTD7.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
618 UARTD7.dmarx = NULL;
619 UARTD7.dmatx = NULL;
620#if !defined(STM32_UART7_SUPPRESS_ISR) && defined(STM32_UART7_NUMBER)
621 nvicEnableVector(STM32_UART7_NUMBER, STM32_UART_UART7_IRQ_PRIORITY);
622#endif
623#endif
624
625#if STM32_UART_USE_UART8
626 uartObjectInit(&UARTD8);
627 UARTD8.usart = UART8;
628 UARTD8.clock = STM32_UART8CLK;
629 UARTD8.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
630 UARTD8.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
631 UARTD8.dmarx = NULL;
632 UARTD8.dmatx = NULL;
633#if !defined(STM32_UART8_SUPPRESS_ISR) && defined(STM32_UART8_NUMBER)
634 nvicEnableVector(STM32_UART8_NUMBER, STM32_UART_UART8_IRQ_PRIORITY);
635#endif
636#endif
637}
638
639/**
640 * @brief Configures and activates the UART peripheral.
641 *
642 * @param[in] uartp pointer to the @p UARTDriver object
643 *
644 * @notapi
645 */
646void uart_lld_start(UARTDriver *uartp) {
647
648 if (uartp->state == UART_STOP) {
649#if STM32_UART_USE_USART1
650 if (&UARTD1 == uartp) {
651 uartp->dmarx = dmaStreamAllocI(STM32_UART_USART1_RX_DMA_STREAM,
652 STM32_UART_USART1_IRQ_PRIORITY,
653 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
654 (void *)uartp);
655 osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
656 uartp->dmatx = dmaStreamAllocI(STM32_UART_USART1_TX_DMA_STREAM,
657 STM32_UART_USART1_IRQ_PRIORITY,
658 (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
659 (void *)uartp);
660 osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
661
662 rccEnableUSART1(true);
663 uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
664 STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
665 uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART1_TX_DMA_CHANNEL) |
666 STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
667#if STM32_DMA_SUPPORTS_DMAMUX
668 dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_USART1_RX);
669 dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_USART1_TX);
670#endif
671 }
672#endif
673
674#if STM32_UART_USE_USART2
675 if (&UARTD2 == uartp) {
676 uartp->dmarx = dmaStreamAllocI(STM32_UART_USART2_RX_DMA_STREAM,
677 STM32_UART_USART2_IRQ_PRIORITY,
678 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
679 (void *)uartp);
680 osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
681 uartp->dmatx = dmaStreamAllocI(STM32_UART_USART2_TX_DMA_STREAM,
682 STM32_UART_USART2_IRQ_PRIORITY,
683 (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
684 (void *)uartp);
685 osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
686
687 rccEnableUSART2(true);
688 uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
689 STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
690 uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART2_TX_DMA_CHANNEL) |
691 STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
692#if STM32_DMA_SUPPORTS_DMAMUX
693 dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_USART2_RX);
694 dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_USART2_TX);
695#endif
696 }
697#endif
698
699#if STM32_UART_USE_USART3
700 if (&UARTD3 == uartp) {
701 uartp->dmarx = dmaStreamAllocI(STM32_UART_USART3_RX_DMA_STREAM,
702 STM32_UART_USART3_IRQ_PRIORITY,
703 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
704 (void *)uartp);
705 osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
706 uartp->dmatx = dmaStreamAllocI(STM32_UART_USART3_TX_DMA_STREAM,
707 STM32_UART_USART3_IRQ_PRIORITY,
708 (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
709 (void *)uartp);
710 osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
711
712 rccEnableUSART3(true);
713 uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
714 STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
715 uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART3_TX_DMA_CHANNEL) |
716 STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
717#if STM32_DMA_SUPPORTS_DMAMUX
718 dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_USART3_RX);
719 dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_USART3_TX);
720#endif
721 }
722#endif
723
724#if STM32_UART_USE_UART4
725 if (&UARTD4 == uartp) {
726 uartp->dmarx = dmaStreamAllocI(STM32_UART_UART4_RX_DMA_STREAM,
727 STM32_UART_UART4_IRQ_PRIORITY,
728 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
729 (void *)uartp);
730 osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
731 uartp->dmatx = dmaStreamAllocI(STM32_UART_UART4_TX_DMA_STREAM,
732 STM32_UART_UART4_IRQ_PRIORITY,
733 (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
734 (void *)uartp);
735 osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
736
737 rccEnableUART4(true);
738 uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) |
739 STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY);
740 uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART4_TX_DMA_CHANNEL) |
741 STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY);
742#if STM32_DMA_SUPPORTS_DMAMUX
743 dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_UART4_RX);
744 dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_UART4_TX);
745#endif
746 }
747#endif
748
749#if STM32_UART_USE_UART5
750 if (&UARTD5 == uartp) {
751 uartp->dmarx = dmaStreamAllocI(STM32_UART_UART5_RX_DMA_STREAM,
752 STM32_UART_UART5_IRQ_PRIORITY,
753 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
754 (void *)uartp);
755 osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
756 uartp->dmatx = dmaStreamAllocI(STM32_UART_UART5_TX_DMA_STREAM,
757 STM32_UART_UART5_IRQ_PRIORITY,
758 (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
759 (void *)uartp);
760 osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
761
762 rccEnableUART5(true);
763 uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) |
764 STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY);
765 uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART5_TX_DMA_CHANNEL) |
766 STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY);
767#if STM32_DMA_SUPPORTS_DMAMUX
768 dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_UART5_RX);
769 dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_UART5_TX);
770#endif
771 }
772#endif
773
774#if STM32_UART_USE_USART6
775 if (&UARTD6 == uartp) {
776 uartp->dmarx = dmaStreamAllocI(STM32_UART_USART6_RX_DMA_STREAM,
777 STM32_UART_USART6_IRQ_PRIORITY,
778 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
779 (void *)uartp);
780 osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
781 uartp->dmatx = dmaStreamAllocI(STM32_UART_USART6_TX_DMA_STREAM,
782 STM32_UART_USART6_IRQ_PRIORITY,
783 (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
784 (void *)uartp);
785 osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
786
787 rccEnableUSART6(true);
788 uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) |
789 STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY);
790 uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART6_TX_DMA_CHANNEL) |
791 STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY);
792#if STM32_DMA_SUPPORTS_DMAMUX
793 dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_USART6_RX);
794 dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_USART6_TX);
795#endif
796 }
797#endif
798
799#if STM32_UART_USE_UART7
800 if (&UARTD7 == uartp) {
801 uartp->dmarx = dmaStreamAllocI(STM32_UART_UART7_RX_DMA_STREAM,
802 STM32_UART_UART7_IRQ_PRIORITY,
803 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
804 (void *)uartp);
805 osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
806 uartp->dmatx = dmaStreamAllocI(STM32_UART_UART7_TX_DMA_STREAM,
807 STM32_UART_UART7_IRQ_PRIORITY,
808 (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
809 (void *)uartp);
810 osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
811
812 rccEnableUART7(true);
813 uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) |
814 STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY);
815 uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART7_TX_DMA_CHANNEL) |
816 STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY);
817#if STM32_DMA_SUPPORTS_DMAMUX
818 dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_UART7_RX);
819 dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_UART7_TX);
820#endif
821 }
822#endif
823
824#if STM32_UART_USE_UART8
825 if (&UARTD8 == uartp) {
826 uartp->dmarx = dmaStreamAllocI(STM32_UART_UART8_RX_DMA_STREAM,
827 STM32_UART_UART8_IRQ_PRIORITY,
828 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
829 (void *)uartp);
830 osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
831 uartp->dmatx = dmaStreamAllocI(STM32_UART_UART8_TX_DMA_STREAM,
832 STM32_UART_UART8_IRQ_PRIORITY,
833 (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
834 (void *)uartp);
835 osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
836
837 rccEnableUART8(true);
838 uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) |
839 STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY);
840 uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART8_TX_DMA_CHANNEL) |
841 STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY);
842#if STM32_DMA_SUPPORTS_DMAMUX
843 dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_UART8_RX);
844 dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_UART8_TX);
845#endif
846 }
847#endif
848
849 /* Static DMA setup, the transfer size depends on the USART settings,
850 it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
851 if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M0) {
852 uartp->dmarxmode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
853 uartp->dmatxmode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
854 }
855 dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR);
856 dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR);
857 uartp->rxbuf = 0;
858 }
859
860 uartp->rxstate = UART_RX_IDLE;
861 uartp->txstate = UART_TX_IDLE;
862 usart_start(uartp);
863}
864
865/**
866 * @brief Deactivates the UART peripheral.
867 *
868 * @param[in] uartp pointer to the @p UARTDriver object
869 *
870 * @notapi
871 */
872void uart_lld_stop(UARTDriver *uartp) {
873
874 if (uartp->state == UART_READY) {
875 usart_stop(uartp);
876 dmaStreamFreeI(uartp->dmarx);
877 dmaStreamFreeI(uartp->dmatx);
878 uartp->dmarx = NULL;
879 uartp->dmatx = NULL;
880
881#if STM32_UART_USE_USART1
882 if (&UARTD1 == uartp) {
883 rccDisableUSART1();
884 return;
885 }
886#endif
887
888#if STM32_UART_USE_USART2
889 if (&UARTD2 == uartp) {
890 rccDisableUSART2();
891 return;
892 }
893#endif
894
895#if STM32_UART_USE_USART3
896 if (&UARTD3 == uartp) {
897 rccDisableUSART3();
898 return;
899 }
900#endif
901
902#if STM32_UART_USE_UART4
903 if (&UARTD4 == uartp) {
904 rccDisableUART4();
905 return;
906 }
907#endif
908
909#if STM32_UART_USE_UART5
910 if (&UARTD5 == uartp) {
911 rccDisableUART5();
912 return;
913 }
914#endif
915
916#if STM32_UART_USE_USART6
917 if (&UARTD6 == uartp) {
918 rccDisableUSART6();
919 return;
920 }
921#endif
922
923#if STM32_UART_USE_UART7
924 if (&UARTD7 == uartp) {
925 rccDisableUART7();
926 return;
927 }
928#endif
929
930#if STM32_UART_USE_UART8
931 if (&UARTD8 == uartp) {
932 rccDisableUART8();
933 return;
934 }
935#endif
936 }
937}
938
939/**
940 * @brief Starts a transmission on the UART peripheral.
941 * @note The buffers are organized as uint8_t arrays for data sizes below
942 * or equal to 8 bits else it is organized as uint16_t arrays.
943 *
944 * @param[in] uartp pointer to the @p UARTDriver object
945 * @param[in] n number of data frames to send
946 * @param[in] txbuf the pointer to the transmit buffer
947 *
948 * @notapi
949 */
950void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
951
952 /* TX DMA channel preparation.*/
953 dmaStreamSetMemory0(uartp->dmatx, txbuf);
954 dmaStreamSetTransactionSize(uartp->dmatx, n);
955 dmaStreamSetMode(uartp->dmatx, uartp->dmatxmode | STM32_DMA_CR_DIR_M2P |
956 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
957
958 /* Only enable TC interrupt if there's a callback attached to it or
959 if called from uartSendFullTimeout(). Also we need to clear TC flag
960 which could be set before.*/
961#if UART_USE_WAIT == TRUE
962 if ((uartp->config->txend2_cb != NULL) || (uartp->early == false)) {
963#else
964 if (uartp->config->txend2_cb != NULL) {
965#endif
966 uartp->usart->ICR = USART_ICR_TCCF;
967 uartp->usart->CR1 |= USART_CR1_TCIE;
968 }
969
970 /* Starting transfer.*/
971 dmaStreamEnable(uartp->dmatx);
972}
973
974/**
975 * @brief Stops any ongoing transmission.
976 * @note Stopping a transmission also suppresses the transmission callbacks.
977 *
978 * @param[in] uartp pointer to the @p UARTDriver object
979 *
980 * @return The number of data frames not transmitted by the
981 * stopped transmit operation.
982 *
983 * @notapi
984 */
985size_t uart_lld_stop_send(UARTDriver *uartp) {
986
987 dmaStreamDisable(uartp->dmatx);
988
989 return dmaStreamGetTransactionSize(uartp->dmatx);
990}
991
992/**
993 * @brief Starts a receive operation on the UART peripheral.
994 * @note The buffers are organized as uint8_t arrays for data sizes below
995 * or equal to 8 bits else it is organized as uint16_t arrays.
996 *
997 * @param[in] uartp pointer to the @p UARTDriver object
998 * @param[in] n number of data frames to send
999 * @param[out] rxbuf the pointer to the receive buffer
1000 *
1001 * @notapi
1002 */
1003void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
1004
1005 /* Stopping previous activity (idle state).*/
1006 dmaStreamDisable(uartp->dmarx);
1007
1008 /* RX DMA channel preparation.*/
1009 dmaStreamSetMemory0(uartp->dmarx, rxbuf);
1010 dmaStreamSetTransactionSize(uartp->dmarx, n);
1011 dmaStreamSetMode(uartp->dmarx, uartp->dmarxmode | STM32_DMA_CR_DIR_P2M |
1012 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
1013
1014 /* Starting transfer.*/
1015 dmaStreamEnable(uartp->dmarx);
1016}
1017
1018/**
1019 * @brief Stops any ongoing receive operation.
1020 * @note Stopping a receive operation also suppresses the receive callbacks.
1021 *
1022 * @param[in] uartp pointer to the @p UARTDriver object
1023 *
1024 * @return The number of data frames not received by the
1025 * stopped receive operation.
1026 *
1027 * @notapi
1028 */
1029size_t uart_lld_stop_receive(UARTDriver *uartp) {
1030 size_t n;
1031
1032 dmaStreamDisable(uartp->dmarx);
1033 n = dmaStreamGetTransactionSize(uartp->dmarx);
1034 uart_enter_rx_idle_loop(uartp);
1035
1036 return n;
1037}
1038
1039/**
1040 * @brief USART common service routine.
1041 *
1042 * @param[in] uartp pointer to the @p UARTDriver object
1043 */
1044void uart_lld_serve_interrupt(UARTDriver *uartp) {
1045 uint32_t isr;
1046 USART_TypeDef *u = uartp->usart;
1047 uint32_t cr1 = u->CR1;
1048
1049 /* Reading and clearing status.*/
1050 isr = u->ISR;
1051 u->ICR = isr;
1052
1053 if (isr & (USART_ISR_LBDF | USART_ISR_ORE | USART_ISR_NE |
1054 USART_ISR_FE | USART_ISR_PE)) {
1055 _uart_rx_error_isr_code(uartp, translate_errors(isr));
1056 }
1057
1058 if ((isr & USART_ISR_TC) && (cr1 & USART_CR1_TCIE)) {
1059 /* TC interrupt disabled.*/
1060 u->CR1 = cr1 & ~USART_CR1_TCIE;
1061
1062 /* End of transmission, a callback is generated.*/
1063 _uart_tx2_isr_code(uartp);
1064 }
1065
1066 /* Timeout interrupt sources are only checked if enabled in CR1.*/
1067 if (((cr1 & USART_CR1_IDLEIE) && (isr & USART_ISR_IDLE)) ||
1068 ((cr1 & USART_CR1_RTOIE) && (isr & USART_ISR_RTOF))) {
1069 _uart_timeout_isr_code(uartp);
1070 }
1071}
1072
1073#endif /* HAL_USE_UART */
1074
1075/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h
new file mode 100644
index 000000000..a68beb90d
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h
@@ -0,0 +1,842 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/hal_uart_lld.h
19 * @brief STM32 low level UART driver header.
20 *
21 * @addtogroup UART
22 * @{
23 */
24
25#ifndef HAL_UART_LLD_H
26#define HAL_UART_LLD_H
27
28#if HAL_USE_UART || defined(__DOXYGEN__)
29
30/*===========================================================================*/
31/* Driver constants. */
32/*===========================================================================*/
33
34/*===========================================================================*/
35/* Driver pre-compile time settings. */
36/*===========================================================================*/
37
38/**
39 * @name Configuration options
40 * @{
41 */
42/**
43 * @brief UART driver on USART1 enable switch.
44 * @details If set to @p TRUE the support for USART1 is included.
45 * @note The default is @p FALSE.
46 */
47#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__)
48#define STM32_UART_USE_USART1 FALSE
49#endif
50
51/**
52 * @brief UART driver on USART2 enable switch.
53 * @details If set to @p TRUE the support for USART2 is included.
54 * @note The default is @p FALSE.
55 */
56#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__)
57#define STM32_UART_USE_USART2 FALSE
58#endif
59
60/**
61 * @brief UART driver on USART3 enable switch.
62 * @details If set to @p TRUE the support for USART3 is included.
63 * @note The default is @p FALSE.
64 */
65#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__)
66#define STM32_UART_USE_USART3 FALSE
67#endif
68
69/**
70 * @brief UART driver on UART4 enable switch.
71 * @details If set to @p TRUE the support for UART4 is included.
72 * @note The default is @p FALSE.
73 */
74#if !defined(STM32_UART_USE_UART4) || defined(__DOXYGEN__)
75#define STM32_UART_USE_UART4 FALSE
76#endif
77
78/**
79 * @brief UART driver on UART5 enable switch.
80 * @details If set to @p TRUE the support for UART5 is included.
81 * @note The default is @p FALSE.
82 */
83#if !defined(STM32_UART_USE_UART5) || defined(__DOXYGEN__)
84#define STM32_UART_USE_UART5 FALSE
85#endif
86
87/**
88 * @brief UART driver on USART6 enable switch.
89 * @details If set to @p TRUE the support for USART6 is included.
90 * @note The default is @p FALSE.
91 */
92#if !defined(STM32_UART_USE_USART6) || defined(__DOXYGEN__)
93#define STM32_UART_USE_USART6 FALSE
94#endif
95
96/**
97 * @brief UART driver on UART7 enable switch.
98 * @details If set to @p TRUE the support for UART7 is included.
99 * @note The default is @p FALSE.
100 */
101#if !defined(STM32_UART_USE_UART7) || defined(__DOXYGEN__)
102#define STM32_UART_USE_UART7 FALSE
103#endif
104
105/**
106 * @brief UART driver on UART8 enable switch.
107 * @details If set to @p TRUE the support for UART8 is included.
108 * @note The default is @p FALSE.
109 */
110#if !defined(STM32_UART_USE_UART8) || defined(__DOXYGEN__)
111#define STM32_UART_USE_UART8 FALSE
112#endif
113
114/**
115 * @brief USART1 interrupt priority level setting.
116 */
117#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
118#define STM32_UART_USART1_IRQ_PRIORITY 12
119#endif
120
121/**
122 * @brief USART2 interrupt priority level setting.
123 */
124#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
125#define STM32_UART_USART2_IRQ_PRIORITY 12
126#endif
127
128/**
129 * @brief USART3 interrupt priority level setting.
130 */
131#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
132#define STM32_UART_USART3_IRQ_PRIORITY 12
133#endif
134
135/**
136 * @brief UART4 interrupt priority level setting.
137 */
138#if !defined(STM32_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__)
139#define STM32_UART_UART4_IRQ_PRIORITY 12
140#endif
141
142/**
143 * @brief UART5 interrupt priority level setting.
144 */
145#if !defined(STM32_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__)
146#define STM32_UART_UART5_IRQ_PRIORITY 12
147#endif
148
149/**
150 * @brief USART6 interrupt priority level setting.
151 */
152#if !defined(STM32_UART_USART6_IRQ_PRIORITY) || defined(__DOXYGEN__)
153#define STM32_UART_USART6_IRQ_PRIORITY 12
154#endif
155
156/**
157 * @brief UART7 interrupt priority level setting.
158 */
159#if !defined(STM32_UART_UART7_IRQ_PRIORITY) || defined(__DOXYGEN__)
160#define STM32_UART_UART7_IRQ_PRIORITY 12
161#endif
162
163/**
164 * @brief UART8 interrupt priority level setting.
165 */
166#if !defined(STM32_UART_UART8_IRQ_PRIORITY) || defined(__DOXYGEN__)
167#define STM32_UART_UART8_IRQ_PRIORITY 12
168#endif
169
170/**
171 * @brief USART1 DMA priority (0..3|lowest..highest).
172 * @note The priority level is used for both the TX and RX DMA channels but
173 * because of the channels ordering the RX channel has always priority
174 * over the TX channel.
175 */
176#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__)
177#define STM32_UART_USART1_DMA_PRIORITY 0
178#endif
179
180/**
181 * @brief USART2 DMA priority (0..3|lowest..highest).
182 * @note The priority level is used for both the TX and RX DMA channels but
183 * because of the channels ordering the RX channel has always priority
184 * over the TX channel.
185 */
186#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__)
187#define STM32_UART_USART2_DMA_PRIORITY 0
188#endif
189
190/**
191 * @brief USART3 DMA priority (0..3|lowest..highest).
192 * @note The priority level is used for both the TX and RX DMA channels but
193 * because of the channels ordering the RX channel has always priority
194 * over the TX channel.
195 */
196#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__)
197#define STM32_UART_USART3_DMA_PRIORITY 0
198#endif
199
200/**
201 * @brief UART4 DMA priority (0..3|lowest..highest).
202 * @note The priority level is used for both the TX and RX DMA channels but
203 * because of the channels ordering the RX channel has always priority
204 * over the TX channel.
205 */
206#if !defined(STM32_UART_UART4_DMA_PRIORITY) || defined(__DOXYGEN__)
207#define STM32_UART_UART4_DMA_PRIORITY 0
208#endif
209
210/**
211 * @brief UART5 DMA priority (0..3|lowest..highest).
212 * @note The priority level is used for both the TX and RX DMA channels but
213 * because of the channels ordering the RX channel has always priority
214 * over the TX channel.
215 */
216#if !defined(STM32_UART_UART5_DMA_PRIORITY) || defined(__DOXYGEN__)
217#define STM32_UART_UART5_DMA_PRIORITY 0
218#endif
219
220/**
221 * @brief USART6 DMA priority (0..3|lowest..highest).
222 * @note The priority level is used for both the TX and RX DMA channels but
223 * because of the channels ordering the RX channel has always priority
224 * over the TX channel.
225 */
226#if !defined(STM32_UART_USART6_DMA_PRIORITY) || defined(__DOXYGEN__)
227#define STM32_UART_USART6_DMA_PRIORITY 0
228#endif
229
230/**
231 * @brief UART7 DMA priority (0..3|lowest..highest).
232 * @note The priority level is used for both the TX and RX DMA channels but
233 * because of the channels ordering the RX channel has always priority
234 * over the TX channel.
235 */
236#if !defined(STM32_UART_UART7_DMA_PRIORITY) || defined(__DOXYGEN__)
237#define STM32_UART_UART7_DMA_PRIORITY 0
238#endif
239
240/**
241 * @brief UART8 DMA priority (0..3|lowest..highest).
242 * @note The priority level is used for both the TX and RX DMA channels but
243 * because of the channels ordering the RX channel has always priority
244 * over the TX channel.
245 */
246#if !defined(STM32_UART_UART8_DMA_PRIORITY) || defined(__DOXYGEN__)
247#define STM32_UART_UART8_DMA_PRIORITY 0
248#endif
249
250/**
251 * @brief UART DMA error hook.
252 * @note The default action for DMA errors is a system halt because DMA
253 * error can only happen because programming errors.
254 */
255#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
256#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
257#endif
258/** @} */
259
260/*===========================================================================*/
261/* Derived constants and error checks. */
262/*===========================================================================*/
263
264#if STM32_UART_USE_USART1 && !STM32_HAS_USART1
265#error "USART1 not present in the selected device"
266#endif
267
268#if STM32_UART_USE_USART2 && !STM32_HAS_USART2
269#error "USART2 not present in the selected device"
270#endif
271
272#if STM32_UART_USE_USART3 && !STM32_HAS_USART3
273#error "USART3 not present in the selected device"
274#endif
275
276#if STM32_UART_USE_UART4 && !STM32_HAS_UART4
277#error "UART4 not present in the selected device"
278#endif
279
280#if STM32_UART_USE_UART5 && !STM32_HAS_UART5
281#error "UART5 not present in the selected device"
282#endif
283
284#if STM32_UART_USE_UART7 && !STM32_HAS_UART7
285#error "UART7 not present in the selected device"
286#endif
287
288#if STM32_UART_USE_UART8 && !STM32_HAS_UART8
289#error "UART8 not present in the selected device"
290#endif
291
292#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \
293 !STM32_UART_USE_USART3 && !STM32_UART_USE_UART4 && \
294 !STM32_UART_USE_UART5 && !STM32_UART_USE_USART6 && \
295 !STM32_UART_USE_UART7 && !STM32_UART_USE_UART8
296#error "UART driver activated but no USART/UART peripheral assigned"
297#endif
298
299#if !defined(STM32_USART1_SUPPRESS_ISR) && \
300 STM32_UART_USE_USART1 && \
301 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY)
302#error "Invalid IRQ priority assigned to USART1"
303#endif
304
305#if !defined(STM32_USART2_SUPPRESS_ISR) && \
306 STM32_UART_USE_USART2 && \
307 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY)
308#error "Invalid IRQ priority assigned to USART2"
309#endif
310
311#if !defined(STM32_USART3_SUPPRESS_ISR) && \
312 STM32_UART_USE_USART3 && \
313 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY)
314#error "Invalid IRQ priority assigned to USART3"
315#endif
316
317#if !defined(STM32_UART4_SUPPRESS_ISR) && \
318 STM32_UART_USE_UART4 && \
319 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART4_IRQ_PRIORITY)
320#error "Invalid IRQ priority assigned to UART4"
321#endif
322
323#if !defined(STM32_UART5_SUPPRESS_ISR) && \
324 STM32_UART_USE_UART5 && \
325 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART5_IRQ_PRIORITY)
326#error "Invalid IRQ priority assigned to UART5"
327#endif
328
329#if !defined(STM32_USART6_SUPPRESS_ISR) && \
330 STM32_UART_USE_USART6 && \
331 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART6_IRQ_PRIORITY)
332#error "Invalid IRQ priority assigned to USART6"
333#endif
334
335#if !defined(STM32_UART7_SUPPRESS_ISR) && \
336 STM32_UART_USE_UART7 && \
337 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART7_IRQ_PRIORITY)
338#error "Invalid IRQ priority assigned to UART7"
339#endif
340
341#if !defined(STM32_UART8_SUPPRESS_ISR) && \
342 STM32_UART_USE_UART8 && \
343 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART8_IRQ_PRIORITY)
344#error "Invalid IRQ priority assigned to UART8"
345#endif
346
347/* Check on DMA priorities.*/
348#if STM32_UART_USE_USART1 && \
349 !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY)
350#error "Invalid DMA priority assigned to USART1"
351#endif
352
353#if STM32_UART_USE_USART2 && \
354 !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY)
355#error "Invalid DMA priority assigned to USART2"
356#endif
357
358#if STM32_UART_USE_USART3 && \
359 !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY)
360#error "Invalid DMA priority assigned to USART3"
361#endif
362
363#if STM32_UART_USE_UART4 && \
364 !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART4_DMA_PRIORITY)
365#error "Invalid DMA priority assigned to UART4"
366#endif
367
368#if STM32_UART_USE_UART5 && \
369 !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART5_DMA_PRIORITY)
370#error "Invalid DMA priority assigned to UART5"
371#endif
372
373#if STM32_UART_USE_USART6 && \
374 !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART6_DMA_PRIORITY)
375#error "Invalid DMA priority assigned to USART6"
376#endif
377
378#if STM32_UART_USE_UART7 && \
379 !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART7_DMA_PRIORITY)
380#error "Invalid DMA priority assigned to UART7"
381#endif
382
383#if STM32_UART_USE_UART8 && \
384 !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART8_DMA_PRIORITY)
385#error "Invalid DMA priority assigned to UART8"
386#endif
387
388/* Check on the presence of the DMA streams settings in mcuconf.h.*/
389#if STM32_UART_USE_USART1 && (!defined(STM32_UART_USART1_RX_DMA_STREAM) || \
390 !defined(STM32_UART_USART1_TX_DMA_STREAM))
391#error "USART1 DMA streams not defined"
392#endif
393
394#if STM32_UART_USE_USART2 && (!defined(STM32_UART_USART2_RX_DMA_STREAM) || \
395 !defined(STM32_UART_USART2_TX_DMA_STREAM))
396#error "USART2 DMA streams not defined"
397#endif
398
399#if STM32_UART_USE_USART3 && (!defined(STM32_UART_USART3_RX_DMA_STREAM) || \
400 !defined(STM32_UART_USART3_TX_DMA_STREAM))
401#error "USART3 DMA streams not defined"
402#endif
403
404#if STM32_UART_USE_UART4 && (!defined(STM32_UART_UART4_RX_DMA_STREAM) || \
405 !defined(STM32_UART_UART4_TX_DMA_STREAM))
406#error "UART4 DMA streams not defined"
407#endif
408
409#if STM32_UART_USE_UART5 && (!defined(STM32_UART_UART5_RX_DMA_STREAM) || \
410 !defined(STM32_UART_UART5_TX_DMA_STREAM))
411#error "UART5 DMA streams not defined"
412#endif
413
414#if STM32_UART_USE_USART6 && (!defined(STM32_UART_USART6_RX_DMA_STREAM) || \
415 !defined(STM32_UART_USART6_TX_DMA_STREAM))
416#error "USART6 DMA streams not defined"
417#endif
418
419#if STM32_UART_USE_UART7 && (!defined(STM32_UART_UART7_RX_DMA_STREAM) || \
420 !defined(STM32_UART_UART7_TX_DMA_STREAM))
421#error "UART7 DMA streams not defined"
422#endif
423
424#if STM32_UART_USE_UART8 && (!defined(STM32_UART_UART8_RX_DMA_STREAM) || \
425 !defined(STM32_UART_UART8_TX_DMA_STREAM))
426#error "UART8 DMA streams not defined"
427#endif
428
429/* Check on the validity of the assigned DMA channels.*/
430#if STM32_UART_USE_USART1 && \
431 !STM32_DMA_IS_VALID_STREAM(STM32_UART_USART1_RX_DMA_STREAM)
432#error "Invalid DMA channel assigned to USART1 RX"
433#endif
434
435#if STM32_UART_USE_USART1 && \
436 !STM32_DMA_IS_VALID_STREAM(STM32_UART_USART1_TX_DMA_STREAM)
437#error "Invalid DMA channel assigned to USART1 TX"
438#endif
439
440#if STM32_UART_USE_USART2 && \
441 !STM32_DMA_IS_VALID_STREAM(STM32_UART_USART2_RX_DMA_STREAM)
442#error "Invalid DMA channel assigned to USART2 RX"
443#endif
444
445#if STM32_UART_USE_USART2 && \
446 !STM32_DMA_IS_VALID_STREAM(STM32_UART_USART2_TX_DMA_STREAM)
447#error "Invalid DMA channel assigned to USART2 TX"
448#endif
449
450#if STM32_UART_USE_USART3 && \
451 !STM32_DMA_IS_VALID_STREAM(STM32_UART_USART3_RX_DMA_STREAM)
452#error "Invalid DMA channel assigned to USART3 RX"
453#endif
454
455#if STM32_UART_USE_USART3 && \
456 !STM32_DMA_IS_VALID_STREAM(STM32_UART_USART3_TX_DMA_STREAM)
457#error "Invalid DMA channel assigned to USART3 TX"
458#endif
459
460#if STM32_UART_USE_UART4 && \
461 !STM32_DMA_IS_VALID_STREAM(STM32_UART_UART4_RX_DMA_STREAM)
462#error "Invalid DMA channel assigned to UART4 RX"
463#endif
464
465#if STM32_UART_USE_UART4 && \
466 !STM32_DMA_IS_VALID_STREAM(STM32_UART_UART4_TX_DMA_STREAM)
467#error "Invalid DMA channel assigned to UART4 TX"
468#endif
469
470#if STM32_UART_USE_UART5 && \
471 !STM32_DMA_IS_VALID_STREAM(STM32_UART_UART5_RX_DMA_STREAM)
472#error "Invalid DMA channel assigned to UART5 RX"
473#endif
474
475#if STM32_UART_USE_UART5 && \
476 !STM32_DMA_IS_VALID_STREAM(STM32_UART_UART5_TX_DMA_STREAM)
477#error "Invalid DMA channel assigned to UART5 TX"
478#endif
479
480#if STM32_UART_USE_USART6 && \
481 !STM32_DMA_IS_VALID_STREAM(STM32_UART_USART6_RX_DMA_STREAM)
482#error "Invalid DMA channel assigned to USART6 RX"
483#endif
484
485#if STM32_UART_USE_USART6 && \
486 !STM32_DMA_IS_VALID_STREAM(STM32_UART_USART6_TX_DMA_STREAM)
487#error "Invalid DMA channel assigned to USART6 TX"
488#endif
489
490#if STM32_UART_USE_UART7 && \
491 !STM32_DMA_IS_VALID_STREAM(STM32_UART_UART7_RX_DMA_STREAM)
492#error "Invalid DMA channel assigned to UART7 RX"
493#endif
494
495#if STM32_UART_USE_UART7 && \
496 !STM32_DMA_IS_VALID_STREAM(STM32_UART_UART7_TX_DMA_STREAM)
497#error "Invalid DMA channel assigned to UART7 TX"
498#endif
499
500#if STM32_UART_USE_UART8 && \
501 !STM32_DMA_IS_VALID_STREAM(STM32_UART_UART8_RX_DMA_STREAM)
502#error "Invalid DMA channel assigned to UART8 RX"
503#endif
504
505#if STM32_UART_USE_UART8 && \
506 !STM32_DMA_IS_VALID_STREAM(STM32_UART_UART8_TX_DMA_STREAM)
507#error "Invalid DMA channel assigned to UART8 TX"
508#endif
509
510/* Devices without DMAMUX require an additional check.*/
511#if STM32_ADVANCED_DMA && !STM32_DMA_SUPPORTS_DMAMUX
512
513/* Check on the validity of the assigned DMA channels.*/
514#if STM32_UART_USE_USART1 && \
515 !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \
516 STM32_USART1_RX_DMA_MSK)
517#error "invalid DMA stream associated to USART1 RX"
518#endif
519
520#if STM32_UART_USE_USART1 && \
521 !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM, \
522 STM32_USART1_TX_DMA_MSK)
523#error "invalid DMA stream associated to USART1 TX"
524#endif
525
526#if STM32_UART_USE_USART2 && \
527 !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM, \
528 STM32_USART2_RX_DMA_MSK)
529#error "invalid DMA stream associated to USART2 RX"
530#endif
531
532#if STM32_UART_USE_USART2 && \
533 !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM, \
534 STM32_USART2_TX_DMA_MSK)
535#error "invalid DMA stream associated to USART2 TX"
536#endif
537
538#if STM32_UART_USE_USART3 && \
539 !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM, \
540 STM32_USART3_RX_DMA_MSK)
541#error "invalid DMA stream associated to USART3 RX"
542#endif
543
544#if STM32_UART_USE_USART3 && \
545 !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM, \
546 STM32_USART3_TX_DMA_MSK)
547#error "invalid DMA stream associated to USART3 TX"
548#endif
549
550#if STM32_UART_USE_UART4 && \
551 !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_RX_DMA_STREAM, \
552 STM32_UART4_RX_DMA_MSK)
553#error "invalid DMA stream associated to UART4 RX"
554#endif
555
556#if STM32_UART_USE_UART4 && \
557 !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_TX_DMA_STREAM, \
558 STM32_UART4_TX_DMA_MSK)
559#error "invalid DMA stream associated to UART4 TX"
560#endif
561
562#if STM32_UART_USE_UART5 && \
563 !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_RX_DMA_STREAM, \
564 STM32_UART5_RX_DMA_MSK)
565#error "invalid DMA stream associated to UART5 RX"
566#endif
567
568#if STM32_UART_USE_UART5 && \
569 !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_TX_DMA_STREAM, \
570 STM32_UART5_TX_DMA_MSK)
571#error "invalid DMA stream associated to UART5 TX"
572#endif
573
574#if STM32_UART_USE_USART6 && \
575 !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_RX_DMA_STREAM, \
576 STM32_USART6_RX_DMA_MSK)
577#error "invalid DMA stream associated to USART6 RX"
578#endif
579
580#if STM32_UART_USE_USART6 && \
581 !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_TX_DMA_STREAM, \
582 STM32_USART6_TX_DMA_MSK)
583#error "invalid DMA stream associated to USART6 TX"
584#endif
585
586#if STM32_UART_USE_UART7 && \
587 !STM32_DMA_IS_VALID_ID(STM32_UART_UART7_RX_DMA_STREAM, \
588 STM32_UART7_RX_DMA_MSK)
589#error "invalid DMA stream associated to UART7 RX"
590#endif
591
592#if STM32_UART_USE_UART7 && \
593 !STM32_DMA_IS_VALID_ID(STM32_UART_UART7_TX_DMA_STREAM, \
594 STM32_UART7_TX_DMA_MSK)
595#error "invalid DMA stream associated to UART7 TX"
596#endif
597
598#if STM32_UART_USE_UART8 && \
599 !STM32_DMA_IS_VALID_ID(STM32_UART_UART8_RX_DMA_STREAM, \
600 STM32_UART8_RX_DMA_MSK)
601#error "invalid DMA stream associated to UART8 RX"
602#endif
603
604#if STM32_UART_USE_UART8 && \
605 !STM32_DMA_IS_VALID_ID(STM32_UART_UART8_TX_DMA_STREAM, \
606 STM32_UART8_TX_DMA_MSK)
607#error "invalid DMA stream associated to UART8 TX"
608#endif
609
610#endif /* STM32_ADVANCED_DMA && !STM32_DMA_SUPPORTS_DMAMUX */
611
612#if !defined(STM32_DMA_REQUIRED)
613#define STM32_DMA_REQUIRED
614#endif
615
616/*===========================================================================*/
617/* Driver data structures and types. */
618/*===========================================================================*/
619
620/**
621 * @brief UART driver condition flags type.
622 */
623typedef uint32_t uartflags_t;
624
625/**
626 * @brief Structure representing an UART driver.
627 */
628typedef struct UARTDriver UARTDriver;
629
630/**
631 * @brief Generic UART notification callback type.
632 *
633 * @param[in] uartp pointer to the @p UARTDriver object
634 */
635typedef void (*uartcb_t)(UARTDriver *uartp);
636
637/**
638 * @brief Character received UART notification callback type.
639 *
640 * @param[in] uartp pointer to the @p UARTDriver object
641 * @param[in] c received character
642 */
643typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c);
644
645/**
646 * @brief Receive error UART notification callback type.
647 *
648 * @param[in] uartp pointer to the @p UARTDriver object
649 * @param[in] e receive error mask
650 */
651typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e);
652
653/**
654 * @brief Driver configuration structure.
655 * @note It could be empty on some architectures.
656 */
657typedef struct {
658 /**
659 * @brief End of transmission buffer callback.
660 */
661 uartcb_t txend1_cb;
662 /**
663 * @brief Physical end of transmission callback.
664 */
665 uartcb_t txend2_cb;
666 /**
667 * @brief Receive buffer filled callback.
668 */
669 uartcb_t rxend_cb;
670 /**
671 * @brief Character received while out if the @p UART_RECEIVE state.
672 */
673 uartccb_t rxchar_cb;
674 /**
675 * @brief Receive error callback.
676 */
677 uartecb_t rxerr_cb;
678 /* End of the mandatory fields.*/
679 /**
680 * @brief Receiver timeout callback.
681 * @details Handles both idle and timeout interrupts depending on configured
682 * flags in CR registers and supported hardware features.
683 */
684 uartcb_t timeout_cb;
685 /**
686 * @brief Receiver timeout value in terms of number of bit duration.
687 * @details Set it to 0 when you want to handle idle interrupt instead of
688 * hardware timeout.
689 */
690 uint32_t timeout;
691 /**
692 * @brief Bit rate.
693 */
694 uint32_t speed;
695 /**
696 * @brief Initialization value for the CR1 register.
697 */
698 uint32_t cr1;
699 /**
700 * @brief Initialization value for the CR2 register.
701 */
702 uint32_t cr2;
703 /**
704 * @brief Initialization value for the CR3 register.
705 */
706 uint32_t cr3;
707} UARTConfig;
708
709/**
710 * @brief Structure representing an UART driver.
711 */
712struct UARTDriver {
713 /**
714 * @brief Driver state.
715 */
716 uartstate_t state;
717 /**
718 * @brief Transmitter state.
719 */
720 uarttxstate_t txstate;
721 /**
722 * @brief Receiver state.
723 */
724 uartrxstate_t rxstate;
725 /**
726 * @brief Current configuration data.
727 */
728 const UARTConfig *config;
729#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__)
730 /**
731 * @brief Synchronization flag for transmit operations.
732 */
733 bool early;
734 /**
735 * @brief Waiting thread on RX.
736 */
737 thread_reference_t threadrx;
738 /**
739 * @brief Waiting thread on TX.
740 */
741 thread_reference_t threadtx;
742#endif /* UART_USE_WAIT */
743#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
744 /**
745 * @brief Mutex protecting the peripheral.
746 */
747 mutex_t mutex;
748#endif /* UART_USE_MUTUAL_EXCLUSION */
749#if defined(UART_DRIVER_EXT_FIELDS)
750 UART_DRIVER_EXT_FIELDS
751#endif
752 /* End of the mandatory fields.*/
753 /**
754 * @brief Pointer to the USART registers block.
755 */
756 USART_TypeDef *usart;
757 /**
758 * @brief Clock frequency for the associated USART/UART.
759 */
760 uint32_t clock;
761 /**
762 * @brief Receive DMA mode bit mask.
763 */
764 uint32_t dmarxmode;
765 /**
766 * @brief Send DMA mode bit mask.
767 */
768 uint32_t dmatxmode;
769 /**
770 * @brief Receive DMA channel.
771 */
772 const stm32_dma_stream_t *dmarx;
773 /**
774 * @brief Transmit DMA channel.
775 */
776 const stm32_dma_stream_t *dmatx;
777 /**
778 * @brief Default receive buffer while into @p UART_RX_IDLE state.
779 */
780 volatile uint16_t rxbuf;
781};
782
783/*===========================================================================*/
784/* Driver macros. */
785/*===========================================================================*/
786
787/*===========================================================================*/
788/* External declarations. */
789/*===========================================================================*/
790
791#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__)
792extern UARTDriver UARTD1;
793#endif
794
795#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__)
796extern UARTDriver UARTD2;
797#endif
798
799#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__)
800extern UARTDriver UARTD3;
801#endif
802
803#if STM32_UART_USE_UART4 && !defined(__DOXYGEN__)
804extern UARTDriver UARTD4;
805#endif
806
807#if STM32_UART_USE_UART5 && !defined(__DOXYGEN__)
808extern UARTDriver UARTD5;
809#endif
810
811#if STM32_UART_USE_USART6 && !defined(__DOXYGEN__)
812extern UARTDriver UARTD6;
813#endif
814
815#if STM32_UART_USE_UART7 && !defined(__DOXYGEN__)
816extern UARTDriver UARTD7;
817#endif
818
819#if STM32_UART_USE_UART8 && !defined(__DOXYGEN__)
820extern UARTDriver UARTD8;
821#endif
822
823#ifdef __cplusplus
824extern "C" {
825#endif
826 void uart_lld_init(void);
827 void uart_lld_start(UARTDriver *uartp);
828 void uart_lld_stop(UARTDriver *uartp);
829 void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf);
830 size_t uart_lld_stop_send(UARTDriver *uartp);
831 void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf);
832 size_t uart_lld_stop_receive(UARTDriver *uartp);
833 void uart_lld_serve_interrupt(UARTDriver *uartp);
834#ifdef __cplusplus
835}
836#endif
837
838#endif /* HAL_USE_UART */
839
840#endif /* HAL_UART_LLD_H */
841
842/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_lpuart1.inc b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_lpuart1.inc
new file mode 100644
index 000000000..223ce2e12
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_lpuart1.inc
@@ -0,0 +1,110 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/stm32_lpuart1.inc
19 * @brief Shared LPUART1 handler.
20 *
21 * @addtogroup STM32_LPUART1_HANDLER
22 * @{
23 */
24
25/*===========================================================================*/
26/* Driver local definitions. */
27/*===========================================================================*/
28
29/*===========================================================================*/
30/* Derived constants and error checks. */
31/*===========================================================================*/
32
33/* Registry checks for robustness.*/
34#if !defined(STM32_HAS_LPUART1)
35#error "STM32_HAS_LPUART1 not defined in registry"
36#endif
37
38#if STM32_HAS_LPUART1
39
40/* Priority settings checks.*/
41#if !defined(STM32_IRQ_LPUART1_PRIORITY)
42#error "STM32_IRQ_LPUART1_PRIORITY not defined in mcuconf.h"
43#endif
44
45#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_LPUART1_PRIORITY)
46#error "Invalid IRQ priority assigned to STM32_IRQ_LPUART1_PRIORITY"
47#endif
48
49#endif /* STM32_HAS_LPUART1 */
50
51/* Other checks.*/
52#if (HAL_USE_SERIAL && STM32_SERIAL_USE_LPUART1)
53#define STM32_LPUART1_IS_USED TRUE
54#else
55#define STM32_LPUART1_IS_USED FALSE
56#endif
57
58/*===========================================================================*/
59/* Driver exported variables. */
60/*===========================================================================*/
61
62/*===========================================================================*/
63/* Driver local variables. */
64/*===========================================================================*/
65
66/*===========================================================================*/
67/* Driver local functions. */
68/*===========================================================================*/
69
70static inline void lpuart1_irq_init(void) {
71#if STM32_LPUART1_IS_USED
72 nvicEnableVector(STM32_LPUART1_NUMBER, STM32_IRQ_LPUART1_PRIORITY);
73#endif
74}
75
76static inline void lpuart1_irq_deinit(void) {
77#if STM32_LPUART1_IS_USED
78 nvicDisableVector(STM32_LPUART1_NUMBER);
79#endif
80}
81
82/*===========================================================================*/
83/* Driver interrupt handlers. */
84/*===========================================================================*/
85
86#if STM32_LPUART1_IS_USED || defined(__DOXYGEN__)
87/**
88 * @brief LPUART1 interrupt handler.
89 *
90 * @isr
91 */
92OSAL_IRQ_HANDLER(STM32_LPUART1_HANDLER) {
93
94 OSAL_IRQ_PROLOGUE();
95
96#if HAL_USE_SERIAL
97#if STM32_SERIAL_USE_LPUART1
98 sd_lld_serve_interrupt(&LPSD1);
99#endif
100#endif
101
102 OSAL_IRQ_EPILOGUE();
103}
104#endif
105
106/*===========================================================================*/
107/* Driver exported functions. */
108/*===========================================================================*/
109
110/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart4.inc b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart4.inc
new file mode 100644
index 000000000..5dd7b5101
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart4.inc
@@ -0,0 +1,121 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/stm32_uart4.inc
19 * @brief Shared UART4 handler.
20 *
21 * @addtogroup STM32_UART4_HANDLER
22 * @{
23 */
24
25/*===========================================================================*/
26/* Driver local definitions. */
27/*===========================================================================*/
28
29/*===========================================================================*/
30/* Derived constants and error checks. */
31/*===========================================================================*/
32
33/* Registry checks for robustness.*/
34#if !defined(STM32_HAS_UART4)
35#error "STM32_HAS_UART4 not defined in registry"
36#endif
37
38#if STM32_HAS_UART4
39
40/* Priority settings checks.*/
41#if !defined(STM32_IRQ_UART4_PRIORITY)
42#error "STM32_IRQ_UART4_PRIORITY not defined in mcuconf.h"
43#endif
44
45#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_UART4_PRIORITY)
46#error "Invalid IRQ priority assigned to STM32_IRQ_UART4_PRIORITY"
47#endif
48
49#endif /* STM32_HAS_UART4 */
50
51/* Other checks.*/
52#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART4) && \
53 (HAL_USE_UART && STM32_UART_USE_UART4)
54#error "UART4 used by multiple drivers"
55#endif
56
57#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART4) || \
58 (HAL_USE_UART && STM32_UART_USE_UART4)
59#define STM32_UART4_IS_USED TRUE
60#else
61#define STM32_UART4_IS_USED FALSE
62#endif
63
64/*===========================================================================*/
65/* Driver exported variables. */
66/*===========================================================================*/
67
68/*===========================================================================*/
69/* Driver local variables. */
70/*===========================================================================*/
71
72/*===========================================================================*/
73/* Driver local functions. */
74/*===========================================================================*/
75
76static inline void uart4_irq_init(void) {
77#if STM32_UART4_IS_USED
78 nvicEnableVector(STM32_UART4_NUMBER, STM32_IRQ_UART4_PRIORITY);
79#endif
80}
81
82static inline void uart4_irq_deinit(void) {
83#if STM32_UART4_IS_USED
84 nvicDisableVector(STM32_UART4_NUMBER);
85#endif
86}
87
88/*===========================================================================*/
89/* Driver interrupt handlers. */
90/*===========================================================================*/
91
92#if STM32_UART4_IS_USED || defined(__DOXYGEN__)
93/**
94 * @brief UART4 interrupt handler.
95 *
96 * @isr
97 */
98OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) {
99
100 OSAL_IRQ_PROLOGUE();
101
102#if HAL_USE_SERIAL
103#if STM32_SERIAL_USE_UART4
104 sd_lld_serve_interrupt(&SD4);
105#endif
106#endif
107#if HAL_USE_UART
108#if STM32_UART_USE_UART4
109 uart_lld_serve_interrupt(&UARTD4);
110#endif
111#endif
112
113 OSAL_IRQ_EPILOGUE();
114}
115#endif
116
117/*===========================================================================*/
118/* Driver exported functions. */
119/*===========================================================================*/
120
121/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart5.inc b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart5.inc
new file mode 100644
index 000000000..b382d849d
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart5.inc
@@ -0,0 +1,121 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/stm32_uart5.inc
19 * @brief Shared UART5 handler.
20 *
21 * @addtogroup STM32_UART5_HANDLER
22 * @{
23 */
24
25/*===========================================================================*/
26/* Driver local definitions. */
27/*===========================================================================*/
28
29/*===========================================================================*/
30/* Derived constants and error checks. */
31/*===========================================================================*/
32
33/* Registry checks for robustness.*/
34#if !defined(STM32_HAS_UART5)
35#error "STM32_HAS_UART5 not defined in registry"
36#endif
37
38#if STM32_HAS_UART5
39
40/* Priority settings checks.*/
41#if !defined(STM32_IRQ_UART5_PRIORITY)
42#error "STM32_IRQ_UART5_PRIORITY not defined in mcuconf.h"
43#endif
44
45#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_UART5_PRIORITY)
46#error "Invalid IRQ priority assigned to STM32_IRQ_UART5_PRIORITY"
47#endif
48
49#endif /* STM32_HAS_UART5 */
50
51/* Other checks.*/
52#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART5) && \
53 (HAL_USE_UART && STM32_UART_USE_UART5)
54#error "UART5 used by multiple drivers"
55#endif
56
57#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART5) || \
58 (HAL_USE_UART && STM32_UART_USE_UART5)
59#define STM32_UART5_IS_USED TRUE
60#else
61#define STM32_UART5_IS_USED FALSE
62#endif
63
64/*===========================================================================*/
65/* Driver exported variables. */
66/*===========================================================================*/
67
68/*===========================================================================*/
69/* Driver local variables. */
70/*===========================================================================*/
71
72/*===========================================================================*/
73/* Driver local functions. */
74/*===========================================================================*/
75
76static inline void uart5_irq_init(void) {
77#if STM32_UART5_IS_USED
78 nvicEnableVector(STM32_UART5_NUMBER, STM32_IRQ_UART5_PRIORITY);
79#endif
80}
81
82static inline void uart5_irq_deinit(void) {
83#if STM32_UART5_IS_USED
84 nvicDisableVector(STM32_UART5_NUMBER);
85#endif
86}
87
88/*===========================================================================*/
89/* Driver interrupt handlers. */
90/*===========================================================================*/
91
92#if STM32_UART5_IS_USED || defined(__DOXYGEN__)
93/**
94 * @brief UART5 interrupt handler.
95 *
96 * @isr
97 */
98OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) {
99
100 OSAL_IRQ_PROLOGUE();
101
102#if HAL_USE_SERIAL
103#if STM32_SERIAL_USE_UART5
104 sd_lld_serve_interrupt(&SD5);
105#endif
106#endif
107#if HAL_USE_UART
108#if STM32_UART_USE_UART5
109 uart_lld_serve_interrupt(&UARTD5);
110#endif
111#endif
112
113 OSAL_IRQ_EPILOGUE();
114}
115#endif
116
117/*===========================================================================*/
118/* Driver exported functions. */
119/*===========================================================================*/
120
121/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart7.inc b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart7.inc
new file mode 100644
index 000000000..2ec791e35
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart7.inc
@@ -0,0 +1,121 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/stm32_uart7.inc
19 * @brief Shared UART7 handler.
20 *
21 * @addtogroup STM32_UART7_HANDLER
22 * @{
23 */
24
25/*===========================================================================*/
26/* Driver local definitions. */
27/*===========================================================================*/
28
29/*===========================================================================*/
30/* Derived constants and error checks. */
31/*===========================================================================*/
32
33/* Registry checks for robustness.*/
34#if !defined(STM32_HAS_UART7)
35#error "STM32_HAS_UART7 not defined in registry"
36#endif
37
38#if STM32_HAS_UART7
39
40/* Priority settings checks.*/
41#if !defined(STM32_IRQ_UART7_PRIORITY)
42#error "STM32_IRQ_UART7_PRIORITY not defined in mcuconf.h"
43#endif
44
45#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_UART7_PRIORITY)
46#error "Invalid IRQ priority assigned to STM32_IRQ_UART7_PRIORITY"
47#endif
48
49#endif /* STM32_HAS_UART7 */
50
51/* Other checks.*/
52#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART7) && \
53 (HAL_USE_UART && STM32_UART_USE_UART7)
54#error "UART7 used by multiple drivers"
55#endif
56
57#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART7) || \
58 (HAL_USE_UART && STM32_UART_USE_UART7)
59#define STM32_UART7_IS_USED TRUE
60#else
61#define STM32_UART7_IS_USED FALSE
62#endif
63
64/*===========================================================================*/
65/* Driver exported variables. */
66/*===========================================================================*/
67
68/*===========================================================================*/
69/* Driver local variables. */
70/*===========================================================================*/
71
72/*===========================================================================*/
73/* Driver local functions. */
74/*===========================================================================*/
75
76static inline void uart7_irq_init(void) {
77#if STM32_UART7_IS_USED
78 nvicEnableVector(STM32_UART7_NUMBER, STM32_IRQ_UART7_PRIORITY);
79#endif
80}
81
82static inline void uart7_irq_deinit(void) {
83#if STM32_UART7_IS_USED
84 nvicDisableVector(STM32_UART7_NUMBER);
85#endif
86}
87
88/*===========================================================================*/
89/* Driver interrupt handlers. */
90/*===========================================================================*/
91
92#if STM32_UART7_IS_USED || defined(__DOXYGEN__)
93/**
94 * @brief UART7 interrupt handler.
95 *
96 * @isr
97 */
98OSAL_IRQ_HANDLER(STM32_UART7_HANDLER) {
99
100 OSAL_IRQ_PROLOGUE();
101
102#if HAL_USE_SERIAL
103#if STM32_SERIAL_USE_UART7
104 sd_lld_serve_interrupt(&SD7);
105#endif
106#endif
107#if HAL_USE_UART
108#if STM32_UART_USE_UART7
109 uart_lld_serve_interrupt(&UARTD7);
110#endif
111#endif
112
113 OSAL_IRQ_EPILOGUE();
114}
115#endif
116
117/*===========================================================================*/
118/* Driver exported functions. */
119/*===========================================================================*/
120
121/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart8.inc b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart8.inc
new file mode 100644
index 000000000..89584318b
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_uart8.inc
@@ -0,0 +1,121 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/stm32_uart8.inc
19 * @brief Shared UART8 handler.
20 *
21 * @addtogroup STM32_UART8_HANDLER
22 * @{
23 */
24
25/*===========================================================================*/
26/* Driver local definitions. */
27/*===========================================================================*/
28
29/*===========================================================================*/
30/* Derived constants and error checks. */
31/*===========================================================================*/
32
33/* Registry checks for robustness.*/
34#if !defined(STM32_HAS_UART8)
35#error "STM32_HAS_UART8 not defined in registry"
36#endif
37
38#if STM32_HAS_UART8
39
40/* Priority settings checks.*/
41#if !defined(STM32_IRQ_UART8_PRIORITY)
42#error "STM32_IRQ_UART8_PRIORITY not defined in mcuconf.h"
43#endif
44
45#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_UART8_PRIORITY)
46#error "Invalid IRQ priority assigned to STM32_IRQ_UART8_PRIORITY"
47#endif
48
49#endif /* STM32_HAS_UART8 */
50
51/* Other checks.*/
52#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART8) && \
53 (HAL_USE_UART && STM32_UART_USE_UART8)
54#error "UART8 used by multiple drivers"
55#endif
56
57#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART8) || \
58 (HAL_USE_UART && STM32_UART_USE_UART8)
59#define STM32_UART8_IS_USED TRUE
60#else
61#define STM32_UART8_IS_USED FALSE
62#endif
63
64/*===========================================================================*/
65/* Driver exported variables. */
66/*===========================================================================*/
67
68/*===========================================================================*/
69/* Driver local variables. */
70/*===========================================================================*/
71
72/*===========================================================================*/
73/* Driver local functions. */
74/*===========================================================================*/
75
76static inline void uart8_irq_init(void) {
77#if STM32_UART8_IS_USED
78 nvicEnableVector(STM32_UART8_NUMBER, STM32_IRQ_UART8_PRIORITY);
79#endif
80}
81
82static inline void uart8_irq_deinit(void) {
83#if STM32_UART8_IS_USED
84 nvicDisableVector(STM32_UART8_NUMBER);
85#endif
86}
87
88/*===========================================================================*/
89/* Driver interrupt handlers. */
90/*===========================================================================*/
91
92#if STM32_UART8_IS_USED || defined(__DOXYGEN__)
93/**
94 * @brief UART8 interrupt handler.
95 *
96 * @isr
97 */
98OSAL_IRQ_HANDLER(STM32_UART8_HANDLER) {
99
100 OSAL_IRQ_PROLOGUE();
101
102#if HAL_USE_SERIAL
103#if STM32_SERIAL_USE_UART8
104 sd_lld_serve_interrupt(&SD8);
105#endif
106#endif
107#if HAL_USE_UART
108#if STM32_UART_USE_UART8
109 uart_lld_serve_interrupt(&UARTD8);
110#endif
111#endif
112
113 OSAL_IRQ_EPILOGUE();
114}
115#endif
116
117/*===========================================================================*/
118/* Driver exported functions. */
119/*===========================================================================*/
120
121/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart1.inc b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart1.inc
new file mode 100644
index 000000000..19aac1008
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart1.inc
@@ -0,0 +1,121 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/stm32_usart1.inc
19 * @brief Shared USART1 handler.
20 *
21 * @addtogroup STM32_USART1_HANDLER
22 * @{
23 */
24
25/*===========================================================================*/
26/* Driver local definitions. */
27/*===========================================================================*/
28
29/*===========================================================================*/
30/* Derived constants and error checks. */
31/*===========================================================================*/
32
33/* Registry checks for robustness.*/
34#if !defined(STM32_HAS_USART1)
35#error "STM32_HAS_USART1 not defined in registry"
36#endif
37
38#if STM32_HAS_USART1
39
40/* Priority settings checks.*/
41#if !defined(STM32_IRQ_USART1_PRIORITY)
42#error "STM32_IRQ_USART1_PRIORITY not defined in mcuconf.h"
43#endif
44
45#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART1_PRIORITY)
46#error "Invalid IRQ priority assigned to STM32_IRQ_USART1_PRIORITY"
47#endif
48
49#endif /* STM32_HAS_USART1 */
50
51/* Other checks.*/
52#if (HAL_USE_SERIAL && STM32_SERIAL_USE_USART1) && \
53 (HAL_USE_UART && STM32_UART_USE_USART1)
54#error "USART1 used by multiple drivers"
55#endif
56
57#if (HAL_USE_SERIAL && STM32_SERIAL_USE_USART1) || \
58 (HAL_USE_UART && STM32_UART_USE_USART1)
59#define STM32_USART1_IS_USED TRUE
60#else
61#define STM32_USART1_IS_USED FALSE
62#endif
63
64/*===========================================================================*/
65/* Driver exported variables. */
66/*===========================================================================*/
67
68/*===========================================================================*/
69/* Driver local variables. */
70/*===========================================================================*/
71
72/*===========================================================================*/
73/* Driver local functions. */
74/*===========================================================================*/
75
76static inline void usart1_irq_init(void) {
77#if STM32_USART1_IS_USED
78 nvicEnableVector(STM32_USART1_NUMBER, STM32_IRQ_USART1_PRIORITY);
79#endif
80}
81
82static inline void usart1_irq_deinit(void) {
83#if STM32_USART1_IS_USED
84 nvicDisableVector(STM32_USART1_NUMBER);
85#endif
86}
87
88/*===========================================================================*/
89/* Driver interrupt handlers. */
90/*===========================================================================*/
91
92#if STM32_USART1_IS_USED|| defined(__DOXYGEN__)
93/**
94 * @brief USART1 interrupt handler.
95 *
96 * @isr
97 */
98OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
99
100 OSAL_IRQ_PROLOGUE();
101
102#if HAL_USE_SERIAL
103#if STM32_SERIAL_USE_USART1
104 sd_lld_serve_interrupt(&SD1);
105#endif
106#endif
107#if HAL_USE_UART
108#if STM32_UART_USE_USART1
109 uart_lld_serve_interrupt(&UARTD1);
110#endif
111#endif
112
113 OSAL_IRQ_EPILOGUE();
114}
115#endif
116
117/*===========================================================================*/
118/* Driver exported functions. */
119/*===========================================================================*/
120
121/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart2.inc b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart2.inc
new file mode 100644
index 000000000..c4b900017
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart2.inc
@@ -0,0 +1,121 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/stm32_usart2.inc
19 * @brief Shared USART2 handler.
20 *
21 * @addtogroup STM32_USART2_HANDLER
22 * @{
23 */
24
25/*===========================================================================*/
26/* Driver local definitions. */
27/*===========================================================================*/
28
29/*===========================================================================*/
30/* Derived constants and error checks. */
31/*===========================================================================*/
32
33/* Registry checks for robustness.*/
34#if !defined(STM32_HAS_USART2)
35#error "STM32_HAS_USART2 not defined in registry"
36#endif
37
38#if STM32_HAS_USART2
39
40/* Priority settings checks.*/
41#if !defined(STM32_IRQ_USART2_PRIORITY)
42#error "STM32_IRQ_USART2_PRIORITY not defined in mcuconf.h"
43#endif
44
45#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART2_PRIORITY)
46#error "Invalid IRQ priority assigned to STM32_IRQ_USART2_PRIORITY"
47#endif
48
49#endif /* STM32_HAS_USART2 */
50
51/* Other checks.*/
52#if (HAL_USE_SERIAL && STM32_SERIAL_USE_USART2) && \
53 (HAL_USE_UART && STM32_UART_USE_USART2)
54#error "USART2 used by multiple drivers"
55#endif
56
57#if (HAL_USE_SERIAL && STM32_SERIAL_USE_USART2) || \
58 (HAL_USE_UART && STM32_UART_USE_USART2)
59#define STM32_USART2_IS_USED TRUE
60#else
61#define STM32_USART2_IS_USED FALSE
62#endif
63
64/*===========================================================================*/
65/* Driver exported variables. */
66/*===========================================================================*/
67
68/*===========================================================================*/
69/* Driver local variables. */
70/*===========================================================================*/
71
72/*===========================================================================*/
73/* Driver local functions. */
74/*===========================================================================*/
75
76static inline void usart2_irq_init(void) {
77#if STM32_USART2_IS_USED
78 nvicEnableVector(STM32_USART2_NUMBER, STM32_IRQ_USART2_PRIORITY);
79#endif
80}
81
82static inline void usart2_irq_deinit(void) {
83#if STM32_USART2_IS_USED
84 nvicDisableVector(STM32_USART2_NUMBER);
85#endif
86}
87
88/*===========================================================================*/
89/* Driver interrupt handlers. */
90/*===========================================================================*/
91
92#if STM32_USART2_IS_USED || defined(__DOXYGEN__)
93/**
94 * @brief USART2 interrupt handler.
95 *
96 * @isr
97 */
98OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
99
100 OSAL_IRQ_PROLOGUE();
101
102#if HAL_USE_SERIAL
103#if STM32_SERIAL_USE_USART2
104 sd_lld_serve_interrupt(&SD2);
105#endif
106#endif
107#if HAL_USE_UART
108#if STM32_UART_USE_USART2
109 uart_lld_serve_interrupt(&UARTD2);
110#endif
111#endif
112
113 OSAL_IRQ_EPILOGUE();
114}
115#endif
116
117/*===========================================================================*/
118/* Driver exported functions. */
119/*===========================================================================*/
120
121/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3.inc b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3.inc
new file mode 100644
index 000000000..ff5dbda86
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3.inc
@@ -0,0 +1,121 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/stm32_usart3.inc
19 * @brief Shared USART3 handler.
20 *
21 * @addtogroup STM32_USART3_HANDLER
22 * @{
23 */
24
25/*===========================================================================*/
26/* Driver local definitions. */
27/*===========================================================================*/
28
29/*===========================================================================*/
30/* Derived constants and error checks. */
31/*===========================================================================*/
32
33/* Registry checks for robustness.*/
34#if !defined(STM32_HAS_USART3)
35#error "STM32_HAS_USART3 not defined in registry"
36#endif
37
38#if STM32_HAS_USART3
39
40/* Priority settings checks.*/
41#if !defined(STM32_IRQ_USART3_PRIORITY)
42#error "STM32_IRQ_USART3_PRIORITY not defined in mcuconf.h"
43#endif
44
45#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART3_PRIORITY)
46#error "Invalid IRQ priority assigned to STM32_IRQ_USART3_PRIORITY"
47#endif
48
49#endif /* STM32_HAS_USART3 */
50
51/* Other checks.*/
52#if (HAL_USE_SERIAL && STM32_SERIAL_USE_USART3) && \
53 (HAL_USE_UART && STM32_UART_USE_USART3)
54#error "USART3 used by multiple drivers"
55#endif
56
57#if (HAL_USE_SERIAL && STM32_SERIAL_USE_USART3) || \
58 (HAL_USE_UART && STM32_UART_USE_USART3)
59#define STM32_USART3_IS_USED TRUE
60#else
61#define STM32_USART3_IS_USED FALSE
62#endif
63
64/*===========================================================================*/
65/* Driver exported variables. */
66/*===========================================================================*/
67
68/*===========================================================================*/
69/* Driver local variables. */
70/*===========================================================================*/
71
72/*===========================================================================*/
73/* Driver local functions. */
74/*===========================================================================*/
75
76static inline void usart3_irq_init(void) {
77#if STM32_USART3_IS_USED
78 nvicEnableVector(STM32_USART3_NUMBER, STM32_IRQ_USART3_PRIORITY);
79#endif
80}
81
82static inline void usart3_irq_deinit(void) {
83#if STM32_USART3_IS_USED
84 nvicDisableVector(STM32_USART3_NUMBER);
85#endif
86}
87
88/*===========================================================================*/
89/* Driver interrupt handlers. */
90/*===========================================================================*/
91
92#if STM32_USART3_IS_USED || defined(__DOXYGEN__)
93/**
94 * @brief USART3 interrupt handler.
95 *
96 * @isr
97 */
98OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) {
99
100 OSAL_IRQ_PROLOGUE();
101
102#if HAL_USE_SERIAL
103#if STM32_SERIAL_USE_USART3
104 sd_lld_serve_interrupt(&SD3);
105#endif
106#endif
107#if HAL_USE_UART
108#if STM32_UART_USE_USART3
109 uart_lld_serve_interrupt(&UARTD3);
110#endif
111#endif
112
113 OSAL_IRQ_EPILOGUE();
114}
115#endif
116
117/*===========================================================================*/
118/* Driver exported functions. */
119/*===========================================================================*/
120
121/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3_4_lp1.inc b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3_4_lp1.inc
new file mode 100644
index 000000000..596237fb2
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3_4_lp1.inc
@@ -0,0 +1,157 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/stm32_usart3_4_lp1.inc
19 * @brief Shared USART3, USART4, LPUART1 handler.
20 *
21 * @addtogroup STM32_USART3_4_LP1_HANDLER
22 * @{
23 */
24
25/*===========================================================================*/
26/* Driver local definitions. */
27/*===========================================================================*/
28
29/*===========================================================================*/
30/* Derived constants and error checks. */
31/*===========================================================================*/
32
33/* Registry checks for robustness.*/
34#if !defined(STM32_HAS_USART3)
35#error "STM32_HAS_USART3 not defined in registry"
36#endif
37
38#if !defined(STM32_HAS_UART4)
39#error "STM32_HAS_UART4 not defined in registry"
40#endif
41
42#if !defined(STM32_HAS_LPUART1)
43#error "STM32_HAS_LPUART1 not defined in registry"
44#endif
45
46#if STM32_HAS_USART3 || STM32_HAS_UART4 || STM32_HAS_LPUART1
47
48/* Priority settings checks.*/
49#if !defined(STM32_IRQ_USART3_4_LP1_PRIORITY)
50#error "STM32_IRQ_USART3_4_LP1_PRIORITY not defined in mcuconf.h"
51#endif
52
53#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART3_4_LP1_PRIORITY)
54#error "Invalid IRQ priority assigned to STM32_IRQ_USART3_4_LP1_PRIORITY"
55#endif
56
57#endif /* STM32_HAS_USART3 || STM32_HAS_UART4 || STM32_HAS_LPUART1 */
58
59/* Other checks.*/
60#if (HAL_USE_SERIAL && STM32_SERIAL_USE_USART3) && \
61 (HAL_USE_UART && STM32_UART_USE_USART3)
62#error "USART3 used by multiple drivers"
63#endif
64
65#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART4) && \
66 (HAL_USE_UART && STM32_UART_USE_UART4)
67#error "USART4 used by multiple drivers"
68#endif
69
70#if (HAL_USE_SERIAL && STM32_SERIAL_USE_USART3) || \
71 (HAL_USE_UART && STM32_UART_USE_USART3)
72#define STM32_USART3_IS_USED TRUE
73#else
74#define STM32_USART3_IS_USED FALSE
75#endif
76
77#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART4) || \
78 (HAL_USE_UART && STM32_UART_USE_UART4)
79#define STM32_USART4_IS_USED TRUE
80#else
81#define STM32_USART4_IS_USED FALSE
82#endif
83
84#if (HAL_USE_SERIAL && STM32_SERIAL_USE_LPUART1)
85#define STM32_LPUART1_IS_USED TRUE
86#else
87#define STM32_LPUART1_IS_USED FALSE
88#endif
89
90/*===========================================================================*/
91/* Driver exported variables. */
92/*===========================================================================*/
93
94/*===========================================================================*/
95/* Driver local variables. */
96/*===========================================================================*/
97
98/*===========================================================================*/
99/* Driver local functions. */
100/*===========================================================================*/
101
102static inline void usart3_usart4_lpuart1_irq_init(void) {
103#if STM32_USART3_IS_USED || STM32_USART4_IS_USED || STM32_LPUART1_IS_USED
104 nvicEnableVector(STM32_USART3_4_LP1_NUMBER, STM32_IRQ_USART3_4_LP1_PRIORITY);
105#endif
106}
107
108static inline void usart3_usart4_lpuart1_irq_deinit(void) {
109#if STM32_USART3_IS_USED || STM32_USART4_IS_USED || STM32_LPUART1_IS_USED
110 nvicDisableVector(STM32_USART3_4_LP1_NUMBER);
111#endif
112}
113
114/*===========================================================================*/
115/* Driver interrupt handlers. */
116/*===========================================================================*/
117
118#if STM32_USART3_IS_USED || STM32_USART4_IS_USED || \
119 STM32_LPUART1_IS_USED || defined(__DOXYGEN__)
120/**
121 * @brief USART4, USART5, LPUART1 interrupt handler.
122 *
123 * @isr
124 */
125OSAL_IRQ_HANDLER(STM32_USART3_4_LP1_HANDLER) {
126
127 OSAL_IRQ_PROLOGUE();
128
129#if HAL_USE_SERIAL
130#if STM32_SERIAL_USE_USART3
131 sd_lld_serve_interrupt(&SD3);
132#endif
133#if STM32_SERIAL_USE_UART4
134 sd_lld_serve_interrupt(&SD4);
135#endif
136#if STM32_SERIAL_USE_LPUART1
137 sd_lld_serve_interrupt(&LPSD1);
138#endif
139#endif
140#if HAL_USE_UART
141#if STM32_UART_USE_USART3
142 uart_lld_serve_interrupt(&UARTD3);
143#endif
144#if STM32_UART_USE_UART4
145 uart_lld_serve_interrupt(&UARTD4);
146#endif
147#endif
148
149 OSAL_IRQ_EPILOGUE();
150}
151#endif
152
153/*===========================================================================*/
154/* Driver exported functions. */
155/*===========================================================================*/
156
157/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart4_5.inc b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart4_5.inc
new file mode 100644
index 000000000..7d003a3c6
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart4_5.inc
@@ -0,0 +1,144 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/stm32_usart4_5.inc
19 * @brief Shared USART4, USART5 handler.
20 *
21 * @addtogroup STM32_USART4_5_HANDLER
22 * @{
23 */
24
25/*===========================================================================*/
26/* Driver local definitions. */
27/*===========================================================================*/
28
29/*===========================================================================*/
30/* Derived constants and error checks. */
31/*===========================================================================*/
32
33/* Registry checks for robustness.*/
34#if !defined(STM32_HAS_UART4)
35#error "STM32_HAS_UART4 not defined in registry"
36#endif
37
38#if !defined(STM32_HAS_UART5)
39#error "STM32_HAS_UART5 not defined in registry"
40#endif
41
42#if STM32_HAS_UART4 || STM32_HAS_UART5
43
44/* Priority settings checks.*/
45#if !defined(STM32_IRQ_USART4_5_PRIORITY)
46#error "STM32_IRQ_USART4_5_PRIORITY not defined in mcuconf.h"
47#endif
48
49#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART4_5_PRIORITY)
50#error "Invalid IRQ priority assigned to STM32_IRQ_USART4_5_PRIORITY"
51#endif
52
53#endif /* STM32_HAS_UART4 || STM32_HAS_UART5 */
54
55/* Other checks.*/
56#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART4) && \
57 (HAL_USE_UART && STM32_UART_USE_UART4)
58#error "USART4 used by multiple drivers"
59#endif
60
61#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART5) && \
62 (HAL_USE_UART && STM32_UART_USE_UART5)
63#error "USART5 used by multiple drivers"
64#endif
65
66#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART4) || \
67 (HAL_USE_UART && STM32_UART_USE_UART4)
68#define STM32_USART4_IS_USED TRUE
69#else
70#define STM32_USART4_IS_USED FALSE
71#endif
72
73#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART5) || \
74 (HAL_USE_UART && STM32_UART_USE_UART45)
75#define STM32_USART5_IS_USED TRUE
76#else
77#define STM32_USART5_IS_USED FALSE
78#endif
79
80/*===========================================================================*/
81/* Driver exported variables. */
82/*===========================================================================*/
83
84/*===========================================================================*/
85/* Driver local variables. */
86/*===========================================================================*/
87
88/*===========================================================================*/
89/* Driver local functions. */
90/*===========================================================================*/
91
92static inline void usart4_usart5_irq_init(void) {
93#if STM32_USART4_IS_USED || STM32_USART5_IS_USED
94 nvicEnableVector(STM32_USART4_5_NUMBER, STM32_IRQ_USART4_5_PRIORITY);
95#endif
96}
97
98static inline void usart4_usart5_irq_deinit(void) {
99#if STM32_USART4_IS_USED || STM32_USART5_IS_USED
100 nvicDisableVector(STM32_USART4_5_NUMBER);
101#endif
102}
103
104/*===========================================================================*/
105/* Driver interrupt handlers. */
106/*===========================================================================*/
107
108#if STM32_USART4_IS_USED || STM32_USART5_IS_USED || \
109 defined(__DOXYGEN__)
110/**
111 * @brief USART4, USART5, LPUART1 interrupt handler.
112 *
113 * @isr
114 */
115OSAL_IRQ_HANDLER(STM32_USART4_5_HANDLER) {
116
117 OSAL_IRQ_PROLOGUE();
118
119#if HAL_USE_SERIAL
120#if STM32_SERIAL_USE_UART4
121 sd_lld_serve_interrupt(&SD4);
122#endif
123#if STM32_SERIAL_USE_UART5
124 sd_lld_serve_interrupt(&SD5);
125#endif
126#endif
127#if HAL_USE_UART
128#if STM32_UART_USE_UART4
129 uart_lld_serve_interrupt(&UARTD4);
130#endif
131#if STM32_UART_USE_UART5
132 uart_lld_serve_interrupt(&UARTD5);
133#endif
134#endif
135
136 OSAL_IRQ_EPILOGUE();
137}
138#endif
139
140/*===========================================================================*/
141/* Driver exported functions. */
142/*===========================================================================*/
143
144/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart6.inc b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart6.inc
new file mode 100644
index 000000000..ea812a8e9
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/LLD/USARTv2/stm32_usart6.inc
@@ -0,0 +1,121 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file USARTv2/stm32_usart6.inc
19 * @brief Shared USART6 handler.
20 *
21 * @addtogroup STM32_USART6_HANDLER
22 * @{
23 */
24
25/*===========================================================================*/
26/* Driver local definitions. */
27/*===========================================================================*/
28
29/*===========================================================================*/
30/* Derived constants and error checks. */
31/*===========================================================================*/
32
33/* Registry checks for robustness.*/
34#if !defined(STM32_HAS_USART6)
35#error "STM32_HAS_USART6 not defined in registry"
36#endif
37
38#if STM32_HAS_USART6
39
40/* Priority settings checks.*/
41#if !defined(STM32_IRQ_USART6_PRIORITY)
42#error "STM32_IRQ_USART6_PRIORITY not defined in mcuconf.h"
43#endif
44
45#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART6_PRIORITY)
46#error "Invalid IRQ priority assigned to STM32_IRQ_USART6_PRIORITY"
47#endif
48
49#endif /* STM32_HAS_USART6 */
50
51/* Other checks.*/
52#if (HAL_USE_SERIAL && STM32_SERIAL_USE_USART6) && \
53 (HAL_USE_UART && STM32_UART_USE_USART6)
54#error "USART6 used by multiple drivers"
55#endif
56
57#if (HAL_USE_SERIAL && STM32_SERIAL_USE_USART6) || \
58 (HAL_USE_UART && STM32_UART_USE_USART6)
59#define STM32_USART6_IS_USED TRUE
60#else
61#define STM32_USART6_IS_USED FALSE
62#endif
63
64/*===========================================================================*/
65/* Driver exported variables. */
66/*===========================================================================*/
67
68/*===========================================================================*/
69/* Driver local variables. */
70/*===========================================================================*/
71
72/*===========================================================================*/
73/* Driver local functions. */
74/*===========================================================================*/
75
76static inline void usart6_irq_init(void) {
77#if STM32_USART6_IS_USED
78 nvicEnableVector(STM32_USART6_NUMBER, STM32_IRQ_USART6_PRIORITY);
79#endif
80}
81
82static inline void usart6_irq_deinit(void) {
83#if STM32_USART6_IS_USED
84 nvicDisableVector(STM32_USART6_NUMBER);
85#endif
86}
87
88/*===========================================================================*/
89/* Driver interrupt handlers. */
90/*===========================================================================*/
91
92#if STM32_USART6_IS_USED || defined(__DOXYGEN__)
93/**
94 * @brief USART6 interrupt handler.
95 *
96 * @isr
97 */
98OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) {
99
100 OSAL_IRQ_PROLOGUE();
101
102#if HAL_USE_SERIAL
103#if STM32_SERIAL_USE_USART6
104 sd_lld_serve_interrupt(&SD6);
105#endif
106#endif
107#if HAL_USE_UART
108#if STM32_UART_USE_USART6
109 uart_lld_serve_interrupt(&UARTD6);
110#endif
111#endif
112
113 OSAL_IRQ_EPILOGUE();
114}
115#endif
116
117/*===========================================================================*/
118/* Driver exported functions. */
119/*===========================================================================*/
120
121/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 23:12:08 +0100