1 files changed, 235 insertions, 0 deletions

diff --git a/lib/chibios/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c b/lib/chibios/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c
new file mode 100644
index 000000000..ac44ea553
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c
@@ -0,0 +1,235 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F1xx/hal_adc_lld.c
+ * @brief   STM32F1xx ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Shared ADC DMA ISR service routine.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+  if ((flags & STM32_DMA_ISR_TEIF) != 0) {
+    /* DMA, this could help only if the DMA tries to access an unmapped
+       address space or violates alignment rules.*/
+    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
+  }
+  else {
+    if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+      /* Transfer complete processing.*/
+      _adc_isr_full_code(adcp);
+    }
+    else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+      /* Half transfer processing.*/
+      _adc_isr_half_code(adcp);
+    }
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if STM32_ADC_USE_ADC1
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD1);
+  ADCD1.adc = ADC1;
+  ADCD1.dmastp  = NULL;
+  ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
+                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_TEIE;
+
+  /* Temporary activation.*/
+  rccEnableADC1(true);
+  ADC1->CR1 = 0;
+  ADC1->CR2 = ADC_CR2_ADON;
+
+  /* Reset calibration just to be safe.*/
+  ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
+  while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
+    ;
+
+  /* Calibration.*/
+  ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
+  while ((ADC1->CR2 & ADC_CR2_CAL) != 0)
+    ;
+
+  /* Return the ADC in low power mode.*/
+  ADC1->CR2 = 0;
+  rccDisableADC1();
+#endif
+}
+
+/**
+ * @brief   Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+  /* If in stopped state then enables the ADC and DMA clocks.*/
+  if (adcp->state == ADC_STOP) {
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp) {
+      adcp->dmastp = dmaStreamAllocI(STM32_DMA_STREAM_ID(1, 1),
+                                     STM32_ADC_ADC1_IRQ_PRIORITY,
+                                     (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
+                                     (void *)adcp);
+      osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
+      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
+      rccEnableADC1(true);
+    }
+#endif
+
+    /* ADC setup, the calibration procedure has already been performed
+       during initialization.*/
+    adcp->adc->CR1 = 0;
+    adcp->adc->CR2 = 0;
+  }
+}
+
+/**
+ * @brief   Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+  /* If in ready state then disables the ADC clock.*/
+  if (adcp->state == ADC_READY) {
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp) {
+      ADC1->CR1 = 0;
+      ADC1->CR2 = 0;
+
+      dmaStreamFreeI(adcp->dmastp);
+      adcp->dmastp = NULL;
+
+      rccDisableADC1();
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Starts an ADC conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+  uint32_t mode, cr2;
+  const ADCConversionGroup *grpp = adcp->grpp;
+
+  /* DMA setup.*/
+  mode = adcp->dmamode;
+  if (grpp->circular) {
+    mode |= STM32_DMA_CR_CIRC;
+    if (adcp->depth > 1) {
+      /* If circular buffer depth > 1, then the half transfer interrupt
+         is enabled in order to allow streaming processing.*/
+      mode |= STM32_DMA_CR_HTIE;
+    }
+  }
+  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
+  dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
+                                            (uint32_t)adcp->depth);
+  dmaStreamSetMode(adcp->dmastp, mode);
+  dmaStreamEnable(adcp->dmastp);
+
+  /* ADC setup.*/
+  adcp->adc->CR1   = grpp->cr1 | ADC_CR1_SCAN;
+  cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
+  if ((cr2 & (ADC_CR2_EXTTRIG | ADC_CR2_JEXTTRIG)) == 0)
+    cr2 |= ADC_CR2_CONT;
+  adcp->adc->CR2   = grpp->cr2 | cr2;
+  adcp->adc->SMPR1 = grpp->smpr1;
+  adcp->adc->SMPR2 = grpp->smpr2;
+  adcp->adc->SQR1  = grpp->sqr1;
+  adcp->adc->SQR2  = grpp->sqr2;
+  adcp->adc->SQR3  = grpp->sqr3;
+
+  /* ADC start by writing ADC_CR2_ADON a second time.*/
+  adcp->adc->CR2   = cr2;
+}
+
+/**
+ * @brief   Stops an ongoing conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+
+  dmaStreamDisable(adcp->dmastp);
+  adcp->adc->CR2 = 0;
+}
+
+#endif /* HAL_USE_ADC */
+
+/** @} */