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diff --git a/lib/chibios/os/hal/ports/STM32/STM32F1xx/hal_lld.h b/lib/chibios/os/hal/ports/STM32/STM32F1xx/hal_lld.h
new file mode 100644
index 000000000..a26c32aeb
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F1xx/hal_lld.h
@@ -0,0 +1,226 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F1xx/hal_lld.h
+ * @brief   STM32F1xx HAL subsystem low level driver header.
+ * @pre     This module requires the following macros to be defined in the
+ *          @p board.h file:
+ *          - STM32_LSECLK.
+ *          - STM32_LSE_BYPASS (optionally).
+ *          - STM32_HSECLK.
+ *          - STM32_HSE_BYPASS (optionally).
+ *          .
+ *          One of the following macros must also be defined:
+ *          - STM32F100xB for Value Line Medium Density devices.
+ *          - STM32F100xE for Value Line High Density devices.
+ *          - STM32F101x6, STM32F102x6, STM32F103x6 for Performance
+ *            Low Density devices.
+ *          - STM32F101xB, STM32F102xB, STM32F103xB for Performance
+ *            Medium Density devices.
+ *          - STM32F101xE, STM32F103xE for Performance High Density devices.
+ *          - STM32F101xG, STM32F103xG for Performance eXtra Density devices.
+ *          - STM32F105xC, STM32F107xC for Connectivity Line devices.
+ *          .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Platform identification
+ * @{
+ */
+#if defined(__DOXYGEN__)
+#define PLATFORM_NAME           "STM32F1xx"
+
+#elif defined(STM32F10X_MD_VL)
+#define PLATFORM_NAME           "STM32F100 Value Line Medium Density"
+
+#elif defined(STM32F10X_HD_VL)
+#define PLATFORM_NAME           "STM32F100 Value Line High Density"
+
+#elif defined(STM32F10X_LD)
+#define PLATFORM_NAME           "STM32F10x Performance Line Low Density"
+
+#elif defined(STM32F10X_MD)
+#define PLATFORM_NAME           "STM32F10x Performance Line Medium Density"
+
+#elif defined(STM32F10X_HD)
+#define PLATFORM_NAME           "STM32F10x Performance Line High Density"
+
+#elif defined(STM32F10X_XL)
+#define PLATFORM_NAME           "STM32F10x Performance Line eXtra Density"
+
+#elif defined(STM32F10X_CL)
+#define PLATFORM_NAME           "STM32F10x Connectivity Line"
+
+#else
+#error "unsupported or unrecognized STM32F1xx member"
+#endif
+
+/**
+ * @brief   Sub-family identifier.
+ */
+#if !defined(STM32F1XX) || defined(__DOXYGEN__)
+#define STM32F1XX
+#endif
+/** @} */
+
+/**
+ * @name    Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK            8000000     /**< High speed internal clock. */
+#define STM32_LSICLK            40000       /**< Low speed internal clock.  */
+/** @} */
+
+/**
+ * @name    PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */
+#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */
+#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */
+#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 2.               */
+#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 3.               */
+#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 4.               */
+#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 5.               */
+#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 6.               */
+#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
+/** @} */
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT               FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE            FALSE
+#endif
+
+/**
+ * @brief   Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS                   STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief   Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED           TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED           FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED           TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED           FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL) ||                 \
+    defined(__DOXYGEN__)
+#include "hal_lld_f100.h"
+
+#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) ||                     \
+      defined(STM32F10X_HD) || defined(STM32F10X_XL) ||                     \
+      defined(__DOXYGEN__)
+#include "hal_lld_f103.h"
+
+#elif defined(STM32F10X_CL) || defined(__DOXYGEN__)
+#include "hal_lld_f105_f107.h"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "cache.h"
+#include "mpu_v7m.h"
+#include "stm32_isr.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+#include "stm32_tim.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void hal_lld_init(void);
+  void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */