1 files changed, 604 insertions, 0 deletions
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h b/lib/chibios/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h
new file mode 100644
index 000000000..24724a4f8
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h
@@ -0,0 +1,604 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/**
+ * @defgroup STM32F103_HAL STM32F103 HAL Support
+ * @details HAL support for STM32 Performance Line LD, MD and HD sub-families.
+ *
+ * @ingroup HAL
+ */
+/**
+ * @file    STM32F1xx/hal_lld_f103.h
+ * @brief   STM32F103 Performance Line HAL subsystem low level driver header.
+ *
+ * @addtogroup STM32F103_HAL
+ * @{
+ */
+#ifndef _HAL_LLD_F103_H_
+#define _HAL_LLD_F103_H_
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+/**
+ * @name    Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief   Maximum system clock frequency.
+ */
+#define STM32_SYSCLK_MAX        72000000
+/**
+ * @brief   Maximum HSE clock frequency.
+ */
+#define STM32_HSECLK_MAX        25000000
+/**
+ * @brief   Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN        1000000
+/**
+ * @brief   Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX        1000000
+/**
+ * @brief   Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN        32768
+/**
+ * @brief   Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX         25000000
+/**
+ * @brief   Minimum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN         1000000
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MAX        72000000
+/**
+ * @brief   Minimum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MIN        16000000
+/**
+ * @brief   Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX         36000000
+/**
+ * @brief   Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX         72000000
+/**
+ * @brief   Maximum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MAX        14000000
+/** @} */
+/**
+ * @name    RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
+#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
+#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
+#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
+#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
+#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
+#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
+#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
+#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
+#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
+#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
+#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
+#define STM32_PPRE1_DIV1        (0 << 8)    /**< HCLK divided by 1.         */
+#define STM32_PPRE1_DIV2        (4 << 8)    /**< HCLK divided by 2.         */
+#define STM32_PPRE1_DIV4        (5 << 8)    /**< HCLK divided by 4.         */
+#define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
+#define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
+#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */
+#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */
+#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */
+#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */
+#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */
+#define STM32_ADCPRE_DIV2       (0 << 14)   /**< PPRE2 divided by 2.        */
+#define STM32_ADCPRE_DIV4       (1 << 14)   /**< PPRE2 divided by 4.        */
+#define STM32_ADCPRE_DIV6       (2 << 14)   /**< PPRE2 divided by 6.        */
+#define STM32_ADCPRE_DIV8       (3 << 14)   /**< PPRE2 divided by 8.        */
+#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI.   */
+#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is HSE.   */
+#define STM32_PLLXTPRE_DIV1     (0 << 17)   /**< HSE divided by 1.          */
+#define STM32_PLLXTPRE_DIV2     (1 << 17)   /**< HSE divided by 2.          */
+#define STM32_USBPRE_DIV1P5     (0 << 22)   /**< PLLOUT divided by 1.5.     */
+#define STM32_USBPRE_DIV1       (1 << 22)   /**< PLLOUT divided by 1.       */
+#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
+#define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
+#define STM32_MCOSEL_HSI        (5 << 24)   /**< HSI clock on MCO pin.      */
+#define STM32_MCOSEL_HSE        (6 << 24)   /**< HSE clock on MCO pin.      */
+#define STM32_MCOSEL_PLLDIV2    (7 << 24)   /**< PLL/2 clock on MCO pin.    */
+/** @} */
+/**
+ * @name    RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC clock source mask.     */
+#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No clock.                  */
+#define STM32_RTCSEL_LSE        (1 << 8)    /**< LSE used as RTC clock.     */
+#define STM32_RTCSEL_LSI        (2 << 8)    /**< LSI used as RTC clock.     */
+#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< HSE divided by 128 used as
+                                                 RTC clock.                 */
+/** @} */
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Main clock source selection.
+ * @note    If the selected clock source is not the PLL then the PLL is not
+ *          initialized and started.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW                    STM32_SW_PLL
+#endif
+/**
+ * @brief   Clock source for the PLL.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC                STM32_PLLSRC_HSE
+#endif
+/**
+ * @brief   Crystal PLL pre-divider.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
+#define STM32_PLLXTPRE              STM32_PLLXTPRE_DIV1
+#endif
+/**
+ * @brief   PLL multiplier value.
+ * @note    The allowed range is 2...16.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE          9
+#endif
+/**
+ * @brief   AHB prescaler value.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE                  STM32_HPRE_DIV1
+#endif
+/**
+ * @brief   APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1                 STM32_PPRE1_DIV2
+#endif
+/**
+ * @brief   APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2                 STM32_PPRE2_DIV2
+#endif
+/**
+ * @brief   ADC prescaler value.
+ */
+#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
+#define STM32_ADCPRE                STM32_ADCPRE_DIV4
+#endif
+/**
+ * @brief   USB clock setting.
+ */
+#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
+#define STM32_USB_CLOCK_REQUIRED    TRUE
+#endif
+/**
+ * @brief   USB prescaler initialization.
+ */
+#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
+#define STM32_USBPRE                STM32_USBPRE_DIV1P5
+#endif
+/**
+ * @brief   MCO pin setting.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL                STM32_MCOSEL_NOCLOCK
+#endif
+/**
+ * @brief   RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL                STM32_RTCSEL_LSI
+#endif
+/** @} */
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F103_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F103_MCUCONF not defined"
+#endif
+/*
+ * HSI related checks.
+ */
+#if STM32_HSI_ENABLED
+#else /* !STM32_HSI_ENABLED */
+#if STM32_SW == STM32_SW_HSI
+#error "HSI not enabled, required by STM32_SW"
+#endif
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "HSI not enabled, required by STM32_MCOSEL"
+#endif
+#endif /* !STM32_HSI_ENABLED */
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+#if STM32_HSECLK == 0
+#error "HSE frequency not defined"
+#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+#else /* !STM32_HSE_ENABLED */
+#if STM32_SW == STM32_SW_HSE
+#error "HSE not enabled, required by STM32_SW"
+#endif
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCOSEL"
+#endif
+#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#error "HSE not enabled, required by STM32_RTCSEL"
+#endif
+#endif /* !STM32_HSE_ENABLED */
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+#if HAL_USE_RTC && (STM32_RTCSEL == STM32_RTCSEL_LSI)
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+#endif /* !STM32_LSI_ENABLED */
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+#if (STM32_LSECLK == 0)
+#error "LSE frequency not defined"
+#endif
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+#else /* !STM32_LSE_ENABLED */
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+#endif /* !STM32_LSE_ENABLED */
+/* PLL activation conditions.*/
+#if STM32_USB_CLOCK_REQUIRED ||                                             \
+    (STM32_SW == STM32_SW_PLL) ||                                           \
+    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
+    defined(__DOXYGEN__)
+/**
+ * @brief   PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL          TRUE
+#else
+#define STM32_ACTIVATE_PLL          FALSE
+#endif
+/* HSE prescaler setting check.*/
+#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) &&                              \
+    (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
+#error "invalid STM32_PLLXTPRE value specified"
+#endif
+/**
+ * @brief   PLLMUL field.
+ */
+#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) ||            \
+    defined(__DOXYGEN__)
+#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+/**
+ * @brief   PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
+#define STM32_PLLCLKIN              (STM32_HSECLK / 1)
+#else
+#define STM32_PLLCLKIN              (STM32_HSECLK / 2)
+#endif
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+/**
+ * @brief   PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
+#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
+#endif
+/**
+ * @brief   System clock source.
+ */
+#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
+#define STM32_SYSCLK                STM32_PLLCLKOUT
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK                STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK                STM32_HSECLK
+#else
+#error "invalid STM32_SW value specified"
+#endif
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+/**
+ * @brief   AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK                  (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK                  (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK                  (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK                  (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK                  (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK                  (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK                  (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK                  (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK                  (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+/**
+ * @brief   APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1                 (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1                 (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1                 (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1                 (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1                 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+/* APB1 frequency check.*/
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+/**
+ * @brief   APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2                 (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2                 (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2                 (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2                 (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2                 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+/* APB2 frequency check.*/
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+/**
+ * @brief   RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
+#define STM32_RTCCLK                STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK                STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK                (STM32_HSECLK / 128)
+#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+#define STM32_RTCCLK                0
+#else
+#error "invalid source selected for RTC clock"
+#endif
+/**
+ * @brief   ADC frequency.
+ */
+#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_ADCCLK                (STM32_PCLK2 / 2)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
+#define STM32_ADCCLK                (STM32_PCLK2 / 4)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
+#define STM32_ADCCLK                (STM32_PCLK2 / 6)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
+#define STM32_ADCCLK                (STM32_PCLK2 / 8)
+#else
+#error "invalid STM32_ADCPRE value specified"
+#endif
+/* ADC frequency check.*/
+#if STM32_ADCCLK > STM32_ADCCLK_MAX
+#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+/**
+ * @brief   USB frequency.
+ */
+#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
+#define STM32_USBCLK                ((STM32_PLLCLKOUT * 2) / 3)
+#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
+#define STM32_USBCLK                STM32_PLLCLKOUT
+#else
+#error "invalid STM32_USBPRE value specified"
+#endif
+/**
+ * @brief   Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
+#endif
+/**
+ * @brief   Timers 1, 8, 9, 10, 11 clock.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
+#endif
+/**
+ * @brief   Flash settings.
+ */
+#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS             0x00000010
+#elif STM32_HCLK <= 48000000
+#define STM32_FLASHBITS             0x00000011
+#else
+#define STM32_FLASHBITS             0x00000012
+#endif
+#endif /* _HAL_LLD_F103_H_ */
+/** @} */

diff --git a/lib/chibios/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h b/lib/chibios/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h new file mode 100644 index 000000000..24724a4f8 --- /dev/null +++ b/lib/chibios/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h
@@ -0,0 +1,604 @@
	1	/*
	2	ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
	3
	4	Licensed under the Apache License, Version 2.0 (the "License");
	5	you may not use this file except in compliance with the License.
	6	You may obtain a copy of the License at
	7
	8	http://www.apache.org/licenses/LICENSE-2.0
	9
	10	Unless required by applicable law or agreed to in writing, software
	11	distributed under the License is distributed on an "AS IS" BASIS,
	12	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
	13	See the License for the specific language governing permissions and
	14	limitations under the License.
	15	*/
	16
	17	/**
	18	* @defgroup STM32F103_HAL STM32F103 HAL Support
	19	* @details HAL support for STM32 Performance Line LD, MD and HD sub-families.
	20	*
	21	* @ingroup HAL
	22	*/
	23
	24	/**
	25	* @file STM32F1xx/hal_lld_f103.h
	26	* @brief STM32F103 Performance Line HAL subsystem low level driver header.
	27	*
	28	* @addtogroup STM32F103_HAL
	29	* @{
	30	*/
	31
	32	#ifndef _HAL_LLD_F103_H_
	33	#define _HAL_LLD_F103_H_
	34
	35	/===========================================================================/
	36	/* Driver constants. */
	37	/===========================================================================/
	38
	39	/**
	40	* @name Absolute Maximum Ratings
	41	* @{
	42	*/
	43	/**
	44	* @brief Maximum system clock frequency.
	45	*/
	46	#define STM32_SYSCLK_MAX 72000000
	47
	48	/**
	49	* @brief Maximum HSE clock frequency.
	50	*/
	51	#define STM32_HSECLK_MAX 25000000
	52
	53	/**
	54	* @brief Minimum HSE clock frequency.
	55	*/
	56	#define STM32_HSECLK_MIN 1000000
	57
	58	/**
	59	* @brief Maximum LSE clock frequency.
	60	*/
	61	#define STM32_LSECLK_MAX 1000000
	62
	63	/**
	64	* @brief Minimum LSE clock frequency.
	65	*/
	66	#define STM32_LSECLK_MIN 32768
	67
	68	/**
	69	* @brief Maximum PLLs input clock frequency.
	70	*/
	71	#define STM32_PLLIN_MAX 25000000
	72
	73	/**
	74	* @brief Minimum PLLs input clock frequency.
	75	*/
	76	#define STM32_PLLIN_MIN 1000000
	77
	78	/**
	79	* @brief Maximum PLL output clock frequency.
	80	*/
	81	#define STM32_PLLOUT_MAX 72000000
	82
	83	/**
	84	* @brief Minimum PLL output clock frequency.
	85	*/
	86	#define STM32_PLLOUT_MIN 16000000
	87
	88	/**
	89	* @brief Maximum APB1 clock frequency.
	90	*/
	91	#define STM32_PCLK1_MAX 36000000
	92
	93	/**
	94	* @brief Maximum APB2 clock frequency.
	95	*/
	96	#define STM32_PCLK2_MAX 72000000
	97
	98	/**
	99	* @brief Maximum ADC clock frequency.
	100	*/
	101	#define STM32_ADCCLK_MAX 14000000
	102	/** @} */
	103
	104	/**
	105	* @name RCC_CFGR register bits definitions
	106	* @{
	107	*/
	108	#define STM32_SW_HSI (0 << 0) /*< SYSCLK source is HSI. /
	109	#define STM32_SW_HSE (1 << 0) /*< SYSCLK source is HSE. /
	110	#define STM32_SW_PLL (2 << 0) /*< SYSCLK source is PLL. /
	111
	112	#define STM32_HPRE_DIV1 (0 << 4) /*< SYSCLK divided by 1. /
	113	#define STM32_HPRE_DIV2 (8 << 4) /*< SYSCLK divided by 2. /
	114	#define STM32_HPRE_DIV4 (9 << 4) /*< SYSCLK divided by 4. /
	115	#define STM32_HPRE_DIV8 (10 << 4) /*< SYSCLK divided by 8. /
	116	#define STM32_HPRE_DIV16 (11 << 4) /*< SYSCLK divided by 16. /
	117	#define STM32_HPRE_DIV64 (12 << 4) /*< SYSCLK divided by 64. /
	118	#define STM32_HPRE_DIV128 (13 << 4) /*< SYSCLK divided by 128. /
	119	#define STM32_HPRE_DIV256 (14 << 4) /*< SYSCLK divided by 256. /
	120	#define STM32_HPRE_DIV512 (15 << 4) /*< SYSCLK divided by 512. /
	121
	122	#define STM32_PPRE1_DIV1 (0 << 8) /*< HCLK divided by 1. /
	123	#define STM32_PPRE1_DIV2 (4 << 8) /*< HCLK divided by 2. /
	124	#define STM32_PPRE1_DIV4 (5 << 8) /*< HCLK divided by 4. /
	125	#define STM32_PPRE1_DIV8 (6 << 8) /*< HCLK divided by 8. /
	126	#define STM32_PPRE1_DIV16 (7 << 8) /*< HCLK divided by 16. /
	127
	128	#define STM32_PPRE2_DIV1 (0 << 11) /*< HCLK divided by 1. /
	129	#define STM32_PPRE2_DIV2 (4 << 11) /*< HCLK divided by 2. /
	130	#define STM32_PPRE2_DIV4 (5 << 11) /*< HCLK divided by 4. /
	131	#define STM32_PPRE2_DIV8 (6 << 11) /*< HCLK divided by 8. /
	132	#define STM32_PPRE2_DIV16 (7 << 11) /*< HCLK divided by 16. /
	133
	134	#define STM32_ADCPRE_DIV2 (0 << 14) /*< PPRE2 divided by 2. /
	135	#define STM32_ADCPRE_DIV4 (1 << 14) /*< PPRE2 divided by 4. /
	136	#define STM32_ADCPRE_DIV6 (2 << 14) /*< PPRE2 divided by 6. /
	137	#define STM32_ADCPRE_DIV8 (3 << 14) /*< PPRE2 divided by 8. /
	138
	139	#define STM32_PLLSRC_HSI (0 << 16) /*< PLL clock source is HSI. /
	140	#define STM32_PLLSRC_HSE (1 << 16) /*< PLL clock source is HSE. /
	141
	142	#define STM32_PLLXTPRE_DIV1 (0 << 17) /*< HSE divided by 1. /
	143	#define STM32_PLLXTPRE_DIV2 (1 << 17) /*< HSE divided by 2. /
	144
	145	#define STM32_USBPRE_DIV1P5 (0 << 22) /*< PLLOUT divided by 1.5. /
	146	#define STM32_USBPRE_DIV1 (1 << 22) /*< PLLOUT divided by 1. /
	147
	148	#define STM32_MCOSEL_NOCLOCK (0 << 24) /*< No clock on MCO pin. /
	149	#define STM32_MCOSEL_SYSCLK (4 << 24) /*< SYSCLK on MCO pin. /
	150	#define STM32_MCOSEL_HSI (5 << 24) /*< HSI clock on MCO pin. /
	151	#define STM32_MCOSEL_HSE (6 << 24) /*< HSE clock on MCO pin. /
	152	#define STM32_MCOSEL_PLLDIV2 (7 << 24) /*< PLL/2 clock on MCO pin. /
	153	/** @} */
	154
	155	/**
	156	* @name RCC_BDCR register bits definitions
	157	* @{
	158	*/
	159	#define STM32_RTCSEL_MASK (3 << 8) /*< RTC clock source mask. /
	160	#define STM32_RTCSEL_NOCLOCK (0 << 8) /*< No clock. /
	161	#define STM32_RTCSEL_LSE (1 << 8) /*< LSE used as RTC clock. /
	162	#define STM32_RTCSEL_LSI (2 << 8) /*< LSI used as RTC clock. /
	163	#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
	164	RTC clock. */
	165	/** @} */
	166
	167	/===========================================================================/
	168	/* Driver pre-compile time settings. */
	169	/===========================================================================/
	170
	171	/**
	172	* @name Configuration options
	173	* @{
	174	*/
	175	/**
	176	* @brief Main clock source selection.
	177	* @note If the selected clock source is not the PLL then the PLL is not
	178	* initialized and started.
	179	* @note The default value is calculated for a 72MHz system clock from
	180	* a 8MHz crystal using the PLL.
	181	*/
	182	#if !defined(STM32_SW) \|\| defined(__DOXYGEN__)
	183	#define STM32_SW STM32_SW_PLL
	184	#endif
	185
	186	/**
	187	* @brief Clock source for the PLL.
	188	* @note This setting has only effect if the PLL is selected as the
	189	* system clock source.
	190	* @note The default value is calculated for a 72MHz system clock from
	191	* a 8MHz crystal using the PLL.
	192	*/
	193	#if !defined(STM32_PLLSRC) \|\| defined(__DOXYGEN__)
	194	#define STM32_PLLSRC STM32_PLLSRC_HSE
	195	#endif
	196
	197	/**
	198	* @brief Crystal PLL pre-divider.
	199	* @note This setting has only effect if the PLL is selected as the
	200	* system clock source.
	201	* @note The default value is calculated for a 72MHz system clock from
	202	* a 8MHz crystal using the PLL.
	203	*/
	204	#if !defined(STM32_PLLXTPRE) \|\| defined(__DOXYGEN__)
	205	#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
	206	#endif
	207
	208	/**
	209	* @brief PLL multiplier value.
	210	* @note The allowed range is 2...16.
	211	* @note The default value is calculated for a 72MHz system clock from
	212	* a 8MHz crystal using the PLL.
	213	*/
	214	#if !defined(STM32_PLLMUL_VALUE) \|\| defined(__DOXYGEN__)
	215	#define STM32_PLLMUL_VALUE 9
	216	#endif
	217
	218	/**
	219	* @brief AHB prescaler value.
	220	* @note The default value is calculated for a 72MHz system clock from
	221	* a 8MHz crystal using the PLL.
	222	*/
	223	#if !defined(STM32_HPRE) \|\| defined(__DOXYGEN__)
	224	#define STM32_HPRE STM32_HPRE_DIV1
	225	#endif
	226
	227	/**
	228	* @brief APB1 prescaler value.
	229	*/
	230	#if !defined(STM32_PPRE1) \|\| defined(__DOXYGEN__)
	231	#define STM32_PPRE1 STM32_PPRE1_DIV2
	232	#endif
	233
	234	/**
	235	* @brief APB2 prescaler value.
	236	*/
	237	#if !defined(STM32_PPRE2) \|\| defined(__DOXYGEN__)
	238	#define STM32_PPRE2 STM32_PPRE2_DIV2
	239	#endif
	240
	241	/**
	242	* @brief ADC prescaler value.
	243	*/
	244	#if !defined(STM32_ADCPRE) \|\| defined(__DOXYGEN__)
	245	#define STM32_ADCPRE STM32_ADCPRE_DIV4
	246	#endif
	247
	248	/**
	249	* @brief USB clock setting.
	250	*/
	251	#if !defined(STM32_USB_CLOCK_REQUIRED) \|\| defined(__DOXYGEN__)
	252	#define STM32_USB_CLOCK_REQUIRED TRUE
	253	#endif
	254
	255	/**
	256	* @brief USB prescaler initialization.
	257	*/
	258	#if !defined(STM32_USBPRE) \|\| defined(__DOXYGEN__)
	259	#define STM32_USBPRE STM32_USBPRE_DIV1P5
	260	#endif
	261
	262	/**
	263	* @brief MCO pin setting.
	264	*/
	265	#if !defined(STM32_MCOSEL) \|\| defined(__DOXYGEN__)
	266	#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
	267	#endif
	268
	269	/**
	270	* @brief RTC clock source.
	271	*/
	272	#if !defined(STM32_RTCSEL) \|\| defined(__DOXYGEN__)
	273	#define STM32_RTCSEL STM32_RTCSEL_LSI
	274	#endif
	275	/** @} */
	276
	277	/===========================================================================/
	278	/* Derived constants and error checks. */
	279	/===========================================================================/
	280
	281	/*
	282	* Configuration-related checks.
	283	*/
	284	#if !defined(STM32F103_MCUCONF)
	285	#error "Using a wrong mcuconf.h file, STM32F103_MCUCONF not defined"
	286	#endif
	287
	288	/*
	289	* HSI related checks.
	290	*/
	291	#if STM32_HSI_ENABLED
	292	#else /* !STM32_HSI_ENABLED */
	293
	294	#if STM32_SW == STM32_SW_HSI
	295	#error "HSI not enabled, required by STM32_SW"
	296	#endif
	297
	298	#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
	299	#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
	300	#endif
	301
	302	#if (STM32_MCOSEL == STM32_MCOSEL_HSI) \|\| \
	303	((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
	304	(STM32_PLLSRC == STM32_PLLSRC_HSI))
	305	#error "HSI not enabled, required by STM32_MCOSEL"
	306	#endif
	307
	308	#endif /* !STM32_HSI_ENABLED */
	309
	310	/*
	311	* HSE related checks.
	312	*/
	313	#if STM32_HSE_ENABLED
	314
	315	#if STM32_HSECLK == 0
	316	#error "HSE frequency not defined"
	317	#elif (STM32_HSECLK < STM32_HSECLK_MIN) \|\| (STM32_HSECLK > STM32_HSECLK_MAX)
	318	#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
	319	#endif
	320
	321	#else /* !STM32_HSE_ENABLED */
	322
	323	#if STM32_SW == STM32_SW_HSE
	324	#error "HSE not enabled, required by STM32_SW"
	325	#endif
	326
	327	#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
	328	#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
	329	#endif
	330
	331	#if (STM32_MCOSEL == STM32_MCOSEL_HSE) \|\| \
	332	((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
	333	(STM32_PLLSRC == STM32_PLLSRC_HSE))
	334	#error "HSE not enabled, required by STM32_MCOSEL"
	335	#endif
	336
	337	#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
	338	#error "HSE not enabled, required by STM32_RTCSEL"
	339	#endif
	340
	341	#endif /* !STM32_HSE_ENABLED */
	342
	343	/*
	344	* LSI related checks.
	345	*/
	346	#if STM32_LSI_ENABLED
	347	#else /* !STM32_LSI_ENABLED */
	348
	349	#if HAL_USE_RTC && (STM32_RTCSEL == STM32_RTCSEL_LSI)
	350	#error "LSI not enabled, required by STM32_RTCSEL"
	351	#endif
	352
	353	#endif /* !STM32_LSI_ENABLED */
	354
	355	/*
	356	* LSE related checks.
	357	*/
	358	#if STM32_LSE_ENABLED
	359
	360	#if (STM32_LSECLK == 0)
	361	#error "LSE frequency not defined"
	362	#endif
	363
	364	#if (STM32_LSECLK < STM32_LSECLK_MIN) \|\| (STM32_LSECLK > STM32_LSECLK_MAX)
	365	#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
	366	#endif
	367
	368	#else /* !STM32_LSE_ENABLED */
	369
	370	#if STM32_RTCSEL == STM32_RTCSEL_LSE
	371	#error "LSE not enabled, required by STM32_RTCSEL"
	372	#endif
	373
	374	#endif /* !STM32_LSE_ENABLED */
	375
	376	/* PLL activation conditions.*/
	377	#if STM32_USB_CLOCK_REQUIRED \|\| \
	378	(STM32_SW == STM32_SW_PLL) \|\| \
	379	(STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) \|\| \
	380	defined(__DOXYGEN__)
	381	/**
	382	* @brief PLL activation flag.
	383	*/
	384	#define STM32_ACTIVATE_PLL TRUE
	385	#else
	386	#define STM32_ACTIVATE_PLL FALSE
	387	#endif
	388
	389	/* HSE prescaler setting check.*/
	390	#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \
	391	(STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
	392	#error "invalid STM32_PLLXTPRE value specified"
	393	#endif
	394
	395	/**
	396	* @brief PLLMUL field.
	397	*/
	398	#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) \|\| \
	399	defined(__DOXYGEN__)
	400	#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
	401	#else
	402	#error "invalid STM32_PLLMUL_VALUE value specified"
	403	#endif
	404
	405	/**
	406	* @brief PLL input clock frequency.
	407	*/
	408	#if (STM32_PLLSRC == STM32_PLLSRC_HSE) \|\| defined(__DOXYGEN__)
	409	#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
	410	#define STM32_PLLCLKIN (STM32_HSECLK / 1)
	411	#else
	412	#define STM32_PLLCLKIN (STM32_HSECLK / 2)
	413	#endif
	414	#elif STM32_PLLSRC == STM32_PLLSRC_HSI
	415	#define STM32_PLLCLKIN (STM32_HSICLK / 2)
	416	#else
	417	#error "invalid STM32_PLLSRC value specified"
	418	#endif
	419
	420	/* PLL input frequency range check.*/
	421	#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) \|\| (STM32_PLLCLKIN > STM32_PLLIN_MAX)
	422	#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
	423	#endif
	424
	425	/**
	426	* @brief PLL output clock frequency.
	427	*/
	428	#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
	429
	430	/* PLL output frequency range check.*/
	431	#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) \|\| (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
	432	#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
	433	#endif
	434
	435	/**
	436	* @brief System clock source.
	437	*/
	438	#if (STM32_SW == STM32_SW_PLL) \|\| defined(__DOXYGEN__)
	439	#define STM32_SYSCLK STM32_PLLCLKOUT
	440	#elif (STM32_SW == STM32_SW_HSI)
	441	#define STM32_SYSCLK STM32_HSICLK
	442	#elif (STM32_SW == STM32_SW_HSE)
	443	#define STM32_SYSCLK STM32_HSECLK
	444	#else
	445	#error "invalid STM32_SW value specified"
	446	#endif
	447
	448	/* Check on the system clock.*/
	449	#if STM32_SYSCLK > STM32_SYSCLK_MAX
	450	#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
	451	#endif
	452
	453	/**
	454	* @brief AHB frequency.
	455	*/
	456	#if (STM32_HPRE == STM32_HPRE_DIV1) \|\| defined(__DOXYGEN__)
	457	#define STM32_HCLK (STM32_SYSCLK / 1)
	458	#elif STM32_HPRE == STM32_HPRE_DIV2
	459	#define STM32_HCLK (STM32_SYSCLK / 2)
	460	#elif STM32_HPRE == STM32_HPRE_DIV4
	461	#define STM32_HCLK (STM32_SYSCLK / 4)
	462	#elif STM32_HPRE == STM32_HPRE_DIV8
	463	#define STM32_HCLK (STM32_SYSCLK / 8)
	464	#elif STM32_HPRE == STM32_HPRE_DIV16
	465	#define STM32_HCLK (STM32_SYSCLK / 16)
	466	#elif STM32_HPRE == STM32_HPRE_DIV64
	467	#define STM32_HCLK (STM32_SYSCLK / 64)
	468	#elif STM32_HPRE == STM32_HPRE_DIV128
	469	#define STM32_HCLK (STM32_SYSCLK / 128)
	470	#elif STM32_HPRE == STM32_HPRE_DIV256
	471	#define STM32_HCLK (STM32_SYSCLK / 256)
	472	#elif STM32_HPRE == STM32_HPRE_DIV512
	473	#define STM32_HCLK (STM32_SYSCLK / 512)
	474	#else
	475	#error "invalid STM32_HPRE value specified"
	476	#endif
	477
	478	/* AHB frequency check.*/
	479	#if STM32_HCLK > STM32_SYSCLK_MAX
	480	#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
	481	#endif
	482
	483	/**
	484	* @brief APB1 frequency.
	485	*/
	486	#if (STM32_PPRE1 == STM32_PPRE1_DIV1) \|\| defined(__DOXYGEN__)
	487	#define STM32_PCLK1 (STM32_HCLK / 1)
	488	#elif STM32_PPRE1 == STM32_PPRE1_DIV2
	489	#define STM32_PCLK1 (STM32_HCLK / 2)
	490	#elif STM32_PPRE1 == STM32_PPRE1_DIV4
	491	#define STM32_PCLK1 (STM32_HCLK / 4)
	492	#elif STM32_PPRE1 == STM32_PPRE1_DIV8
	493	#define STM32_PCLK1 (STM32_HCLK / 8)
	494	#elif STM32_PPRE1 == STM32_PPRE1_DIV16
	495	#define STM32_PCLK1 (STM32_HCLK / 16)
	496	#else
	497	#error "invalid STM32_PPRE1 value specified"
	498	#endif
	499
	500	/* APB1 frequency check.*/
	501	#if STM32_PCLK1 > STM32_PCLK1_MAX
	502	#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
	503	#endif
	504
	505	/**
	506	* @brief APB2 frequency.
	507	*/
	508	#if (STM32_PPRE2 == STM32_PPRE2_DIV1) \|\| defined(__DOXYGEN__)
	509	#define STM32_PCLK2 (STM32_HCLK / 1)
	510	#elif STM32_PPRE2 == STM32_PPRE2_DIV2
	511	#define STM32_PCLK2 (STM32_HCLK / 2)
	512	#elif STM32_PPRE2 == STM32_PPRE2_DIV4
	513	#define STM32_PCLK2 (STM32_HCLK / 4)
	514	#elif STM32_PPRE2 == STM32_PPRE2_DIV8
	515	#define STM32_PCLK2 (STM32_HCLK / 8)
	516	#elif STM32_PPRE2 == STM32_PPRE2_DIV16
	517	#define STM32_PCLK2 (STM32_HCLK / 16)
	518	#else
	519	#error "invalid STM32_PPRE2 value specified"
	520	#endif
	521
	522	/* APB2 frequency check.*/
	523	#if STM32_PCLK2 > STM32_PCLK2_MAX
	524	#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
	525	#endif
	526
	527	/**
	528	* @brief RTC clock.
	529	*/
	530	#if (STM32_RTCSEL == STM32_RTCSEL_LSE) \|\| defined(__DOXYGEN__)
	531	#define STM32_RTCCLK STM32_LSECLK
	532	#elif STM32_RTCSEL == STM32_RTCSEL_LSI
	533	#define STM32_RTCCLK STM32_LSICLK
	534	#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
	535	#define STM32_RTCCLK (STM32_HSECLK / 128)
	536	#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
	537	#define STM32_RTCCLK 0
	538	#else
	539	#error "invalid source selected for RTC clock"
	540	#endif
	541
	542	/**
	543	* @brief ADC frequency.
	544	*/
	545	#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) \|\| defined(__DOXYGEN__)
	546	#define STM32_ADCCLK (STM32_PCLK2 / 2)
	547	#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
	548	#define STM32_ADCCLK (STM32_PCLK2 / 4)
	549	#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
	550	#define STM32_ADCCLK (STM32_PCLK2 / 6)
	551	#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
	552	#define STM32_ADCCLK (STM32_PCLK2 / 8)
	553	#else
	554	#error "invalid STM32_ADCPRE value specified"
	555	#endif
	556
	557	/* ADC frequency check.*/
	558	#if STM32_ADCCLK > STM32_ADCCLK_MAX
	559	#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
	560	#endif
	561
	562	/**
	563	* @brief USB frequency.
	564	*/
	565	#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) \|\| defined(__DOXYGEN__)
	566	#define STM32_USBCLK ((STM32_PLLCLKOUT * 2) / 3)
	567	#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
	568	#define STM32_USBCLK STM32_PLLCLKOUT
	569	#else
	570	#error "invalid STM32_USBPRE value specified"
	571	#endif
	572
	573	/**
	574	* @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
	575	*/
	576	#if (STM32_PPRE1 == STM32_PPRE1_DIV1) \|\| defined(__DOXYGEN__)
	577	#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
	578	#else
	579	#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
	580	#endif
	581
	582	/**
	583	* @brief Timers 1, 8, 9, 10, 11 clock.
	584	*/
	585	#if (STM32_PPRE2 == STM32_PPRE2_DIV1) \|\| defined(__DOXYGEN__)
	586	#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
	587	#else
	588	#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
	589	#endif
	590
	591	/**
	592	* @brief Flash settings.
	593	*/
	594	#if (STM32_HCLK <= 24000000) \|\| defined(__DOXYGEN__)
	595	#define STM32_FLASHBITS 0x00000010
	596	#elif STM32_HCLK <= 48000000
	597	#define STM32_FLASHBITS 0x00000011
	598	#else
	599	#define STM32_FLASHBITS 0x00000012
	600	#endif
	601
	602	#endif /* _HAL_LLD_F103_H_ */
	603
	604	/** @} */