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Diffstat (limited to 'lib/chibios/os/hal/ports/STM32/STM32F3xx/stm32_isr.c')
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diff --git a/lib/chibios/os/hal/ports/STM32/STM32F3xx/stm32_isr.c b/lib/chibios/os/hal/ports/STM32/STM32F3xx/stm32_isr.c
new file mode 100644
index 000000000..f2112492e
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F3xx/stm32_isr.c
@@ -0,0 +1,382 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F3xx/stm32_isr.c
19 * @brief STM32F3xx ISR handler code.
20 *
21 * @addtogroup STM32F3xx_ISR
22 * @{
23 */
24
25#include "hal.h"
26
27/*===========================================================================*/
28/* Driver local definitions. */
29/*===========================================================================*/
30
31/*===========================================================================*/
32/* Driver exported variables. */
33/*===========================================================================*/
34
35/*===========================================================================*/
36/* Driver local variables. */
37/*===========================================================================*/
38
39/*===========================================================================*/
40/* Driver local functions. */
41/*===========================================================================*/
42
43#define exti_serve_irq(pr, channel) { \
44 \
45 if ((pr) & (1U << (channel))) { \
46 _pal_isr_code(channel); \
47 } \
48}
49
50/*===========================================================================*/
51/* Driver interrupt handlers. */
52/*===========================================================================*/
53
54#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__)
55#if !defined(STM32_DISABLE_EXTI0_HANDLER)
56/**
57 * @brief EXTI[0] interrupt handler.
58 *
59 * @isr
60 */
61OSAL_IRQ_HANDLER(Vector58) {
62 uint32_t pr;
63
64 OSAL_IRQ_PROLOGUE();
65
66 pr = EXTI->PR;
67 pr &= EXTI->IMR & (1U << 0);
68 EXTI->PR = pr;
69
70 exti_serve_irq(pr, 0);
71
72 OSAL_IRQ_EPILOGUE();
73}
74#endif
75
76#if !defined(STM32_DISABLE_EXTI1_HANDLER)
77/**
78 * @brief EXTI[1] interrupt handler.
79 *
80 * @isr
81 */
82OSAL_IRQ_HANDLER(Vector5C) {
83 uint32_t pr;
84
85 OSAL_IRQ_PROLOGUE();
86
87 pr = EXTI->PR;
88 pr &= EXTI->IMR & (1U << 1);
89 EXTI->PR = pr;
90
91 exti_serve_irq(pr, 1);
92
93 OSAL_IRQ_EPILOGUE();
94}
95#endif
96
97#if !defined(STM32_DISABLE_EXTI2_HANDLER)
98/**
99 * @brief EXTI[2] interrupt handler.
100 *
101 * @isr
102 */
103OSAL_IRQ_HANDLER(Vector60) {
104 uint32_t pr;
105
106 OSAL_IRQ_PROLOGUE();
107
108 pr = EXTI->PR;
109 pr &= EXTI->IMR & (1U << 2);
110 EXTI->PR = pr;
111
112 exti_serve_irq(pr, 2);
113
114 OSAL_IRQ_EPILOGUE();
115}
116#endif
117
118#if !defined(STM32_DISABLE_EXTI3_HANDLER)
119/**
120 * @brief EXTI[3] interrupt handler.
121 *
122 * @isr
123 */
124OSAL_IRQ_HANDLER(Vector64) {
125 uint32_t pr;
126
127 OSAL_IRQ_PROLOGUE();
128
129 pr = EXTI->PR;
130 pr &= EXTI->IMR & (1U << 3);
131 EXTI->PR = pr;
132
133 exti_serve_irq(pr, 3);
134
135 OSAL_IRQ_EPILOGUE();
136}
137#endif
138
139#if !defined(STM32_DISABLE_EXTI4_HANDLER)
140/**
141 * @brief EXTI[4] interrupt handler.
142 *
143 * @isr
144 */
145OSAL_IRQ_HANDLER(Vector68) {
146 uint32_t pr;
147
148 OSAL_IRQ_PROLOGUE();
149
150 pr = EXTI->PR;
151 pr &= EXTI->IMR & (1U << 4);
152 EXTI->PR = pr;
153
154 exti_serve_irq(pr, 4);
155
156 OSAL_IRQ_EPILOGUE();
157}
158#endif
159
160#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
161/**
162 * @brief EXTI[5]...EXTI[9] interrupt handler.
163 *
164 * @isr
165 */
166OSAL_IRQ_HANDLER(Vector9C) {
167 uint32_t pr;
168
169 OSAL_IRQ_PROLOGUE();
170
171 pr = EXTI->PR;
172 pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
173 (1U << 9));
174 EXTI->PR = pr;
175
176 exti_serve_irq(pr, 5);
177 exti_serve_irq(pr, 6);
178 exti_serve_irq(pr, 7);
179 exti_serve_irq(pr, 8);
180 exti_serve_irq(pr, 9);
181
182 OSAL_IRQ_EPILOGUE();
183}
184#endif
185
186#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
187/**
188 * @brief EXTI[10]...EXTI[15] interrupt handler.
189 *
190 * @isr
191 */
192OSAL_IRQ_HANDLER(VectorE0) {
193 uint32_t pr;
194
195 OSAL_IRQ_PROLOGUE();
196
197 pr = EXTI->PR;
198 pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
199 (1U << 14) | (1U << 15));
200 EXTI->PR = pr;
201
202 exti_serve_irq(pr, 10);
203 exti_serve_irq(pr, 11);
204 exti_serve_irq(pr, 12);
205 exti_serve_irq(pr, 13);
206 exti_serve_irq(pr, 14);
207 exti_serve_irq(pr, 15);
208
209 OSAL_IRQ_EPILOGUE();
210}
211#endif
212#endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */
213
214#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
215/**
216 * @brief TIM1-BRK, TIM15 interrupt handler.
217 *
218 * @isr
219 */
220OSAL_IRQ_HANDLER(VectorA0) {
221
222 OSAL_IRQ_PROLOGUE();
223
224#if HAL_USE_GPT
225#if STM32_GPT_USE_TIM15
226 gpt_lld_serve_interrupt(&GPTD15);
227#endif
228#endif
229#if HAL_USE_ICU
230#if STM32_ICU_USE_TIM15
231 icu_lld_serve_interrupt(&ICUD15);
232#endif
233#endif
234#if HAL_USE_PWM
235#if STM32_PWM_USE_TIM15
236 pwm_lld_serve_interrupt(&PWMD15);
237#endif
238#endif
239
240 OSAL_IRQ_EPILOGUE();
241}
242
243/**
244 * @brief TIM1-UP, TIM16 interrupt handler.
245 *
246 * @isr
247 */
248OSAL_IRQ_HANDLER(VectorA4) {
249
250 OSAL_IRQ_PROLOGUE();
251
252#if HAL_USE_GPT
253#if STM32_GPT_USE_TIM1
254 gpt_lld_serve_interrupt(&GPTD1);
255#endif
256#if STM32_GPT_USE_TIM16
257 gpt_lld_serve_interrupt(&GPTD16);
258#endif
259#endif
260#if HAL_USE_ICU
261#if STM32_ICU_USE_TIM1
262 icu_lld_serve_interrupt(&ICUD1);
263#endif
264#endif
265#if HAL_USE_PWM
266#if STM32_PWM_USE_TIM1
267 pwm_lld_serve_interrupt(&PWMD1);
268#endif
269#if STM32_PWM_USE_TIM16
270 pwm_lld_serve_interrupt(&PWMD16);
271#endif
272#endif
273
274 OSAL_IRQ_EPILOGUE();
275}
276
277/**
278 * @brief TIM1-TRG-COM, TIM17 interrupt handler.
279 *
280 * @isr
281 */
282OSAL_IRQ_HANDLER(VectorA8) {
283
284 OSAL_IRQ_PROLOGUE();
285
286#if HAL_USE_GPT
287#if STM32_GPT_USE_TIM17
288 gpt_lld_serve_interrupt(&GPTD17);
289#endif
290#endif
291#if HAL_USE_ICU
292 /* Not used by ICU.*/
293#endif
294#if HAL_USE_PWM
295#if STM32_PWM_USE_TIM17
296 pwm_lld_serve_interrupt(&PWMD17);
297#endif
298#endif
299
300 OSAL_IRQ_EPILOGUE();
301}
302
303/**
304 * @brief TIM1-CC interrupt handler.
305 *
306 * @isr
307 */
308OSAL_IRQ_HANDLER(VectorAC) {
309
310 OSAL_IRQ_PROLOGUE();
311
312#if HAL_USE_GPT
313 /* Not used by GPT.*/
314#endif
315#if HAL_USE_ICU
316#if STM32_ICU_USE_TIM1
317 icu_lld_serve_interrupt(&ICUD1);
318#endif
319#endif
320#if HAL_USE_PWM
321#if STM32_PWM_USE_TIM1
322 pwm_lld_serve_interrupt(&PWMD1);
323#endif
324#endif
325
326 OSAL_IRQ_EPILOGUE();
327}
328#endif /* HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM */
329
330/*===========================================================================*/
331/* Driver exported functions. */
332/*===========================================================================*/
333
334/**
335 * @brief Enables IRQ sources.
336 *
337 * @notapi
338 */
339void irqInit(void) {
340
341#if HAL_USE_PAL
342 nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY);
343 nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY);
344 nvicEnableVector(EXTI2_TSC_IRQn, STM32_IRQ_EXTI2_PRIORITY);
345 nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY);
346 nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY);
347 nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY);
348 nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY);
349#endif
350#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
351 nvicEnableVector(TIM1_BRK_TIM15_IRQn, STM32_IRQ_TIM1_BRK_TIM15_PRIORITY);
352 nvicEnableVector(TIM1_UP_TIM16_IRQn, STM32_IRQ_TIM1_UP_TIM16_PRIORITY);
353 nvicEnableVector(TIM1_TRG_COM_TIM17_IRQn, STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY);
354 nvicEnableVector(TIM1_CC_IRQn, STM32_IRQ_TIM1_CC_PRIORITY);
355#endif
356}
357
358/**
359 * @brief Disables IRQ sources.
360 *
361 * @notapi
362 */
363void irqDeinit(void) {
364
365#if HAL_USE_PAL
366 nvicDisableVector(EXTI0_IRQn);
367 nvicDisableVector(EXTI1_IRQn);
368 nvicDisableVector(EXTI2_TSC_IRQn);
369 nvicDisableVector(EXTI3_IRQn);
370 nvicDisableVector(EXTI4_IRQn);
371 nvicDisableVector(EXTI9_5_IRQn);
372 nvicDisableVector(EXTI15_10_IRQn);
373#endif
374#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
375 nvicDisableVector(TIM1_BRK_TIM15_IRQn);
376 nvicDisableVector(TIM1_UP_TIM16_IRQn);
377 nvicDisableVector(TIM1_TRG_COM_TIM17_IRQn);
378 nvicDisableVector(TIM1_CC_IRQn);
379#endif
380}
381
382/** @} */
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