aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h')
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h1026
1 files changed, 1026 insertions, 0 deletions
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h b/lib/chibios/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
new file mode 100644
index 000000000..04631cc66
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
@@ -0,0 +1,1026 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F3xx/stm32_rcc.h
19 * @brief RCC helper driver header.
20 * @note This file requires definitions from the ST header file
21 * @p stm32f30x.h.
22 *
23 * @addtogroup STM32F3xx_RCC
24 * @{
25 */
26
27#ifndef STM32_RCC_H
28#define STM32_RCC_H
29
30/*===========================================================================*/
31/* Driver constants. */
32/*===========================================================================*/
33
34/*===========================================================================*/
35/* Driver pre-compile time settings. */
36/*===========================================================================*/
37
38/*===========================================================================*/
39/* Derived constants and error checks. */
40/*===========================================================================*/
41
42/*===========================================================================*/
43/* Driver data structures and types. */
44/*===========================================================================*/
45
46/*===========================================================================*/
47/* Driver macros. */
48/*===========================================================================*/
49
50/**
51 * @name Generic RCC operations
52 * @{
53 */
54/**
55 * @brief Enables the clock of one or more peripheral on the APB1 bus.
56 *
57 * @param[in] mask APB1 peripherals mask
58 * @param[in] lp low power enable flag
59 *
60 * @api
61 */
62#define rccEnableAPB1(mask, lp) { \
63 RCC->APB1ENR |= (mask); \
64 (void)RCC->APB1ENR; \
65}
66
67/**
68 * @brief Disables the clock of one or more peripheral on the APB1 bus.
69 *
70 * @param[in] mask APB1 peripherals mask
71 *
72 * @api
73 */
74#define rccDisableAPB1(mask) { \
75 RCC->APB1ENR &= ~(mask); \
76 (void)RCC->APB1ENR; \
77}
78
79/**
80 * @brief Resets one or more peripheral on the APB1 bus.
81 *
82 * @param[in] mask APB1 peripherals mask
83 *
84 * @api
85 */
86#define rccResetAPB1(mask) { \
87 RCC->APB1RSTR |= (mask); \
88 RCC->APB1RSTR &= ~(mask); \
89 (void)RCC->APB1RSTR; \
90}
91
92/**
93 * @brief Enables the clock of one or more peripheral on the APB2 bus.
94 *
95 * @param[in] mask APB2 peripherals mask
96 * @param[in] lp low power enable flag
97 *
98 * @api
99 */
100#define rccEnableAPB2(mask, lp) { \
101 RCC->APB2ENR |= (mask); \
102 (void)RCC->APB2ENR; \
103}
104
105/**
106 * @brief Disables the clock of one or more peripheral on the APB2 bus.
107 *
108 * @param[in] mask APB2 peripherals mask
109 *
110 * @api
111 */
112#define rccDisableAPB2(mask) { \
113 RCC->APB2ENR &= ~(mask); \
114 (void)RCC->APB2ENR; \
115}
116
117/**
118 * @brief Resets one or more peripheral on the APB2 bus.
119 *
120 * @param[in] mask APB2 peripherals mask
121 *
122 * @api
123 */
124#define rccResetAPB2(mask) { \
125 RCC->APB2RSTR |= (mask); \
126 RCC->APB2RSTR &= ~(mask); \
127 (void)RCC->APB2RSTR; \
128}
129
130/**
131 * @brief Enables the clock of one or more peripheral on the AHB bus.
132 *
133 * @param[in] mask AHB peripherals mask
134 * @param[in] lp low power enable flag
135 *
136 * @api
137 */
138#define rccEnableAHB(mask, lp) { \
139 RCC->AHBENR |= (mask); \
140 (void)RCC->AHBENR; \
141}
142
143/**
144 * @brief Disables the clock of one or more peripheral on the AHB bus.
145 *
146 * @param[in] mask AHB peripherals mask
147 *
148 * @api
149 */
150#define rccDisableAHB(mask) { \
151 RCC->AHBENR &= ~(mask); \
152 (void)RCC->AHBENR; \
153}
154
155/**
156 * @brief Resets one or more peripheral on the AHB bus.
157 *
158 * @param[in] mask AHB peripherals mask
159 *
160 * @api
161 */
162#define rccResetAHB(mask) { \
163 RCC->AHBRSTR |= (mask); \
164 RCC->AHBRSTR &= ~(mask); \
165 (void)RCC->AHBRSTR; \
166}
167/** @} */
168
169/**
170 * @name ADC peripherals specific RCC operations
171 * @{
172 */
173/**
174 * @brief Enables the ADC1/ADC2 peripheral clock.
175 *
176 * @param[in] lp low power enable flag
177 *
178 * @api
179 */
180#if defined(RCC_AHBENR_ADC12EN) || defined(__DOXYGEN__)
181#define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC12EN, lp)
182#else
183#define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC1EN, lp)
184#endif
185
186/**
187 * @brief Disables the ADC1/ADC2 peripheral clock.
188 *
189 * @api
190 */
191#if defined(RCC_AHBENR_ADC12EN) || defined(__DOXYGEN__)
192#define rccDisableADC12() rccDisableAHB(RCC_AHBENR_ADC12EN)
193#else
194#define rccDisableADC12() rccDisableAHB(RCC_AHBENR_ADC1EN)
195#endif
196
197/**
198 * @brief Resets the ADC1/ADC2 peripheral.
199 *
200 * @api
201 */
202#if defined(RCC_AHBRSTR_ADC12RST) || defined(__DOXYGEN__)
203#define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC12RST)
204#else
205#define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC1RST)
206#endif
207
208/**
209 * @brief Enables the ADC3/ADC4 peripheral clock.
210 *
211 * @param[in] lp low power enable flag
212 *
213 * @api
214 */
215#if defined(RCC_AHBENR_ADC34EN) || defined(__DOXYGEN__)
216#define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC34EN, lp)
217#else
218#define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC3EN, lp)
219#endif
220
221/**
222 * @brief Disables the ADC3/ADC4 peripheral clock.
223 *
224 * @api
225 */
226#if defined(RCC_AHBENR_ADC34EN) || defined(__DOXYGEN__)
227#define rccDisableADC34() rccDisableAHB(RCC_AHBENR_ADC34EN)
228#else
229#define rccDisableADC34() rccDisableAHB(RCC_AHBENR_ADC3EN)
230#endif
231
232/**
233 * @brief Resets the ADC3/ADC4 peripheral.
234 *
235 * @api
236 */
237#if defined(RCC_AHBRSTR_ADC34RST) || defined(__DOXYGEN__)
238#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC34RST)
239#else
240#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC3RST)
241#endif
242/** @} */
243
244/**
245 * @name DAC peripheral specific RCC operations
246 * @{
247 */
248/**
249 * @brief Enables the DAC1 peripheral clock.
250 *
251 * @param[in] lp low power enable flag
252 *
253 * @api
254 */
255#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DAC1EN, lp)
256
257/**
258 * @brief Disables the DAC1 peripheral clock.
259 *
260 * @api
261 */
262#define rccDisableDAC1() rccDisableAPB1(RCC_APB1ENR_DAC1EN)
263
264/**
265 * @brief Resets the DAC1 peripheral.
266 *
267 * @api
268 */
269#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DAC1RST)
270
271/**
272 * @brief Enables the DAC1 peripheral clock.
273 *
274 * @param[in] lp low power enable flag
275 *
276 * @api
277 */
278#define rccEnableDAC2(lp) rccEnableAPB1(RCC_APB1ENR_DAC2EN, lp)
279
280/**
281 * @brief Disables the DAC1 peripheral clock.
282 *
283 * @api
284 */
285#define rccDisableDAC2() rccDisableAPB1(RCC_APB1ENR_DAC2EN)
286
287/**
288 * @brief Resets the DAC1 peripheral.
289 *
290 * @api
291 */
292#define rccResetDAC2() rccResetAPB1(RCC_APB1RSTR_DAC2RST)
293/** @} */
294
295/**
296 * @name CAN peripherals specific RCC operations
297 * @{
298 */
299/**
300 * @brief Enables the CAN1 peripheral clock.
301 * @note The @p lp parameter is ignored in this family.
302 *
303 * @param[in] lp low power enable flag
304 *
305 * @api
306 */
307#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CANEN, lp)
308
309/**
310 * @brief Disables the CAN1 peripheral clock.
311 *
312 * @api
313 */
314#define rccDisableCAN1() rccDisableAPB1(RCC_APB1ENR_CANEN)
315
316/**
317 * @brief Resets the CAN1 peripheral.
318 *
319 * @api
320 */
321#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CANRST)
322/** @} */
323
324/**
325 * @name DMA peripheral specific RCC operations
326 * @{
327 */
328/**
329 * @brief Enables the DMA1 peripheral clock.
330 *
331 * @param[in] lp low power enable flag
332 *
333 * @api
334 */
335#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
336
337/**
338 * @brief Disables the DMA1 peripheral clock.
339 *
340 * @api
341 */
342#define rccDisableDMA1() rccDisableAHB(RCC_AHBENR_DMA1EN)
343
344/**
345 * @brief Resets the DMA1 peripheral.
346 *
347 * @api
348 */
349#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
350
351/**
352 * @brief Enables the DMA2 peripheral clock.
353 *
354 * @param[in] lp low power enable flag
355 *
356 * @api
357 */
358#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)
359
360/**
361 * @brief Disables the DMA2 peripheral clock.
362 *
363 * @api
364 */
365#define rccDisableDMA2() rccDisableAHB(RCC_AHBENR_DMA2EN)
366
367/**
368 * @brief Resets the DMA2 peripheral.
369 *
370 * @api
371 */
372#define rccResetDMA2() rccResetAHB(RCC_AHBRSTR_DMA2RST)
373/** @} */
374
375/**
376 * @name PWR interface specific RCC operations
377 * @{
378 */
379/**
380 * @brief Enables the PWR interface clock.
381 * @note The @p lp parameter is ignored in this family.
382 *
383 * @param[in] lp low power enable flag
384 *
385 * @api
386 */
387#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
388
389/**
390 * @brief Disables PWR interface clock.
391 *
392 * @api
393 */
394#define rccDisablePWRInterface() rccDisableAPB1(RCC_APB1ENR_PWREN)
395
396/**
397 * @brief Resets the PWR interface.
398 *
399 * @api
400 */
401#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
402/** @} */
403
404/**
405 * @name I2C peripherals specific RCC operations
406 * @{
407 */
408/**
409 * @brief Enables the I2C1 peripheral clock.
410 *
411 * @param[in] lp low power enable flag
412 *
413 * @api
414 */
415#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
416
417/**
418 * @brief Disables the I2C1 peripheral clock.
419 *
420 * @api
421 */
422#define rccDisableI2C1() rccDisableAPB1(RCC_APB1ENR_I2C1EN)
423
424/**
425 * @brief Resets the I2C1 peripheral.
426 *
427 * @api
428 */
429#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
430
431/**
432 * @brief Enables the I2C2 peripheral clock.
433 *
434 * @param[in] lp low power enable flag
435 *
436 * @api
437 */
438#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
439
440/**
441 * @brief Disables the I2C2 peripheral clock.
442 *
443 * @api
444 */
445#define rccDisableI2C2() rccDisableAPB1(RCC_APB1ENR_I2C2EN)
446
447/**
448 * @brief Resets the I2C2 peripheral.
449 *
450 * @api
451 */
452#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
453/** @} */
454
455/**
456 * @name SPI peripherals specific RCC operations
457 * @{
458 */
459/**
460 * @brief Enables the SPI1 peripheral clock.
461 *
462 * @param[in] lp low power enable flag
463 *
464 * @api
465 */
466#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
467
468/**
469 * @brief Disables the SPI1 peripheral clock.
470 *
471 * @api
472 */
473#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
474
475/**
476 * @brief Resets the SPI1 peripheral.
477 *
478 * @api
479 */
480#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
481
482/**
483 * @brief Enables the SPI2 peripheral clock.
484 *
485 * @param[in] lp low power enable flag
486 *
487 * @api
488 */
489#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
490
491/**
492 * @brief Disables the SPI2 peripheral clock.
493 *
494 * @api
495 */
496#define rccDisableSPI2() rccDisableAPB1(RCC_APB1ENR_SPI2EN)
497
498/**
499 * @brief Resets the SPI2 peripheral.
500 *
501 * @api
502 */
503#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
504
505/**
506 * @brief Enables the SPI3 peripheral clock.
507 * @note The @p lp parameter is ignored in this family.
508 *
509 * @param[in] lp low power enable flag
510 *
511 * @api
512 */
513#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
514
515/**
516 * @brief Disables the SPI3 peripheral clock.
517 *
518 * @api
519 */
520#define rccDisableSPI3() rccDisableAPB1(RCC_APB1ENR_SPI3EN)
521
522/**
523 * @brief Resets the SPI3 peripheral.
524 *
525 * @api
526 */
527#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
528/** @} */
529
530/**
531 * @name TIM peripherals specific RCC operations
532 * @{
533 */
534/**
535 * @brief Enables the TIM1 peripheral clock.
536 * @note The @p lp parameter is ignored in this family.
537 *
538 * @param[in] lp low power enable flag
539 *
540 * @api
541 */
542#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
543
544/**
545 * @brief Disables the TIM1 peripheral clock.
546 *
547 * @api
548 */
549#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
550
551/**
552 * @brief Resets the TIM1 peripheral.
553 *
554 * @api
555 */
556#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
557
558/**
559 * @brief Enables the TIM2 peripheral clock.
560 *
561 * @param[in] lp low power enable flag
562 *
563 * @api
564 */
565#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
566
567/**
568 * @brief Disables the TIM2 peripheral clock.
569 *
570 * @api
571 */
572#define rccDisableTIM2() rccDisableAPB1(RCC_APB1ENR_TIM2EN)
573
574/**
575 * @brief Resets the TIM2 peripheral.
576 *
577 * @api
578 */
579#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
580
581/**
582 * @brief Enables the TIM3 peripheral clock.
583 *
584 * @param[in] lp low power enable flag
585 *
586 * @api
587 */
588#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
589
590/**
591 * @brief Disables the TIM3 peripheral clock.
592 *
593 * @api
594 */
595#define rccDisableTIM3() rccDisableAPB1(RCC_APB1ENR_TIM3EN)
596
597/**
598 * @brief Resets the TIM3 peripheral.
599 *
600 * @api
601 */
602#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
603
604/**
605 * @brief Enables the TIM4 peripheral clock.
606 *
607 * @param[in] lp low power enable flag
608 *
609 * @api
610 */
611#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
612
613/**
614 * @brief Disables the TIM4 peripheral clock.
615 *
616 * @api
617 */
618#define rccDisableTIM4() rccDisableAPB1(RCC_APB1ENR_TIM4EN)
619
620/**
621 * @brief Resets the TIM4 peripheral.
622 *
623 * @api
624 */
625#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
626
627/**
628 * @brief Enables the TIM6 peripheral clock.
629 *
630 * @param[in] lp low power enable flag
631 *
632 * @api
633 */
634#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
635
636/**
637 * @brief Disables the TIM6 peripheral clock.
638 *
639 * @api
640 */
641#define rccDisableTIM6() rccDisableAPB1(RCC_APB1ENR_TIM6EN)
642
643/**
644 * @brief Resets the TIM6 peripheral.
645 *
646 * @api
647 */
648#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
649
650/**
651 * @brief Enables the TIM7 peripheral clock.
652 *
653 * @param[in] lp low power enable flag
654 *
655 * @api
656 */
657#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
658
659/**
660 * @brief Disables the TIM7 peripheral clock.
661 *
662 * @api
663 */
664#define rccDisableTIM7() rccDisableAPB1(RCC_APB1ENR_TIM7EN)
665
666/**
667 * @brief Resets the TIM7 peripheral.
668 *
669 * @api
670 */
671#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
672
673/**
674 * @brief Enables the TIM8 peripheral clock.
675 * @note The @p lp parameter is ignored in this family.
676 *
677 * @param[in] lp low power enable flag
678 *
679 * @api
680 */
681#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
682
683/**
684 * @brief Disables the TIM8 peripheral clock.
685 *
686 * @api
687 */
688#define rccDisableTIM8() rccDisableAPB2(RCC_APB2ENR_TIM8EN)
689
690/**
691 * @brief Resets the TIM8 peripheral.
692 *
693 * @api
694 */
695#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
696
697/**
698 * @brief Enables the TIM15 peripheral clock.
699 *
700 * @param[in] lp low power enable flag
701 *
702 * @api
703 */
704#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
705
706/**
707 * @brief Disables the TIM15 peripheral clock.
708 *
709 * @api
710 */
711#define rccDisableTIM15() rccDisableAPB2(RCC_APB2ENR_TIM15EN)
712
713/**
714 * @brief Resets the TIM15 peripheral.
715 *
716 * @api
717 */
718#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
719
720/**
721 * @brief Enables the TIM16 peripheral clock.
722 *
723 * @param[in] lp low power enable flag
724 *
725 * @api
726 */
727#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
728
729/**
730 * @brief Disables the TIM16 peripheral clock.
731 *
732 * @api
733 */
734#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN)
735
736/**
737 * @brief Resets the TIM16 peripheral.
738 *
739 * @api
740 */
741#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
742
743/**
744 * @brief Enables the TIM17 peripheral clock.
745 *
746 * @param[in] lp low power enable flag
747 *
748 * @api
749 */
750#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
751
752/**
753 * @brief Disables the TIM17 peripheral clock.
754 *
755 * @api
756 */
757#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN)
758
759/**
760 * @brief Resets the TIM17 peripheral.
761 *
762 * @api
763 */
764#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
765
766/**
767 * @brief Enables the TIM20 peripheral clock.
768 *
769 * @param[in] lp low power enable flag
770 *
771 * @api
772 */
773#define rccEnableTIM20(lp) rccEnableAPB2(RCC_APB2ENR_TIM20EN, lp)
774
775/**
776 * @brief Disables the TIM20 peripheral clock.
777 *
778 * @api
779 */
780#define rccDisableTIM20(lp) rccDisableAPB2(RCC_APB2ENR_TIM20EN)
781
782/**
783 * @brief Resets the TIM20 peripheral.
784 *
785 * @api
786 */
787#define rccResetTIM20() rccResetAPB2(RCC_APB2RSTR_TIM20RST)
788/** @} */
789
790/**
791 * @name HRTIM peripheral specific RCC operations
792 * @{
793 */
794/**
795
796 * @brief Enables the HRTIM1 peripheral clock.
797 * @note The @p lp parameter is ignored in this family.
798 *
799 * @param[in] lp low power enable flag
800 *
801 * @api
802 */
803#define rccEnableHRTIM1(lp) rccEnableAPB2(RCC_APB2ENR_HRTIM1EN, lp)
804
805/**
806 * @brief Disables the HRTIM1 peripheral clock.
807 *
808 * @api
809 */
810#define rccDisableHRTIM1(lp) rccDisableAPB2(RCC_APB2ENR_HRTIM1EN)
811
812/**
813 * @brief Resets the HRTIM1 peripheral.
814 *
815 * @api
816
817 */
818#define rccResetHRTIM1() rccResetAPB2(RCC_APB2RSTR_HRTIM1RST)
819/** @} */
820
821/**
822 * @name USART/UART peripherals specific RCC operations
823 * @{
824 */
825/**
826 * @brief Enables the USART1 peripheral clock.
827 *
828 * @param[in] lp low power enable flag
829 *
830 * @api
831 */
832#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
833
834/**
835 * @brief Disables the USART1 peripheral clock.
836 *
837 * @api
838 */
839#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
840
841/**
842 * @brief Resets the USART1 peripheral.
843 *
844 * @api
845 */
846#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
847
848/**
849 * @brief Enables the USART2 peripheral clock.
850 *
851 * @param[in] lp low power enable flag
852 *
853 * @api
854 */
855#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
856
857/**
858 * @brief Disables the USART2 peripheral clock.
859 *
860 * @api
861 */
862#define rccDisableUSART2() rccDisableAPB1(RCC_APB1ENR_USART2EN)
863
864/**
865 * @brief Resets the USART2 peripheral.
866 *
867 * @api
868 */
869#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
870
871/**
872 * @brief Enables the USART3 peripheral clock.
873 *
874 * @param[in] lp low power enable flag
875 *
876 * @api
877 */
878#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
879
880/**
881 * @brief Disables the USART3 peripheral clock.
882 *
883 * @api
884 */
885#define rccDisableUSART3() rccDisableAPB1(RCC_APB1ENR_USART3EN)
886
887/**
888 * @brief Resets the USART3 peripheral.
889 *
890 * @api
891 */
892#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
893
894/**
895 * @brief Enables the UART4 peripheral clock.
896 * @note The @p lp parameter is ignored in this family.
897 *
898 * @param[in] lp low power enable flag
899 *
900 * @api
901 */
902#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)
903
904/**
905 * @brief Disables the UART4 peripheral clock.
906 *
907 * @api
908 */
909#define rccDisableUART4() rccDisableAPB1(RCC_APB1ENR_UART4EN)
910
911/**
912 * @brief Resets the UART4 peripheral.
913 *
914 * @api
915 */
916#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)
917
918/**
919 * @brief Enables the UART5 peripheral clock.
920 * @note The @p lp parameter is ignored in this family.
921 *
922 * @param[in] lp low power enable flag
923 *
924 * @api
925 */
926#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)
927
928/**
929 * @brief Disables the UART5 peripheral clock.
930 *
931 * @api
932 */
933#define rccDisableUART5() rccDisableAPB1(RCC_APB1ENR_UART5EN)
934
935/**
936 * @brief Resets the UART5 peripheral.
937 *
938 * @api
939 */
940#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
941/** @} */
942
943/**
944 * @name USB peripheral specific RCC operations
945 * @{
946 */
947/**
948 * @brief Enables the USB peripheral clock.
949 *
950 * @param[in] lp low power enable flag
951 *
952 * @api
953 */
954#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
955
956/**
957 * @brief Disables the USB peripheral clock.
958 *
959 * @api
960 */
961#define rccDisableUSB() rccDisableAPB1(RCC_APB1ENR_USBEN)
962
963/**
964 * @brief Resets the USB peripheral.
965 *
966 * @api
967 */
968#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
969/** @} */
970
971/**
972 * @name FSMC peripherals specific RCC operations
973 * @{
974 */
975/**
976 * @brief Enables the FMC peripheral clock.
977 *
978 * @param[in] lp low power enable flag
979 *
980 * @api
981 */
982#define rccEnableFSMC(lp) rccEnableAHB(RCC_AHBENR_FMCEN, lp)
983
984/**
985 * @brief Disables the FMC peripheral clock.
986 *
987 * @api
988 */
989#define rccDisableFSMC() rccDisableAHB(RCC_AHBENR_FMCEN)
990/** @} */
991
992/**
993 * @name CRC peripherals specific RCC operations
994 * @{
995 */
996/**
997 * @brief Enables the CRC peripheral clock.
998 *
999 * @param[in] lp low power enable flag
1000 *
1001 * @api
1002 */
1003#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp)
1004
1005/**
1006 * @brief Disables the CRC peripheral clock.
1007 *
1008 * @api
1009 */
1010#define rccDisableCRC() rccDisableAHB(RCC_AHBENR_CRCEN)
1011/** @} */
1012
1013/*===========================================================================*/
1014/* External declarations. */
1015/*===========================================================================*/
1016
1017#ifdef __cplusplus
1018extern "C" {
1019#endif
1020#ifdef __cplusplus
1021}
1022#endif
1023
1024#endif /* STM32_RCC_H */
1025
1026/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 13:56:57 +0100