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-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c668
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h134
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld.c334
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld.h278
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h1996
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h1212
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F4xx/platform.mk49
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F4xx/stm32_isr.c255
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F4xx/stm32_isr.h275
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h1658
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F4xx/stm32_registry.h3174
11 files changed, 10033 insertions, 0 deletions
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c b/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c
new file mode 100644
index 000000000..bfaf5dff0
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c
@@ -0,0 +1,668 @@
1/*
2 ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file hal_efl_lld.c
19 * @brief STM32F4xx Embedded Flash subsystem low level driver source.
20 *
21 * @addtogroup HAL_EFL
22 * @{
23 */
24
25#include <string.h>
26
27#include "hal.h"
28
29#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__)
30
31/*===========================================================================*/
32/* Driver local definitions. */
33/*===========================================================================*/
34
35#define STM32_FLASH_LINE_SIZE (1 << STM32_FLASH_PSIZE)
36#define STM32_FLASH_LINE_MASK (STM32_FLASH_LINE_SIZE - 1U)
37
38#define FLASH_PDKEY1 0x04152637U
39#define FLASH_PDKEY2 0xFAFBFCFDU
40
41#define FLASH_KEY1 0x45670123U
42#define FLASH_KEY2 0xCDEF89ABU
43
44#define FLASH_OPTKEY1 0x08192A3BU
45#define FLASH_OPTKEY2 0x4C5D6E7FU
46
47#if !defined(FLASH_SR_OPERR)
48#define FLASH_SR_OPERR FLASH_SR_SOP
49#endif
50
51/*===========================================================================*/
52/* Driver exported variables. */
53/*===========================================================================*/
54
55/**
56 * @brief EFL1 driver identifier.
57 */
58EFlashDriver EFLD1;
59
60/*===========================================================================*/
61/* Driver local variables and types. */
62/*===========================================================================*/
63
64#if defined(STM32F413xx) || defined(STM32F412xx) || defined(STM32F40_41xxx) \
65 || defined(__DOXYGEN__)
66
67/* Sector table for 1.5M device. */
68static const flash_sector_descriptor_t efl_lld_sect1[STM32_FLASH1_SECTORS_TOTAL] = {
69 { 0, 16384}, /* Sector 0. */
70 { 1 * 16384, 16384}, /* Sector 1. */
71 { 2 * 16384, 16384}, /* Sector 2. */
72 { 3 * 16384, 16384}, /* Sector 3. */
73 { 4 * 16384, 65536}, /* Sector 4. */
74 { 4 * 16384 + 65536, 131072}, /* Sector 5. */
75 { 4 * 16384 + 65536 + 1 * 131072, 131072}, /* Sector 6. */
76 { 4 * 16384 + 65536 + 2 * 131072, 131072}, /* Sector 7. */
77 { 4 * 16384 + 65536 + 3 * 131072, 131072}, /* Sector 8. */
78 { 4 * 16384 + 65536 + 4 * 131072, 131072}, /* Sector 9. */
79 { 4 * 16384 + 65536 + 5 * 131072, 131072}, /* Sector 10. */
80 { 4 * 16384 + 65536 + 6 * 131072, 131072}, /* Sector 11. */
81 { 4 * 16384 + 65536 + 7 * 131072, 131072}, /* Sector 12. */
82 { 4 * 16384 + 65536 + 8 * 131072, 131072}, /* Sector 13. */
83 { 4 * 16384 + 65536 + 9 * 131072, 131072}, /* Sector 14. */
84 { 4 * 16384 + 65536 + 10 * 131072, 131072} /* Sector 15. */
85};
86
87/* Sector table for 1M device. */
88static const flash_sector_descriptor_t efl_lld_sect2[STM32_FLASH2_SECTORS_TOTAL] = {
89 { 0, 16384}, /* Sector 0. */
90 { 1 * 16384, 16384}, /* Sector 1. */
91 { 2 * 16384, 16384}, /* Sector 2. */
92 { 3 * 16384, 16384}, /* Sector 3. */
93 { 4 * 16384, 65536}, /* Sector 4. */
94 { 4 * 16384 + 65536, 131072}, /* Sector 5. */
95 { 4 * 16384 + 65536 + 1 * 131072, 131072}, /* Sector 6. */
96 { 4 * 16384 + 65536 + 2 * 131072, 131072}, /* Sector 7. */
97 { 4 * 16384 + 65536 + 3 * 131072, 131072}, /* Sector 8. */
98 { 4 * 16384 + 65536 + 4 * 131072, 131072}, /* Sector 9. */
99 { 4 * 16384 + 65536 + 5 * 131072, 131072}, /* Sector 10. */
100 { 4 * 16384 + 65536 + 6 * 131072, 131072} /* Sector 11. */
101};
102
103/* The descriptors for 1.5M device. */
104static const flash_descriptor_t efl_lld_size1[STM32_FLASH_NUMBER_OF_BANKS] = {
105 { /* Single bank organisation. */
106 .attributes = FLASH_ATTR_ERASED_IS_ONE |
107 FLASH_ATTR_MEMORY_MAPPED,
108 .page_size = STM32_FLASH_LINE_SIZE,
109 .sectors_count = STM32_FLASH1_SECTORS_TOTAL,
110 .sectors = efl_lld_sect1,
111 .sectors_size = 0,
112 .address = (uint8_t *)FLASH_BASE,
113 .size = STM32_FLASH1_SIZE * STM32_FLASH_SIZE_SCALE
114 }
115};
116
117/* The descriptors for 1M device. */
118static const flash_descriptor_t efl_lld_size2[STM32_FLASH_NUMBER_OF_BANKS] = {
119 { /* Single bank organisation. */
120 .attributes = FLASH_ATTR_ERASED_IS_ONE |
121 FLASH_ATTR_MEMORY_MAPPED,
122 .page_size = STM32_FLASH_LINE_SIZE,
123 .sectors_count = STM32_FLASH2_SECTORS_TOTAL,
124 .sectors = efl_lld_sect2,
125 .sectors_size = 0,
126 .address = (uint8_t *)FLASH_BASE,
127 .size = STM32_FLASH2_SIZE * STM32_FLASH_SIZE_SCALE
128 }
129};
130
131/* Table describing possible flash sizes and descriptors for this device. */
132static const efl_lld_size_t efl_lld_flash_sizes[] = {
133 {
134 .desc = efl_lld_size1
135 },
136 {
137 .desc = efl_lld_size2
138 }
139};
140#else
141#error "This EFL driver does not support the selected device"
142#endif
143
144/*===========================================================================*/
145/* Driver local functions. */
146/*===========================================================================*/
147
148static inline void stm32_flash_lock(EFlashDriver *eflp) {
149
150 eflp->flash->CR |= FLASH_CR_LOCK;
151}
152
153static inline void stm32_flash_unlock(EFlashDriver *eflp) {
154
155 eflp->flash->KEYR |= FLASH_KEY1;
156 eflp->flash->KEYR |= FLASH_KEY2;
157}
158
159static inline void stm32_flash_enable_pgm(EFlashDriver *eflp) {
160
161 /* Set parallelism. */
162 eflp->flash->CR &= ~FLASH_CR_PSIZE;
163 eflp->flash->CR |= STM32_FLASH_PSIZE << FLASH_CR_PSIZE_Pos;
164
165 /* Enable programming. */
166 eflp->flash->CR |= FLASH_CR_PG;
167}
168
169static inline void stm32_flash_disable_pgm(EFlashDriver *eflp) {
170
171 eflp->flash->CR &= ~FLASH_CR_PG;
172}
173
174static inline void stm32_flash_clear_status(EFlashDriver *eflp) {
175
176 eflp->flash->SR = 0x0000FFFFU;
177}
178
179static inline void stm32_flash_wait_busy(EFlashDriver *eflp) {
180
181 /* Wait for busy bit clear.*/
182 while ((eflp->flash->SR & FLASH_SR_BSY) != 0U) {
183 }
184}
185
186static inline size_t stm32_flash_get_size(void) {
187 return *(uint16_t*)((uint32_t) STM32_FLASH_SIZE_REGISTER) * STM32_FLASH_SIZE_SCALE;
188}
189
190static inline bool stm32_flash_dual_bank(EFlashDriver *eflp) {
191
192#if STM32_FLASH_NUMBER_OF_BANKS > 1
193 return ((eflp->flash->OPTCR & FLASH_OPTCR_DB1M) != 0U);
194#endif
195 (void)eflp;
196 return false;
197}
198
199static inline flash_error_t stm32_flash_check_errors(EFlashDriver *eflp) {
200 uint32_t sr = eflp->flash->SR;
201
202 /* Clearing error conditions.*/
203 eflp->flash->SR = sr & 0x0000FFFFU;
204
205 /* Some errors are only caught by assertion.*/
206 osalDbgAssert((sr & 0) == 0U, "unexpected flash error");
207
208 /* Decoding relevant errors.*/
209 if ((sr & FLASH_SR_WRPERR) != 0U) {
210 return FLASH_ERROR_HW_FAILURE;
211 }
212
213 if ((sr & (FLASH_SR_PGAERR | FLASH_SR_PGPERR | FLASH_SR_OPERR)) != 0U) {
214 return eflp->state == FLASH_PGM ? FLASH_ERROR_PROGRAM : FLASH_ERROR_ERASE;
215 }
216
217 return FLASH_NO_ERROR;
218}
219
220/*===========================================================================*/
221/* Driver interrupt handlers. */
222/*===========================================================================*/
223
224/*===========================================================================*/
225/* Driver exported functions. */
226/*===========================================================================*/
227
228/**
229 * @brief Low level Embedded Flash driver initialization.
230 *
231 * @notapi
232 */
233void efl_lld_init(void) {
234
235 /* Driver initialization.*/
236 eflObjectInit(&EFLD1);
237 EFLD1.flash = FLASH;
238 /* Find the size of the flash and set descriptor reference. */
239 uint8_t i;
240 for (i = 0; i < (sizeof(efl_lld_flash_sizes) / sizeof(efl_lld_size_t)); i++) {
241 if (efl_lld_flash_sizes[i].desc->size == stm32_flash_get_size()) {
242 EFLD1.descriptor = efl_lld_flash_sizes[i].desc;
243 if (stm32_flash_dual_bank(&EFLD1)) {
244 /* Point to the dual bank descriptor. */
245 EFLD1.descriptor++;
246 }
247 return;
248 }
249 }
250 osalDbgAssert(false, "invalid flash configuration");
251}
252
253/**
254 * @brief Configures and activates the Embedded Flash peripheral.
255 *
256 * @param[in] eflp pointer to a @p EFlashDriver structure
257 *
258 * @notapi
259 */
260void efl_lld_start(EFlashDriver *eflp) {
261 stm32_flash_unlock(eflp);
262 FLASH->CR = 0x00000000U;
263}
264
265/**
266 * @brief Deactivates the Embedded Flash peripheral.
267 *
268 * @param[in] eflp pointer to a @p EFlashDriver structure
269 *
270 * @notapi
271 */
272void efl_lld_stop(EFlashDriver *eflp) {
273
274 stm32_flash_lock(eflp);
275}
276
277/**
278 * @brief Gets the flash descriptor structure.
279 *
280 * @param[in] ip pointer to a @p EFlashDriver instance
281 * @return A flash device descriptor.
282 * @retval Pointer to single bank if DBM not enabled.
283 * @retval Pointer to bank1 if DBM enabled.
284 *
285 * @notapi
286 */
287const flash_descriptor_t *efl_lld_get_descriptor(void *instance) {
288 EFlashDriver *devp = (EFlashDriver *)instance;
289 return devp->descriptor;
290}
291
292/**
293 * @brief Read operation.
294 *
295 * @param[in] ip pointer to a @p EFlashDriver instance
296 * @param[in] offset offset within full flash address space
297 * @param[in] n number of bytes to be read
298 * @param[out] rp pointer to the data buffer
299 * @return An error code.
300 * @retval FLASH_NO_ERROR if there is no erase operation in progress.
301 * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
302 * @retval FLASH_ERROR_READ if the read operation failed.
303 * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
304 *
305 * @notapi
306 */
307flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
308 size_t n, uint8_t *rp) {
309 EFlashDriver *devp = (EFlashDriver *)instance;
310 flash_error_t err = FLASH_NO_ERROR;
311
312 osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U));
313
314 const flash_descriptor_t *bank = efl_lld_get_descriptor(instance);
315 osalDbgCheck((size_t)offset + n <= (size_t)bank->size);
316 osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
317 "invalid state");
318
319 /* No reading while erasing.*/
320 if (devp->state == FLASH_ERASE) {
321 return FLASH_BUSY_ERASING;
322 }
323
324 /* FLASH_READ state while the operation is performed.*/
325 devp->state = FLASH_READ;
326
327 /* Clearing error status bits.*/
328 stm32_flash_clear_status(devp);
329
330 /* Actual read implementation.*/
331 memcpy((void *)rp, (const void *)efl_lld_get_descriptor(instance)->address
332 + offset, n);
333
334#if defined(FLASH_CR_RDERR)
335 /* Checking for errors after reading.*/
336 if ((devp->flash->SR & FLASH_SR_RDERR) != 0U) {
337 err = FLASH_ERROR_READ;
338 }
339#endif
340
341 /* Ready state again.*/
342 devp->state = FLASH_READY;
343
344 return err;
345
346}
347
348/**
349 * @brief Program operation.
350 * @note Successive write operations are possible without the need of
351 * an erase when changing bits from one to zero. Writing one requires
352 * an erase operation.
353 *
354 * @param[in] ip pointer to a @p EFlashDriver instance
355 * @param[in] offset offset within full flash address space
356 * @param[in] n number of bytes to be programmed
357 * @param[in] pp pointer to the data buffer
358 * @return An error code.
359 * @retval FLASH_NO_ERROR if there is no erase operation in progress.
360 * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
361 * @retval FLASH_ERROR_PROGRAM if the program operation failed.
362 * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
363 *
364 * @notapi
365 */
366flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
367 size_t n, const uint8_t *pp) {
368 EFlashDriver *devp = (EFlashDriver *)instance;
369 const flash_descriptor_t *bank = efl_lld_get_descriptor(instance);
370 flash_error_t err = FLASH_NO_ERROR;
371
372 osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U));
373 osalDbgCheck((size_t)offset + n <= (size_t)bank->size);
374 osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
375 "invalid state");
376
377 /* No programming while erasing.*/
378 if (devp->state == FLASH_ERASE) {
379 return FLASH_BUSY_ERASING;
380 }
381
382 /* FLASH_PGM state while the operation is performed.*/
383 devp->state = FLASH_PGM;
384
385 /* Clearing error status bits.*/
386 stm32_flash_clear_status(devp);
387
388 /* Enabling PGM mode in the controller.*/
389 stm32_flash_enable_pgm(devp);
390
391 /* Actual program implementation.*/
392 while (n > 0U) {
393 volatile uint32_t *address;
394
395 /* Create an array of sufficient size to hold line(s). */
396 union {
397 uint32_t w[STM32_FLASH_LINE_SIZE / sizeof(uint32_t)];
398 uint16_t h[STM32_FLASH_LINE_SIZE / sizeof(uint16_t)];
399 uint8_t b[STM32_FLASH_LINE_SIZE / sizeof(uint8_t)];
400 } line;
401
402 /* Unwritten bytes are initialized to all ones.*/
403 uint8_t i;
404 for (i = 0; i < bank->page_size; i++) {
405 line.b[i] = 0xFF;
406 }
407
408 /* Programming address aligned to flash lines.*/
409 address = (volatile uint32_t *)(bank->address +
410 (offset & ~STM32_FLASH_LINE_MASK));
411
412 /* Copying data inside the prepared line(s).*/
413 do {
414 line.b[offset & STM32_FLASH_LINE_MASK] = *pp;
415 offset++;
416 n--;
417 pp++;
418 }
419 while ((n > 0U) & ((offset & STM32_FLASH_LINE_MASK) != 0U));
420
421 /* Programming line according to parallelism.*/
422 switch (STM32_FLASH_LINE_SIZE) {
423 case 1:
424 address[0] = line.b[0];
425 break;
426
427 case 2:
428 address[0] = line.h[0];
429 break;
430
431 case 4:
432 address[0] = line.w[0];
433 break;
434
435 case 8:
436 address[0] = line.w[0];
437 address[1] = line.w[1];
438 break;
439
440 default:
441 osalDbgAssert(false, "invalid line size");
442 break;
443 }
444
445 stm32_flash_wait_busy(devp);
446 err = stm32_flash_check_errors(devp);
447 if (err != FLASH_NO_ERROR) {
448 break;
449 }
450 }
451
452 /* Disabling PGM mode in the controller.*/
453 stm32_flash_disable_pgm(devp);
454
455 /* Ready state again.*/
456 devp->state = FLASH_READY;
457
458 return err;
459}
460
461/**
462 * @brief Starts a whole-device erase operation.
463 * @note This function only erases bank 2 if it is present. Bank 1 is not
464 * allowed since it is normally where the primary program is located.
465 * Sectors on bank 1 can be individually erased.
466 *
467 * @param[in] ip pointer to a @p EFlashDriver instance
468 * @return An error code.
469 * @retval FLASH_NO_ERROR if there is no erase operation in progress.
470 * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
471 * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
472 *
473 * @notapi
474 */
475flash_error_t efl_lld_start_erase_all(void *instance) {
476 EFlashDriver *devp = (EFlashDriver *)instance;
477
478 osalDbgCheck(instance != NULL);
479 osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
480 "invalid state");
481
482 /* No erasing while erasing.*/
483 if (devp->state == FLASH_ERASE) {
484 return FLASH_BUSY_ERASING;
485 }
486
487#if defined(FLASH_CR_MER1)
488 /* If dual bank is active then mass erase bank2. */
489 if (stm32_flash_dual_bank(devp)) {
490
491 /* FLASH_ERASE state while the operation is performed.*/
492 devp->state = FLASH_ERASE;
493
494 /* Clearing error status bits.*/
495 stm32_flash_clear_status(devp);
496
497 devp->flash->CR |= FLASH_CR_MER1;
498 devp->flash->CR |= FLASH_CR_STRT;
499 return FLASH_NO_ERROR;
500 }
501#endif
502
503 /* Mass erase not allowed. */
504 return FLASH_ERROR_UNIMPLEMENTED;
505}
506
507/**
508 * @brief Starts an sector erase operation.
509 *
510 * @param[in] ip pointer to a @p EFlashDriver instance
511 * @param[in] sector sector to be erased
512 * this is an index within the total sectors
513 * in a flash bank
514 * @return An error code.
515 * @retval FLASH_NO_ERROR if there is no erase operation in progress.
516 * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
517 * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
518 *
519 * @notapi
520 */
521flash_error_t efl_lld_start_erase_sector(void *instance,
522 flash_sector_t sector) {
523 EFlashDriver *devp = (EFlashDriver *)instance;
524 const flash_descriptor_t *bank = efl_lld_get_descriptor(instance);
525 osalDbgCheck(instance != NULL);
526 osalDbgCheck(sector < bank->sectors_count);
527 osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
528 "invalid state");
529
530 /* No erasing while erasing.*/
531 if (devp->state == FLASH_ERASE) {
532 return FLASH_BUSY_ERASING;
533 }
534
535 /* FLASH_PGM state while the operation is performed.*/
536 devp->state = FLASH_ERASE;
537
538 /* Clearing error status bits.*/
539 stm32_flash_clear_status(devp);
540
541 /* Enable sector erase.*/
542 devp->flash->CR |= FLASH_CR_SER;
543
544 /* Mask off the sector and parallelism selection bits.*/
545 devp->flash->CR &= ~FLASH_CR_SNB;
546 devp->flash->CR &= ~FLASH_CR_PSIZE;
547
548 /* Set sector and parallelism. */
549 devp->flash->CR |= (sector << FLASH_CR_SNB_Pos) |
550 (STM32_FLASH_PSIZE << FLASH_CR_PSIZE_Pos);
551
552 /* Start the erase.*/
553 devp->flash->CR |= FLASH_CR_STRT;
554
555 return FLASH_NO_ERROR;
556}
557
558/**
559 * @brief Queries the driver for erase operation progress.
560 *
561 * @param[in] instance pointer to a @p EFlashDriver instance
562 * @param[out] msec recommended time, in milliseconds, that
563 * should be spent before calling this
564 * function again, can be @p NULL
565 * @return An error code.
566 * @retval FLASH_NO_ERROR if there is no erase operation in progress.
567 * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
568 * @retval FLASH_ERROR_ERASE if the erase operation failed.
569 * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
570 *
571 * @api
572 */
573flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) {
574 EFlashDriver *devp = (EFlashDriver *)instance;
575 flash_error_t err;
576
577 /* If there is an erase in progress then the device must be checked.*/
578 if (devp->state == FLASH_ERASE) {
579
580 /* Checking for operation in progress.*/
581 if ((devp->flash->SR & FLASH_SR_BSY) == 0U) {
582
583 /* Disabling the various erase control bits.*/
584 devp->flash->CR &= ~(FLASH_CR_MER |
585#if defined(FLASH_CR_MER1)
586 FLASH_CR_MER1 |
587#endif
588 FLASH_CR_SER);
589
590 /* No operation in progress, checking for errors.*/
591 err = stm32_flash_check_errors(devp);
592
593 /* Back to ready state.*/
594 devp->state = FLASH_READY;
595 }
596 else {
597 /* Recommended time before polling again. This is a simplified
598 implementation.*/
599 if (msec != NULL) {
600 *msec = (uint32_t)STM32_FLASH_WAIT_TIME_MS;
601 }
602
603 err = FLASH_BUSY_ERASING;
604 }
605 }
606 else {
607 err = FLASH_NO_ERROR;
608 }
609
610 return err;
611}
612
613/**
614 * @brief Returns the erase state of a sector.
615 *
616 * @param[in] ip pointer to a @p EFlashDriver instance
617 * @param[in] sector sector to be verified
618 * @return An error code.
619 * @retval FLASH_NO_ERROR if the sector is erased.
620 * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
621 * @retval FLASH_ERROR_VERIFY if the verify operation failed.
622 * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
623 *
624 * @notapi
625 */
626flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) {
627 EFlashDriver *devp = (EFlashDriver *)instance;
628 uint32_t *address;
629 const flash_descriptor_t *bank = efl_lld_get_descriptor(instance);
630 flash_error_t err = FLASH_NO_ERROR;
631 unsigned i;
632
633 osalDbgCheck(instance != NULL);
634 osalDbgCheck(sector < bank->sectors_count);
635 osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
636 "invalid state");
637
638 /* No verifying while erasing.*/
639 if (devp->state == FLASH_ERASE) {
640 return FLASH_BUSY_ERASING;
641 }
642
643 /* Address of the sector in the bank.*/
644 address = (uint32_t *)(bank->address +
645 flashGetSectorOffset(getBaseFlash(devp), sector));
646
647 /* FLASH_READ state while the operation is performed.*/
648 devp->state = FLASH_READ;
649
650 /* Scanning the sector space.*/
651 uint32_t sector_size = flashGetSectorSize(getBaseFlash(devp), sector);
652 for (i = 0U; i < sector_size / sizeof(uint32_t); i++) {
653 if (*address != 0xFFFFFFFFU) {
654 err = FLASH_ERROR_VERIFY;
655 break;
656 }
657 address++;
658 }
659
660 /* Ready state again.*/
661 devp->state = FLASH_READY;
662
663 return err;
664}
665
666#endif /* HAL_USE_EFL == TRUE */
667
668/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h b/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h
new file mode 100644
index 000000000..21614b461
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h
@@ -0,0 +1,134 @@
1/*
2 ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file hal_efl_lld.h
19 * @brief STM32F4xx Embedded Flash subsystem low level driver header.
20 *
21 * @addtogroup HAL_EFL
22 * @{
23 */
24
25#ifndef HAL_EFL_LLD_H
26#define HAL_EFL_LLD_H
27
28#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__)
29
30/*===========================================================================*/
31/* Driver constants. */
32/*===========================================================================*/
33
34/*===========================================================================*/
35/* Driver pre-compile time settings. */
36/*===========================================================================*/
37
38/**
39 * @name STM32F412/413 EFL driver configuration options
40 * @{
41 */
42/**
43 * @brief Suggested wait time during erase operations polling.
44 */
45#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__)
46#define STM32_FLASH_WAIT_TIME_MS 5
47#endif
48/** @} */
49
50/*===========================================================================*/
51/* Derived constants and error checks. */
52/*===========================================================================*/
53
54#if defined(STM32F413xx) || defined(STM32F412xx) || defined(STM32F40_41xxx) \
55 || defined(__DOXYGEN__)
56
57/* Flash size register. */
58#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22
59#define STM32_FLASH_SIZE_SCALE 1024U
60
61/*
62 * Device flash size...
63 *
64 */
65#define STM32_FLASH_NUMBER_OF_BANKS 1
66#define STM32_FLASH1_SIZE 1536U
67#define STM32_FLASH2_SIZE 1024U
68#define STM32_FLASH1_SECTORS_TOTAL 16
69#define STM32_FLASH2_SECTORS_TOTAL 12
70#else
71#error "This EFL driver does not support the selected device"
72#endif
73
74/*===========================================================================*/
75/* Driver data structures and types. */
76/*===========================================================================*/
77
78/* A flash size declaration. */
79typedef struct {
80 const flash_descriptor_t* desc;
81} efl_lld_size_t;
82
83/*===========================================================================*/
84/* Driver macros. */
85/*===========================================================================*/
86
87/**
88 * @brief Low level fields of the embedded flash driver structure.
89 */
90#define efl_lld_driver_fields \
91 /* Flash registers.*/ \
92 FLASH_TypeDef *flash; \
93 const flash_descriptor_t *descriptor;
94
95/**
96 * @brief Low level fields of the embedded flash configuration structure.
97 */
98#define efl_lld_config_fields \
99 /* Dummy configuration, it is not needed.*/ \
100 uint32_t dummy
101
102/*===========================================================================*/
103/* External declarations. */
104/*===========================================================================*/
105
106#if !defined(__DOXYGEN__)
107extern EFlashDriver EFLD1;
108#endif
109
110#ifdef __cplusplus
111extern "C" {
112#endif
113 void efl_lld_init(void);
114 void efl_lld_start(EFlashDriver *eflp);
115 void efl_lld_stop(EFlashDriver *eflp);
116 const flash_descriptor_t *efl_lld_get_descriptor(void *instance);
117 flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
118 size_t n, uint8_t *rp);
119 flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
120 size_t n, const uint8_t *pp);
121 flash_error_t efl_lld_start_erase_all(void *instance);
122 flash_error_t efl_lld_start_erase_sector(void *instance,
123 flash_sector_t sector);
124 flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec);
125 flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector);
126#ifdef __cplusplus
127}
128#endif
129
130#endif /* HAL_USE_EFL == TRUE */
131
132#endif /* HAL_EFL_LLD_H */
133
134/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld.c
new file mode 100644
index 000000000..63b30c24d
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -0,0 +1,334 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F4xx/hal_lld.c
19 * @brief STM32F4xx/STM32F2xx HAL subsystem low level driver source.
20 *
21 * @addtogroup HAL
22 * @{
23 */
24
25#include "hal.h"
26
27/*===========================================================================*/
28/* Driver local definitions. */
29/*===========================================================================*/
30
31/*===========================================================================*/
32/* Driver exported variables. */
33/*===========================================================================*/
34
35/**
36 * @brief CMSIS system core clock variable.
37 * @note It is declared in system_stm32f4xx.h.
38 */
39uint32_t SystemCoreClock = STM32_HCLK;
40
41/*===========================================================================*/
42/* Driver local variables and types. */
43/*===========================================================================*/
44
45/*===========================================================================*/
46/* Driver local functions. */
47/*===========================================================================*/
48
49/**
50 * @brief Initializes the backup domain.
51 * @note WARNING! Changing clock source impossible without resetting
52 * of the whole BKP domain.
53 */
54static void hal_lld_backup_domain_init(void) {
55
56 /* Backup domain access enabled and left open.*/
57 PWR->CR |= PWR_CR_DBP;
58
59 /* Reset BKP domain if different clock source selected.*/
60 if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
61 /* Backup domain reset.*/
62 RCC->BDCR = RCC_BDCR_BDRST;
63 RCC->BDCR = 0;
64 }
65
66#if STM32_LSE_ENABLED
67#if defined(STM32_LSE_BYPASS)
68 /* LSE Bypass.*/
69 RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
70#else
71 /* No LSE Bypass.*/
72 RCC->BDCR |= RCC_BDCR_LSEON;
73#endif
74 while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
75 ; /* Waits until LSE is stable. */
76#endif
77
78#if HAL_USE_RTC
79 /* If the backup domain hasn't been initialized yet then proceed with
80 initialization.*/
81 if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
82 /* Selects clock source.*/
83 RCC->BDCR |= STM32_RTCSEL;
84
85 /* RTC clock enabled.*/
86 RCC->BDCR |= RCC_BDCR_RTCEN;
87 }
88#endif /* HAL_USE_RTC */
89
90#if STM32_BKPRAM_ENABLE
91 rccEnableBKPSRAM(true);
92
93 PWR->CSR |= PWR_CSR_BRE;
94 while ((PWR->CSR & PWR_CSR_BRR) == 0)
95 ; /* Waits until the regulator is stable */
96#else
97 PWR->CSR &= ~PWR_CSR_BRE;
98#endif /* STM32_BKPRAM_ENABLE */
99}
100
101/*===========================================================================*/
102/* Driver interrupt handlers. */
103/*===========================================================================*/
104
105/*===========================================================================*/
106/* Driver exported functions. */
107/*===========================================================================*/
108
109/**
110 * @brief Low level HAL driver initialization.
111 *
112 * @notapi
113 */
114void hal_lld_init(void) {
115
116 /* Reset of all peripherals. AHB3 is not reseted because it could have
117 been initialized in the board initialization file (board.c).
118 Note, GPIOs are not reset because initialized before this point in
119 board files.*/
120 rccResetAHB1(~STM32_GPIO_EN_MASK);
121#if !defined(STM32F410xx)
122 rccResetAHB2(~0);
123#endif
124 rccResetAPB1(~RCC_APB1RSTR_PWRRST);
125 rccResetAPB2(~0);
126
127 /* PWR clock enabled.*/
128 rccEnablePWRInterface(true);
129
130 /* Initializes the backup domain.*/
131 hal_lld_backup_domain_init();
132
133 /* DMA subsystems initialization.*/
134#if defined(STM32_DMA_REQUIRED)
135 dmaInit();
136#endif
137
138 /* IRQ subsystem initialization.*/
139 irqInit();
140
141 /* Programmable voltage detector enable.*/
142#if STM32_PVD_ENABLE
143 PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
144#endif /* STM32_PVD_ENABLE */
145}
146
147/**
148 * @brief STM32F2xx clocks and PLL initialization.
149 * @note All the involved constants come from the file @p board.h.
150 * @note This function should be invoked just after the system reset.
151 *
152 * @special
153 */
154void stm32_clock_init(void) {
155
156#if !STM32_NO_INIT
157 /* PWR clock enable.*/
158#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR_RTCAPBEN)
159 RCC->APB1ENR = RCC_APB1ENR_PWREN | RCC_APB1ENR_RTCAPBEN;
160#else
161 RCC->APB1ENR = RCC_APB1ENR_PWREN;
162#endif
163
164 /* PWR initialization.*/
165#if defined(STM32F4XX) || defined(__DOXYGEN__)
166 PWR->CR = STM32_VOS;
167#else
168 PWR->CR = 0;
169#endif
170
171 /* HSI setup, it enforces the reset situation in order to handle possible
172 problems with JTAG probes and re-initializations.*/
173 RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
174 while (!(RCC->CR & RCC_CR_HSIRDY))
175 ; /* Wait until HSI is stable. */
176
177 /* HSI is selected as new source without touching the other fields in
178 CFGR. Clearing the register has to be postponed after HSI is the
179 new source.*/
180 RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW, selecting HSI. */
181 while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
182 ; /* Wait until HSI is selected. */
183
184 /* Registers finally cleared to reset values.*/
185 RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
186 RCC->CFGR = 0; /* CFGR reset value. */
187
188#if STM32_HSE_ENABLED
189 /* HSE activation.*/
190#if defined(STM32_HSE_BYPASS)
191 /* HSE Bypass.*/
192 RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
193#else
194 /* No HSE Bypass.*/
195 RCC->CR |= RCC_CR_HSEON;
196#endif
197 while ((RCC->CR & RCC_CR_HSERDY) == 0)
198 ; /* Waits until HSE is stable. */
199#endif
200
201#if STM32_LSI_ENABLED
202 /* LSI activation.*/
203 RCC->CSR |= RCC_CSR_LSION;
204 while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
205 ; /* Waits until LSI is stable. */
206#endif
207
208#if STM32_ACTIVATE_PLL
209 /* PLL activation.*/
210 RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
211 STM32_PLLM;
212 RCC->CR |= RCC_CR_PLLON;
213
214 /* Synchronization with voltage regulator stabilization.*/
215#if defined(STM32F4XX)
216 while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
217 ; /* Waits until power regulator is stable. */
218
219#if STM32_OVERDRIVE_REQUIRED
220 /* Overdrive activation performed after activating the PLL in order to save
221 time as recommended in RM in "Entering Over-drive mode" paragraph.*/
222 PWR->CR |= PWR_CR_ODEN;
223 while (!(PWR->CSR & PWR_CSR_ODRDY))
224 ;
225 PWR->CR |= PWR_CR_ODSWEN;
226 while (!(PWR->CSR & PWR_CSR_ODSWRDY))
227 ;
228#endif /* STM32_OVERDRIVE_REQUIRED */
229#endif /* defined(STM32F4XX) */
230
231 /* Waiting for PLL lock.*/
232 while (!(RCC->CR & RCC_CR_PLLRDY))
233 ;
234#endif /* STM32_ACTIVATE_PLL */
235
236#if STM32_ACTIVATE_PLLI2S
237 /* PLLI2S activation.*/
238 RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN | STM32_PLLI2SP |
239 STM32_PLLI2SSRC | STM32_PLLI2SQ | STM32_PLLI2SM;
240 RCC->CR |= RCC_CR_PLLI2SON;
241
242 /* Waiting for PLL lock.*/
243 while (!(RCC->CR & RCC_CR_PLLI2SRDY))
244 ;
245#endif /* STM32_ACTIVATE_PLLI2S */
246
247#if STM32_ACTIVATE_PLLSAI
248 /* PLLSAI activation.*/
249 RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIN | STM32_PLLSAIP |
250 STM32_PLLSAIQ | STM32_PLLSAIM;
251 RCC->CR |= RCC_CR_PLLSAION;
252
253 /* Waiting for PLL lock.*/
254 while (!(RCC->CR & RCC_CR_PLLSAIRDY))
255 ;
256#endif /* STM32_ACTIVATE_PLLSAI */
257
258 /* Other clock-related settings (dividers, MCO etc).*/
259#if !defined(STM32F413xx)
260 RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
261 STM32_I2SSRC | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
262 STM32_HPRE;
263#else
264 RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
265 STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
266 STM32_HPRE;
267#endif
268
269#if STM32_HAS_RCC_DCKCFGR
270 /* DCKCFGR register initialization, note, must take care of the _OFF
271 pseudo settings.*/
272 {
273 uint32_t dckcfgr = 0;
274#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
275 dckcfgr |= STM32_SAI2SEL;
276#endif
277#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
278 dckcfgr |= STM32_SAI1SEL;
279#endif
280#if (STM32_ACTIVATE_PLLSAI == TRUE) && \
281 (STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF)
282 dckcfgr |= STM32_PLLSAIDIVR;
283#endif
284#if defined(STM32F469xx) || defined(STM32F479xx)
285 /* Special case, in those devices STM32_CK48MSEL is located in the
286 DCKCFGR register.*/
287 dckcfgr |= STM32_CK48MSEL;
288#endif
289#if !defined(STM32F413xx)
290 RCC->DCKCFGR = dckcfgr |
291 STM32_TIMPRE | STM32_PLLSAIDIVQ | STM32_PLLI2SDIVQ;
292#else
293 RCC->DCKCFGR = dckcfgr |
294 STM32_TIMPRE | STM32_PLLDIVR | STM32_PLLI2SDIVR;
295#endif
296 }
297#endif
298
299#if STM32_HAS_RCC_DCKCFGR2
300 /* DCKCFGR2 register initialization.*/
301 RCC->DCKCFGR2 = STM32_CK48MSEL;
302#endif
303
304 /* Flash setup.*/
305#if !defined(STM32_REMOVE_REVISION_A_FIX)
306 /* Some old revisions of F4x MCUs randomly crashes with compiler
307 optimizations enabled AND flash caches enabled. */
308 if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241))
309 FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS;
310 else
311 FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
312 FLASH_ACR_DCEN | STM32_FLASHBITS;
313#else
314 FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
315 FLASH_ACR_DCEN | STM32_FLASHBITS;
316#endif
317 while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
318 (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
319 }
320
321 /* Switching to the configured clock source if it is different from HSI.*/
322#if (STM32_SW != STM32_SW_HSI)
323 RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
324 while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
325 ;
326#endif
327#endif /* STM32_NO_INIT */
328
329 /* SYSCFG clock enabled here because it is a multi-functional unit shared
330 among multiple drivers.*/
331 rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
332}
333
334/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld.h
new file mode 100644
index 000000000..68501510c
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld.h
@@ -0,0 +1,278 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F4xx/hal_lld.h
19 * @brief STM32F4xx/STM32F2xx HAL subsystem low level driver header.
20 *
21 * @addtogroup HAL
22 * @{
23 */
24
25#ifndef HAL_LLD_H
26#define HAL_LLD_H
27
28#include "stm32_registry.h"
29
30#if defined(STM32F413xx)
31#include "hal_lld_type2.h"
32#else
33#include "hal_lld_type1.h"
34#endif
35
36/* Various helpers.*/
37#include "nvic.h"
38#include "cache.h"
39#include "mpu_v7m.h"
40#include "stm32_isr.h"
41#include "stm32_dma.h"
42#include "stm32_exti.h"
43#include "stm32_rcc.h"
44#include "stm32_tim.h"
45
46/*===========================================================================*/
47/* Driver constants. */
48/*===========================================================================*/
49
50/*===========================================================================*/
51/* Driver pre-compile time settings. */
52/*===========================================================================*/
53
54/*===========================================================================*/
55/* Derived constants and error checks. */
56/*===========================================================================*/
57
58/**
59 * @brief MCO1 divider clock.
60 */
61#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
62#define STM32_MCO1DIVCLK STM32_HSICLK
63
64#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
65#define STM32_MCO1DIVCLK STM32_LSECLK
66
67#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
68#define STM32_MCO1DIVCLK STM32_HSECLK
69
70#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
71#define STM32_MCO1DIVCLK STM32_PLLCLKOUT
72
73#else
74#error "invalid STM32_MCO1SEL value specified"
75#endif
76
77/**
78 * @brief MCO1 output pin clock.
79 */
80#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
81#define STM32_MCO1CLK STM32_MCO1DIVCLK
82
83#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
84#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
85
86#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
87#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
88
89#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
90#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
91
92#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
93#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
94
95#else
96#error "invalid STM32_MCO1PRE value specified"
97#endif
98
99/**
100 * @brief MCO2 divider clock.
101 */
102#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
103#define STM32_MCO2DIVCLK STM32_HSECLK
104
105#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
106#define STM32_MCO2DIVCLK STM32_PLLCLKOUT
107
108#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
109#define STM32_MCO2DIVCLK STM32_SYSCLK
110
111#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
112#define STM32_MCO2DIVCLK STM32_PLLI2S
113
114#else
115#error "invalid STM32_MCO2SEL value specified"
116#endif
117
118/**
119 * @brief MCO2 output pin clock.
120 */
121#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
122#define STM32_MCO2CLK STM32_MCO2DIVCLK
123
124#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
125#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
126
127#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
128#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
129
130#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
131#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
132
133#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
134#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
135
136#else
137#error "invalid STM32_MCO2PRE value specified"
138#endif
139
140/**
141 * @brief RTC HSE divider setting.
142 */
143#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
144 defined(__DOXYGEN__)
145#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16)
146#else
147#error "invalid STM32_RTCPRE value specified"
148#endif
149
150/**
151 * @brief HSE divider toward RTC clock.
152 */
153#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
154 defined(__DOXYGEN__)
155#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE)
156#else
157#error "invalid STM32_RTCPRE value specified"
158#endif
159
160/**
161 * @brief RTC clock.
162 */
163#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
164#define STM32_RTCCLK 0
165
166#elif STM32_RTCSEL == STM32_RTCSEL_LSE
167#define STM32_RTCCLK STM32_LSECLK
168
169#elif STM32_RTCSEL == STM32_RTCSEL_LSI
170#define STM32_RTCCLK STM32_LSICLK
171
172#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
173#define STM32_RTCCLK STM32_HSEDIVCLK
174
175#else
176#error "invalid STM32_RTCSEL value specified"
177#endif
178
179/**
180 * @brief 48MHz frequency.
181 */
182#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
183#if STM32_HAS_RCC_CK48MSEL || defined(__DOXYGEN__)
184#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
185#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
186#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLALT
187#define STM32_PLL48CLK STM32_PLL48CLK_ALTSRC
188#else
189#error "invalid source selected for PLL48CLK clock"
190#endif
191#else /* !STM32_HAS_RCC_CK48MSEL */
192#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
193#endif /* !STM32_HAS_RCC_CK48MSEL */
194#else /* !STM32_CLOCK48_REQUIRED */
195#define STM32_PLL48CLK 0
196#endif /* STM32_CLOCK48_REQUIRED */
197
198#if !STM32_HAS_RCC_DCKCFGR || (STM32_TIMPRE == STM32_TIMPRE_PCLK) || \
199 defined(__DOXYGEN__)
200/**
201 * @brief Clock of timers connected to APB1
202 * (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14).
203 */
204#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
205#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
206#else
207#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
208#endif
209
210/**
211 * @brief Clock of timers connected to APB2 (Timers 1, 8, 9, 10, 11).
212 */
213#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
214#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
215#else
216#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
217#endif
218
219#else /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
220#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \
221 (STM32_PPRE1 == STM32_PPRE1_DIV2) || \
222 ((STM32_PPRE1 == STM32_PPRE1_DIV4) && \
223 (STM32_TIMPRE_PRESCALE4 == TRUE)) || defined(__DOXYGEN__)
224#define STM32_TIMCLK1 STM32_HCLK
225#else
226#define STM32_TIMCLK1 (STM32_PCLK1 * 4)
227#endif
228
229#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || \
230 (STM32_PPRE2 == STM32_PPRE2_DIV2) || \
231 ((STM32_PPRE2 == STM32_PPRE2_DIV4) && \
232 (STM32_TIMPRE_PRESCALE4 == TRUE)) || defined(__DOXYGEN__)
233#define STM32_TIMCLK2 STM32_HCLK
234#else
235#define STM32_TIMCLK2 (STM32_PCLK2 * 4)
236#endif
237#endif /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
238
239/**
240 * @brief Flash settings.
241 */
242#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
243#define STM32_FLASHBITS 0x00000000
244#elif STM32_HCLK <= STM32_1WS_THRESHOLD
245#define STM32_FLASHBITS 0x00000001
246#elif STM32_HCLK <= STM32_2WS_THRESHOLD
247#define STM32_FLASHBITS 0x00000002
248#elif STM32_HCLK <= STM32_3WS_THRESHOLD
249#define STM32_FLASHBITS 0x00000003
250#elif STM32_HCLK <= STM32_4WS_THRESHOLD
251#define STM32_FLASHBITS 0x00000004
252#elif STM32_HCLK <= STM32_5WS_THRESHOLD
253#define STM32_FLASHBITS 0x00000005
254#elif STM32_HCLK <= STM32_6WS_THRESHOLD
255#define STM32_FLASHBITS 0x00000006
256#elif STM32_HCLK <= STM32_7WS_THRESHOLD
257#define STM32_FLASHBITS 0x00000007
258#elif STM32_HCLK <= STM32_8WS_THRESHOLD
259#define STM32_FLASHBITS 0x00000008
260#else
261#error "invalid frequency at specified VDD level"
262#endif
263
264/*===========================================================================*/
265/* Driver data structures and types. */
266/*===========================================================================*/
267
268/*===========================================================================*/
269/* Driver macros. */
270/*===========================================================================*/
271
272/*===========================================================================*/
273/* External declarations. */
274/*===========================================================================*/
275
276#endif /* HAL_LLD_H */
277
278/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h b/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
new file mode 100644
index 000000000..7db4df8f9
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
@@ -0,0 +1,1996 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F4xx/hal_lld_type1.h
19 * @brief STM32F4xx/STM32F2xx HAL subsystem low level driver header.
20 * @pre This module requires the following macros to be defined in the
21 * @p board.h file:
22 * - STM32_LSECLK.
23 * - STM32_LSE_BYPASS (optionally).
24 * - STM32_HSECLK.
25 * - STM32_HSE_BYPASS (optionally).
26 * - STM32_VDD (as hundredths of Volt).
27 * .
28 * One of the following macros must also be defined:
29 * - STM32F2XX for High-performance STM32F2 devices.
30 * - STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx,
31 * STM32F446xx for High-performance STM32F4 devices of
32 * Foundation line.
33 * - STM32F401xx, STM32F410xx, STM32F411xx, STM32F412xx
34 * for High-performance STM32F4 devices of Access line.
35 * - STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx, STM32F469xx,
36 * STM32F479xx for High-performance STM32F4 devices of Advanced line.
37 * .
38 *
39 * @addtogroup HAL
40 * @{
41 */
42
43#ifndef HAL_LLD_TYPE1_H
44#define HAL_LLD_TYPE1_H
45
46/*===========================================================================*/
47/* Driver constants. */
48/*===========================================================================*/
49
50/**
51 * @brief Defines the support for realtime counters in the HAL.
52 */
53#define HAL_IMPLEMENTS_COUNTERS TRUE
54
55/**
56 * @name Platform identification macros
57 * @{
58 */
59#if defined(STM32F205xx) || defined(__DOXYGEN__)
60#define PLATFORM_NAME "STM32F205 High Performance"
61
62#elif defined(STM32F207xx)
63#define PLATFORM_NAME "STM32F207 High Performance"
64
65#elif defined(STM32F215xx)
66#define PLATFORM_NAME "STM32F215 High Performance"
67
68#elif defined(STM32F217xx)
69#define PLATFORM_NAME "STM32F217 High Performance"
70
71#elif defined(STM32F401xx)
72#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU"
73
74#elif defined(STM32F405xx)
75#define PLATFORM_NAME "STM32F405 High Performance with DSP and FPU"
76
77#elif defined(STM32F407xx)
78#define PLATFORM_NAME "STM32F407 High Performance with DSP and FPU"
79
80#elif defined(STM32F410xx)
81#define PLATFORM_NAME "STM32F410 High Performance with DSP and FPU"
82
83#elif defined(STM32F411xx)
84#define PLATFORM_NAME "STM32F411 High Performance with DSP and FPU"
85
86#elif defined(STM32F412xx)
87#define PLATFORM_NAME "STM32F412 High Performance with DSP and FPU"
88
89#elif defined(STM32F415xx)
90#define PLATFORM_NAME "STM32F415 High Performance with DSP and FPU"
91
92#elif defined(STM32F417xx)
93#define PLATFORM_NAME "STM32F417 High Performance with DSP and FPU"
94
95#elif defined(STM32F427xx)
96#define PLATFORM_NAME "STM32F427 High Performance with DSP and FPU"
97
98#elif defined(STM32F429xx)
99#define PLATFORM_NAME "STM32F429 High Performance with DSP and FPU"
100
101#elif defined(STM32F437xx)
102#define PLATFORM_NAME "STM32F437 High Performance with DSP and FPU"
103
104#elif defined(STM32F439xx)
105#define PLATFORM_NAME "STM32F439 High Performance with DSP and FPU"
106
107#elif defined(STM32F446xx)
108#define PLATFORM_NAME "STM32F446 High Performance with DSP and FPU"
109
110#elif defined(STM32F469xx)
111#define PLATFORM_NAME "STM32F469 High Performance with DSP and FPU"
112
113#elif defined(STM32F479xx)
114#define PLATFORM_NAME "STM32F479 High Performance with DSP and FPU"
115
116#else
117#error "STM32F2xx/F4xx device not specified"
118#endif
119/** @} */
120
121/**
122 * @name Absolute Maximum Ratings
123 * @{
124 */
125#if defined(STM32F427xx) || defined(STM32F437xx) || \
126 defined(STM32F429xx) || defined(STM32F439xx) || \
127 defined(STM32F469xx) || defined(STM32F479xx) || defined(__DOXYGEN__)
128/**
129 * @brief Absolute maximum system clock.
130 */
131#define STM32_SYSCLK_MAX 180000000
132
133/**
134 * @brief Maximum HSE clock frequency.
135 */
136#define STM32_HSECLK_MAX 26000000
137
138/**
139 * @brief Maximum HSE clock frequency using an external source.
140 */
141#define STM32_HSECLK_BYP_MAX 50000000
142
143/**
144 * @brief Minimum HSE clock frequency.
145 */
146#define STM32_HSECLK_MIN 4000000
147
148/**
149 * @brief Minimum HSE clock frequency using an external source.
150 */
151#define STM32_HSECLK_BYP_MIN 1000000
152
153/**
154 * @brief Maximum LSE clock frequency.
155 */
156#define STM32_LSECLK_MAX 32768
157
158/**
159 * @brief Maximum LSE clock frequency using an external source.
160 */
161#define STM32_LSECLK_BYP_MAX 1000000
162
163/**
164 * @brief Minimum LSE clock frequency.
165 */
166#define STM32_LSECLK_MIN 32768
167
168/**
169 * @brief Maximum PLLs input clock frequency.
170 */
171#define STM32_PLLIN_MAX 2100000
172
173/**
174 * @brief Minimum PLLs input clock frequency.
175 */
176#define STM32_PLLIN_MIN 950000
177
178/**
179 * @brief Maximum PLLs VCO clock frequency.
180 */
181#define STM32_PLLVCO_MAX 432000000
182
183/**
184 * @brief Minimum PLLs VCO clock frequency.
185 */
186#define STM32_PLLVCO_MIN 192000000
187
188/**
189 * @brief Maximum PLL output clock frequency.
190 */
191#define STM32_PLLOUT_MAX 180000000
192
193/**
194 * @brief Minimum PLL output clock frequency.
195 */
196#define STM32_PLLOUT_MIN 24000000
197
198/**
199 * @brief Maximum PLLI2S output clock frequency.
200 */
201#define STM32_PLLI2SOUT_MAX 216000000
202
203/**
204 * @brief Maximum PLLSAI output clock frequency.
205 */
206#define STM32_PLLSAIOUT_MAX 216000000
207
208/**
209 * @brief Maximum APB1 clock frequency.
210 */
211#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4)
212
213/**
214 * @brief Maximum APB2 clock frequency.
215 */
216#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2)
217
218/**
219 * @brief Maximum SPI/I2S clock frequency.
220 */
221#define STM32_SPII2S_MAX 45000000
222#endif
223
224#if defined(STM32F40_41xxx)
225#define STM32_SYSCLK_MAX 168000000
226#define STM32_HSECLK_MAX 26000000
227#define STM32_HSECLK_BYP_MAX 50000000
228#define STM32_HSECLK_MIN 4000000
229#define STM32_HSECLK_BYP_MIN 1000000
230#define STM32_LSECLK_MAX 32768
231#define STM32_LSECLK_BYP_MAX 1000000
232#define STM32_LSECLK_MIN 32768
233#define STM32_PLLIN_MAX 2100000
234#define STM32_PLLIN_MIN 950000
235#define STM32_PLLVCO_MAX 432000000
236#define STM32_PLLVCO_MIN 192000000
237#define STM32_PLLOUT_MAX 168000000
238#define STM32_PLLOUT_MIN 24000000
239#define STM32_PCLK1_MAX 42000000
240#define STM32_PCLK2_MAX 84000000
241#define STM32_SPII2S_MAX 42000000
242#endif
243
244#if defined(STM32F401xx)
245#define STM32_SYSCLK_MAX 84000000
246#define STM32_HSECLK_MAX 26000000
247#define STM32_HSECLK_BYP_MAX 50000000
248#define STM32_HSECLK_MIN 4000000
249#define STM32_HSECLK_BYP_MIN 1000000
250#define STM32_LSECLK_MAX 32768
251#define STM32_LSECLK_BYP_MAX 1000000
252#define STM32_LSECLK_MIN 32768
253#define STM32_PLLIN_MAX 2100000
254#define STM32_PLLIN_MIN 950000
255#define STM32_PLLVCO_MAX 432000000
256#define STM32_PLLVCO_MIN 192000000
257#define STM32_PLLOUT_MAX 84000000
258#define STM32_PLLOUT_MIN 24000000
259#define STM32_PCLK1_MAX 42000000
260#define STM32_PCLK2_MAX 84000000
261#define STM32_SPII2S_MAX 42000000
262#endif
263
264#if defined(STM32F410xx) || defined(STM32F411xx) || \
265 defined(STM32F412xx)
266#define STM32_SYSCLK_MAX 100000000
267#define STM32_HSECLK_MAX 26000000
268#define STM32_HSECLK_BYP_MAX 50000000
269#define STM32_HSECLK_MIN 4000000
270#define STM32_HSECLK_BYP_MIN 1000000
271#define STM32_LSECLK_MAX 32768
272#define STM32_LSECLK_BYP_MAX 1000000
273#define STM32_LSECLK_MIN 32768
274#define STM32_PLLIN_MAX 2100000
275#define STM32_PLLIN_MIN 950000
276#define STM32_PLLVCO_MAX 432000000
277#define STM32_PLLVCO_MIN 100000000
278#define STM32_PLLOUT_MAX 100000000
279#define STM32_PLLOUT_MIN 24000000
280#define STM32_PCLK1_MAX 50000000
281#define STM32_PCLK2_MAX 100000000
282#define STM32_SPII2S_MAX 50000000
283#endif
284
285#if defined(STM32F446xx)
286#define STM32_SYSCLK_MAX 180000000
287#define STM32_HSECLK_MAX 26000000
288#define STM32_HSECLK_BYP_MAX 50000000
289#define STM32_HSECLK_MIN 4000000
290#define STM32_HSECLK_BYP_MIN 1000000
291#define STM32_LSECLK_MAX 32768
292#define STM32_LSECLK_BYP_MAX 1000000
293#define STM32_LSECLK_MIN 32768
294#define STM32_PLLIN_MAX 2100000
295#define STM32_PLLIN_MIN 950000
296#define STM32_PLLVCO_MAX 432000000
297#define STM32_PLLVCO_MIN 100000000
298#define STM32_PLLOUT_MAX 180000000
299#define STM32_PLLOUT_MIN 12500000
300#define STM32_PLLI2SOUT_MAX 216000000
301#define STM32_PLLSAIOUT_MAX 216000000
302#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4)
303#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2)
304#define STM32_SPII2S_MAX 45000000
305#endif
306
307#if defined(STM32F2XX)
308#define STM32_SYSCLK_MAX 120000000
309#define STM32_HSECLK_MAX 26000000
310#define STM32_HSECLK_BYP_MAX 26000000
311#define STM32_HSECLK_MIN 1000000
312#define STM32_HSECLK_BYP_MIN 1000000
313#define STM32_LSECLK_MAX 32768
314#define STM32_LSECLK_BYP_MAX 1000000
315#define STM32_LSECLK_MIN 32768
316#define STM32_PLLIN_MAX 2000000
317#define STM32_PLLIN_MIN 950000
318#define STM32_PLLVCO_MAX 432000000
319#define STM32_PLLVCO_MIN 192000000
320#define STM32_PLLOUT_MAX 120000000
321#define STM32_PLLOUT_MIN 24000000
322#define STM32_PCLK1_MAX 30000000
323#define STM32_PCLK2_MAX 60000000
324#define STM32_SPII2S_MAX 30000000
325#endif
326/** @} */
327
328/**
329 * @name Internal clock sources
330 * @{
331 */
332#define STM32_HSICLK 16000000 /**< High speed internal clock. */
333#define STM32_LSICLK 32000 /**< Low speed internal clock. */
334/** @} */
335
336/**
337 * @name PWR_CR register bits definitions
338 * @{
339 */
340#define STM32_VOS_SCALE3 0x00004000
341#define STM32_VOS_SCALE2 0x00008000
342#define STM32_VOS_SCALE1 0x0000C000
343#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
344#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
345#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
346#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
347#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
348#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
349#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
350#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
351#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
352/** @} */
353
354/**
355 * @name RCC_PLLCFGR register bits definitions
356 * @{
357 */
358#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */
359#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */
360#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */
361#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */
362#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */
363
364#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */
365#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */
366/** @} */
367
368/**
369 * @name RCC_CFGR register bits definitions
370 * @{
371 */
372#define STM32_SW_MASK (3 << 0) /**< SW mask. */
373#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
374#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
375#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
376
377#define STM32_HPRE_MASK (15 << 4) /**< HPRE mask. */
378#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
379#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
380#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
381#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
382#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
383#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
384#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
385#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
386#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
387
388#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */
389#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */
390#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */
391#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */
392#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */
393#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */
394
395#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */
396#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */
397#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */
398#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */
399#define STM32_PPRE2_DIV8 (6 << 13) /**< HCLK divided by 8. */
400#define STM32_PPRE2_DIV16 (7 << 13) /**< HCLK divided by 16. */
401
402#define STM32_RTCPRE_MASK (31 << 16) /**< RTCPRE mask. */
403
404#define STM32_MCO1SEL_MASK (3 << 21) /**< MCO1 mask. */
405#define STM32_MCO1SEL_HSI (0 << 21) /**< HSI clock on MCO1 pin. */
406#define STM32_MCO1SEL_LSE (1 << 21) /**< LSE clock on MCO1 pin. */
407#define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */
408#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */
409
410#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */
411#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */
412#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */
413
414#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */
415#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */
416#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */
417#define STM32_MCO1PRE_DIV3 (5 << 24) /**< MCO1 divided by 3. */
418#define STM32_MCO1PRE_DIV4 (6 << 24) /**< MCO1 divided by 4. */
419#define STM32_MCO1PRE_DIV5 (7 << 24) /**< MCO1 divided by 5. */
420
421#define STM32_MCO2PRE_MASK (7 << 27) /**< MCO2PRE mask. */
422#define STM32_MCO2PRE_DIV1 (0 << 27) /**< MCO2 divided by 1. */
423#define STM32_MCO2PRE_DIV2 (4 << 27) /**< MCO2 divided by 2. */
424#define STM32_MCO2PRE_DIV3 (5 << 27) /**< MCO2 divided by 3. */
425#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */
426#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */
427
428#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */
429#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */
430#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */
431#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */
432#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */
433
434/**
435 * @name RCC_PLLI2SCFGR register bits definitions
436 * @{
437 */
438#define STM32_PLLI2SM_MASK (31 << 0) /**< PLLI2SM mask. */
439#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */
440#define STM32_PLLI2SP_MASK (3 << 16) /**< PLLI2SP mask. */
441#define STM32_PLLI2SP_DIV2 (0 << 16) /**< PLLI2S clock divided by 2. */
442#define STM32_PLLI2SP_DIV4 (1 << 16) /**< PLLI2S clock divided by 4. */
443#define STM32_PLLI2SP_DIV6 (2 << 16) /**< PLLI2S clock divided by 6. */
444#define STM32_PLLI2SP_DIV8 (3 << 16) /**< PLLI2S clock divided by 8. */
445#define STM32_PLLI2SSRC_MASK (1 << 22) /**< PLLI2SSRC mask. */
446#define STM32_PLLI2SSRC_PLLSRC (0 << 22) /**< PLLI2SSRC is selected PLL
447 source. */
448#define STM32_PLLI2SSRC_CKIN (1 << 22) /**< PLLI2SSRC is I2S_CKIN. */
449#define STM32_PLLI2SQ_MASK (15 << 24) /**< PLLI2SQ mask. */
450#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
451/** @} */
452
453/**
454 * @name RCC_PLLSAICFGR register bits definitions
455 * @{
456 */
457#define STM32_PLLSAIM_MASK (31 << 0) /**< PLLSAIM mask. */
458#define STM32_PLLSAIN_MASK (511 << 6) /**< PLLSAIN mask. */
459#define STM32_PLLSAIP_MASK (3 << 16) /**< PLLSAIP mask. */
460#define STM32_PLLSAIP_DIV2 (0 << 16) /**< PLLSAI clock divided by 2. */
461#define STM32_PLLSAIP_DIV4 (1 << 16) /**< PLLSAI clock divided by 4. */
462#define STM32_PLLSAIP_DIV6 (2 << 16) /**< PLLSAI clock divided by 6. */
463#define STM32_PLLSAIP_DIV8 (3 << 16) /**< PLLSAI clock divided by 8. */
464#define STM32_PLLSAIQ_MASK (15 << 24) /**< PLLSAIQ mask. */
465#define STM32_PLLSAIR_MASK (7 << 28) /**< PLLSAIR mask. */
466/** @} */
467
468/**
469 * @name RCC_BDCR register bits definitions
470 * @{
471 */
472#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */
473#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */
474#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */
475#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */
476#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */
477/** @} */
478
479/**
480 * @name RCC_DCKCFGR register bits definitions
481 * @{
482 */
483#define STM32_PLLI2SDIVQ_MASK (31 << 0) /**< PLLI2SDIVQ mask. */
484#define STM32_PLLSAIDIVQ_MASK (31 << 8) /**< PLLSAIDIVQ mask. */
485
486#define STM32_PLLSAIDIVR_MASK (3 << 16) /**< PLLSAIDIVR mask. */
487#define STM32_PLLSAIDIVR_DIV2 (0 << 16) /**< LCD_CLK is R divided by 2. */
488#define STM32_PLLSAIDIVR_DIV4 (1 << 16) /**< LCD_CLK is R divided by 4. */
489#define STM32_PLLSAIDIVR_DIV8 (2 << 16) /**< LCD_CLK is R divided by 8. */
490#define STM32_PLLSAIDIVR_DIV16 (3 << 16) /**< LCD_CLK is R divided by 16.*/
491#define STM32_PLLSAIDIVR_OFF 0xFFFFFFFFU /**< LCD CLK is not required. */
492
493#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */
494#define STM32_SAI1SEL_PLLSAI (0 << 20) /**< SAI1 source is PLLSAI. */
495#define STM32_SAI1SEL_PLLI2S (1 << 20) /**< SAI1 source is PLLI2S. */
496#define STM32_SAI1SEL_PLLR (2 << 20) /**< SAI1 source is PLLR. */
497#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
498
499#define STM32_SAI2SEL_MASK (3 << 22) /**< SAI2SEL mask. */
500#define STM32_SAI2SEL_PLLSAI (0 << 22) /**< SAI2 source is PLLSAI. */
501#define STM32_SAI2SEL_PLLI2S (1 << 22) /**< SAI2 source is PLLI2S. */
502#define STM32_SAI2SEL_PLLR (2 << 22) /**< SAI2 source is PLLR. */
503#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
504
505#define STM32_TIMPRE_MASK (1 << 24) /**< TIMPRE mask. */
506#define STM32_TIMPRE_PCLK (0 << 24) /**< TIM clocks from PCLKx. */
507#define STM32_TIMPRE_HCLK (1 << 24) /**< TIM clocks from HCLK. */
508
509#define STM32_I2S1SEL_MASK (3 << 25) /**< I2S1SEL mask. */
510#define STM32_I2S1SEL_PLLR (0 << 25) /**< I2S1 source is PLLR. */
511#define STM32_I2S1SEL_AFIN (1 << 25) /**< I2S1 source is AF Input. */
512#define STM32_I2S1SEL_MCO1 (2 << 25) /**< I2S1 source is MCO1. */
513#define STM32_I2S1SEL_OFF 0xFFFFFFFFU /**< I2S1 clock is not required.*/
514
515#define STM32_I2S2SEL_MASK (3 << 27) /**< I2S2SEL mask. */
516#define STM32_I2S2SEL_PLLR (0 << 27) /**< I2S2 source is PLLR. */
517#define STM32_I2S2SEL_AFIN (1 << 27) /**< I2S2 source is AF Input. */
518#define STM32_I2S2SEL_MCO1 (2 << 27) /**< I2S2 source is MCO1. */
519#define STM32_I2S2SEL_OFF 0xFFFFFFFFU /**< I2S2 clock is not required.*/
520
521#define STM32_DSISEL_MASK (1 << 28) /**< DSISEL mask. */
522#define STM32_DSISEL_PHY (0 << 28) /**< DSI source is DSI-PSY. */
523#define STM32_DSISEL_PLLR (1 << 28) /**< DSI source is PLLR. */
524/** @} */
525
526/**
527 * @name RCC_DCKCFGR2 register bits definitions
528 * @{
529 */
530#define STM32_I2C1SEL_MASK (3 << 22) /**< I2C1SEL mask. */
531#define STM32_I2C1SEL_PCLK1 (0 << 22) /**< I2C1 source is APB/PCLK1. */
532#define STM32_I2C1SEL_SYSCLK (1 << 22) /**< I2C1 source is SYSCLK. */
533#define STM32_I2C1SEL_HSI (2 << 22) /**< I2C1 source is HSI. */
534
535#define STM32_CECSEL_MASK (1 << 26) /**< CECSEL mask. */
536#define STM32_CECSEL_LSE (0 << 26) /**< CEC source is LSE. */
537#define STM32_CECSEL_HSIDIV488 (1 << 26) /**< CEC source is HSI/488. */
538
539#define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */
540#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
541#define STM32_CK48MSEL_PLLSAI (1 << 27) /**< PLL48CLK source is PLLSAI. */
542#define STM32_CK48MSEL_PLLALT (1 << 27) /**< Alias. */
543
544#define STM32_SDMMCSEL_MASK (1 << 28) /**< SDMMCSEL mask. */
545#define STM32_SDMMCSEL_PLL48CLK (0 << 28) /**< SDMMC source is PLL48CLK. */
546#define STM32_SDMMCSEL_SYSCLK (1 << 28) /**< SDMMC source is SYSCLK. */
547
548#define STM32_SPDIFSEL_MASK (1 << 29) /**< SPDIFSEL mask. */
549#define STM32_SPDIFSEL_PLLI2S (0 << 29) /**< SPDIF source is PLLI2S. */
550#define STM32_SPDIFSEL_PLL (1 << 29) /**< SPDIF source is PLL. */
551
552#define STM32_LPTIM1SEL_MASK (3 << 30) /**< LPTIM1 mask. */
553#define STM32_LPTIM1SEL_APB (0 << 30) /**< LPTIM1 source is APB. */
554#define STM32_LPTIM1SEL_HSI (1 << 30) /**< LPTIM1 source is HSI. */
555#define STM32_LPTIM1SEL_LSI (2 << 30) /**< LPTIM1 source is LSI. */
556#define STM32_LPTIM1SEL_LSE (3 << 30) /**< LPTIM1 source is LSE. */
557/** @} */
558
559/*===========================================================================*/
560/* Driver pre-compile time settings. */
561/*===========================================================================*/
562
563/**
564 * @name Configuration options
565 * @{
566 */
567/**
568 * @brief Disables the PWR/RCC initialization in the HAL.
569 */
570#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
571#define STM32_NO_INIT FALSE
572#endif
573
574/**
575 * @brief Enables or disables the programmable voltage detector.
576 */
577#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
578#define STM32_PVD_ENABLE FALSE
579#endif
580
581/**
582 * @brief Sets voltage level for programmable voltage detector.
583 */
584#if !defined(STM32_PLS) || defined(__DOXYGEN__)
585#define STM32_PLS STM32_PLS_LEV0
586#endif
587
588/**
589 * @brief Enables the backup RAM regulator.
590 */
591#if !defined(STM32_BKPRAM_ENABLE) || defined(__DOXYGEN__)
592#define STM32_BKPRAM_ENABLE FALSE
593#endif
594
595/**
596 * @brief Enables or disables the HSI clock source.
597 */
598#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
599#define STM32_HSI_ENABLED TRUE
600#endif
601
602/**
603 * @brief Enables or disables the LSI clock source.
604 */
605#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
606#define STM32_LSI_ENABLED FALSE
607#endif
608
609/**
610 * @brief Enables or disables the HSE clock source.
611 */
612#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
613#define STM32_HSE_ENABLED TRUE
614#endif
615
616/**
617 * @brief Enables or disables the LSE clock source.
618 */
619#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
620#define STM32_LSE_ENABLED FALSE
621#endif
622
623/**
624 * @brief USB/SDIO clock setting.
625 */
626#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__)
627#define STM32_CLOCK48_REQUIRED TRUE
628#endif
629
630/**
631 * @brief Main clock source selection.
632 * @note If the selected clock source is not the PLL then the PLL is not
633 * initialized and started.
634 * @note The default value is calculated for a 168MHz system clock from
635 * an external 8MHz HSE clock.
636 */
637#if !defined(STM32_SW) || defined(__DOXYGEN__)
638#define STM32_SW STM32_SW_PLL
639#endif
640
641#if defined(STM32F4XX) || defined(__DOXYGEN__)
642/**
643 * @brief Clock source for the PLLs.
644 * @note This setting has only effect if the PLL is selected as the
645 * system clock source.
646 * @note The default value is calculated for a 168MHz system clock from
647 * an external 8MHz HSE clock.
648 */
649#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
650#define STM32_PLLSRC STM32_PLLSRC_HSE
651#endif
652
653/**
654 * @brief PLLM divider value.
655 * @note The allowed values are 2..63.
656 * @note The default value is calculated for a 168MHz system clock from
657 * an external 8MHz HSE clock.
658 */
659#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
660#define STM32_PLLM_VALUE 8
661#endif
662
663/**
664 * @brief PLLN multiplier value.
665 * @note The allowed values are 192..432.
666 * @note The default value is calculated for a 168MHz system clock from
667 * an external 8MHz HSE clock.
668 */
669#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
670#define STM32_PLLN_VALUE 336
671#endif
672
673/**
674 * @brief PLLP divider value.
675 * @note The allowed values are 2, 4, 6, 8.
676 * @note The default value is calculated for a 168MHz system clock from
677 * an external 8MHz HSE clock.
678 */
679#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
680#define STM32_PLLP_VALUE 2
681#endif
682
683/**
684 * @brief PLLQ multiplier value.
685 * @note The allowed values are 2..15.
686 * @note The default value is calculated for a 168MHz system clock from
687 * an external 8MHz HSE clock.
688 */
689#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
690#define STM32_PLLQ_VALUE 7
691#endif
692
693/**
694 * @brief PLLR divider value.
695 * @note The allowed values are 2..7.
696 * @note The default value is calculated for a 96MHz system clock from
697 * an external 8MHz HSE clock.
698 */
699#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
700#define STM32_PLLR_VALUE 4
701#endif
702
703#else /* !defined(STM32F4XX) */
704/**
705 * @brief Clock source for the PLLs.
706 * @note This setting has only effect if the PLL is selected as the
707 * system clock source.
708 * @note The default value is calculated for a 120MHz system clock from
709 * an external 8MHz HSE clock.
710 */
711#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
712#define STM32_PLLSRC STM32_PLLSRC_HSE
713#endif
714
715/**
716 * @brief PLLM divider value.
717 * @note The allowed values are 2..63.
718 * @note The default value is calculated for a 120MHz system clock from
719 * an external 8MHz HSE clock.
720 */
721#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
722#define STM32_PLLM_VALUE 8
723#endif
724
725/**
726 * @brief PLLN multiplier value.
727 * @note The allowed values are 192..432.
728 * @note The default value is calculated for a 120MHz system clock from
729 * an external 8MHz HSE clock.
730 */
731#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
732#define STM32_PLLN_VALUE 240
733#endif
734
735/**
736 * @brief PLLP divider value.
737 * @note The allowed values are 2, 4, 6, 8.
738 * @note The default value is calculated for a 120MHz system clock from
739 * an external 8MHz HSE clock.
740 */
741#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
742#define STM32_PLLP_VALUE 2
743#endif
744
745/**
746 * @brief PLLQ multiplier value.
747 * @note The allowed values are 2..15.
748 * @note The default value is calculated for a 120MHz system clock from
749 * an external 8MHz HSE clock.
750 */
751#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
752#define STM32_PLLQ_VALUE 5
753#endif
754#endif /* !defined(STM32F4XX) */
755
756/**
757 * @brief I2S clock source (post-PLL).
758 * @note Not all devices have this setting, it is alternative to
759 * @p STM32_PLLI2SSRC.
760 */
761#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)
762#define STM32_I2SSRC STM32_I2SSRC_CKIN
763#endif
764
765/**
766 * @brief I2S clock source (pre-PLL).
767 * @note Not all devices have this setting, it is alternative to
768 * @p STM32_I2SSRC.
769 */
770#if !defined(STM32_PLLI2SSRC) || defined(__DOXYGEN__)
771#define STM32_PLLI2SSRC STM32_PLLI2SSRC_CKIN
772#endif
773
774/**
775 * @brief I2S external clock value, zero if not present.
776 * @note Not all devices have this setting.
777 */
778#if !defined(STM32_I2SCKIN_VALUE) || defined(__DOXYGEN__)
779#define STM32_I2SCKIN_VALUE 0
780#endif
781
782/**
783 * @brief PLLI2SN multiplier value.
784 * @note The allowed values are 192..432, except for
785 * STM32F446 where values are 50...432.
786 * @note The default value is calculated for a 96MHz I2S clock
787 * output from an external 8MHz HSE clock.
788 */
789#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
790#define STM32_PLLI2SN_VALUE 192
791#endif
792
793/**
794 * @brief PLLI2SM divider value.
795 * @note The allowed values are 2..63.
796 * @note The default value is calculated for a 96MHz I2S clock
797 * output from an external 8MHz HSE clock.
798 */
799#if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__)
800#define STM32_PLLI2SM_VALUE 4
801#endif
802
803/**
804 * @brief PLLI2SR divider value.
805 * @note The allowed values are 2..7.
806 * @note The default value is calculated for a 96MHz I2S clock
807 * output from an external 8MHz HSE clock.
808 */
809#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
810#define STM32_PLLI2SR_VALUE 4
811#endif
812
813/**
814 * @brief PLLI2SP divider value.
815 * @note The allowed values are 2, 4, 6 and 8.
816 */
817#if !defined(STM32_PLLI2SP_VALUE) || defined(__DOXYGEN__)
818#define STM32_PLLI2SP_VALUE 4
819#endif
820
821/**
822 * @brief PLLI2SQ divider value.
823 * @note The allowed values are 2..15.
824 */
825#if !defined(STM32_PLLI2SQ_VALUE) || defined(__DOXYGEN__)
826#define STM32_PLLI2SQ_VALUE 4
827#endif
828
829/**
830 * @brief PLLI2SDIVQ divider value (SAI clock divider).
831 * @note The allowed values are 1..32.
832 */
833#if !defined(STM32_PLLI2SDIVQ_VALUE) || defined(__DOXYGEN__)
834#define STM32_PLLI2SDIVQ_VALUE 1
835#endif
836
837/**
838 * @brief PLLSAIM value.
839 * @note The allowed values are 2..63.
840 * @note The default value is calculated for a 96MHz SAI clock
841 * output from an external 8MHz HSE clock.
842 */
843#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__)
844#define STM32_PLLSAIM_VALUE 4
845#endif
846
847/**
848 * @brief PLLSAIN value.
849 * @note The allowed values are 50..432.
850 * @note The default value is calculated for a 96MHz SAI clock
851 * output from an external 8MHz HSE clock.
852 */
853#if !defined(STM32_PLLSAIN_VALUE) || defined(__DOXYGEN__)
854#define STM32_PLLSAIN_VALUE 192
855#endif
856
857/**
858 * @brief PLLSAIM value.
859 * @note The allowed values are 2..63.
860 * @note The default value is calculated for a 96MHz SAI clock
861 * output from an external 8MHz HSE clock.
862 */
863#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__)
864#define STM32_PLLSAIM_VALUE 4
865#endif
866
867/**
868 * @brief PLLSAIR value.
869 * @note The allowed values are 2..7.
870 */
871#if !defined(STM32_PLLSAIR_VALUE) || defined(__DOXYGEN__)
872#define STM32_PLLSAIR_VALUE 4
873#endif
874
875/**
876 * @brief PLLSAIP divider value.
877 * @note The allowed values are 2, 4, 6 and 8.
878 */
879#if !defined(STM32_PLLSAIP_VALUE) || defined(__DOXYGEN__)
880#define STM32_PLLSAIP_VALUE 8
881#endif
882
883/**
884 * @brief PLLSAIQ value.
885 * @note The allowed values are 2..15.
886 */
887#if !defined(STM32_PLLSAIQ_VALUE) || defined(__DOXYGEN__)
888#define STM32_PLLSAIQ_VALUE 4
889#endif
890
891/**
892 * @brief PLLSAIDIVR divider value (SAI clock divider).
893 */
894#if !defined(STM32_PLLSAIDIVR) || defined(__DOXYGEN__)
895#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
896#endif
897
898/**
899 * @brief PLLSAIDIVQ divider value (LCD clock divider).
900 * @note The allowed values are 1..32.
901 */
902#if !defined(STM32_PLLSAIDIVQ_VALUE) || defined(__DOXYGEN__)
903#define STM32_PLLSAIDIVQ_VALUE 1
904#endif
905
906/**
907 * @brief SAI1SEL value (SAI1 clock source).
908 */
909#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
910#define STM32_SAI1SEL STM32_SAI1SEL_OFF
911#endif
912
913/**
914 * @brief SAI2SEL value (SAI2 clock source).
915 */
916#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__)
917#define STM32_SAI2SEL STM32_SAI2SEL_OFF
918#endif
919
920/**
921 * @brief TIM prescaler clock source.
922 */
923#if !defined(STM32_TIMPRE) || defined(__DOXYGEN__)
924#define STM32_TIMPRE STM32_TIMPRE_PCLK
925#endif
926
927/**
928 * @brief PLL48CLK clock source.
929 */
930#if !defined(STM32_CK48MSEL) || defined(__DOXYGEN__)
931#define STM32_CK48MSEL STM32_CK48MSEL_PLL
932#endif
933
934/**
935 * @brief AHB prescaler value.
936 */
937#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
938#define STM32_HPRE STM32_HPRE_DIV1
939#endif
940
941/**
942 * @brief APB1 prescaler value.
943 */
944#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
945#define STM32_PPRE1 STM32_PPRE1_DIV4
946#endif
947
948/**
949 * @brief APB2 prescaler value.
950 */
951#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
952#define STM32_PPRE2 STM32_PPRE2_DIV2
953#endif
954
955/**
956 * @brief RTC clock source.
957 */
958#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
959#define STM32_RTCSEL STM32_RTCSEL_LSE
960#endif
961
962/**
963 * @brief RTC HSE prescaler value.
964 */
965#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__)
966#define STM32_RTCPRE_VALUE 8
967#endif
968
969/**
970 * @brief MCO1 clock source value.
971 * @note The default value outputs HSI clock on MCO1 pin.
972 */
973#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__)
974#define STM32_MCO1SEL STM32_MCO1SEL_HSI
975#endif
976
977/**
978 * @brief MCO1 prescaler value.
979 * @note The default value outputs HSI clock on MCO1 pin.
980 */
981#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)
982#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
983#endif
984
985/**
986 * @brief MCO2 clock source value.
987 * @note The default value outputs SYSCLK / 5 on MCO2 pin.
988 */
989#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
990#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
991#endif
992
993/**
994 * @brief MCO2 prescaler value.
995 * @note The default value outputs SYSCLK / 5 on MCO2 pin.
996 */
997#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
998#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
999#endif
1000/** @} */
1001
1002/*===========================================================================*/
1003/* Derived constants and error checks. */
1004/*===========================================================================*/
1005
1006#if defined(STM32F4XX) || defined(__DOXYGEN__)
1007/*
1008 * Configuration-related checks.
1009 */
1010#if !defined(STM32F4xx_MCUCONF)
1011#error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined"
1012#endif
1013
1014#if defined(STM32F405xx) && !defined(STM32F405_MCUCONF)
1015#error "Using a wrong mcuconf.h file, STM32F405_MCUCONF not defined"
1016#endif
1017
1018#if defined(STM32F415xx) && !defined(STM32F415_MCUCONF)
1019#error "Using a wrong mcuconf.h file, STM32F415_MCUCONF not defined"
1020#endif
1021
1022#if defined(STM32F407xx) && !defined(STM32F407_MCUCONF)
1023#error "Using a wrong mcuconf.h file, STM32F407_MCUCONF not defined"
1024#endif
1025
1026#if defined(STM32F417xx) && !defined(STM32F417_MCUCONF)
1027#error "Using a wrong mcuconf.h file, STM32F417_MCUCONF not defined"
1028#endif
1029
1030#else /* !defined(STM32F4XX) */
1031/*
1032 * Configuration-related checks.
1033 */
1034#if !defined(STM32F2xx_MCUCONF)
1035#error "Using a wrong mcuconf.h file, STM32F2xx_MCUCONF not defined"
1036#endif
1037#endif /* !defined(STM32F4XX) */
1038
1039/**
1040 * @name Maximum frequency thresholds, wait states and
1041 * parallelism for flash access.
1042 * @{
1043 */
1044#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
1045 defined(STM32F40_41xxx) || defined(STM32F446xx) || \
1046 defined(STM32F469_479xx) || defined(__DOXYGEN__)
1047#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)
1048#define STM32_0WS_THRESHOLD 30000000
1049#define STM32_1WS_THRESHOLD 60000000
1050#define STM32_2WS_THRESHOLD 90000000
1051#define STM32_3WS_THRESHOLD 120000000
1052#define STM32_4WS_THRESHOLD 150000000
1053#define STM32_5WS_THRESHOLD 180000000
1054#define STM32_6WS_THRESHOLD 0
1055#define STM32_7WS_THRESHOLD 0
1056#define STM32_8WS_THRESHOLD 0
1057#define STM32_FLASH_PSIZE 2
1058#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
1059#define STM32_0WS_THRESHOLD 24000000
1060#define STM32_1WS_THRESHOLD 48000000
1061#define STM32_2WS_THRESHOLD 72000000
1062#define STM32_3WS_THRESHOLD 96000000
1063#define STM32_4WS_THRESHOLD 120000000
1064#define STM32_5WS_THRESHOLD 144000000
1065#define STM32_6WS_THRESHOLD 168000000
1066#define STM32_7WS_THRESHOLD 180000000
1067#define STM32_8WS_THRESHOLD 0
1068#define STM32_FLASH_PSIZE 1
1069#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
1070#define STM32_0WS_THRESHOLD 22000000
1071#define STM32_1WS_THRESHOLD 44000000
1072#define STM32_2WS_THRESHOLD 66000000
1073#define STM32_3WS_THRESHOLD 88000000
1074#define STM32_4WS_THRESHOLD 110000000
1075#define STM32_5WS_THRESHOLD 132000000
1076#define STM32_6WS_THRESHOLD 154000000
1077#define STM32_7WS_THRESHOLD 176000000
1078#define STM32_8WS_THRESHOLD 180000000
1079#define STM32_FLASH_PSIZE 1
1080#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
1081#define STM32_0WS_THRESHOLD 20000000
1082#define STM32_1WS_THRESHOLD 40000000
1083#define STM32_2WS_THRESHOLD 60000000
1084#define STM32_3WS_THRESHOLD 80000000
1085#define STM32_4WS_THRESHOLD 100000000
1086#define STM32_5WS_THRESHOLD 120000000
1087#define STM32_6WS_THRESHOLD 140000000
1088#define STM32_7WS_THRESHOLD 168000000
1089#define STM32_8WS_THRESHOLD 0
1090#define STM32_FLASH_PSIZE 0
1091#else
1092#error "invalid VDD voltage specified"
1093#endif
1094
1095#elif defined(STM32F412xx)
1096#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
1097#define STM32_0WS_THRESHOLD 30000000
1098#define STM32_1WS_THRESHOLD 64000000
1099#define STM32_2WS_THRESHOLD 90000000
1100#define STM32_3WS_THRESHOLD 100000000
1101#define STM32_4WS_THRESHOLD 0
1102#define STM32_5WS_THRESHOLD 0
1103#define STM32_6WS_THRESHOLD 0
1104#define STM32_7WS_THRESHOLD 0
1105#define STM32_8WS_THRESHOLD 0
1106#define STM32_FLASH_PSIZE 2
1107#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
1108#define STM32_0WS_THRESHOLD 24000000
1109#define STM32_1WS_THRESHOLD 48000000
1110#define STM32_2WS_THRESHOLD 72000000
1111#define STM32_3WS_THRESHOLD 96000000
1112#define STM32_4WS_THRESHOLD 100000000
1113#define STM32_5WS_THRESHOLD 0
1114#define STM32_6WS_THRESHOLD 0
1115#define STM32_7WS_THRESHOLD 0
1116#define STM32_8WS_THRESHOLD 0
1117#define STM32_FLASH_PSIZE 1
1118#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
1119#define STM32_0WS_THRESHOLD 18000000
1120#define STM32_1WS_THRESHOLD 36000000
1121#define STM32_2WS_THRESHOLD 54000000
1122#define STM32_3WS_THRESHOLD 72000000
1123#define STM32_4WS_THRESHOLD 90000000
1124#define STM32_5WS_THRESHOLD 100000000
1125#define STM32_6WS_THRESHOLD 0
1126#define STM32_7WS_THRESHOLD 0
1127#define STM32_8WS_THRESHOLD 0
1128#define STM32_FLASH_PSIZE 1
1129#elif (STM32_VDD >= 170) && (STM32_VDD < 210)
1130#define STM32_0WS_THRESHOLD 16000000
1131#define STM32_1WS_THRESHOLD 32000000
1132#define STM32_2WS_THRESHOLD 48000000
1133#define STM32_3WS_THRESHOLD 64000000
1134#define STM32_4WS_THRESHOLD 80000000
1135#define STM32_5WS_THRESHOLD 96000000
1136#define STM32_6WS_THRESHOLD 100000000
1137#define STM32_7WS_THRESHOLD 0
1138#define STM32_8WS_THRESHOLD 0
1139#define STM32_FLASH_PSIZE 0
1140#else
1141#error "invalid VDD voltage specified"
1142#endif
1143
1144#elif defined(STM32F410xx) || defined(STM32F411xx)
1145#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
1146#define STM32_0WS_THRESHOLD 30000000
1147#define STM32_1WS_THRESHOLD 64000000
1148#define STM32_2WS_THRESHOLD 90000000
1149#define STM32_3WS_THRESHOLD 100000000
1150#define STM32_4WS_THRESHOLD 0
1151#define STM32_5WS_THRESHOLD 0
1152#define STM32_6WS_THRESHOLD 0
1153#define STM32_7WS_THRESHOLD 0
1154#define STM32_8WS_THRESHOLD 0
1155#define STM32_FLASH_PSIZE 2
1156#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
1157#define STM32_0WS_THRESHOLD 24000000
1158#define STM32_1WS_THRESHOLD 48000000
1159#define STM32_2WS_THRESHOLD 72000000
1160#define STM32_3WS_THRESHOLD 96000000
1161#define STM32_4WS_THRESHOLD 100000000
1162#define STM32_5WS_THRESHOLD 0
1163#define STM32_6WS_THRESHOLD 0
1164#define STM32_7WS_THRESHOLD 0
1165#define STM32_8WS_THRESHOLD 0
1166#define STM32_FLASH_PSIZE 1
1167#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
1168#define STM32_0WS_THRESHOLD 18000000
1169#define STM32_1WS_THRESHOLD 36000000
1170#define STM32_2WS_THRESHOLD 54000000
1171#define STM32_3WS_THRESHOLD 72000000
1172#define STM32_4WS_THRESHOLD 90000000
1173#define STM32_5WS_THRESHOLD 100000000
1174#define STM32_6WS_THRESHOLD 0
1175#define STM32_7WS_THRESHOLD 0
1176#define STM32_8WS_THRESHOLD 0
1177#define STM32_FLASH_PSIZE 1
1178#elif (STM32_VDD >= 171) && (STM32_VDD < 210)
1179#define STM32_0WS_THRESHOLD 16000000
1180#define STM32_1WS_THRESHOLD 32000000
1181#define STM32_2WS_THRESHOLD 48000000
1182#define STM32_3WS_THRESHOLD 64000000
1183#define STM32_4WS_THRESHOLD 80000000
1184#define STM32_5WS_THRESHOLD 96000000
1185#define STM32_6WS_THRESHOLD 100000000
1186#define STM32_7WS_THRESHOLD 0
1187#define STM32_8WS_THRESHOLD 0
1188#define STM32_FLASH_PSIZE 0
1189
1190#else
1191#error "invalid VDD voltage specified"
1192#endif
1193
1194#elif defined(STM32F401xx)
1195#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
1196#define STM32_0WS_THRESHOLD 30000000
1197#define STM32_1WS_THRESHOLD 60000000
1198#define STM32_2WS_THRESHOLD 84000000
1199#define STM32_3WS_THRESHOLD 0
1200#define STM32_4WS_THRESHOLD 0
1201#define STM32_5WS_THRESHOLD 0
1202#define STM32_6WS_THRESHOLD 0
1203#define STM32_7WS_THRESHOLD 0
1204#define STM32_8WS_THRESHOLD 0
1205#define STM32_FLASH_PSIZE 2
1206
1207#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
1208#define STM32_0WS_THRESHOLD 24000000
1209#define STM32_1WS_THRESHOLD 48000000
1210#define STM32_2WS_THRESHOLD 72000000
1211#define STM32_3WS_THRESHOLD 84000000
1212#define STM32_4WS_THRESHOLD 0
1213#define STM32_5WS_THRESHOLD 0
1214#define STM32_6WS_THRESHOLD 0
1215#define STM32_7WS_THRESHOLD 0
1216#define STM32_8WS_THRESHOLD 0
1217#define STM32_FLASH_PSIZE 1
1218
1219#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
1220#define STM32_0WS_THRESHOLD 18000000
1221#define STM32_1WS_THRESHOLD 36000000
1222#define STM32_2WS_THRESHOLD 54000000
1223#define STM32_3WS_THRESHOLD 72000000
1224#define STM32_4WS_THRESHOLD 84000000
1225#define STM32_5WS_THRESHOLD 0
1226#define STM32_6WS_THRESHOLD 0
1227#define STM32_7WS_THRESHOLD 0
1228#define STM32_8WS_THRESHOLD 0
1229#define STM32_FLASH_PSIZE 1
1230
1231#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
1232#define STM32_0WS_THRESHOLD 16000000
1233#define STM32_1WS_THRESHOLD 32000000
1234#define STM32_2WS_THRESHOLD 48000000
1235#define STM32_3WS_THRESHOLD 64000000
1236#define STM32_4WS_THRESHOLD 80000000
1237#define STM32_5WS_THRESHOLD 84000000
1238#define STM32_6WS_THRESHOLD 0
1239#define STM32_7WS_THRESHOLD 0
1240#define STM32_8WS_THRESHOLD 0
1241#define STM32_FLASH_PSIZE 0
1242
1243#else
1244#error "invalid VDD voltage specified"
1245#endif
1246
1247#else /* STM32F2XX */
1248#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
1249#define STM32_0WS_THRESHOLD 30000000
1250#define STM32_1WS_THRESHOLD 60000000
1251#define STM32_2WS_THRESHOLD 90000000
1252#define STM32_3WS_THRESHOLD 120000000
1253#define STM32_4WS_THRESHOLD 0
1254#define STM32_5WS_THRESHOLD 0
1255#define STM32_6WS_THRESHOLD 0
1256#define STM32_7WS_THRESHOLD 0
1257#define STM32_FLASH_PSIZE 2
1258#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
1259#define STM32_0WS_THRESHOLD 24000000
1260#define STM32_1WS_THRESHOLD 48000000
1261#define STM32_2WS_THRESHOLD 72000000
1262#define STM32_3WS_THRESHOLD 96000000
1263#define STM32_4WS_THRESHOLD 120000000
1264#define STM32_5WS_THRESHOLD 0
1265#define STM32_6WS_THRESHOLD 0
1266#define STM32_7WS_THRESHOLD 0
1267#define STM32_FLASH_PSIZE 1
1268#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
1269#define STM32_0WS_THRESHOLD 18000000
1270#define STM32_1WS_THRESHOLD 36000000
1271#define STM32_2WS_THRESHOLD 54000000
1272#define STM32_3WS_THRESHOLD 72000000
1273#define STM32_4WS_THRESHOLD 90000000
1274#define STM32_5WS_THRESHOLD 108000000
1275#define STM32_6WS_THRESHOLD 120000000
1276#define STM32_7WS_THRESHOLD 0
1277#define STM32_FLASH_PSIZE 1
1278#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
1279#define STM32_0WS_THRESHOLD 16000000
1280#define STM32_1WS_THRESHOLD 32000000
1281#define STM32_2WS_THRESHOLD 48000000
1282#define STM32_3WS_THRESHOLD 64000000
1283#define STM32_4WS_THRESHOLD 80000000
1284#define STM32_5WS_THRESHOLD 96000000
1285#define STM32_6WS_THRESHOLD 112000000
1286#define STM32_7WS_THRESHOLD 120000000
1287#define STM32_FLASH_PSIZE 0
1288
1289#else
1290#error "invalid VDD voltage specified"
1291#endif
1292#endif /* STM32F2XX */
1293/** @} */
1294
1295/*
1296 * HSI related checks.
1297 */
1298#if STM32_HSI_ENABLED
1299#else /* !STM32_HSI_ENABLED */
1300
1301#if STM32_SW == STM32_SW_HSI
1302#error "HSI not enabled, required by STM32_SW"
1303#endif
1304
1305#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
1306#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
1307#endif
1308
1309#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || \
1310 ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \
1311 (STM32_PLLSRC == STM32_PLLSRC_HSI))
1312#error "HSI not enabled, required by STM32_MCO1SEL"
1313#endif
1314
1315#if (STM32_MCO2SEL == STM32_MCO2SEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
1316#error "HSI not enabled, required by STM32_MCO2SEL"
1317#endif
1318
1319#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \
1320 (STM32_PLLSRC == STM32_PLLSRC_HSI)
1321#error "HSI not enabled, required by STM32_I2SSRC"
1322#endif
1323
1324#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) && \
1325 (STM32_PLLSRC == STM32_PLLSRC_HSI)
1326#error "HSI not enabled, required by STM32_I2SSRC"
1327#endif
1328
1329#if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \
1330 (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S)) && \
1331 (STM32_PLLSRC == STM32_PLLSRC_HSI)
1332#error "HSI not enabled, required by STM32_SAI1SEL"
1333#endif
1334
1335#if ((STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI) || \
1336 (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S)) && \
1337 (STM32_PLLSRC == STM32_PLLSRC_HSI)
1338#error "HSI not enabled, required by STM32_SAI2SEL"
1339#endif
1340#endif /* !STM32_HSI_ENABLED */
1341
1342/*
1343 * HSE related checks.
1344 */
1345#if STM32_HSE_ENABLED
1346
1347#if STM32_HSECLK == 0
1348#error "HSE frequency not defined"
1349#else /* STM32_HSECLK != 0 */
1350#if defined(STM32_HSE_BYPASS)
1351#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
1352#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_BYP_MAX)"
1353#endif
1354#else /* !defined(STM32_HSE_BYPASS) */
1355#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
1356#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
1357#endif
1358#endif /* !defined(STM32_HSE_BYPASS) */
1359#endif /* STM32_HSECLK != 0 */
1360#else /* !STM32_HSE_ENABLED */
1361
1362#if STM32_SW == STM32_SW_HSE
1363#error "HSE not enabled, required by STM32_SW"
1364#endif
1365
1366#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
1367#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
1368#endif
1369
1370#if (STM32_MCO1SEL == STM32_MCO1SEL_HSE) || \
1371 ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \
1372 (STM32_PLLSRC == STM32_PLLSRC_HSE))
1373#error "HSE not enabled, required by STM32_MCO1SEL"
1374#endif
1375
1376#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || \
1377 ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \
1378 (STM32_PLLSRC == STM32_PLLSRC_HSE))
1379#error "HSE not enabled, required by STM32_MCO2SEL"
1380#endif
1381
1382#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \
1383 (STM32_PLLSRC == STM32_PLLSRC_HSE)
1384#error "HSE not enabled, required by STM32_I2SSRC"
1385#endif
1386
1387#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) && \
1388 (STM32_PLLSRC == STM32_PLLSRC_HSE)
1389#error "HSE not enabled, required by STM32_PLLI2SSRC"
1390#endif
1391
1392#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
1393#error "HSE not enabled, required by STM32_RTCSEL"
1394#endif
1395
1396#endif /* !STM32_HSE_ENABLED */
1397
1398/*
1399 * LSI related checks.
1400 */
1401#if STM32_LSI_ENABLED
1402#else /* !STM32_LSI_ENABLED */
1403
1404#if HAL_USE_RTC && (STM32_RTCSEL == STM32_RTCSEL_LSI)
1405#error "LSI not enabled, required by STM32_RTCSEL"
1406#endif
1407
1408#endif /* !STM32_LSI_ENABLED */
1409
1410/*
1411 * LSE related checks.
1412 */
1413#if STM32_LSE_ENABLED
1414
1415#if (STM32_LSECLK == 0)
1416#error "LSE frequency not defined"
1417#endif
1418
1419#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
1420#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
1421#endif
1422
1423#else /* !STM32_LSE_ENABLED */
1424
1425#if STM32_RTCSEL == STM32_RTCSEL_LSE
1426#error "LSE not enabled, required by STM32_RTCSEL"
1427#endif
1428
1429#endif /* !STM32_LSE_ENABLED */
1430
1431/**
1432 * @brief Clock frequency feeding PLLs.
1433 */
1434#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
1435#define STM32_PLLSRCCLK STM32_HSECLK
1436#elif STM32_PLLSRC == STM32_PLLSRC_HSI
1437#define STM32_PLLSRCCLK STM32_HSICLK
1438#else
1439#error "invalid STM32_PLLSRC value specified"
1440#endif
1441
1442/**
1443 * @brief STM32_PLLM field.
1444 */
1445#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \
1446 defined(__DOXYGEN__)
1447#define STM32_PLLM (STM32_PLLM_VALUE << 0)
1448#else
1449#error "invalid STM32_PLLM_VALUE value specified"
1450#endif
1451
1452/**
1453 * @brief PLL input clock frequency.
1454 */
1455#define STM32_PLLCLKIN (STM32_PLLSRCCLK / STM32_PLLM_VALUE)
1456
1457/*
1458 * PLLs input frequency range check.
1459 */
1460#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
1461#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
1462#endif
1463
1464/*
1465 * PLL enable check.
1466 */
1467#if (STM32_CLOCK48_REQUIRED && \
1468 STM32_HAS_RCC_CK48MSEL && \
1469 (STM32_CK48MSEL == STM32_CK48MSEL_PLL)) || \
1470 (STM32_SW == STM32_SW_PLL) || \
1471 (STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \
1472 (STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \
1473 defined(__DOXYGEN__)
1474/**
1475 * @brief PLL activation flag.
1476 */
1477#define STM32_ACTIVATE_PLL TRUE
1478#else
1479#define STM32_ACTIVATE_PLL FALSE
1480#endif
1481
1482/**
1483 * @brief STM32_PLLN field.
1484 */
1485#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \
1486 defined(__DOXYGEN__)
1487#define STM32_PLLN (STM32_PLLN_VALUE << 6)
1488#else
1489#error "invalid STM32_PLLN_VALUE value specified"
1490#endif
1491
1492/**
1493 * @brief STM32_PLLP field.
1494 */
1495#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__)
1496#define STM32_PLLP STM32_PLLP_DIV2
1497#elif STM32_PLLP_VALUE == 4
1498#define STM32_PLLP STM32_PLLP_DIV4
1499#elif STM32_PLLP_VALUE == 6
1500#define STM32_PLLP STM32_PLLP_DIV6
1501#elif STM32_PLLP_VALUE == 8
1502#define STM32_PLLP STM32_PLLP_DIV8
1503#else
1504#error "invalid STM32_PLLP_VALUE value specified"
1505#endif
1506
1507/**
1508 * @brief STM32_PLLQ field.
1509 */
1510#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) || \
1511 defined(__DOXYGEN__)
1512#define STM32_PLLQ (STM32_PLLQ_VALUE << 24)
1513#else
1514#error "invalid STM32_PLLQ_VALUE value specified"
1515#endif
1516
1517#if defined(STM32F4XX) || defined(__DOXYGEN__)
1518/**
1519 * @brief STM32_PLLR field.
1520 */
1521#if ((STM32_PLLR_VALUE >= 2) && (STM32_PLLR_VALUE <= 7)) || \
1522 defined(__DOXYGEN__)
1523#define STM32_PLLR (STM32_PLLR_VALUE << 28)
1524#else
1525#error "invalid STM32_PLLR_VALUE value specified"
1526#endif
1527#else /* !defined(STM32F4XX) */
1528#define STM32_PLLR 0
1529#endif /* !defined(STM32F4XX) */
1530
1531/**
1532 * @brief PLL VCO frequency.
1533 */
1534#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
1535
1536/*
1537 * PLL VCO frequency range check.
1538 */
1539#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
1540#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
1541#endif
1542
1543/**
1544 * @brief PLL output clock frequency.
1545 */
1546#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
1547
1548/*
1549 * PLL output frequency range check.
1550 */
1551#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
1552#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
1553#endif
1554
1555/**
1556 * @brief System clock source.
1557 */
1558#if STM32_NO_INIT || defined(__DOXYGEN__)
1559#define STM32_SYSCLK STM32_HSICLK
1560#elif (STM32_SW == STM32_SW_HSI)
1561#define STM32_SYSCLK STM32_HSICLK
1562#elif (STM32_SW == STM32_SW_HSE)
1563#define STM32_SYSCLK STM32_HSECLK
1564#elif (STM32_SW == STM32_SW_PLL)
1565#define STM32_SYSCLK STM32_PLLCLKOUT
1566#else
1567#error "invalid STM32_SW value specified"
1568#endif
1569
1570/* Check on the system clock.*/
1571#if STM32_SYSCLK > STM32_SYSCLK_MAX
1572#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
1573#endif
1574
1575/* Calculating VOS settings, it is different for each sub-platform.*/
1576#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
1577 defined(STM32F446xx) || defined(STM32F469_479xx) || \
1578 defined(__DOXYGEN__)
1579#if STM32_SYSCLK <= 120000000
1580#define STM32_VOS STM32_VOS_SCALE3
1581#define STM32_OVERDRIVE_REQUIRED FALSE
1582#elif STM32_SYSCLK <= 144000000
1583#define STM32_VOS STM32_VOS_SCALE2
1584#define STM32_OVERDRIVE_REQUIRED FALSE
1585#elif STM32_SYSCLK <= 168000000
1586#define STM32_VOS STM32_VOS_SCALE1
1587#define STM32_OVERDRIVE_REQUIRED FALSE
1588#else
1589#define STM32_VOS STM32_VOS_SCALE1
1590#define STM32_OVERDRIVE_REQUIRED TRUE
1591#endif
1592
1593#elif defined(STM32F40_41xxx)
1594#if STM32_SYSCLK <= 144000000
1595#define STM32_VOS STM32_VOS_SCALE2
1596#else
1597#define STM32_VOS STM32_VOS_SCALE1
1598#endif
1599#define STM32_OVERDRIVE_REQUIRED FALSE
1600
1601#elif defined(STM32F401xx)
1602#if STM32_SYSCLK <= 60000000
1603#define STM32_VOS STM32_VOS_SCALE3
1604#else
1605#define STM32_VOS STM32_VOS_SCALE2
1606#endif
1607#define STM32_OVERDRIVE_REQUIRED FALSE
1608
1609#elif defined(STM32F410xx) || defined(STM32F411xx) || \
1610 defined(STM32F412xx)
1611#if STM32_SYSCLK <= 64000000
1612#define STM32_VOS STM32_VOS_SCALE3
1613#elif STM32_SYSCLK <= 84000000
1614#define STM32_VOS STM32_VOS_SCALE2
1615#else
1616#define STM32_VOS STM32_VOS_SCALE1
1617#endif
1618#define STM32_OVERDRIVE_REQUIRED FALSE
1619
1620#else /* STM32F2XX */
1621#define STM32_OVERDRIVE_REQUIRED FALSE
1622#endif
1623
1624/**
1625 * @brief AHB frequency.
1626 */
1627#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
1628#define STM32_HCLK (STM32_SYSCLK / 1)
1629#elif STM32_HPRE == STM32_HPRE_DIV2
1630#define STM32_HCLK (STM32_SYSCLK / 2)
1631#elif STM32_HPRE == STM32_HPRE_DIV4
1632#define STM32_HCLK (STM32_SYSCLK / 4)
1633#elif STM32_HPRE == STM32_HPRE_DIV8
1634#define STM32_HCLK (STM32_SYSCLK / 8)
1635#elif STM32_HPRE == STM32_HPRE_DIV16
1636#define STM32_HCLK (STM32_SYSCLK / 16)
1637#elif STM32_HPRE == STM32_HPRE_DIV64
1638#define STM32_HCLK (STM32_SYSCLK / 64)
1639#elif STM32_HPRE == STM32_HPRE_DIV128
1640#define STM32_HCLK (STM32_SYSCLK / 128)
1641#elif STM32_HPRE == STM32_HPRE_DIV256
1642#define STM32_HCLK (STM32_SYSCLK / 256)
1643#elif STM32_HPRE == STM32_HPRE_DIV512
1644#define STM32_HCLK (STM32_SYSCLK / 512)
1645#else
1646#error "invalid STM32_HPRE value specified"
1647#endif
1648
1649/*
1650 * AHB frequency check.
1651 */
1652#if STM32_HCLK > STM32_SYSCLK_MAX
1653#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
1654#endif
1655
1656/**
1657 * @brief APB1 frequency.
1658 */
1659#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
1660#define STM32_PCLK1 (STM32_HCLK / 1)
1661#elif STM32_PPRE1 == STM32_PPRE1_DIV2
1662#define STM32_PCLK1 (STM32_HCLK / 2)
1663#elif STM32_PPRE1 == STM32_PPRE1_DIV4
1664#define STM32_PCLK1 (STM32_HCLK / 4)
1665#elif STM32_PPRE1 == STM32_PPRE1_DIV8
1666#define STM32_PCLK1 (STM32_HCLK / 8)
1667#elif STM32_PPRE1 == STM32_PPRE1_DIV16
1668#define STM32_PCLK1 (STM32_HCLK / 16)
1669#else
1670#error "invalid STM32_PPRE1 value specified"
1671#endif
1672
1673/*
1674 * APB1 frequency check.
1675 */
1676#if STM32_PCLK1 > STM32_PCLK1_MAX
1677#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
1678#endif
1679
1680/**
1681 * @brief APB2 frequency.
1682 */
1683#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
1684#define STM32_PCLK2 (STM32_HCLK / 1)
1685#elif STM32_PPRE2 == STM32_PPRE2_DIV2
1686#define STM32_PCLK2 (STM32_HCLK / 2)
1687#elif STM32_PPRE2 == STM32_PPRE2_DIV4
1688#define STM32_PCLK2 (STM32_HCLK / 4)
1689#elif STM32_PPRE2 == STM32_PPRE2_DIV8
1690#define STM32_PCLK2 (STM32_HCLK / 8)
1691#elif STM32_PPRE2 == STM32_PPRE2_DIV16
1692#define STM32_PCLK2 (STM32_HCLK / 16)
1693#else
1694#error "invalid STM32_PPRE2 value specified"
1695#endif
1696
1697/*
1698 * APB2 frequency check.
1699 */
1700#if STM32_PCLK2 > STM32_PCLK2_MAX
1701#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
1702#endif
1703
1704/*
1705 * PLLI2S enable check.
1706 */
1707#if (STM32_HAS_RCC_PLLI2S && \
1708 (STM32_CLOCK48_REQUIRED && \
1709 (STM32_HAS_RCC_CK48MSEL && \
1710 STM32_RCC_CK48MSEL_USES_I2S && \
1711 (STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) || \
1712 (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
1713 (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) || \
1714 (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S))) || \
1715 defined(__DOXYGEN__)
1716
1717/**
1718 * @brief PLLI2S activation flag.
1719 */
1720#define STM32_ACTIVATE_PLLI2S TRUE
1721#else
1722#define STM32_ACTIVATE_PLLI2S FALSE
1723#endif
1724
1725/**
1726 * @brief STM32_PLLI2SM field.
1727 */
1728#if ((STM32_PLLI2SM_VALUE >= 2) && (STM32_PLLI2SM_VALUE <= 63)) || \
1729 defined(__DOXYGEN__)
1730#define STM32_PLLI2SM (STM32_PLLI2SM_VALUE << 0)
1731#else
1732#error "invalid STM32_PLLI2SM_VALUE value specified"
1733#endif
1734
1735/**
1736 * @brief STM32_PLLI2SN field.
1737 */
1738#if ((STM32_PLLI2SN_VALUE >= 50) && (STM32_PLLI2SN_VALUE <= 432)) || \
1739 defined(__DOXYGEN__)
1740#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6)
1741#else
1742#error "invalid STM32_PLLI2SN_VALUE value specified"
1743#endif
1744
1745/**
1746 * @brief STM32_PLLI2SP field.
1747 */
1748#if (STM32_PLLI2SP_VALUE == 2) || defined(__DOXYGEN__)
1749#define STM32_PLLI2SP STM32_PLLI2SP_DIV2
1750#elif STM32_PLLI2SP_VALUE == 4
1751#define STM32_PLLI2SP STM32_PLLI2SP_DIV4
1752#elif STM32_PLLI2SP_VALUE == 6
1753#define STM32_PLLI2SP STM32_PLLI2SP_DIV6
1754#elif STM32_PLLI2SP_VALUE == 8
1755#define STM32_PLLI2SP STM32_PLLI2SP_DIV8
1756#else
1757#error "invalid STM32_PLLI2SP_VALUE value specified"
1758#endif
1759
1760/**
1761 * @brief STM32_PLLI2SQ field.
1762 */
1763#if ((STM32_PLLI2SQ_VALUE >= 2) && (STM32_PLLI2SQ_VALUE <= 15)) || \
1764 defined(__DOXYGEN__)
1765#define STM32_PLLI2SQ (STM32_PLLI2SQ_VALUE << 24)
1766#else
1767#error "invalid STM32_PLLI2SQ_VALUE value specified"
1768#endif
1769
1770/**
1771 * @brief STM32_PLLI2SDIVQ field.
1772 */
1773#if ((STM32_PLLI2SDIVQ_VALUE >= 1) && (STM32_PLLI2SDIVQ_VALUE <= 32)) || \
1774 defined(__DOXYGEN__)
1775#define STM32_PLLI2SDIVQ ((STM32_PLLI2SQ_VALUE - 1) << 0)
1776#else
1777#error "invalid STM32_PLLI2SDIVQ_VALUE value specified"
1778#endif
1779
1780/**
1781 * @brief STM32_PLLI2SR field.
1782 */
1783#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \
1784 defined(__DOXYGEN__)
1785#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28)
1786#else
1787#error "invalid STM32_PLLI2SR_VALUE value specified"
1788#endif
1789
1790/**
1791 * @brief PLLI2S input clock frequency.
1792 */
1793#if STM32_HAS_RCC_I2SPLLSRC || defined(__DOXYGEN__)
1794#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) || defined(__DOXYGEN__)
1795#define STM32_PLLI2SCLKIN (STM32_PLLSRCCLK / STM32_PLLI2SM_VALUE)
1796#elif STM32_PLLI2SSRC == STM32_PLLI2SSRC_CKIN
1797#define STM32_PLLI2SCLKIN (STM32_I2SCKIN_VALUE / STM32_PLLI2SM_VALUE)
1798#else
1799#error "invalid STM32_PLLI2SSRC value specified"
1800#endif
1801#else
1802#define STM32_PLLI2SCLKIN (STM32_PLLSRCCLK / STM32_PLLM_VALUE)
1803#endif
1804
1805/**
1806 * @brief PLLI2S VCO frequency.
1807 */
1808#define STM32_PLLI2SVCO (STM32_PLLI2SCLKIN * STM32_PLLI2SN_VALUE)
1809
1810/*
1811 * PLLI2S VCO frequency range check.
1812 */
1813#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \
1814 (STM32_PLLI2SVCO > STM32_PLLVCO_MAX)
1815#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
1816#endif
1817
1818/**
1819 * @brief PLLI2S P output clock frequency.
1820 */
1821#define STM32_PLLI2S_P_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SP_VALUE)
1822
1823/**
1824 * @brief PLLI2S Q output clock frequency.
1825 */
1826#define STM32_PLLI2S_Q_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SQ_VALUE)
1827
1828/**
1829 * @brief PLLI2S R output clock frequency.
1830 */
1831#define STM32_PLLI2S_R_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)
1832
1833/*
1834 * PLLSAI enable check.
1835 */
1836#if (STM32_HAS_RCC_PLLSAI && \
1837 (STM32_CLOCK48_REQUIRED && \
1838 (STM32_HAS_RCC_CK48MSEL && \
1839 !STM32_RCC_CK48MSEL_USES_I2S && \
1840 (STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) || \
1841 (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
1842 (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \
1843 (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI))) || \
1844 (STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) || \
1845 defined(__DOXYGEN__)
1846/**
1847 * @brief PLLSAI activation flag.
1848 */
1849#define STM32_ACTIVATE_PLLSAI TRUE
1850#else
1851#define STM32_ACTIVATE_PLLSAI FALSE
1852#endif
1853
1854/**
1855 * @brief STM32_PLLSAIM field.
1856 */
1857#if ((STM32_PLLSAIM_VALUE >= 2) && (STM32_PLLSAIM_VALUE <= 63)) || \
1858 defined(__DOXYGEN__)
1859#define STM32_PLLSAIM (STM32_PLLSAIM_VALUE << 0)
1860#else
1861#error "invalid STM32_PLLSAIM_VALUE value specified"
1862#endif
1863
1864/**
1865 * @brief STM32_PLLSAIN field.
1866 */
1867#if ((STM32_PLLSAIN_VALUE >= 49) && (STM32_PLLSAIN_VALUE <= 432)) || \
1868 defined(__DOXYGEN__)
1869#define STM32_PLLSAIN (STM32_PLLSAIN_VALUE << 6)
1870#else
1871#error "invalid STM32_PLLSAIN_VALUE value specified"
1872#endif
1873
1874/**
1875 * @brief STM32_PLLSAIQ field.
1876 */
1877#if ((STM32_PLLSAIQ_VALUE >= 2) && (STM32_PLLSAIQ_VALUE <= 15)) || \
1878 defined(__DOXYGEN__)
1879#define STM32_PLLSAIQ (STM32_PLLSAIQ_VALUE << 24)
1880#else
1881#error "invalid STM32_PLLSAIQ_VALUE value specified"
1882#endif
1883
1884/**
1885 * @brief STM32_PLLSAIDIVQ_VALUE field.
1886 */
1887#if ((STM32_PLLSAIDIVQ_VALUE >= 1) && (STM32_PLLSAIDIVQ_VALUE <= 32)) || \
1888 defined(__DOXYGEN__)
1889#define STM32_PLLSAIDIVQ ((STM32_PLLSAIDIVQ_VALUE - 1) << 8)
1890#else
1891#error "invalid STM32_PLLSAIDIVQ_VALUE value specified"
1892#endif
1893
1894/**
1895 * @brief STM32_PLLSAIR field.
1896 */
1897#if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) || \
1898 defined(__DOXYGEN__)
1899#define STM32_PLLSAIR (STM32_PLLSAIR_VALUE << 28)
1900#else
1901#error "invalid STM32_PLLSAIR_VALUE value specified"
1902#endif
1903
1904/**
1905 * @brief STM32_PLLSAIP field.
1906 */
1907
1908#if (STM32_PLLSAIP_VALUE == 2) || defined(__DOXYGEN__)
1909#define STM32_PLLSAIP STM32_PLLSAIP_DIV2
1910
1911#elif STM32_PLLSAIP_VALUE == 4
1912#define STM32_PLLSAIP STM32_PLLSAIP_DIV4
1913
1914#elif STM32_PLLSAIP_VALUE == 6
1915#define STM32_PLLSAIP STM32_PLLSAIP_DIV6
1916
1917#elif STM32_PLLSAIP_VALUE == 8
1918#define STM32_PLLSAIP STM32_PLLSAIP_DIV8
1919
1920#else
1921#error "invalid STM32_PLLSAIP_VALUE value specified"
1922#endif
1923
1924/**
1925 * @brief PLLSAI input clock frequency.
1926 */
1927#if defined(STM32F446xx)
1928#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
1929#define STM32_PLLSAICLKIN (STM32_HSECLK / STM32_PLLSAIM_VALUE)
1930#elif STM32_PLLSRC == STM32_PLLSRC_HSI
1931#define STM32_PLLSAICLKIN (STM32_HSICLK / STM32_PLLSAIM_VALUE)
1932#else
1933#error "invalid STM32_PLLSRC value specified"
1934#endif
1935#else /* !defined(STM32F446xx) */
1936#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
1937#define STM32_PLLSAICLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
1938#elif STM32_PLLSRC == STM32_PLLSRC_HSI
1939#define STM32_PLLSAICLKIN (STM32_HSICLK / STM32_PLLM_VALUE)
1940#else
1941#error "invalid STM32_PLLSRC value specified"
1942#endif
1943#endif /* defined(STM32F446xx) */
1944
1945/**
1946 * @brief PLLSAI VCO frequency.
1947 */
1948#define STM32_PLLSAIVCO (STM32_PLLSAICLKIN * STM32_PLLSAIN_VALUE)
1949
1950/*
1951 * PLLSAI VCO frequency range check.
1952 */
1953#if (STM32_PLLSAIVCO < STM32_PLLVCO_MIN) || \
1954 (STM32_PLLSAIVCO > STM32_PLLVCO_MAX)
1955#error "STM32_PLLSAIVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
1956#endif
1957
1958/**
1959 * @brief PLLSAI P output clock frequency.
1960 */
1961#define STM32_PLLSAI_P_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)
1962
1963/**
1964 * @brief PLLSAI Q output clock frequency.
1965 */
1966#define STM32_PLLSAI_Q_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE)
1967
1968/**
1969 * @brief PLLSAI R output clock frequency.
1970 */
1971#define STM32_PLLSAI_R_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIR_VALUE)
1972
1973/*===========================================================================*/
1974/* Driver data structures and types. */
1975/*===========================================================================*/
1976
1977/*===========================================================================*/
1978/* Driver macros. */
1979/*===========================================================================*/
1980
1981/*===========================================================================*/
1982/* External declarations. */
1983/*===========================================================================*/
1984
1985#ifdef __cplusplus
1986extern "C" {
1987#endif
1988 void hal_lld_init(void);
1989 void stm32_clock_init(void);
1990#ifdef __cplusplus
1991}
1992#endif
1993
1994#endif /* HAL_LLD_TYPE1_H */
1995
1996/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h b/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h
new file mode 100644
index 000000000..b90a427f5
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h
@@ -0,0 +1,1212 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F4xx/hal_lld_type2.h
19 * @brief STM32F4xx/STM32F2xx HAL subsystem low level driver header.
20 * @pre This module requires the following macros to be defined in the
21 * @p board.h file:
22 * - STM32_LSECLK.
23 * - STM32_LSE_BYPASS (optionally).
24 * - STM32_HSECLK.
25 * - STM32_HSE_BYPASS (optionally).
26 * - STM32_VDD (as hundredths of Volt).
27 * .
28 * One of the following macros must also be defined:
29 * - STM32F413xx for High-performance STM32F4 devices of Access line.
30 * .
31 *
32 * @addtogroup HAL
33 * @{
34 */
35
36#ifndef HAL_LLD_TYPE2_H
37#define HAL_LLD_TYPE2_H
38
39/*===========================================================================*/
40/* Driver constants. */
41/*===========================================================================*/
42
43/**
44 * @brief Defines the support for realtime counters in the HAL.
45 */
46#define HAL_IMPLEMENTS_COUNTERS TRUE
47
48/**
49 * @name Platform identification macros
50 * @{
51 */
52#if defined(STM32F413xx)
53#define PLATFORM_NAME "STM32F413 High Performance with DSP and FPU"
54
55#else
56#error "STM32F2xx/F4xx device not specified"
57#endif
58/** @} */
59
60/**
61 * @name Absolute Maximum Ratings
62 * @{
63 */
64
65#if defined(STM32F413xx) || defined(__DOXYGEN__)
66/**
67 * @brief Absolute maximum system clock.
68 */
69#define STM32_SYSCLK_MAX 100000000
70
71/**
72 * @brief Maximum HSE clock frequency.
73 */
74#define STM32_HSECLK_MAX 26000000
75
76/**
77 * @brief Maximum HSE clock frequency using an external source.
78 */
79#define STM32_HSECLK_BYP_MAX 50000000
80
81/**
82 * @brief Minimum HSE clock frequency.
83 */
84#define STM32_HSECLK_MIN 4000000
85
86/**
87 * @brief Minimum HSE clock frequency using an external source.
88 */
89#define STM32_HSECLK_BYP_MIN 1000000
90
91/**
92 * @brief Maximum LSE clock frequency.
93 */
94#define STM32_LSECLK_MAX 32768
95
96/**
97 * @brief Maximum LSE clock frequency using an external source.
98 */
99#define STM32_LSECLK_BYP_MAX 1000000
100
101/**
102 * @brief Minimum LSE clock frequency.
103 */
104#define STM32_LSECLK_MIN 32768
105
106/**
107 * @brief Maximum PLLs input clock frequency.
108 */
109#define STM32_PLLIN_MAX 2100000
110
111/**
112 * @brief Minimum PLLs input clock frequency.
113 */
114#define STM32_PLLIN_MIN 950000
115
116/**
117 * @brief Maximum PLLs VCO clock frequency.
118 */
119#define STM32_PLLVCO_MAX 432000000
120
121/**
122 * @brief Minimum PLLs VCO clock frequency.
123 */
124#define STM32_PLLVCO_MIN 100000000
125
126/**
127 * @brief Maximum PLL output clock frequency.
128 */
129#define STM32_PLLOUT_MAX 100000000
130
131/**
132 * @brief Minimum PLL output clock frequency.
133 */
134#define STM32_PLLOUT_MIN 24000000
135
136/**
137 * @brief Maximum APB1 clock frequency.
138 */
139#define STM32_PCLK1_MAX 50000000
140
141/**
142 * @brief Maximum APB2 clock frequency.
143 */
144#define STM32_PCLK2_MAX 100000000
145
146/**
147 * @brief Maximum SPI/I2S clock frequency.
148 */
149#define STM32_SPII2S_MAX 50000000
150#endif
151/** @} */
152
153/**
154 * @name Internal clock sources
155 * @{
156 */
157#define STM32_HSICLK 16000000 /**< High speed internal clock. */
158#define STM32_LSICLK 32000 /**< Low speed internal clock. */
159/** @} */
160
161/**
162 * @name PWR_CR register bits definitions
163 * @{
164 */
165#define STM32_VOS_SCALE3 0x00004000
166#define STM32_VOS_SCALE2 0x00008000
167#define STM32_VOS_SCALE1 0x0000C000
168#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
169#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
170#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
171#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
172#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
173#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
174#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
175#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
176#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
177/** @} */
178
179/**
180 * @name RCC_PLLCFGR register bits definitions
181 * @{
182 */
183#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */
184#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */
185#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */
186#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */
187#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */
188
189#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */
190#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */
191/** @} */
192
193/**
194 * @name RCC_CFGR register bits definitions
195 * @{
196 */
197#define STM32_SW_MASK (3 << 0) /**< SW mask. */
198#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
199#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
200#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
201
202#define STM32_HPRE_MASK (15 << 4) /**< HPRE mask. */
203#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
204#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
205#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
206#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
207#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
208#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
209#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
210#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
211#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
212
213#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */
214#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */
215#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */
216#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */
217#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */
218#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */
219
220#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */
221#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */
222#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */
223#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */
224#define STM32_PPRE2_DIV8 (6 << 13) /**< HCLK divided by 8. */
225#define STM32_PPRE2_DIV16 (7 << 13) /**< HCLK divided by 16. */
226
227#define STM32_RTCPRE_MASK (31 << 16) /**< RTCPRE mask. */
228
229#define STM32_MCO1SEL_MASK (3 << 21) /**< MCO1 mask. */
230#define STM32_MCO1SEL_HSI (0 << 21) /**< HSI clock on MCO1 pin. */
231#define STM32_MCO1SEL_LSE (1 << 21) /**< LSE clock on MCO1 pin. */
232#define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */
233#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */
234
235#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */
236#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */
237#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */
238#define STM32_MCO1PRE_DIV3 (5 << 24) /**< MCO1 divided by 3. */
239#define STM32_MCO1PRE_DIV4 (6 << 24) /**< MCO1 divided by 4. */
240#define STM32_MCO1PRE_DIV5 (7 << 24) /**< MCO1 divided by 5. */
241
242#define STM32_MCO2PRE_MASK (7 << 27) /**< MCO2PRE mask. */
243#define STM32_MCO2PRE_DIV1 (0 << 27) /**< MCO2 divided by 1. */
244#define STM32_MCO2PRE_DIV2 (4 << 27) /**< MCO2 divided by 2. */
245#define STM32_MCO2PRE_DIV3 (5 << 27) /**< MCO2 divided by 3. */
246#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */
247#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */
248
249#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */
250#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */
251#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */
252#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */
253#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */
254
255/**
256 * @name RCC_PLLI2SCFGR register bits definitions
257 * @{
258 */
259#define STM32_PLLI2SM_MASK (31 << 0) /**< PLLI2SM mask. */
260#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */
261#define STM32_PLLI2SSRC_MASK (1 << 22) /**< PLLI2SSRC mask. */
262#define STM32_PLLI2SSRC_PLLSRC (0 << 22) /**< PLLI2SSRC is selected PLL
263 source. */
264#define STM32_PLLI2SSRC_CKIN (1 << 22) /**< PLLI2SSRC is I2S_CKIN. */
265#define STM32_PLLI2SQ_MASK (15 << 24) /**< PLLI2SQ mask. */
266#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
267/** @} */
268
269/**
270 * @name RCC_BDCR register bits definitions
271 * @{
272 */
273#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */
274#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */
275#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */
276#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */
277#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */
278/** @} */
279
280/**
281 * @name RCC_DCKCFGR register bits definitions
282 * @{
283 */
284#define STM32_PLLI2SDIVR_MASK (31 << 0) /**< PLLI2SDIVR mask. */
285#define STM32_PLLDIVR_MASK (31 << 8) /**< PLLDIVR mask. */
286
287#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */
288#define STM32_SAI1SEL_PLLSAI (0 << 20) /**< SAI1 source is PLLSAI. */
289#define STM32_SAI1SEL_PLLI2S (1 << 20) /**< SAI1 source is PLLI2S. */
290#define STM32_SAI1SEL_PLLR (2 << 20) /**< SAI1 source is PLLR. */
291#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
292
293#define STM32_SAI2SEL_MASK (3 << 22) /**< SAI2SEL mask. */
294#define STM32_SAI2SEL_PLLSAI (0 << 22) /**< SAI2 source is PLLSAI. */
295#define STM32_SAI2SEL_PLLI2S (1 << 22) /**< SAI2 source is PLLI2S. */
296#define STM32_SAI2SEL_PLLR (2 << 22) /**< SAI2 source is PLLR. */
297#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
298
299#define STM32_TIMPRE_MASK (1 << 24) /**< TIMPRE mask. */
300#define STM32_TIMPRE_PCLK (0 << 24) /**< TIM clocks from PCLKx. */
301#define STM32_TIMPRE_HCLK (1 << 24) /**< TIM clocks from HCLK. */
302
303#define STM32_I2S1SEL_MASK (3 << 25) /**< I2S1SEL mask. */
304#define STM32_I2S1SEL_PLLR (0 << 25) /**< I2S1 source is PLLR. */
305#define STM32_I2S1SEL_AFIN (1 << 25) /**< I2S1 source is AF Input. */
306#define STM32_I2S1SEL_MCO1 (2 << 25) /**< I2S1 source is MCO1. */
307#define STM32_I2S1SEL_OFF 0xFFFFFFFFU /**< I2S1 clock is not required.*/
308
309#define STM32_I2S2SEL_MASK (3 << 27) /**< I2S2SEL mask. */
310#define STM32_I2S2SEL_PLLR (0 << 27) /**< I2S2 source is PLLR. */
311#define STM32_I2S2SEL_AFIN (1 << 27) /**< I2S2 source is AF Input. */
312#define STM32_I2S2SEL_MCO1 (2 << 27) /**< I2S2 source is MCO1. */
313#define STM32_I2S2SEL_OFF 0xFFFFFFFFU /**< I2S2 clock is not required.*/
314/** @} */
315
316/**
317 * @name RCC_DCKCFGR2 register bits definitions
318 * @{
319 */
320#define STM32_I2CFMP1SEL_MASK (3 << 22) /**< I2CFMP1SEL mask. */
321#define STM32_I2CFMP1SEL_PCLK1 (0 << 22) /**< I2C1 source is APB/PCLK1. */
322#define STM32_I2CFMP1SEL_SYSCLK (1 << 22) /**< I2C1 source is SYSCLK. */
323#define STM32_I2CFMP1SEL_HSI (2 << 22) /**< I2C1 source is HSI. */
324
325#define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */
326#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
327#define STM32_CK48MSEL_PLLI2S (1 << 27) /**< PLL48CLK source is PLLI2S. */
328#define STM32_CK48MSEL_PLLALT (1 << 27) /**< Alias. */
329
330#define STM32_SDIOSEL_MASK (1 << 28) /**< SDIOSEL mask. */
331#define STM32_SDIOSEL_PLL48CLK (0 << 28) /**< SDIO source is PLL48CLK. */
332#define STM32_SDIOSEL_SYSCLK (1 << 28) /**< SDIO source is SYSCLK. */
333
334#define STM32_LPTIM1SEL_MASK (3 << 30) /**< LPTIM1 mask. */
335#define STM32_LPTIM1SEL_APB (0 << 30) /**< LPTIM1 source is APB. */
336#define STM32_LPTIM1SEL_HSI (1 << 30) /**< LPTIM1 source is HSI. */
337#define STM32_LPTIM1SEL_LSI (2 << 30) /**< LPTIM1 source is LSI. */
338#define STM32_LPTIM1SEL_LSE (3 << 30) /**< LPTIM1 source is LSE. */
339/** @} */
340
341/*===========================================================================*/
342/* Driver pre-compile time settings. */
343/*===========================================================================*/
344
345/**
346 * @name Configuration options
347 * @{
348 */
349/**
350 * @brief Disables the PWR/RCC initialization in the HAL.
351 */
352#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
353#define STM32_NO_INIT FALSE
354#endif
355
356/**
357 * @brief Enables or disables the programmable voltage detector.
358 */
359#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
360#define STM32_PVD_ENABLE FALSE
361#endif
362
363/**
364 * @brief Sets voltage level for programmable voltage detector.
365 */
366#if !defined(STM32_PLS) || defined(__DOXYGEN__)
367#define STM32_PLS STM32_PLS_LEV0
368#endif
369
370/**
371 * @brief Enables the backup RAM regulator.
372 */
373#if !defined(STM32_BKPRAM_ENABLE) || defined(__DOXYGEN__)
374#define STM32_BKPRAM_ENABLE FALSE
375#endif
376
377/**
378 * @brief Enables or disables the HSI clock source.
379 */
380#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
381#define STM32_HSI_ENABLED TRUE
382#endif
383
384/**
385 * @brief Enables or disables the LSI clock source.
386 */
387#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
388#define STM32_LSI_ENABLED FALSE
389#endif
390
391/**
392 * @brief Enables or disables the HSE clock source.
393 */
394#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
395#define STM32_HSE_ENABLED TRUE
396#endif
397
398/**
399 * @brief Enables or disables the LSE clock source.
400 */
401#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
402#define STM32_LSE_ENABLED FALSE
403#endif
404
405/**
406 * @brief USB/SDIO clock setting.
407 */
408#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__)
409#define STM32_CLOCK48_REQUIRED TRUE
410#endif
411
412/**
413 * @brief Main clock source selection.
414 * @note If the selected clock source is not the PLL then the PLL is not
415 * initialized and started.
416 * @note The default value is calculated for a 168MHz system clock from
417 * an external 8MHz HSE clock.
418 */
419#if !defined(STM32_SW) || defined(__DOXYGEN__)
420#define STM32_SW STM32_SW_PLL
421#endif
422
423/**
424 * @brief Clock source for the PLLs.
425 * @note This setting has only effect if the PLL is selected as the
426 * system clock source.
427 * @note The default value is calculated for a 168MHz system clock from
428 * an external 8MHz HSE clock.
429 */
430#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
431#define STM32_PLLSRC STM32_PLLSRC_HSE
432#endif
433
434/**
435 * @brief PLLM divider value.
436 * @note The allowed values are 2..63.
437 * @note The default value is calculated for a 168MHz system clock from
438 * an external 8MHz HSE clock.
439 */
440#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
441#define STM32_PLLM_VALUE 8
442#endif
443
444/**
445 * @brief PLLN multiplier value.
446 * @note The allowed values are 192..432.
447 * @note The default value is calculated for a 96MHz system clock from
448 * an external 8MHz HSE clock.
449 */
450#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
451#define STM32_PLLN_VALUE 384
452#endif
453
454/**
455 * @brief PLLP divider value.
456 * @note The allowed values are 2, 4, 6, 8.
457 * @note The default value is calculated for a 96MHz system clock from
458 * an external 8MHz HSE clock.
459 */
460#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
461#define STM32_PLLP_VALUE 4
462#endif
463
464/**
465 * @brief PLLQ multiplier value.
466 * @note The allowed values are 2..15.
467 * @note The default value is calculated for a 96MHz system clock from
468 * an external 8MHz HSE clock.
469 */
470#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
471#define STM32_PLLQ_VALUE 8
472#endif
473
474/**
475 * @brief AHB prescaler value.
476 */
477#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
478#define STM32_HPRE STM32_HPRE_DIV1
479#endif
480
481/**
482 * @brief APB1 prescaler value.
483 */
484#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
485#define STM32_PPRE1 STM32_PPRE1_DIV4
486#endif
487
488/**
489 * @brief APB2 prescaler value.
490 */
491#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
492#define STM32_PPRE2 STM32_PPRE2_DIV2
493#endif
494
495/**
496 * @brief I2S clock source (pre-PLL).
497 */
498#if !defined(STM32_PLLI2SSRC) || defined(__DOXYGEN__)
499#define STM32_PLLI2SSRC STM32_PLLI2SSRC_PLLSRC
500#endif
501
502/**
503 * @brief I2S external clock value, zero if not present.
504 */
505#if !defined(STM32_I2SCKIN_VALUE) || defined(__DOXYGEN__)
506#define STM32_I2SCKIN_VALUE 0
507#endif
508
509/**
510 * @brief PLLI2SM divider value.
511 * @note The allowed values are 2..63.
512 * @note The default value is calculated for a 96MHz I2S clock
513 * output from an external 8MHz HSE clock.
514 */
515#if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__)
516#define STM32_PLLI2SM_VALUE 8
517#endif
518
519/**
520 * @brief PLLI2SN multiplier value.
521 * @note The allowed values are 192..432, except for
522 * STM32F446 where values are 50...432.
523 * @note The default value is calculated for a 96MHz I2S clock
524 * output from an external 8MHz HSE clock.
525 */
526#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
527#define STM32_PLLI2SN_VALUE 192
528#endif
529
530/**
531 * @brief PLLI2SR divider value.
532 * @note The allowed values are 2..7.
533 * @note The default value is calculated for a 96MHz I2S clock
534 * output from an external 8MHz HSE clock.
535 */
536#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
537#define STM32_PLLI2SR_VALUE 4
538#endif
539
540/**
541 * @brief PLLI2SQ divider value.
542 * @note The allowed values are 2..15.
543 */
544#if !defined(STM32_PLLI2SQ_VALUE) || defined(__DOXYGEN__)
545#define STM32_PLLI2SQ_VALUE 4
546#endif
547
548/**
549 * @brief PLLI2SDIVR divider value (SAI clock divider).
550 * @note The allowed values are 1..32.
551 */
552#if !defined(STM32_PLLI2SDIVR_VALUE) || defined(__DOXYGEN__)
553#define STM32_PLLI2SDIVR_VALUE 1
554#endif
555
556/**
557 * @brief PLLDIVR divider value (SAI clock divider).
558 * @note The allowed values are 1..32.
559 */
560#if !defined(STM32_PLLDIVR_VALUE) || defined(__DOXYGEN__)
561#define STM32_PLLDIVR_VALUE 1
562#endif
563
564/**
565 * @brief SAI1SEL value (SAI1 clock source).
566 */
567#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
568#define STM32_SAI1SEL STM32_SAI1SEL_OFF
569#endif
570
571/**
572 * @brief SAI2SEL value (SAI2 clock source).
573 */
574#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__)
575#define STM32_SAI2SEL STM32_SAI2SEL_OFF
576#endif
577
578/**
579 * @brief TIM prescaler clock source.
580 */
581#if !defined(STM32_TIMPRE) || defined(__DOXYGEN__)
582#define STM32_TIMPRE STM32_TIMPRE_PCLK
583#endif
584
585/**
586 * @brief PLL48CLK clock source.
587 */
588#if !defined(STM32_CK48MSEL) || defined(__DOXYGEN__)
589#define STM32_CK48MSEL STM32_CK48MSEL_PLL
590#endif
591
592/**
593 * @brief RTC clock source.
594 */
595#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
596#define STM32_RTCSEL STM32_RTCSEL_LSE
597#endif
598
599/**
600 * @brief RTC HSE prescaler value.
601 */
602#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__)
603#define STM32_RTCPRE_VALUE 8
604#endif
605
606/**
607 * @brief MCO1 clock source value.
608 * @note The default value outputs HSI clock on MCO1 pin.
609 */
610#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__)
611#define STM32_MCO1SEL STM32_MCO1SEL_HSI
612#endif
613
614/**
615 * @brief MCO1 prescaler value.
616 * @note The default value outputs HSI clock on MCO1 pin.
617 */
618#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)
619#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
620#endif
621
622/**
623 * @brief MCO2 clock source value.
624 * @note The default value outputs SYSCLK / 5 on MCO2 pin.
625 */
626#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
627#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
628#endif
629
630/**
631 * @brief MCO2 prescaler value.
632 * @note The default value outputs SYSCLK / 5 on MCO2 pin.
633 */
634#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
635#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
636#endif
637/** @} */
638
639/*===========================================================================*/
640/* Derived constants and error checks. */
641/*===========================================================================*/
642
643/*
644 * Configuration-related checks.
645 */
646#if !defined(STM32F4xx_MCUCONF)
647#error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined"
648#endif
649
650#if defined(STM32F413xx) && !defined(STM32F413_MCUCONF)
651#error "Using a wrong mcuconf.h file, STM32F413_MCUCONF not defined"
652#endif
653
654/**
655 * @name Maximum frequency thresholds, wait states and
656 * parallelism for flash access.
657 * @{
658 */
659#if defined(STM32F413xx)
660#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
661#define STM32_0WS_THRESHOLD 25000000
662#define STM32_1WS_THRESHOLD 50000000
663#define STM32_2WS_THRESHOLD 75000000
664#define STM32_3WS_THRESHOLD 100000000
665#define STM32_4WS_THRESHOLD 0
666#define STM32_5WS_THRESHOLD 0
667#define STM32_6WS_THRESHOLD 0
668#define STM32_7WS_THRESHOLD 0
669#define STM32_8WS_THRESHOLD 0
670#define STM32_FLASH_PSIZE 2
671#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
672#define STM32_0WS_THRESHOLD 20000000
673#define STM32_1WS_THRESHOLD 40000000
674#define STM32_2WS_THRESHOLD 60000000
675#define STM32_3WS_THRESHOLD 80000000
676#define STM32_4WS_THRESHOLD 100000000
677#define STM32_5WS_THRESHOLD 0
678#define STM32_6WS_THRESHOLD 0
679#define STM32_7WS_THRESHOLD 0
680#define STM32_8WS_THRESHOLD 0
681#define STM32_FLASH_PSIZE 1
682#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
683#define STM32_0WS_THRESHOLD 18000000
684#define STM32_1WS_THRESHOLD 36000000
685#define STM32_2WS_THRESHOLD 54000000
686#define STM32_3WS_THRESHOLD 72000000
687#define STM32_4WS_THRESHOLD 90000000
688#define STM32_5WS_THRESHOLD 100000000
689#define STM32_6WS_THRESHOLD 0
690#define STM32_7WS_THRESHOLD 0
691#define STM32_8WS_THRESHOLD 0
692#define STM32_FLASH_PSIZE 1
693#elif (STM32_VDD >= 170) && (STM32_VDD < 210)
694#define STM32_0WS_THRESHOLD 16000000
695#define STM32_1WS_THRESHOLD 32000000
696#define STM32_2WS_THRESHOLD 48000000
697#define STM32_3WS_THRESHOLD 64000000
698#define STM32_4WS_THRESHOLD 80000000
699#define STM32_5WS_THRESHOLD 96000000
700#define STM32_6WS_THRESHOLD 100000000
701#define STM32_7WS_THRESHOLD 0
702#define STM32_8WS_THRESHOLD 0
703#define STM32_FLASH_PSIZE 0
704#else
705#error "invalid VDD voltage specified"
706#endif
707#define FLASH_SR_OPERR FLASH_SR_SOP
708#endif /* defined(STM32F413xx) */
709/** @} */
710
711/*
712 * HSI related checks.
713 */
714#if STM32_HSI_ENABLED
715#else /* !STM32_HSI_ENABLED */
716
717#if STM32_SW == STM32_SW_HSI
718#error "HSI not enabled, required by STM32_SW"
719#endif
720
721#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
722#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
723#endif
724
725#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || \
726 ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \
727 (STM32_PLLSRC == STM32_PLLSRC_HSI))
728#error "HSI not enabled, required by STM32_MCO1SEL"
729#endif
730
731#if (STM32_MCO2SEL == STM32_MCO2SEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
732#error "HSI not enabled, required by STM32_MCO2SEL"
733#endif
734
735#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) && \
736 (STM32_PLLSRC == STM32_PLLSRC_HSI)
737#error "HSI not enabled, required by STM32_I2SSRC"
738#endif
739
740#if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \
741 (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S)) && \
742 (STM32_PLLSRC == STM32_PLLSRC_HSI)
743#error "HSI not enabled, required by STM32_SAI1SEL"
744#endif
745
746#if ((STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI) || \
747 (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S)) && \
748 (STM32_PLLSRC == STM32_PLLSRC_HSI)
749#error "HSI not enabled, required by STM32_SAI2SEL"
750#endif
751#endif /* !STM32_HSI_ENABLED */
752
753/*
754 * HSE related checks.
755 */
756#if STM32_HSE_ENABLED
757
758#if STM32_HSECLK == 0
759#error "HSE frequency not defined"
760#else /* STM32_HSECLK != 0 */
761#if defined(STM32_HSE_BYPASS)
762#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
763#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_BYP_MAX)"
764#endif
765#else /* !defined(STM32_HSE_BYPASS) */
766#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
767#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
768#endif
769#endif /* !defined(STM32_HSE_BYPASS) */
770#endif /* STM32_HSECLK != 0 */
771#else /* !STM32_HSE_ENABLED */
772
773#if STM32_SW == STM32_SW_HSE
774#error "HSE not enabled, required by STM32_SW"
775#endif
776
777#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
778#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
779#endif
780
781#if (STM32_MCO1SEL == STM32_MCO1SEL_HSE) || \
782 ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \
783 (STM32_PLLSRC == STM32_PLLSRC_HSE))
784#error "HSE not enabled, required by STM32_MCO1SEL"
785#endif
786
787#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || \
788 ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \
789 (STM32_PLLSRC == STM32_PLLSRC_HSE))
790#error "HSE not enabled, required by STM32_MCO2SEL"
791#endif
792
793#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) && \
794 (STM32_PLLSRC == STM32_PLLSRC_HSE)
795#error "HSE not enabled, required by STM32_PLLI2SSRC"
796#endif
797
798#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
799#error "HSE not enabled, required by STM32_RTCSEL"
800#endif
801
802#endif /* !STM32_HSE_ENABLED */
803
804/*
805 * LSI related checks.
806 */
807#if STM32_LSI_ENABLED
808#else /* !STM32_LSI_ENABLED */
809
810#if HAL_USE_RTC && (STM32_RTCSEL == STM32_RTCSEL_LSI)
811#error "LSI not enabled, required by STM32_RTCSEL"
812#endif
813
814#endif /* !STM32_LSI_ENABLED */
815
816/*
817 * LSE related checks.
818 */
819#if STM32_LSE_ENABLED
820
821#if (STM32_LSECLK == 0)
822#error "LSE frequency not defined"
823#endif
824
825#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
826#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
827#endif
828
829#else /* !STM32_LSE_ENABLED */
830
831#if STM32_RTCSEL == STM32_RTCSEL_LSE
832#error "LSE not enabled, required by STM32_RTCSEL"
833#endif
834
835#endif /* !STM32_LSE_ENABLED */
836
837/**
838 * @brief Clock frequency feeding PLLs.
839 */
840#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
841#define STM32_PLLSRCCLK STM32_HSECLK
842#elif STM32_PLLSRC == STM32_PLLSRC_HSI
843#define STM32_PLLSRCCLK STM32_HSICLK
844#else
845#error "invalid STM32_PLLSRC value specified"
846#endif
847
848/**
849 * @brief STM32_PLLM field.
850 */
851#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \
852 defined(__DOXYGEN__)
853#define STM32_PLLM (STM32_PLLM_VALUE << 0)
854#else
855#error "invalid STM32_PLLM_VALUE value specified"
856#endif
857
858/**
859 * @brief PLL input clock frequency.
860 */
861#define STM32_PLLCLKIN (STM32_PLLSRCCLK / STM32_PLLM_VALUE)
862
863/*
864 * PLLs input frequency range check.
865 */
866#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
867#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
868#endif
869
870/*
871 * PLL enable check.
872 */
873#if (STM32_CLOCK48_REQUIRED && \
874 STM32_HAS_RCC_CK48MSEL && \
875 (STM32_CK48MSEL == STM32_CK48MSEL_PLL)) || \
876 (STM32_SW == STM32_SW_PLL) || \
877 (STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \
878 (STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \
879 defined(__DOXYGEN__)
880/**
881 * @brief PLL activation flag.
882 */
883#define STM32_ACTIVATE_PLL TRUE
884#else
885#define STM32_ACTIVATE_PLL FALSE
886#endif
887
888/**
889 * @brief STM32_PLLN field.
890 */
891#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \
892 defined(__DOXYGEN__)
893#define STM32_PLLN (STM32_PLLN_VALUE << 6)
894#else
895#error "invalid STM32_PLLN_VALUE value specified"
896#endif
897
898/**
899 * @brief STM32_PLLP field.
900 */
901#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__)
902#define STM32_PLLP STM32_PLLP_DIV2
903#elif STM32_PLLP_VALUE == 4
904#define STM32_PLLP STM32_PLLP_DIV4
905#elif STM32_PLLP_VALUE == 6
906#define STM32_PLLP STM32_PLLP_DIV6
907#elif STM32_PLLP_VALUE == 8
908#define STM32_PLLP STM32_PLLP_DIV8
909#else
910#error "invalid STM32_PLLP_VALUE value specified"
911#endif
912
913/**
914 * @brief STM32_PLLQ field.
915 */
916#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) || \
917 defined(__DOXYGEN__)
918#define STM32_PLLQ (STM32_PLLQ_VALUE << 24)
919#else
920#error "invalid STM32_PLLQ_VALUE value specified"
921#endif
922
923/**
924 * @brief STM32_PLLDIVR_VALUE field.
925 */
926#if ((STM32_PLLDIVR_VALUE >= 1) && (STM32_PLLDIVR_VALUE <= 32)) || \
927 defined(__DOXYGEN__)
928#define STM32_PLLDIVR ((STM32_PLLDIVR_VALUE - 1) << 8)
929#else
930#error "invalid STM32_PLLDIVR_VALUE value specified"
931#endif
932
933/**
934 * @brief PLL VCO frequency.
935 */
936#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
937
938/*
939 * PLL VCO frequency range check.
940 */
941#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
942#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
943#endif
944
945/**
946 * @brief PLL output clock frequency.
947 */
948#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
949
950/*
951 * PLL output frequency range check.
952 */
953#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
954#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
955#endif
956
957/**
958 * @brief System clock source.
959 */
960#if STM32_NO_INIT || defined(__DOXYGEN__)
961#define STM32_SYSCLK STM32_HSICLK
962#elif (STM32_SW == STM32_SW_HSI)
963#define STM32_SYSCLK STM32_HSICLK
964#elif (STM32_SW == STM32_SW_HSE)
965#define STM32_SYSCLK STM32_HSECLK
966#elif (STM32_SW == STM32_SW_PLL)
967#define STM32_SYSCLK STM32_PLLCLKOUT
968#else
969#error "invalid STM32_SW value specified"
970#endif
971
972/* Check on the system clock.*/
973#if STM32_SYSCLK > STM32_SYSCLK_MAX
974#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
975#endif
976
977/* Calculating VOS settings, it is different for each sub-platform.*/
978#if defined(STM32F413xx)
979#if STM32_SYSCLK <= 64000000
980#define STM32_VOS STM32_VOS_SCALE3
981#elif STM32_SYSCLK <= 84000000
982#define STM32_VOS STM32_VOS_SCALE2
983#else
984#define STM32_VOS STM32_VOS_SCALE1
985#endif
986#define STM32_OVERDRIVE_REQUIRED FALSE
987#endif
988
989/**
990 * @brief AHB frequency.
991 */
992#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
993#define STM32_HCLK (STM32_SYSCLK / 1)
994#elif STM32_HPRE == STM32_HPRE_DIV2
995#define STM32_HCLK (STM32_SYSCLK / 2)
996#elif STM32_HPRE == STM32_HPRE_DIV4
997#define STM32_HCLK (STM32_SYSCLK / 4)
998#elif STM32_HPRE == STM32_HPRE_DIV8
999#define STM32_HCLK (STM32_SYSCLK / 8)
1000#elif STM32_HPRE == STM32_HPRE_DIV16
1001#define STM32_HCLK (STM32_SYSCLK / 16)
1002#elif STM32_HPRE == STM32_HPRE_DIV64
1003#define STM32_HCLK (STM32_SYSCLK / 64)
1004#elif STM32_HPRE == STM32_HPRE_DIV128
1005#define STM32_HCLK (STM32_SYSCLK / 128)
1006#elif STM32_HPRE == STM32_HPRE_DIV256
1007#define STM32_HCLK (STM32_SYSCLK / 256)
1008#elif STM32_HPRE == STM32_HPRE_DIV512
1009#define STM32_HCLK (STM32_SYSCLK / 512)
1010#else
1011#error "invalid STM32_HPRE value specified"
1012#endif
1013
1014/*
1015 * AHB frequency check.
1016 */
1017#if STM32_HCLK > STM32_SYSCLK_MAX
1018#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
1019#endif
1020
1021/**
1022 * @brief APB1 frequency.
1023 */
1024#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
1025#define STM32_PCLK1 (STM32_HCLK / 1)
1026#elif STM32_PPRE1 == STM32_PPRE1_DIV2
1027#define STM32_PCLK1 (STM32_HCLK / 2)
1028#elif STM32_PPRE1 == STM32_PPRE1_DIV4
1029#define STM32_PCLK1 (STM32_HCLK / 4)
1030#elif STM32_PPRE1 == STM32_PPRE1_DIV8
1031#define STM32_PCLK1 (STM32_HCLK / 8)
1032#elif STM32_PPRE1 == STM32_PPRE1_DIV16
1033#define STM32_PCLK1 (STM32_HCLK / 16)
1034#else
1035#error "invalid STM32_PPRE1 value specified"
1036#endif
1037
1038/*
1039 * APB1 frequency check.
1040 */
1041#if STM32_PCLK1 > STM32_PCLK1_MAX
1042#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
1043#endif
1044
1045/**
1046 * @brief APB2 frequency.
1047 */
1048#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
1049#define STM32_PCLK2 (STM32_HCLK / 1)
1050#elif STM32_PPRE2 == STM32_PPRE2_DIV2
1051#define STM32_PCLK2 (STM32_HCLK / 2)
1052#elif STM32_PPRE2 == STM32_PPRE2_DIV4
1053#define STM32_PCLK2 (STM32_HCLK / 4)
1054#elif STM32_PPRE2 == STM32_PPRE2_DIV8
1055#define STM32_PCLK2 (STM32_HCLK / 8)
1056#elif STM32_PPRE2 == STM32_PPRE2_DIV16
1057#define STM32_PCLK2 (STM32_HCLK / 16)
1058#else
1059#error "invalid STM32_PPRE2 value specified"
1060#endif
1061
1062/*
1063 * APB2 frequency check.
1064 */
1065#if STM32_PCLK2 > STM32_PCLK2_MAX
1066#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
1067#endif
1068
1069/*
1070 * PLLI2S enable check.
1071 */
1072#if (STM32_HAS_RCC_PLLI2S && \
1073 (STM32_CLOCK48_REQUIRED && \
1074 (STM32_HAS_RCC_CK48MSEL && \
1075 STM32_RCC_CK48MSEL_USES_I2S && \
1076 (STM32_CK48MSEL == STM32_CK48MSEL_PLLI2S)) || \
1077 (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) || \
1078 (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S))) || \
1079 defined(__DOXYGEN__)
1080
1081/**
1082 * @brief PLLI2S activation flag.
1083 */
1084#define STM32_ACTIVATE_PLLI2S TRUE
1085#else
1086#define STM32_ACTIVATE_PLLI2S FALSE
1087#endif
1088
1089/**
1090 * @brief STM32_PLLI2SM field.
1091 */
1092#if ((STM32_PLLI2SM_VALUE >= 2) && (STM32_PLLI2SM_VALUE <= 63)) || \
1093 defined(__DOXYGEN__)
1094#define STM32_PLLI2SM (STM32_PLLI2SM_VALUE << 0)
1095#else
1096#error "invalid STM32_PLLI2SM_VALUE value specified"
1097#endif
1098
1099/**
1100 * @brief STM32_PLLI2SN field.
1101 */
1102#if ((STM32_PLLI2SN_VALUE >= 50) && (STM32_PLLI2SN_VALUE <= 432)) || \
1103 defined(__DOXYGEN__)
1104#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6)
1105#else
1106#error "invalid STM32_PLLI2SN_VALUE value specified"
1107#endif
1108
1109/**
1110 * @brief STM32_PLLI2SQ field.
1111 */
1112#if ((STM32_PLLI2SQ_VALUE >= 2) && (STM32_PLLI2SQ_VALUE <= 15)) || \
1113 defined(__DOXYGEN__)
1114#define STM32_PLLI2SQ (STM32_PLLI2SQ_VALUE << 24)
1115#else
1116#error "invalid STM32_PLLI2SQ_VALUE value specified"
1117#endif
1118
1119/**
1120 * @brief STM32_PLLI2SR field.
1121 */
1122#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \
1123 defined(__DOXYGEN__)
1124#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28)
1125#else
1126#error "invalid STM32_PLLI2SR_VALUE value specified"
1127#endif
1128
1129/**
1130 * @brief STM32_PLLI2SDIVR field.
1131 */
1132#if ((STM32_PLLI2SDIVR_VALUE >= 1) && (STM32_PLLI2SDIVR_VALUE <= 32)) || \
1133 defined(__DOXYGEN__)
1134#define STM32_PLLI2SDIVR ((STM32_PLLI2SR_VALUE - 1) << 0)
1135#else
1136#error "invalid STM32_PLLI2SDIVQ_VALUE value specified"
1137#endif
1138
1139/**
1140 * @brief PLLI2S input clock frequency.
1141 */
1142#if STM32_HAS_RCC_I2SPLLSRC || defined(__DOXYGEN__)
1143#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) || defined(__DOXYGEN__)
1144#define STM32_PLLI2SCLKIN (STM32_PLLSRCCLK / STM32_PLLI2SM_VALUE)
1145#elif STM32_PLLI2SSRC == STM32_PLLI2SSRC_CKIN
1146#define STM32_PLLI2SCLKIN (STM32_I2SCKIN_VALUE / STM32_PLLI2SM_VALUE)
1147#else
1148#error "invalid STM32_PLLI2SSRC value specified"
1149#endif
1150#else
1151#define STM32_PLLI2SCLKIN (STM32_PLLSRCCLK / STM32_PLLM_VALUE)
1152#endif
1153
1154/**
1155 * @brief PLLI2S VCO frequency.
1156 */
1157#define STM32_PLLI2SVCO (STM32_PLLI2SCLKIN * STM32_PLLI2SN_VALUE)
1158
1159/*
1160 * PLLI2S VCO frequency range check.
1161 */
1162#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \
1163 (STM32_PLLI2SVCO > STM32_PLLVCO_MAX)
1164#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
1165#endif
1166
1167/**
1168 * @brief PLLI2S Q output clock frequency.
1169 */
1170#define STM32_PLLI2S_Q_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SQ_VALUE)
1171
1172/**
1173 * @brief PLLI2S R output clock frequency.
1174 */
1175#define STM32_PLLI2S_R_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)
1176
1177/**
1178 * @brief PLLI2SP enable bit.
1179 * @note Always 0, there is no PLLI2SP.
1180 */
1181#define STM32_PLLI2SP 0
1182
1183/**
1184 * @brief PLLSAI activation flag.
1185 * @note Always FALSE, there is no PLLSAI.
1186 */
1187#define STM32_ACTIVATE_PLLSAI FALSE
1188
1189/*===========================================================================*/
1190/* Driver data structures and types. */
1191/*===========================================================================*/
1192