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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32G0xx/hal_lld.h
19 * @brief STM32G0xx HAL subsystem low level driver header.
20 * @pre This module requires the following macros to be defined in the
21 * @p board.h file:
22 * - STM32_LSECLK.
23 * - STM32_LSEDRV.
24 * - STM32_LSE_BYPASS (optionally).
25 * - STM32_HSECLK.
26 * - STM32_HSE_BYPASS (optionally).
27 * .
28 * One of the following macros must also be defined:
29 * - STM32G070xx.
30 * - STM32G071xx, STM32G081xx.
31 * .
32 *
33 * @addtogroup HAL
34 * @{
35 */
36
37#ifndef HAL_LLD_H
38#define HAL_LLD_H
39
40#include "stm32_registry.h"
41
42/*===========================================================================*/
43/* Driver constants. */
44/*===========================================================================*/
45
46/**
47 * @name Platform identification
48 * @{
49 */
50#if defined(STM32G070xx) || defined(__DOXYGEN__)
51#define PLATFORM_NAME "STM32G0 Entry-level Value Line"
52
53#elif defined(STM32G071xx)
54#define PLATFORM_NAME "STM32G0 Entry-level"
55
56#elif defined(STM32G081xx)
57#define PLATFORM_NAME "STM32G0 Entry-level with Crypto"
58
59#else
60#error "STM32G0 device not specified"
61#endif
62
63/**
64 * @brief Sub-family identifier.
65 */
66#if !defined(STM32G0XX) || defined(__DOXYGEN__)
67#define STM32G0XX
68#endif
69/** @} */
70
71/**
72 * @name Internal clock sources
73 * @{
74 */
75#define STM32_HSI16CLK 16000000U /**< 16MHz internal clock. */
76#define STM32_LSICLK 32000U /**< Low speed internal clock. */
77/** @} */
78
79/**
80 * @name PWR_CR1 register bits definitions
81 * @{
82 */
83#define STM32_VOS_MASK (3U << 9U) /**< Core voltage mask. */
84#define STM32_VOS_RANGE1 (1U << 9U) /**< Core voltage 1.2 Volts. */
85#define STM32_VOS_RANGE2 (2U << 9U) /**< Core voltage 1.0 Volts. */
86/** @} */
87
88/**
89 * @name PWR_CR2 register bits definitions
90 * @{
91 */
92#define STM32_PVDE_DISABLED (0U << 1U) /**< PVD enable bit off. */
93#define STM32_PVDE_ENABLED (1U << 1U) /**< PVD enable bit on. */
94
95#define STM32_PVDFT_MASK (7U << 1U) /**< PVDFT bits mask. */
96#define STM32_PVDFT(n) ((n) << 1U) /**< PVDFT level. */
97#define STM32_PVDFT_LEV0 STM32_PVDFT(0U) /**< PVDFT level 0. */
98#define STM32_PVDFT_LEV1 STM32_PVDFT(1U) /**< PVDFT level 1. */
99#define STM32_PVDFT_LEV2 STM32_PVDFT(2U) /**< PVDFT level 2. */
100#define STM32_PVDFT_LEV3 STM32_PVDFT(3U) /**< PVDFT level 3. */
101#define STM32_PVDFT_LEV4 STM32_PVDFT(4U) /**< PVDFT level 4. */
102#define STM32_PVDFT_LEV5 STM32_PVDFT(5U) /**< PVDFT level 5. */
103#define STM32_PVDFT_LEV6 STM32_PVDFT(6U) /**< PVDFT level 6. */
104#define STM32_PVDFT_LEV7 STM32_PVDFT(7U) /**< PVDFT level 7. */
105
106#define STM32_PVDRT_MASK (7U << 4U) /**< PVDRT bits mask. */
107#define STM32_PVDRT(n) ((n) << 4U) /**< PVDRT level. */
108#define STM32_PVDRT_LEV0 STM32_PVDRT(0U) /**< PVDRT level 0. */
109#define STM32_PVDRT_LEV1 STM32_PVDRT(1U) /**< PVDRT level 1. */
110#define STM32_PVDRT_LEV2 STM32_PVDRT(2U) /**< PVDRT level 2. */
111#define STM32_PVDRT_LEV3 STM32_PVDRT(3U) /**< PVDRT level 3. */
112#define STM32_PVDRT_LEV4 STM32_PVDRT(4U) /**< PVDRT level 4. */
113#define STM32_PVDRT_LEV5 STM32_PVDRT(5U) /**< PVDRT level 5. */
114#define STM32_PVDRT_LEV6 STM32_PVDRT(6U) /**< PVDRT level 6. */
115#define STM32_PVDRT_LEV7 STM32_PVDRT(7U) /**< PVDRT level 7. */
116/** @} */
117
118/**
119 * @name RCC_CR register bits definitions
120 * @{
121 */
122#define STM32_HSIDIV_MASK (7U << 11U) /**< HSIDIV field mask. */
123#define STM32_HSIDIV_FIELD(n) ((n) << 11U) /**< HSIDIV field value. */
124#define STM32_HSIDIV_1 STM32_HSIDIV_FIELD(0U)
125#define STM32_HSIDIV_2 STM32_HSIDIV_FIELD(1U)
126#define STM32_HSIDIV_4 STM32_HSIDIV_FIELD(2U)
127#define STM32_HSIDIV_8 STM32_HSIDIV_FIELD(3U)
128#define STM32_HSIDIV_16 STM32_HSIDIV_FIELD(4U)
129#define STM32_HSIDIV_32 STM32_HSIDIV_FIELD(5U)
130#define STM32_HSIDIV_64 STM32_HSIDIV_FIELD(6U)
131#define STM32_HSIDIV_128 STM32_HSIDIV_FIELD(7U)
132/** @} */
133
134/**
135 * @name RCC_CFGR register bits definitions
136 * @{
137 */
138#define STM32_SW_MASK (7U << 0U) /**< SW field mask. */
139#define STM32_SW_HSISYS (0U << 0U) /**< SYSCLK source is HSISYS. */
140#define STM32_SW_HSE (1U << 0U) /**< SYSCLK source is HSE. */
141#define STM32_SW_PLLRCLK (2U << 0U) /**< SYSCLK source is PLL. */
142#define STM32_SW_LSI (3U << 0U) /**< SYSCLK source is LSI. */
143#define STM32_SW_LSE (4U << 0U) /**< SYSCLK source is LSE. */
144
145#define STM32_HPRE_MASK (15U << 8U) /**< HPRE field mask. */
146#define STM32_HPRE_FIELD(n) ((n) << 8U) /**< HPRE field value. */
147#define STM32_HPRE_DIV1 STM32_HPRE_FIELD(0U)
148#define STM32_HPRE_DIV2 STM32_HPRE_FIELD(8U)
149#define STM32_HPRE_DIV4 STM32_HPRE_FIELD(9U)
150#define STM32_HPRE_DIV8 STM32_HPRE_FIELD(10U)
151#define STM32_HPRE_DIV16 STM32_HPRE_FIELD(11U)
152#define STM32_HPRE_DIV64 STM32_HPRE_FIELD(12U)
153#define STM32_HPRE_DIV128 STM32_HPRE_FIELD(13U)
154#define STM32_HPRE_DIV256 STM32_HPRE_FIELD(14U)
155#define STM32_HPRE_DIV512 STM32_HPRE_FIELD(15U)
156
157#define STM32_PPRE_MASK (7U << 12U) /**< PPRE field mask. */
158#define STM32_PPRE_FIELD(n) ((n) << 12U) /**< PPRE field value. */
159#define STM32_PPRE_DIV1 STM32_PPRE_FIELD(0U)
160#define STM32_PPRE_DIV2 STM32_PPRE_FIELD(4U)
161#define STM32_PPRE_DIV4 STM32_PPRE_FIELD(5U)
162#define STM32_PPRE_DIV8 STM32_PPRE_FIELD(6U)
163#define STM32_PPRE_DIV16 STM32_PPRE_FIELD(7U)
164
165#define STM32_MCOSEL_MASK (7U << 24U) /**< MCOSEL field mask. */
166#define STM32_MCOSEL_NOCLOCK (0U << 24U) /**< No clock on MCO pin. */
167#define STM32_MCOSEL_SYSCLK (1U << 24U) /**< SYSCLK on MCO pin. */
168#define STM32_MCOSEL_HSI16 (3U << 24U) /**< HSI16 clock on MCO pin. */
169#define STM32_MCOSEL_HSE (4U << 24U) /**< HSE clock on MCO pin. */
170#define STM32_MCOSEL_PLLRCLK (5U << 24U) /**< PLLR clock on MCO pin. */
171#define STM32_MCOSEL_LSI (6U << 24U) /**< LSI clock on MCO pin. */
172#define STM32_MCOSEL_LSE (7U << 24U) /**< LSE clock on MCO pin. */
173
174#define STM32_MCOPRE_MASK (7U << 28U) /**< MCOPRE field mask. */
175#define STM32_MCOPRE_FIELD(n) ((n) << 28U)/**< MCOPRE field value */
176#define STM32_MCOPRE_DIV1 STM32_MCOPRE_FIELD(0U)
177#define STM32_MCOPRE_DIV2 STM32_MCOPRE_FIELD(1U)
178#define STM32_MCOPRE_DIV4 STM32_MCOPRE_FIELD(2U)
179#define STM32_MCOPRE_DIV8 STM32_MCOPRE_FIELD(3U)
180#define STM32_MCOPRE_DIV16 STM32_MCOPRE_FIELD(4U)
181#define STM32_MCOPRE_DIV32 STM32_MCOPRE_FIELD(5U)
182#define STM32_MCOPRE_DIV64 STM32_MCOPRE_FIELD(6U)
183#define STM32_MCOPRE_DIV128 STM32_MCOPRE_FIELD(7U)
184/** @} */
185
186/**
187 * @name RCC_PLLCFGR register bits definitions
188 * @{
189 */
190#define STM32_PLLSRC_MASK (3 << 0) /**< PLL clock source mask. */
191#define STM32_PLLSRC_NOCLOCK (0 << 0) /**< PLL clock source disabled. */
192#define STM32_PLLSRC_HSI16 (2 << 0) /**< PLL clock source is HSI16. */
193#define STM32_PLLSRC_HSE (3 << 0) /**< PLL clock source is HSE. */
194/** @} */
195
196/**
197 * @name RCC_CCIPR register bits definitions
198 * @{
199 */
200#define STM32_USART1SEL_MASK (3U << 0U) /**< USART1SEL mask. */
201#define STM32_USART1SEL_PCLK (0U << 0U) /**< USART1 source is PCLK. */
202#define STM32_USART1SEL_SYSCLK (1U << 0U) /**< USART1 source is SYSCLK. */
203#define STM32_USART1SEL_HSI16 (2U << 0U) /**< USART1 source is HSI16. */
204#define STM32_USART1SEL_LSE (3U << 0U) /**< USART1 source is LSE. */
205
206#define STM32_USART2SEL_MASK (3U << 2U) /**< USART2 mask. */
207#define STM32_USART2SEL_PCLK (0U << 2U) /**< USART2 source is PCLK. */
208#define STM32_USART2SEL_SYSCLK (1U << 2U) /**< USART2 source is SYSCLK. */
209#define STM32_USART2SEL_HSI16 (2U << 2U) /**< USART2 source is HSI16. */
210#define STM32_USART2SEL_LSE (3U << 2U) /**< USART2 source is LSE. */
211
212#define STM32_CECSEL_MASK (1U << 6U) /**< CEC mask. */
213#define STM32_CECSEL_HSI16DIV (0U << 6U) /**< CEC source is HSI16/448. */
214#define STM32_CECSEL_LSE (1U << 6U) /**< CEC source is LSE. */
215
216#define STM32_LPUART1SEL_MASK (3U << 10U) /**< LPUART1 mask. */
217#define STM32_LPUART1SEL_PCLK (0U << 10U) /**< LPUART1 source is PCLK. */
218#define STM32_LPUART1SEL_SYSCLK (1U << 10U) /**< LPUART1 source is SYSCLK. */
219#define STM32_LPUART1SEL_HSI16 (2U << 10U) /**< LPUART1 source is HSI16. */
220#define STM32_LPUART1SEL_LSE (3U << 10U) /**< LPUART1 source is LSE. */
221
222#define STM32_I2C1SEL_MASK (3U << 12U) /**< I2C1SEL mask. */
223#define STM32_I2C1SEL_PCLK (0U << 12U) /**< I2C1 source is PCLK. */
224#define STM32_I2C1SEL_SYSCLK (1U << 12U) /**< I2C1 source is SYSCLK. */
225#define STM32_I2C1SEL_HSI16 (2U << 12U) /**< I2C1 source is HSI16. */
226
227#define STM32_I2S1SEL_MASK (3U << 14U) /**< I2S1SEL mask. */
228#define STM32_I2S1SEL_SYSCLK (0U << 14U) /**< I2S1 source is SYSCLK. */
229#define STM32_I2S1SEL_PLLPCLK (1U << 14U) /**< I2S1 source is PLLPCLK. */
230#define STM32_I2S1SEL_HSI16 (2U << 14U) /**< I2S1 source is HSI16. */
231#define STM32_I2S1SEL_CKIN (3U << 14U) /**< I2S1 source is CKIN. */
232
233#define STM32_LPTIM1SEL_MASK (3U << 18U) /**< LPTIM1SEL mask. */
234#define STM32_LPTIM1SEL_PCLK (0U << 18U) /**< LPTIM1 source is PCLK. */
235#define STM32_LPTIM1SEL_LSI (1U << 18U) /**< LPTIM1 source is LSI. */
236#define STM32_LPTIM1SEL_HSI16 (2U << 18U) /**< LPTIM1 source is HSI16. */
237#define STM32_LPTIM1SEL_LSE (3U << 18U) /**< LPTIM1 source is LSE. */
238
239#define STM32_LPTIM2SEL_MASK (3U << 20U) /**< LPTIM2SEL mask. */
240#define STM32_LPTIM2SEL_PCLK (0U << 20U) /**< LPTIM2 source is PCLK. */
241#define STM32_LPTIM2SEL_LSI (1U << 20U) /**< LPTIM2 source is LSI. */
242#define STM32_LPTIM2SEL_HSI16 (2U << 20U) /**< LPTIM2 source is HSI16. */
243#define STM32_LPTIM2SEL_LSE (3U << 20U) /**< LPTIM2 source is LSE. */
244
245#define STM32_TIM1SEL_MASK (1U << 22U) /**< TIM1SEL mask. */
246#define STM32_TIM1SEL_TIMPCLK (0U << 22U) /**< TIM1SEL source is TIMPCLK. */
247#define STM32_TIM1SEL_PLLQCLK (1U << 22U) /**< TIM1SEL source is PLLQCLK. */
248
249#define STM32_TIM15SEL_MASK (1U << 24U) /**< TIM15SEL mask. */
250#define STM32_TIM15SEL_TIMPCLK (0U << 24U) /**< TIM15SEL source is TIMPCLK.*/
251#define STM32_TIM15SEL_PLLQCLK (1U << 24U) /**< TIM15SEL source is PLLQCLK.*/
252
253#define STM32_RNGSEL_MASK (3U << 26U) /**< RNGSEL mask. */
254#define STM32_RNGSEL_NOCLOCK (0U << 26U) /**< RNG source is disabled. */
255#define STM32_RNGSEL_HSI16 (1U << 26U) /**< RNG source is HSI16. */
256#define STM32_RNGSEL_SYSCLK (2U << 26U) /**< RNG source is SYSCLK. */
257#define STM32_RNGSEL_PLLQCLK (3U << 26U) /**< RNG source is PLLQCLK. */
258
259#define STM32_RNGDIV_MASK (3U << 28U) /**< RNGDIV field mask. */
260#define STM32_RNGDIV_FIELD(n) ((n) << 28U)/**< RNGDIV field value */
261#define STM32_RNGDIV_1 STM32_RNGDIV_FIELD(0U)
262#define STM32_RNGDIV_2 STM32_RNGDIV_FIELD(1U)
263#define STM32_RNGDIV_4 STM32_RNGDIV_FIELD(2U)
264#define STM32_RNGDIV_8 STM32_RNGDIV_FIELD(3U)
265
266#define STM32_ADCSEL_MASK (3U << 30U) /**< ADCSEL mask. */
267#define STM32_ADCSEL_SYSCLK (0U << 30U) /**< ADC source is SYSCLK. */
268#define STM32_ADCSEL_PLLPCLK (1U << 30U) /**< ADC source is PLLPCLK. */
269#define STM32_ADCSEL_HSI16 (2U << 30U) /**< ADC source is HSI16. */
270/** @} */
271
272/**
273 * @name RCC_BDCR register bits definitions
274 * @{
275 */
276#define STM32_RTCSEL_MASK (3U << 8U) /**< RTC source mask. */
277#define STM32_RTCSEL_NOCLOCK (0U << 8U) /**< No RTC source. */
278#define STM32_RTCSEL_LSE (1U << 8U) /**< RTC source is LSE. */
279#define STM32_RTCSEL_LSI (2U << 8U) /**< RTC source is LSI. */
280#define STM32_RTCSEL_HSEDIV (3U << 8U) /**< RTC source is HSE divided. */
281
282#define STM32_LSCOSEL_MASK (3U << 24U) /**< LSCO pin clock source. */
283#define STM32_LSCOSEL_NOCLOCK (0U << 24U) /**< No clock on LSCO pin. */
284#define STM32_LSCOSEL_LSI (1U << 24U) /**< LSI on LSCO pin. */
285#define STM32_LSCOSEL_LSE (3U << 24U) /**< LSE on LSCO pin. */
286/** @} */
287
288/*===========================================================================*/
289/* Driver pre-compile time settings. */
290/*===========================================================================*/
291
292/**
293 * @name Configuration options
294 * @{
295 */
296/**
297 * @brief Disables the PWR/RCC initialization in the HAL.
298 */
299#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
300#define STM32_NO_INIT FALSE
301#endif
302
303/**
304 * @brief Core voltage selection.
305 * @note This setting affects all the performance and clock related
306 * settings, the maximum performance is only obtainable selecting
307 * the maximum voltage.
308 */
309#if !defined(STM32_VOS) || defined(__DOXYGEN__)
310#define STM32_VOS STM32_VOS_RANGE1
311#endif
312
313/**
314 * @brief PWR CR2 register initialization value.
315 */
316#if !defined(STM32_PWR_CR2) || defined(__DOXYGEN__)
317#define STM32_PWR_CR2 (STM32_PVDRT_LEV0 | \
318 STM32_PVDFT_LEV0 | \
319 STM32_PVDE_DISABLED)
320#endif
321
322/**
323 * @brief HSI16 divider value.
324 * @note The allowed values are 1, 2, 4, 8, 16, 32, 64, 128.
325 */
326#if !defined(STM32_HSIDIV_VALUE) || defined(__DOXYGEN__)
327#define STM32_HSIDIV_VALUE 1
328#endif
329
330/**
331 * @brief Enables or disables the HSI16 clock source.
332 */
333#if !defined(STM32_HSI16_ENABLED) || defined(__DOXYGEN__)
334#define STM32_HSI16_ENABLED FALSE
335#endif
336
337/**
338 * @brief Enables or disables the HSE clock source.
339 */
340#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
341#define STM32_HSE_ENABLED FALSE
342#endif
343
344/**
345 * @brief Enables or disables the LSI clock source.
346 */
347#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
348#define STM32_LSI_ENABLED FALSE
349#endif
350
351/**
352 * @brief Enables or disables the LSE clock source.
353 */
354#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
355#define STM32_LSE_ENABLED FALSE
356#endif
357
358/**
359 * @brief Main clock source selection.
360 * @note If the selected clock source is not the PLL then the PLL is not
361 * initialized and started.
362 * @note The default value is calculated for a 64MHz system clock from
363 * the internal 16MHz HSI clock.
364 */
365#if !defined(STM32_SW) || defined(__DOXYGEN__)
366#define STM32_SW STM32_SW_PLLRCLK
367#endif
368
369/**
370 * @brief Clock source for the PLL.
371 * @note This setting has only effect if the PLL is selected as the
372 * system clock source.
373 * @note The default value is calculated for a 64MHz system clock from
374 * the internal 16MHz HSI clock.
375 */
376#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
377#define STM32_PLLSRC STM32_PLLSRC_HSI16
378#endif
379
380/**
381 * @brief PLLM divider value.
382 * @note The allowed values are 1..8.
383 * @note The default value is calculated for a 64MHz system clock from
384 * the internal 16MHz HSI clock.
385 */
386#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
387#define STM32_PLLM_VALUE 2
388#endif
389
390/**
391 * @brief PLLN multiplier value.
392 * @note The allowed values are 8..86.
393 * @note The default value is calculated for a 64MHz system clock from
394 * the internal 16MHz HSI clock.
395 */
396#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
397#define STM32_PLLN_VALUE 16
398#endif
399
400/**
401 * @brief PLLP divider value.
402 * @note The allowed values are 2..32.
403 */
404#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
405#define STM32_PLLP_VALUE 2
406#endif
407
408/**
409 * @brief PLLQ divider value.
410 * @note The allowed values are 2..8.
411 */
412#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
413#define STM32_PLLQ_VALUE 4
414#endif
415
416/**
417 * @brief PLLR divider value.
418 * @note The allowed values are 2..8.
419 * @note The default value is calculated for a 64MHz system clock from
420 * the internal 16MHz HSI clock.
421 */
422#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
423#define STM32_PLLR_VALUE 2
424#endif
425
426/**
427 * @brief AHB prescaler value.
428 * @note The default value is calculated for a 64MHz system clock from
429 * the internal 16MHz HSI clock.
430 */
431#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
432#define STM32_HPRE STM32_HPRE_DIV1
433#endif
434
435/**
436 * @brief APB prescaler value.
437 */
438#if !defined(STM32_PPRE) || defined(__DOXYGEN__)
439#define STM32_PPRE STM32_PPRE_DIV1
440#endif
441
442/**
443 * @brief MCO clock source.
444 */
445#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
446#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
447#endif
448
449/**
450 * @brief MCO divider setting.
451 */
452#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
453#define STM32_MCOPRE STM32_MCOPRE_DIV1
454#endif
455
456/**
457 * @brief LSCO clock source.
458 */
459#if !defined(STM32_LSCOSEL) || defined(__DOXYGEN__)
460#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
461#endif
462
463/**
464 * @brief USART1 clock source.
465 */
466#if !defined(STM32_USART1SEL) || defined(__DOXYGEN__)
467#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
468#endif
469
470/**
471 * @brief USART2 clock source.
472 */
473#if !defined(STM32_USART2SEL) || defined(__DOXYGEN__)
474#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
475#endif
476
477/**
478 * @brief LPUART1 clock source.
479 */
480#if !defined(STM32_LPUART1SEL) || defined(__DOXYGEN__)
481#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
482#endif
483
484/**
485 * @brief CEC clock source.
486 */
487#if !defined(STM32_CECSEL) || defined(__DOXYGEN__)
488#define STM32_CECSEL STM32_CECSEL_HSI16DIV
489#endif
490
491/**
492 * @brief I2C1 clock source.
493 */
494#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__)
495#define STM32_I2C1SEL STM32_I2C1SEL_PCLK
496#endif
497
498/**
499 * @brief I2S1 clock source.
500 */
501#if !defined(STM32_I2S1SEL) || defined(__DOXYGEN__)
502#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK
503#endif
504
505/**
506 * @brief LPTIM1 clock source.
507 */
508#if !defined(STM32_LPTIM1SEL) || defined(__DOXYGEN__)
509#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK
510#endif
511
512/**
513 * @brief LPTIM2 clock source.
514 */
515#if !defined(STM32_LPTIM2SEL) || defined(__DOXYGEN__)
516#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK
517#endif
518
519/**
520 * @brief TIM1 clock source.
521 */
522#if !defined(STM32_TIM1SEL) || defined(__DOXYGEN__)
523#define STM32_TIM1SEL STM32_TIM1SEL_TIMPCLK
524#endif
525
526/**
527 * @brief TIM15 clock source.
528 */
529#if !defined(STM32_TIM15SEL) || defined(__DOXYGEN__)
530#define STM32_TIM15SEL STM32_TIM15SEL_TIMPCLK
531#endif
532
533/**
534 * @brief RNG clock source.
535 */
536#if !defined(STM32_RNGSEL) || defined(__DOXYGEN__)
537#define STM32_RNGSEL STM32_RNGSEL_HSI16
538#endif
539
540/**
541 * @brief RNG divider value.
542 */
543#if !defined(STM32_RNGDIV_VALUE) || defined(__DOXYGEN__)
544#define STM32_RNGDIV_VALUE 1
545#endif
546
547/**
548 * @brief ADC clock source.
549 */
550#if !defined(STM32_ADCSEL) || defined(__DOXYGEN__)
551#define STM32_ADCSEL STM32_ADCSEL_PLLPCLK
552#endif
553
554/**
555 * @brief RTC clock source.
556 */
557#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
558#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
559#endif
560/** @} */
561
562/*===========================================================================*/
563/* Derived constants and error checks. */
564/*===========================================================================*/
565
566/*
567 * Configuration-related checks.
568 */
569#if !defined(STM32G0xx_MCUCONF)
570#error "Using a wrong mcuconf.h file, STM32G0xx_MCUCONF not defined"
571#endif
572
573#if defined(STM32G070xx) && !defined(STM32G070_MCUCONF)
574#error "Using a wrong mcuconf.h file, STM32G070_MCUCONF not defined"
575
576#elif defined(STM32G071xx) && !defined(STM32G071_MCUCONF)
577#error "Using a wrong mcuconf.h file, STM32G071_MCUCONF not defined"
578
579#elif defined(STM32G081xx) && !defined(STM32G081_MCUCONF)
580#error "Using a wrong mcuconf.h file, STM32G071_MCUCONF not defined"
581
582#endif
583
584/*
585 * Board files sanity checks.
586 */
587#if !defined(STM32_LSECLK)
588#error "STM32_LSECLK not defined in board.h"
589#endif
590
591#if !defined(STM32_LSEDRV)
592#error "STM32_LSEDRV not defined in board.h"
593#endif
594
595#if !defined(STM32_HSECLK)
596#error "STM32_HSECLK not defined in board.h"
597#endif
598
599/* Voltage related limits.*/
600#if (STM32_VOS == STM32_VOS_RANGE1) || defined(__DOXYGEN__)
601/**
602 * @name System Limits
603 * @{
604 */
605/**
606 * @brief Maximum SYSCLK clock frequency.
607 */
608#define STM32_SYSCLK_MAX 64000000
609
610/**
611 * @brief Maximum HSE clock frequency at current voltage setting.
612 */
613#define STM32_HSECLK_MAX 48000000
614
615/**
616 * @brief Maximum HSE clock frequency using an external source.
617 */
618#define STM32_HSECLK_BYP_MAX 48000000
619
620/**
621 * @brief Minimum HSE clock frequency.
622 */
623#define STM32_HSECLK_MIN 4000000
624
625/**
626 * @brief Minimum HSE clock frequency using an external source.
627 */
628#define STM32_HSECLK_BYP_MIN 8000000
629
630/**
631 * @brief Maximum LSE clock frequency.
632 */
633#define STM32_LSECLK_MAX 32768
634
635/**
636 * @brief Maximum LSE clock frequency.
637 */
638#define STM32_LSECLK_BYP_MAX 1000000
639
640/**
641 * @brief Minimum LSE clock frequency.
642 */
643#define STM32_LSECLK_MIN 32768
644
645/**
646 * @brief Minimum LSE clock frequency.
647 */
648#define STM32_LSECLK_BYP_MIN 32768
649
650/**
651 * @brief Maximum PLLs input clock frequency.
652 */
653#define STM32_PLLIN_MAX 16000000
654
655/**
656 * @brief Minimum PLLs input clock frequency.
657 */
658#define STM32_PLLIN_MIN 2660000
659
660/**
661 * @brief Maximum VCO clock frequency at current voltage setting.
662 */
663#define STM32_PLLVCO_MAX 344000000
664
665/**
666 * @brief Minimum VCO clock frequency at current voltage setting.
667 */
668#define STM32_PLLVCO_MIN 64000000
669
670/**
671 * @brief Maximum PLL-P output clock frequency.
672 */
673#define STM32_PLLP_MAX 128000000
674
675/**
676 * @brief Minimum PLL-P output clock frequency.
677 */
678#define STM32_PLLP_MIN 3090000
679
680/**
681 * @brief Maximum PLL-Q output clock frequency.
682 */
683#define STM32_PLLQ_MAX 128000000
684
685/**
686 * @brief Minimum PLL-Q output clock frequency.
687 */
688#define STM32_PLLQ_MIN 12000000
689
690/**
691 * @brief Maximum PLL-R output clock frequency.
692 */
693#define STM32_PLLR_MAX 64000000
694
695/**
696 * @brief Minimum PLL-R output clock frequency.
697 */
698#define STM32_PLLR_MIN 12000000
699
700/**
701 * @brief Maximum APB clock frequency.
702 */
703#define STM32_PCLK_MAX 64000000
704
705/**
706 * @brief Maximum ADC clock frequency.
707 */
708#define STM32_ADCCLK_MAX 350000000
709/** @} */
710
711/**
712 * @name Flash Wait states
713 * @{
714 */
715#define STM32_0WS_THRESHOLD 24000000
716#define STM32_1WS_THRESHOLD 48000000
717#define STM32_2WS_THRESHOLD 64000000
718#define STM32_3WS_THRESHOLD 0
719#define STM32_4WS_THRESHOLD 0
720#define STM32_5WS_THRESHOLD 0
721/** @} */
722
723#elif STM32_VOS == STM32_VOS_RANGE2
724#define STM32_SYSCLK_MAX 16000000
725#define STM32_HSECLK_MAX 16000000
726#define STM32_HSECLK_BYP_MAX 16000000
727#define STM32_HSECLK_MIN 4000000
728#define STM32_HSECLK_BYP_MIN 8000000
729#define STM32_LSECLK_MAX 32768
730#define STM32_LSECLK_BYP_MAX 1000000
731#define STM32_LSECLK_MIN 32768
732#define STM32_LSECLK_BYP_MIN 32768
733#define STM32_PLLIN_MAX 16000000
734#define STM32_PLLIN_MIN 2660000
735#define STM32_PLLVCO_MAX 128000000
736#define STM32_PLLVCO_MIN 96000000
737#define STM32_PLLP_MAX 40000000
738#define STM32_PLLP_MIN 3090000
739#define STM32_PLLQ_MAX 32000000
740#define STM32_PLLQ_MIN 12000000
741#define STM32_PLLR_MAX 16000000
742#define STM32_PLLR_MIN 12000000
743#define STM32_PCLK_MAX 16000000
744#define STM32_ADCCLK_MAX 16000000
745
746#define STM32_0WS_THRESHOLD 8000000
747#define STM32_1WS_THRESHOLD 16000000
748#define STM32_2WS_THRESHOLD 0
749#define STM32_3WS_THRESHOLD 0
750#define STM32_4WS_THRESHOLD 0
751#define STM32_5WS_THRESHOLD 0
752
753#else
754#error "invalid STM32_VOS value specified"
755#endif
756
757/*
758 * HSI16 related checks.
759 */
760#if STM32_HSI16_ENABLED
761#else /* !STM32_HSI16_ENABLED */
762
763#if STM32_SW == STM32_SW_HSISYS
764#error "HSI16 not enabled, required by STM32_SW"
765#endif
766
767#if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSI16)
768#error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC"
769#endif
770
771/* NOTE: Missing checks on the HSI16 pre-muxes, it is also required for newer
772 L4 devices.*/
773
774#if (STM32_MCOSEL == STM32_MCOSEL_HSI16) || \
775 ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
776 (STM32_PLLSRC == STM32_PLLSRC_HSI16))
777#error "HSI16 not enabled, required by STM32_MCOSEL"
778#endif
779
780#if (STM32_USART1SEL == STM32_USART1SEL_HSI16)
781#error "HSI16 not enabled, required by STM32_USART1SEL"
782#endif
783#if (STM32_USART2SEL == STM32_USART2SEL_HSI16)
784#error "HSI16 not enabled, required by STM32_USART2SEL"
785#endif
786#if (STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16)
787#error "HSI16 not enabled, required by STM32_LPUART1SEL"
788#endif
789
790#if (STM32_CECSEL == STM32_CECSEL_HSI16DIV)
791#error "HSI16 not enabled, required by STM32_CECSEL"
792#endif
793
794#if (STM32_I2C1SEL == STM32_I2C1SEL_HSI16)
795#error "HSI16 not enabled, required by STM32_I2C1SEL"
796#endif
797#if (STM32_I2S1SEL == STM32_I2S1SEL_HSI16)
798#error "HSI16 not enabled, required by STM32_I2S1SEL"
799#endif
800
801#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16)
802#error "HSI16 not enabled, required by STM32_LPTIM1SEL"
803#endif
804#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16)
805#error "HSI16 not enabled, required by STM32_LPTIM2SEL"
806#endif
807
808#if (STM32_RNGSEL == STM32_RNGSEL_HSI16)
809#error "HSI16 not enabled, required by STM32_RNGSEL"
810#endif
811
812#if (STM32_ADCSEL == STM32_ADCSEL_HSI16)
813#error "HSI16 not enabled, required by STM32_ADCSEL"
814#endif
815
816#endif /* !STM32_HSI16_ENABLED */
817
818/*
819 * HSE related checks.
820 */
821#if STM32_HSE_ENABLED
822
823 #if STM32_HSECLK == 0
824 #error "HSE frequency not defined"
825 #else /* STM32_HSECLK != 0 */
826 #if defined(STM32_HSE_BYPASS)
827 #if (STM32_HSECLK < STM32_HSECLK_BYP_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
828 #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_BYP_MIN...STM32_HSECLK_BYP_MAX)"
829 #endif
830 #else /* !defined(STM32_HSE_BYPASS) */
831 #if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
832 #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
833 #endif
834 #endif /* !defined(STM32_HSE_BYPASS) */
835 #endif /* STM32_HSECLK != 0 */
836
837 #else /* !STM32_HSE_ENABLED */
838
839 #if STM32_SW == STM32_SW_HSE
840 #error "HSE not enabled, required by STM32_SW"
841 #endif
842
843 #if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
844 #error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
845 #endif
846
847 #if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
848 ((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \
849 (STM32_PLLSRC == STM32_PLLSRC_HSE))
850 #error "HSE not enabled, required by STM32_MCOSEL"
851 #endif
852
853 #if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
854 #error "HSE not enabled, required by STM32_RTCSEL"
855 #endif
856
857#endif /* !STM32_HSE_ENABLED */
858
859/*
860 * LSI related checks.
861 */
862#if STM32_LSI_ENABLED
863#else /* !STM32_LSI_ENABLED */
864
865 #if HAL_USE_RTC && (STM32_RTCSEL == STM32_RTCSEL_LSI)
866 #error "LSI not enabled, required by STM32_RTCSEL"
867 #endif
868
869 #if STM32_MCOSEL == STM32_MCOSEL_LSI
870 #error "LSI not enabled, required by STM32_MCOSEL"
871 #endif
872
873 #if STM32_LSCOSEL == STM32_LSCOSEL_LSI
874 #error "LSI not enabled, required by STM32_LSCOSEL"
875 #endif
876
877#endif /* !STM32_LSI_ENABLED */
878
879/*
880 * LSE related checks.
881 */
882#if STM32_LSE_ENABLED
883
884 #if (STM32_LSECLK == 0)
885 #error "LSE frequency not defined"
886 #endif
887
888 #if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
889 #error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
890 #endif
891
892#else /* !STM32_LSE_ENABLED */
893
894 #if STM32_RTCSEL == STM32_RTCSEL_LSE
895 #error "LSE not enabled, required by STM32_RTCSEL"
896 #endif
897
898 #if STM32_MCOSEL == STM32_MCOSEL_LSE
899 #error "LSE not enabled, required by STM32_MCOSEL"
900 #endif
901
902 #if STM32_LSCOSEL == STM32_LSCOSEL_LSE
903 #error "LSE not enabled, required by STM32_LSCOSEL"
904 #endif
905
906#endif /* !STM32_LSE_ENABLED */
907
908/**
909 * @brief STM32_HSIDIV field.
910 */
911#if (STM32_HSIDIV_VALUE == 1) || defined(__DOXYGEN__)
912#define STM32_HSIDIV STM32_HSIDIV_1
913#elif STM32_HSIDIV_VALUE == 2
914#define STM32_HSIDIV STM32_HSIDIV_2
915#elif STM32_HSIDIV_VALUE == 4
916#define STM32_HSIDIV STM32_HSIDIV_4
917#elif STM32_HSIDIV_VALUE == 8
918#define STM32_HSIDIV STM32_HSIDIV_8
919#elif STM32_HSIDIV_VALUE == 16
920#define STM32_HSIDIV STM32_HSIDIV_16
921#elif STM32_HSIDIV_VALUE == 32
922#define STM32_HSIDIV STM32_HSIDIV_32
923#elif STM32_HSIDIV_VALUE == 64
924#define STM32_HSIDIV STM32_HSIDIV_64
925#elif STM32_HSIDIV_VALUE == 128
926#define STM32_HSIDIV STM32_HSIDIV_128
927#else
928#error "invalid STM32_HSIDIV_VALUE value specified"
929#endif
930
931/**
932 * @brief STM32_PLLM field.
933 */
934#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 8)) || \
935 defined(__DOXYGEN__)
936#define STM32_PLLM ((STM32_PLLM_VALUE - 1) << 4)
937#else
938#error "invalid STM32_PLLM_VALUE value specified"
939#endif
940
941/**
942 * @brief PLL input clock frequency.
943 */
944#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
945#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
946
947#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
948#define STM32_PLLCLKIN (STM32_HSI16CLK / STM32_PLLM_VALUE)
949
950#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
951#define STM32_PLLCLKIN 0
952
953#else
954#error "invalid STM32_PLLSRC value specified"
955#endif
956
957/*
958 * PLL input frequency range check.
959 */
960#if (STM32_PLLCLKIN != 0) && \
961 ((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX))
962#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
963#endif
964
965/*
966 * PLL enable check.
967 */
968#if (STM32_SW == STM32_SW_PLLRCLK) || \
969 (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
970 (STM32_TIM1SEL == STM32_TIM1SEL_PLLQCLK) || \
971 (STM32_TIM15SEL == STM32_TIM15SEL_PLLQCLK) || \
972 (STM32_RNGSEL == STM32_RNGSEL_PLLQCLK) || \
973 (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \
974 (STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK) || \
975 defined(__DOXYGEN__)
976
977#if STM32_PLLCLKIN == 0
978#error "PLL activation required but no PLL clock selected"
979#endif
980
981/**
982 * @brief PLL activation flag.
983 */
984#define STM32_ACTIVATE_PLL TRUE
985#else
986#define STM32_ACTIVATE_PLL FALSE
987#endif
988
989/**
990 * @brief STM32_PLLN field.
991 */
992#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 86)) || \
993 defined(__DOXYGEN__)
994#define STM32_PLLN (STM32_PLLN_VALUE << 8)
995#else
996#error "invalid STM32_PLLN_VALUE value specified"
997#endif
998
999/**
1000 * @brief STM32_PLLR field.
1001 */
1002#if ((STM32_PLLR_VALUE >= 2) && (STM32_PLLR_VALUE <= 8)) || \
1003 defined(__DOXYGEN__)
1004#define STM32_PLLR ((STM32_PLLR_VALUE - 1) << 29)
1005#else
1006#error "invalid STM32_PLLR_VALUE value specified"
1007#endif
1008
1009/**
1010 * @brief STM32_PLLQ field.
1011 */
1012#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 8)) || \
1013 defined(__DOXYGEN__)
1014#define STM32_PLLQ ((STM32_PLLQ_VALUE - 1) << 25)
1015#else
1016#error "invalid STM32_PLLQ_VALUE value specified"
1017#endif
1018
1019/**
1020 * @brief STM32_PLLP field.
1021 */
1022#if ((STM32_PLLP_VALUE >= 2) && (STM32_PLLP_VALUE <= 32)) || \
1023 defined(__DOXYGEN__)
1024#define STM32_PLLP ((STM32_PLLP_VALUE - 1) << 17)
1025#else
1026#error "invalid STM32_PLLP_VALUE value specified"
1027#endif
1028
1029/**
1030 * @brief STM32_PLLREN field.
1031 */
1032#if (STM32_SW == STM32_SW_PLLRCLK) || \
1033 (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
1034 defined(__DOXYGEN__)
1035#define STM32_PLLREN (1 << 28)
1036#else
1037#define STM32_PLLREN (0 << 28)
1038#endif
1039
1040/**
1041 * @brief STM32_PLLQEN field.
1042 */
1043#if (STM32_TIM1SEL == STM32_TIM1SEL_PLLQCLK) || \
1044 (STM32_TIM15SEL == STM32_TIM15SEL_PLLQCLK) || \
1045 (STM32_RNGSEL == STM32_RNGSEL_PLLQCLK) || \
1046 defined(__DOXYGEN__)
1047#define STM32_PLLQEN (1 << 24)
1048#else
1049#define STM32_PLLQEN (0 << 24)
1050#endif
1051
1052/**
1053 * @brief STM32_PLLPEN field.
1054 */
1055#if (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \
1056 (STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK) || \
1057 defined(__DOXYGEN__)
1058#define STM32_PLLPEN (1 << 16)
1059#else
1060#define STM32_PLLPEN (0 << 16)
1061#endif
1062
1063/**
1064 * @brief PLL VCO frequency.
1065 */
1066#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
1067
1068/*
1069 * PLL VCO frequency range check.
1070 */
1071#if STM32_ACTIVATE_PLL && \
1072 ((STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX))
1073#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
1074#endif
1075
1076/**
1077 * @brief PLL R output clock frequency.
1078 */
1079#define STM32_PLL_R_CLKOUT (STM32_PLLVCO / STM32_PLLR_VALUE)
1080
1081/**
1082 * @brief PLL Q output clock frequency.
1083 */
1084#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE)
1085
1086/**
1087 * @brief PLL P output clock frequency.
1088 */
1089#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
1090
1091/*
1092 * PLL-R output frequency range check.
1093 */
1094#if STM32_ACTIVATE_PLL && \
1095 ((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX))
1096#error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
1097#endif
1098
1099/*
1100 * PLL-Q output frequency range check.
1101 */
1102#if STM32_ACTIVATE_PLL && \
1103 ((STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX))
1104#error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
1105#endif
1106
1107/*
1108 * PLL-P output frequency range check.
1109 */
1110#if STM32_ACTIVATE_PLL && \
1111 ((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX))
1112#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
1113#endif
1114
1115/**
1116 * @brief HSISYS clock frequency.
1117 */
1118#define STM32_HSISYSCLK (STM32_HSI16CLK / STM32_HSIDIV_VALUE)
1119
1120/**
1121 * @brief System clock source.
1122 */
1123#if STM32_NO_INIT || defined(__DOXYGEN__)
1124#define STM32_SYSCLK STM32_HSISYSCLK
1125
1126#elif (STM32_SW == STM32_SW_HSISYS)
1127#define STM32_SYSCLK STM32_HSISYSCLK
1128
1129#elif (STM32_SW == STM32_SW_HSE)
1130#define STM32_SYSCLK STM32_HSECLK
1131
1132#elif (STM32_SW == STM32_SW_PLLRCLK)
1133#define STM32_SYSCLK STM32_PLL_R_CLKOUT
1134
1135#elif (STM32_SW == STM32_SW_LSI)
1136#define STM32_SYSCLK STM32_LSICLK
1137
1138#elif (STM32_SW == STM32_SW_LSE)
1139#define STM32_SYSCLK STM32_LSECLK
1140
1141#else
1142#error "invalid STM32_SW value specified"
1143#endif
1144
1145/* Check on the system clock.*/
1146#if STM32_SYSCLK > STM32_SYSCLK_MAX
1147#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
1148#endif
1149
1150/**
1151 * @brief AHB frequency.
1152 */
1153#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
1154#define STM32_HCLK (STM32_SYSCLK / 1)
1155
1156#elif STM32_HPRE == STM32_HPRE_DIV2
1157#define STM32_HCLK (STM32_SYSCLK / 2)
1158
1159#elif STM32_HPRE == STM32_HPRE_DIV4
1160#define STM32_HCLK (STM32_SYSCLK / 4)
1161
1162#elif STM32_HPRE == STM32_HPRE_DIV8
1163#define STM32_HCLK (STM32_SYSCLK / 8)
1164
1165#elif STM32_HPRE == STM32_HPRE_DIV16
1166#define STM32_HCLK (STM32_SYSCLK / 16)
1167
1168#elif STM32_HPRE == STM32_HPRE_DIV64
1169#define STM32_HCLK (STM32_SYSCLK / 64)
1170
1171#elif STM32_HPRE == STM32_HPRE_DIV128
1172#define STM32_HCLK (STM32_SYSCLK / 128)
1173
1174#elif STM32_HPRE == STM32_HPRE_DIV256
1175#define STM32_HCLK (STM32_SYSCLK / 256)
1176
1177#elif STM32_HPRE == STM32_HPRE_DIV512
1178#define STM32_HCLK (STM32_SYSCLK / 512)
1179
1180#else
1181#error "invalid STM32_HPRE value specified"
1182#endif
1183
1184/*
1185 * AHB frequency check.
1186 */
1187#if STM32_HCLK > STM32_SYSCLK_MAX
1188#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
1189#endif
1190
1191/**
1192 * @brief APB frequency.
1193 */
1194#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
1195#define STM32_PCLK (STM32_HCLK / 1)
1196
1197#elif STM32_PPRE == STM32_PPRE_DIV2
1198#define STM32_PCLK (STM32_HCLK / 2)
1199
1200#elif STM32_PPRE == STM32_PPRE_DIV4
1201#define STM32_PCLK (STM32_HCLK / 4)
1202
1203#elif STM32_PPRE == STM32_PPRE_DIV8
1204#define STM32_PCLK (STM32_HCLK / 8)
1205
1206#elif STM32_PPRE == STM32_PPRE_DIV16
1207#define STM32_PCLK (STM32_HCLK / 16)
1208
1209#else
1210#error "invalid STM32_PPRE value specified"
1211#endif
1212
1213/*
1214 * Compatibility definitions.
1215 */
1216#define STM32_PCLK1 STM32_PCLK
1217#define STM32_PCLK2 STM32_PCLK
1218
1219/*
1220 * APB frequency check.
1221 */
1222#if STM32_PCLK > STM32_PCLK_MAX
1223#error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)"
1224#endif
1225
1226/**
1227 * @brief MCO divider clock frequency.
1228 */
1229#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
1230#define STM32_MCODIVCLK 0
1231
1232#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
1233#define STM32_MCODIVCLK STM32_SYSCLK
1234
1235#elif STM32_MCOSEL == STM32_MCOSEL_HSI16
1236#define STM32_MCODIVCLK STM32_HSI16CLK
1237
1238#elif STM32_MCOSEL == STM32_MCOSEL_HSE
1239#define STM32_MCODIVCLK STM32_HSECLK
1240
1241#elif STM32_MCOSEL == STM32_MCOSEL_PLLRCLK
1242#define STM32_MCODIVCLK STM32_PLL_R_CLKOUT
1243
1244#elif STM32_MCOSEL == STM32_MCOSEL_LSI
1245#define STM32_MCODIVCLK STM32_LSICLK
1246
1247#elif STM32_MCOSEL == STM32_MCOSEL_LSE
1248#define STM32_MCODIVCLK STM32_LSECLK
1249
1250#else
1251#error "invalid STM32_MCOSEL value specified"
1252#endif
1253
1254/**
1255 * @brief MCO output pin clock frequency.
1256 */
1257#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
1258#define STM32_MCOCLK STM32_MCODIVCLK
1259
1260#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
1261#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
1262
1263#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
1264#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
1265
1266#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
1267#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
1268
1269#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
1270#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
1271
1272#elif STM32_MCOPRE == STM32_MCOPRE_DIV32
1273#define STM32_MCOCLK (STM32_MCODIVCLK / 32)
1274
1275#elif STM32_MCOPRE == STM32_MCOPRE_DIV64
1276#define STM32_MCOCLK (STM32_MCODIVCLK / 64)
1277
1278#elif STM32_MCOPRE == STM32_MCOPRE_DIV128
1279#define STM32_MCOCLK (STM32_MCODIVCLK / 128)
1280
1281#else
1282#error "invalid STM32_MCOPRE value specified"
1283#endif
1284
1285/**
1286 * @brief RTC clock frequency.
1287 */
1288#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
1289#define STM32_RTCCLK 0
1290
1291#elif STM32_RTCSEL == STM32_RTCSEL_LSE
1292#define STM32_RTCCLK STM32_LSECLK
1293
1294#elif STM32_RTCSEL == STM32_RTCSEL_LSI
1295#define STM32_RTCCLK STM32_LSICLK
1296
1297#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
1298#define STM32_RTCCLK (STM32_HSECLK / 32)
1299
1300#else
1301#error "invalid STM32_RTCSEL value specified"
1302#endif
1303
1304/**
1305 * @brief USART1 clock frequency.
1306 */
1307#if (STM32_USART1SEL == STM32_USART1SEL_PCLK) || defined(__DOXYGEN__)
1308#define STM32_USART1CLK STM32_PCLK
1309#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
1310#define STM32_USART1CLK STM32_SYSCLK
1311#elif STM32_USART1SEL == STM32_USART1SEL_HSI16
1312#define STM32_USART1CLK STM32_HSI16CLK
1313#elif STM32_USART1SEL == STM32_USART1SEL_LSE
1314#define STM32_USART1CLK STM32_LSECLK
1315#else
1316#error "invalid source selected for USART1 clock"
1317#endif
1318
1319/**
1320 * @brief USART2 clock frequency.
1321 */
1322#if (STM32_USART2SEL == STM32_USART2SEL_PCLK) || defined(__DOXYGEN__)
1323#define STM32_USART2CLK STM32_PCLK
1324#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
1325#define STM32_USART2CLK STM32_SYSCLK
1326#elif STM32_USART2SEL == STM32_USART2SEL_HSI16
1327#define STM32_USART2CLK STM32_HSI16CLK
1328#elif STM32_USART2SEL == STM32_USART2SEL_LSE
1329#define STM32_USART2CLK STM32_LSECLK
1330#else
1331#error "invalid source selected for USART2 clock"
1332#endif
1333
1334/**
1335 * @brief USART3 frequency.
1336 */
1337#define STM32_USART3CLK STM32_PCLK
1338
1339/**
1340 * @brief UART4 frequency.
1341 */
1342#define STM32_UART4CLK STM32_PCLK
1343
1344/**
1345 * @brief UART5 frequency.
1346 */
1347#define STM32_UART5CLK STM32_PCLK
1348
1349/**
1350 * @brief LPUART1 clock frequency.
1351 */
1352#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK) || defined(__DOXYGEN__)
1353#define STM32_LPUART1CLK STM32_PCLK
1354#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
1355#define STM32_LPUART1CLK STM32_SYSCLK
1356#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16
1357#define STM32_LPUART1CLK STM32_HSI16CLK
1358#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE
1359#define STM32_LPUART1CLK STM32_LSECLK
1360#else
1361#error "invalid source selected for LPUART1 clock"
1362#endif
1363
1364/**
1365 * @brief CEC clock frequency.
1366 */
1367#if (STM32_CECSEL == STM32_CECSEL_HSI16DIV) || defined(__DOXYGEN__)
1368#define STM32_CECCLK (STM32_HSI16CLK / 448)
1369#elif STM32_CECSEL == STM32_CECSEL_LSE
1370#define STM32_CECCLK STM32_LSECLK
1371#else
1372#error "invalid source selected for CEC clock"
1373#endif
1374
1375/**
1376 * @brief I2C1 clock frequency.
1377 */
1378#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK) || defined(__DOXYGEN__)
1379#define STM32_I2C1CLK STM32_PCLK
1380#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
1381#define STM32_I2C1CLK STM32_SYSCLK
1382#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16
1383#define STM32_I2C1CLK STM32_HSI16CLK
1384#else
1385#error "invalid source selected for I2C1 clock"
1386#endif
1387
1388/**
1389 * @brief I2S1 clock frequency.
1390 */
1391#if (STM32_I2S1SEL == STM32_I2S1SEL_SYSCLK) || defined(__DOXYGEN__)
1392#define STM32_I2S1CLK STM32_SYSCLK
1393#elif STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK
1394#define STM32_I2S1CLK STM32_PLL_P_CLKOUT
1395#elif STM32_I2S1SEL == STM32_I2S1SEL_HSI16
1396#define STM32_I2S1CLK STM32_HSI16CLK
1397#elif STM32_I2S1SEL == STM32_I2S1SEL_CKIN
1398#define STM32_I2S1CLK 0 /* Unknown, would require a board value */
1399#else
1400#error "invalid source selected for I2S1 clock"
1401#endif
1402
1403/**
1404 * @brief LPTIM1 clock frequency.
1405 */
1406#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK) || defined(__DOXYGEN__)
1407#define STM32_LPTIM1CLK STM32_PCLK
1408#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
1409#define STM32_LPTIM1CLK STM32_LSICLK
1410#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16
1411#define STM32_LPTIM1CLK STM32_HSI16CLK
1412#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
1413#define STM32_LPTIM1CLK STM32_LSECLK
1414#else
1415#error "invalid source selected for LPTIM1 clock"
1416#endif
1417
1418/**
1419 * @brief LPTIM2 clock frequency.
1420 */
1421#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK) || defined(__DOXYGEN__)
1422#define STM32_LPTIM2CLK STM32_PCLK
1423#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSI
1424#define STM32_LPTIM2CLK STM32_LSICLK
1425#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16
1426#define STM32_LPTIM2CLK STM32_HSI16CLK
1427#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSE
1428#define STM32_LPTIM2CLK STM32_LSECLK
1429#else
1430#error "invalid source selected for LPTIM2 clock"
1431#endif
1432
1433/**
1434 * @brief RNGDIV field.
1435 */
1436#if (STM32_RNGDIV_VALUE == 1) || defined(__DOXYGEN__)
1437#define STM32_RNGDIV (0U << 28U)
1438#elif STM32_RNGDIV_VALUE == 2
1439#define STM32_RNGDIV (1U << 28U)
1440#elif STM32_RNGDIV_VALUE == 4
1441#define STM32_RNGDIV (2U << 28U)
1442#elif STM32_RNGDIV_VALUE == 8
1443#define STM32_RNGDIV (3U << 28U)
1444#else
1445#error "invalid STM32_RNGDIV_VALUE value specified"
1446#endif
1447
1448/**
1449 * @brief RNG clock frequency.
1450 */
1451#if (STM32_RNGSEL == STM32_RNGSEL_NOCLOCK) || defined(__DOXYGEN__)
1452#define STM32_RNGCLK 0
1453#elif STM32_RNGSEL == STM32_RNGSEL_HSI16
1454#define STM32_RNGCLK (STM32_HSI16CLK / STM32_RNGDIV_VALUE)
1455#elif STM32_RNGSEL == STM32_RNGSEL_SYSCLK
1456#define STM32_RNGCLK (STM32_SYSCLK / STM32_RNGDIV_VALUE)
1457#elif STM32_RNGSEL == STM32_RNGSEL_PLLQCLK
1458#define STM32_RNGCLK (STM32_PLL_Q_CLKOUT / STM32_RNGDIV_VALUE)
1459#else
1460#error "invalid source selected for RNG clock"
1461#endif
1462
1463/**
1464 * @brief ADC clock frequency.
1465 */
1466#if (STM32_ADCSEL == STM32_ADCSEL_SYSCLK) || defined(__DOXYGEN__)
1467#define STM32_ADCCLK STM32_SYSCLK
1468#elif STM32_ADCSEL == STM32_ADCSEL_PLLPCLK
1469#define STM32_ADCCLK STM32_PLL_P_CLKOUT
1470#elif STM32_ADCSEL == STM32_ADCSEL_HSI16
1471#define STM32_ADCCLK STM32_HSI16CLK
1472#else
1473#error "invalid source selected for ADC clock"
1474#endif
1475
1476/**
1477 * @brief TIMPCLK clock frequency.
1478 */
1479#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
1480#define STM32_TIMPCLK (STM32_PCLK * 1)
1481#else
1482#define STM32_TIMPCLK (STM32_PCLK * 2)
1483#endif
1484
1485/**
1486 * @brief TIM1 clock frequency.
1487 */
1488#if (STM32_TIM1SEL == STM32_TIM1SEL_TIMPCLK) || defined(__DOXYGEN__)
1489#define STM32_TIM1CLK STM32_TIMPCLK
1490#elif STM32_TIM1SEL == STM32_TIM1SEL_PLLQCLK
1491#define STM32_TIM1CLK STM32_PLL_Q_CLKOUT
1492#else
1493#error "invalid source selected for TIM1 clock"
1494#endif
1495
1496/**
1497 * @brief TIM15 clock frequency.
1498 */
1499#if (STM32_TIM15SEL == STM32_TIM15SEL_TIMPCLK) || defined(__DOXYGEN__)
1500#define STM32_TIM15CLK STM32_TIMPCLK
1501#elif STM32_TIM15SEL == STM32_TIM15SEL_PLLQCLK
1502#define STM32_TIM15CLK STM32_PLL_Q_CLKOUT
1503#else
1504#error "invalid source selected for TIM15 clock"
1505#endif
1506
1507/**
1508 * @brief Clock of timers connected to APB1.
1509 */
1510#define STM32_TIMCLK1 STM32_TIMPCLK
1511
1512/**
1513 * @brief Clock of timers connected to APB2.
1514 */
1515#define STM32_TIMCLK2 STM32_TIMPCLK
1516
1517/**
1518 * @brief Flash settings.
1519 */
1520#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
1521#define STM32_FLASHBITS 0
1522
1523#elif STM32_HCLK <= STM32_1WS_THRESHOLD
1524#define STM32_FLASHBITS FLASH_ACR_LATENCY_0
1525
1526#elif STM32_HCLK <= STM32_2WS_THRESHOLD
1527#define STM32_FLASHBITS FLASH_ACR_LATENCY_1
1528
1529#else
1530#define STM32_FLASHBITS (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0)
1531#endif
1532
1533/*===========================================================================*/
1534/* Driver data structures and types. */
1535/*===========================================================================*/
1536
1537/*===========================================================================*/
1538/* Driver macros. */
1539/*===========================================================================*/
1540
1541/*===========================================================================*/
1542/* External declarations. */
1543/*===========================================================================*/
1544
1545/* Various helpers.*/
1546#include "nvic.h"
1547#include "cache.h"
1548#include "stm32_isr.h"
1549#include "stm32_dma.h"
1550#include "stm32_exti.h"
1551#include "stm32_rcc.h"
1552#include "stm32_tim.h"
1553
1554#ifdef __cplusplus
1555extern "C" {
1556#endif
1557 void hal_lld_init(void);
1558 void stm32_clock_init(void);
1559#ifdef __cplusplus
1560}
1561#endif
1562
1563#endif /* HAL_LLD_H */
1564
1565/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 05:58:53 +0100