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1/*
2 ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F7xx/stm32_rcc.h
19 * @brief RCC helper driver header.
20 * @note This file requires definitions from the ST header file
21 * @p stm32f7xx.h.
22 *
23 * @addtogroup STM32F7xx_RCC
24 * @{
25 */
26#ifndef STM32_RCC_H
27#define STM32_RCC_H
28
29/*===========================================================================*/
30/* Driver constants. */
31/*===========================================================================*/
32
33/*===========================================================================*/
34/* Driver pre-compile time settings. */
35/*===========================================================================*/
36
37/*===========================================================================*/
38/* Derived constants and error checks. */
39/*===========================================================================*/
40
41/*===========================================================================*/
42/* Driver data structures and types. */
43/*===========================================================================*/
44
45/*===========================================================================*/
46/* Driver macros. */
47/*===========================================================================*/
48
49/**
50 * @name Generic RCC operations
51 * @{
52 */
53/**
54 * @brief Enables the clock of one or more peripheral on the APB1 bus.
55 *
56 * @param[in] mask APB1 peripherals mask, low set
57 * @param[in] lp low power enable flag
58 *
59 * @api
60 */
61#define rccEnableAPB1L(mask, lp) { \
62 RCC->APB1LENR |= (mask); \
63 if (lp) \
64 RCC->APB1LLPENR |= (mask); \
65 else \
66 RCC->APB1LLPENR &= ~(mask); \
67 (void)RCC->APB1LLPENR; \
68}
69
70/**
71 * @brief Enables the clock of one or more peripheral on the APB1 bus.
72 *
73 * @param[in] mask APB1 peripherals mask, high set
74 * @param[in] lp low power enable flag
75 *
76 * @api
77 */
78#define rccEnableAPB1H(mask, lp) { \
79 RCC->APB1HENR |= (mask); \
80 if (lp) \
81 RCC->APB1HLPENR |= (mask); \
82 else \
83 RCC->APB1HLPENR &= ~(mask); \
84 (void)RCC->APB1HLPENR; \
85}
86
87/**
88 * @brief Disables the clock of one or more peripheral on the APB1 bus.
89 *
90 * @param[in] mask APB1 peripherals mask, low set
91 *
92 * @api
93 */
94#define rccDisableAPB1L(mask) { \
95 RCC->APB1LENR &= ~(mask); \
96 RCC->APB1LLPENR &= ~(mask); \
97 (void)RCC->APB1LLPENR; \
98}
99
100/**
101 * @brief Disables the clock of one or more peripheral on the APB1 bus.
102 *
103 * @param[in] mask APB1 peripherals mask, high set
104 *
105 * @api
106 */
107#define rccDisableAPB1H(mask) { \
108 RCC->APB1HENR &= ~(mask); \
109 RCC->APB1HLPENR &= ~(mask); \
110 (void)RCC->APB1HLPENR; \
111}
112
113/**
114 * @brief Resets one or more peripheral on the APB1 bus.
115 *
116 * @param[in] mask APB1 peripherals mask, low set
117 *
118 * @api
119 */
120#define rccResetAPB1L(mask) { \
121 RCC->APB1LRSTR |= (mask); \
122 RCC->APB1LRSTR &= ~(mask); \
123 (void)RCC->APB1LRSTR; \
124}
125
126/**
127 * @brief Resets one or more peripheral on the APB1 bus.
128 *
129 * @param[in] mask APB1 peripherals mask, high set
130 *
131 * @api
132 */
133#define rccResetAPB1H(mask) { \
134 RCC->APB1HRSTR |= (mask); \
135 RCC->APB1HRSTR &= ~(mask); \
136 (void)RCC->APB1HRSTR; \
137}
138
139/**
140 * @brief Enables the clock of one or more peripheral on the APB2 bus.
141 *
142 * @param[in] mask APB2 peripherals mask
143 * @param[in] lp low power enable flag
144 *
145 * @api
146 */
147#define rccEnableAPB2(mask, lp) { \
148 RCC->APB2ENR |= (mask); \
149 if (lp) \
150 RCC->APB2LPENR |= (mask); \
151 else \
152 RCC->APB2LPENR &= ~(mask); \
153 (void)RCC->APB2LPENR; \
154}
155
156/**
157 * @brief Disables the clock of one or more peripheral on the APB2 bus.
158 *
159 * @param[in] mask APB2 peripherals mask
160 *
161 * @api
162 */
163#define rccDisableAPB2(mask) { \
164 RCC->APB2ENR &= ~(mask); \
165 RCC->APB2LPENR &= ~(mask); \
166 (void)RCC->APB2LPENR; \
167}
168
169/**
170 * @brief Resets one or more peripheral on the APB2 bus.
171 *
172 * @param[in] mask APB2 peripherals mask
173 *
174 * @api
175 */
176#define rccResetAPB2(mask) { \
177 RCC->APB2RSTR |= (mask); \
178 RCC->APB2RSTR &= ~(mask); \
179 (void)RCC->APB2RSTR; \
180}
181
182/**
183 * @brief Enables the clock of one or more peripheral on the APB3 bus.
184 *
185 * @param[in] mask APB3 peripherals mask
186 * @param[in] lp low power enable flag
187 *
188 * @api
189 */
190#define rccEnableAPB3(mask, lp) { \
191 RCC->APB3ENR |= (mask); \
192 if (lp) \
193 RCC->APB3LPENR |= (mask); \
194 else \
195 RCC->APB3LPENR &= ~(mask); \
196 (void)RCC->APB3LPENR; \
197}
198
199/**
200 * @brief Disables the clock of one or more peripheral on the APB3 bus.
201 *
202 * @param[in] mask APB3 peripherals mask
203 *
204 * @api
205 */
206#define rccDisableAPB3(mask) { \
207 RCC->APB3ENR &= ~(mask); \
208 RCC->APB3LPENR &= ~(mask); \
209 (void)RCC->APB3LPENR; \
210}
211
212/**
213 * @brief Resets one or more peripheral on the APB3 bus.
214 *
215 * @param[in] mask APB2 peripherals mask
216 *
217 * @api
218 */
219#define rccResetAPB3(mask) { \
220 RCC->APB3RSTR |= (mask); \
221 RCC->APB3RSTR &= ~(mask); \
222 (void)RCC->APB3RSTR; \
223}
224
225/**
226 * @brief Enables the clock of one or more peripheral on the APB4 bus.
227 *
228 * @param[in] mask APB4 peripherals mask
229 * @param[in] lp low power enable flag
230 *
231 * @api
232 */
233#define rccEnableAPB4(mask, lp) { \
234 RCC->APB4ENR |= (mask); \
235 if (lp) \
236 RCC->APB4LPENR |= (mask); \
237 else \
238 RCC->APB4LPENR &= ~(mask); \
239 (void)RCC->APB4LPENR; \
240}
241
242/**
243 * @brief Disables the clock of one or more peripheral on the APB4 bus.
244 *
245 * @param[in] mask APB4 peripherals mask
246 *
247 * @api
248 */
249#define rccDisableAPB4(mask) { \
250 RCC->APB4ENR &= ~(mask); \
251 RCC->APB4LPENR &= ~(mask); \
252 (void)RCC->APB4LPENR; \
253}
254
255/**
256 * @brief Resets one or more peripheral on the APB4 bus.
257 *
258 * @param[in] mask APB4 peripherals mask
259 *
260 * @api
261 */
262#define rccResetAPB4(mask) { \
263 RCC->APB4RSTR |= (mask); \
264 RCC->APB4RSTR &= ~(mask); \
265 (void)RCC->APB4RSTR; \
266}
267
268/**
269 * @brief Enables the clock of one or more peripheral on the AHB1 bus.
270 *
271 * @param[in] mask AHB1 peripherals mask
272 * @param[in] lp low power enable flag
273 *
274 * @api
275 */
276#define rccEnableAHB1(mask, lp) { \
277 RCC->AHB1ENR |= (mask); \
278 if (lp) \
279 RCC->AHB1LPENR |= (mask); \
280 else \
281 RCC->AHB1LPENR &= ~(mask); \
282 (void)RCC->AHB1LPENR; \
283}
284
285/**
286 * @brief Disables the clock of one or more peripheral on the AHB1 bus.
287 *
288 * @param[in] mask AHB1 peripherals mask
289 *
290 * @api
291 */
292#define rccDisableAHB1(mask) { \
293 RCC->AHB1ENR &= ~(mask); \
294 RCC->AHB1LPENR &= ~(mask); \
295 (void)RCC->AHB1LPENR; \
296}
297
298/**
299 * @brief Resets one or more peripheral on the AHB1 bus.
300 *
301 * @param[in] mask AHB1 peripherals mask
302 *
303 * @api
304 */
305#define rccResetAHB1(mask) { \
306 RCC->AHB1RSTR |= (mask); \
307 RCC->AHB1RSTR &= ~(mask); \
308 (void)RCC->AHB1RSTR; \
309}
310
311/**
312 * @brief Enables the clock of one or more peripheral on the AHB2 bus.
313 *
314 * @param[in] mask AHB2 peripherals mask
315 * @param[in] lp low power enable flag
316 *
317 * @api
318 */
319#define rccEnableAHB2(mask, lp) { \
320 RCC->AHB2ENR |= (mask); \
321 if (lp) \
322 RCC->AHB2LPENR |= (mask); \
323 else \
324 RCC->AHB2LPENR &= ~(mask); \
325 (void)RCC->AHB2LPENR; \
326}
327
328/**
329 * @brief Disables the clock of one or more peripheral on the AHB2 bus.
330 *
331 * @param[in] mask AHB2 peripherals mask
332 *
333 * @api
334 */
335#define rccDisableAHB2(mask) { \
336 RCC->AHB2ENR &= ~(mask); \
337 RCC->AHB2LPENR &= ~(mask); \
338 (void)RCC->AHB2LPENR; \
339}
340
341/**
342 * @brief Resets one or more peripheral on the AHB2 bus.
343 *
344 * @param[in] mask AHB2 peripherals mask
345 *
346 * @api
347 */
348#define rccResetAHB2(mask) { \
349 RCC->AHB2RSTR |= (mask); \
350 RCC->AHB2RSTR &= ~(mask); \
351 (void)RCC->AHB2RSTR; \
352}
353
354/**
355 * @brief Enables the clock of one or more peripheral on the AHB3 bus.
356 *
357 * @param[in] mask AHB3 peripherals mask
358 * @param[in] lp low power enable flag
359 *
360 * @api
361 */
362#define rccEnableAHB3(mask, lp) { \
363 RCC->AHB3ENR |= (mask); \
364 if (lp) \
365 RCC->AHB3LPENR |= (mask); \
366 else \
367 RCC->AHB3LPENR &= ~(mask); \
368 (void)RCC->AHB3LPENR; \
369}
370
371/**
372 * @brief Disables the clock of one or more peripheral on the AHB3 bus.
373 *
374 * @param[in] mask AHB3 peripherals mask
375 *
376 * @api
377 */
378#define rccDisableAHB3(mask) { \
379 RCC->AHB3ENR &= ~(mask); \
380 RCC->AHB3LPENR &= ~(mask); \
381 (void)RCC->AHB3LPENR; \
382}
383
384/**
385 * @brief Resets one or more peripheral on the AHB3 bus.
386 *
387 * @param[in] mask AHB3 peripherals mask
388 *
389 * @api
390 */
391#define rccResetAHB3(mask) { \
392 RCC->AHB3RSTR |= (mask); \
393 RCC->AHB3RSTR &= ~(mask); \
394 (void)RCC->AHB3RSTR; \
395}
396
397/**
398 * @brief Enables the clock of one or more peripheral on the AHB4 bus.
399 *
400 * @param[in] mask AHB4 peripherals mask
401 * @param[in] lp low power enable flag
402 *
403 * @api
404 */
405#define rccEnableAHB4(mask, lp) { \
406 RCC->AHB4ENR |= (mask); \
407 if (lp) \
408 RCC->AHB4LPENR |= (mask); \
409 else \
410 RCC->AHB4LPENR &= ~(mask); \
411 (void)RCC->AHB4LPENR; \
412}
413
414/**
415 * @brief Disables the clock of one or more peripheral on the AHB4 bus.
416 *
417 * @param[in] mask AHB4 peripherals mask
418 *
419 * @api
420 */
421#define rccDisableAHB4(mask) { \
422 RCC->AHB4ENR &= ~(mask); \
423 RCC->AHB4LPENR &= ~(mask); \
424 (void)RCC->AHB4LPENR; \
425}
426
427/**
428 * @brief Resets one or more peripheral on the AHB4 bus.
429 *
430 * @param[in] mask AHB4 peripherals mask
431 *
432 * @api
433 */
434#define rccResetAHB4(mask) { \
435 RCC->AHB4RSTR |= (mask); \
436 RCC->AHB4RSTR &= ~(mask); \
437 (void)RCC->AHB4RSTR; \
438}
439/** @} */
440
441/**
442 * @name ADC peripherals specific RCC operations
443 * @{
444 */
445/**
446 * @brief Enables the ADC1/ADC2 peripheral clock.
447 *
448 * @param[in] lp low power enable flag
449 *
450 * @api
451 */
452#define rccEnableADC12(lp) rccEnableAHB1(RCC_AHB1ENR_ADC12EN, lp)
453
454/**
455 * @brief Disables the ADC1/ADC2 peripheral clock.
456 *
457 * @api
458 */
459#define rccDisableADC12() rccDisableAHB1(RCC_AHB1ENR_ADC12EN)
460
461/**
462 * @brief Resets the ADC1/ADC2 peripheral.
463 *
464 * @api
465 */
466#define rccResetADC12() rccResetAHB1(RCC_AHB1RSTR_ADC12RST)
467
468/**
469 * @brief Enables the ADC3 peripheral clock.
470 *
471 * @param[in] lp low power enable flag
472 *
473 * @api
474 */
475#define rccEnableADC3(lp) rccEnableAHB4(RCC_AHB4ENR_ADC3EN, lp)
476
477/**
478 * @brief Disables the ADC3 peripheral clock.
479 *
480 * @api
481 */
482#define rccDisableADC3() rccDisableAHB4(RCC_AHB4ENR_ADC3EN)
483
484/**
485 * @brief Resets the ADC3 peripheral.
486 *
487 * @api
488 */
489#define rccResetADC3() rccResetAHB4(RCC_AHB4RSTR_ADC3RST)
490/** @} */
491
492/**
493 * @name CRC peripheral specific RCC operations
494 * @{
495 */
496/**
497 * @brief Enables the CRC peripheral clock.
498 *
499 * @param[in] lp low power enable flag
500 *
501 * @api
502 */
503#define rccEnableCRC(lp) rccEnableAHB4(RCC_AHB4ENR_CRCEN, lp)
504
505/**
506 * @brief Disables the CRC peripheral clock.
507 *
508 * @api
509 */
510#define rccDisableCRC() rccDisableAHB4(RCC_AHB4ENR_CRCEN)
511
512/**
513 * @brief Resets the CRC peripheral.
514 *
515 * @api
516 */
517#define rccResetCRC() rccResetAHB4(RCC_AHB4RSTR_CRCRST)
518/** @} */
519
520/**
521 * @name CRYP peripheral specific RCC operations
522 * @{
523 */
524/**
525 * @brief Enables the CRYP peripheral clock.
526 *
527 * @param[in] lp low power enable flag
528 *
529 * @api
530 */
531#define rccEnableCRYP(lp) rccEnableAHB2(RCC_AHB2ENR_CRYPEN, lp)
532
533/**
534 * @brief Disables the CRYP peripheral clock.
535 *
536 * @api
537 */
538#define rccDisableCRYP() rccDisableAHB2(RCC_AHB2ENR_CRYPEN)
539
540/**
541 * @brief Resets the CRYP peripheral.
542 *
543 * @api
544 */
545#define rccResetCRYP() rccResetAHB2(RCC_AHB2RSTR_CRYPRST)
546/** @} */
547
548/**
549 * @name HASH peripheral specific RCC operations
550 * @{
551 */
552/**
553 * @brief Enables the HASH peripheral clock.
554 *
555 * @param[in] lp low power enable flag
556 *
557 * @api
558 */
559#define rccEnableHASH(lp) rccEnableAHB2(RCC_AHB2ENR_HASHEN, lp)
560
561/**
562 * @brief Disables the HASH peripheral clock.
563 *
564 * @api
565 */
566#define rccDisableHASH() rccDisableAHB2(RCC_AHB2ENR_HASHEN)
567
568/**
569 * @brief Resets the HASH peripheral.
570 *
571 * @api
572 */
573#define rccResetHASH() rccResetAHB2(RCC_AHB2RSTR_HASHRST)
574/** @} */
575
576/**
577 * @name DAC peripheral specific RCC operations
578 * @{
579 */
580/**
581 * @brief Enables the DAC1 peripheral clock.
582 *
583 * @param[in] lp low power enable flag
584 *
585 * @api
586 */
587#define rccEnableDAC1(lp) rccEnableAPB1L(RCC_APB1LENR_DAC12EN, lp)
588
589/**
590 * @brief Disables the DAC1 peripheral clock.
591 *
592 * @api
593 */
594#define rccDisableDAC1() rccDisableAPB1L(RCC_APB1LENR_DAC12EN)
595
596/**
597 * @brief Resets the DAC1 peripheral.
598 *
599 * @api
600 */
601#define rccResetDAC1() rccResetAPB1L(RCC_APB1LRSTR_DAC12RST)
602/** @} */
603
604/**
605 * @name DMA peripheral specific RCC operations
606 * @{
607 */
608/**
609 * @brief Enables the BDMA1 peripheral clock.
610 *
611 * @param[in] lp low power enable flag
612 *
613 * @api
614 */
615#define rccEnableBDMA1(lp) rccEnableAHB4(RCC_AHB4ENR_BDMAEN, lp)
616
617/**
618 * @brief Disables the BDMA1 peripheral clock.
619 *
620 * @api
621 */
622#define rccDisableBDMA1() rccDisableAHB4(RCC_AHB4ENR_BDMAEN)
623
624/**
625 * @brief Resets the BDMA1 peripheral.
626 *
627 * @api
628 */
629#define rccResetBDMA1() rccResetAHB4(RCC_AHB4RSTR_BDMARST)
630
631/**
632 * @brief Enables the DMA1 peripheral clock.
633 *
634 * @param[in] lp low power enable flag
635 *
636 * @api
637 */
638#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
639
640/**
641 * @brief Disables the DMA1 peripheral clock.
642 *
643 * @api
644 */
645#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN)
646
647/**
648 * @brief Resets the DMA1 peripheral.
649 *
650 * @api
651 */
652#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
653
654/**
655 * @brief Enables the DMA2 peripheral clock.
656 *
657 * @param[in] lp low power enable flag
658 *
659 * @api
660 */
661#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
662
663/**
664 * @brief Disables the DMA2 peripheral clock.
665 *
666 * @api
667 */
668#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN)
669
670/**
671 * @brief Resets the DMA2 peripheral.
672 *
673 * @api
674 */
675#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
676
677/**
678 * @brief Enables the MDMA peripheral clock.
679 *
680 * @param[in] lp low power enable flag
681 *
682 * @api
683 */
684#define rccEnableMDMA(lp) rccEnableAHB3(RCC_AHB3ENR_MDMAEN, lp)
685
686/**
687 * @brief Disables the MDMA peripheral clock.
688 *
689 * @api
690 */
691#define rccDisableMDMA() rccDisableAHB3(RCC_AHB3ENR_MDMAEN)
692
693/**
694 * @brief Resets the MDMA peripheral.
695 *
696 * @api
697 */
698#define rccResetMDMA() rccResetAHB3(RCC_AHB3ENR_MDMARST)
699/** @} */
700
701/**
702 * @name RAM specific RCC operations
703 * @{
704 */
705/**
706 * @brief Enables the BKPRAM clock.
707 *
708 * @param[in] lp low power enable flag
709 *
710 * @api
711 */
712#define rccEnableBKPRAM(lp) rccEnableAHB4(RCC_AHB4ENR_BKPRAMEN, lp)
713
714/**
715 * @brief Disables the BKPRAM clock.
716 *
717 * @api
718 */
719#define rccDisableBKPRAM() rccDisableAHB4(RCC_AHB4ENR_BKPRAMEN)
720
721/**
722 * @brief Enables the SRAM1 clock.
723 *
724 * @param[in] lp low power enable flag
725 *
726 * @api
727 */
728#define rccEnableSRAM1(lp) rccEnableAHB2(RCC_AHB2ENR_D2SRAM1EN, lp)
729
730/**
731 * @brief Disables the SRAM1 clock.
732 *
733 * @api
734 */
735#define rccDisableSRAM1() rccDisableAHB2(RCC_AHB2ENR_D2SRAM1EN)
736
737/**
738 * @brief Enables the SRAM2 clock.
739 *
740 * @param[in] lp low power enable flag
741 *
742 * @api
743 */
744#define rccEnableSRAM2(lp) rccEnableAHB2(RCC_AHB2ENR_D2SRAM2EN, lp)
745
746/**
747 * @brief Disables the SRAM2 clock.
748 *
749 * @api
750 */
751#define rccDisableSRAM2() rccDisableAHB2(RCC_AHB2ENR_D2SRAM2EN)
752
753/**
754 * @brief Enables the SRAM3 clock.
755 *
756 * @param[in] lp low power enable flag
757 *
758 * @api
759 */
760#define rccEnableSRAM3(lp) rccEnableAHB2(RCC_AHB2ENR_D2SRAM3EN, lp)
761
762/**
763 * @brief Disables the SRAM3 clock.
764 *
765 * @api
766 */
767#define rccDisableSRAM3() rccDisableAHB2(RCC_AHB2ENR_D2SRAM3EN)
768/** @} */
769
770/**
771 * @name ETH peripheral specific RCC operations
772 * @{
773 */
774/**
775 * @brief Enables the ETH peripheral clock.
776 *
777 * @param[in] lp low power enable flag
778 *
779 * @api
780 */
781#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETH1MACEN | \
782 RCC_AHB1ENR_ETH1TXEN | \
783 RCC_AHB1ENR_ETH1RXEN, lp)
784
785/**
786 * @brief Disables the ETH peripheral clock.
787 *
788 * @api
789 */
790#define rccDisableETH() rccDisableAHB1(RCC_AHB1ENR_ETH1MACEN | \
791 RCC_AHB1ENR_ETH1TXEN | \
792 RCC_AHB1ENR_ETH1RXEN)
793
794/**
795 * @brief Resets the ETH peripheral.
796 *
797 * @api
798 */
799#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETH1MACRST)
800/** @} */
801
802/**
803 * @name FDCAN peripherals specific RCC operations
804 * @{
805 */
806/**
807 * @brief Enables the FDCAN peripheral clock.
808 *
809 * @param[in] lp low power enable flag
810 *
811 * @api
812 */
813#define rccEnableFDCAN(lp) rccEnableAPB1H(RCC_APB1HENR_FDCANEN, lp)
814
815/**
816 * @brief Disables the FDCAN peripheral clock.
817 *
818 * @api
819 */
820#define rccDisableFDCAN() rccDisableAPB1H(RCC_APB1HENR_FDCANEN)
821
822/**
823 * @brief Resets the FDCAN peripheral.
824 *
825 * @api
826 */
827#define rccResetFDCAN() rccResetAPB1H(RCC_APB1HRSTR_FDCANRST)
828/** @} */
829
830/**
831 * @name I2C peripherals specific RCC operations
832 * @{
833 */
834/**
835 * @brief Enables the I2C1 peripheral clock.
836 *
837 * @param[in] lp low power enable flag
838 *
839 * @api
840 */
841#define rccEnableI2C1(lp) rccEnableAPB1L(RCC_APB1LENR_I2C1EN, lp)
842
843/**
844 * @brief Disables the I2C1 peripheral clock.
845 *
846 * @api
847 */
848#define rccDisableI2C1() rccDisableAPB1L(RCC_APB1LENR_I2C1EN)
849
850/**
851 * @brief Resets the I2C1 peripheral.
852 *
853 * @api
854 */
855#define rccResetI2C1() rccResetAPB1L(RCC_APB1LRSTR_I2C1RST)
856
857/**
858 * @brief Enables the I2C2 peripheral clock.
859 *
860 * @param[in] lp low power enable flag
861 *
862 * @api
863 */
864#define rccEnableI2C2(lp) rccEnableAPB1L(RCC_APB1LENR_I2C2EN, lp)
865
866/**
867 * @brief Disables the I2C2 peripheral clock.
868 *
869 * @api
870 */
871#define rccDisableI2C2() rccDisableAPB1L(RCC_APB1LENR_I2C2EN)
872
873/**
874 * @brief Resets the I2C2 peripheral.
875 *
876 * @api
877 */
878#define rccResetI2C2() rccResetAPB1L(RCC_APB1LRSTR_I2C2RST)
879
880/**
881 * @brief Enables the I2C3 peripheral clock.
882 *
883 * @param[in] lp low power enable flag
884 *
885 * @api
886 */
887#define rccEnableI2C3(lp) rccEnableAPB1L(RCC_APB1LENR_I2C3EN, lp)
888
889/**
890 * @brief Disables the I2C3 peripheral clock.
891 *
892 * @api
893 */
894#define rccDisableI2C3() rccDisableAPB1L(RCC_APB1LENR_I2C3EN)
895
896/**
897 * @brief Resets the I2C3 peripheral.
898 *
899 * @api
900 */
901#define rccResetI2C3() rccResetAPB1L(RCC_APB1LRSTR_I2C3RST)
902
903/**
904 * @brief Enables the I2C4 peripheral clock.
905 *
906 * @param[in] lp low power enable flag
907 *
908 * @api
909 */
910#define rccEnableI2C4(lp) rccEnableAPB4(RCC_APB4ENR_I2C4EN, lp)
911
912/**
913 * @brief Disables the I2C4 peripheral clock.
914 *
915 * @api
916 */
917#define rccDisableI2C4() rccDisableAPB4(RCC_APB4ENR_I2C4EN)
918
919/**
920 * @brief Resets the I2C4 peripheral.
921 *
922 * @api
923 */
924#define rccResetI2C4() rccResetAPB4(RCC_APB4RSTR_I2C4RST)
925/** @} */
926
927/**
928 * @name OTG peripherals specific RCC operations
929 * @{
930 */
931/**
932 * @brief Enables the USB1_OTG_HS peripheral clock.
933 *
934 * @param[in] lp low power enable flag
935 *
936 * @api
937 */
938#define rccEnableUSB1_OTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_USB1OTGHSEN, lp)
939
940/**
941 * @brief Disables the USB1_OTG_HS peripheral clock.
942 *
943 * @api
944 */
945#define rccDisableUSB1_OTG_HS() rccDisableAHB1(RCC_AHB1ENR_USB1OTGHSEN)
946
947/**
948 * @brief Resets the USB1_OTG_HS peripheral.
949 *
950 * @api
951 */
952#define rccResetUSB1_OTG_HS() rccResetAHB1(RCC_AHB1RSTR_USB1OTGHSRST)
953
954/**
955 * @brief Enables the USB1_OTG_HS ULPI peripheral clock.
956 *
957 * @param[in] lp low power enable flag
958 *
959 * @api
960 */
961#define rccEnableUSB1_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_USB1OTGHSULPIEN, lp)
962
963/**
964 * @brief Disables the USB1_OTG_HS peripheral clock.
965 *
966 * @api
967 */
968#define rccDisableUSB1_HSULPI() rccDisableAHB1(RCC_AHB1ENR_USB1OTGHSULPIEN)
969
970/**
971 * @brief Enables the USB2_OTG_FS peripheral clock.
972 *
973 * @param[in] lp low power enable flag
974 *
975 * @api
976 */
977#define rccEnableUSB2_OTG_FS(lp) rccEnableAHB1(RCC_AHB1ENR_USB2OTGFSEN, lp)
978
979/**
980 * @brief Disables the USB2_OTG_FS peripheral clock.
981 *
982 * @api
983 */
984#define rccDisableUSB2_OTG_FS() rccDisableAHB1(RCC_AHB1ENR_USB2OTGFSEN)
985
986/**
987 * @brief Resets the USB2_OTG_FS peripheral.
988 *
989 * @api
990 */
991#define rccResetUSB2_OTG_FS() rccResetAHB1(RCC_AHB1RSTR_USB2OTGFSRST)
992
993/**
994 * @brief Enables the USB2_OTG_HS ULPI peripheral clock.
995 *
996 * @param[in] lp low power enable flag
997 *
998 * @api
999 */
1000#define rccEnableUSB2_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_USB2OTGHSULPIEN, lp)
1001
1002/**
1003 * @brief Disables the USB2_OTG_HS peripheral clock.
1004 *
1005 * @api
1006 */
1007#define rccDisableUSB2_HSULPI() rccDisableAHB1(RCC_AHB1ENR_USB2OTGHSULPIEN)
1008/** @} */
1009
1010/**
1011 * @name QUADSPI peripherals specific RCC operations
1012 * @{
1013 */
1014/**
1015 * @brief Enables the QUADSPI1 peripheral clock.
1016 *
1017 * @param[in] lp low power enable flag
1018 *
1019 * @api
1020 */
1021#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
1022
1023/**
1024 * @brief Disables the QUADSPI1 peripheral clock.
1025 *
1026 * @api
1027 */
1028#define rccDisableQUADSPI1() rccDisableAHB3(RCC_AHB3ENR_QSPIEN)
1029
1030/**
1031 * @brief Resets the QUADSPI1 peripheral.
1032 *
1033 * @api
1034 */
1035#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
1036/** @} */
1037
1038/**
1039 * @name RNG peripherals specific RCC operations
1040 * @{
1041 */
1042/**
1043 * @brief Enables the RNG peripheral clock.
1044 *
1045 * @param[in] lp low power enable flag
1046 *
1047 * @api
1048 */
1049#define rccEnableRNG(lp) rccEnableAHB2(RCC_AHB2ENR_RNGEN, lp)
1050
1051/**
1052 * @brief Disables the RNG peripheral clock.
1053 *
1054 * @api
1055 */
1056#define rccDisableRNG() rccDisableAHB2(RCC_AHB2ENR_RNGEN)
1057
1058/**
1059 * @brief Resets the RNG peripheral.
1060 *
1061 * @api
1062 */
1063#define rccResetRNG() rccResetAHB2(RCC_AHB2RSTR_RNGRST)
1064/** @} */
1065
1066/**
1067 * @name SDMMC peripheral specific RCC operations
1068 * @{
1069 */
1070/**
1071 * @brief Enables the SDMMC1 peripheral clock.
1072 *
1073 * @param[in] lp low power enable flag
1074 *
1075 * @api
1076 */
1077#define rccEnableSDMMC1(lp) rccEnableAHB3(RCC_AHB3ENR_SDMMC1EN, lp)
1078
1079/**
1080 * @brief Disables the SDMMC1 peripheral clock.
1081 *
1082 * @api
1083 */
1084#define rccDisableSDMMC1() rccDisableAHB3(RCC_AHB3ENR_SDMMC1EN)
1085
1086/**
1087 * @brief Resets the SDMMC1 peripheral.
1088 *
1089 * @api
1090 */
1091#define rccResetSDMMC1() rccResetAHB3(RCC_AHB3RSTR_SDMMC1RST)
1092
1093/**
1094 * @brief Enables the SDMMC2 peripheral clock.
1095 *
1096 * @param[in] lp low power enable flag
1097 *
1098 * @api
1099 */
1100#define rccEnableSDMMC2(lp) rccEnableAHB2(RCC_AHB2ENR_SDMMC2EN, lp)
1101
1102/**
1103 * @brief Disables the SDMMC2 peripheral clock.
1104 *
1105 * @api
1106 */
1107#define rccDisableSDMMC2() rccDisableAHB2(RCC_AHB2ENR_SDMMC2EN)
1108
1109/**
1110 * @brief Resets the SDMMC2 peripheral.
1111 *
1112 * @api
1113 */
1114#define rccResetSDMMC2() rccResetAHB2(RCC_AHB2RSTR_SDMMC2RST)
1115/** @} */
1116
1117/**
1118 * @name SPI peripherals specific RCC operations
1119 * @{
1120 */
1121/**
1122 * @brief Enables the SPI1 peripheral clock.
1123 *
1124 * @param[in] lp low power enable flag
1125 *
1126 * @api
1127 */
1128#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
1129
1130/**
1131 * @brief Disables the SPI1 peripheral clock.
1132 *
1133 * @api
1134 */
1135#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
1136
1137/**
1138 * @brief Resets the SPI1 peripheral.
1139 *
1140 * @api
1141 */
1142#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
1143
1144/**
1145 * @brief Enables the SPI2 peripheral clock.
1146 *
1147 * @param[in] lp low power enable flag
1148 *
1149 * @api
1150 */
1151#define rccEnableSPI2(lp) rccEnableAPB1L(RCC_APB1LENR_SPI2EN, lp)
1152
1153/**
1154 * @brief Disables the SPI2 peripheral clock.
1155 *
1156 * @api
1157 */
1158#define rccDisableSPI2() rccDisableAPB1L(RCC_APB1LENR_SPI2EN)
1159
1160/**
1161 * @brief Resets the SPI2 peripheral.
1162 *
1163 * @api
1164 */
1165#define rccResetSPI2() rccResetAPB1L(RCC_APB1LRSTR_SPI2RST)
1166
1167/**
1168 * @brief Enables the SPI3 peripheral clock.
1169 *
1170 * @param[in] lp low power enable flag
1171 *
1172 * @api
1173 */
1174#define rccEnableSPI3(lp) rccEnableAPB1L(RCC_APB1LENR_SPI3EN, lp)
1175
1176/**
1177 * @brief Disables the SPI3 peripheral clock.
1178 *
1179 * @api
1180 */
1181#define rccDisableSPI3() rccDisableAPB1L(RCC_APB1LENR_SPI3EN)
1182
1183/**
1184 * @brief Resets the SPI3 peripheral.
1185 *
1186 * @api
1187 */
1188#define rccResetSPI3() rccResetAPB1L(RCC_APB1LRSTR_SPI3RST)
1189
1190/**
1191 * @brief Enables the SPI4 peripheral clock.
1192 *
1193 * @param[in] lp low power enable flag
1194 *
1195 * @api
1196 */
1197#define rccEnableSPI4(lp) rccEnableAPB2(RCC_APB2ENR_SPI4EN, lp)
1198
1199/**
1200 * @brief Disables the SPI4 peripheral clock.
1201 *
1202 * @api
1203 */
1204#define rccDisableSPI4() rccDisableAPB2(RCC_APB2ENR_SPI4EN)
1205
1206/**
1207 * @brief Resets the SPI4 peripheral.
1208 *
1209 * @api
1210 */
1211#define rccResetSPI4() rccResetAPB2(RCC_APB2RSTR_SPI4RST)
1212
1213/**
1214 * @brief Enables the SPI5 peripheral clock.
1215 *
1216 * @param[in] lp low power enable flag
1217 *
1218 * @api
1219 */
1220#define rccEnableSPI5(lp) rccEnableAPB2(RCC_APB2ENR_SPI5EN, lp)
1221
1222/**
1223 * @brief Disables the SPI5 peripheral clock.
1224 *
1225 * @api
1226 */
1227#define rccDisableSPI5() rccDisableAPB2(RCC_APB2ENR_SPI5EN)
1228
1229/**
1230 * @brief Resets the SPI5 peripheral.
1231 *
1232 * @api
1233 */
1234#define rccResetSPI5() rccResetAPB2(RCC_APB2RSTR_SPI5RST)
1235
1236/**
1237 * @brief Enables the SPI6 peripheral clock.
1238 *
1239 * @param[in] lp low power enable flag
1240 *
1241 * @api
1242 */
1243#define rccEnableSPI6(lp) rccEnableAPB4(RCC_APB4ENR_SPI6EN, lp)
1244
1245/**
1246 * @brief Disables the SPI6 peripheral clock.
1247 *
1248 * @api
1249 */
1250#define rccDisableSPI6() rccDisableAPB4(RCC_APB4ENR_SPI6EN)
1251
1252/**
1253 * @brief Resets the SPI6 peripheral.
1254 *
1255 * @api
1256 */
1257#define rccResetSPI6() rccResetAPB4(RCC_APB4RSTR_SPI6RST)
1258/** @} */
1259
1260/**
1261 * @name TIM peripherals specific RCC operations
1262 * @{
1263 */
1264/**
1265 * @brief Enables the TIM1 peripheral clock.
1266 *
1267 * @param[in] lp low power enable flag
1268 *
1269 * @api
1270 */
1271#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
1272
1273/**
1274 * @brief Disables the TIM1 peripheral clock.
1275 *
1276 * @api
1277 */
1278#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
1279
1280/**
1281 * @brief Resets the TIM1 peripheral.
1282 *
1283 * @api
1284 */
1285#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
1286
1287/**
1288 * @brief Enables the TIM2 peripheral clock.
1289 *
1290 * @param[in] lp low power enable flag
1291 *
1292 * @api
1293 */
1294#define rccEnableTIM2(lp) rccEnableAPB1L(RCC_APB1LENR_TIM2EN, lp)
1295
1296/**
1297 * @brief Disables the TIM2 peripheral clock.
1298 *
1299 * @api
1300 */
1301#define rccDisableTIM2() rccDisableAPB1L(RCC_APB1LENR_TIM2EN)
1302
1303/**
1304 * @brief Resets the TIM2 peripheral.
1305 *
1306 * @api
1307 */
1308#define rccResetTIM2() rccResetAPB1L(RCC_APB1LRSTR_TIM2RST)
1309
1310/**
1311 * @brief Enables the TIM3 peripheral clock.
1312 *
1313 * @param[in] lp low power enable flag
1314 *
1315 * @api
1316 */
1317#define rccEnableTIM3(lp) rccEnableAPB1L(RCC_APB1LENR_TIM3EN, lp)
1318
1319/**
1320 * @brief Disables the TIM3 peripheral clock.
1321 *
1322 * @api
1323 */
1324#define rccDisableTIM3() rccDisableAPB1L(RCC_APB1LENR_TIM3EN)
1325
1326/**
1327 * @brief Resets the TIM3 peripheral.
1328 *
1329 * @api
1330 */
1331#define rccResetTIM3() rccResetAPB1L(RCC_APB1LRSTR_TIM3RST)
1332
1333/**
1334 * @brief Enables the TIM4 peripheral clock.
1335 *
1336 * @param[in] lp low power enable flag
1337 *
1338 * @api
1339 */
1340#define rccEnableTIM4(lp) rccEnableAPB1L(RCC_APB1LENR_TIM4EN, lp)
1341
1342/**
1343 * @brief Disables the TIM4 peripheral clock.
1344 *
1345 * @api
1346 */
1347#define rccDisableTIM4() rccDisableAPB1L(RCC_APB1LENR_TIM4EN)
1348
1349/**
1350 * @brief Resets the TIM4 peripheral.
1351 *
1352 * @api
1353 */
1354#define rccResetTIM4() rccResetAPB1L(RCC_APB1LRSTR_TIM4RST)
1355
1356/**
1357 * @brief Enables the TIM5 peripheral clock.
1358 *
1359 * @param[in] lp low power enable flag
1360 *
1361 * @api
1362 */
1363#define rccEnableTIM5(lp) rccEnableAPB1L(RCC_APB1LENR_TIM5EN, lp)
1364
1365/**
1366 * @brief Disables the TIM5 peripheral clock.
1367 *
1368 * @api
1369 */
1370#define rccDisableTIM5() rccDisableAPB1L(RCC_APB1LENR_TIM5EN)
1371
1372/**
1373 * @brief Resets the TIM5 peripheral.
1374 *
1375 * @api
1376 */
1377#define rccResetTIM5() rccResetAPB1L(RCC_APB1LRSTR_TIM5RST)
1378
1379/**
1380 * @brief Enables the TIM6 peripheral clock.
1381 *
1382 * @param[in] lp low power enable flag
1383 *
1384 * @api
1385 */
1386#define rccEnableTIM6(lp) rccEnableAPB1L(RCC_APB1LENR_TIM6EN, lp)
1387
1388/**
1389 * @brief Disables the TIM6 peripheral clock.
1390 *
1391 * @api
1392 */
1393#define rccDisableTIM6() rccDisableAPB1L(RCC_APB1LENR_TIM6EN)
1394
1395/**
1396 * @brief Resets the TIM6 peripheral.
1397 *
1398 * @api
1399 */
1400#define rccResetTIM6() rccResetAPB1L(RCC_APB1LRSTR_TIM6RST)
1401
1402/**
1403 * @brief Enables the TIM7 peripheral clock.
1404 *
1405 * @param[in] lp low power enable flag
1406 *
1407 * @api
1408 */
1409#define rccEnableTIM7(lp) rccEnableAPB1L(RCC_APB1LENR_TIM7EN, lp)
1410
1411/**
1412 * @brief Disables the TIM7 peripheral clock.
1413 *
1414 * @api
1415 */
1416#define rccDisableTIM7() rccDisableAPB1L(RCC_APB1LENR_TIM7EN)
1417
1418/**
1419 * @brief Resets the TIM7 peripheral.
1420 *
1421 * @api
1422 */
1423#define rccResetTIM7() rccResetAPB1L(RCC_APB1LRSTR_TIM7RST)
1424
1425/**
1426 * @brief Enables the TIM8 peripheral clock.
1427 *
1428 * @param[in] lp low power enable flag
1429 *
1430 * @api
1431 */
1432#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
1433
1434/**
1435 * @brief Disables the TIM8 peripheral clock.
1436 *
1437 * @api
1438 */
1439#define rccDisableTIM8() rccDisableAPB2(RCC_APB2ENR_TIM8EN)
1440
1441/**
1442 * @brief Resets the TIM8 peripheral.
1443 *
1444 * @api
1445 */
1446#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
1447
1448/**
1449 * @brief Enables the TIM12 peripheral clock.
1450 *
1451 * @param[in] lp low power enable flag
1452 *
1453 * @api
1454 */
1455#define rccEnableTIM12(lp) rccEnableAPB1L(RCC_APB1LENR_TIM12EN, lp)
1456
1457/**
1458 * @brief Disables the TIM12 peripheral clock.
1459 *
1460 * @api
1461 */
1462#define rccDisableTIM12() rccDisableAPB1L(RCC_APB1LENR_TIM12EN)
1463
1464/**
1465 * @brief Resets the TIM12 peripheral.
1466 *
1467 * @api
1468 */
1469#define rccResetTIM12() rccResetAPB1L(RCC_APB1LRSTR_TIM12RST)
1470
1471/**
1472 * @brief Enables the TIM13 peripheral clock.
1473 *
1474 * @param[in] lp low power enable flag
1475 *
1476 * @api
1477 */
1478#define rccEnableTIM13(lp) rccEnableAPB1L(RCC_APB1LENR_TIM13EN, lp)
1479
1480/**
1481 * @brief Disables the TIM13 peripheral clock.
1482 *
1483 * @api
1484 */
1485#define rccDisableTIM13() rccDisableAPB1L(RCC_APB1LENR_TIM13EN)
1486
1487/**
1488 * @brief Resets the TIM13 peripheral.
1489 *
1490 * @api
1491 */
1492#define rccResetTIM13() rccResetAPB1L(RCC_APB1LRSTR_TIM13RST)
1493
1494/**
1495 * @brief Enables the TIM14 peripheral clock.
1496 *
1497 * @param[in] lp low power enable flag
1498 *
1499 * @api
1500 */
1501#define rccEnableTIM14(lp) rccEnableAPB1L(RCC_APB1LENR_TIM14EN, lp)
1502
1503/**
1504 * @brief Disables the TIM14 peripheral clock.
1505 *
1506 * @api
1507 */
1508#define rccDisableTIM14() rccDisableAPB1L(RCC_APB1LENR_TIM14EN)
1509
1510/**
1511 * @brief Resets the TIM14 peripheral.
1512 *
1513 * @api
1514 */
1515#define rccResetTIM14() rccResetAPB1L(RCC_APB1LRSTR_TIM14RST)
1516
1517/**
1518 * @brief Enables the TIM15 peripheral clock.
1519 *
1520 * @param[in] lp low power enable flag
1521 *
1522 * @api
1523 */
1524#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
1525
1526/**
1527 * @brief Disables the TIM15 peripheral clock.
1528 *
1529 * @api
1530 */
1531#define rccDisableTIM15() rccDisableAPB2(RCC_APB2ENR_TIM15EN)
1532
1533/**
1534 * @brief Resets the TIM15 peripheral.
1535 *
1536 * @api
1537 */
1538#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
1539
1540/**
1541 * @brief Enables the TIM16 peripheral clock.
1542 *
1543 * @param[in] lp low power enable flag
1544 *
1545 * @api
1546 */
1547#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
1548
1549/**
1550 * @brief Disables the TIM16 peripheral clock.
1551 *
1552 * @api
1553 */
1554#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN)
1555
1556/**
1557 * @brief Resets the TIM16 peripheral.
1558 *
1559 * @api
1560 */
1561#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
1562
1563/**
1564 * @brief Enables the TIM17 peripheral clock.
1565 *
1566 * @param[in] lp low power enable flag
1567 *
1568 * @api
1569 */
1570#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
1571
1572/**
1573 * @brief Disables the TIM17 peripheral clock.
1574 *
1575 * @api
1576 */
1577#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN)
1578
1579/**
1580 * @brief Resets the TIM17 peripheral.
1581 *
1582 * @api
1583 */
1584#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
1585/** @} */
1586
1587/**
1588 * @name USART/UART peripherals specific RCC operations
1589 * @{
1590 */
1591/**
1592 * @brief Enables the USART1 peripheral clock.
1593 *
1594 * @param[in] lp low power enable flag
1595 *
1596 * @api
1597 */
1598#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
1599
1600/**
1601 * @brief Disables the USART1 peripheral clock.
1602 *
1603 * @api
1604 */
1605#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
1606
1607/**
1608 * @brief Resets the USART1 peripheral.
1609 *
1610 * @api
1611 */
1612#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
1613
1614/**
1615 * @brief Enables the USART2 peripheral clock.
1616 *
1617 * @param[in] lp low power enable flag
1618 *
1619 * @api
1620 */
1621#define rccEnableUSART2(lp) rccEnableAPB1L(RCC_APB1LENR_USART2EN, lp)
1622
1623/**
1624 * @brief Disables the USART2 peripheral clock.
1625 *
1626 * @api
1627 */
1628#define rccDisableUSART2() rccDisableAPB1L(RCC_APB1LENR_USART2EN)
1629
1630/**
1631 * @brief Resets the USART2 peripheral.
1632 *
1633 * @api
1634 */
1635#define rccResetUSART2() rccResetAPB1L(RCC_APB1LRSTR_USART2RST)
1636
1637/**
1638 * @brief Enables the USART3 peripheral clock.
1639 *
1640 * @param[in] lp low power enable flag
1641 *
1642 * @api
1643 */
1644#define rccEnableUSART3(lp) rccEnableAPB1L(RCC_APB1LENR_USART3EN, lp)
1645
1646/**
1647 * @brief Disables the USART3 peripheral clock.
1648 *
1649 * @api
1650 */
1651#define rccDisableUSART3() rccDisableAPB1L(RCC_APB1LENR_USART3EN)
1652
1653/**
1654 * @brief Resets the USART3 peripheral.
1655 *
1656 * @api
1657 */
1658#define rccResetUSART3() rccResetAPB1L(RCC_APB1LRSTR_USART3RST)
1659
1660/**
1661 * @brief Enables the UART4 peripheral clock.
1662 *
1663 * @param[in] lp low power enable flag
1664 *
1665 * @api
1666 */
1667#define rccEnableUART4(lp) rccEnableAPB1L(RCC_APB1LENR_UART4EN, lp)
1668
1669/**
1670 * @brief Disables the UART4 peripheral clock.
1671 *
1672 * @api
1673 */
1674#define rccDisableUART4() rccDisableAPB1L(RCC_APB1LENR_UART4EN)
1675
1676/**
1677 * @brief Resets the UART4 peripheral.
1678 *
1679 * @api
1680 */
1681#define rccResetUART4() rccResetAPB1L(RCC_APB1LRSTR_UART4RST)
1682
1683/**
1684 * @brief Enables the UART5 peripheral clock.
1685 *
1686 * @param[in] lp low power enable flag
1687 *
1688 * @api
1689 */
1690#define rccEnableUART5(lp) rccEnableAPB1L(RCC_APB1LENR_UART5EN, lp)
1691
1692/**
1693 * @brief Disables the UART5 peripheral clock.
1694 *
1695 * @api
1696 */
1697#define rccDisableUART5() rccDisableAPB1L(RCC_APB1LENR_UART5EN)
1698
1699/**
1700 * @brief Resets the UART5 peripheral.
1701 *
1702 * @api
1703 */
1704#define rccResetUART5() rccResetAPB1L(RCC_APB1LRSTR_UART5RST)
1705
1706/**
1707 * @brief Enables the USART6 peripheral clock.
1708 *
1709 * @param[in] lp low power enable flag
1710 *
1711 * @api
1712 */
1713#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)
1714
1715/**
1716 * @brief Disables the USART6 peripheral clock.
1717 *
1718 * @api
1719 */
1720#define rccDisableUSART6() rccDisableAPB2(RCC_APB2ENR_USART6EN)
1721
1722/**
1723 * @brief Resets the USART6 peripheral.
1724 *
1725 * @api
1726 */
1727#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST)
1728
1729/**
1730 * @brief Enables the UART7 peripheral clock.
1731 *
1732 * @param[in] lp low power enable flag
1733 *
1734 * @api
1735 */
1736#define rccEnableUART7(lp) rccEnableAPB1L(RCC_APB1LENR_UART7EN, lp)
1737
1738/**
1739 * @brief Disables the UART7 peripheral clock.
1740 *
1741 * @api
1742 */
1743#define rccDisableUART7() rccDisableAPB1L(RCC_APB1LENR_UART7EN)
1744
1745/**
1746 * @brief Resets the UART7 peripheral.
1747 *
1748 * @api
1749 */
1750#define rccResetUART7() rccResetAPB1L(RCC_APB1LRSTR_UART7RST)
1751
1752/**
1753 * @brief Enables the UART8 peripheral clock.
1754 *
1755 * @param[in] lp low power enable flag
1756 *
1757 * @api
1758 */
1759#define rccEnableUART8(lp) rccEnableAPB1L(RCC_APB1LENR_UART8EN, lp)
1760
1761/**
1762 * @brief Disables the UART8 peripheral clock.
1763 *
1764 * @api
1765 */
1766#define rccDisableUART8() rccDisableAPB1L(RCC_APB1LENR_UART8EN)
1767
1768/**
1769 * @brief Resets the UART8 peripheral.
1770 *
1771 * @api
1772 */
1773#define rccResetUART8() rccResetAPB1L(RCC_APB1LRSTR_UART8RST)
1774
1775/**
1776 * @brief Enables the LPUART1 peripheral clock.
1777 *
1778 * @param[in] lp low power enable flag
1779 *
1780 * @api
1781 */
1782#define rccEnableLPUART1(lp) rccEnableAPB4(RCC_APB4ENR_LPUART1EN, lp)
1783
1784/**
1785 * @brief Disables the LPUART1 peripheral clock.
1786 *
1787 * @api
1788 */
1789#define rccDisableLPUART1() rccDisableAPB4(RCC_APB4ENR_LPUART1EN)
1790
1791/**
1792 * @brief Resets the LPUART1 peripheral.
1793 *
1794 * @api
1795 */
1796#define rccResetLPUART1() rccResetAPB4(RCC_APB4RSTR_LPUART1RST)
1797/** @} */
1798
1799/**
1800 * @name LTDC peripheral specific RCC operations
1801 * @{
1802 */
1803/**
1804 * @brief Enables the LTDC peripheral clock.
1805 *
1806 * @param[in] lp low power enable flag
1807 *
1808 * @api
1809 */
1810#define rccEnableLTDC(lp) rccEnableAPB3(RCC_APB3ENR_LTDCEN, lp)
1811
1812/**
1813 * @brief Disables the LTDC peripheral clock.
1814. *
1815 * @api
1816 */
1817#define rccDisableLTDC() rccDisableAPB3(RCC_APB3ENR_LTDCEN)
1818
1819/**
1820 * @brief Resets the LTDC peripheral.
1821 *
1822 * @api
1823 */
1824#define rccResetLTDC() rccResetAPB3(RCC_APB3RSTR_LTDCRST)
1825
1826/**
1827 * @name DMA2D peripheral specific RCC operations
1828 * @{
1829 */
1830/**
1831 * @brief Enables the DMA2D peripheral clock.
1832 *
1833 * @param[in] lp low power enable flag
1834 *
1835 * @api
1836 */
1837#define rccEnableDMA2D(lp) rccEnableAHB3(RCC_AHB3ENR_DMA2DEN, lp)
1838
1839/**
1840 * @brief Disables the DMA2D peripheral clock.
1841 *
1842 * @api
1843 */
1844#define rccDisableDMA2D() rccDisableAHB3(RCC_AHB3ENR_DMA2DEN)
1845
1846/**
1847 * @brief Resets the DMA2D peripheral.
1848 *
1849 * @api
1850 */
1851#define rccResetDMA2D() rccResetAHB3(RCC_AHB3RSTR_DMA2DRST)
1852/** @} */
1853
1854/**
1855 * @name FSMC peripherals specific RCC operations
1856 * @{
1857 */
1858/**
1859 * @brief Enables the FSMC peripheral clock.
1860 *
1861 * @param[in] lp low power enable flag
1862 *
1863 * @api
1864 */
1865#if defined(STM32_FSMC_IS_FMC)
1866 #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp)
1867#else
1868 #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FSMCEN, lp)
1869#endif
1870
1871/**
1872 * @brief Disables the FSMC peripheral clock.
1873 *
1874 * @api
1875 */
1876#if defined(STM32_FSMC_IS_FMC)
1877 #define rccDisableFSMC() rccDisableAHB3(RCC_AHB3ENR_FMCEN)
1878#else
1879 #define rccDisableFSMC() rccDisableAHB3(RCC_AHB3ENR_FSMCEN)
1880#endif
1881
1882/**
1883 * @brief Resets the FSMC peripheral.
1884 *
1885 * @api
1886 */
1887#if defined(STM32_FSMC_IS_FMC)
1888 #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST)
1889#else
1890 #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FSMCRST)
1891#endif
1892/** @} */
1893
1894/*===========================================================================*/
1895/* External declarations. */
1896/*===========================================================================*/
1897
1898#ifdef __cplusplus
1899extern "C" {
1900#endif
1901#ifdef __cplusplus
1902}
1903#endif
1904
1905#endif /* STM32_RCC_H */
1906
1907/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 13:35:48 +0100