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-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c294
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.h383
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_lld.c237
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_lld.h863
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32L1xx/platform.dox315
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32L1xx/platform.mk46
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_isr.c255
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_isr.h230
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h795
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_registry.h377
10 files changed, 3795 insertions, 0 deletions
diff --git a/lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c b/lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c
new file mode 100644
index 000000000..b61a73d20
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c
@@ -0,0 +1,294 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32L1xx/hal_adc_lld.c
19 * @brief STM32L1xx ADC subsystem low level driver source.
20 *
21 * @addtogroup ADC
22 * @{
23 */
24
25#include "hal.h"
26
27#if HAL_USE_ADC || defined(__DOXYGEN__)
28
29/*===========================================================================*/
30/* Driver local definitions. */
31/*===========================================================================*/
32
33/*===========================================================================*/
34/* Driver exported variables. */
35/*===========================================================================*/
36
37/** @brief ADC1 driver identifier.*/
38#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
39ADCDriver ADCD1;
40#endif
41
42/*===========================================================================*/
43/* Driver local variables and types. */
44/*===========================================================================*/
45
46/*===========================================================================*/
47/* Driver local functions. */
48/*===========================================================================*/
49
50/**
51 * @brief ADC DMA ISR service routine.
52 *
53 * @param[in] adcp pointer to the @p ADCDriver object
54 * @param[in] flags pre-shifted content of the ISR register
55 */
56static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
57
58 /* DMA errors handling.*/
59 if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
60 /* DMA, this could help only if the DMA tries to access an unmapped
61 address space or violates alignment rules.*/
62 _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
63 }
64 else {
65 /* It is possible that the conversion group has already be reset by the
66 ADC error handler, in this case this interrupt is spurious.*/
67 if (adcp->grpp != NULL) {
68 if ((flags & STM32_DMA_ISR_TCIF) != 0) {
69 /* Transfer complete processing.*/
70 _adc_isr_full_code(adcp);
71 }
72 else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
73 /* Half transfer processing.*/
74 _adc_isr_half_code(adcp);
75 }
76 }
77 }
78}
79
80/*===========================================================================*/
81/* Driver interrupt handlers. */
82/*===========================================================================*/
83
84#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
85/**
86 * @brief ADC interrupt handler.
87 *
88 * @isr
89 */
90OSAL_IRQ_HANDLER(Vector88) {
91 uint32_t sr;
92
93 OSAL_IRQ_PROLOGUE();
94
95 sr = ADC1->SR;
96 ADC1->SR = 0;
97 /* Note, an overflow may occur after the conversion ended before the driver
98 is able to stop the ADC, this is why the DMA channel is checked too.*/
99 if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
100 /* ADC overflow condition, this could happen only if the DMA is unable
101 to read data fast enough.*/
102 if (ADCD1.grpp != NULL)
103 _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
104 }
105 /* CHTODO: Add here analog watchdog handling.*/
106
107 OSAL_IRQ_EPILOGUE();
108}
109#endif
110
111/*===========================================================================*/
112/* Driver exported functions. */
113/*===========================================================================*/
114
115/**
116 * @brief Low level ADC driver initialization.
117 *
118 * @notapi
119 */
120void adc_lld_init(void) {
121
122#if STM32_ADC_USE_ADC1
123 /* Driver initialization.*/
124 adcObjectInit(&ADCD1);
125 ADCD1.adc = ADC1;
126 ADCD1.dmastp = NULL;
127 ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
128 STM32_DMA_CR_DIR_P2M |
129 STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
130 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
131 STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
132#endif
133
134 /* The shared vector is initialized on driver initialization and never
135 disabled.*/
136 nvicEnableVector(ADC1_IRQn, STM32_ADC_IRQ_PRIORITY);
137}
138
139/**
140 * @brief Configures and activates the ADC peripheral.
141 *
142 * @param[in] adcp pointer to the @p ADCDriver object
143 *
144 * @notapi
145 */
146void adc_lld_start(ADCDriver *adcp) {
147
148 /* If in stopped state then enables the ADC and DMA clocks.*/
149 if (adcp->state == ADC_STOP) {
150#if STM32_ADC_USE_ADC1
151 if (&ADCD1 == adcp) {
152 adcp->dmastp = dmaStreamAllocI(STM32_DMA_STREAM_ID(1, 1),
153 STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
154 (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
155 (void *)adcp);
156 osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
157
158 dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
159 rccEnableADC1(true);
160 }
161#endif /* STM32_ADC_USE_ADC1 */
162
163 ADC->CCR = (ADC->CCR & ADC_CCR_TSVREFE) | (STM32_ADC_ADCPRE << 16);
164
165 /* ADC initial setup, starting the analog part here in order to reduce
166 the latency when starting a conversion.*/
167 adcp->adc->CR1 = 0;
168 adcp->adc->CR2 = 0;
169 adcp->adc->CR2 = ADC_CR2_ADON;
170 }
171}
172
173/**
174 * @brief Deactivates the ADC peripheral.
175 *
176 * @param[in] adcp pointer to the @p ADCDriver object
177 *
178 * @notapi
179 */
180void adc_lld_stop(ADCDriver *adcp) {
181
182 /* If in ready state then disables the ADC clock and analog part.*/
183 if (adcp->state == ADC_READY) {
184 dmaStreamFreeI(adcp->dmastp);
185 adcp->dmastp = NULL;
186
187 adcp->adc->CR1 = 0;
188 adcp->adc->CR2 = 0;
189
190#if STM32_ADC_USE_ADC1
191 if (&ADCD1 == adcp)
192 rccDisableADC1();
193#endif
194 }
195}
196
197/**
198 * @brief Starts an ADC conversion.
199 *
200 * @param[in] adcp pointer to the @p ADCDriver object
201 *
202 * @notapi
203 */
204void adc_lld_start_conversion(ADCDriver *adcp) {
205 uint32_t mode;
206 uint32_t cr2;
207 const ADCConversionGroup *grpp = adcp->grpp;
208
209 /* DMA setup.*/
210 mode = adcp->dmamode;
211 if (grpp->circular) {
212 mode |= STM32_DMA_CR_CIRC;
213 if (adcp->depth > 1) {
214 /* If circular buffer depth > 1, then the half transfer interrupt
215 is enabled in order to allow streaming processing.*/
216 mode |= STM32_DMA_CR_HTIE;
217 }
218 }
219 dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
220 dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
221 (uint32_t)adcp->depth);
222 dmaStreamSetMode(adcp->dmastp, mode);
223 dmaStreamEnable(adcp->dmastp);
224
225 /* ADC setup.*/
226 adcp->adc->SR = 0;
227 adcp->adc->SMPR1 = grpp->smpr1;
228 adcp->adc->SMPR2 = grpp->smpr2;
229 adcp->adc->SMPR3 = grpp->smpr3;
230 adcp->adc->SQR1 = grpp->sqr1;
231 adcp->adc->SQR2 = grpp->sqr2;
232 adcp->adc->SQR3 = grpp->sqr3;
233 adcp->adc->SQR4 = grpp->sqr4;
234 adcp->adc->SQR5 = grpp->sqr5;
235
236 /* ADC configuration and start.*/
237 adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
238
239 /* Enforcing the mandatory bits in CR2.*/
240 cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON;
241
242 /* The start method is different dependign if HW or SW triggered, the
243 start is performed using the method specified in the CR2 configuration.*/
244 if ((cr2 & ADC_CR2_SWSTART) != 0) {
245 /* Initializing CR2 while keeping ADC_CR2_SWSTART at zero.*/
246 adcp->adc->CR2 = (cr2 | ADC_CR2_CONT) & ~ADC_CR2_SWSTART;
247
248 /* Finally enabling ADC_CR2_SWSTART.*/
249 adcp->adc->CR2 = (cr2 | ADC_CR2_CONT);
250 }
251 else
252 adcp->adc->CR2 = cr2;
253}
254
255/**
256 * @brief Stops an ongoing conversion.
257 *
258 * @param[in] adcp pointer to the @p ADCDriver object
259 *
260 * @notapi
261 */
262void adc_lld_stop_conversion(ADCDriver *adcp) {
263
264 dmaStreamDisable(adcp->dmastp);
265 adcp->adc->CR1 = 0;
266 adcp->adc->CR2 = 0;
267 adcp->adc->CR2 = ADC_CR2_ADON;
268}
269
270/**
271 * @brief Enables the TSVREFE bit.
272 * @details The TSVREFE bit is required in order to sample the internal
273 * temperature sensor and internal reference voltage.
274 * @note This is an STM32-only functionality.
275 */
276void adcSTM32EnableTSVREFE(void) {
277
278 ADC->CCR |= ADC_CCR_TSVREFE;
279}
280
281/**
282 * @brief Disables the TSVREFE bit.
283 * @details The TSVREFE bit is required in order to sample the internal
284 * temperature sensor and internal reference voltage.
285 * @note This is an STM32-only functionality.
286 */
287void adcSTM32DisableTSVREFE(void) {
288
289 ADC->CCR &= ~ADC_CCR_TSVREFE;
290}
291
292#endif /* HAL_USE_ADC */
293
294/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.h b/lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.h
new file mode 100644
index 000000000..091e06f96
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.h
@@ -0,0 +1,383 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32L1xx/hal_adc_lld.h
19 * @brief STM32L1xx ADC subsystem low level driver header.
20 *
21 * @addtogroup ADC
22 * @{
23 */
24
25#ifndef HAL_ADC_LLD_H
26#define HAL_ADC_LLD_H
27
28#if HAL_USE_ADC || defined(__DOXYGEN__)
29
30/*===========================================================================*/
31/* Driver constants. */
32/*===========================================================================*/
33
34/**
35 * @name Triggers selection
36 * @{
37 */
38#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */
39/** @} */
40
41/**
42 * @name ADC clock divider settings
43 * @{
44 */
45#define ADC_CCR_ADCPRE_DIV1 0
46#define ADC_CCR_ADCPRE_DIV2 1
47#define ADC_CCR_ADCPRE_DIV4 2
48/** @} */
49
50/**
51 * @name Available analog channels
52 * @{
53 */
54#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */
55#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
56#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
57#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
58#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */
59#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */
60#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */
61#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */
62#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */
63#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */
64#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */
65#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */
66#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */
67#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */
68#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */
69#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */
70#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/
71#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */
72#define ADC_CHANNEL_IN18 18 /**< @brief External analog input 18. */
73#define ADC_CHANNEL_IN19 19 /**< @brief External analog input 19. */
74#define ADC_CHANNEL_IN20 20 /**< @brief External analog input 20. */
75#define ADC_CHANNEL_IN21 21 /**< @brief External analog input 21. */
76#define ADC_CHANNEL_IN22 22 /**< @brief External analog input 22. */
77#define ADC_CHANNEL_IN23 23 /**< @brief External analog input 23. */
78#define ADC_CHANNEL_IN24 24 /**< @brief External analog input 24. */
79#define ADC_CHANNEL_IN25 25 /**< @brief External analog input 25. */
80/** @} */
81
82/**
83 * @name Sampling rates
84 * @{
85 */
86#define ADC_SAMPLE_4 0 /**< @brief 4 cycles sampling time. */
87#define ADC_SAMPLE_9 1 /**< @brief 9 cycles sampling time. */
88#define ADC_SAMPLE_16 2 /**< @brief 16 cycles sampling time. */
89#define ADC_SAMPLE_24 3 /**< @brief 24 cycles sampling time. */
90#define ADC_SAMPLE_48 4 /**< @brief 48 cycles sampling time. */
91#define ADC_SAMPLE_96 5 /**< @brief 96 cycles sampling time. */
92#define ADC_SAMPLE_192 6 /**< @brief 192 cycles sampling time. */
93#define ADC_SAMPLE_384 7 /**< @brief 384 cycles sampling time. */
94/** @} */
95
96/*===========================================================================*/
97/* Driver pre-compile time settings. */
98/*===========================================================================*/
99
100/**
101 * @name Configuration options
102 * @{
103 */
104/**
105 * @brief ADC1 driver enable switch.
106 * @details If set to @p TRUE the support for ADC1 is included.
107 * @note The default is @p TRUE.
108 */
109#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
110#define STM32_ADC_USE_ADC1 FALSE
111#endif
112
113/**
114 * @brief ADC common clock divider.
115 * @note This setting is influenced by the VDDA voltage and other
116 * external conditions, please refer to the STM32L15x datasheet
117 * for more info.<br>
118 * See section 6.3.15 "12-bit ADC characteristics".
119 */
120#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
121#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV1
122#endif
123
124/**
125 * @brief ADC1 DMA priority (0..3|lowest..highest).
126 */
127#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
128#define STM32_ADC_ADC1_DMA_PRIORITY 2
129#endif
130
131/**
132 * @brief ADC interrupt priority level setting.
133 */
134#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
135#define STM32_ADC_IRQ_PRIORITY 5
136#endif
137
138/**
139 * @brief ADC1 DMA interrupt priority level setting.
140 */
141#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
142#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
143#endif
144
145/** @} */
146
147/*===========================================================================*/
148/* Derived constants and error checks. */
149/*===========================================================================*/
150
151#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
152#error "ADC1 not present in the selected device"
153#endif
154
155#if !STM32_ADC_USE_ADC1
156#error "ADC driver activated but no ADC peripheral assigned"
157#endif
158
159#if STM32_ADC_USE_ADC1 && \
160 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_IRQ_PRIORITY)
161#error "Invalid IRQ priority assigned to ADC1"
162#endif
163
164#if STM32_ADC_USE_ADC1 && \
165 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
166#error "Invalid IRQ priority assigned to ADC1 DMA"
167#endif
168
169#if STM32_ADC_USE_ADC1 && \
170 !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
171#error "Invalid DMA priority assigned to ADC1"
172#endif
173
174#if !defined(STM32_DMA_REQUIRED)
175#define STM32_DMA_REQUIRED
176#endif
177
178/**
179 * * @brief ADC frequency.
180 * */
181/* ADC clock related settings and checks.*/
182#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV1
183#define STM32_ADCCLK STM32_HSICLK
184#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2
185#define STM32_ADCCLK (STM32_HSICLK / 2)
186#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4
187#define STM32_ADCCLK (STM32_HSICLK / 4)
188#else
189#error "invalid STM32_ADC_ADCPRE value specified"
190#endif
191
192/*===========================================================================*/
193/* Driver data structures and types. */
194/*===========================================================================*/
195
196/**
197 * @brief ADC sample data type.
198 */
199typedef uint16_t adcsample_t;
200
201/**
202 * @brief Channels number in a conversion group.
203 */
204typedef uint16_t adc_channels_num_t;
205
206/**
207 * @brief Possible ADC failure causes.
208 * @note Error codes are architecture dependent and should not relied
209 * upon.
210 */
211typedef enum {
212 ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
213 ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */
214} adcerror_t;
215
216/*===========================================================================*/
217/* Driver macros. */
218/*===========================================================================*/
219
220/**
221 * @brief Low level fields of the ADC driver structure.
222 */
223#define adc_lld_driver_fields \
224 /* Pointer to the ADCx registers block.*/ \
225 ADC_TypeDef *adc; \
226 /* Pointer to associated DMA channel.*/ \
227 const stm32_dma_stream_t *dmastp; \
228 /* DMA mode bit mask.*/ \
229 uint32_t dmamode
230
231/**
232 * @brief Low level fields of the ADC configuration structure.
233 */
234#define adc_lld_config_fields \
235 /* Dummy configuration, it is not needed.*/ \
236 uint32_t dummy
237
238/**
239 * @brief Low level fields of the ADC configuration structure.
240 */
241#define adc_lld_configuration_group_fields \
242 /* ADC CR1 register initialization data. \
243 NOTE: All the required bits must be defined into this field except \
244 @p ADC_CR1_SCAN that is enforced inside the driver.*/ \
245 uint32_t cr1; \
246 /* ADC CR2 register initialization data. \
247 NOTE: All the required bits must be defined into this field except \
248 @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are \
249 enforced inside the driver.*/ \
250 uint32_t cr2; \
251 /* ADC SMPR1 register initialization data. \
252 NOTE: In this field must be specified the sample times for channels \
253 20...25.*/ \
254 uint32_t smpr1; \
255 /* ADC SMPR2 register initialization data. \
256 NOTE: In this field must be specified the sample times for channels \
257 10...19.*/ \
258 uint32_t smpr2; \
259 /* ADC SMPR3 register initialization data. \
260 NOTE: In this field must be specified the sample times for channels \
261 0...9.*/ \
262 uint32_t smpr3; \
263 /* ADC SQR1 register initialization data. \
264 NOTE: Conversion group sequence 25...27 + sequence length.*/ \
265 uint32_t sqr1; \
266 /* ADC SQR2 register initialization data. \
267 NOTE: Conversion group sequence 19...24.*/ \
268 uint32_t sqr2; \
269 /* ADC SQR3 register initialization data. \
270 NOTE: Conversion group sequence 13...18.*/ \
271 uint32_t sqr3; \
272 /* ADC SQR3 register initialization data. \
273 NOTE: Conversion group sequence 7...12.*/ \
274 uint32_t sqr4; \
275 /* ADC SQR3 register initialization data. \
276 NOTE: Conversion group sequence 1...6.*/ \
277 uint32_t sqr5
278
279/**
280 * @name Sequences building helper macros
281 * @{
282 */
283/**
284 * @brief Number of channels in a conversion sequence.
285 */
286#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
287
288#define ADC_SQR5_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
289#define ADC_SQR5_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
290#define ADC_SQR5_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
291#define ADC_SQR5_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
292#define ADC_SQR5_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
293#define ADC_SQR5_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
294
295#define ADC_SQR4_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
296#define ADC_SQR4_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
297#define ADC_SQR4_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */
298#define ADC_SQR4_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/
299#define ADC_SQR4_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
300#define ADC_SQR4_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
301
302#define ADC_SQR3_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
303#define ADC_SQR3_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
304#define ADC_SQR3_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
305#define ADC_SQR3_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
306#define ADC_SQR3_SQ17_N(n) ((n) << 20) /**< @brief 17th channel in seq.*/
307#define ADC_SQR3_SQ18_N(n) ((n) << 25) /**< @brief 18th channel in seq.*/
308
309#define ADC_SQR2_SQ19_N(n) ((n) << 0) /**< @brief 19th channel in seq.*/
310#define ADC_SQR2_SQ20_N(n) ((n) << 5) /**< @brief 20th channel in seq.*/
311#define ADC_SQR2_SQ21_N(n) ((n) << 10) /**< @brief 21th channel in seq.*/
312#define ADC_SQR2_SQ22_N(n) ((n) << 15) /**< @brief 22th channel in seq.*/
313#define ADC_SQR2_SQ23_N(n) ((n) << 20) /**< @brief 23th channel in seq.*/
314#define ADC_SQR2_SQ24_N(n) ((n) << 25) /**< @brief 24th channel in seq.*/
315
316#define ADC_SQR1_SQ25_N(n) ((n) << 0) /**< @brief 25th channel in seq.*/
317#define ADC_SQR1_SQ26_N(n) ((n) << 5) /**< @brief 26th channel in seq.*/
318#define ADC_SQR1_SQ27_N(n) ((n) << 10) /**< @brief 27th channel in seq.*/
319/** @} */
320
321/**
322 * @name Sampling rate settings helper macros
323 * @{
324 */
325#define ADC_SMPR3_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */
326#define ADC_SMPR3_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
327#define ADC_SMPR3_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
328#define ADC_SMPR3_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
329#define ADC_SMPR3_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */
330#define ADC_SMPR3_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */
331#define ADC_SMPR3_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */
332#define ADC_SMPR3_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */
333#define ADC_SMPR3_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */
334#define ADC_SMPR3_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */
335
336#define ADC_SMPR2_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */
337#define ADC_SMPR2_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */
338#define ADC_SMPR2_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */
339#define ADC_SMPR2_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */
340#define ADC_SMPR2_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */
341#define ADC_SMPR2_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */
342#define ADC_SMPR2_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
343 sampling time. */
344#define ADC_SMPR2_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference
345 sampling time. */
346#define ADC_SMPR2_SMP_AN18(n) ((n) << 24) /**< @brief AN18 sampling time. */
347#define ADC_SMPR2_SMP_AN19(n) ((n) << 27) /**< @brief AN19 sampling time. */
348
349#define ADC_SMPR1_SMP_AN20(n) ((n) << 0) /**< @brief AN20 sampling time. */
350#define ADC_SMPR1_SMP_AN21(n) ((n) << 3) /**< @brief AN21 sampling time. */
351#define ADC_SMPR1_SMP_AN22(n) ((n) << 6) /**< @brief AN22 sampling time. */
352#define ADC_SMPR1_SMP_AN23(n) ((n) << 9) /**< @brief AN23 sampling time. */
353#define ADC_SMPR1_SMP_AN24(n) ((n) << 12) /**< @brief AN24 sampling time. */
354#define ADC_SMPR1_SMP_AN25(n) ((n) << 15) /**< @brief AN25 sampling time. */
355/** @} */
356
357/*===========================================================================*/
358/* External declarations. */
359/*===========================================================================*/
360
361#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
362extern ADCDriver ADCD1;
363#endif
364
365#ifdef __cplusplus
366extern "C" {
367#endif
368 void adc_lld_init(void);
369 void adc_lld_start(ADCDriver *adcp);
370 void adc_lld_stop(ADCDriver *adcp);
371 void adc_lld_start_conversion(ADCDriver *adcp);
372 void adc_lld_stop_conversion(ADCDriver *adcp);
373 void adcSTM32EnableTSVREFE(void);
374 void adcSTM32DisableTSVREFE(void);
375#ifdef __cplusplus
376}
377#endif
378
379#endif /* HAL_USE_ADC */
380
381#endif /* HAL_ADC_LLD_H */
382
383/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_lld.c b/lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_lld.c
new file mode 100644
index 000000000..325a8f4da
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_lld.c
@@ -0,0 +1,237 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32L1xx/hal_lld.c
19 * @brief STM32L1xx HAL subsystem low level driver source.
20 *
21 * @addtogroup HAL
22 * @{
23 */
24
25/* CHTODO: LSEBYP like in F3.*/
26
27#include "hal.h"
28
29/*===========================================================================*/
30/* Driver local definitions. */
31/*===========================================================================*/
32
33/*===========================================================================*/
34/* Driver exported variables. */
35/*===========================================================================*/
36
37/**
38 * @brief CMSIS system core clock variable.
39 * @note It is declared in system_stm32l1xx.h.
40 */
41uint32_t SystemCoreClock = STM32_HCLK;
42
43/*===========================================================================*/
44/* Driver local variables and types. */
45/*===========================================================================*/
46
47/*===========================================================================*/
48/* Driver local functions. */
49/*===========================================================================*/
50
51/**
52 * @brief Initializes the backup domain.
53 */
54static void hal_lld_backup_domain_init(void) {
55
56 /* Backup domain access enabled and left open.*/
57 PWR->CR |= PWR_CR_DBP;
58
59 /* Reset BKP domain if different clock source selected.*/
60 if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
61 /* Backup domain reset.*/
62 RCC->CSR |= RCC_CSR_RTCRST;
63 RCC->CSR &= ~RCC_CSR_RTCRST;
64 }
65
66 /* If enabled then the LSE is started.*/
67#if STM32_LSE_ENABLED
68 RCC->CSR |= RCC_CSR_LSEON;
69 while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
70 ; /* Waits until LSE is stable. */
71#endif
72
73#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
74 /* If the backup domain hasn't been initialized yet then proceed with
75 initialization.*/
76 if ((RCC->CSR & RCC_CSR_RTCEN) == 0) {
77 /* Selects clock source.*/
78 RCC->CSR |= STM32_RTCSEL;
79
80 /* RTC clock enabled.*/
81 RCC->CSR |= RCC_CSR_RTCEN;
82 }
83#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
84}
85
86/*===========================================================================*/
87/* Driver interrupt handlers. */
88/*===========================================================================*/
89
90/*===========================================================================*/
91/* Driver exported functions. */
92/*===========================================================================*/
93
94/**
95 * @brief Low level HAL driver initialization.
96 *
97 * @notapi
98 */
99void hal_lld_init(void) {
100
101 /* Reset of all peripherals.
102 Note, GPIOs are not reset because initialized before this point in
103 board files.*/
104 rccResetAHB(~(RCC_AHBRSTR_FLITFRST | STM32_GPIO_EN_MASK));
105 rccResetAPB1(~RCC_APB1RSTR_PWRRST);
106 rccResetAPB2(~0);
107
108 /* PWR clock enabled.*/
109 rccEnablePWRInterface(true);
110
111 /* Initializes the backup domain.*/
112 hal_lld_backup_domain_init();
113
114 /* DMA subsystems initialization.*/
115#if defined(STM32_DMA_REQUIRED)
116 dmaInit();
117#endif
118
119 /* IRQ subsystem initialization.*/
120 irqInit();
121
122 /* Programmable voltage detector enable.*/
123#if STM32_PVD_ENABLE
124 PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
125#endif /* STM32_PVD_ENABLE */
126}
127
128/**
129 * @brief STM32L1xx voltage, clocks and PLL initialization.
130 * @note All the involved constants come from the file @p board.h.
131 * @note This function should be invoked just after the system reset.
132 *
133 * @special
134 */
135/**
136 * @brief Clocks and internal voltage initialization.
137 */
138void stm32_clock_init(void) {
139
140#if !STM32_NO_INIT
141 /* PWR clock enable.*/
142 RCC->APB1ENR = RCC_APB1ENR_PWREN;
143
144 /* Core voltage setup.*/
145 while ((PWR->CSR & PWR_CSR_VOSF) != 0)
146 ; /* Waits until regulator is stable. */
147 PWR->CR = STM32_VOS;
148 while ((PWR->CSR & PWR_CSR_VOSF) != 0)
149 ; /* Waits until regulator is stable. */
150
151 /* Initial clocks setup and wait for MSI stabilization, the MSI clock is
152 always enabled because it is the fallback clock when PLL the fails.
153 Trim fields are not altered from reset values.*/
154 RCC->CFGR = 0;
155 RCC->ICSCR = (RCC->ICSCR & ~STM32_MSIRANGE_MASK) | STM32_MSIRANGE;
156 RCC->CR = RCC_CR_MSION;
157 while ((RCC->CR & RCC_CR_MSIRDY) == 0)
158 ; /* Waits until MSI is stable. */
159
160#if STM32_HSI_ENABLED
161 /* HSI activation.*/
162 RCC->CR |= RCC_CR_HSION;
163 while ((RCC->CR & RCC_CR_HSIRDY) == 0)
164 ; /* Waits until HSI is stable. */
165#endif
166
167#if STM32_HSE_ENABLED
168#if defined(STM32_HSE_BYPASS)
169 /* HSE Bypass.*/
170 RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
171#endif
172 /* HSE activation.*/
173 RCC->CR |= RCC_CR_HSEON;
174 while ((RCC->CR & RCC_CR_HSERDY) == 0)
175 ; /* Waits until HSE is stable. */
176#endif
177
178#if STM32_LSI_ENABLED
179 /* LSI activation.*/
180 RCC->CSR |= RCC_CSR_LSION;
181 while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
182 ; /* Waits until LSI is stable. */
183#endif
184
185#if STM32_LSE_ENABLED
186 /* LSE activation, have to unlock the register.*/
187 if ((RCC->CSR & RCC_CSR_LSEON) == 0) {
188 PWR->CR |= PWR_CR_DBP;
189 RCC->CSR |= RCC_CSR_LSEON;
190 PWR->CR &= ~PWR_CR_DBP;
191 }
192 while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
193 ; /* Waits until LSE is stable. */
194#endif
195
196#if STM32_ACTIVATE_PLL
197 /* PLL activation.*/
198 RCC->CFGR |= STM32_PLLDIV | STM32_PLLMUL | STM32_PLLSRC;
199 RCC->CR |= RCC_CR_PLLON;
200 while (!(RCC->CR & RCC_CR_PLLRDY))
201 ; /* Waits until PLL is stable. */
202#endif
203
204 /* Other clock-related settings (dividers, MCO etc).*/
205 RCC->CR |= STM32_RTCPRE;
206 RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL |
207 STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
208 RCC->CSR |= STM32_RTCSEL;
209
210 /* Flash setup and final clock selection.*/
211#if defined(STM32_FLASHBITS1)
212 FLASH->ACR = STM32_FLASHBITS1;
213 while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
214 (STM32_FLASHBITS1 & FLASH_ACR_LATENCY_Msk)) {
215 }
216#endif
217#if defined(STM32_FLASHBITS2)
218 FLASH->ACR = STM32_FLASHBITS2;
219 while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
220 (STM32_FLASHBITS2 & FLASH_ACR_LATENCY_Msk)) {
221 }
222#endif
223
224 /* Switching to the configured clock source if it is different from MSI.*/
225#if (STM32_SW != STM32_SW_MSI)
226 RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
227 while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
228 ;
229#endif
230#endif /* STM32_NO_INIT */
231
232 /* SYSCFG clock enabled here because it is a multi-functional unit shared
233 among multiple drivers.*/
234 rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
235}
236
237/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_lld.h b/lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_lld.h
new file mode 100644
index 000000000..869e0a696
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32L1xx/hal_lld.h
@@ -0,0 +1,863 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32L1xx/hal_lld.h
19 * @brief STM32L1xx HAL subsystem low level driver header.
20 * @pre This module requires the following macros to be defined in the
21 * @p board.h file:
22 * - STM32_LSECLK.
23 * - STM32_HSECLK.
24 * - STM32_HSE_BYPASS (optionally).
25 * .
26 * One of the following macros must also be defined:
27 * - STM32L100xB, STM32L100xBA, STM32L100xC.
28 * - STM32L151xB, STM32L151xBA, STM32L151xC, STM32L151xCA,
29 * STM32L151xD, STM32L151xDX, STM32L151xE.
30 * - STM32L152xB, STM32L152xBA, STM32L152xC, STM32L152xCA,
31 * STM32L152xD, STM32L152xDX, STM32L152xE.
32 * - STM32L162xC, STM32L162xCA, STM32L162xD, STM32L162xDX,
33 * STM32L162xE.
34 * .
35 *
36 * @addtogroup HAL
37 * @{
38 */
39
40#ifndef HAL_LLD_H
41#define HAL_LLD_H
42
43#include "stm32_registry.h"
44
45/*===========================================================================*/
46/* Driver constants. */
47/*===========================================================================*/
48
49/**
50 * @name Platform identification
51 * @{
52 */
53#if defined(STM32L100xB) || defined(STM32L151xB) || \
54 defined(STM32L152xB) || defined(__DOXYGEN__)
55#define PLATFORM_NAME "STM32L1xx Ultra Low Power Medium Density"
56
57#elif defined(STM32L100xBA) || defined(STM32L100xC) || \
58 defined(STM32L151xBA) || defined(STM32L151xC) || \
59 defined(STM32L151xCA) || defined(STM32L152xBA) || \
60 defined(STM32L152xC) || defined(STM32L152xCA) || \
61 defined(STM32L162xC) || defined(STM32L162xCA)
62#define PLATFORM_NAME "STM32L1xx Ultra Low Power Medium Density Plus"
63
64#elif defined(STM32L151xD) || defined(STM32L151xDX) || \
65 defined(STM32L151xE) || defined(STM32L152xD) || \
66 defined(STM32L152xDX) || defined(STM32L152xE) || \
67 defined(STM32L162xD) || defined(STM32L162xDX) || \
68 defined(STM32L162xE)
69#define PLATFORM_NAME "STM32L1xx Ultra Low Power High Density"
70
71#else
72#error "STM32L1xx device not specified"
73#endif
74
75/**
76 * @brief Sub-family identifier.
77 */
78#if !defined(STM32L1XX) || defined(__DOXYGEN__)
79#define STM32L1XX
80#endif
81/** @} */
82
83/**
84 * @name Internal clock sources
85 * @{
86 */
87#define STM32_HSICLK 16000000 /**< High speed internal clock. */
88#define STM32_LSICLK 38000 /**< Low speed internal clock. */
89/** @} */
90
91/**
92 * @name PWR_CR register bits definitions
93 * @{
94 */
95#define STM32_VOS_MASK (3 << 11) /**< Core voltage mask. */
96#define STM32_VOS_1P8 (1 << 11) /**< Core voltage 1.8 Volts. */
97#define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */
98#define STM32_VOS_1P2 (3 << 11) /**< Core voltage 1.2 Volts. */
99
100#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
101#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
102#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
103#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
104#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
105#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
106#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
107#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
108#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
109/** @} */
110
111/**
112 * @name RCC_CR register bits definitions
113 * @{
114 */
115#define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */
116#define STM32_RTCPRE_DIV2 (0 << 29) /**< HSE divided by 2. */
117#define STM32_RTCPRE_DIV4 (1 << 29) /**< HSE divided by 4. */
118#define STM32_RTCPRE_DIV8 (2 << 29) /**< HSE divided by 2. */
119#define STM32_RTCPRE_DIV16 (3 << 29) /**< HSE divided by 16. */
120/** @} */
121
122/**
123 * @name RCC_CFGR register bits definitions
124 * @{
125 */
126#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */
127#define STM32_SW_HSI (1 << 0) /**< SYSCLK source is HSI. */
128#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
129#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */
130
131#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
132#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
133#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
134#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
135#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
136#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
137#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
138#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
139#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
140
141#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
142#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
143#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
144#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
145#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
146
147#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
148#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
149#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
150#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
151#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
152
153#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
154#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
155
156#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
157#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */
158#define STM32_MCOSEL_HSI (2 << 24) /**< HSI clock on MCO pin. */
159#define STM32_MCOSEL_MSI (3 << 24) /**< MSI clock on MCO pin. */
160#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */
161#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */
162#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */
163#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */
164
165#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
166#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 2. */
167#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 4. */
168#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 8. */
169#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 16. */
170/** @} */
171
172/**
173 * @name RCC_ICSCR register bits definitions
174 * @{
175 */
176#define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */
177#define STM32_MSIRANGE_64K (0 << 13) /**< 64kHz nominal. */
178#define STM32_MSIRANGE_128K (1 << 13) /**< 128kHz nominal. */
179#define STM32_MSIRANGE_256K (2 << 13) /**< 256kHz nominal. */
180#define STM32_MSIRANGE_512K (3 << 13) /**< 512kHz nominal. */
181#define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */
182#define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */
183#define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */
184/** @} */
185
186/**
187 * @name RCC_CSR register bits definitions
188 * @{
189 */
190#define STM32_RTCSEL_MASK (3 << 16) /**< RTC source mask. */
191#define STM32_RTCSEL_NOCLOCK (0 << 16) /**< No RTC source. */
192#define STM32_RTCSEL_LSE (1 << 16) /**< RTC source is LSE. */
193#define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */
194#define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */
195/** @} */
196
197/*===========================================================================*/
198/* Driver pre-compile time settings. */
199/*===========================================================================*/
200
201/**
202 * @name Configuration options
203 * @{
204 */
205/**
206 * @brief Disables the PWR/RCC initialization in the HAL.
207 */
208#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
209#define STM32_NO_INIT FALSE
210#endif
211
212/**
213 * @brief Core voltage selection.
214 * @note This setting affects all the performance and clock related
215 * settings, the maximum performance is only obtainable selecting
216 * the maximum voltage.
217 */
218#if !defined(STM32_VOS) || defined(__DOXYGEN__)
219#define STM32_VOS STM32_VOS_1P8
220#endif
221
222/**
223 * @brief Enables or disables the programmable voltage detector.
224 */
225#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
226#define STM32_PVD_ENABLE FALSE
227#endif
228
229/**
230 * @brief Sets voltage level for programmable voltage detector.
231 */
232#if !defined(STM32_PLS) || defined(__DOXYGEN__)
233#define STM32_PLS STM32_PLS_LEV0
234#endif
235
236/**
237 * @brief Enables or disables the HSI clock source.
238 */
239#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
240#define STM32_HSI_ENABLED TRUE
241#endif
242
243/**
244 * @brief Enables or disables the LSI clock source.
245 */
246#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
247#define STM32_LSI_ENABLED TRUE
248#endif
249
250/**
251 * @brief Enables or disables the HSE clock source.
252 */
253#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
254#define STM32_HSE_ENABLED FALSE
255#endif
256
257/**
258 * @brief Enables or disables the LSE clock source.
259 */
260#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
261#define STM32_LSE_ENABLED FALSE
262#endif
263
264/**
265 * @brief ADC clock setting.
266 */
267#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__)
268#define STM32_ADC_CLOCK_ENABLED TRUE
269#endif
270
271/**
272 * @brief USB clock setting.
273 */
274#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__)
275#define STM32_USB_CLOCK_ENABLED TRUE
276#endif
277
278/**
279 * @brief MSI frequency setting.
280 */
281#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__)
282#define STM32_MSIRANGE STM32_MSIRANGE_2M
283#endif
284
285/**
286 * @brief Main clock source selection.
287 * @note If the selected clock source is not the PLL then the PLL is not
288 * initialized and started.
289 * @note The default value is calculated for a 32MHz system clock from
290 * the internal 16MHz HSI clock.
291 */
292#if !defined(STM32_SW) || defined(__DOXYGEN__)
293#define STM32_SW STM32_SW_PLL
294#endif
295
296/**
297 * @brief Clock source for the PLL.
298 * @note This setting has only effect if the PLL is selected as the
299 * system clock source.
300 * @note The default value is calculated for a 32MHz system clock from
301 * the internal 16MHz HSI clock.
302 */
303#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
304#define STM32_PLLSRC STM32_PLLSRC_HSI
305#endif
306
307/**
308 * @brief PLL multiplier value.
309 * @note The allowed values are 3, 4, 6, 8, 12, 16, 32, 48.
310 * @note The default value is calculated for a 32MHz system clock from
311 * the internal 16MHz HSI clock.
312 */
313#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
314#define STM32_PLLMUL_VALUE 6
315#endif
316
317/**
318 * @brief PLL divider value.
319 * @note The allowed values are 2, 3, 4.
320 * @note The default value is calculated for a 32MHz system clock from
321 * the internal 16MHz HSI clock.
322 */
323#if !defined(STM32_PLLDIV_VALUE) || defined(__DOXYGEN__)
324#define STM32_PLLDIV_VALUE 3
325#endif
326
327/**
328 * @brief AHB prescaler value.
329 * @note The default value is calculated for a 32MHz system clock from
330 * the internal 16MHz HSI clock.
331 */
332#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
333#define STM32_HPRE STM32_HPRE_DIV1
334#endif
335
336/**
337 * @brief APB1 prescaler value.
338 */
339#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
340#define STM32_PPRE1 STM32_PPRE1_DIV1
341#endif
342
343/**
344 * @brief APB2 prescaler value.
345 */
346#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
347#define STM32_PPRE2 STM32_PPRE2_DIV1
348#endif
349
350/**
351 * @brief MCO clock source.
352 */
353#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
354#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
355#endif
356
357/**
358 * @brief MCO divider setting.
359 */
360#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
361#define STM32_MCOPRE STM32_MCOPRE_DIV1
362#endif
363
364/**
365 * @brief RTC/LCD clock source.
366 */
367#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
368#define STM32_RTCSEL STM32_RTCSEL_LSE
369#endif
370
371/**
372 * @brief HSE divider toward RTC setting.
373 */
374#if !defined(STM32_RTCPRE) || defined(__DOXYGEN__)
375#define STM32_RTCPRE STM32_RTCPRE_DIV2
376#endif
377/** @} */
378
379/*===========================================================================*/
380/* Derived constants and error checks. */
381/*===========================================================================*/
382
383/*
384 * Configuration-related checks.
385 */
386#if !defined(STM32L1xx_MCUCONF)
387#error "Using a wrong mcuconf.h file, STM32L1xx_MCUCONF not defined"
388#endif
389
390/* Voltage related limits.*/
391#if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__)
392/**
393 * @brief Maximum HSE clock frequency at current voltage setting.
394 */
395#define STM32_HSECLK_MAX 32000000
396
397/**
398 * @brief Maximum SYSCLK clock frequency at current voltage setting.
399 */
400#define STM32_SYSCLK_MAX 32000000
401
402/**
403 * @brief Maximum VCO clock frequency at current voltage setting.
404 */
405#define STM32_PLLVCO_MAX 96000000
406
407/**
408 * @brief Minimum VCO clock frequency at current voltage setting.
409 */
410#define STM32_PLLVCO_MIN 6000000
411
412/**
413 * @brief Maximum APB1 clock frequency.
414 */
415#define STM32_PCLK1_MAX 32000000
416
417/**
418 * @brief Maximum APB2 clock frequency.
419 */
420#define STM32_PCLK2_MAX 32000000
421
422/**
423 * @brief Maximum frequency not requiring a wait state for flash accesses.
424 */
425#define STM32_0WS_THRESHOLD 16000000
426
427/**
428 * @brief HSI availability at current voltage settings.
429 */
430#define STM32_HSI_AVAILABLE TRUE
431
432#elif STM32_VOS == STM32_VOS_1P5
433#define STM32_HSECLK_MAX 16000000
434#define STM32_SYSCLK_MAX 16000000
435#define STM32_PLLVCO_MAX 48000000
436#define STM32_PLLVCO_MIN 6000000
437#define STM32_PCLK1_MAX 16000000
438#define STM32_PCLK2_MAX 16000000
439#define STM32_0WS_THRESHOLD 8000000
440#define STM32_HSI_AVAILABLE TRUE
441#elif STM32_VOS == STM32_VOS_1P2
442#define STM32_HSECLK_MAX 4000000
443#define STM32_SYSCLK_MAX 4000000
444#define STM32_PLLVCO_MAX 24000000
445#define STM32_PLLVCO_MIN 6000000
446#define STM32_PCLK1_MAX 4000000
447#define STM32_PCLK2_MAX 4000000
448#define STM32_0WS_THRESHOLD 2000000
449#define STM32_HSI_AVAILABLE FALSE
450#else
451#error "invalid STM32_VOS value specified"
452#endif
453
454/* HSI related checks.*/
455#if STM32_HSI_ENABLED
456#if !STM32_HSI_AVAILABLE
457 #error "impossible to activate HSI under the current voltage settings"
458#endif
459#else /* !STM32_HSI_ENABLED */
460#if STM32_ADC_CLOCK_ENABLED || \
461 (STM32_SW == STM32_SW_HSI) || \
462 ((STM32_SW == STM32_SW_PLL) && \
463 (STM32_PLLSRC == STM32_PLLSRC_HSI)) || \
464 (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
465 ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
466 (STM32_PLLSRC == STM32_PLLSRC_HSI))
467#error "required HSI clock is not enabled"
468#endif
469#endif /* !STM32_HSI_ENABLED */
470
471/* HSE related checks.*/
472#if STM32_HSE_ENABLED
473#if STM32_HSECLK == 0
474#error "impossible to activate HSE"
475#endif
476#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX)
477#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)"
478#endif
479#else /* !STM32_HSE_ENABLED */
480#if (STM32_SW == STM32_SW_HSE) || \
481 ((STM32_SW == STM32_SW_PLL) && \
482 (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
483 (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
484 ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
485 (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
486 (STM32_RTCSEL == STM32_RTCSEL_HSEDIV)
487#error "required HSE clock is not enabled"
488#endif
489#endif /* !STM32_HSE_ENABLED */
490
491/* LSI related checks.*/
492#if STM32_LSI_ENABLED
493#else /* !STM32_LSI_ENABLED */
494
495#if STM32_MCOSEL == STM32_MCOSEL_LSI
496#error "LSI not enabled, required by STM32_MCOSEL"
497#endif
498
499#if HAL_USE_RTC && (STM32_RTCSEL == STM32_RTCSEL_LSI)
500#error "LSI not enabled, required by STM32_RTCSEL"
501#endif
502
503#endif /* !STM32_LSI_ENABLED */
504
505/* LSE related checks.*/
506#if STM32_LSE_ENABLED
507#if (STM32_LSECLK == 0)
508#error "impossible to activate LSE"
509#endif
510#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000)
511#error "STM32_LSECLK outside acceptable range (1...1000kHz)"
512#endif
513#else /* !STM32_LSE_ENABLED */
514
515#if STM32_MCOSEL == STM32_MCOSEL_LSE
516#error "LSE not enabled, required by STM32_MCOSEL"
517#endif
518
519#if STM32_RTCSEL == STM32_RTCSEL_LSE
520#error "LSE not enabled, required by STM32_RTCSEL"
521#endif
522
523#endif /* !STM32_LSE_ENABLED */
524
525/* PLL related checks.*/
526#if STM32_USB_CLOCK_ENABLED || \
527 (STM32_SW == STM32_SW_PLL) || \
528 (STM32_MCOSEL == STM32_MCOSEL_PLL) || \
529 defined(__DOXYGEN__)
530/**
531 * @brief PLL activation flag.
532 */
533#define STM32_ACTIVATE_PLL TRUE
534#else
535#define STM32_ACTIVATE_PLL FALSE
536#endif
537
538/**
539 * @brief PLLMUL field.
540 */
541#if (STM32_PLLMUL_VALUE == 3) || defined(__DOXYGEN__)
542#define STM32_PLLMUL (0 << 18)
543#elif STM32_PLLMUL_VALUE == 4
544#define STM32_PLLMUL (1 << 18)
545#elif STM32_PLLMUL_VALUE == 6
546#define STM32_PLLMUL (2 << 18)
547#elif STM32_PLLMUL_VALUE == 8
548#define STM32_PLLMUL (3 << 18)
549#elif STM32_PLLMUL_VALUE == 12
550#define STM32_PLLMUL (4 << 18)
551#elif STM32_PLLMUL_VALUE == 16
552#define STM32_PLLMUL (5 << 18)
553#elif STM32_PLLMUL_VALUE == 24
554#define STM32_PLLMUL (6 << 18)
555#elif STM32_PLLMUL_VALUE == 32
556#define STM32_PLLMUL (7 << 18)
557#elif STM32_PLLMUL_VALUE == 48
558#define STM32_PLLMUL (8 << 18)
559#else
560#error "invalid STM32_PLLMUL_VALUE value specified"
561#endif
562
563/**
564 * @brief PLLDIV field.
565 */
566#if (STM32_PLLDIV_VALUE == 2) || defined(__DOXYGEN__)
567#define STM32_PLLDIV (1 << 22)
568#elif STM32_PLLDIV_VALUE == 3
569#define STM32_PLLDIV (2 << 22)
570#elif STM32_PLLDIV_VALUE == 4
571#define STM32_PLLDIV (3 << 22)
572#else
573#error "invalid STM32_PLLDIV_VALUE value specified"
574#endif
575
576/**
577 * @brief PLL input clock frequency.
578 */
579#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
580#define STM32_PLLCLKIN STM32_HSECLK
581#elif STM32_PLLSRC == STM32_PLLSRC_HSI
582#define STM32_PLLCLKIN STM32_HSICLK
583#else
584#error "invalid STM32_PLLSRC value specified"
585#endif
586
587/* PLL input frequency range check.*/
588#if (STM32_PLLCLKIN < 2000000) || (STM32_PLLCLKIN > 24000000)
589#error "STM32_PLLCLKIN outside acceptable range (2...24MHz)"
590#endif
591
592/**
593 * @brief PLL VCO frequency.
594 */
595#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
596
597/* PLL output frequency range check.*/
598#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
599#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
600#endif
601
602/**
603 * @brief PLL output clock frequency.
604 */
605#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLDIV_VALUE)
606
607/* PLL output frequency range check.*/
608#if (STM32_PLLCLKOUT < 2000000) || (STM32_PLLCLKOUT > 32000000)
609#error "STM32_PLLCLKOUT outside acceptable range (2...32MHz)"
610#endif
611
612/**
613 * @brief MSI frequency.
614 */
615#if STM32_MSIRANGE == STM32_MSIRANGE_64K
616#define STM32_MSICLK 65500
617#elif STM32_MSIRANGE == STM32_MSIRANGE_128K
618#define STM32_MSICLK 131000
619#elif STM32_MSIRANGE == STM32_MSIRANGE_256K
620#define STM32_MSICLK 262000
621#elif STM32_MSIRANGE == STM32_MSIRANGE_512K
622#define STM32_MSICLK 524000
623#elif STM32_MSIRANGE == STM32_MSIRANGE_1M
624#define STM32_MSICLK 1050000
625#elif STM32_MSIRANGE == STM32_MSIRANGE_2M
626#define STM32_MSICLK 2100000
627#elif STM32_MSIRANGE == STM32_MSIRANGE_4M
628#define STM32_MSICLK 4200000
629#else
630#error "invalid STM32_MSIRANGE value specified"
631#endif
632
633/**
634 * @brief System clock source.
635 */
636#if STM32_NO_INIT || defined(__DOXYGEN__)
637#define STM32_SYSCLK 2100000
638#elif (STM32_SW == STM32_SW_MSI)
639#define STM32_SYSCLK STM32_MSICLK
640#elif (STM32_SW == STM32_SW_HSI)
641#define STM32_SYSCLK STM32_HSICLK
642#elif (STM32_SW == STM32_SW_HSE)
643#define STM32_SYSCLK STM32_HSECLK
644#elif (STM32_SW == STM32_SW_PLL)
645#define STM32_SYSCLK STM32_PLLCLKOUT
646#else
647#error "invalid STM32_SW value specified"
648#endif
649
650/* Check on the system clock.*/
651#if STM32_SYSCLK > STM32_SYSCLK_MAX
652#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
653#endif
654
655/**
656 * @brief AHB frequency.
657 */
658#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
659#define STM32_HCLK (STM32_SYSCLK / 1)
660#elif STM32_HPRE == STM32_HPRE_DIV2
661#define STM32_HCLK (STM32_SYSCLK / 2)
662#elif STM32_HPRE == STM32_HPRE_DIV4
663#define STM32_HCLK (STM32_SYSCLK / 4)
664#elif STM32_HPRE == STM32_HPRE_DIV8
665#define STM32_HCLK (STM32_SYSCLK / 8)
666#elif STM32_HPRE == STM32_HPRE_DIV16
667#define STM32_HCLK (STM32_SYSCLK / 16)
668#elif STM32_HPRE == STM32_HPRE_DIV64
669#define STM32_HCLK (STM32_SYSCLK / 64)
670#elif STM32_HPRE == STM32_HPRE_DIV128
671#define STM32_HCLK (STM32_SYSCLK / 128)
672#elif STM32_HPRE == STM32_HPRE_DIV256
673#define STM32_HCLK (STM32_SYSCLK / 256)
674#elif STM32_HPRE == STM32_HPRE_DIV512
675#define STM32_HCLK (STM32_SYSCLK / 512)
676#else
677#error "invalid STM32_HPRE value specified"
678#endif
679
680/* AHB frequency check.*/
681#if STM32_HCLK > STM32_SYSCLK_MAX
682#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
683#endif
684
685/**
686 * @brief APB1 frequency.
687 */
688#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
689#define STM32_PCLK1 (STM32_HCLK / 1)
690#elif STM32_PPRE1 == STM32_PPRE1_DIV2
691#define STM32_PCLK1 (STM32_HCLK / 2)
692#elif STM32_PPRE1 == STM32_PPRE1_DIV4
693#define STM32_PCLK1 (STM32_HCLK / 4)
694#elif STM32_PPRE1 == STM32_PPRE1_DIV8
695#define STM32_PCLK1 (STM32_HCLK / 8)
696#elif STM32_PPRE1 == STM32_PPRE1_DIV16
697#define STM32_PCLK1 (STM32_HCLK / 16)
698#else
699#error "invalid STM32_PPRE1 value specified"
700#endif
701
702/* APB1 frequency check.*/
703#if STM32_PCLK1 > STM32_PCLK1_MAX
704#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
705#endif
706
707/**
708 * @brief APB2 frequency.
709 */
710#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
711#define STM32_PCLK2 (STM32_HCLK / 1)
712#elif STM32_PPRE2 == STM32_PPRE2_DIV2
713#define STM32_PCLK2 (STM32_HCLK / 2)
714#elif STM32_PPRE2 == STM32_PPRE2_DIV4
715#define STM32_PCLK2 (STM32_HCLK / 4)
716#elif STM32_PPRE2 == STM32_PPRE2_DIV8
717#define STM32_PCLK2 (STM32_HCLK / 8)
718#elif STM32_PPRE2 == STM32_PPRE2_DIV16
719#define STM32_PCLK2 (STM32_HCLK / 16)
720#else
721#error "invalid STM32_PPRE2 value specified"
722#endif
723
724/* APB2 frequency check.*/
725#if STM32_PCLK2 > STM32_PCLK2_MAX
726#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
727#endif
728
729/**
730 * @brief MCO clock before divider.
731 */
732#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
733#define STM32_MCODIVCLK 0
734#elif STM32_MCOSEL == STM32_MCOSEL_HSI
735#define STM32_MCODIVCLK STM32_HSICLK
736#elif STM32_MCOSEL == STM32_MCOSEL_MSI
737#define STM32_MCODIVCLK STM32_MSICLK
738#elif STM32_MCOSEL == STM32_MCOSEL_HSE
739#define STM32_MCODIVCLK STM32_HSECLK
740#elif STM32_MCOSEL == STM32_MCOSEL_PLL
741#define STM32_MCODIVCLK STM32_PLLCLKOUT
742#elif STM32_MCOSEL == STM32_MCOSEL_LSI
743#define STM32_MCODIVCLK STM32_LSICLK
744#elif STM32_MCOSEL == STM32_MCOSEL_LSE
745#define STM32_MCODIVCLK STM32_LSECLK
746#else
747#error "invalid STM32_MCOSEL value specified"
748#endif
749
750/**
751 * @brief MCO output pin clock.
752 */
753#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
754#define STM32_MCOCLK STM32_MCODIVCLK
755#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
756#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
757#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
758#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
759#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
760#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
761#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
762#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
763#else
764#error "invalid STM32_MCOPRE value specified"
765#endif
766
767/**
768 * @brief HSE divider toward RTC clock.
769 */
770#if (STM32_RTCPRE == STM32_RTCPRE_DIV2) || defined(__DOXYGEN__)
771#define STM32_HSEDIVCLK (STM32_HSECLK / 2)
772#elif (STM32_RTCPRE == STM32_RTCPRE_DIV4) || defined(__DOXYGEN__)
773#define STM32_HSEDIVCLK (STM32_HSECLK / 4)
774#elif (STM32_RTCPRE == STM32_RTCPRE_DIV8) || defined(__DOXYGEN__)
775#define STM32_HSEDIVCLK (STM32_HSECLK / 8)
776#elif (STM32_RTCPRE == STM32_RTCPRE_DIV16) || defined(__DOXYGEN__)
777#define STM32_HSEDIVCLK (STM32_HSECLK / 16)
778#else
779#error "invalid STM32_RTCPRE value specified"
780#endif
781
782/**
783 * @brief RTC/LCD clock.
784 */
785#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
786#define STM32_RTCCLK 0
787#elif STM32_RTCSEL == STM32_RTCSEL_LSE
788#define STM32_RTCCLK STM32_LSECLK
789#elif STM32_RTCSEL == STM32_RTCSEL_LSI
790#define STM32_RTCCLK STM32_LSICLK
791#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
792#define STM32_RTCCLK STM32_HSEDIVCLK
793#else
794#error "invalid STM32_RTCSEL value specified"
795#endif
796
797/**
798 * @brief USB frequency.
799 */
800#define STM32_USBCLK (STM32_PLLVCO / 2)
801
802/**
803 * @brief Timers 2, 3, 4, 6, 7 clock.
804 */
805#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
806#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
807#else
808#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
809#endif
810
811/**
812 * @brief Timers 9, 10, 11 clock.
813 */
814#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
815#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
816#else
817#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
818#endif
819
820/**
821 * @brief Flash settings.
822 */
823#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
824#define STM32_FLASHBITS1 0x00000000
825#else
826#define STM32_FLASHBITS1 0x00000004
827#define STM32_FLASHBITS2 0x00000007
828#endif
829
830/*===========================================================================*/
831/* Driver data structures and types. */
832/*===========================================================================*/
833
834/*===========================================================================*/
835/* Driver macros. */
836/*===========================================================================*/
837
838/*===========================================================================*/
839/* External declarations. */
840/*===========================================================================*/
841
842/* Various helpers.*/
843#include "nvic.h"
844#include "cache.h"
845#include "mpu_v7m.h"
846#include "stm32_isr.h"
847#include "stm32_dma.h"
848#include "stm32_exti.h"
849#include "stm32_rcc.h"
850#include "stm32_tim.h"
851
852#ifdef __cplusplus
853extern "C" {
854#endif
855 void hal_lld_init(void);
856 void stm32_clock_init(void);
857#ifdef __cplusplus
858}
859#endif
860
861#endif /* HAL_LLD_H */
862
863/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32L1xx/platform.dox b/lib/chibios/os/hal/ports/STM32/STM32L1xx/platform.dox
new file mode 100644
index 000000000..09dc6742e
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32L1xx/platform.dox
@@ -0,0 +1,315 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @defgroup STM32L1xx_DRIVERS STM32L1xx Drivers
19 * @details This section describes all the supported drivers on the STM32L1xx
20 * platform and the implementation details of the single drivers.
21 *
22 * @ingroup platforms
23 */
24
25/**
26 * @defgroup STM32L1xx_HAL STM32L1xx Initialization Support
27 * @details The STM32L1xx HAL support is responsible for system initialization.
28 *
29 * @section stm32l1xx_hal_1 Supported HW resources
30 * - PLL1.
31 * - RCC.
32 * - Flash.
33 * .
34 * @section stm32l1xx_hal_2 STM32L1xx HAL driver implementation features
35 * - PLL startup and stabilization.
36 * - Clock tree initialization.
37 * - Clock source selection.
38 * - Flash wait states initialization based on the selected clock options.
39 * - SYSTICK initialization based on current clock and kernel required rate.
40 * - DMA support initialization.
41 * .
42 * @ingroup STM32L1xx_DRIVERS
43 */
44
45/**
46 * @defgroup STM32L1xx_ADC STM32L1xx ADC Support
47 * @details The STM32L1xx ADC driver supports the ADC peripherals using DMA
48 * channels for maximum performance.
49 *
50 * @section stm32l1xx_adc_1 Supported HW resources
51 * - ADC1.
52 * - DMA1.
53 * .
54 * @section stm32l1xx_adc_2 STM32L1xx ADC driver implementation features
55 * - Clock stop for reduced power usage when the driver is in stop state.
56 * - Streaming conversion using DMA for maximum performance.
57 * - Programmable ADC interrupt priority level.
58 * - Programmable DMA bus priority for each DMA channel.
59 * - Programmable DMA interrupt priority for each DMA channel.
60 * - DMA and ADC errors detection.
61 * .
62 * @ingroup STM32L1xx_DRIVERS
63 */
64
65/**
66 * @defgroup STM32L1xx_EXT STM32L1xx EXT Support
67 * @details The STM32L1xx EXT driver uses the EXTI peripheral.
68 *
69 * @section stm32l1xx_ext_1 Supported HW resources
70 * - EXTI.
71 * .
72 * @section stm32l1xx_ext_2 STM32L1xx EXT driver implementation features
73 * - Each EXTI channel can be independently enabled and programmed.
74 * - Programmable EXTI interrupts priority level.
75 * - Capability to work as event sources (WFE) rather than interrupt sources.
76 * .
77 * @ingroup STM32L1xx_DRIVERS
78 */
79
80/**
81 * @defgroup STM32L1xx_GPT STM32L1xx GPT Support
82 * @details The STM32L1xx GPT driver uses the TIMx peripherals.
83 *
84 * @section stm32l1xx_gpt_1 Supported HW resources
85 * - TIM2.
86 * - TIM3.
87 * - TIM4.
88 * .
89 * @section stm32l1xx_gpt_2 STM32L1xx GPT driver implementation features
90 * - Each timer can be independently enabled and programmed. Unused
91 * peripherals are left in low power mode.
92 * - Programmable TIMx interrupts priority level.
93 * .
94 * @ingroup STM32L1xx_DRIVERS
95 */
96
97/**
98 * @defgroup STM32L1xx_ICU STM32L1xx ICU Support
99 * @details The STM32L1xx ICU driver uses the TIMx peripherals.
100 *
101 * @section stm32l1xx_icu_1 Supported HW resources
102 * - TIM2.
103 * - TIM3.
104 * - TIM4.
105 * .
106 * @section stm32l1xx_icu_2 STM32L1xx ICU driver implementation features
107 * - Each timer can be independently enabled and programmed. Unused
108 * peripherals are left in low power mode.
109 * - Programmable TIMx interrupts priority level.
110 * .
111 * @ingroup STM32L1xx_DRIVERS
112 */
113
114/**
115 * @defgroup STM32L1xx_PAL STM32L1xx PAL Support
116 * @details The STM32L1xx PAL driver uses the GPIO peripherals.
117 *
118 * @section stm32l1xx_pal_1 Supported HW resources
119 * - GPIOA.
120 * - GPIOB.
121 * - GPIOC.
122 * - GPIOD.
123 * - GPIOE.
124 * - GPIOH.
125 * .
126 * @section stm32l1xx_pal_2 STM32L1xx PAL driver implementation features
127 * The PAL driver implementation fully supports the following hardware
128 * capabilities:
129 * - 16 bits wide ports.
130 * - Atomic set/reset functions.
131 * - Atomic set+reset function (atomic bus operations).
132 * - Output latched regardless of the pad setting.
133 * - Direct read of input pads regardless of the pad setting.
134 * .
135 * @section stm32l1xx_pal_3 Supported PAL setup modes
136 * The STM32L1xx PAL driver supports the following I/O modes:
137 * - @p PAL_MODE_RESET.
138 * - @p PAL_MODE_UNCONNECTED.
139 * - @p PAL_MODE_INPUT.
140 * - @p PAL_MODE_INPUT_PULLUP.
141 * - @p PAL_MODE_INPUT_PULLDOWN.
142 * - @p PAL_MODE_INPUT_ANALOG.
143 * - @p PAL_MODE_OUTPUT_PUSHPULL.
144 * - @p PAL_MODE_OUTPUT_OPENDRAIN.
145 * - @p PAL_MODE_ALTERNATE (non standard).
146 * .
147 * Any attempt to setup an invalid mode is ignored.
148 *
149 * @section stm32l1xx_pal_4 Suboptimal behavior
150 * The STM32L1xx GPIO is less than optimal in several areas, the limitations
151 * should be taken in account while using the PAL driver:
152 * - Pad/port toggling operations are not atomic.
153 * - Pad/group mode setup is not atomic.
154 * .
155 * @ingroup STM32L1xx_DRIVERS
156 */
157
158/**
159 * @defgroup STM32L1xx_PWM STM32L1xx PWM Support
160 * @details The STM32L1xx PWM driver uses the TIMx peripherals.
161 *
162 * @section stm32l1xx_pwm_1 Supported HW resources
163 * - TIM1.
164 * - TIM2.
165 * - TIM3.
166 * - TIM4.
167 * .
168 * @section stm32l1xx_pwm_2 STM32L1xx PWM driver implementation features
169 * - Each timer can be independently enabled and programmed. Unused
170 * peripherals are left in low power mode.
171 * - Four independent PWM channels per timer.
172 * - Programmable TIMx interrupts priority level.
173 * .
174 * @ingroup STM32L1xx_DRIVERS
175 */
176
177/**
178 * @defgroup STM32L1xx_SERIAL STM32L1xx Serial Support
179 * @details The STM32L1xx Serial driver uses the USART/UART peripherals in a
180 * buffered, interrupt driven, implementation.
181 *
182 * @section stm32l1xx_serial_1 Supported HW resources
183 * The serial driver can support any of the following hardware resources:
184 * - USART1.
185 * - USART2.
186 * - USART3 (where present).
187 * - UART4 (where present).
188 * - UART5 (where present).
189 * .
190 * @section stm32l1xx_serial_2 STM32L1xx Serial driver implementation features
191 * - Clock stop for reduced power usage when the driver is in stop state.
192 * - Each UART/USART can be independently enabled and programmed. Unused
193 * peripherals are left in low power mode.
194 * - Fully interrupt driven.
195 * - Programmable priority levels for each UART/USART.
196 * .
197 * @ingroup STM32L1xx_DRIVERS
198 */
199
200/**
201 * @defgroup STM32L1xx_SPI STM32L1xx SPI Support
202 * @details The SPI driver supports the STM32L1xx SPI peripherals using DMA
203 * channels for maximum performance.
204 *
205 * @section stm32l1xx_spi_1 Supported HW resources
206 * - SPI1.
207 * - SPI2.
208 * - SPI3 (where present).
209 * - DMA1.
210 * - DMA2 (where present).
211 * .
212 * @section stm32l1xx_spi_2 STM32L1xx SPI driver implementation features
213 * - Clock stop for reduced power usage when the driver is in stop state.
214 * - Each SPI can be independently enabled and programmed. Unused
215 * peripherals are left in low power mode.
216 * - Programmable interrupt priority levels for each SPI.
217 * - DMA is used for receiving and transmitting.
218 * - Programmable DMA bus priority for each DMA channel.
219 * - Programmable DMA interrupt priority for each DMA channel.
220 * - Programmable DMA error hook.
221 * .
222 * @ingroup STM32L1xx_DRIVERS
223 */
224
225/**
226 * @defgroup STM32L1xx_UART STM32L1xx UART Support
227 * @details The UART driver supports the STM32L1xx USART peripherals using DMA
228 * channels for maximum performance.
229 *
230 * @section stm32l1xx_uart_1 Supported HW resources
231 * The UART driver can support any of the following hardware resources:
232 * - USART1.
233 * - USART2.
234 * - USART3 (where present).
235 * - DMA1.
236 * .
237 * @section stm32l1xx_uart_2 STM32L1xx UART driver implementation features
238 * - Clock stop for reduced power usage when the driver is in stop state.
239 * - Each UART/USART can be independently enabled and programmed. Unused
240 * peripherals are left in low power mode.
241 * - Programmable interrupt priority levels for each UART/USART.
242 * - DMA is used for receiving and transmitting.
243 * - Programmable DMA bus priority for each DMA channel.
244 * - Programmable DMA interrupt priority for each DMA channel.
245 * - Programmable DMA error hook.
246 * .
247 * @ingroup STM32L1xx_DRIVERS
248 */
249
250/**
251 * @defgroup STM32L1xx_USB STM32L1xx USB Support
252 * @details The USB driver supports the STM32L1xx USB peripheral.
253 *
254 * @section stm32l1xx_usb_1 Supported HW resources
255 * The USB driver can support any of the following hardware resources:
256 * - USB.
257 * .
258 * @section stm32l1xx_usb_2 STM32L1xx USB driver implementation features
259 * - Clock stop for reduced power usage when the driver is in stop state.
260 * - Programmable interrupt priority levels.
261 * - Each endpoint programmable in Control, Bulk and Interrupt modes.
262 * .
263 * @ingroup STM32L1xx_DRIVERS
264 */
265
266/**
267 * @defgroup STM32L1xx_PLATFORM_DRIVERS STM32L1xx Platform Drivers
268 * @details Platform support drivers. Platform drivers do not implement HAL
269 * standard driver templates, their role is to support platform
270 * specific functionalities.
271 *
272 * @ingroup STM32L1xx_DRIVERS
273 */
274
275/**
276 * @defgroup STM32L1xx_DMA STM32L1xx DMA Support
277 * @details This DMA helper driver is used by the other drivers in order to
278 * access the shared DMA resources in a consistent way.
279 *
280 * @section stm32l1xx_dma_1 Supported HW resources
281 * The DMA driver can support any of the following hardware resources:
282 * - DMA1.
283 * .
284 * @section stm32l1xx_dma_2 STM32L1xx DMA driver implementation features
285 * - Exports helper functions/macros to the other drivers that share the
286 * DMA resource.
287 * - Automatic DMA clock stop when not in use by any driver.
288 * - DMA streams and interrupt vectors sharing among multiple drivers.
289 * .
290 * @ingroup STM32L1xx_PLATFORM_DRIVERS
291 */
292
293/**
294 * @defgroup STM32L1xx_ISR STM32L1xx ISR Support
295 * @details This ISR helper driver is used by the other drivers in order to
296 * map ISR names to physical vector names.
297 *
298 * @ingroup STM32L1xx_PLATFORM_DRIVERS
299 */
300
301/**
302 * @defgroup STM32L1xx_RCC STM32L1xx RCC Support
303 * @details This RCC helper driver is used by the other drivers in order to
304 * access the shared RCC resources in a consistent way.
305 *
306 * @section stm32f1xx_rcc_1 Supported HW resources
307 * - RCC.
308 * .
309 * @section stm32l1xx_rcc_2 STM32L1xx RCC driver implementation features
310 * - Peripherals reset.
311 * - Peripherals clock enable.
312 * - Peripherals clock disable.
313 * .
314 * @ingroup STM32L1xx_PLATFORM_DRIVERS
315 */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32L1xx/platform.mk b/lib/chibios/os/hal/ports/STM32/STM32L1xx/platform.mk
new file mode 100644
index 000000000..7510bac10
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32L1xx/platform.mk
@@ -0,0 +1,46 @@
1# Required platform files.
2PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
3 $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/stm32_isr.c \
4 $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_lld.c
5
6# Required include directories.
7PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
8 $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx
9
10# Optional platform files.
11ifeq ($(USE_SMART_BUILD),yes)
12
13# Configuration files directory
14ifeq ($(HALCONFDIR),)
15 ifeq ($(CONFDIR),)
16 HALCONFDIR = .
17 else
18 HALCONFDIR := $(CONFDIR)
19 endif
20endif
21
22HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
23
24ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
25PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c
26endif
27else
28PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c
29endif
30
31# Drivers compatible with the platform.
32include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
33include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
34include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
35include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
36include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/driver.mk
37include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
38include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/driver.mk
39include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
40include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/driver.mk
41include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
42include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
43
44# Shared variables
45ALLCSRC += $(PLATFORMSRC)
46ALLINC += $(PLATFORMINC)
diff --git a/lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_isr.c b/lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_isr.c
new file mode 100644
index 000000000..0f2f7c8c8
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_isr.c
@@ -0,0 +1,255 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32L1xx/stm32_isr.c
19 * @brief STM32L1xx ISR handler code.
20 *
21 * @addtogroup STM32L1xx_ISR
22 * @{
23 */
24
25#include "hal.h"
26
27/*===========================================================================*/
28/* Driver local definitions. */
29/*===========================================================================*/
30
31/*===========================================================================*/
32/* Driver exported variables. */
33/*===========================================================================*/
34
35/*===========================================================================*/
36/* Driver local variables. */
37/*===========================================================================*/
38
39/*===========================================================================*/
40/* Driver local functions. */
41/*===========================================================================*/
42
43#define exti_serve_irq(pr, channel) { \
44 \
45 if ((pr) & (1U << (channel))) { \
46 _pal_isr_code(channel); \
47 } \
48}
49
50/*===========================================================================*/
51/* Driver interrupt handlers. */
52/*===========================================================================*/
53
54#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__)
55#if !defined(STM32_DISABLE_EXTI0_HANDLER)
56/**
57 * @brief EXTI[0] interrupt handler.
58 *
59 * @isr
60 */
61OSAL_IRQ_HANDLER(Vector58) {
62 uint32_t pr;
63
64 OSAL_IRQ_PROLOGUE();
65
66 pr = EXTI->PR;
67 pr &= EXTI->IMR & (1U << 0);
68 EXTI->PR = pr;
69
70 exti_serve_irq(pr, 0);
71
72 OSAL_IRQ_EPILOGUE();
73}
74#endif
75
76#if !defined(STM32_DISABLE_EXTI1_HANDLER)
77/**
78 * @brief EXTI[1] interrupt handler.
79 *
80 * @isr
81 */
82OSAL_IRQ_HANDLER(Vector5C) {
83 uint32_t pr;
84
85 OSAL_IRQ_PROLOGUE();
86
87 pr = EXTI->PR;
88 pr &= EXTI->IMR & (1U << 1);
89 EXTI->PR = pr;
90
91 exti_serve_irq(pr, 1);
92
93 OSAL_IRQ_EPILOGUE();
94}
95#endif
96
97#if !defined(STM32_DISABLE_EXTI2_HANDLER)
98/**
99 * @brief EXTI[2] interrupt handler.
100 *
101 * @isr
102 */
103OSAL_IRQ_HANDLER(Vector60) {
104 uint32_t pr;
105
106 OSAL_IRQ_PROLOGUE();
107
108 pr = EXTI->PR;
109 pr &= EXTI->IMR & (1U << 2);
110 EXTI->PR = pr;
111
112 exti_serve_irq(pr, 2);
113
114 OSAL_IRQ_EPILOGUE();
115}
116#endif
117
118#if !defined(STM32_DISABLE_EXTI3_HANDLER)
119/**
120 * @brief EXTI[3] interrupt handler.
121 *
122 * @isr
123 */
124OSAL_IRQ_HANDLER(Vector64) {
125 uint32_t pr;
126
127 OSAL_IRQ_PROLOGUE();
128
129 pr = EXTI->PR;
130 pr &= EXTI->IMR & (1U << 3);
131 EXTI->PR = pr;
132
133 exti_serve_irq(pr, 3);
134
135 OSAL_IRQ_EPILOGUE();
136}
137#endif
138
139#if !defined(STM32_DISABLE_EXTI4_HANDLER)
140/**
141 * @brief EXTI[4] interrupt handler.
142 *
143 * @isr
144 */
145OSAL_IRQ_HANDLER(Vector68) {
146 uint32_t pr;
147
148 OSAL_IRQ_PROLOGUE();
149
150 pr = EXTI->PR;
151 pr &= EXTI->IMR & (1U << 4);
152 EXTI->PR = pr;
153
154 exti_serve_irq(pr, 4);
155
156 OSAL_IRQ_EPILOGUE();
157}
158#endif
159
160#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
161/**
162 * @brief EXTI[5]...EXTI[9] interrupt handler.
163 *
164 * @isr
165 */
166OSAL_IRQ_HANDLER(Vector9C) {
167 uint32_t pr;
168
169 OSAL_IRQ_PROLOGUE();
170
171 pr = EXTI->PR;
172 pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
173 (1U << 9));
174 EXTI->PR = pr;
175
176 exti_serve_irq(pr, 5);
177 exti_serve_irq(pr, 6);
178 exti_serve_irq(pr, 7);
179 exti_serve_irq(pr, 8);
180 exti_serve_irq(pr, 9);
181
182 OSAL_IRQ_EPILOGUE();
183}
184#endif
185
186#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
187/**
188 * @brief EXTI[10]...EXTI[15] interrupt handler.
189 *
190 * @isr
191 */
192OSAL_IRQ_HANDLER(VectorE0) {
193 uint32_t pr;
194
195 OSAL_IRQ_PROLOGUE();
196
197 pr = EXTI->PR;
198 pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
199 (1U << 14) | (1U << 15));
200 EXTI->PR = pr;
201
202 exti_serve_irq(pr, 10);
203 exti_serve_irq(pr, 11);
204 exti_serve_irq(pr, 12);
205 exti_serve_irq(pr, 13);
206 exti_serve_irq(pr, 14);
207 exti_serve_irq(pr, 15);
208
209 OSAL_IRQ_EPILOGUE();
210}
211#endif
212
213#endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */
214
215/*===========================================================================*/
216/* Driver exported functions. */
217/*===========================================================================*/
218
219/**
220 * @brief Enables IRQ sources.
221 *
222 * @notapi
223 */
224void irqInit(void) {
225
226#if HAL_USE_PAL
227 nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY);
228 nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY);
229 nvicEnableVector(EXTI2_IRQn, STM32_IRQ_EXTI2_PRIORITY);
230 nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY);
231 nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY);
232 nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY);
233 nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY);
234#endif
235}
236
237/**
238 * @brief Disables IRQ sources.
239 *
240 * @notapi
241 */
242void irqDeinit(void) {
243
244#if HAL_USE_PAL
245 nvicDisableVector(EXTI0_IRQn);
246 nvicDisableVector(EXTI1_IRQn);
247 nvicDisableVector(EXTI2_IRQn);
248 nvicDisableVector(EXTI3_IRQn);
249 nvicDisableVector(EXTI4_IRQn);
250 nvicDisableVector(EXTI9_5_IRQn);
251 nvicDisableVector(EXTI15_10_IRQn);
252#endif
253}
254
255/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_isr.h b/lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_isr.h
new file mode 100644
index 000000000..6919a1217
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_isr.h
@@ -0,0 +1,230 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32L1xx/stm32_isr.h
19 * @brief STM32L1xx ISR handler header.
20 *
21 * @addtogroup STM32L1xx_ISR
22 * @{
23 */
24
25#ifndef STM32_ISR_H
26#define STM32_ISR_H
27
28/*===========================================================================*/
29/* Driver constants. */
30/*===========================================================================*/
31
32/**
33 * @name ISR names and numbers remapping
34 * @{
35 */
36/*
37 * I2C units.
38 */
39#define STM32_I2C1_EVENT_HANDLER VectorBC
40#define STM32_I2C1_ERROR_HANDLER VectorC0
41#define STM32_I2C1_EVENT_NUMBER 31
42#define STM32_I2C1_ERROR_NUMBER 32
43
44#define STM32_I2C2_EVENT_HANDLER VectorC4
45#define STM32_I2C2_ERROR_HANDLER VectorC8
46#define STM32_I2C2_EVENT_NUMBER 33
47#define STM32_I2C2_ERROR_NUMBER 34
48
49/*
50 * TIM units.
51 */
52#define STM32_TIM2_HANDLER VectorB0
53#define STM32_TIM3_HANDLER VectorB4
54#define STM32_TIM4_HANDLER VectorB8
55#define STM32_TIM5_HANDLER VectorF8
56#define STM32_TIM6_HANDLER VectorEC
57#define STM32_TIM7_HANDLER VectorF0
58#define STM32_TIM9_HANDLER VectorA4
59#define STM32_TIM10_HANDLER VectorA8
60#define STM32_TIM11_HANDLER VectorAC
61
62#define STM32_TIM2_NUMBER 28
63#define STM32_TIM3_NUMBER 29
64#define STM32_TIM4_NUMBER 30
65#define STM32_TIM5_NUMBER 46
66#define STM32_TIM6_NUMBER 43
67#define STM32_TIM7_NUMBER 44
68#define STM32_TIM9_NUMBER 25
69#define STM32_TIM10_NUMBER 26
70#define STM32_TIM11_NUMBER 27
71
72/*
73 * USART units.
74 */
75#define STM32_USART1_HANDLER VectorD4
76#define STM32_USART2_HANDLER VectorD8
77#define STM32_USART3_HANDLER VectorDC
78#define STM32_UART4_HANDLER Vector100
79#define STM32_UART5_HANDLER Vector104
80
81#define STM32_USART1_NUMBER 37
82#define STM32_USART2_NUMBER 38
83#define STM32_USART3_NUMBER 39
84#define STM32_UART4_NUMBER 48
85#define STM32_UART5_NUMBER 49
86/*
87 * USB units.
88 */
89#define STM32_USB1_HP_HANDLER Vector8C
90#define STM32_USB1_LP_HANDLER Vector90
91
92#define STM32_USB1_HP_NUMBER 19
93#define STM32_USB1_LP_NUMBER 20
94/** @} */
95
96/*===========================================================================*/
97/* Driver pre-compile time settings. */
98/*===========================================================================*/
99
100/**
101 * @name Configuration options
102 * @{
103 */
104/**
105 * @brief EXTI0 interrupt priority level setting.
106 */
107#if !defined(STM32_IRQ_EXTI0_PRIORITY) || defined(__DOXYGEN__)
108#define STM32_IRQ_EXTI0_PRIORITY 6
109#endif
110
111/**
112 * @brief EXTI1 interrupt priority level setting.
113 */
114#if !defined(STM32_IRQ_EXTI1_PRIORITY) || defined(__DOXYGEN__)
115#define STM32_IRQ_EXTI1_PRIORITY 6
116#endif
117
118/**
119 * @brief EXTI2 interrupt priority level setting.
120 */
121#if !defined(STM32_IRQ_EXTI2_PRIORITY) || defined(__DOXYGEN__)
122#define STM32_IRQ_EXTI2_PRIORITY 6
123#endif
124
125/**
126 * @brief EXTI3 interrupt priority level setting.
127 */
128#if !defined(STM32_IRQ_EXTI3_PRIORITY) || defined(__DOXYGEN__)
129#define STM32_IRQ_EXTI3_PRIORITY 6
130#endif
131
132/**
133 * @brief EXTI4 interrupt priority level setting.
134 */
135#if !defined(STM32_IRQ_EXTI4_PRIORITY) || defined(__DOXYGEN__)
136#define STM32_IRQ_EXTI4_PRIORITY 6
137#endif
138
139/**
140 * @brief EXTI9..5 interrupt priority level setting.
141 */
142#if !defined(STM32_IRQ_EXTI5_9_PRIORITY) || defined(__DOXYGEN__)
143#define STM32_IRQ_EXTI5_9_PRIORITY 6
144#endif
145
146/**
147 * @brief EXTI15..10 interrupt priority level setting.
148 */
149#if !defined(STM32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__)
150#define STM32_IRQ_EXTI10_15_PRIORITY 6
151#endif
152
153/**
154 * @brief EXTI16 interrupt priority level setting.
155 */
156#if !defined(STM32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__)
157#define STM32_IRQ_EXTI16_PRIORITY 6
158#endif
159
160/**
161 * @brief EXTI17 interrupt priority level setting.
162 */
163#if !defined(STM32_IRQ_EXTI17_PRIORITY) || defined(__DOXYGEN__)
164#define STM32_IRQ_EXTI17_PRIORITY 6
165#endif
166
167/**
168 * @brief EXTI18 interrupt priority level setting.
169 */
170#if !defined(STM32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__)
171#define STM32_IRQ_EXTI18_PRIORITY 6
172#endif
173
174/**
175 * @brief EXTI19 interrupt priority level setting.
176 */
177#if !defined(STM32_IRQ_EXTI19_PRIORITY) || defined(__DOXYGEN__)
178#define STM32_IRQ_EXTI19_PRIORITY 6
179#endif
180
181/**
182 * @brief EXTI20 interrupt priority level setting.
183 */
184#if !defined(STM32_IRQ_EXTI20_PRIORITY) || defined(__DOXYGEN__)
185#define STM32_IRQ_EXTI20_PRIORITY 6
186#endif
187
188/**
189 * @brief EXTI21..22 interrupt priority level setting.
190 */
191#if !defined(STM32_IRQ_EXTI21_22_PRIORITY) || defined(__DOXYGEN__)
192#define STM32_IRQ_EXTI21_22_PRIORITY 6
193#endif
194
195/**
196 * @brief EXTI23 interrupt priority level setting.
197 */
198#if !defined(STM32_IRQ_EXTI23_PRIORITY) || defined(__DOXYGEN__)
199#define STM32_IRQ_EXTI23_PRIORITY 6
200#endif
201/** @} */
202
203/*===========================================================================*/
204/* Derived constants and error checks. */
205/*===========================================================================*/
206
207/*===========================================================================*/
208/* Driver data structures and types. */
209/*===========================================================================*/
210
211/*===========================================================================*/
212/* Driver macros. */
213/*===========================================================================*/
214
215/*===========================================================================*/
216/* External declarations. */
217/*===========================================================================*/
218
219#ifdef __cplusplus
220extern "C" {
221#endif
222 void irqInit(void);
223 void irqDeinit(void);
224#ifdef __cplusplus
225}
226#endif
227
228#endif /* STM32_ISR_H */
229
230/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h b/lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h
new file mode 100644
index 000000000..5c0d318d2
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h
@@ -0,0 +1,795 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32L1xx/stm32_rcc.h
19 * @brief RCC helper driver header.
20 * @note This file requires definitions from the ST header file
21 * @p stm32l1xx.h.
22 *
23 * @addtogroup STM32L1xx_RCC
24 * @{
25 */
26
27#ifndef STM32_RCC_H
28#define STM32_RCC_H
29
30/*===========================================================================*/
31/* Driver constants. */
32/*===========================================================================*/
33
34/*===========================================================================*/
35/* Driver pre-compile time settings. */
36/*===========================================================================*/
37
38/*===========================================================================*/
39/* Derived constants and error checks. */
40/*===========================================================================*/
41
42/*===========================================================================*/
43/* Driver data structures and types. */
44/*===========================================================================*/
45
46/*===========================================================================*/
47/* Driver macros. */
48/*===========================================================================*/
49
50/**
51 * @name Generic RCC operations
52 * @{
53 */
54/**
55 * @brief Enables the clock of one or more peripheral on the APB1 bus.
56 *
57 * @param[in] mask APB1 peripherals mask
58 * @param[in] lp low power enable flag
59 *
60 * @api
61 */
62#define rccEnableAPB1(mask, lp) { \
63 RCC->APB1ENR |= (mask); \
64 if (lp) \
65 RCC->APB1LPENR |= (mask); \
66 else \
67 RCC->APB1LPENR &= ~(mask); \
68 (void)RCC->APB1LPENR; \
69}
70
71/**
72 * @brief Disables the clock of one or more peripheral on the APB1 bus.
73 *
74 * @param[in] mask APB1 peripherals mask
75 *
76 * @api
77 */
78#define rccDisableAPB1(mask) { \
79 RCC->APB1ENR &= ~(mask); \
80 RCC->APB1LPENR &= ~(mask); \
81 (void)RCC->APB1LPENR; \
82}
83
84/**
85 * @brief Resets one or more peripheral on the APB1 bus.
86 *
87 * @param[in] mask APB1 peripherals mask
88 *
89 * @api
90 */
91#define rccResetAPB1(mask) { \
92 RCC->APB1RSTR |= (mask); \
93 RCC->APB1RSTR &= ~(mask); \
94 (void)RCC->APB1RSTR; \
95}
96
97/**
98 * @brief Enables the clock of one or more peripheral on the APB2 bus.
99 *
100 * @param[in] mask APB2 peripherals mask
101 * @param[in] lp low power enable flag
102 *
103 * @api
104 */
105#define rccEnableAPB2(mask, lp) { \
106 RCC->APB2ENR |= (mask); \
107 if (lp) \
108 RCC->APB2LPENR |= (mask); \
109 else \
110 RCC->APB2LPENR &= ~(mask); \
111 (void)RCC->APB2LPENR; \
112}
113
114/**
115 * @brief Disables the clock of one or more peripheral on the APB2 bus.
116 *
117 * @param[in] mask APB2 peripherals mask
118 *
119 * @api
120 */
121#define rccDisableAPB2(mask) { \
122 RCC->APB2ENR &= ~(mask); \
123 RCC->APB2LPENR &= ~(mask); \
124 (void)RCC->APB2LPENR; \
125}
126
127/**
128 * @brief Resets one or more peripheral on the APB2 bus.
129 *
130 * @param[in] mask APB2 peripherals mask
131 *
132 * @api
133 */
134#define rccResetAPB2(mask) { \
135 RCC->APB2RSTR |= (mask); \
136 RCC->APB2RSTR &= ~(mask); \
137 (void)RCC->APB2RSTR; \
138}
139
140/**
141 * @brief Enables the clock of one or more peripheral on the AHB bus.
142 *
143 * @param[in] mask AHB peripherals mask
144 * @param[in] lp low power enable flag
145 *
146 * @api
147 */
148#define rccEnableAHB(mask, lp) { \
149 RCC->AHBENR |= (mask); \
150 if (lp) \
151 RCC->AHBLPENR |= (mask); \
152 else \
153 RCC->AHBLPENR &= ~(mask); \
154 (void)RCC->AHBLPENR; \
155}
156
157/**
158 * @brief Disables the clock of one or more peripheral on the AHB bus.
159 *
160 * @param[in] mask AHB peripherals mask
161 *
162 * @api
163 */
164#define rccDisableAHB(mask) { \
165 RCC->AHBENR &= ~(mask); \
166 RCC->AHBLPENR &= ~(mask); \
167 (void)RCC->AHBLPENR; \
168}
169
170/**
171 * @brief Resets one or more peripheral on the AHB bus.
172 *
173 * @param[in] mask AHB peripherals mask
174 *
175 * @api
176 */
177#define rccResetAHB(mask) { \
178 RCC->AHBRSTR |= (mask); \
179 RCC->AHBRSTR &= ~(mask); \
180 (void)RCC->AHBRSTR; \
181}
182/** @} */
183
184/**
185 * @name ADC peripherals specific RCC operations
186 * @{
187 */
188/**
189 * @brief Enables the ADC1 peripheral clock.
190 *
191 * @param[in] lp low power enable flag
192 *
193 * @api
194 */
195#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
196
197/**
198 * @brief Disables the ADC1 peripheral clock.
199 *
200 * @api
201 */
202#define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN)
203
204/**
205 * @brief Resets the ADC1 peripheral.
206 *
207 * @api
208 */
209#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
210/** @} */
211
212/**
213 * @name DAC peripheral specific RCC operations
214 * @{
215 */
216/**
217 * @brief Enables the DAC1 peripheral clock.
218 *
219 * @param[in] lp low power enable flag
220 *
221 * @api
222 */
223#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
224
225/**
226 * @brief Disables the DAC1 peripheral clock.
227 *
228 * @api
229 */
230#define rccDisableDAC1() rccDisableAPB1(RCC_APB1ENR_DACEN)
231
232/**
233 * @brief Resets the DAC1 peripheral.
234 *
235 * @api
236 */
237#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
238/** @} */
239
240/**
241 * @name DMA peripheral specific RCC operations
242 * @{
243 */
244/**
245 * @brief Enables the DMA1 peripheral clock.
246 *
247 * @param[in] lp low power enable flag
248 *
249 * @api
250 */
251#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
252
253/**
254 * @brief Disables the DMA1 peripheral clock.
255 *
256 * @api
257 */
258#define rccDisableDMA1() rccDisableAHB(RCC_AHBENR_DMA1EN)
259
260/**
261 * @brief Resets the DMA1 peripheral.
262 *
263 * @api
264 */
265#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
266
267/**
268 * @brief Enables the DMA2 peripheral clock.
269 *
270 * @param[in] lp low power enable flag
271 *
272 * @api
273 */
274#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)
275
276/**
277 * @brief Disables the DMA2 peripheral clock.
278 *
279 * @api
280 */
281#define rccDisableDMA2() rccDisableAHB(RCC_AHBENR_DMA2EN)
282
283/**
284 * @brief Resets the DMA2 peripheral.
285 *
286 * @api
287 */
288#define rccResetDMA2() rccResetAHB(RCC_AHBRSTR_DMA2RST)
289/** @} */
290
291/**
292 * @name PWR interface specific RCC operations
293 * @{
294 */
295/**
296 * @brief Enables the PWR interface clock.
297 *
298 * @param[in] lp low power enable flag
299 *
300 * @api
301 */
302#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
303
304/**
305 * @brief Disables PWR interface clock.
306 *
307 * @api
308 */
309#define rccDisablePWRInterface() rccDisableAPB1(RCC_APB1ENR_PWREN)
310
311/**
312 * @brief Resets the PWR interface.
313 *
314 * @api
315 */
316#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
317/** @} */
318
319/**
320 * @name I2C peripherals specific RCC operations
321 * @{
322 */
323/**
324 * @brief Enables the I2C1 peripheral clock.
325 *
326 * @param[in] lp low power enable flag
327 *
328 * @api
329 */
330#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
331
332/**
333 * @brief Disables the I2C1 peripheral clock.
334 *
335 * @api
336 */
337#define rccDisableI2C1() rccDisableAPB1(RCC_APB1ENR_I2C1EN)
338
339/**
340 * @brief Resets the I2C1 peripheral.
341 *
342 * @api
343 */
344#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
345
346/**
347 * @brief Enables the I2C2 peripheral clock.
348 *
349 * @param[in] lp low power enable flag
350 *
351 * @api
352 */
353#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
354
355/**
356 * @brief Disables the I2C2 peripheral clock.
357 *
358 * @api
359 */
360#define rccDisableI2C2() rccDisableAPB1(RCC_APB1ENR_I2C2EN)
361
362/**
363 * @brief Resets the I2C2 peripheral.
364 *
365 * @api
366 */
367#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
368/** @} */
369
370/**
371 * @name SPI peripherals specific RCC operations
372 * @{
373 */
374/**
375 * @brief Enables the SPI1 peripheral clock.
376 *
377 * @param[in] lp low power enable flag
378 *
379 * @api
380 */
381#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
382
383/**
384 * @brief Disables the SPI1 peripheral clock.
385 *
386 * @api
387 */
388#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
389
390/**
391 * @brief Resets the SPI1 peripheral.
392 *
393 * @api
394 */
395#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
396
397/**
398 * @brief Enables the SPI2 peripheral clock.
399 *
400 * @param[in] lp low power enable flag
401 *
402 * @api
403 */
404#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
405
406/**
407 * @brief Disables the SPI2 peripheral clock.
408 *
409 * @api
410 */
411#define rccDisableSPI2() rccDisableAPB1(RCC_APB1ENR_SPI2EN)
412
413/**
414 * @brief Resets the SPI2 peripheral.
415 *
416 * @api
417 */
418#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
419/** @} */
420
421/**
422 * @name TIM peripherals specific RCC operations
423 * @{
424 */
425/**
426 * @brief Enables the TIM2 peripheral clock.
427 *
428 * @param[in] lp low power enable flag
429 *
430 * @api
431 */
432#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
433
434/**
435 * @brief Disables the TIM2 peripheral clock.
436 *
437 * @api
438 */
439#define rccDisableTIM2() rccDisableAPB1(RCC_APB1ENR_TIM2EN)
440
441/**
442 * @brief Resets the TIM2 peripheral.
443 *
444 * @api
445 */
446#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
447
448/**
449 * @brief Enables the TIM3 peripheral clock.
450 *
451 * @param[in] lp low power enable flag
452 *
453 * @api
454 */
455#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
456
457/**
458 * @brief Disables the TIM3 peripheral clock.
459 *
460 * @api
461 */
462#define rccDisableTIM3() rccDisableAPB1(RCC_APB1ENR_TIM3EN)
463
464/**
465 * @brief Resets the TIM3 peripheral.
466 *
467 * @api
468 */
469#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
470
471/**
472 * @brief Enables the TIM4 peripheral clock.
473 *
474 * @param[in] lp low power enable flag
475 *
476 * @api
477 */
478#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
479
480/**
481 * @brief Disables the TIM4 peripheral clock.
482 *
483 * @api
484 */
485#define rccDisableTIM4() rccDisableAPB1(RCC_APB1ENR_TIM4EN)
486
487/**
488 * @brief Resets the TIM4 peripheral.
489 *
490 * @api
491 */
492#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
493
494/**
495 * @brief Enables the TIM5 peripheral clock.
496 *
497 * @param[in] lp low power enable flag
498 *
499 * @api
500 */
501#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp)
502
503/**
504 * @brief Disables the TIM5 peripheral clock.
505 *
506 * @api
507 */
508#define rccDisableTIM5() rccDisableAPB1(RCC_APB1ENR_TIM5EN)
509
510/**
511 * @brief Resets the TIM5 peripheral.
512 *
513 * @api
514 */
515#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)
516
517/**
518 * @brief Enables the TIM6 peripheral clock.
519 *
520 * @param[in] lp low power enable flag
521 *
522 * @api
523 */
524#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
525
526/**
527 * @brief Disables the TIM6 peripheral clock.
528 *
529 * @api
530 */
531#define rccDisableTIM6() rccDisableAPB1(RCC_APB1ENR_TIM6EN)
532
533/**
534 * @brief Resets the TIM6 peripheral.
535 *
536 * @api
537 */
538#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
539
540/**
541 * @brief Enables the TIM7 peripheral clock.
542 *
543 * @param[in] lp low power enable flag
544 *
545 * @api
546 */
547#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
548
549/**
550 * @brief Disables the TIM7 peripheral clock.
551 *
552 * @api
553 */
554#define rccDisableTIM7() rccDisableAPB1(RCC_APB1ENR_TIM7EN)
555
556/**
557 * @brief Resets the TIM7 peripheral.
558 *
559 * @api
560 */
561#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
562
563/**
564 * @brief Enables the TIM9 peripheral clock.
565 *
566 * @param[in] lp low power enable flag
567 *
568 * @api
569 */
570#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp)
571
572/**
573 * @brief Disables the TIM9 peripheral clock.
574 *
575 * @api
576 */
577#define rccDisableTIM9() rccDisableAPB2(RCC_APB2ENR_TIM9EN)
578
579/**
580 * @brief Resets the TIM9 peripheral.
581 *
582 * @api
583 */
584#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST)
585
586/**
587 * @brief Enables the TIM10 peripheral clock.
588 *
589 * @param[in] lp low power enable flag
590 *
591 * @api
592 */
593#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp)
594
595/**
596 * @brief Disables the TIM10 peripheral clock.
597 *
598 * @api
599 */
600#define rccDisableTIM10() rccDisableAPB2(RCC_APB2ENR_TIM10EN)
601
602/**
603 * @brief Resets the TIM10 peripheral.
604 *
605 * @api
606 */
607#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST)
608
609/**
610 * @brief Enables the TIM10 peripheral clock.
611 *
612 * @param[in] lp low power enable flag
613 *
614 * @api
615 */
616#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp)
617
618/**
619 * @brief Disables the TIM11 peripheral clock.
620 *
621 * @api
622 */
623#define rccDisableTIM11() rccDisableAPB2(RCC_APB2ENR_TIM11EN)
624
625/**
626 * @brief Resets the TIM11 peripheral.
627 *
628 * @api
629 */
630#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST)
631
632/** @} */
633
634/**
635 * @name USART/UART peripherals specific RCC operations
636 * @{
637 */
638/**
639 * @brief Enables the USART1 peripheral clock.
640 *
641 * @param[in] lp low power enable flag
642 *
643 * @api
644 */
645#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
646
647/**
648 * @brief Disables the USART1 peripheral clock.
649 *
650 * @api
651 */
652#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
653
654/**
655 * @brief Resets the USART1 peripheral.
656 *
657 * @api
658 */
659#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
660
661/**
662 * @brief Enables the USART2 peripheral clock.
663 *
664 * @param[in] lp low power enable flag
665 *
666 * @api
667 */
668#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
669
670/**
671 * @brief Disables the USART2 peripheral clock.
672 *
673 * @api
674 */
675#define rccDisableUSART2() rccDisableAPB1(RCC_APB1ENR_USART2EN)
676
677/**
678 * @brief Resets the USART2 peripheral.
679 *
680 * @api
681 */
682#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
683
684/**
685 * @brief Enables the USART3 peripheral clock.
686 *
687 * @param[in] lp low power enable flag
688 *
689 * @api
690 */
691#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
692
693/**
694 * @brief Disables the USART3 peripheral clock.
695 *
696 * @api
697 */
698#define rccDisableUSART3() rccDisableAPB1(RCC_APB1ENR_USART3EN)
699
700/**
701 * @brief Resets the USART3 peripheral.
702 *
703 * @api
704 */
705#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
706
707/**
708 * @brief Enables the UART4 peripheral clock.
709 *
710 * @param[in] lp low power enable flag
711 *
712 * @api
713 */
714#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)
715
716/**
717 * @brief Disables the UART4 peripheral clock.
718 *
719 * @api
720 */
721#define rccDisableUART4() rccDisableAPB1(RCC_APB1ENR_UART4EN)
722
723/**
724 * @brief Resets the UART4 peripheral.
725 *
726 * @api
727 */
728#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)
729
730/**
731 * @brief Enables the UART5 peripheral clock.
732 *
733 * @param[in] lp low power enable flag
734 *
735 * @api
736 */
737#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)
738
739/**
740 * @brief Disables the UART5 peripheral clock.
741 *
742 * @api
743 */
744#define rccDisableUART5() rccDisableAPB1(RCC_APB1ENR_UART5EN)
745
746/**
747 * @brief Resets the UART5 peripheral.
748 *
749 * @api
750 */
751#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
752/** @} */
753
754/**
755 * @name USB peripheral specific RCC operations
756 * @{
757 */
758/**
759 * @brief Enables the USB peripheral clock.
760 *
761 * @param[in] lp low power enable flag
762 *
763 * @api
764 */
765#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
766
767/**
768 * @brief Disables the USB peripheral clock.
769 *
770 * @api
771 */
772#define rccDisableUSB() rccDisableAPB1(RCC_APB1ENR_USBEN)
773
774/**
775 * @brief Resets the USB peripheral.
776 *
777 * @api
778 */
779#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
780/** @} */
781
782/*===========================================================================*/
783/* External declarations. */
784/*===========================================================================*/
785
786#ifdef __cplusplus
787extern "C" {
788#endif
789#ifdef __cplusplus
790}
791#endif
792
793#endif /* STM32_RCC_H */
794
795/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_registry.h b/lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
new file mode 100644
index 000000000..8e0b28525
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
@@ -0,0 +1,377 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32L1xx/stm32_registry.h
19 * @brief STM32L1xx capabilities registry.
20 *
21 * @addtogroup HAL
22 * @{
23 */
24
25#ifndef STM32_REGISTRY_H
26#define STM32_REGISTRY_H
27
28#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
29#define STM32L1XX_PROD_CAT 1
30
31#elif defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)
32#define STM32L1XX_PROD_CAT 2
33
34#elif defined(STM32L100xC) || defined(STM32L151xC) || \
35 defined(STM32L151xCA) || defined(STM32L152xC) || \
36 defined(STM32L152xCA) || defined(STM32L162xC) || \
37 defined(STM32L162xCA)
38#define STM32L1XX_PROD_CAT 3
39
40#elif defined(STM32L151xD) || defined(STM32L152xD) || \
41 defined(STM32L162xD)
42#define STM32L1XX_PROD_CAT 4
43
44#elif defined(STM32L151xE) || defined (STM32L152xE) || \
45 defined(STM32L162xE)
46#define STM32L1XX_PROD_CAT 5
47
48#elif defined(STM32L151xDX) || defined (STM32L152xDX) || \
49 defined(STM32L162xDX)
50#define STM32L1XX_PROD_CAT 6
51
52#else
53#error "STM32L1xx device not specified"
54#endif
55
56#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)
57#define STM32L1XX_VALUE_LINE TRUE
58#else
59#define STM32L1XX_VALUE_LINE FALSE
60#endif
61
62/*===========================================================================*/
63/* Platform capabilities. */
64/*===========================================================================*/
65
66/**
67 * @name STM32L1xx capabilities
68 * @{
69 */
70/* ADC attributes.*/
71#define STM32_HAS_ADC1 TRUE
72#define STM32_HAS_ADC2 FALSE
73#define STM32_HAS_ADC3 FALSE
74#define STM32_HAS_ADC4 FALSE
75
76/* CAN attributes.*/
77#define STM32_HAS_CAN1 FALSE
78#define STM32_HAS_CAN2 FALSE
79#define STM32_HAS_CAN3 FALSE
80
81/* DAC attributes.*/
82#define STM32_HAS_DAC1_CH1 TRUE
83#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
84
85#define STM32_HAS_DAC1_CH2 TRUE
86#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
87
88#define STM32_HAS_DAC2_CH1 FALSE
89#define STM32_HAS_DAC2_CH2 FALSE
90
91/* DMA attributes.*/
92#define STM32_ADVANCED_DMA FALSE
93#define STM32_DMA_SUPPORTS_DMAMUX FALSE
94#define STM32_DMA_SUPPORTS_CSELR FALSE
95
96#define STM32_DMA1_NUM_CHANNELS 7
97#define STM32_DMA1_CH1_HANDLER Vector6C
98#define STM32_DMA1_CH2_HANDLER Vector70
99#define STM32_DMA1_CH3_HANDLER Vector74
100#define STM32_DMA1_CH4_HANDLER Vector78
101#define STM32_DMA1_CH5_HANDLER Vector7C
102#define STM32_DMA1_CH6_HANDLER Vector80
103#define STM32_DMA1_CH7_HANDLER Vector84
104#define STM32_DMA1_CH1_NUMBER 11
105#define STM32_DMA1_CH2_NUMBER 12
106#define STM32_DMA1_CH3_NUMBER 13
107#define STM32_DMA1_CH4_NUMBER 14
108#define STM32_DMA1_CH5_NUMBER 15
109#define STM32_DMA1_CH6_NUMBER 16
110#define STM32_DMA1_CH7_NUMBER 17
111
112#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
113 defined(__DOXYGEN__)
114#define STM32_DMA2_NUM_CHANNELS 0
115#else
116#define STM32_DMA2_NUM_CHANNELS 5
117#define STM32_DMA2_CH1_HANDLER Vector108
118#define STM32_DMA2_CH2_HANDLER Vector10C
119#define STM32_DMA2_CH3_HANDLER Vector110
120#define STM32_DMA2_CH4_HANDLER Vector114
121#define STM32_DMA2_CH5_HANDLER Vector118
122#define STM32_DMA2_CH1_NUMBER 50
123#define STM32_DMA2_CH2_NUMBER 51
124#define STM32_DMA2_CH3_NUMBER 52
125#define STM32_DMA2_CH4_NUMBER 53
126#define STM32_DMA2_CH5_NUMBER 54
127#endif
128
129/* ETH attributes.*/
130#define STM32_HAS_ETH FALSE
131
132/* EXTI attributes.*/
133#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
134 defined(__DOXYGEN__)
135#define STM32_EXTI_NUM_LINES 23
136#else
137#define STM32_EXTI_NUM_LINES 24
138#endif
139#define STM32_EXTI_IMR1_MASK 0x00000000U
140
141#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
142 (STM32L1XX_PROD_CAT == 3) || defined(__DOXYGEN__)
143#define STM32_HAS_GPIOA TRUE
144#define STM32_HAS_GPIOB TRUE
145#define STM32_HAS_GPIOC TRUE
146#define STM32_HAS_GPIOD TRUE
147#define STM32_HAS_GPIOE TRUE
148#define STM32_HAS_GPIOF FALSE
149#define STM32_HAS_GPIOG FALSE
150#define STM32_HAS_GPIOH TRUE
151#define STM32_HAS_GPIOI FALSE
152#define STM32_HAS_GPIOJ FALSE
153#define STM32_HAS_GPIOK FALSE
154#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
155 RCC_AHBENR_GPIOBEN | \
156 RCC_AHBENR_GPIOCEN | \
157 RCC_AHBENR_GPIODEN | \
158 RCC_AHBENR_GPIOEEN | \
159 RCC_AHBENR_GPIOHEN)
160#else
161#define STM32_HAS_GPIOA TRUE
162#define STM32_HAS_GPIOB TRUE
163#define STM32_HAS_GPIOC TRUE
164#define STM32_HAS_GPIOD TRUE
165#define STM32_HAS_GPIOE TRUE
166#define STM32_HAS_GPIOF TRUE
167#define STM32_HAS_GPIOG TRUE
168#define STM32_HAS_GPIOH TRUE
169#define STM32_HAS_GPIOI FALSE
170#define STM32_HAS_GPIOJ FALSE
171#define STM32_HAS_GPIOK FALSE
172#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
173 RCC_AHBENR_GPIOBEN | \
174 RCC_AHBENR_GPIOCEN | \
175 RCC_AHBENR_GPIODEN | \
176 RCC_AHBENR_GPIOEEN | \
177 RCC_AHBENR_GPIOFEN | \
178 RCC_AHBENR_GPIOGEN | \
179 RCC_AHBENR_GPIOHEN)
180#endif
181
182/* I2C attributes.*/
183#define STM32_HAS_I2C1 TRUE
184#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
185#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
186
187#define STM32_HAS_I2C2 TRUE
188#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
189#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
190
191#define STM32_HAS_I2C3 FALSE
192#define STM32_HAS_I2C4 FALSE
193
194/* QUADSPI attributes.*/
195#define STM32_HAS_QUADSPI1 FALSE
196
197/* RTC attributes.*/
198#define STM32_HAS_RTC TRUE
199#if (STM32L1XX_PROD_CAT == 1) || defined(__DOXYGEN__)
200#define STM32_RTC_HAS_SUBSECONDS FALSE
201#else
202#define STM32_RTC_HAS_SUBSECONDS TRUE
203#endif
204#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
205#define STM32_RTC_NUM_ALARMS 2
206#if STM32L1XX_VALUE_LINE || defined(__DOXYGEN__)
207#define STM32_RTC_STORAGE_SIZE 20
208#elif (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2)
209#define STM32_RTC_STORAGE_SIZE 80
210#else
211#define STM32_RTC_STORAGE_SIZE 128
212#endif
213#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
214#define STM32_RTC_WKUP_HANDLER Vector4C
215#define STM32_RTC_ALARM_HANDLER VectorE4
216#define STM32_RTC_TAMP_STAMP_NUMBER 3
217#define STM32_RTC_WKUP_NUMBER 1
218#define STM32_RTC_ALARM_NUMBER 2
219#define STM32_RTC_ALARM_EXTI 17
220#define STM32_RTC_TAMP_STAMP_EXTI 19
221#define STM32_RTC_WKUP_EXTI 20
222#define STM32_RTC_IRQ_ENABLE() do { \
223 nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \
224 nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \
225 nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \
226} while (false)
227
228/* SDIO attributes.*/
229#define STM32_HAS_SDIO TRUE
230
231/* SPI attributes.*/
232#define STM32_HAS_SPI1 TRUE
233#define STM32_SPI1_SUPPORTS_I2S FALSE
234#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
235#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
236
237#define STM32_HAS_SPI2 TRUE
238#define STM32_SPI2_SUPPORTS_I2S TRUE
239#define STM32_SPI2_I2S_FULLDUPLEX FALSE
240#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
241#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
242
243#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
244 defined(__DOXYGEN__)
245#define STM32_HAS_SPI3 FALSE
246#else
247#define STM32_HAS_SPI3 TRUE
248#define STM32_SPI3_SUPPORTS_I2S TRUE
249#define STM32_SPI3_I2S_FULLDUPLEX FALSE
250#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
251#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
252#endif
253
254#define STM32_HAS_SPI4 FALSE
255#define STM32_HAS_SPI5 FALSE
256#define STM32_HAS_SPI6 FALSE
257
258/* TIM attributes.*/
259#define STM32_TIM_MAX_CHANNELS 4
260
261#define STM32_HAS_TIM2 TRUE
262#define STM32_TIM2_IS_32BITS FALSE
263#define STM32_TIM2_CHANNELS 4
264
265#define STM32_HAS_TIM3 TRUE
266#define STM32_TIM3_IS_32BITS FALSE
267#define STM32_TIM3_CHANNELS 4
268
269#define STM32_HAS_TIM4 TRUE
270#define STM32_TIM4_IS_32BITS FALSE
271#define STM32_TIM4_CHANNELS 4
272
273#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
274 defined(__DOXYGEN__)
275#define STM32_HAS_TIM5 FALSE
276#else
277#define STM32_HAS_TIM5 TRUE
278#define STM32_TIM5_IS_32BITS TRUE
279#define STM32_TIM5_CHANNELS 4
280#endif
281
282#define STM32_HAS_TIM6 TRUE
283#define STM32_TIM6_IS_32BITS FALSE
284#define STM32_TIM6_CHANNELS 0
285
286#define STM32_HAS_TIM7 TRUE
287#define STM32_TIM7_IS_32BITS FALSE
288#define STM32_TIM7_CHANNELS 0
289
290#define STM32_HAS_TIM9 TRUE
291#define STM32_TIM9_IS_32BITS FALSE
292#define STM32_TIM9_CHANNELS 2
293
294#define STM32_HAS_TIM10 TRUE
295#define STM32_TIM10_IS_32BITS FALSE
296#define STM32_TIM10_CHANNELS 2
297
298#define STM32_HAS_TIM11 TRUE
299#define STM32_TIM11_IS_32BITS FALSE
300#define STM32_TIM11_CHANNELS 2
301
302#define STM32_HAS_TIM1 FALSE
303#define STM32_HAS_TIM8 FALSE
304#define STM32_HAS_TIM12 FALSE
305#define STM32_HAS_TIM13 FALSE
306#define STM32_HAS_TIM14 FALSE
307#define STM32_HAS_TIM15 FALSE
308#define STM32_HAS_TIM16 FALSE
309#define STM32_HAS_TIM17 FALSE
310#define STM32_HAS_TIM18 FALSE
311#define STM32_HAS_TIM19 FALSE
312#define STM32_HAS_TIM20 FALSE
313#define STM32_HAS_TIM21 FALSE
314#define STM32_HAS_TIM22 FALSE
315
316/* USART attributes.*/
317#define STM32_HAS_USART1 TRUE
318#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
319#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
320
321#define STM32_HAS_USART2 TRUE
322#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
323#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
324
325#define STM32_HAS_USART3 TRUE
326#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
327#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
328
329#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
330 (STM32L1XX_PROD_CAT == 3) || defined(__DOXYGEN__)
331#define STM32_HAS_UART4 FALSE
332#define STM32_HAS_UART5 FALSE
333#else
334#define STM32_HAS_UART4 TRUE
335#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
336#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
337
338#define STM32_HAS_UART5 TRUE
339#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
340#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
341#endif
342
343#define STM32_HAS_USART6 FALSE
344#define STM32_HAS_UART7 FALSE
345#define STM32_HAS_UART8 FALSE
346#define STM32_HAS_LPUART1 FALSE
347
348/* USB attributes.*/
349#define STM32_HAS_USB TRUE
350#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
351#define STM32_USB_PMA_SIZE 512
352#define STM32_USB_HAS_BCDR FALSE
353#define STM32_HAS_OTG1 FALSE
354#define STM32_HAS_OTG2 FALSE
355
356/* IWDG attributes.*/
357#define STM32_HAS_IWDG TRUE
358#define STM32_IWDG_IS_WINDOWED FALSE
359
360/* LTDC attributes.*/
361#define STM32_HAS_LTDC FALSE
362
363/* DMA2D attributes.*/
364#define STM32_HAS_DMA2D FALSE
365
366/* FSMC attributes.*/
367#define STM32_HAS_FSMC FALSE
368
369/* CRC attributes.*/
370#define STM32_HAS_CRC TRUE
371#define STM32_CRC_PROGRAMMABLE FALSE
372
373/** @} */
374
375#endif /* STM32_REGISTRY_H */
376
377/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 04:34:45 +0100