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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32L4xx+/stm32_rcc.h
19 * @brief RCC helper driver header.
20 * @note This file requires definitions from the ST header file
21 * @p stm32l4xx.h.
22 *
23 * @addtogroup STM32L4xx_RCC
24 * @{
25 */
26#ifndef STM32_RCC_H
27#define STM32_RCC_H
28
29/*===========================================================================*/
30/* Driver constants. */
31/*===========================================================================*/
32
33/*===========================================================================*/
34/* Driver pre-compile time settings. */
35/*===========================================================================*/
36
37/*===========================================================================*/
38/* Derived constants and error checks. */
39/*===========================================================================*/
40
41/*===========================================================================*/
42/* Driver data structures and types. */
43/*===========================================================================*/
44
45/*===========================================================================*/
46/* Driver macros. */
47/*===========================================================================*/
48
49/**
50 * @name Generic RCC operations
51 * @{
52 */
53/**
54 * @brief Enables the clock of one or more peripheral on the APB1 bus (R1).
55 *
56 * @param[in] mask APB1 R1 peripherals mask
57 * @param[in] lp low power enable flag
58 *
59 * @api
60 */
61#define rccEnableAPB1R1(mask, lp) { \
62 RCC->APB1ENR1 |= (mask); \
63 if (lp) \
64 RCC->APB1SMENR1 |= (mask); \
65 else \
66 RCC->APB1SMENR1 &= ~(mask); \
67 (void)RCC->APB1SMENR1; \
68}
69
70/**
71 * @brief Disables the clock of one or more peripheral on the APB1 bus (R1).
72 *
73 * @param[in] mask APB1 R1 peripherals mask
74 *
75 * @api
76 */
77#define rccDisableAPB1R1(mask) { \
78 RCC->APB1ENR1 &= ~(mask); \
79 RCC->APB1SMENR1 &= ~(mask); \
80 (void)RCC->APB1SMENR1; \
81}
82
83/**
84 * @brief Resets one or more peripheral on the APB1 bus (R1).
85 *
86 * @param[in] mask APB1 R1 peripherals mask
87 *
88 * @api
89 */
90#define rccResetAPB1R1(mask) { \
91 RCC->APB1RSTR1 |= (mask); \
92 RCC->APB1RSTR1 &= ~(mask); \
93 (void)RCC->APB1RSTR1; \
94}
95
96/**
97 * @brief Enables the clock of one or more peripheral on the APB1 bus (R2).
98 *
99 * @param[in] mask APB1 R2 peripherals mask
100 * @param[in] lp low power enable flag
101 *
102 * @api
103 */
104#define rccEnableAPB1R2(mask, lp) { \
105 RCC->APB1ENR2 |= (mask); \
106 if (lp) \
107 RCC->APB1SMENR2 |= (mask); \
108 else \
109 RCC->APB1SMENR2 &= ~(mask); \
110 (void)RCC->APB1SMENR2; \
111}
112
113/**
114 * @brief Disables the clock of one or more peripheral on the APB1 bus (R2).
115 *
116 * @param[in] mask APB1 R2 peripherals mask
117 *
118 * @api
119 */
120#define rccDisableAPB1R2(mask) { \
121 RCC->APB1ENR2 &= ~(mask); \
122 RCC->APB1SMENR2 &= ~(mask); \
123 (void)RCC->APB1SMENR2; \
124}
125
126/**
127 * @brief Resets one or more peripheral on the APB1 bus (R2).
128 *
129 * @param[in] mask APB1 R2 peripherals mask
130 *
131 * @api
132 */
133#define rccResetAPB1R2(mask) { \
134 RCC->APB1RSTR2 |= (mask); \
135 RCC->APB1RSTR2 &= ~(mask); \
136 (void)RCC->APB1RSTR2; \
137}
138
139/**
140 * @brief Enables the clock of one or more peripheral on the APB2 bus.
141 *
142 * @param[in] mask APB2 peripherals mask
143 * @param[in] lp low power enable flag
144 *
145 * @api
146 */
147#define rccEnableAPB2(mask, lp) { \
148 RCC->APB2ENR |= (mask); \
149 if (lp) \
150 RCC->APB2SMENR |= (mask); \
151 else \
152 RCC->APB2SMENR &= ~(mask); \
153 (void)RCC->APB2SMENR; \
154}
155
156/**
157 * @brief Disables the clock of one or more peripheral on the APB2 bus.
158 *
159 * @param[in] mask APB2 peripherals mask
160 *
161 * @api
162 */
163#define rccDisableAPB2(mask) { \
164 RCC->APB2ENR &= ~(mask); \
165 RCC->APB2SMENR &= ~(mask); \
166 (void)RCC->APB2SMENR; \
167}
168
169/**
170 * @brief Resets one or more peripheral on the APB2 bus.
171 *
172 * @param[in] mask APB2 peripherals mask
173 *
174 * @api
175 */
176#define rccResetAPB2(mask) { \
177 RCC->APB2RSTR |= (mask); \
178 RCC->APB2RSTR &= ~(mask); \
179 (void)RCC->APB2RSTR; \
180}
181
182/**
183 * @brief Enables the clock of one or more peripheral on the AHB1 bus.
184 *
185 * @param[in] mask AHB1 peripherals mask
186 * @param[in] lp low power enable flag
187 *
188 * @api
189 */
190#define rccEnableAHB1(mask, lp) { \
191 RCC->AHB1ENR |= (mask); \
192 if (lp) \
193 RCC->AHB1SMENR |= (mask); \
194 else \
195 RCC->AHB1SMENR &= ~(mask); \
196 (void)RCC->AHB1SMENR; \
197}
198
199/**
200 * @brief Disables the clock of one or more peripheral on the AHB1 bus.
201 *
202 * @param[in] mask AHB1 peripherals mask
203 *
204 * @api
205 */
206#define rccDisableAHB1(mask) { \
207 RCC->AHB1ENR &= ~(mask); \
208 RCC->AHB1SMENR &= ~(mask); \
209 (void)RCC->AHB1SMENR; \
210}
211
212/**
213 * @brief Resets one or more peripheral on the AHB1 bus.
214 *
215 * @param[in] mask AHB1 peripherals mask
216 *
217 * @api
218 */
219#define rccResetAHB1(mask) { \
220 RCC->AHB1RSTR |= (mask); \
221 RCC->AHB1RSTR &= ~(mask); \
222 (void)RCC->AHB1RSTR; \
223}
224
225/**
226 * @brief Enables the clock of one or more peripheral on the AHB2 bus.
227 *
228 * @param[in] mask AHB2 peripherals mask
229 * @param[in] lp low power enable flag
230 *
231 * @api
232 */
233#define rccEnableAHB2(mask, lp) { \
234 RCC->AHB2ENR |= (mask); \
235 if (lp) \
236 RCC->AHB2SMENR |= (mask); \
237 else \
238 RCC->AHB2SMENR &= ~(mask); \
239 (void)RCC->AHB2SMENR; \
240}
241
242/**
243 * @brief Disables the clock of one or more peripheral on the AHB2 bus.
244 *
245 * @param[in] mask AHB2 peripherals mask
246 *
247 * @api
248 */
249#define rccDisableAHB2(mask) { \
250 RCC->AHB2ENR &= ~(mask); \
251 RCC->AHB2SMENR &= ~(mask); \
252 (void)RCC->AHB2SMENR; \
253}
254
255/**
256 * @brief Resets one or more peripheral on the AHB2 bus.
257 *
258 * @param[in] mask AHB2 peripherals mask
259 *
260 * @api
261 */
262#define rccResetAHB2(mask) { \
263 RCC->AHB2RSTR |= (mask); \
264 RCC->AHB2RSTR &= ~(mask); \
265 (void)RCC->AHB2RSTR; \
266}
267
268/**
269 * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.
270 *
271 * @param[in] mask AHB3 peripherals mask
272 * @param[in] lp low power enable flag
273 *
274 * @api
275 */
276#define rccEnableAHB3(mask, lp) { \
277 RCC->AHB3ENR |= (mask); \
278 if (lp) \
279 RCC->AHB3SMENR |= (mask); \
280 else \
281 RCC->AHB3SMENR &= ~(mask); \
282 (void)RCC->AHB3SMENR; \
283}
284
285/**
286 * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.
287 *
288 * @param[in] mask AHB3 peripherals mask
289 *
290 * @api
291 */
292#define rccDisableAHB3(mask) { \
293 RCC->AHB3ENR &= ~(mask); \
294 RCC->AHB3SMENR &= ~(mask); \
295 (void)RCC->AHB3SMENR; \
296}
297
298/**
299 * @brief Resets one or more peripheral on the AHB3 (FSMC) bus.
300 *
301 * @param[in] mask AHB3 peripherals mask
302 *
303 * @api
304 */
305#define rccResetAHB3(mask) { \
306 RCC->AHB3RSTR |= (mask); \
307 RCC->AHB3RSTR &= ~(mask); \
308 (void)RCC->AHB3RSTR; \
309}
310/** @} */
311
312/**
313 * @name ADC peripherals specific RCC operations
314 * @{
315 */
316/**
317 * @brief Enables the ADC1/ADC2/ADC3 peripheral clock.
318 *
319 * @param[in] lp low power enable flag
320 *
321 * @api
322 */
323#define rccEnableADC123(lp) rccEnableAHB2(RCC_AHB2ENR_ADCEN, lp)
324
325/**
326 * @brief Disables the ADC1/ADC2/ADC3 peripheral clock.
327 *
328 * @api
329 */
330#define rccDisableADC123() rccDisableAHB2(RCC_AHB2ENR_ADCEN)
331
332/**
333 * @brief Resets the ADC1/ADC2/ADC3 peripheral.
334 *
335 * @api
336 */
337#define rccResetADC123() rccResetAHB2(RCC_AHB2RSTR_ADCRST)
338/** @} */
339
340/**
341 * @name DAC peripheral specific RCC operations
342 * @{
343 */
344/**
345 * @brief Enables the DAC1 peripheral clock.
346 *
347 * @param[in] lp low power enable flag
348 *
349 * @api
350 */
351#define rccEnableDAC1(lp) rccEnableAPB1R1(RCC_APB1ENR1_DAC1EN, lp)
352
353/**
354 * @brief Disables the DAC1 peripheral clock.
355 *
356 * @api
357 */
358#define rccDisableDAC1() rccDisableAPB1R1(RCC_APB1ENR1_DAC1EN)
359
360/**
361 * @brief Resets the DAC1 peripheral.
362 *
363 * @api
364 */
365#define rccResetDAC1() rccResetAPB1R1(RCC_APB1RSTR1_DAC1RST)
366/** @} */
367
368/**
369 * @name DMA peripheral specific RCC operations
370 * @{
371 */
372/**
373 * @brief Enables the DMA1 peripheral clock.
374 *
375 * @param[in] lp low power enable flag
376 *
377 * @api
378 */
379#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
380
381/**
382 * @brief Disables the DMA1 peripheral clock.
383 *
384 * @api
385 */
386#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN)
387
388/**
389 * @brief Resets the DMA1 peripheral.
390 *
391 * @api
392 */
393#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
394
395/**
396 * @brief Enables the DMA2 peripheral clock.
397 *
398 * @param[in] lp low power enable flag
399 *
400 * @api
401 */
402#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
403
404/**
405 * @brief Disables the DMA2 peripheral clock.
406 *
407 * @api
408 */
409#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN)
410
411/**
412 * @brief Resets the DMA2 peripheral.
413 *
414 * @api
415 */
416#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
417/** @} */
418
419/**
420 * @name DMAMUX peripheral specific RCC operations
421 * @{
422 */
423/**
424 * @brief Enables the DMAMUX peripheral clock.
425 *
426 * @param[in] lp low power enable flag
427 *
428 * @api
429 */
430#define rccEnableDMAMUX(lp) rccEnableAHB1(RCC_AHB1ENR_DMAMUX1EN, lp)
431
432/**
433 * @brief Disables the DMAMUX peripheral clock.
434 *
435 * @api
436 */
437#define rccDisableDMAMUX() rccDisableAHB1(RCC_AHB1ENR_DMAMUX1EN)
438
439/**
440 * @brief Resets the DMAMUX peripheral.
441 *
442 * @api
443 */
444#define rccResetDMAMUX() rccResetAHB1(RCC_AHB1RSTR_DMAMUX1RST)
445/** @} */
446
447/**
448 * @name PWR interface specific RCC operations
449 * @{
450 */
451/**
452 * @brief Enables the PWR interface clock.
453 *
454 * @param[in] lp low power enable flag
455 *
456 * @api
457 */
458#define rccEnablePWRInterface(lp) rccEnableAPB1R1(RCC_APB1ENR1_PWREN, lp)
459
460/**
461 * @brief Disables PWR interface clock.
462 *
463 * @api
464 */
465#define rccDisablePWRInterface() rccDisableAPB1R1(RCC_APB1ENR1_PWREN)
466
467/**
468 * @brief Resets the PWR interface.
469 *
470 * @api
471 */
472#define rccResetPWRInterface() rccResetAPB1R1(RCC_APB1RSTR1_PWRRST)
473/** @} */
474
475/**
476 * @name CAN peripherals specific RCC operations
477 * @{
478 */
479/**
480 * @brief Enables the CAN1 peripheral clock.
481 *
482 * @param[in] lp low power enable flag
483 *
484 * @api
485 */
486#define rccEnableCAN1(lp) rccEnableAPB1R1(RCC_APB1ENR1_CAN1EN, lp)
487
488/**
489 * @brief Disables the CAN1 peripheral clock.
490 *
491 * @api
492 */
493#define rccDisableCAN1() rccDisableAPB1R1(RCC_APB1ENR1_CAN1EN)
494
495/**
496 * @brief Resets the CAN1 peripheral.
497 *
498 * @api
499 */
500#define rccResetCAN1() rccResetAPB1R1(RCC_APB1RSTR1_CAN1RST)
501
502/**
503 * @brief Enables the CAN2 peripheral clock.
504 *
505 * @param[in] lp low power enable flag
506 *
507 * @api
508 */
509#define rccEnableCAN2(lp) rccEnableAPB1R1(RCC_APB1ENR1_CAN2EN, lp)
510
511/**
512 * @brief Disables the CAN2 peripheral clock.
513 *
514 * @api
515 */
516#define rccDisableCAN2() rccDisableAPB1R1(RCC_APB1ENR1_CAN2EN)
517
518/**
519 * @brief Resets the CAN2 peripheral.
520 *
521 * @api
522 */
523#define rccResetCAN2() rccResetAPB1R1(RCC_APB1RSTR1_CAN2RST)
524/** @} */
525
526/**
527 * @name I2C peripherals specific RCC operations
528 * @{
529 */
530/**
531 * @brief Enables the I2C1 peripheral clock.
532 *
533 * @param[in] lp low power enable flag
534 *
535 * @api
536 */
537#define rccEnableI2C1(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C1EN, lp)
538
539/**
540 * @brief Disables the I2C1 peripheral clock.
541 *
542 * @api
543 */
544#define rccDisableI2C1() rccDisableAPB1R1(RCC_APB1ENR1_I2C1EN)
545
546/**
547 * @brief Resets the I2C1 peripheral.
548 *
549 * @api
550 */
551#define rccResetI2C1() rccResetAPB1R1(RCC_APB1RSTR1_I2C1RST)
552
553/**
554 * @brief Enables the I2C2 peripheral clock.
555 *
556 * @param[in] lp low power enable flag
557 *
558 * @api
559 */
560#define rccEnableI2C2(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C2EN, lp)
561
562/**
563 * @brief Disables the I2C2 peripheral clock.
564 *
565 * @api
566 */
567#define rccDisableI2C2() rccDisableAPB1R1(RCC_APB1ENR1_I2C2EN)
568
569/**
570 * @brief Resets the I2C2 peripheral.
571 *
572 * @api
573 */
574#define rccResetI2C2() rccResetAPB1R1(RCC_APB1RSTR1_I2C2RST)
575
576/**
577 * @brief Enables the I2C3 peripheral clock.
578 *
579 * @param[in] lp low power enable flag
580 *
581 * @api
582 */
583#define rccEnableI2C3(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C3EN, lp)
584
585/**
586 * @brief Disables the I2C3 peripheral clock.
587 *
588 * @api
589 */
590#define rccDisableI2C3() rccDisableAPB1R1(RCC_APB1ENR1_I2C3EN)
591
592/**
593 * @brief Resets the I2C3 peripheral.
594 *
595 * @api
596 */
597#define rccResetI2C3() rccResetAPB1R1(RCC_APB1RSTR1_I2C3RST)
598
599/**
600 * @brief Enables the I2C4 peripheral clock.
601 *
602 * @param[in] lp low power enable flag
603 *
604 * @api
605 */
606#define rccEnableI2C4(lp) rccEnableAPB1R2(RCC_APB1ENR2_I2C4EN, lp)
607
608/**
609 * @brief Disables the I2C4 peripheral clock.
610 *
611 * @api
612 */
613#define rccDisableI2C4() rccDisableAPB1R1(RCC_APB1ENR2_I2C4EN)
614
615/**
616 * @brief Resets the I2C4 peripheral.
617 *
618 * @api
619 */
620#define rccResetI2C4() rccResetAPB1R1(RCC_APB1RSTR2_I2C4RST)
621/** @} */
622
623/**
624 * @name OTG peripherals specific RCC operations
625 * @{
626 */
627/**
628 * @brief Enables the OTG_FS peripheral clock.
629 *
630 * @param[in] lp low power enable flag
631 *
632 * @api
633 */
634#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
635
636/**
637 * @brief Disables the OTG_FS peripheral clock.
638 *
639 * @api
640 */
641#define rccDisableOTG_FS() rccDisableAHB2(RCC_AHB2ENR_OTGFSEN)
642
643/**
644 * @brief Resets the OTG_FS peripheral.
645 *
646 * @api
647 */
648#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
649/** @} */
650
651/**
652 * @name OCTOSPI peripherals specific RCC operations
653 * @{
654 */
655/**
656 * @brief Enables the OCTOSPI1 peripheral clock.
657 *
658 * @param[in] lp low power enable flag
659 *
660 * @api
661 */
662#define rccEnableOCTOSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_OSPI1EN, lp)
663
664/**
665 * @brief Disables the OCTOSPI1 peripheral clock.
666 *
667 * @api
668 */
669#define rccDisableOCTOSPI1() rccDisableAHB3(RCC_AHB3ENR_OSPI1EN)
670
671/**
672 * @brief Resets the OCTOSPI1 peripheral.
673 *
674 * @api
675 */
676#define rccResetOCTOSPI1() rccResetAHB3(RCC_AHB3RSTR_OSPI1RST)
677
678/**
679 * @brief Enables the OCTOSPI2 peripheral clock.
680 *
681 * @param[in] lp low power enable flag
682 *
683 * @api
684 */
685#define rccEnableOCTOSPI2(lp) rccEnableAHB3(RCC_AHB3ENR_OSPI2EN, lp)
686
687/**
688 * @brief Disables the OCTOSPI2 peripheral clock.
689 *
690 * @api
691 */
692#define rccDisableOCTOSPI2() rccDisableAHB3(RCC_AHB3ENR_OSPI2EN)
693
694/**
695 * @brief Resets the OCTOSPI1 peripheral.
696 *
697 * @api
698 */
699#define rccResetOCTOSPI2() rccResetAHB3(RCC_AHB3RSTR_OSPI2RST)
700/** @} */
701
702/**
703 * @name RNG peripherals specific RCC operations
704 * @{
705 */
706/**
707 * @brief Enables the RNG peripheral clock.
708 *
709 * @param[in] lp low power enable flag
710 *
711 * @api
712 */
713#define rccEnableRNG(lp) rccEnableAHB2(RCC_AHB2ENR_RNGEN, lp)
714
715/**
716 * @brief Disables the RNG peripheral clock.
717 *
718 * @api
719 */
720#define rccDisableRNG() rccDisableAHB2(RCC_AHB2ENR_RNGEN)
721
722/**
723 * @brief Resets the RNG peripheral.
724 *
725 * @api
726 */
727#define rccResetRNG() rccResetAHB2(RCC_AHB2RSTR_RNGRST)
728/** @} */
729
730/**
731 * @name SDMMC peripheral specific RCC operations
732 * @{
733 */
734/**
735 * @brief Enables the SDMMC1 peripheral clock.
736 *
737 * @param[in] lp low power enable flag
738 *
739 * @api
740 */
741#define rccEnableSDMMC1(lp) rccEnableAHB2(RCC_AHB2ENR_SDMMC1EN, lp)
742
743/**
744 * @brief Disables the SDMMC1 peripheral clock.
745 *
746 * @api
747 */
748#define rccDisableSDMMC1() rccDisableAHB2(RCC_AHB2ENR_SDMMC1EN)
749
750/**
751 * @brief Resets the SDMMC1 peripheral.
752 *
753 * @api
754 */
755#define rccResetSDMMC1() rccResetAHB2(RCC_AHB2RSTR_SDMMC1RST)
756/** @} */
757
758/**
759 * @name SPI peripherals specific RCC operations
760 * @{
761 */
762/**
763 * @brief Enables the SPI1 peripheral clock.
764 *
765 * @param[in] lp low power enable flag
766 *
767 * @api
768 */
769#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
770
771/**
772 * @brief Disables the SPI1 peripheral clock.
773 *
774 * @api
775 */
776#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
777
778/**
779 * @brief Resets the SPI1 peripheral.
780 *
781 * @api
782 */
783#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
784
785/**
786 * @brief Enables the SPI2 peripheral clock.
787 *
788 * @param[in] lp low power enable flag
789 *
790 * @api
791 */
792#define rccEnableSPI2(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI2EN, lp)
793
794/**
795 * @brief Disables the SPI2 peripheral clock.
796 *
797 * @api
798 */
799#define rccDisableSPI2() rccDisableAPB1R1(RCC_APB1ENR1_SPI2EN)
800
801/**
802 * @brief Resets the SPI2 peripheral.
803 *
804 * @api
805 */
806#define rccResetSPI2() rccResetAPB1R1(RCC_APB1RSTR1_SPI2RST)
807
808/**
809 * @brief Enables the SPI3 peripheral clock.
810 *
811 * @param[in] lp low power enable flag
812 *
813 * @api
814 */
815#define rccEnableSPI3(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI3EN, lp)
816
817/**
818 * @brief Disables the SPI3 peripheral clock.
819 *
820 * @api
821 */
822#define rccDisableSPI3() rccDisableAPB1R1(RCC_APB1ENR1_SPI3EN)
823
824/**
825 * @brief Resets the SPI3 peripheral.
826 *
827 * @api
828 */
829#define rccResetSPI3() rccResetAPB1R1(RCC_APB1RSTR1_SPI3RST)
830/** @} */
831
832/**
833 * @name TIM peripherals specific RCC operations
834 * @{
835 */
836/**
837 * @brief Enables the TIM1 peripheral clock.
838 *
839 * @param[in] lp low power enable flag
840 *
841 * @api
842 */
843#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
844
845/**
846 * @brief Disables the TIM1 peripheral clock.
847 *
848 * @api
849 */
850#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
851
852/**
853 * @brief Resets the TIM1 peripheral.
854 *
855 * @api
856 */
857#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
858
859/**
860 * @brief Enables the TIM2 peripheral clock.
861 *
862 * @param[in] lp low power enable flag
863 *
864 * @api
865 */
866#define rccEnableTIM2(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM2EN, lp)
867
868/**
869 * @brief Disables the TIM2 peripheral clock.
870 *
871 * @api
872 */
873#define rccDisableTIM2() rccDisableAPB1R1(RCC_APB1ENR1_TIM2EN)
874
875/**
876 * @brief Resets the TIM2 peripheral.
877 *
878 * @api
879 */
880#define rccResetTIM2() rccResetAPB1R1(RCC_APB1RSTR1_TIM2RST)
881
882/**
883 * @brief Enables the TIM3 peripheral clock.
884 *
885 * @param[in] lp low power enable flag
886 *
887 * @api
888 */
889#define rccEnableTIM3(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM3EN, lp)
890
891/**
892 * @brief Disables the TIM3 peripheral clock.
893 *
894 * @api
895 */
896#define rccDisableTIM3() rccDisableAPB1R1(RCC_APB1ENR1_TIM3EN)
897
898/**
899 * @brief Resets the TIM3 peripheral.
900 *
901 * @api
902 */
903#define rccResetTIM3() rccResetAPB1R1(RCC_APB1RSTR1_TIM3RST)
904
905/**
906 * @brief Enables the TIM4 peripheral clock.
907 *
908 * @param[in] lp low power enable flag
909 *
910 * @api
911 */
912#define rccEnableTIM4(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM4EN, lp)
913
914/**
915 * @brief Disables the TIM4 peripheral clock.
916 *
917 * @api
918 */
919#define rccDisableTIM4() rccDisableAPB1R1(RCC_APB1ENR1_TIM4EN)
920
921/**
922 * @brief Resets the TIM4 peripheral.
923 *
924 * @api
925 */
926#define rccResetTIM4() rccResetAPB1R1(RCC_APB1RSTR1_TIM4RST)
927
928/**
929 * @brief Enables the TIM5 peripheral clock.
930 *
931 * @param[in] lp low power enable flag
932 *
933 * @api
934 */
935#define rccEnableTIM5(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM5EN, lp)
936
937/**
938 * @brief Disables the TIM5 peripheral clock.
939 *
940 * @api
941 */
942#define rccDisableTIM5() rccDisableAPB1R1(RCC_APB1ENR1_TIM5EN)
943
944/**
945 * @brief Resets the TIM5 peripheral.
946 *
947 * @api
948 */
949#define rccResetTIM5() rccResetAPB1R1(RCC_APB1RSTR1_TIM5RST)
950
951/**
952 * @brief Enables the TIM6 peripheral clock.
953 *
954 * @param[in] lp low power enable flag
955 *
956 * @api
957 */
958#define rccEnableTIM6(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM6EN, lp)
959
960/**
961 * @brief Disables the TIM6 peripheral clock.
962 *
963 * @api
964 */
965#define rccDisableTIM6() rccDisableAPB1R1(RCC_APB1ENR1_TIM6EN)
966
967/**
968 * @brief Resets the TIM6 peripheral.
969 *
970 * @api
971 */
972#define rccResetTIM6() rccResetAPB1R1(RCC_APB1RSTR1_TIM6RST)
973
974/**
975 * @brief Enables the TIM7 peripheral clock.
976 *
977 * @param[in] lp low power enable flag
978 *
979 * @api
980 */
981#define rccEnableTIM7(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM7EN, lp)
982
983/**
984 * @brief Disables the TIM7 peripheral clock.
985 *
986 * @api
987 */
988#define rccDisableTIM7() rccDisableAPB1R1(RCC_APB1ENR1_TIM7EN)
989
990/**
991 * @brief Resets the TIM7 peripheral.
992 *
993 * @api
994 */
995#define rccResetTIM7() rccResetAPB1R1(RCC_APB1RSTR1_TIM7RST)
996
997/**
998 * @brief Enables the TIM8 peripheral clock.
999 *
1000 * @param[in] lp low power enable flag
1001 *
1002 * @api
1003 */
1004#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
1005
1006/**
1007 * @brief Disables the TIM8 peripheral clock.
1008 *
1009 * @api
1010 */
1011#define rccDisableTIM8() rccDisableAPB2(RCC_APB2ENR_TIM8EN)
1012
1013/**
1014 * @brief Resets the TIM8 peripheral.
1015 *
1016 * @api
1017 */
1018#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
1019
1020/**
1021 * @brief Enables the TIM15 peripheral clock.
1022 *
1023 * @param[in] lp low power enable flag
1024 *
1025 * @api
1026 */
1027#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
1028
1029/**
1030 * @brief Disables the TIM15 peripheral clock.
1031 *
1032 * @api
1033 */
1034#define rccDisableTIM15() rccDisableAPB2(RCC_APB2ENR_TIM15EN)
1035
1036/**
1037 * @brief Resets the TIM15 peripheral.
1038 *
1039 * @api
1040 */
1041#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
1042
1043/**
1044 * @brief Enables the TIM16 peripheral clock.
1045 *
1046 * @param[in] lp low power enable flag
1047 *
1048 * @api
1049 */
1050#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
1051
1052/**
1053 * @brief Disables the TIM16 peripheral clock.
1054 *
1055 * @api
1056 */
1057#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN)
1058
1059/**
1060 * @brief Resets the TIM16 peripheral.
1061 *
1062 * @api
1063 */
1064#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
1065
1066/**
1067 * @brief Enables the TIM17 peripheral clock.
1068 *
1069 * @param[in] lp low power enable flag
1070 *
1071 * @api
1072 */
1073#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
1074
1075/**
1076 * @brief Disables the TIM17 peripheral clock.
1077 *
1078 * @api
1079 */
1080#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN)
1081
1082/**
1083 * @brief Resets the TIM17 peripheral.
1084 *
1085 * @api
1086 */
1087#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
1088/** @} */
1089
1090/**
1091 * @name USART/UART peripherals specific RCC operations
1092 * @{
1093 */
1094/**
1095 * @brief Enables the USART1 peripheral clock.
1096 *
1097 * @param[in] lp low power enable flag
1098 *
1099 * @api
1100 */
1101#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
1102
1103/**
1104 * @brief Disables the USART1 peripheral clock.
1105 *
1106 * @api
1107 */
1108#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
1109
1110/**
1111 * @brief Resets the USART1 peripheral.
1112 *
1113 * @api
1114 */
1115#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
1116
1117/**
1118 * @brief Enables the USART2 peripheral clock.
1119 *
1120 * @param[in] lp low power enable flag
1121 *
1122 * @api
1123 */
1124#define rccEnableUSART2(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART2EN, lp)
1125
1126/**
1127 * @brief Disables the USART2 peripheral clock.
1128 *
1129 * @api
1130 */
1131#define rccDisableUSART2() rccDisableAPB1R1(RCC_APB1ENR1_USART2EN)
1132
1133/**
1134 * @brief Resets the USART2 peripheral.
1135 *
1136 * @api
1137 */
1138#define rccResetUSART2() rccResetAPB1R1(RCC_APB1RSTR1_USART2RST)
1139
1140/**
1141 * @brief Enables the USART3 peripheral clock.
1142 *
1143 * @param[in] lp low power enable flag
1144 *
1145 * @api
1146 */
1147#define rccEnableUSART3(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART3EN, lp)
1148
1149/**
1150 * @brief Disables the USART3 peripheral clock.
1151 *
1152 * @api
1153 */
1154#define rccDisableUSART3() rccDisableAPB1R1(RCC_APB1ENR1_USART3EN)
1155
1156/**
1157 * @brief Resets the USART3 peripheral.
1158 *
1159 * @api
1160 */
1161#define rccResetUSART3() rccResetAPB1R1(RCC_APB1RSTR1_USART3RST)
1162
1163/**
1164 * @brief Enables the UART4 peripheral clock.
1165 *
1166 * @param[in] lp low power enable flag
1167 *
1168 * @api
1169 */
1170#define rccEnableUART4(lp) rccEnableAPB1R1(RCC_APB1ENR1_UART4EN, lp)
1171
1172/**
1173 * @brief Disables the UART4 peripheral clock.
1174 *
1175 * @api
1176 */
1177#define rccDisableUART4() rccDisableAPB1R1(RCC_APB1ENR1_UART4EN)
1178
1179/**
1180 * @brief Resets the UART4 peripheral.
1181 *
1182 * @api
1183 */
1184#define rccResetUART4() rccResetAPB1R1(RCC_APB1RSTR1_UART4RST)
1185
1186/**
1187 * @brief Enables the UART5 peripheral clock.
1188 *
1189 * @param[in] lp low power enable flag
1190 *
1191 * @api
1192 */
1193#define rccEnableUART5(lp) rccEnableAPB1R1(RCC_APB1ENR1_UART5EN, lp)
1194
1195/**
1196 * @brief Disables the UART5 peripheral clock.
1197 *
1198 * @api
1199 */
1200#define rccDisableUART5() rccDisableAPB1R1(RCC_APB1ENR1_UART5EN)
1201
1202/**
1203 * @brief Resets the UART5 peripheral.
1204 *
1205 * @api
1206 */
1207#define rccResetUART5() rccResetAPB1R1(RCC_APB1RSTR1_UART5RST)
1208
1209/**
1210 * @brief Enables the LPUART1 peripheral clock.
1211 *
1212 * @param[in] lp low power enable flag
1213 *
1214 * @api
1215 */
1216#define rccEnableLPUART1(lp) rccEnableAPB1R2(RCC_APB1ENR2_LPUART1EN, lp)
1217
1218/**
1219 * @brief Disables the LPUART1 peripheral clock.
1220 *
1221 * @api
1222 */
1223#define rccDisableLPUART1() rccDisableAPB1R2(RCC_APB1ENR2_LPUART1EN)
1224
1225/**
1226 * @brief Resets the USART1 peripheral.
1227 *
1228 * @api
1229 */
1230#define rccResetLPUART1() rccResetAPB1R2(RCC_APB1RSTR2_LPUART1RST)
1231/** @} */
1232
1233/**
1234 * @name USB peripheral specific RCC operations
1235 * @{
1236 */
1237/**
1238 * @brief Enables the USB peripheral clock.
1239 *
1240 * @param[in] lp low power enable flag
1241 *
1242 * @api
1243 */
1244#define rccEnableUSB(lp) rccEnableAPB1R1(RCC_APB1ENR1_USBFSEN, lp)
1245
1246/**
1247 * @brief Disables the USB peripheral clock.
1248 *
1249 * @api
1250 */
1251#define rccDisableUSB() rccDisableAPB1R1(RCC_APB1ENR1_USBFSEN)
1252
1253/**
1254 * @brief Resets the USB peripheral.
1255 *
1256 * @api
1257 */
1258#define rccResetUSB() rccResetAPB1R1(RCC_APB1RSTR1_USBFSRST)
1259/** @} */
1260
1261/**
1262 * @name CRC peripheral specific RCC operations
1263 * @{
1264 */
1265/**
1266 * @brief Enables the CRC peripheral clock.
1267 *
1268 * @param[in] lp low power enable flag
1269 *
1270 * @api
1271 */
1272#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp)
1273
1274/**
1275 * @brief Disables the CRC peripheral clock.
1276 *
1277 * @api
1278 */
1279#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN)
1280
1281/**
1282 * @brief Resets the CRC peripheral.
1283 *
1284 * @api
1285 */
1286#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
1287/** @} */
1288
1289/**
1290 * @name FSMC peripherals specific RCC operations
1291 * @{
1292 */
1293/**
1294 * @brief Enables the FSMC peripheral clock.
1295 *
1296 * @param[in] lp low power enable flag
1297 *
1298 * @api
1299 */
1300#define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp)
1301
1302/**
1303 * @brief Disables the FSMC peripheral clock.
1304 *
1305 * @api
1306 */
1307#define rccDisableFSMC() rccDisableAHB3(RCC_AHB3ENR_FMCEN)
1308
1309/**
1310 * @brief Resets the FSMC peripheral.
1311 *
1312 * @api
1313 */
1314#define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST)
1315/** @} */
1316
1317/**
1318 * @name DCMI peripheral specific RCC operations
1319 * @{
1320 */
1321/**
1322 * @brief Enables the DCMI peripheral clock.
1323 *
1324 * @param[in] lp low power enable flag
1325 *
1326 * @api
1327 */
1328#define rccEnableDCMI(lp) rccEnableAHB2(RCC_AHB2ENR_DCMIEN, lp)
1329
1330/**
1331 * @brief Disables the DCMI peripheral clock.
1332+ *
1333+ * @api
1334 */
1335#define rccDisableDCMI() rccDisableAHB2(RCC_AHB2ENR_DCMIEN)
1336
1337/**
1338 * @brief Resets the DCMI peripheral.
1339 *
1340 * @api
1341 */
1342#define rccResetDCMI() rccResetAHB2(RCC_AHB2RSTR_DCMIRST)
1343/** @} */
1344
1345/*===========================================================================*/
1346/* External declarations. */
1347/*===========================================================================*/
1348
1349#ifdef __cplusplus
1350extern "C" {
1351#endif
1352#ifdef __cplusplus
1353}
1354#endif
1355
1356#endif /* STM32_RCC_H */
1357
1358/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 14:01:28 +0100