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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32L5xx/hal_lld.h
19 * @brief STM32L5xx HAL subsystem low level driver header.
20 * @pre This module requires the following macros to be defined in the
21 * @p board.h file:
22 * - STM32_LSECLK.
23 * - STM32_LSEDRV.
24 * - STM32_LSE_BYPASS (optionally).
25 * - STM32_HSECLK.
26 * - STM32_HSE_BYPASS (optionally).
27 * .
28 * One of the following macros must also be defined:
29 * - STM32L4R5xx, STM32L4R7xx, STM32L4R9xx.
30 * - STM32L4S5xx, STM32L4S7xx, STM32L4S9xx.
31 * .
32 *
33 * @addtogroup HAL
34 * @{
35 */
36
37#ifndef HAL_LLD_H
38#define HAL_LLD_H
39
40#include "stm32_registry.h"
41
42/*===========================================================================*/
43/* Driver constants. */
44/*===========================================================================*/
45
46/**
47 * @name Platform identification
48 * @{
49 */
50#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || \
51 defined(__DOXYGEN__)
52#define PLATFORM_NAME "STM32L4+ Ultra Low Power"
53
54#elif defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
55#define PLATFORM_NAME "STM32L4+ Ultra Low Power with Crypto"
56
57#else
58#error "STM32L4+ device not specified"
59#endif
60
61/**
62 * @brief Sub-family identifier.
63 */
64#if !defined(STM32L5XX) || defined(__DOXYGEN__)
65#define STM32L5XX
66#endif
67/** @} */
68
69/**
70 * @name Internal clock sources
71 * @{
72 */
73#define STM32_HSI16CLK 16000000 /**< 16MHz internal clock. */
74#define STM32_HSI48CLK 48000000 /**< 48MHz internal clock. */
75#define STM32_LSICLK 32000 /**< Low speed internal clock. */
76/** @} */
77
78/**
79 * @name PWR_CR1 register bits definitions
80 * @{
81 */
82#define STM32_VOS_MASK (3 << 9) /**< Core voltage mask. */
83#define STM32_VOS_RANGE0 (0 << 9) /**< Core voltage 1.28 Volts. */
84#define STM32_VOS_RANGE1 (1 << 9) /**< Core voltage 1.2 Volts. */
85#define STM32_VOS_RANGE2 (2 << 9) /**< Core voltage 1.0 Volts. */
86/** @} */
87
88/**
89 * @name PWR_CR2 register bits definitions
90 * @{
91 */
92#define STM32_PLS_MASK (7 << 1) /**< PLS bits mask. */
93#define STM32_PLS_LEV0 (0 << 1) /**< PVD level 0. */
94#define STM32_PLS_LEV1 (1 << 1) /**< PVD level 1. */
95#define STM32_PLS_LEV2 (2 << 1) /**< PVD level 2. */
96#define STM32_PLS_LEV3 (3 << 1) /**< PVD level 3. */
97#define STM32_PLS_LEV4 (4 << 1) /**< PVD level 4. */
98#define STM32_PLS_LEV5 (5 << 1) /**< PVD level 5. */
99#define STM32_PLS_LEV6 (6 << 1) /**< PVD level 6. */
100#define STM32_PLS_EXT (7 << 1) /**< PVD level 7. */
101/** @} */
102
103/**
104 * @name RCC_CR register bits definitions
105 * @{
106 */
107#define STM32_MSIRANGE_MASK (15 << 4) /**< MSIRANGE field mask. */
108#define STM32_MSIRANGE_100K (0 << 4) /**< 100kHz nominal. */
109#define STM32_MSIRANGE_200K (1 << 4) /**< 200kHz nominal. */
110#define STM32_MSIRANGE_400K (2 << 4) /**< 400kHz nominal. */
111#define STM32_MSIRANGE_800K (3 << 4) /**< 800kHz nominal. */
112#define STM32_MSIRANGE_1M (4 << 4) /**< 1MHz nominal. */
113#define STM32_MSIRANGE_2M (5 << 4) /**< 2MHz nominal. */
114#define STM32_MSIRANGE_4M (6 << 4) /**< 4MHz nominal. */
115#define STM32_MSIRANGE_8M (7 << 4) /**< 8MHz nominal. */
116#define STM32_MSIRANGE_16M (8 << 4) /**< 16MHz nominal. */
117#define STM32_MSIRANGE_24M (9 << 4) /**< 24MHz nominal. */
118#define STM32_MSIRANGE_32M (10 << 4) /**< 32MHz nominal. */
119#define STM32_MSIRANGE_48M (11 << 4) /**< 48MHz nominal. */
120/** @} */
121
122/**
123 * @name RCC_CFGR register bits definitions
124 * @{
125 */
126#define STM32_SW_MASK (3 << 0) /**< SW field mask. */
127#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */
128#define STM32_SW_HSI16 (1 << 0) /**< SYSCLK source is HSI. */
129#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
130#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */
131
132#define STM32_HPRE_MASK (15 << 4) /**< HPRE field mask. */
133#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
134#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
135#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
136#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
137#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
138#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
139#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
140#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
141#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
142
143#define STM32_PPRE1_MASK (7 << 8) /**< PPRE1 field mask. */
144#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
145#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
146#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
147#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
148#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
149
150#define STM32_PPRE2_MASK (7 << 11) /**< PPRE2 field mask. */
151#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
152#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
153#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
154#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
155#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
156
157#define STM32_STOPWUCK_MASK (1 << 15) /**< STOPWUCK field mask. */
158#define STM32_STOPWUCK_MSI (0 << 15) /**< Wakeup clock is MSI. */
159#define STM32_STOPWUCK_HSI16 (1 << 15) /**< Wakeup clock is HSI16. */
160
161#define STM32_MCOSEL_MASK (15 << 24) /**< MCOSEL field mask. */
162#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
163#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */
164#define STM32_MCOSEL_MSI (2 << 24) /**< MSI clock on MCO pin. */
165#define STM32_MCOSEL_HSI16 (3 << 24) /**< HSI16 clock on MCO pin. */
166#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */
167#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */
168#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */
169#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */
170#define STM32_MCOSEL_HSI48 (8 << 24) /**< HSI48 clock on MCO pin. */
171
172#define STM32_MCOPRE_MASK (7 << 28) /**< MCOPRE field mask. */
173#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
174#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 2. */
175#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 4. */
176#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 8. */
177#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 16. */
178/** @} */
179
180/**
181 * @name RCC_PLLCFGR register bits definitions
182 * @{
183 */
184#define STM32_PLLSRC_MASK (3 << 0) /**< PLL clock source mask. */
185#define STM32_PLLSRC_NOCLOCK (0 << 0) /**< PLL clock source disabled. */
186#define STM32_PLLSRC_MSI (1 << 0) /**< PLL clock source is MSI. */
187#define STM32_PLLSRC_HSI16 (2 << 0) /**< PLL clock source is HSI16. */
188#define STM32_PLLSRC_HSE (3 << 0) /**< PLL clock source is HSE. */
189
190/**
191 * @name RCC_PLLSAI1CFGR register bits definitions
192 * @{
193 */
194#define STM32_PLLSAI1SRC_MASK (3 << 0) /**< PLL clock source mask. */
195#define STM32_PLLSAI1SRC_NOCLOCK (0 << 0) /**< PLL clock source disabled. */
196#define STM32_PLLSAI1SRC_MSI (1 << 0) /**< PLL clock source is MSI. */
197#define STM32_PLLSAI1SRC_HSI16 (2 << 0) /**< PLL clock source is HSI16. */
198#define STM32_PLLSAI1SRC_HSE (3 << 0) /**< PLL clock source is HSE. */
199/** @} */
200
201/**
202 * @name RCC_PLLSAI2CFGR register bits definitions
203 * @{
204 */
205#define STM32_PLLSAI2SRC_MASK (3 << 0) /**< PLL clock source mask. */
206#define STM32_PLLSAI2SRC_NOCLOCK (0 << 0) /**< PLL clock source disabled. */
207#define STM32_PLLSAI2SRC_MSI (1 << 0) /**< PLL clock source is MSI. */
208#define STM32_PLLSAI2SRC_HSI16 (2 << 0) /**< PLL clock source is HSI16. */
209#define STM32_PLLSAI2SRC_HSE (3 << 0) /**< PLL clock source is HSE. */
210/** @} */
211
212/**
213 * @name RCC_CCIPR register bits definitions
214 * @{
215 */
216#define STM32_USART1SEL_MASK (3 << 0) /**< USART1SEL mask. */
217#define STM32_USART1SEL_PCLK2 (0 << 0) /**< USART1 source is PCLK2. */
218#define STM32_USART1SEL_SYSCLK (1 << 0) /**< USART1 source is SYSCLK. */
219#define STM32_USART1SEL_HSI16 (2 << 0) /**< USART1 source is HSI16. */
220#define STM32_USART1SEL_LSE (3 << 0) /**< USART1 source is LSE. */
221
222#define STM32_USART2SEL_MASK (3 << 2) /**< USART2 mask. */
223#define STM32_USART2SEL_PCLK1 (0 << 2) /**< USART2 source is PCLK1. */
224#define STM32_USART2SEL_SYSCLK (1 << 2) /**< USART2 source is SYSCLK. */
225#define STM32_USART2SEL_HSI16 (2 << 2) /**< USART2 source is HSI16. */
226#define STM32_USART2SEL_LSE (3 << 2) /**< USART2 source is LSE. */
227
228#define STM32_USART3SEL_MASK (3 << 4) /**< USART3 mask. */
229#define STM32_USART3SEL_PCLK1 (0 << 4) /**< USART3 source is PCLK1. */
230#define STM32_USART3SEL_SYSCLK (1 << 4) /**< USART3 source is SYSCLK. */
231#define STM32_USART3SEL_HSI16 (2 << 4) /**< USART3 source is HSI16. */
232#define STM32_USART3SEL_LSE (3 << 4) /**< USART3 source is LSE. */
233
234#define STM32_UART4SEL_MASK (3 << 6) /**< UART4 mask. */
235#define STM32_UART4SEL_PCLK1 (0 << 6) /**< UART4 source is PCLK1. */
236#define STM32_UART4SEL_SYSCLK (1 << 6) /**< UART4 source is SYSCLK. */
237#define STM32_UART4SEL_HSI16 (2 << 6) /**< UART4 source is HSI16. */
238#define STM32_UART4SEL_LSE (3 << 6) /**< UART4 source is LSE. */
239
240#define STM32_UART5SEL_MASK (3 << 8) /**< UART5 mask. */
241#define STM32_UART5SEL_PCLK1 (0 << 8) /**< UART5 source is PCLK1. */
242#define STM32_UART5SEL_SYSCLK (1 << 8) /**< UART5 source is SYSCLK. */
243#define STM32_UART5SEL_HSI16 (2 << 8) /**< UART5 source is HSI16. */
244#define STM32_UART5SEL_LSE (3 << 8) /**< UART5 source is LSE. */
245
246#define STM32_LPUART1SEL_MASK (3 << 10) /**< LPUART1 mask. */
247#define STM32_LPUART1SEL_PCLK1 (0 << 10) /**< LPUART1 source is PCLK1. */
248#define STM32_LPUART1SEL_SYSCLK (1 << 10) /**< LPUART1 source is SYSCLK. */
249#define STM32_LPUART1SEL_HSI16 (2 << 10) /**< LPUART1 source is HSI16. */
250#define STM32_LPUART1SEL_LSE (3 << 10) /**< LPUART1 source is LSE. */
251
252#define STM32_I2C1SEL_MASK (3 << 12) /**< I2C1SEL mask. */
253#define STM32_I2C1SEL_PCLK1 (0 << 12) /**< I2C1 source is PCLK1. */
254#define STM32_I2C1SEL_SYSCLK (1 << 12) /**< I2C1 source is SYSCLK. */
255#define STM32_I2C1SEL_HSI16 (2 << 12) /**< I2C1 source is HSI16. */
256
257#define STM32_I2C2SEL_MASK (3 << 14) /**< I2C2SEL mask. */
258#define STM32_I2C2SEL_PCLK1 (0 << 14) /**< I2C2 source is PCLK1. */
259#define STM32_I2C2SEL_SYSCLK (1 << 14) /**< I2C2 source is SYSCLK. */
260#define STM32_I2C2SEL_HSI16 (2 << 14) /**< I2C2 source is HSI16. */
261
262#define STM32_I2C3SEL_MASK (3 << 16) /**< I2C3SEL mask. */
263#define STM32_I2C3SEL_PCLK1 (0 << 16) /**< I2C3 source is PCLK1. */
264#define STM32_I2C3SEL_SYSCLK (1 << 16) /**< I2C3 source is SYSCLK. */
265#define STM32_I2C3SEL_HSI16 (2 << 16) /**< I2C3 source is HSI16. */
266
267#define STM32_LPTIM1SEL_MASK (3 << 18) /**< LPTIM1SEL mask. */
268#define STM32_LPTIM1SEL_PCLK1 (0 << 18) /**< LPTIM1 source is PCLK1. */
269#define STM32_LPTIM1SEL_LSI (1 << 18) /**< LPTIM1 source is LSI. */
270#define STM32_LPTIM1SEL_HSI16 (2 << 18) /**< LPTIM1 source is HSI16. */
271#define STM32_LPTIM1SEL_LSE (3 << 18) /**< LPTIM1 source is LSE. */
272
273#define STM32_LPTIM2SEL_MASK (3 << 20) /**< LPTIM2SEL mask. */
274#define STM32_LPTIM2SEL_PCLK1 (0 << 20) /**< LPTIM2 source is PCLK1. */
275#define STM32_LPTIM2SEL_LSI (1 << 20) /**< LPTIM2 source is LSI. */
276#define STM32_LPTIM2SEL_HSI16 (2 << 20) /**< LPTIM2 source is HSI16. */
277#define STM32_LPTIM2SEL_LSE (3 << 20) /**< LPTIM2 source is LSE. */
278
279#define STM32_LPTIM3SEL_MASK (3 << 22) /**< LPTIM3SEL mask. */
280#define STM32_LPTIM3SEL_PCLK1 (0 << 22) /**< LPTIM3 source is PCLK1. */
281#define STM32_LPTIM3SEL_LSI (1 << 22) /**< LPTIM3 source is LSI. */
282#define STM32_LPTIM3SEL_HSI16 (2 << 22) /**< LPTIM3 source is HSI16. */
283#define STM32_LPTIM3SEL_LSE (3 << 22) /**< LPTIM3 source is LSE. */
284
285#define STM32_FDCANSEL_MASK (3 << 24) /**< FDCANSEL mask. */
286#define STM32_FDCANSEL_HSE (0 << 24) /**< FDCAN source is HSE. */
287#define STM32_FDCANSEL_PLL (1 << 24) /**< FDCAN source is PLL-Q. */
288#define STM32_FDCANSEL_PLLSAI1 (2 << 24) /**< FDCAN source is PLLSAI1-P. */
289
290#define STM32_CLK48SEL_MASK (3 << 26) /**< CLK48SEL mask. */
291#define STM32_CLK48SEL_HSI48 (0 << 26) /**< CLK48 source is HSI48. */
292#define STM32_CLK48SEL_PLLSAI1 (1 << 26) /**< CLK48 source is PLLSAI1-Q. */
293#define STM32_CLK48SEL_PLL (2 << 26) /**< CLK48 source is PLL-Q. */
294#define STM32_CLK48SEL_MSI (3 << 26) /**< CLK48 source is MSI. */
295
296#define STM32_ADCSEL_MASK (3 << 28) /**< ADCSEL mask. */
297#define STM32_ADCSEL_NOCLK (0 << 28) /**< ADC clock disabled. */
298#define STM32_ADCSEL_PLLSAI1 (1 << 28) /**< ADC source is PLLSAI1-R. */
299#define STM32_ADCSEL_SYSCLK (3 << 28) /**< ADC source is SYSCLK. */
300/** @} */
301
302/**
303 * @name RCC_CCIPR2 register bits definitions
304 * @{
305 */
306#define STM32_I2C4SEL_MASK (3 << 0) /**< I2C1SEL mask. */
307#define STM32_I2C4SEL_PCLK1 (0 << 0) /**< I2C1 source is PCLK1. */
308#define STM32_I2C4SEL_SYSCLK (1 << 0) /**< I2C1 source is SYSCLK. */
309#define STM32_I2C4SEL_HSI16 (2 << 0) /**< I2C1 source is HSI16. */
310
311#define STM32_DFSDMSEL_MASK (1 << 2) /**< DFSDMSEL mask. */
312#define STM32_DFSDMSEL_PCLK2 (0 << 2) /**< DFSDMSEL source is PCLK2. */
313#define STM32_DFSDMSEL_SYSCLK (1 << 2) /**< DFSDMSEL source is SYSCLK. */
314
315#define STM32_ADFSDMSEL_MASK (3 << 3) /**< ADFSDMSEL mask. */
316#define STM32_ADFSDMSEL_SAI1CLK (0 << 3) /**< ADFSDMSEL source is
317 SAI1CLK. */
318#define STM32_ADFSDMSEL_HSI16 (1 << 3) /**< ADFSDMSEL source is HSI16. */
319#define STM32_ADFSDMSEL_MSI (2 << 3) /**< ADFSDMSEL source is MSI. */
320
321#define STM32_SAI1SEL_MASK (7 << 5) /**< SAI1SEL mask. */
322#define STM32_SAI1SEL_PLLSAI1 (0 << 5) /**< SAI1 source is PLLSAI1CLK. */
323#define STM32_SAI1SEL_PLLSAI2 (1 << 5) /**< SAI1 source is PLLSAI2CLK. */
324#define STM32_SAI1SEL_PLL (2 << 5) /**< SAI1 source is PLLSAI3CLK */
325#define STM32_SAI1SEL_EXTCLK (3 << 5) /**< SAI1 source is external. */
326#define STM32_SAI1SEL_HSI16 (4 << 5) /**< SAI1 source is HSI16. */
327#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
328
329#define STM32_SAI2SEL_MASK (7 << 8) /**< SAI2SEL mask. */
330#define STM32_SAI2SEL_PLLSAI1 (0 << 8) /**< SAI2 source is PLLSAI1CLK. */
331#define STM32_SAI2SEL_PLLSAI2 (1 << 8) /**< SAI2 source is PLLSAI2CLK. */
332#define STM32_SAI2SEL_PLL (2 << 8) /**< SAI2 source is PLLSAI3CLK */
333#define STM32_SAI2SEL_EXTCLK (3 << 8) /**< SAI2 source is external. */
334#define STM32_SAI2SEL_HSI16 (4 << 8) /**< SAI2 source is HSI16. */
335#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
336
337#define STM32_SDMMCSEL_MASK (1 << 14) /**< SDMMCSEL mask. */
338#define STM32_SDMMCSEL_48CLK (0 << 14) /**< SDMMCSEL source is 48CLK. */
339#define STM32_SDMMCSEL_PLL (1 << 14) /**< SDMMCSEL source is
340 PLLSAI3CLK. */
341
342#define STM32_OSPISEL_MASK (3 << 20) /**< OSPISEL mask. */
343#define STM32_OSPISEL_SYSCLK (0 << 20) /**< OSPI source is SYSCLK. */
344#define STM32_OSPISEL_MSI (1 << 20) /**< OSPI source is MSI. */
345#define STM32_OSPISEL_48CLK (2 << 20) /**< OSPI source is 48CLK. */
346/** @} */
347
348/**
349 * @name RCC_BDCR register bits definitions
350 * @{
351 */
352#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */
353#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */
354#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */
355#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */
356#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */
357
358#define STM32_LSCOSEL_MASK (3 << 24) /**< LSCO pin clock source. */
359#define STM32_LSCOSEL_NOCLOCK (0 << 24) /**< No clock on LSCO pin. */
360#define STM32_LSCOSEL_LSI (1 << 24) /**< LSI on LSCO pin. */
361#define STM32_LSCOSEL_LSE (3 << 24) /**< LSE on LSCO pin. */
362/** @} */
363
364/**
365 * @name RCC_CSR register bits definitions
366 * @{
367 */
368#define STM32_MSISRANGE_MASK (15 << 8) /**< MSISRANGE field mask. */
369#define STM32_MSISRANGE_1M (4 << 8) /**< 1MHz nominal. */
370#define STM32_MSISRANGE_2M (5 << 8) /**< 2MHz nominal. */
371#define STM32_MSISRANGE_4M (6 << 8) /**< 4MHz nominal. */
372#define STM32_MSISRANGE_8M (7 << 8) /**< 8MHz nominal. */
373/** @} */
374
375/*===========================================================================*/
376/* Driver pre-compile time settings. */
377/*===========================================================================*/
378
379/**
380 * @name Configuration options
381 * @{
382 */
383/**
384 * @brief Disables the PWR/RCC initialization in the HAL.
385 */
386#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
387#define STM32_NO_INIT FALSE
388#endif
389
390/**
391 * @brief Core voltage selection.
392 * @note This setting affects all the performance and clock related
393 * settings, the maximum performance is only obtainable selecting
394 * the maximum voltage.
395 */
396#if !defined(STM32_VOS) || defined(__DOXYGEN__)
397#define STM32_VOS STM32_VOS_RANGE1
398#endif
399
400/**
401 * @brief Enables or disables the programmable voltage detector.
402 */
403#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
404#define STM32_PVD_ENABLE FALSE
405#endif
406
407/**
408 * @brief Sets voltage level for programmable voltage detector.
409 */
410#if !defined(STM32_PLS) || defined(__DOXYGEN__)
411#define STM32_PLS STM32_PLS_LEV0
412#endif
413
414/**
415 * @brief Enables or disables the HSI16 clock source.
416 */
417#if !defined(STM32_HSI16_ENABLED) || defined(__DOXYGEN__)
418#define STM32_HSI16_ENABLED FALSE
419#endif
420
421/**
422 * @brief Enables or disables the HSI48 clock source.
423 */
424#if !defined(STM32_HSI48_ENABLED) || defined(__DOXYGEN__)
425#define STM32_HSI48_ENABLED FALSE
426#endif
427
428/**
429 * @brief Enables or disables the LSI clock source.
430 */
431#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
432#define STM32_LSI_ENABLED TRUE
433#endif
434
435/**
436 * @brief Enables or disables the HSE clock source.
437 */
438#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
439#define STM32_HSE_ENABLED FALSE
440#endif
441
442/**
443 * @brief Enables or disables the LSE clock source.
444 */
445#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
446#define STM32_LSE_ENABLED FALSE
447#endif
448
449/**
450 * @brief Enables or disables the MSI PLL on LSE clock source.
451 */
452#if !defined(STM32_MSIPLL_ENABLED) || defined(__DOXYGEN__)
453#define STM32_MSIPLL_ENABLED FALSE
454#endif
455
456/**
457 * @brief MSI frequency setting.
458 */
459#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__)
460#define STM32_MSIRANGE STM32_MSIRANGE_4M
461#endif
462
463/**
464 * @brief MSI frequency setting after standby.
465 */
466#if !defined(STM32_MSISRANGE) || defined(__DOXYGEN__)
467#define STM32_MSISRANGE STM32_MSISRANGE_4M
468#endif
469
470/**
471 * @brief Main clock source selection.
472 * @note If the selected clock source is not the PLL then the PLL is not
473 * initialized and started.
474 * @note The default value is calculated for a 120MHz system clock from
475 * the internal 4MHz MSI clock.
476 */
477#if !defined(STM32_SW) || defined(__DOXYGEN__)
478#define STM32_SW STM32_SW_PLL
479#endif
480
481/**
482 * @brief Clock source for the PLL.
483 * @note This setting has only effect if the PLL is selected as the
484 * system clock source.
485 * @note The default value is calculated for a 120MHz system clock from
486 * the internal 4MHz MSI clock.
487 */
488#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
489#define STM32_PLLSRC STM32_PLLSRC_MSI
490#endif
491
492/**
493 * @brief PLLM divider value.
494 * @note The allowed values are 1..16.
495 * @note The default value is calculated for a 120MHz system clock from
496 * the internal 4MHz MSI clock.
497 */
498#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
499#define STM32_PLLM_VALUE 1
500#endif
501
502/**
503 * @brief PLLN multiplier value.
504 * @note The allowed values are 8..127.
505 * @note The default value is calculated for a 120MHz system clock from
506 * the internal 4MHz MSI clock.
507 */
508#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
509#define STM32_PLLN_VALUE 60
510#endif
511
512/**
513 * @brief PLLPDIV divider value or zero if disabled.
514 * @note The allowed values are 0, 2..31.
515 */
516#if !defined(STM32_PLLPDIV_VALUE) || defined(__DOXYGEN__)
517#define STM32_PLLPDIV_VALUE 0
518#endif
519
520/**
521 * @brief PLLP divider value.
522 * @note The allowed values are 7, 17.
523 */
524#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
525#define STM32_PLLP_VALUE 7
526#endif
527
528/**
529 * @brief PLLQ divider value.
530 * @note The allowed values are 2, 4, 6, 8.
531 */
532#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
533#define STM32_PLLQ_VALUE 4
534#endif
535
536/**
537 * @brief PLLR divider value.
538 * @note The allowed values are 2, 4, 6, 8.
539 * @note The default value is calculated for a 120MHz system clock from
540 * the internal 4MHz MSI clock.
541 */
542#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
543#define STM32_PLLR_VALUE 2
544#endif
545
546/**
547 * @brief AHB prescaler value.
548 * @note The default value is calculated for a 120MHz system clock from
549 * the internal 4MHz MSI clock.
550 */
551#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
552#define STM32_HPRE STM32_HPRE_DIV1
553#endif
554
555/**
556 * @brief APB1 prescaler value.
557 */
558#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
559#define STM32_PPRE1 STM32_PPRE1_DIV1
560#endif
561
562/**
563 * @brief APB2 prescaler value.
564 */
565#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
566#define STM32_PPRE2 STM32_PPRE2_DIV1
567#endif
568
569/**
570 * @brief STOPWUCK clock setting.
571 */
572#if !defined(STM32_STOPWUCK) || defined(__DOXYGEN__)
573#define STM32_STOPWUCK STM32_STOPWUCK_MSI
574#endif
575
576/**
577 * @brief MCO clock source.
578 */
579#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
580#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
581#endif
582
583/**
584 * @brief MCO divider setting.
585 */
586#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
587#define STM32_MCOPRE STM32_MCOPRE_DIV1
588#endif
589
590/**
591 * @brief LSCO clock source.
592 */
593#if !defined(STM32_LSCOSEL) || defined(__DOXYGEN__)
594#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
595#endif
596
597/**
598 * @brief Clock source for the PLLSAL1.
599 */
600#if !defined(STM32_PLLSAI1SRC) || defined(__DOXYGEN__)
601#define STM32_PLLSAI1SRC STM32_PLLSAI1SRC_MSI
602#endif
603
604/**
605 * @brief PLLSAI1M divider value.
606 * @note The allowed values are 1..16.
607 * @note The default value is calculated for a 120MHz system clock from
608 * the internal 4MHz MSI clock.
609 */
610#if !defined(STM32_PLLSAI1M_VALUE) || defined(__DOXYGEN__)
611#define STM32_PLLSAI1M_VALUE 1
612#endif
613
614/**
615 * @brief PLLSAI1N multiplier value.
616 * @note The allowed values are 8..127.
617 */
618#if !defined(STM32_PLLSAI1N_VALUE) || defined(__DOXYGEN__)
619#define STM32_PLLSAI1N_VALUE 72
620#endif
621
622/**
623 * @brief PLLSAI1PDIV divider value or zero if disabled.
624 * @note The allowed values are 0, 2..31.
625 */
626#if !defined(STM32_PLLSAI1PDIV_VALUE) || defined(__DOXYGEN__)
627#define STM32_PLLSAI1PDIV_VALUE 6
628#endif
629
630/**
631 * @brief PLLSAI1P divider value.
632 * @note The allowed values are 7, 17.
633 */
634#if !defined(STM32_PLLSAI1P_VALUE) || defined(__DOXYGEN__)
635#define STM32_PLLSAI1P_VALUE 7
636#endif
637
638/**
639 * @brief PLLSAI1Q divider value.
640 * @note The allowed values are 2, 4, 6, 8.
641 */
642#if !defined(STM32_PLLSAI1Q_VALUE) || defined(__DOXYGEN__)
643#define STM32_PLLSAI1Q_VALUE 6
644#endif
645
646/**
647 * @brief PLLSAI1R divider value.
648 * @note The allowed values are 2, 4, 6, 8.
649 */
650#if !defined(STM32_PLLSAI1R_VALUE) || defined(__DOXYGEN__)
651#define STM32_PLLSAI1R_VALUE 6
652#endif
653
654/**
655 * @brief Clock source for the PLLSAL2.
656 */
657#if !defined(STM32_PLLSAI2SRC) || defined(__DOXYGEN__)
658#define STM32_PLLSAI2SRC STM32_PLLSAI2SRC_MSI
659#endif
660
661/**
662 * @brief PLLSAI2M divider value.
663 * @note The allowed values are 1..16.
664 * @note The default value is calculated for a 120MHz system clock from
665 * the internal 4MHz MSI clock.
666 */
667#if !defined(STM32_PLLSAI2M_VALUE) || defined(__DOXYGEN__)
668#define STM32_PLLSAI2M_VALUE 1
669#endif
670
671/**
672 * @brief PLLSAI2N multiplier value.
673 * @note The allowed values are 8..127.
674 */
675#if !defined(STM32_PLLSAI2N_VALUE) || defined(__DOXYGEN__)
676#define STM32_PLLSAI2N_VALUE 72
677#endif
678
679/**
680 * @brief PLLSAI2PDIV divider value or zero if disabled.
681 * @note The allowed values are 0, 2..31.
682 */
683#if !defined(STM32_PLLSAI2PDIV_VALUE) || defined(__DOXYGEN__)
684#define STM32_PLLSAI2PDIV_VALUE 6
685#endif
686
687/**
688 * @brief PLLSAI2P divider value.
689 * @note The allowed values are 7, 17.
690 */
691#if !defined(STM32_PLLSAI2P_VALUE) || defined(__DOXYGEN__)
692#define STM32_PLLSAI2P_VALUE 7
693#endif
694
695/**
696 * @brief PLLSAI2Q divider value.
697 * @note The allowed values are 2, 4, 6, 8.
698 */
699#if !defined(STM32_PLLSAI2Q_VALUE) || defined(__DOXYGEN__)
700#define STM32_PLLSAI2Q_VALUE 6
701#endif
702
703/**
704 * @brief PLLSAI2R divider value.
705 * @note The allowed values are 2, 4, 6, 8.
706 */
707#if !defined(STM32_PLLSAI2R_VALUE) || defined(__DOXYGEN__)
708#define STM32_PLLSAI2R_VALUE 6
709#endif
710
711/**
712 * @brief PLLSAI2DIVR value.
713 */
714#if !defined(STM32_PLLSAI2DIVR) || defined(__DOXYGEN__)
715#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16
716#endif
717
718/**
719 * @brief USART1 clock source.
720 */
721#if !defined(STM32_USART1SEL) || defined(__DOXYGEN__)
722#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
723#endif
724
725/**
726 * @brief USART2 clock source.
727 */
728#if !defined(STM32_USART2SEL) || defined(__DOXYGEN__)
729#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
730#endif
731
732/**
733 * @brief USART3 clock source.
734 */
735#if !defined(STM32_USART3SEL) || defined(__DOXYGEN__)
736#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
737#endif
738
739/**
740 * @brief UART4 clock source.
741 */
742#if !defined(STM32_UART4SEL) || defined(__DOXYGEN__)
743#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
744#endif
745
746/**
747 * @brief UART5 clock source.
748 */
749#if !defined(STM32_UART5SEL) || defined(__DOXYGEN__)
750#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
751#endif
752
753/**
754 * @brief LPUART1 clock source.
755 */
756#if !defined(STM32_LPUART1SEL) || defined(__DOXYGEN__)
757#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
758#endif
759
760/**
761 * @brief I2C1 clock source.
762 */
763#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__)
764#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
765#endif
766
767/**
768 * @brief I2C2 clock source.
769 */
770#if !defined(STM32_I2C2SEL) || defined(__DOXYGEN__)
771#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
772#endif
773
774/**
775 * @brief I2C3 clock source.
776 */
777#if !defined(STM32_I2C3SEL) || defined(__DOXYGEN__)
778#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
779#endif
780
781/**
782 * @brief I2C4 clock source.
783 */
784#if !defined(STM32_I2C4SEL) || defined(__DOXYGEN__)
785#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
786#endif
787
788/**
789 * @brief LPTIM1 clock source.
790 */
791#if !defined(STM32_LPTIM1SEL) || defined(__DOXYGEN__)
792#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
793#endif
794
795/**
796 * @brief LPTIM2 clock source.
797 */
798#if !defined(STM32_LPTIM2SEL) || defined(__DOXYGEN__)
799#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
800#endif
801
802/**
803 * @brief LPTIM3 clock source.
804 */
805#if !defined(STM32_LPTIM3SEL) || defined(__DOXYGEN__)
806#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
807#endif
808
809/**
810 * @brief FDCAN value (48MHz clock source).
811 */
812#if !defined(STM32_FDCANSEL) || defined(__DOXYGEN__)
813#define STM32_FDCANSEL STM32_FDCANSEL_PLL
814#endif
815
816/**
817 * @brief CLK48SEL value (48MHz clock source).
818 */
819#if !defined(STM32_CLK48SEL) || defined(__DOXYGEN__)
820#define STM32_CLK48SEL STM32_CLK48SEL_PLL
821#endif
822
823/**
824 * @brief ADCSEL value (ADCs clock source).
825 */
826#if !defined(STM32_ADCSEL) || defined(__DOXYGEN__)
827#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
828#endif
829
830/**
831 * @brief DFSDMSEL value (DFSDM clock source).
832 */
833#if !defined(STM32_DFSDMSEL) || defined(__DOXYGEN__)
834#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
835#endif
836
837/**
838 * @brief ADFSDMSEL value (DFSDM clock source).
839 */
840#if !defined(STM32_ADFSDMSEL) || defined(__DOXYGEN__)
841#define STM32_ADFSDMSEL STM32_ADFSDMSEL_SAI1CLK
842#endif
843
844/**
845 * @brief SAI1SEL value (SAI1 clock source).
846 */
847#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
848#define STM32_SAI1SEL STM32_SAI1SEL_OFF
849#endif
850
851/**
852 * @brief SAI2SEL value (SAI2 clock source).
853 */
854#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__)
855#define STM32_SAI2SEL STM32_SAI2SEL_OFF
856#endif
857
858/**
859 * @brief SDMMC value (SDMMC clock source).
860 */
861#if !defined(STM32_SDMMCSEL) || defined(__DOXYGEN__)
862#define STM32_SDMMCSEL STM32_SDMMCSEL_48CLK
863#endif
864
865/**
866 * @brief OSPISEL value (OSPISEL clock source).
867 */
868#if !defined(STM32_OSPISEL) || defined(__DOXYGEN__)
869#define STM32_OSPISEL STM32_OSPISEL_SYSCLK
870#endif
871
872/**
873 * @brief RTC/LCD clock source.
874 */
875#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
876#define STM32_RTCSEL STM32_RTCSEL_LSI
877#endif
878/** @} */
879
880/*===========================================================================*/
881/* Derived constants and error checks. */
882/*===========================================================================*/
883
884/*
885 * Configuration-related checks.
886 */
887#if !defined(STM32L5xx_MCUCONF)
888#error "Using a wrong mcuconf.h file, STM32L5xx_MCUCONF not defined"
889#endif
890
891#if defined(STM32L5YYxx) && !defined(STM32L5YY_MCUCONF)
892#error "Using a wrong mcuconf.h file, STM32L5YY_MCUCONF not defined"
893
894#endif
895
896/*
897 * Board files sanity checks.
898 */
899#if !defined(STM32_LSECLK)
900#error "STM32_LSECLK not defined in board.h"
901#endif
902
903#if !defined(STM32_LSEDRV)
904#error "STM32_LSEDRV not defined in board.h"
905#endif
906
907#if !defined(STM32_HSECLK)
908#error "STM32_HSECLK not defined in board.h"
909#endif
910
911/* Voltage related limits.*/
912#if (STM32_VOS == STM32_VOS_RANGE0) || defined(__DOXYGEN__)
913/**
914 * @name System Limits
915 * @{
916 */
917/**
918 * @brief Maximum SYSCLK clock frequency.
919 */
920#define STM32_SYSCLK_MAX 110000000
921
922/**
923 * @brief Maximum HSE clock frequency at current voltage setting.
924 */
925#define STM32_HSECLK_MAX 48000000
926
927/**
928 * @brief Maximum HSE clock frequency using an external source.
929 */
930#define STM32_HSECLK_BYP_MAX 48000000
931
932/**
933 * @brief Minimum HSE clock frequency.
934 */
935#define STM32_HSECLK_MIN 4000000
936
937/**
938 * @brief Minimum HSE clock frequency using an external source.
939 */
940#define STM32_HSECLK_BYP_MIN 8000000
941
942/**
943 * @brief Maximum LSE clock frequency.
944 */
945#define STM32_LSECLK_MAX 32768
946
947/**
948 * @brief Maximum LSE clock frequency.
949 */
950#define STM32_LSECLK_BYP_MAX 1000000
951
952/**
953 * @brief Minimum LSE clock frequency.
954 */
955#define STM32_LSECLK_MIN 32768
956
957/**
958 * @brief Minimum LSE clock frequency.
959 */
960#define STM32_LSECLK_BYP_MIN 32768
961
962/**
963 * @brief Maximum PLLs input clock frequency.
964 */
965#define STM32_PLLIN_MAX 16000000
966
967/**
968 * @brief Minimum PLLs input clock frequency.
969 */
970#define STM32_PLLIN_MIN 2660000
971
972/**
973 * @brief Maximum VCO clock frequency at current voltage setting.
974 */
975#define STM32_PLLVCO_MAX 344000000
976
977/**
978 * @brief Minimum VCO clock frequency at current voltage setting.
979 */
980#define STM32_PLLVCO_MIN 64000000
981
982/**
983 * @brief Maximum PLL-P output clock frequency.
984 */
985#define STM32_PLLP_MAX 110000000
986
987/**
988 * @brief Minimum PLL-P output clock frequency.
989 */
990#define STM32_PLLP_MIN 2064500
991
992/**
993 * @brief Maximum PLL-Q output clock frequency.
994 */
995#define STM32_PLLQ_MAX 110000000
996
997/**
998 * @brief Minimum PLL-Q output clock frequency.
999 */
1000#define STM32_PLLQ_MIN 8000000
1001
1002/**
1003 * @brief Maximum PLL-R output clock frequency.
1004 */
1005#define STM32_PLLR_MAX 110000000
1006
1007/**
1008 * @brief Minimum PLL-R output clock frequency.
1009 */
1010#define STM32_PLLR_MIN 8000000
1011
1012/**
1013 * @brief Maximum APB1 clock frequency.
1014 */
1015#define STM32_PCLK1_MAX 110000000
1016
1017/**
1018 * @brief Maximum APB2 clock frequency.
1019 */
1020#define STM32_PCLK2_MAX 110000000
1021
1022/**
1023 * @brief Maximum ADC clock frequency.
1024 */
1025#define STM32_ADCCLK_MAX 80000000
1026/** @} */
1027
1028/**
1029 * @name Flash Wait states
1030 * @{
1031 */
1032#define STM32_0WS_THRESHOLD 20000000
1033#define STM32_1WS_THRESHOLD 40000000
1034#define STM32_2WS_THRESHOLD 60000000
1035#define STM32_3WS_THRESHOLD 80000000
1036#define STM32_4WS_THRESHOLD 100000000
1037#define STM32_5WS_THRESHOLD 110000000
1038/** @} */
1039
1040#elif STM32_VOS == STM32_VOS_RANGE1
1041#define STM32_SYSCLK_MAX 80000000
1042#define STM32_HSECLK_MAX 48000000
1043#define STM32_HSECLK_BYP_MAX 48000000
1044#define STM32_HSECLK_MIN 4000000
1045#define STM32_HSECLK_BYP_MIN 8000000
1046#define STM32_LSECLK_MAX 32768
1047#define STM32_LSECLK_BYP_MAX 1000000
1048#define STM32_LSECLK_MIN 32768
1049#define STM32_LSECLK_BYP_MIN 32768
1050#define STM32_PLLIN_MAX 16000000
1051#define STM32_PLLIN_MIN 2660000
1052#define STM32_PLLVCO_MAX 344000000
1053#define STM32_PLLVCO_MIN 64000000
1054#define STM32_PLLP_MAX 110000000
1055#define STM32_PLLP_MIN 2064500
1056#define STM32_PLLQ_MAX 110000000
1057#define STM32_PLLQ_MIN 8000000
1058#define STM32_PLLR_MAX 110000000
1059#define STM32_PLLR_MIN 8000000
1060#define STM32_PCLK1_MAX 80000000
1061#define STM32_PCLK2_MAX 80000000
1062#define STM32_ADCCLK_MAX 80000000
1063
1064#define STM32_0WS_THRESHOLD 20000000
1065#define STM32_1WS_THRESHOLD 40000000
1066#define STM32_2WS_THRESHOLD 60000000
1067#define STM32_3WS_THRESHOLD 80000000
1068#define STM32_4WS_THRESHOLD 0
1069#define STM32_5WS_THRESHOLD 0
1070
1071#elif STM32_VOS == STM32_VOS_RANGE2
1072#define STM32_SYSCLK_MAX 26000000
1073#define STM32_HSECLK_MAX 26000000
1074#define STM32_HSECLK_BYP_MAX 26000000
1075#define STM32_HSECLK_MIN 4000000
1076#define STM32_HSECLK_BYP_MIN 8000000
1077#define STM32_LSECLK_MAX 32768
1078#define STM32_LSECLK_BYP_MAX 1000000
1079#define STM32_LSECLK_MIN 32768
1080#define STM32_LSECLK_BYP_MIN 32768
1081#define STM32_PLLIN_MAX 16000000
1082#define STM32_PLLIN_MIN 2660000
1083#define STM32_PLLVCO_MAX 128000000
1084#define STM32_PLLVCO_MIN 64000000
1085#define STM32_PLLP_MAX 26000000
1086#define STM32_PLLP_MIN 2064500
1087#define STM32_PLLQ_MAX 26000000
1088#define STM32_PLLQ_MIN 8000000
1089#define STM32_PLLR_MAX 26000000
1090#define STM32_PLLR_MIN 8000000
1091#define STM32_PCLK1_MAX 26000000
1092#define STM32_PCLK2_MAX 26000000
1093#define STM32_ADCCLK_MAX 26000000
1094
1095#define STM32_0WS_THRESHOLD 8000000
1096#define STM32_1WS_THRESHOLD 16000000
1097#define STM32_2WS_THRESHOLD 26000000
1098#define STM32_3WS_THRESHOLD 0
1099#define STM32_4WS_THRESHOLD 0
1100#define STM32_5WS_THRESHOLD 0
1101
1102#else
1103 #error "invalid STM32_VOS value specified"
1104#endif
1105
1106/**
1107 * @brief MSI frequency.
1108 */
1109#if STM32_MSIRANGE == STM32_MSIRANGE_100K
1110 #define STM32_MSICLK 100000
1111#elif STM32_MSIRANGE == STM32_MSIRANGE_200K
1112 #define STM32_MSICLK 200000
1113#elif STM32_MSIRANGE == STM32_MSIRANGE_400K
1114 #define STM32_MSICLK 400000
1115#elif STM32_MSIRANGE == STM32_MSIRANGE_800K
1116 #define STM32_MSICLK 800000
1117#elif STM32_MSIRANGE == STM32_MSIRANGE_1M
1118 #define STM32_MSICLK 1000000
1119#elif STM32_MSIRANGE == STM32_MSIRANGE_2M
1120 #define STM32_MSICLK 2000000
1121#elif STM32_MSIRANGE == STM32_MSIRANGE_4M
1122 #define STM32_MSICLK 4000000
1123#elif STM32_MSIRANGE == STM32_MSIRANGE_8M
1124 #define STM32_MSICLK 8000000
1125#elif STM32_MSIRANGE == STM32_MSIRANGE_16M
1126 #define STM32_MSICLK 16000000
1127#elif STM32_MSIRANGE == STM32_MSIRANGE_24M
1128 #define STM32_MSICLK 24000000
1129#elif STM32_MSIRANGE == STM32_MSIRANGE_32M
1130 #define STM32_MSICLK 32000000
1131#elif STM32_MSIRANGE == STM32_MSIRANGE_48M
1132 #define STM32_MSICLK 48000000
1133#else
1134 #error "invalid STM32_MSIRANGE value specified"
1135#endif
1136
1137/**
1138 * @brief MSIS frequency.
1139 */
1140#if STM32_MSISRANGE == STM32_MSISRANGE_1M
1141 #define STM32_MSISCLK 1000000
1142#elif STM32_MSISRANGE == STM32_MSISRANGE_2M
1143 #define STM32_MSISCLK 2000000
1144#elif STM32_MSISRANGE == STM32_MSISRANGE_4M
1145 #define STM32_MSISCLK 4000000
1146#elif STM32_MSISRANGE == STM32_MSISRANGE_8M
1147 #define STM32_MSISCLK 8000000
1148#else
1149 #error "invalid STM32_MSISRANGE value specified"
1150#endif
1151
1152/*
1153 * HSI16 related checks.
1154 */
1155#if STM32_HSI16_ENABLED
1156#else /* !STM32_HSI16_ENABLED */
1157
1158 #if STM32_SW == STM32_SW_HSI16
1159 #error "HSI16 not enabled, required by STM32_SW"
1160 #endif
1161
1162 #if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI16)
1163 #error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC"
1164 #endif
1165
1166 /* MCO-related checks.*/
1167 #if (STM32_MCOSEL == STM32_MCOSEL_HSI16) || \
1168 ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
1169 (STM32_PLLSRC == STM32_PLLSRC_HSI16))
1170 #error "HSI16 not enabled, required by STM32_MCOSEL"
1171 #endif
1172
1173 /* SAI1-related checks.*/
1174 #if STM32_SAI1SEL == STM32_SAI1SEL_HSI16
1175 #error "HSI16 not enabled, required by STM32_SAI1SEL"
1176 #endif
1177
1178 #if (STM32_SAI1SEL == STM32_SAI1SEL_PLL) && \
1179 (STM32_PLLSRC == STM32_PLLSRC_HSI16)
1180 #error "HSI16 not enabled, required by STM32_SAI1SEL"
1181 #endif
1182
1183 #if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) && \
1184 (STM32_PLLSAI1SRC == STM32_PLLSAI1SRC_HSI16)
1185 #error "HSI16 not enabled, required by STM32_PLLSAI1SRC"
1186 #endif
1187
1188 #if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) && \
1189 (STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_HSI16)
1190 #error "HSI16 not enabled, required by STM32_PLLSAI2SRC"
1191 #endif
1192
1193 /* SAI2-related checks.*/
1194 #if STM32_SAI2SEL == STM32_SAI12SEL_HSI16
1195 #error "HSI16 not enabled, required by STM32_SAI2SEL"
1196 #endif
1197
1198 #if (STM32_SAI2SEL == STM32_SAI2SEL_PLL) && \
1199 (STM32_PLLSRC == STM32_PLLSRC_HSI16)
1200 #error "HSI16 not enabled, required by STM32_SAI2SEL"
1201 #endif
1202
1203 #if (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) && \
1204 (STM32_PLLSAI1SRC == STM32_PLLSAI1SRC_HSI16)
1205 #error "HSI16 not enabled, required by STM32_PLLSAI1SRC"
1206 #endif
1207
1208 #if (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) && \
1209 (STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_HSI16)
1210 #error "HSI16 not enabled, required by STM32_PLLSAI2SRC"
1211 #endif
1212
1213 /* USART/UART-related checks.*/
1214 #if (STM32_USART1SEL == STM32_USART1SEL_HSI16)
1215 #error "HSI16 not enabled, required by STM32_USART1SEL"
1216 #endif
1217 #if (STM32_USART2SEL == STM32_USART2SEL_HSI16)
1218 #error "HSI16 not enabled, required by STM32_USART2SEL"
1219 #endif
1220 #if (STM32_USART3SEL == STM32_USART3SEL_HSI16)
1221 #error "HSI16 not enabled, required by STM32_USART3SEL"
1222 #endif
1223 #if (STM32_UART4SEL == STM32_UART4SEL_HSI16)
1224 #error "HSI16 not enabled, required by STM32_UART4SEL"
1225 #endif
1226 #if (STM32_UART5SEL == STM32_UART5SEL_HSI16)
1227 #error "HSI16 not enabled, required by STM32_UART5SEL"
1228 #endif
1229 #if (STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16)
1230 #error "HSI16 not enabled, required by STM32_LPUART1SEL"
1231 #endif
1232
1233 /* I2C-related checks.*/
1234 #if (STM32_I2C1SEL == STM32_I2C1SEL_HSI16)
1235 #error "HSI16 not enabled, required by I2C1SEL"
1236 #endif
1237 #if (STM32_I2C2SEL == STM32_I2C2SEL_HSI16)
1238 #error "HSI16 not enabled, required by I2C2SEL"
1239 #endif
1240 #if (STM32_I2C3SEL == STM32_I2C3SEL_HSI16)
1241 #error "HSI16 not enabled, required by I2C3SEL"
1242 #endif
1243 #if (STM32_I2C4SEL == STM32_I2C4SEL_HSI16)
1244 #error "HSI16 not enabled, required by I2C4SEL"
1245 #endif
1246
1247 /* LPTIM-related checks.*/
1248 #if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16)
1249 #error "HSI16 not enabled, required by LPTIM1SEL"
1250 #endif
1251 #if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16)
1252 #error "HSI16 not enabled, required by LPTIM2SEL"
1253 #endif
1254
1255 #if (STM32_STOPWUCK == STM32_STOPWUCK_HSI16)
1256 #error "HSI16 not enabled, required by STM32_STOPWUCK"
1257 #endif
1258
1259#endif /* !STM32_HSI16_ENABLED */
1260
1261#if STM32_HSI48_ENABLED
1262#else /* !STM32_HSI48_ENABLED */
1263
1264 #if STM32_MCOSEL == STM32_MCOSEL_HSI48
1265 #error "HSI48 not enabled, required by STM32_MCOSEL"
1266 #endif
1267
1268 #if STM32_CLK48SEL == STM32_CLK48SEL_HSI48
1269 #error "HSI48 not enabled, required by STM32_CLK48SEL"
1270 #endif
1271
1272#endif /* !STM32_HSI48_ENABLED */
1273
1274/*
1275 * HSE related checks.
1276 */
1277#if STM32_HSE_ENABLED
1278
1279 #if STM32_HSECLK == 0
1280 #error "HSE frequency not defined"
1281 #else /* STM32_HSECLK != 0 */
1282 #if defined(STM32_HSE_BYPASS)
1283 #if (STM32_HSECLK < STM32_HSECLK_BYP_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
1284 #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_BYP_MIN...STM32_HSECLK_BYP_MAX)"
1285 #endif
1286 #else /* !defined(STM32_HSE_BYPASS) */
1287 #if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
1288 #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
1289 #endif
1290 #endif /* !defined(STM32_HSE_BYPASS) */
1291 #endif /* STM32_HSECLK != 0 */
1292
1293#else /* !STM32_HSE_ENABLED */
1294
1295 #if STM32_SW == STM32_SW_HSE
1296 #error "HSE not enabled, required by STM32_SW"
1297 #endif
1298
1299 #if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
1300 #error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
1301 #endif
1302
1303 /* MCO-related checks.*/
1304 #if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
1305 ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
1306 (STM32_PLLSRC == STM32_PLLSRC_HSE))
1307 #error "HSE not enabled, required by STM32_MCOSEL"
1308 #endif
1309
1310 /* SAI1-related checks.*/
1311 #if (STM32_SAI1SEL == STM32_SAI1SEL_PLL) && \
1312 (STM32_PLLSRC == STM32_PLLSRC_HSE)
1313 #error "HSE not enabled, required by STM32_SAI1SEL"
1314 #endif
1315
1316 #if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) && \
1317 (STM32_PLLSAI1SRC == STM32_PLLSAI1SRC_HSE)
1318 #error "HSE not enabled, required by STM32_PLLSAI1SRC"
1319 #endif
1320
1321 #if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) && \
1322 (STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_HSE)
1323 #error "HSE not enabled, required by STM32_PLLSAI2SRC"
1324 #endif
1325
1326 /* SAI2-related checks.*/
1327 #if (STM32_SAI2SEL == STM32_SAI2SEL_PLL) && \
1328 (STM32_PLLSRC == STM32_PLLSRC_HSE)
1329 #error "HSE not enabled, required by STM32_SAI2SEL"
1330 #endif
1331
1332 #if (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) && \
1333 (STM32_PLLSAI1SRC == STM32_PLLSAI1SRC_HSE)
1334 #error "HSE not enabled, required by STM32_PLLSAI1SRC"
1335 #endif
1336
1337 #if (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) && \
1338 (STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_HSE)
1339 #error "HSE not enabled, required by STM32_PLLSAI2SRC"
1340 #endif
1341
1342 /* RTC-related checks.*/
1343 #if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
1344 #error "HSE not enabled, required by STM32_RTCSEL"
1345 #endif
1346
1347#endif /* !STM32_HSE_ENABLED */
1348
1349/*
1350 * LSI related checks.
1351 */
1352#if STM32_LSI_ENABLED
1353#else /* !STM32_LSI_ENABLED */
1354
1355 #if STM32_RTCSEL == STM32_RTCSEL_LSI
1356 #error "LSI not enabled, required by STM32_RTCSEL"
1357 #endif
1358
1359 #if STM32_MCOSEL == STM32_MCOSEL_LSI
1360 #error "LSI not enabled, required by STM32_MCOSEL"
1361 #endif
1362
1363 #if STM32_LSCOSEL == STM32_LSCOSEL_LSI
1364 #error "LSI not enabled, required by STM32_LSCOSEL"
1365 #endif
1366
1367#endif /* !STM32_LSI_ENABLED */
1368
1369/*
1370 * LSE related checks.
1371 */
1372#if STM32_LSE_ENABLED
1373
1374 #if (STM32_LSECLK == 0)
1375 #error "LSE frequency not defined"
1376 #endif
1377
1378 #if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
1379 #error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
1380 #endif
1381
1382#else /* !STM32_LSE_ENABLED */
1383
1384 #if STM32_RTCSEL == STM32_RTCSEL_LSE
1385 #error "LSE not enabled, required by STM32_RTCSEL"
1386 #endif
1387
1388 #if STM32_MCOSEL == STM32_MCOSEL_LSE
1389 #error "LSE not enabled, required by STM32_MCOSEL"
1390 #endif
1391
1392 #if STM32_LSCOSEL == STM32_LSCOSEL_LSE
1393 #error "LSE not enabled, required by STM32_LSCOSEL"
1394 #endif
1395
1396 #if STM32_MSIPLL_ENABLED == TRUE
1397 #error "LSE not enabled, required by STM32_MSIPLL_ENABLED"
1398 #endif
1399
1400#endif /* !STM32_LSE_ENABLED */
1401
1402/*
1403 * MSI related checks.
1404 */
1405#if (STM32_MSIRANGE == STM32_MSIRANGE_48M) && !STM32_MSIPLL_ENABLED
1406 #warning "STM32_MSIRANGE_48M should be used with STM32_MSIPLL_ENABLED"
1407#endif
1408
1409/**
1410 * @brief STM32_PLLM field.
1411 */
1412#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 16)) || \
1413 defined(__DOXYGEN__)
1414 #define STM32_PLLM ((STM32_PLLM_VALUE - 1) << 4)
1415#else
1416 #error "invalid STM32_PLLM_VALUE value specified"
1417#endif
1418
1419/**
1420 * @brief PLL input clock frequency.
1421 */
1422#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
1423 #define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
1424
1425#elif STM32_PLLSRC == STM32_PLLSRC_MSI
1426 #define STM32_PLLCLKIN (STM32_MSICLK / STM32_PLLM_VALUE)
1427
1428#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
1429 #define STM32_PLLCLKIN (STM32_HSI16CLK / STM32_PLLM_VALUE)
1430
1431#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
1432 #define STM32_PLLCLKIN 0
1433
1434#else
1435 #error "invalid STM32_PLLSRC value specified"
1436#endif
1437
1438/*
1439 * PLL input frequency range check.
1440 */
1441#if (STM32_PLLCLKIN != 0) && \
1442 ((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX))
1443 #error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
1444#endif
1445
1446/*
1447 * PLL enable check.
1448 */
1449#if (STM32_HSI48_ENABLED && (STM32_CLK48SEL == STM32_CLK48SEL_PLL)) || \
1450 (STM32_SW == STM32_SW_PLL) || \
1451 (STM32_MCOSEL == STM32_MCOSEL_PLL) || \
1452 (STM32_SAI1SEL == STM32_SAI1SEL_PLL) || \
1453 (STM32_SAI2SEL == STM32_SAI2SEL_PLL) || \
1454 defined(__DOXYGEN__)
1455
1456 #if STM32_PLLCLKIN == 0
1457 #error "PLL activation required but no PLL clock selected"
1458 #endif
1459
1460/**
1461 * @brief PLL activation flag.
1462 */
1463 #define STM32_ACTIVATE_PLL TRUE
1464#else
1465 #define STM32_ACTIVATE_PLL FALSE
1466#endif
1467
1468/**
1469 * @brief STM32_PLLN field.
1470 */
1471#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 127)) || \
1472 defined(__DOXYGEN__)
1473#define STM32_PLLN (STM32_PLLN_VALUE << 8)
1474#else
1475#error "invalid STM32_PLLN_VALUE value specified"
1476#endif
1477
1478/**
1479 * @brief STM32_PLLP field.
1480 */
1481#if (STM32_PLLP_VALUE == 7) || defined(__DOXYGEN__)
1482#define STM32_PLLP (0 << 17)
1483
1484#elif STM32_PLLP_VALUE == 17
1485#define STM32_PLLP (1 << 17)
1486
1487#else
1488#error "invalid STM32_PLLP_VALUE value specified"
1489#endif
1490
1491/**
1492 * @brief STM32_PLLQ field.
1493 */
1494#if (STM32_PLLQ_VALUE == 2) || defined(__DOXYGEN__)
1495#define STM32_PLLQ (0 << 21)
1496
1497#elif STM32_PLLQ_VALUE == 4
1498#define STM32_PLLQ (1 << 21)
1499
1500#elif STM32_PLLQ_VALUE == 6
1501#define STM32_PLLQ (2 << 21)
1502
1503#elif STM32_PLLQ_VALUE == 8
1504#define STM32_PLLQ (3 << 21)
1505
1506#else
1507#error "invalid STM32_PLLQ_VALUE value specified"
1508#endif
1509
1510/**
1511 * @brief STM32_PLLR field.
1512 */
1513#if (STM32_PLLR_VALUE == 2) || defined(__DOXYGEN__)
1514#define STM32_PLLR (0 << 25)
1515
1516#elif STM32_PLLR_VALUE == 4
1517#define STM32_PLLR (1 << 25)
1518
1519#elif STM32_PLLR_VALUE == 6
1520#define STM32_PLLR (2 << 25)
1521
1522#elif STM32_PLLR_VALUE == 8
1523#define STM32_PLLR (3 << 25)
1524
1525#else
1526#error "invalid STM32_PLLR_VALUE value specified"
1527#endif
1528
1529/**
1530 * @brief STM32_PLLPDIV field.
1531 */
1532#if (STM32_PLLPDIV_VALUE == 0) || \
1533 ((STM32_PLLPDIV_VALUE != 1) && (STM32_PLLPDIV_VALUE <= 31)) || \
1534 defined(__DOXYGEN__)
1535#define STM32_PLLPDIV (STM32_PLLPDIV_VALUE << 27)
1536#else
1537#error "invalid STM32_PLLPDIV_VALUE value specified"
1538#endif
1539
1540/**
1541 * @brief STM32_PLLPEN field.
1542 */
1543#if (STM32_SAI1SEL == STM32_SAI1SEL_PLL) || \
1544 (STM32_SAI2SEL == STM32_SAI2SEL_PLL) || \
1545 defined(__DOXYGEN__)
1546#define STM32_PLLPEN (1 << 16)
1547#else
1548#define STM32_PLLPEN (0 << 16)
1549#endif
1550
1551/**
1552 * @brief STM32_PLLQEN field.
1553 */
1554#if (STM32_CLK48SEL == STM32_CLK48SEL_PLL) || defined(__DOXYGEN__)
1555#define STM32_PLLQEN (1 << 20)
1556#else
1557#define STM32_PLLQEN (0 << 20)
1558#endif
1559
1560/**
1561 * @brief STM32_PLLREN field.
1562 */
1563#if (STM32_SW == STM32_SW_PLL) || \
1564 (STM32_MCOSEL == STM32_MCOSEL_PLL) || \
1565 defined(__DOXYGEN__)
1566#define STM32_PLLREN (1 << 24)
1567#else
1568#define STM32_PLLREN (0 << 24)
1569#endif
1570
1571/**
1572 * @brief PLL VCO frequency.
1573 */
1574#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
1575
1576/*
1577 * PLL VCO frequency range check.
1578 */
1579#if STM32_ACTIVATE_PLL && \
1580 ((STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX))
1581#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
1582#endif
1583
1584/**
1585 * @brief PLL P output clock frequency.
1586 */
1587#if (STM32_PLLPDIV_VALUE == 0) || defined(__DOXYGEN__)
1588#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
1589#else
1590#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLPDIV_VALUE)
1591#endif
1592
1593/**
1594 * @brief PLL Q output clock frequency.
1595 */
1596#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE)
1597
1598/**
1599 * @brief PLL R output clock frequency.
1600 */
1601#define STM32_PLL_R_CLKOUT (STM32_PLLVCO / STM32_PLLR_VALUE)
1602
1603/*
1604 * PLL-P output frequency range check.
1605 */
1606#if STM32_ACTIVATE_PLL && \
1607 ((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX))
1608#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
1609#endif
1610
1611/*
1612 * PLL-Q output frequency range check.
1613 */
1614#if STM32_ACTIVATE_PLL && \
1615 ((STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX))
1616#error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
1617#endif
1618
1619/*
1620 * PLL-R output frequency range check.
1621 */
1622#if STM32_ACTIVATE_PLL && \
1623 ((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX))
1624#error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
1625#endif
1626
1627/**
1628 * @brief System clock source.
1629 */
1630#if STM32_NO_INIT || defined(__DOXYGEN__)
1631#define STM32_SYSCLK STM32_MSICLK
1632
1633#elif (STM32_SW == STM32_SW_MSI)
1634#define STM32_SYSCLK STM32_MSICLK
1635
1636#elif (STM32_SW == STM32_SW_HSI16)
1637#define STM32_SYSCLK STM32_HSI16CLK
1638
1639#elif (STM32_SW == STM32_SW_HSE)
1640#define STM32_SYSCLK STM32_HSECLK
1641
1642#elif (STM32_SW == STM32_SW_PLL)
1643#define STM32_SYSCLK STM32_PLL_R_CLKOUT
1644
1645#else
1646#error "invalid STM32_SW value specified"
1647#endif
1648
1649/* Check on the system clock.*/
1650#if STM32_SYSCLK > STM32_SYSCLK_MAX
1651#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
1652#endif
1653
1654/**
1655 * @brief AHB frequency.
1656 */
1657#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
1658#define STM32_HCLK (STM32_SYSCLK / 1)
1659
1660#elif STM32_HPRE == STM32_HPRE_DIV2
1661#define STM32_HCLK (STM32_SYSCLK / 2)
1662
1663#elif STM32_HPRE == STM32_HPRE_DIV4
1664#define STM32_HCLK (STM32_SYSCLK / 4)
1665
1666#elif STM32_HPRE == STM32_HPRE_DIV8
1667#define STM32_HCLK (STM32_SYSCLK / 8)
1668
1669#elif STM32_HPRE == STM32_HPRE_DIV16
1670#define STM32_HCLK (STM32_SYSCLK / 16)
1671
1672#elif STM32_HPRE == STM32_HPRE_DIV64
1673#define STM32_HCLK (STM32_SYSCLK / 64)
1674
1675#elif STM32_HPRE == STM32_HPRE_DIV128
1676#define STM32_HCLK (STM32_SYSCLK / 128)
1677
1678#elif STM32_HPRE == STM32_HPRE_DIV256
1679#define STM32_HCLK (STM32_SYSCLK / 256)
1680
1681#elif STM32_HPRE == STM32_HPRE_DIV512
1682#define STM32_HCLK (STM32_SYSCLK / 512)
1683
1684#else
1685#error "invalid STM32_HPRE value specified"
1686#endif
1687
1688/*
1689 * AHB frequency check.
1690 */
1691#if STM32_HCLK > STM32_SYSCLK_MAX
1692#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
1693#endif
1694
1695/**
1696 * @brief APB1 frequency.
1697 */
1698#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
1699#define STM32_PCLK1 (STM32_HCLK / 1)
1700
1701#elif STM32_PPRE1 == STM32_PPRE1_DIV2
1702#define STM32_PCLK1 (STM32_HCLK / 2)
1703
1704#elif STM32_PPRE1 == STM32_PPRE1_DIV4
1705#define STM32_PCLK1 (STM32_HCLK / 4)
1706
1707#elif STM32_PPRE1 == STM32_PPRE1_DIV8
1708#define STM32_PCLK1 (STM32_HCLK / 8)
1709
1710#elif STM32_PPRE1 == STM32_PPRE1_DIV16
1711#define STM32_PCLK1 (STM32_HCLK / 16)
1712
1713#else
1714#error "invalid STM32_PPRE1 value specified"
1715#endif
1716
1717/*
1718 * APB1 frequency check.
1719 */
1720#if STM32_PCLK1 > STM32_PCLK1_MAX
1721#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
1722#endif
1723
1724/**
1725 * @brief APB2 frequency.
1726 */
1727#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
1728#define STM32_PCLK2 (STM32_HCLK / 1)
1729
1730#elif STM32_PPRE2 == STM32_PPRE2_DIV2
1731#define STM32_PCLK2 (STM32_HCLK / 2)
1732
1733#elif STM32_PPRE2 == STM32_PPRE2_DIV4
1734#define STM32_PCLK2 (STM32_HCLK / 4)
1735
1736#elif STM32_PPRE2 == STM32_PPRE2_DIV8
1737#define STM32_PCLK2 (STM32_HCLK / 8)
1738
1739#elif STM32_PPRE2 == STM32_PPRE2_DIV16
1740#define STM32_PCLK2 (STM32_HCLK / 16)
1741
1742#else
1743#error "invalid STM32_PPRE2 value specified"
1744#endif
1745
1746/*
1747 * APB2 frequency check.
1748 */
1749#if STM32_PCLK2 > STM32_PCLK2_MAX
1750#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
1751#endif
1752
1753/**
1754 * @brief STM32_PLLSAI1M field.
1755 */
1756#if ((STM32_PLLSAI1M_VALUE >= 1) && (STM32_PLLSAI1M_VALUE <= 16)) || \
1757 defined(__DOXYGEN__)
1758#define STM32_PLLSAI1M ((STM32_PLLSAI1M_VALUE - 1) << 4)
1759#else
1760#error "invalid STM32_PLLSAI1M_VALUE value specified"
1761#endif
1762
1763/**
1764 * @brief PLLSAI1 input clock frequency.
1765 */
1766#if (STM32_PLLSAI1SRC == STM32_PLLSAI1SRC_HSE) || defined(__DOXYGEN__)
1767#define STM32_PLLSAI1CLKIN (STM32_HSECLK / STM32_PLLSAI1M_VALUE)
1768
1769#elif STM32_PLLSAI1SRC == STM32_PLLSAI1SRC_MSI
1770#define STM32_PLLSAI1CLKIN (STM32_MSICLK / STM32_PLLSAI1M_VALUE)
1771
1772#elif STM32_PLLSAI1SRC == STM32_PLLSAI1SRC_HSI16
1773#define STM32_PLLSAI1CLKIN (STM32_HSI16CLK / STM32_PLLSAI1M_VALUE)
1774
1775#elif STM32_PLLSSAI1RC == STM32_PLLSAI1SRC_NOCLOCK
1776#define STM32_PLLSAI1CLKIN 0
1777
1778#else
1779#error "invalid STM32_PLLSAI1SRC value specified"
1780#endif
1781
1782/*
1783 * PLLSAI1 input frequency range check.
1784 */
1785#if (STM32_PLLSAI1CLKIN != 0) && \
1786 ((STM32_PLLSAI1CLKIN < STM32_PLLIN_MIN) || \
1787 (STM32_PLLSAI1CLKIN > STM32_PLLIN_MAX))
1788#error "STM32_PLLSAI1CLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
1789#endif
1790
1791/*
1792 * PLLSAI1 enable check.
1793 */
1794#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \
1795 (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || \
1796 (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || \
1797 (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \
1798 defined(__DOXYGEN__)
1799
1800#if STM32_PLLSAI1CLKIN == 0
1801#error "PLLSAI1 activation required but no PLL clock selected"
1802#endif
1803
1804/**
1805 * @brief PLLSAI1 activation flag.
1806 */
1807#define STM32_ACTIVATE_PLLSAI1 TRUE
1808#else
1809#define STM32_ACTIVATE_PLLSAI1 FALSE
1810#endif
1811
1812/**
1813 * @brief STM32_PLLSAI1N field.
1814 */
1815#if ((STM32_PLLSAI1N_VALUE >= 8) && (STM32_PLLSAI1N_VALUE <= 127)) || \
1816 defined(__DOXYGEN__)
1817#define STM32_PLLSAI1N (STM32_PLLSAI1N_VALUE << 8)
1818#else
1819#error "invalid STM32_PLLSAI1N_VALUE value specified"
1820#endif
1821
1822/**
1823 * @brief STM32_PLLSAI1P field.
1824 */
1825#if (STM32_PLLSAI1P_VALUE == 7) || defined(__DOXYGEN__)
1826#define STM32_PLLSAI1P (0 << 17)
1827
1828#elif STM32_PLLSAI1P_VALUE == 17
1829#define STM32_PLLSAI1P (1 << 17)
1830
1831#else
1832#error "invalid STM32_PLLSAI1P_VALUE value specified"
1833#endif
1834
1835/**
1836 * @brief STM32_PLLSAI1Q field.
1837 */
1838#if (STM32_PLLSAI1Q_VALUE == 2) || defined(__DOXYGEN__)
1839#define STM32_PLLSAI1Q (0 << 21)
1840
1841#elif STM32_PLLSAI1Q_VALUE == 4
1842#define STM32_PLLSAI1Q (1 << 21)
1843
1844#elif STM32_PLLSAI1Q_VALUE == 6
1845#define STM32_PLLSAI1Q (2 << 21)
1846
1847#elif STM32_PLLSAI1Q_VALUE == 8
1848#define STM32_PLLSAI1Q (3 << 21)
1849
1850#else
1851#error "invalid STM32_PLLSAI1Q_VALUE value specified"
1852#endif
1853
1854/**
1855 * @brief STM32_PLLSAI1R field.
1856 */
1857#if (STM32_PLLSAI1R_VALUE == 2) || defined(__DOXYGEN__)
1858#define STM32_PLLSAI1R (0 << 25)
1859
1860#elif STM32_PLLSAI1R_VALUE == 4
1861#define STM32_PLLSAI1R (1 << 25)
1862
1863#elif STM32_PLLSAI1R_VALUE == 6
1864#define STM32_PLLSAI1R (2 << 25)
1865
1866#elif STM32_PLLSAI1R_VALUE == 8
1867#define STM32_PLLSAI1R (3 << 25)
1868
1869#else
1870#error "invalid STM32_PLLSAI1R_VALUE value specified"
1871#endif
1872
1873/**
1874 * @brief STM32_PLLSAI1PDIV field.
1875 */
1876#if ((STM32_PLLSAI1PDIV_VALUE != 1) && (STM32_PLLSAI1PDIV_VALUE <= 31)) || \
1877 defined(__DOXYGEN__)
1878#define STM32_PLLSAI1PDIV (STM32_PLLSAI1PDIV_VALUE << 27)
1879#else
1880#error "invalid STM32_PLLSAI1PDIV_VALUE value specified"
1881#endif
1882
1883/**
1884 * @brief STM32_PLLSAI1PEN field.
1885 */
1886#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \
1887 (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || \
1888 defined(__DOXYGEN__)
1889#define STM32_PLLSAI1PEN (1 << 16)
1890#else
1891#define STM32_PLLSAI1PEN (0 << 16)
1892#endif
1893
1894/**
1895 * @brief STM32_PLLSAI1QEN field.
1896 */
1897#if (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || defined(__DOXYGEN__)
1898#define STM32_PLLSAI1QEN (1 << 20)
1899#else
1900#define STM32_PLLSAI1QEN (0 << 20)
1901#endif
1902
1903/**
1904 * @brief STM32_PLLSAI1REN field.
1905 */
1906#if (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || defined(__DOXYGEN__)
1907#define STM32_PLLSAI1REN (1 << 24)
1908#else
1909#define STM32_PLLSAI1REN (0 << 24)
1910#endif
1911
1912/**
1913 * @brief PLLSAI1 VCO frequency.
1914 */
1915#define STM32_PLLSAI1VCO (STM32_PLLSAI1CLKIN * STM32_PLLSAI1N_VALUE)
1916
1917/*
1918 * PLLSAI1 VCO frequency range check.
1919 */
1920#if STM32_ACTIVATE_PLLSAI1 && \
1921 ((STM32_PLLSAI1VCO < STM32_PLLVCO_MIN) || (STM32_PLLSAI1VCO > STM32_PLLVCO_MAX))
1922#error "STM32_PLLSAI1VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
1923#endif
1924
1925/**
1926 * @brief PLLSAI1-P output clock frequency.
1927 */
1928#if (STM32_PLLSAI1PDIV_VALUE == 0) || defined(__DOXYGEN__)
1929#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1P_VALUE)
1930#else
1931#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1PDIV_VALUE)
1932#endif
1933
1934/**
1935 * @brief PLLSAI1-Q output clock frequency.
1936 */
1937#define STM32_PLLSAI1_Q_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
1938
1939/**
1940 * @brief PLLSAI1-R output clock frequency.
1941 */
1942#define STM32_PLLSAI1_R_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1R_VALUE)
1943
1944/*
1945 * PLLSAI1-P output frequency range check.
1946 */
1947#if STM32_ACTIVATE_PLLSAI1 && \
1948 ((STM32_PLLSAI1_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI1_P_CLKOUT > STM32_PLLP_MAX))
1949#error "STM32_PLLSAI1_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
1950#endif
1951
1952/*
1953 * PLLSAI1-Q output frequency range check.
1954 */
1955#if STM32_ACTIVATE_PLLSAI1 && \
1956 ((STM32_PLLSAI1_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLLSAI1_Q_CLKOUT > STM32_PLLQ_MAX))
1957#error "STM32_PLLSAI1_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
1958#endif
1959
1960/*
1961 * PLLSAI1-R output frequency range check.
1962 */
1963#if STM32_ACTIVATE_PLLSAI1 && \
1964 ((STM32_PLLSAI1_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI1_R_CLKOUT > STM32_PLLR_MAX))
1965#error "STM32_PLLSAI1_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
1966#endif
1967
1968/**
1969 * @brief STM32_PLLSAI2M field.
1970 */
1971#if ((STM32_PLLSAI2M_VALUE >= 1) && (STM32_PLLSAI2M_VALUE <= 16)) || \
1972 defined(__DOXYGEN__)
1973#define STM32_PLLSAI2M ((STM32_PLLSAI2M_VALUE - 1) << 4)
1974#else
1975#error "invalid STM32_PLLSAI2M_VALUE value specified"
1976#endif
1977
1978/**
1979 * @brief PLLSAI2 input clock frequency.
1980 */
1981#if (STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_HSE) || defined(__DOXYGEN__)
1982#define STM32_PLLSAI2CLKIN (STM32_HSECLK / STM32_PLLSAI2M_VALUE)
1983
1984#elif STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_MSI
1985#define STM32_PLLSAI2CLKIN (STM32_MSICLK / STM32_PLLSAI2M_VALUE)
1986
1987#elif STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_HSI16
1988#define STM32_PLLSAI2CLKIN (STM32_HSI16CLK / STM32_PLLSAI2M_VALUE)
1989
1990#elif STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_NOCLOCK
1991#define STM32_PLLSAI2CLKIN 0
1992
1993#else
1994#error "invalid STM32_PLLSAI2SRC value specified"
1995#endif
1996
1997/*
1998 * PLLSAI2 input frequency range check.
1999 */
2000#if (STM32_PLLSAI2CLKIN != 0) && \
2001 ((STM32_PLLSAI2CLKIN < STM32_PLLIN_MIN) || \
2002 (STM32_PLLSAI2CLKIN > STM32_PLLIN_MAX))
2003#error "STM32_PLLSAI2CLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
2004#endif
2005
2006/*
2007 * PLLSAI2 enable check.
2008 */
2009#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) || \
2010 (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \
2011 (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \
2012 defined(__DOXYGEN__)
2013
2014#if STM32_PLLSAI2CLKIN == 0
2015#error "PLLSAI2 activation required but no PLL clock selected"
2016#endif
2017
2018/**
2019 * @brief PLLSAI2 activation flag.
2020 */
2021#define STM32_ACTIVATE_PLLSAI2 TRUE
2022#else
2023#define STM32_ACTIVATE_PLLSAI2 FALSE
2024#endif
2025
2026/**
2027 * @brief STM32_PLLSAI2N field.
2028 */
2029#if ((STM32_PLLSAI2N_VALUE >= 8) && (STM32_PLLSAI2N_VALUE <= 127)) || \
2030 defined(__DOXYGEN__)
2031#define STM32_PLLSAI2N (STM32_PLLSAI2N_VALUE << 8)
2032#else
2033#error "invalid STM32_PLLSAI2N_VALUE value specified"
2034#endif
2035
2036/**
2037 * @brief STM32_PLLSAI2P field.
2038 */
2039#if (STM32_PLLSAI2P_VALUE == 7) || defined(__DOXYGEN__)
2040#define STM32_PLLSAI2P (0 << 17)
2041
2042#elif STM32_PLLSAI2P_VALUE == 17
2043#define STM32_PLLSAI2P (1 << 17)
2044
2045#else
2046#error "invalid STM32_PLLSAI2P_VALUE value specified"
2047#endif
2048
2049/**
2050 * @brief STM32_PLLSAI2R field.
2051 */
2052#if (STM32_PLLSAI2R_VALUE == 2) || defined(__DOXYGEN__)
2053#define STM32_PLLSAI2R (0 << 25)
2054
2055#elif STM32_PLLSAI2R_VALUE == 4
2056#define STM32_PLLSAI2R (1 << 25)
2057
2058#elif STM32_PLLSAI2R_VALUE == 6
2059#define STM32_PLLSAI2R (2 << 25)
2060
2061#elif STM32_PLLSAI2R_VALUE == 8
2062#define STM32_PLLSAI2R (3 << 25)
2063
2064#else
2065#error "invalid STM32_PLLSAI2R_VALUE value specified"
2066#endif
2067
2068/**
2069 * @brief STM32_PLLSAI2PDIV field.
2070 */
2071#if ((STM32_PLLSAI2PDIV_VALUE != 1) && (STM32_PLLSAI2PDIV_VALUE <= 31)) || \
2072 defined(__DOXYGEN__)
2073#define STM32_PLLSAI2PDIV (STM32_PLLSAI2PDIV_VALUE << 27)
2074#else
2075#error "invalid STM32_PLLSAI2PDIV_VALUE value specified"
2076#endif
2077
2078/**
2079 * @brief STM32_PLLSAI2PEN field.
2080 */
2081#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) || \
2082 (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \
2083 defined(__DOXYGEN__)
2084#define STM32_PLLSAI2PEN (1 << 16)
2085#else
2086#define STM32_PLLSAI2PEN (0 << 16)
2087#endif
2088
2089/**
2090 * @brief STM32_PLLSAI2REN field.
2091 * @note Always enabled.
2092 * @note It should depend on some condition.
2093 */
2094#define STM32_PLLSAI2REN (1 << 24)
2095
2096/**
2097 * @brief PLLSAI2 VCO frequency.
2098 */
2099#define STM32_PLLSAI2VCO (STM32_PLLSAI2CLKIN * STM32_PLLSAI2N_VALUE)
2100
2101/*
2102 * PLLSAI2 VCO frequency range check.
2103 */
2104#if STM32_ACTIVATE_PLLSAI2 && \
2105 ((STM32_PLLSAI2VCO < STM32_PLLVCO_MIN) || (STM32_PLLSAI2VCO > STM32_PLLVCO_MAX))
2106#error "STM32_PLLSAI2VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
2107#endif
2108
2109/**
2110 * @brief PLLSAI2-P output clock frequency.
2111 */
2112#if (STM32_PLLSAI2PDIV_VALUE == 0) || defined(__DOXYGEN__)
2113#define STM32_PLLSAI2_P_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2P_VALUE)
2114#else
2115#define STM32_PLLSAI2_P_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2PDIV_VALUE)
2116#endif
2117
2118/**
2119 * @brief PLLSAI2-R output clock frequency.
2120 */
2121#define STM32_PLLSAI2_R_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2R_VALUE)
2122
2123/*
2124 * PLLSAI2-P output frequency range check.
2125 */
2126#if STM32_ACTIVATE_PLLSAI2 && \
2127 ((STM32_PLLSAI2_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI2_P_CLKOUT > STM32_PLLP_MAX))
2128#error "STM32_PLLSAI2_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
2129#endif
2130
2131/*
2132 * PLLSAI2-R output frequency range check.
2133 */
2134#if STM32_ACTIVATE_PLLSAI2 && \
2135 ((STM32_PLLSAI2_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI2_R_CLKOUT > STM32_PLLR_MAX))
2136#error "STM32_PLLSAI2_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
2137#endif
2138
2139/**
2140 * @brief MCO divider clock frequency.
2141 */
2142#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
2143#define STM32_MCODIVCLK 0
2144
2145#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
2146#define STM32_MCODIVCLK STM32_SYSCLK
2147
2148#elif STM32_MCOSEL == STM32_MCOSEL_MSI
2149#define STM32_MCODIVCLK STM32_MSICLK
2150
2151#elif STM32_MCOSEL == STM32_MCOSEL_HSI16
2152#define STM32_MCODIVCLK STM32_HSI16CLK
2153
2154#elif STM32_MCOSEL == STM32_MCOSEL_HSE
2155#define STM32_MCODIVCLK STM32_HSECLK
2156
2157#elif STM32_MCOSEL == STM32_MCOSEL_PLL
2158#define STM32_MCODIVCLK STM32_PLL_P_CLKOUT
2159
2160#elif STM32_MCOSEL == STM32_MCOSEL_LSI
2161#define STM32_MCODIVCLK STM32_LSICLK
2162
2163#elif STM32_MCOSEL == STM32_MCOSEL_LSE
2164#define STM32_MCODIVCLK STM32_LSECLK
2165
2166#elif STM32_MCOSEL == STM32_MCOSEL_HSI48
2167#define STM32_MCODIVCLK STM32_HSI48CLK
2168
2169#else
2170#error "invalid STM32_MCOSEL value specified"
2171#endif
2172
2173/**
2174 * @brief MCO output pin clock frequency.
2175 */
2176#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
2177#define STM32_MCOCLK STM32_MCODIVCLK
2178
2179#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
2180#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
2181
2182#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
2183#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
2184
2185#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
2186#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
2187
2188#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
2189#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
2190
2191#else
2192#error "invalid STM32_MCOPRE value specified"
2193#endif
2194
2195/**
2196 * @brief RTC clock frequency.
2197 */
2198#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
2199#define STM32_RTCCLK 0
2200
2201#elif STM32_RTCSEL == STM32_RTCSEL_LSE
2202#define STM32_RTCCLK STM32_LSECLK
2203
2204#elif STM32_RTCSEL == STM32_RTCSEL_LSI
2205#define STM32_RTCCLK STM32_LSICLK
2206
2207#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
2208#define STM32_RTCCLK (STM32_HSECLK / 32)
2209
2210#else
2211#error "invalid STM32_RTCSEL value specified"
2212#endif
2213
2214/**
2215 * @brief USART1 clock frequency.
2216 */
2217#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__)
2218#define STM32_USART1CLK STM32_PCLK2
2219
2220#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
2221#define STM32_USART1CLK STM32_SYSCLK
2222
2223#elif STM32_USART1SEL == STM32_USART1SEL_HSI16
2224#define STM32_USART1CLK STM32_HSI16CLK
2225
2226#elif STM32_USART1SEL == STM32_USART1SEL_LSE
2227#define STM32_USART1CLK STM32_LSECLK
2228
2229#else
2230#error "invalid source selected for USART1 clock"
2231#endif
2232
2233/**
2234 * @brief USART2 clock frequency.
2235 */
2236#if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__)
2237#define STM32_USART2CLK STM32_PCLK1
2238
2239#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
2240#define STM32_USART2CLK STM32_SYSCLK
2241
2242#elif STM32_USART2SEL == STM32_USART2SEL_HSI16
2243#define STM32_USART2CLK STM32_HSI16CLK
2244
2245#elif STM32_USART2SEL == STM32_USART2SEL_LSE
2246#define STM32_USART2CLK STM32_LSECLK
2247
2248#else
2249#error "invalid source selected for USART2 clock"
2250#endif
2251
2252/**
2253 * @brief USART3 clock frequency.
2254 */
2255#if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__)
2256#define STM32_USART3CLK STM32_PCLK1
2257
2258#elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK
2259#define STM32_USART3CLK STM32_SYSCLK
2260
2261#elif STM32_USART3SEL == STM32_USART3SEL_HSI16
2262#define STM32_USART3CLK STM32_HSI16CLK
2263
2264#elif STM32_USART3SEL == STM32_USART3SEL_LSE
2265#define STM32_USART3CLK STM32_LSECLK
2266
2267#else
2268#error "invalid source selected for USART3 clock"
2269#endif
2270
2271/**
2272 * @brief UART4 clock frequency.
2273 */
2274#if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__)
2275#define STM32_UART4CLK STM32_PCLK1
2276
2277#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK
2278#define STM32_UART4CLK STM32_SYSCLK
2279
2280#elif STM32_UART4SEL == STM32_UART4SEL_HSI16
2281#define STM32_UART4CLK STM32_HSI16CLK
2282
2283#elif STM32_UART4SEL == STM32_UART4SEL_LSE
2284#define STM32_UART4CLK STM32_LSECLK
2285
2286#else
2287#error "invalid source selected for UART4 clock"
2288#endif
2289
2290/**
2291 * @brief UART5 clock frequency.
2292 */
2293#if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__)
2294#define STM32_UART5CLK STM32_PCLK1
2295
2296#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK
2297#define STM32_UART5CLK STM32_SYSCLK
2298
2299#elif STM32_UART5SEL == STM32_UART5SEL_HSI16
2300#define STM32_UART5CLK STM32_HSI16CLK
2301
2302#elif STM32_UART5SEL == STM32_UART5SEL_LSE
2303#define STM32_UART5CLK STM32_LSECLK
2304
2305#else
2306#error "invalid source selected for UART5 clock"
2307#endif
2308
2309/**
2310 * @brief LPUART1 clock frequency.
2311 */
2312#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK1) || defined(__DOXYGEN__)
2313#define STM32_LPUART1CLK STM32_PCLK1
2314
2315#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
2316#define STM32_LPUART1CLK STM32_SYSCLK
2317
2318#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16
2319#define STM32_LPUART1CLK STM32_HSI16CLK
2320
2321#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE
2322#define STM32_LPUART1CLK STM32_LSECLK
2323
2324#else
2325#error "invalid source selected for LPUART1 clock"
2326#endif
2327
2328/**
2329 * @brief I2C1 clock frequency.
2330 */
2331#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__)
2332#define STM32_I2C1CLK STM32_PCLK1
2333
2334#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
2335#define STM32_I2C1CLK STM32_SYSCLK
2336
2337#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16
2338#define STM32_I2C1CLK STM32_HSI16CLK
2339
2340#else
2341#error "invalid source selected for I2C1 clock"
2342#endif
2343
2344/**
2345 * @brief I2C2 clock frequency.
2346 */
2347#if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK1) || defined(__DOXYGEN__)
2348#define STM32_I2C2CLK STM32_PCLK1
2349
2350#elif STM32_I2C2SEL == STM32_I2C2SEL_SYSCLK
2351#define STM32_I2C2CLK STM32_SYSCLK
2352
2353#elif STM32_I2C2SEL == STM32_I2C2SEL_HSI16
2354#define STM32_I2C2CLK STM32_HSI16CLK
2355
2356#else
2357#error "invalid source selected for I2C2 clock"
2358#endif
2359
2360/**
2361 * @brief I2C3 clock frequency.
2362 */
2363#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__)
2364#define STM32_I2C3CLK STM32_PCLK1
2365
2366#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK
2367#define STM32_I2C3CLK STM32_SYSCLK
2368
2369#elif STM32_I2C3SEL == STM32_I2C3SEL_HSI16
2370#define STM32_I2C3CLK STM32_HSI16CLK
2371
2372#else
2373#error "invalid source selected for I2C3 clock"
2374#endif
2375
2376/**
2377 * @brief I2C4 clock frequency.
2378 */
2379#if (STM32_I2C4SEL == STM32_I2C4SEL_PCLK1) || defined(__DOXYGEN__)
2380#define STM32_I2C4CLK STM32_PCLK1
2381
2382#elif STM32_I2C4SEL == STM32_I2C4SEL_SYSCLK
2383#define STM32_I2C4CLK STM32_SYSCLK
2384
2385#elif STM32_I2C4SEL == STM32_I2C4SEL_HSI16
2386#define STM32_I2C4CLK STM32_HSI16CLK
2387
2388#else
2389#error "invalid source selected for I2C4 clock"
2390#endif
2391
2392/**
2393 * @brief LPTIM1 clock frequency.
2394 */
2395#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__)
2396#define STM32_LPTIM1CLK STM32_PCLK1
2397
2398#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
2399#define STM32_LPTIM1CLK STM32_LSICLK
2400
2401#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16
2402#define STM32_LPTIM1CLK STM32_HSI16CLK
2403
2404#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
2405#define STM32_LPTIM1CLK STM32_LSECLK
2406
2407#else
2408#error "invalid source selected for LPTIM1 clock"
2409#endif
2410
2411/**
2412 * @brief LPTIM2 clock frequency.
2413 */
2414#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK1) || defined(__DOXYGEN__)
2415#define STM32_LPTIM2CLK STM32_PCLK1
2416
2417#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSI
2418#define STM32_LPTIM2CLK STM32_LSICLK
2419
2420#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16
2421#define STM32_LPTIM2CLK STM32_HSI16CLK
2422
2423#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSE
2424#define STM32_LPTIM2CLK STM32_LSECLK
2425
2426#else
2427#error "invalid source selected for LPTIM2 clock"
2428#endif
2429
2430/**
2431 * @brief LPTIM3 clock frequency.
2432 */
2433#if (STM32_LPTIM3SEL == STM32_LPTIM3SEL_PCLK1) || defined(__DOXYGEN__)
2434#define STM32_LPTIM3CLK STM32_PCLK1
2435
2436#elif STM32_LPTIM3SEL == STM32_LPTIM3SEL_LSI
2437#define STM32_LPTIM3CLK STM32_LSICLK
2438
2439#elif STM32_LPTIM3SEL == STM32_LPTIM3SEL_HSI16
2440#define STM32_LPTIM3CLK STM32_HSI16CLK
2441
2442#elif STM32_LPTIM3SEL == STM32_LPTIM3SEL_LSE
2443#define STM32_LPTIM3CLK STM32_LSECLK
2444
2445#else
2446#error "invalid source selected for LPTIM3 clock"
2447#endif
2448
2449/**
2450 * @brief 48MHz clock frequency.
2451 */
2452#if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__)
2453#define STM32_48CLK STM32_HSI48CLK
2454
2455#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1
2456#define STM32_48CLK (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
2457
2458#elif STM32_CLK48SEL == STM32_CLK48SEL_PLL
2459#define STM32_48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
2460
2461#elif STM32_CLK48SEL == STM32_CLK48SEL_MSI
2462#define STM32_48CLK STM32_MSICLK
2463
2464#else
2465#error "invalid source selected for 48CLK clock"
2466#endif
2467
2468/**
2469 * @brief SAI1 clock frequency.
2470 */
2471#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || defined(__DOXYGEN__)
2472#define STM32_SAI1CLK STM32_PLLSAI1_P_CLKOUT
2473
2474#elif STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2
2475#define STM32_SAI1CLK STM32_PLLSAI2_P_CLKOUT
2476
2477#elif STM32_SAI1SEL == STM32_SAI1SEL_PLL
2478#define STM32_SAI1CLK STM32_PLL_P_CLKOUT
2479
2480#elif STM32_SAI1SEL == STM32_SAI1SEL_EXTCLK
2481#define STM32_SAI1CLK 0 /* Unknown, would require a board value */
2482
2483#elif STM32_SAI1SEL == STM32_SAI1SEL_HSI16
2484#define STM32_SAI1CLK STM32_HSI16CLK
2485
2486#elif STM32_SAI1SEL == STM32_SAI1SEL_OFF
2487#define STM32_SAI1CLK 0
2488
2489#else
2490#error "invalid source selected for SAI1 clock"
2491#endif
2492
2493/**
2494 * @brief SAI2 clock frequency.
2495 */
2496#if (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || defined(__DOXYGEN__)
2497#define STM32_SAI2CLK STM32_PLLSAI1_P_CLKOUT
2498
2499#elif STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2
2500#define STM32_SAI2CLK STM32_PLLSAI2_P_CLKOUT
2501
2502#elif STM32_SAI2SEL == STM32_SAI2SEL_PLL
2503#define STM32_SAI2CLK STM32_PLL_P_CLKOUT
2504
2505#elif STM32_SAI2SEL == STM32_SAI2SEL_EXTCLK
2506#define STM32_SAI2CLK 0 /* Unknown, would require a board value */
2507
2508#elif STM32_SAI2SEL == STM32_SAI2SEL_HSI16
2509#define STM32_SAI2CLK STM32_HSI16CLK
2510
2511#elif STM32_SAI2SEL == STM32_SAI2SEL_OFF
2512#define STM32_SAI2CLK 0
2513
2514#else
2515#error "invalid source selected for SAI2 clock"
2516#endif
2517
2518/**
2519 * @brief SDMMC clock frequency.
2520 */
2521#if (STM32_SDMMCSEL == STM32_SDMMCSEL_48CLK) || defined(__DOXYGEN__)
2522#define STM32_SDMMCCLK STM32_48CLK
2523
2524#elif STM32_SDMMCSEL == STM32_SDMMCSEL_PLLSAI3CLK
2525#define STM32_SDMMCCLK STM32_PLL_P_CLKOUT
2526
2527#else
2528#error "invalid source selected for SDMMC clock"
2529#endif
2530
2531/**
2532 * @brief USB clock point.
2533 */
2534#define STM32_USBCLK STM32_48CLK
2535
2536/**
2537 * @brief RNG clock point.
2538 */
2539#define STM32_RNGCLK STM32_48CLK
2540
2541/**
2542 * @brief ADC clock frequency.
2543 */
2544#if (STM32_ADCSEL == STM32_ADCSEL_NOCLK) || defined(__DOXYGEN__)
2545#define STM32_ADCCLK 0
2546
2547#elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI1
2548#define STM32_ADCCLK STM32_PLLSAI1_R_CLKOUT
2549
2550#elif STM32_ADCSEL == STM32_ADCSEL_SYSCLK
2551#define STM32_ADCCLK STM32_SYSCLK
2552
2553#else
2554#error "invalid source selected for ADC clock"
2555#endif
2556
2557/**
2558 * @brief DFSDM clock frequency.
2559 */
2560#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK2) || defined(__DOXYGEN__)
2561#define STM32_DFSDMCLK STM32_PCLK2
2562
2563#elif STM32_DFSDMSEL == STM32_DFSDMSEL_SYSCLK
2564#define STM32_DFSDMCLK STM32_SYSCLK
2565
2566#else
2567#error "invalid source selected for DFSDM clock"
2568#endif
2569
2570/**
2571 * @brief SDMMC frequency.
2572 */
2573#define STM32_SDMMC1CLK STM32_48CLK
2574
2575/**
2576 * @brief OSPI clock frequency.
2577 */
2578#if (STM32_OSPISEL == STM32_OSPISEL_SYSCLK) || defined(__DOXYGEN__)
2579#define STM32_OSPICLK STM32_SYSCLK
2580
2581#elif STM32_OSPISEL == STM32_OSPISEL_MSI
2582#define STM32_OSPICLK STM32_MSICLK
2583
2584#elif STM32_OSPISEL == STM32_OSPISEL_48CLK
2585#define STM32_OSPICLK STM32_PLLSAI1_Q_CLKOUT
2586
2587#else
2588#error "invalid source selected for OSPI clock"
2589#endif
2590
2591/**
2592 * @brief Clock of timers connected to APB1
2593 */
2594#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
2595#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
2596#else
2597#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
2598#endif
2599
2600/**
2601 * @brief Clock of timers connected to APB2.
2602 */
2603#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
2604#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
2605#else
2606#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
2607#endif
2608
2609/**
2610 * @brief Flash settings.
2611 */
2612#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
2613#define STM32_FLASHBITS FLASH_ACR_LATENCY_0WS
2614
2615#elif STM32_HCLK <= STM32_1WS_THRESHOLD
2616#define STM32_FLASHBITS FLASH_ACR_LATENCY_1WS
2617
2618#elif STM32_HCLK <= STM32_2WS_THRESHOLD
2619#define STM32_FLASHBITS FLASH_ACR_LATENCY_2WS
2620
2621#elif STM32_HCLK <= STM32_3WS_THRESHOLD
2622#define STM32_FLASHBITS FLASH_ACR_LATENCY_3WS
2623
2624#else
2625#define STM32_FLASHBITS FLASH_ACR_LATENCY_4WS
2626#endif
2627
2628/**
2629 * @brief Flash settings for MSI.
2630 */
2631#if (STM32_MSICLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
2632#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_0WS
2633
2634#elif STM32_MSICLK <= STM32_1WS_THRESHOLD
2635#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_1WS
2636
2637#elif STM32_MSICLK <= STM32_2WS_THRESHOLD
2638#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_2WS
2639
2640#elif STM32_MSICLK <= STM32_3WS_THRESHOLD
2641#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_3WS
2642
2643#else
2644#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_4WS
2645#endif
2646
2647/*===========================================================================*/
2648/* Driver data structures and types. */
2649/*===========================================================================*/
2650
2651/*===========================================================================*/
2652/* Driver macros. */
2653/*===========================================================================*/
2654
2655/*===========================================================================*/
2656/* External declarations. */
2657/*===========================================================================*/
2658
2659/* Various helpers.*/
2660#include "nvic.h"
2661#include "cache.h"
2662#include "mpu_v7m.h"
2663#include "stm32_isr.h"
2664#include "stm32_dma.h"
2665#include "stm32_exti.h"
2666#include "stm32_rcc.h"
2667#include "stm32_tim.h"
2668
2669#ifdef __cplusplus
2670extern "C" {
2671#endif
2672 void hal_lld_init(void);
2673 void stm32_clock_init(void);
2674#ifdef __cplusplus
2675}
2676#endif
2677
2678#endif /* HAL_LLD_H */
2679
2680/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 13:59:02 +0100