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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32L5xx/stm32_rcc.h
19 * @brief RCC helper driver header.
20 * @note This file requires definitions from the ST header file
21 * @p stm32l5xx.h.
22 *
23 * @addtogroup STM32L5xx_RCC
24 * @{
25 */
26#ifndef STM32_RCC_H
27#define STM32_RCC_H
28
29/*===========================================================================*/
30/* Driver constants. */
31/*===========================================================================*/
32
33/*===========================================================================*/
34/* Driver pre-compile time settings. */
35/*===========================================================================*/
36
37/*===========================================================================*/
38/* Derived constants and error checks. */
39/*===========================================================================*/
40
41/*===========================================================================*/
42/* Driver data structures and types. */
43/*===========================================================================*/
44
45/*===========================================================================*/
46/* Driver macros. */
47/*===========================================================================*/
48
49/**
50 * @name Generic RCC operations
51 * @{
52 */
53/**
54 * @brief Enables the clock of one or more peripheral on the APB1 bus (R1).
55 *
56 * @param[in] mask APB1 R1 peripherals mask
57 * @param[in] lp low power enable flag
58 *
59 * @api
60 */
61#define rccEnableAPB1R1(mask, lp) { \
62 RCC->APB1ENR1 |= (mask); \
63 if (lp) \
64 RCC->APB1SMENR1 |= (mask); \
65 else \
66 RCC->APB1SMENR1 &= ~(mask); \
67 (void)RCC->APB1SMENR1; \
68}
69
70/**
71 * @brief Disables the clock of one or more peripheral on the APB1 bus (R1).
72 *
73 * @param[in] mask APB1 R1 peripherals mask
74 *
75 * @api
76 */
77#define rccDisableAPB1R1(mask) { \
78 RCC->APB1ENR1 &= ~(mask); \
79 RCC->APB1SMENR1 &= ~(mask); \
80 (void)RCC->APB1SMENR1; \
81}
82
83/**
84 * @brief Resets one or more peripheral on the APB1 bus (R1).
85 *
86 * @param[in] mask APB1 R1 peripherals mask
87 *
88 * @api
89 */
90#define rccResetAPB1R1(mask) { \
91 RCC->APB1RSTR1 |= (mask); \
92 RCC->APB1RSTR1 &= ~(mask); \
93 (void)RCC->APB1RSTR1; \
94}
95
96/**
97 * @brief Enables the clock of one or more peripheral on the APB1 bus (R2).
98 *
99 * @param[in] mask APB1 R2 peripherals mask
100 * @param[in] lp low power enable flag
101 *
102 * @api
103 */
104#define rccEnableAPB1R2(mask, lp) { \
105 RCC->APB1ENR2 |= (mask); \
106 if (lp) \
107 RCC->APB1SMENR2 |= (mask); \
108 else \
109 RCC->APB1SMENR2 &= ~(mask); \
110 (void)RCC->APB1SMENR2; \
111}
112
113/**
114 * @brief Disables the clock of one or more peripheral on the APB1 bus (R2).
115 *
116 * @param[in] mask APB1 R2 peripherals mask
117 *
118 * @api
119 */
120#define rccDisableAPB1R2(mask) { \
121 RCC->APB1ENR2 &= ~(mask); \
122 RCC->APB1SMENR2 &= ~(mask); \
123 (void)RCC->APB1SMENR2; \
124}
125
126/**
127 * @brief Resets one or more peripheral on the APB1 bus (R2).
128 *
129 * @param[in] mask APB1 R2 peripherals mask
130 *
131 * @api
132 */
133#define rccResetAPB1R2(mask) { \
134 RCC->APB1RSTR2 |= (mask); \
135 RCC->APB1RSTR2 &= ~(mask); \
136 (void)RCC->APB1RSTR2; \
137}
138
139/**
140 * @brief Enables the clock of one or more peripheral on the APB2 bus.
141 *
142 * @param[in] mask APB2 peripherals mask
143 * @param[in] lp low power enable flag
144 *
145 * @api
146 */
147#define rccEnableAPB2(mask, lp) { \
148 RCC->APB2ENR |= (mask); \
149 if (lp) \
150 RCC->APB2SMENR |= (mask); \
151 else \
152 RCC->APB2SMENR &= ~(mask); \
153 (void)RCC->APB2SMENR; \
154}
155
156/**
157 * @brief Disables the clock of one or more peripheral on the APB2 bus.
158 *
159 * @param[in] mask APB2 peripherals mask
160 *
161 * @api
162 */
163#define rccDisableAPB2(mask) { \
164 RCC->APB2ENR &= ~(mask); \
165 RCC->APB2SMENR &= ~(mask); \
166 (void)RCC->APB2SMENR; \
167}
168
169/**
170 * @brief Resets one or more peripheral on the APB2 bus.
171 *
172 * @param[in] mask APB2 peripherals mask
173 *
174 * @api
175 */
176#define rccResetAPB2(mask) { \
177 RCC->APB2RSTR |= (mask); \
178 RCC->APB2RSTR &= ~(mask); \
179 (void)RCC->APB2RSTR; \
180}
181
182/**
183 * @brief Enables the clock of one or more peripheral on the AHB1 bus.
184 *
185 * @param[in] mask AHB1 peripherals mask
186 * @param[in] lp low power enable flag
187 *
188 * @api
189 */
190#define rccEnableAHB1(mask, lp) { \
191 RCC->AHB1ENR |= (mask); \
192 if (lp) \
193 RCC->AHB1SMENR |= (mask); \
194 else \
195 RCC->AHB1SMENR &= ~(mask); \
196 (void)RCC->AHB1SMENR; \
197}
198
199/**
200 * @brief Disables the clock of one or more peripheral on the AHB1 bus.
201 *
202 * @param[in] mask AHB1 peripherals mask
203 *
204 * @api
205 */
206#define rccDisableAHB1(mask) { \
207 RCC->AHB1ENR &= ~(mask); \
208 RCC->AHB1SMENR &= ~(mask); \
209 (void)RCC->AHB1SMENR; \
210}
211
212/**
213 * @brief Resets one or more peripheral on the AHB1 bus.
214 *
215 * @param[in] mask AHB1 peripherals mask
216 *
217 * @api
218 */
219#define rccResetAHB1(mask) { \
220 RCC->AHB1RSTR |= (mask); \
221 RCC->AHB1RSTR &= ~(mask); \
222 (void)RCC->AHB1RSTR; \
223}
224
225/**
226 * @brief Enables the clock of one or more peripheral on the AHB2 bus.
227 *
228 * @param[in] mask AHB2 peripherals mask
229 * @param[in] lp low power enable flag
230 *
231 * @api
232 */
233#define rccEnableAHB2(mask, lp) { \
234 RCC->AHB2ENR |= (mask); \
235 if (lp) \
236 RCC->AHB2SMENR |= (mask); \
237 else \
238 RCC->AHB2SMENR &= ~(mask); \
239 (void)RCC->AHB2SMENR; \
240}
241
242/**
243 * @brief Disables the clock of one or more peripheral on the AHB2 bus.
244 *
245 * @param[in] mask AHB2 peripherals mask
246 *
247 * @api
248 */
249#define rccDisableAHB2(mask) { \
250 RCC->AHB2ENR &= ~(mask); \
251 RCC->AHB2SMENR &= ~(mask); \
252 (void)RCC->AHB2SMENR; \
253}
254
255/**
256 * @brief Resets one or more peripheral on the AHB2 bus.
257 *
258 * @param[in] mask AHB2 peripherals mask
259 *
260 * @api
261 */
262#define rccResetAHB2(mask) { \
263 RCC->AHB2RSTR |= (mask); \
264 RCC->AHB2RSTR &= ~(mask); \
265 (void)RCC->AHB2RSTR; \
266}
267
268/**
269 * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.
270 *
271 * @param[in] mask AHB3 peripherals mask
272 * @param[in] lp low power enable flag
273 *
274 * @api
275 */
276#define rccEnableAHB3(mask, lp) { \
277 RCC->AHB3ENR |= (mask); \
278 if (lp) \
279 RCC->AHB3SMENR |= (mask); \
280 else \
281 RCC->AHB3SMENR &= ~(mask); \
282 (void)RCC->AHB3SMENR; \
283}
284
285/**
286 * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.
287 *
288 * @param[in] mask AHB3 peripherals mask
289 *
290 * @api
291 */
292#define rccDisableAHB3(mask) { \
293 RCC->AHB3ENR &= ~(mask); \
294 RCC->AHB3SMENR &= ~(mask); \
295 (void)RCC->AHB3SMENR; \
296}
297
298/**
299 * @brief Resets one or more peripheral on the AHB3 (FSMC) bus.
300 *
301 * @param[in] mask AHB3 peripherals mask
302 *
303 * @api
304 */
305#define rccResetAHB3(mask) { \
306 RCC->AHB3RSTR |= (mask); \
307 RCC->AHB3RSTR &= ~(mask); \
308 (void)RCC->AHB3RSTR; \
309}
310/** @} */
311
312/**
313 * @name ADC peripherals specific RCC operations
314 * @{
315 */
316/**
317 * @brief Enables the ADC1/ADC2 peripheral clock.
318 *
319 * @param[in] lp low power enable flag
320 *
321 * @api
322 */
323#define rccEnableADC12(lp) rccEnableAHB2(RCC_AHB2ENR_ADCEN, lp)
324
325/**
326 * @brief Disables the ADC1/ADC2 peripheral clock.
327 *
328 * @api
329 */
330#define rccDisableADC12() rccDisableAHB2(RCC_AHB2ENR_ADCEN)
331
332/**
333 * @brief Resets the ADC1/ADC2 peripheral.
334 *
335 * @api
336 */
337#define rccResetADC12() rccResetAHB2(RCC_AHB2RSTR_ADCRST)
338/** @} */
339
340/**
341 * @name DAC peripheral specific RCC operations
342 * @{
343 */
344/**
345 * @brief Enables the DAC1 peripheral clock.
346 *
347 * @param[in] lp low power enable flag
348 *
349 * @api
350 */
351#define rccEnableDAC1(lp) rccEnableAPB1R1(RCC_APB1ENR1_DAC1EN, lp)
352
353/**
354 * @brief Disables the DAC1 peripheral clock.
355 *
356 * @api
357 */
358#define rccDisableDAC1() rccDisableAPB1R1(RCC_APB1ENR1_DAC1EN)
359
360/**
361 * @brief Resets the DAC1 peripheral.
362 *
363 * @api
364 */
365#define rccResetDAC1() rccResetAPB1R1(RCC_APB1RSTR1_DAC1RST)
366/** @} */
367
368/**
369 * @name DMA peripheral specific RCC operations
370 * @{
371 */
372/**
373 * @brief Enables the DMA1 peripheral clock.
374 *
375 * @param[in] lp low power enable flag
376 *
377 * @api
378 */
379#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
380
381/**
382 * @brief Disables the DMA1 peripheral clock.
383 *
384 * @api
385 */
386#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN)
387
388/**
389 * @brief Resets the DMA1 peripheral.
390 *
391 * @api
392 */
393#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
394
395/**
396 * @brief Enables the DMA2 peripheral clock.
397 *
398 * @param[in] lp low power enable flag
399 *
400 * @api
401 */
402#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
403
404/**
405 * @brief Disables the DMA2 peripheral clock.
406 *
407 * @api
408 */
409#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN)
410
411/**
412 * @brief Resets the DMA2 peripheral.
413 *
414 * @api
415 */
416#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
417/** @} */
418
419/**
420 * @name DMAMUX peripheral specific RCC operations
421 * @{
422 */
423/**
424 * @brief Enables the DMAMUX peripheral clock.
425 *
426 * @param[in] lp low power enable flag
427 *
428 * @api
429 */
430#define rccEnableDMAMUX(lp) rccEnableAHB1(RCC_AHB1ENR_DMAMUX1EN, lp)
431
432/**
433 * @brief Disables the DMAMUX peripheral clock.
434 *
435 * @api
436 */
437#define rccDisableDMAMUX() rccDisableAHB1(RCC_AHB1ENR_DMAMUX1EN)
438
439/**
440 * @brief Resets the DMAMUX peripheral.
441 *
442 * @api
443 */
444#define rccResetDMAMUX() rccResetAHB1(RCC_AHB1RSTR_DMAMUX1RST)
445/** @} */
446
447/**
448 * @name PWR interface specific RCC operations
449 * @{
450 */
451/**
452 * @brief Enables the PWR interface clock.
453 *
454 * @param[in] lp low power enable flag
455 *
456 * @api
457 */
458#define rccEnablePWRInterface(lp) rccEnableAPB1R1(RCC_APB1ENR1_PWREN, lp)
459
460/**
461 * @brief Disables PWR interface clock.
462 *
463 * @api
464 */
465#define rccDisablePWRInterface() rccDisableAPB1R1(RCC_APB1ENR1_PWREN)
466
467/**
468 * @brief Resets the PWR interface.
469 *
470 * @api
471 */
472#define rccResetPWRInterface() rccResetAPB1R1(RCC_APB1RSTR1_PWRRST)
473/** @} */
474
475/**
476 * @name FDCAN peripherals specific RCC operations
477 * @{
478 */
479/**
480 * @brief Enables the FDCAN1 peripheral clock.
481 *
482 * @param[in] lp low power enable flag
483 *
484 * @api
485 */
486#define rccEnableFDCAN1(lp) rccEnableAPB1R2(RCC_APB1ENR2_FDCAN1EN, lp)
487
488/**
489 * @brief Disables the FDCAN1 peripheral clock.
490 *
491 * @api
492 */
493#define rccDisableFDCAN1() rccDisableAPB1R2(RCC_APB1ENR2_FDCAN1EN)
494
495/**
496 * @brief Resets the FDCAN1 peripheral.
497 *
498 * @api
499 */
500#define rccResetFDCAN1() rccResetAPB1R2(RCC_APB1RSTR2_FDCAN1RST)
501
502/**
503 * @name I2C peripherals specific RCC operations
504 * @{
505 */
506/**
507 * @brief Enables the I2C1 peripheral clock.
508 *
509 * @param[in] lp low power enable flag
510 *
511 * @api
512 */
513#define rccEnableI2C1(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C1EN, lp)
514
515/**
516 * @brief Disables the I2C1 peripheral clock.
517 *
518 * @api
519 */
520#define rccDisableI2C1() rccDisableAPB1R1(RCC_APB1ENR1_I2C1EN)
521
522/**
523 * @brief Resets the I2C1 peripheral.
524 *
525 * @api
526 */
527#define rccResetI2C1() rccResetAPB1R1(RCC_APB1RSTR1_I2C1RST)
528
529/**
530 * @brief Enables the I2C2 peripheral clock.
531 *
532 * @param[in] lp low power enable flag
533 *
534 * @api
535 */
536#define rccEnableI2C2(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C2EN, lp)
537
538/**
539 * @brief Disables the I2C2 peripheral clock.
540 *
541 * @api
542 */
543#define rccDisableI2C2() rccDisableAPB1R1(RCC_APB1ENR1_I2C2EN)
544
545/**
546 * @brief Resets the I2C2 peripheral.
547 *
548 * @api
549 */
550#define rccResetI2C2() rccResetAPB1R1(RCC_APB1RSTR1_I2C2RST)
551
552/**
553 * @brief Enables the I2C3 peripheral clock.
554 *
555 * @param[in] lp low power enable flag
556 *
557 * @api
558 */
559#define rccEnableI2C3(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C3EN, lp)
560
561/**
562 * @brief Disables the I2C3 peripheral clock.
563 *
564 * @api
565 */
566#define rccDisableI2C3() rccDisableAPB1R1(RCC_APB1ENR1_I2C3EN)
567
568/**
569 * @brief Resets the I2C3 peripheral.
570 *
571 * @api
572 */
573#define rccResetI2C3() rccResetAPB1R1(RCC_APB1RSTR1_I2C3RST)
574
575/**
576 * @brief Enables the I2C4 peripheral clock.
577 *
578 * @param[in] lp low power enable flag
579 *
580 * @api
581 */
582#define rccEnableI2C4(lp) rccEnableAPB1R2(RCC_APB1ENR2_I2C4EN, lp)
583
584/**
585 * @brief Disables the I2C4 peripheral clock.
586 *
587 * @api
588 */
589#define rccDisableI2C4() rccDisableAPB1R1(RCC_APB1ENR2_I2C4EN)
590
591/**
592 * @brief Resets the I2C4 peripheral.
593 *
594 * @api
595 */
596#define rccResetI2C4() rccResetAPB1R1(RCC_APB1RSTR2_I2C4RST)
597/** @} */
598
599/**
600 * @name OCTOSPI peripherals specific RCC operations
601 * @{
602 */
603/**
604 * @brief Enables the OCTOSPI1 peripheral clock.
605 *
606 * @param[in] lp low power enable flag
607 *
608 * @api
609 */
610#define rccEnableOCTOSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_OSPI1EN, lp)
611
612/**
613 * @brief Disables the OCTOSPI1 peripheral clock.
614 *
615 * @api
616 */
617#define rccDisableOCTOSPI1() rccDisableAHB3(RCC_AHB3ENR_OSPI1EN)
618
619/**
620 * @brief Resets the OCTOSPI1 peripheral.
621 *
622 * @api
623 */
624#define rccResetOCTOSPI1() rccResetAHB3(RCC_AHB3RSTR_OSPI1RST)
625
626/**
627 * @name RNG peripherals specific RCC operations
628 * @{
629 */
630/**
631 * @brief Enables the RNG peripheral clock.
632 *
633 * @param[in] lp low power enable flag
634 *
635 * @api
636 */
637#define rccEnableRNG(lp) rccEnableAHB2(RCC_AHB2ENR_RNGEN, lp)
638
639/**
640 * @brief Disables the RNG peripheral clock.
641 *
642 * @api
643 */
644#define rccDisableRNG() rccDisableAHB2(RCC_AHB2ENR_RNGEN)
645
646/**
647 * @brief Resets the RNG peripheral.
648 *
649 * @api
650 */
651#define rccResetRNG() rccResetAHB2(RCC_AHB2RSTR_RNGRST)
652/** @} */
653
654/**
655 * @name SDMMC peripheral specific RCC operations
656 * @{
657 */
658/**
659 * @brief Enables the SDMMC1 peripheral clock.
660 *
661 * @param[in] lp low power enable flag
662 *
663 * @api
664 */
665#define rccEnableSDMMC1(lp) rccEnableAPB2(RCC_APB2ENR_SDMMC1EN, lp)
666
667/**
668 * @brief Disables the SDMMC1 peripheral clock.
669 *
670 * @api
671 */
672#define rccDisableSDMMC1() rccDisableAPB2(RCC_APB2ENR_SDMMC1EN)
673
674/**
675 * @brief Resets the SDMMC1 peripheral.
676 *
677 * @api
678 */
679#define rccResetSDMMC1() rccResetAPB2(RCC_APB2RSTR_SDMMC1RST)
680/** @} */
681
682/**
683 * @name SPI peripherals specific RCC operations
684 * @{
685 */
686/**
687 * @brief Enables the SPI1 peripheral clock.
688 *
689 * @param[in] lp low power enable flag
690 *
691 * @api
692 */
693#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
694
695/**
696 * @brief Disables the SPI1 peripheral clock.
697 *
698 * @api
699 */
700#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
701
702/**
703 * @brief Resets the SPI1 peripheral.
704 *
705 * @api
706 */
707#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
708
709/**
710 * @brief Enables the SPI2 peripheral clock.
711 *
712 * @param[in] lp low power enable flag
713 *
714 * @api
715 */
716#define rccEnableSPI2(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI2EN, lp)
717
718/**
719 * @brief Disables the SPI2 peripheral clock.
720 *
721 * @api
722 */
723#define rccDisableSPI2() rccDisableAPB1R1(RCC_APB1ENR1_SPI2EN)
724
725/**
726 * @brief Resets the SPI2 peripheral.
727 *
728 * @api
729 */
730#define rccResetSPI2() rccResetAPB1R1(RCC_APB1RSTR1_SPI2RST)
731
732/**
733 * @brief Enables the SPI3 peripheral clock.
734 *
735 * @param[in] lp low power enable flag
736 *
737 * @api
738 */
739#define rccEnableSPI3(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI3EN, lp)
740
741/**
742 * @brief Disables the SPI3 peripheral clock.
743 *
744 * @api
745 */
746#define rccDisableSPI3() rccDisableAPB1R1(RCC_APB1ENR1_SPI3EN)
747
748/**
749 * @brief Resets the SPI3 peripheral.
750 *
751 * @api
752 */
753#define rccResetSPI3() rccResetAPB1R1(RCC_APB1RSTR1_SPI3RST)
754/** @} */
755
756/**
757 * @name TIM peripherals specific RCC operations
758 * @{
759 */
760/**
761 * @brief Enables the TIM1 peripheral clock.
762 *
763 * @param[in] lp low power enable flag
764 *
765 * @api
766 */
767#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
768
769/**
770 * @brief Disables the TIM1 peripheral clock.
771 *
772 * @api
773 */
774#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
775
776/**
777 * @brief Resets the TIM1 peripheral.
778 *
779 * @api
780 */
781#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
782
783/**
784 * @brief Enables the TIM2 peripheral clock.
785 *
786 * @param[in] lp low power enable flag
787 *
788 * @api
789 */
790#define rccEnableTIM2(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM2EN, lp)
791
792/**
793 * @brief Disables the TIM2 peripheral clock.
794 *
795 * @api
796 */
797#define rccDisableTIM2() rccDisableAPB1R1(RCC_APB1ENR1_TIM2EN)
798
799/**
800 * @brief Resets the TIM2 peripheral.
801 *
802 * @api
803 */
804#define rccResetTIM2() rccResetAPB1R1(RCC_APB1RSTR1_TIM2RST)
805
806/**
807 * @brief Enables the TIM3 peripheral clock.
808 *
809 * @param[in] lp low power enable flag
810 *
811 * @api
812 */
813#define rccEnableTIM3(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM3EN, lp)
814
815/**
816 * @brief Disables the TIM3 peripheral clock.
817 *
818 * @api
819 */
820#define rccDisableTIM3() rccDisableAPB1R1(RCC_APB1ENR1_TIM3EN)
821
822/**
823 * @brief Resets the TIM3 peripheral.
824 *
825 * @api
826 */
827#define rccResetTIM3() rccResetAPB1R1(RCC_APB1RSTR1_TIM3RST)
828
829/**
830 * @brief Enables the TIM4 peripheral clock.
831 *
832 * @param[in] lp low power enable flag
833 *
834 * @api
835 */
836#define rccEnableTIM4(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM4EN, lp)
837
838/**
839 * @brief Disables the TIM4 peripheral clock.
840 *
841 * @api
842 */
843#define rccDisableTIM4() rccDisableAPB1R1(RCC_APB1ENR1_TIM4EN)
844
845/**
846 * @brief Resets the TIM4 peripheral.
847 *
848 * @api
849 */
850#define rccResetTIM4() rccResetAPB1R1(RCC_APB1RSTR1_TIM4RST)
851
852/**
853 * @brief Enables the TIM5 peripheral clock.
854 *
855 * @param[in] lp low power enable flag
856 *
857 * @api
858 */
859#define rccEnableTIM5(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM5EN, lp)
860
861/**
862 * @brief Disables the TIM5 peripheral clock.
863 *
864 * @api
865 */
866#define rccDisableTIM5() rccDisableAPB1R1(RCC_APB1ENR1_TIM5EN)
867
868/**
869 * @brief Resets the TIM5 peripheral.
870 *
871 * @api
872 */
873#define rccResetTIM5() rccResetAPB1R1(RCC_APB1RSTR1_TIM5RST)
874
875/**
876 * @brief Enables the TIM6 peripheral clock.
877 *
878 * @param[in] lp low power enable flag
879 *
880 * @api
881 */
882#define rccEnableTIM6(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM6EN, lp)
883
884/**
885 * @brief Disables the TIM6 peripheral clock.
886 *
887 * @api
888 */
889#define rccDisableTIM6() rccDisableAPB1R1(RCC_APB1ENR1_TIM6EN)
890
891/**
892 * @brief Resets the TIM6 peripheral.
893 *
894 * @api
895 */
896#define rccResetTIM6() rccResetAPB1R1(RCC_APB1RSTR1_TIM6RST)
897
898/**
899 * @brief Enables the TIM7 peripheral clock.
900 *
901 * @param[in] lp low power enable flag
902 *
903 * @api
904 */
905#define rccEnableTIM7(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM7EN, lp)
906
907/**
908 * @brief Disables the TIM7 peripheral clock.
909 *
910 * @api
911 */
912#define rccDisableTIM7() rccDisableAPB1R1(RCC_APB1ENR1_TIM7EN)
913
914/**
915 * @brief Resets the TIM7 peripheral.
916 *
917 * @api
918 */
919#define rccResetTIM7() rccResetAPB1R1(RCC_APB1RSTR1_TIM7RST)
920
921/**
922 * @brief Enables the TIM8 peripheral clock.
923 *
924 * @param[in] lp low power enable flag
925 *
926 * @api
927 */
928#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
929
930/**
931 * @brief Disables the TIM8 peripheral clock.
932 *
933 * @api
934 */
935#define rccDisableTIM8() rccDisableAPB2(RCC_APB2ENR_TIM8EN)
936
937/**
938 * @brief Resets the TIM8 peripheral.
939 *
940 * @api
941 */
942#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
943
944/**
945 * @brief Enables the TIM15 peripheral clock.
946 *
947 * @param[in] lp low power enable flag
948 *
949 * @api
950 */
951#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
952
953/**
954 * @brief Disables the TIM15 peripheral clock.
955 *
956 * @api
957 */
958#define rccDisableTIM15() rccDisableAPB2(RCC_APB2ENR_TIM15EN)
959
960/**
961 * @brief Resets the TIM15 peripheral.
962 *
963 * @api
964 */
965#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
966
967/**
968 * @brief Enables the TIM16 peripheral clock.
969 *
970 * @param[in] lp low power enable flag
971 *
972 * @api
973 */
974#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
975
976/**
977 * @brief Disables the TIM16 peripheral clock.
978 *
979 * @api
980 */
981#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN)
982
983/**
984 * @brief Resets the TIM16 peripheral.
985 *
986 * @api
987 */
988#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
989
990/**
991 * @brief Enables the TIM17 peripheral clock.
992 *
993 * @param[in] lp low power enable flag
994 *
995 * @api
996 */
997#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
998
999/**
1000 * @brief Disables the TIM17 peripheral clock.
1001 *
1002 * @api
1003 */
1004#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN)
1005
1006/**
1007 * @brief Resets the TIM17 peripheral.
1008 *
1009 * @api
1010 */
1011#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
1012/** @} */
1013
1014/**
1015 * @name USART/UART peripherals specific RCC operations
1016 * @{
1017 */
1018/**
1019 * @brief Enables the USART1 peripheral clock.
1020 *
1021 * @param[in] lp low power enable flag
1022 *
1023 * @api
1024 */
1025#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
1026
1027/**
1028 * @brief Disables the USART1 peripheral clock.
1029 *
1030 * @api
1031 */
1032#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
1033
1034/**
1035 * @brief Resets the USART1 peripheral.
1036 *
1037 * @api
1038 */
1039#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
1040
1041/**
1042 * @brief Enables the USART2 peripheral clock.
1043 *
1044 * @param[in] lp low power enable flag
1045 *
1046 * @api
1047 */
1048#define rccEnableUSART2(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART2EN, lp)
1049
1050/**
1051 * @brief Disables the USART2 peripheral clock.
1052 *
1053 * @api
1054 */
1055#define rccDisableUSART2() rccDisableAPB1R1(RCC_APB1ENR1_USART2EN)
1056
1057/**
1058 * @brief Resets the USART2 peripheral.
1059 *
1060 * @api
1061 */
1062#define rccResetUSART2() rccResetAPB1R1(RCC_APB1RSTR1_USART2RST)
1063
1064/**
1065 * @brief Enables the USART3 peripheral clock.
1066 *
1067 * @param[in] lp low power enable flag
1068 *
1069 * @api
1070 */
1071#define rccEnableUSART3(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART3EN, lp)
1072
1073/**
1074 * @brief Disables the USART3 peripheral clock.
1075 *
1076 * @api
1077 */
1078#define rccDisableUSART3() rccDisableAPB1R1(RCC_APB1ENR1_USART3EN)
1079
1080/**
1081 * @brief Resets the USART3 peripheral.
1082 *
1083 * @api
1084 */
1085#define rccResetUSART3() rccResetAPB1R1(RCC_APB1RSTR1_USART3RST)
1086
1087/**
1088 * @brief Enables the UART4 peripheral clock.
1089 *
1090 * @param[in] lp low power enable flag
1091 *
1092 * @api
1093 */
1094#define rccEnableUART4(lp) rccEnableAPB1R1(RCC_APB1ENR1_UART4EN, lp)
1095
1096/**
1097 * @brief Disables the UART4 peripheral clock.
1098 *
1099 * @api
1100 */
1101#define rccDisableUART4() rccDisableAPB1R1(RCC_APB1ENR1_UART4EN)
1102
1103/**
1104 * @brief Resets the UART4 peripheral.
1105 *
1106 * @api
1107 */
1108#define rccResetUART4() rccResetAPB1R1(RCC_APB1RSTR1_UART4RST)
1109
1110/**
1111 * @brief Enables the UART5 peripheral clock.
1112 *
1113 * @param[in] lp low power enable flag
1114 *
1115 * @api
1116 */
1117#define rccEnableUART5(lp) rccEnableAPB1R1(RCC_APB1ENR1_UART5EN, lp)
1118
1119/**
1120 * @brief Disables the UART5 peripheral clock.
1121 *
1122 * @api
1123 */
1124#define rccDisableUART5() rccDisableAPB1R1(RCC_APB1ENR1_UART5EN)
1125
1126/**
1127 * @brief Resets the UART5 peripheral.
1128 *
1129 * @api
1130 */
1131#define rccResetUART5() rccResetAPB1R1(RCC_APB1RSTR1_UART5RST)
1132
1133/**
1134 * @brief Enables the LPUART1 peripheral clock.
1135 *
1136 * @param[in] lp low power enable flag
1137 *
1138 * @api
1139 */
1140#define rccEnableLPUART1(lp) rccEnableAPB1R2(RCC_APB1ENR2_LPUART1EN, lp)
1141
1142/**
1143 * @brief Disables the LPUART1 peripheral clock.
1144 *
1145 * @api
1146 */
1147#define rccDisableLPUART1() rccDisableAPB1R2(RCC_APB1ENR2_LPUART1EN)
1148
1149/**
1150 * @brief Resets the USART1 peripheral.
1151 *
1152 * @api
1153 */
1154#define rccResetLPUART1() rccResetAPB1R2(RCC_APB1RSTR2_LPUART1RST)
1155/** @} */
1156
1157/**
1158 * @name USB peripheral specific RCC operations
1159 * @{
1160 */
1161/**
1162 * @brief Enables the USB peripheral clock.
1163 *
1164 * @param[in] lp low power enable flag
1165 *
1166 * @api
1167 */
1168#define rccEnableUSB(lp) rccEnableAPB1R1(RCC_APB1ENR1_USBFSEN, lp)
1169
1170/**
1171 * @brief Disables the USB peripheral clock.
1172 *
1173 * @api
1174 */
1175#define rccDisableUSB() rccDisableAPB1R1(RCC_APB1ENR1_USBFSEN)
1176
1177/**
1178 * @brief Resets the USB peripheral.
1179 *
1180 * @api
1181 */
1182#define rccResetUSB() rccResetAPB1R1(RCC_APB1RSTR1_USBFSRST)
1183/** @} */
1184
1185/**
1186 * @name CRC peripheral specific RCC operations
1187 * @{
1188 */
1189/**
1190 * @brief Enables the CRC peripheral clock.
1191 *
1192 * @param[in] lp low power enable flag
1193 *
1194 * @api
1195 */
1196#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp)
1197
1198/**
1199 * @brief Disables the CRC peripheral clock.
1200 *
1201 * @api
1202 */
1203#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN)
1204
1205/**
1206 * @brief Resets the CRC peripheral.
1207 *
1208 * @api
1209 */
1210#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
1211/** @} */
1212
1213/**
1214 * @name FSMC peripherals specific RCC operations
1215 * @{
1216 */
1217/**
1218 * @brief Enables the FSMC peripheral clock.
1219 *
1220 * @param[in] lp low power enable flag
1221 *
1222 * @api
1223 */
1224#define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp)
1225
1226/**
1227 * @brief Disables the FSMC peripheral clock.
1228 *
1229 * @api
1230 */
1231#define rccDisableFSMC() rccDisableAHB3(RCC_AHB3ENR_FMCEN)
1232
1233/**
1234 * @brief Resets the FSMC peripheral.
1235 *
1236 * @api
1237 */
1238#define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST)
1239/** @} */
1240
1241/*===========================================================================*/
1242/* External declarations. */
1243/*===========================================================================*/
1244
1245#ifdef __cplusplus
1246extern "C" {
1247#endif
1248#ifdef __cplusplus
1249}
1250#endif
1251
1252#endif /* STM32_RCC_H */
1253
1254/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 01:12:00 +0100