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1/**************************************************************************//**
2 * @file cmsis_armcc.h
3 * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
4 * @version V5.1.0
5 * @date 08. May 2019
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#ifndef __CMSIS_ARMCC_H
26#define __CMSIS_ARMCC_H
27
28
29#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
30 #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
31#endif
32
33/* CMSIS compiler control architecture macros */
34#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
35 (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
36 #define __ARM_ARCH_6M__ 1
37#endif
38
39#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
40 #define __ARM_ARCH_7M__ 1
41#endif
42
43#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
44 #define __ARM_ARCH_7EM__ 1
45#endif
46
47 /* __ARM_ARCH_8M_BASE__ not applicable */
48 /* __ARM_ARCH_8M_MAIN__ not applicable */
49
50/* CMSIS compiler control DSP macros */
51#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
52 #define __ARM_FEATURE_DSP 1
53#endif
54
55/* CMSIS compiler specific defines */
56#ifndef __ASM
57 #define __ASM __asm
58#endif
59#ifndef __INLINE
60 #define __INLINE __inline
61#endif
62#ifndef __STATIC_INLINE
63 #define __STATIC_INLINE static __inline
64#endif
65#ifndef __STATIC_FORCEINLINE
66 #define __STATIC_FORCEINLINE static __forceinline
67#endif
68#ifndef __NO_RETURN
69 #define __NO_RETURN __declspec(noreturn)
70#endif
71#ifndef __USED
72 #define __USED __attribute__((used))
73#endif
74#ifndef __WEAK
75 #define __WEAK __attribute__((weak))
76#endif
77#ifndef __PACKED
78 #define __PACKED __attribute__((packed))
79#endif
80#ifndef __PACKED_STRUCT
81 #define __PACKED_STRUCT __packed struct
82#endif
83#ifndef __PACKED_UNION
84 #define __PACKED_UNION __packed union
85#endif
86#ifndef __UNALIGNED_UINT32 /* deprecated */
87 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
88#endif
89#ifndef __UNALIGNED_UINT16_WRITE
90 #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
91#endif
92#ifndef __UNALIGNED_UINT16_READ
93 #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
94#endif
95#ifndef __UNALIGNED_UINT32_WRITE
96 #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
97#endif
98#ifndef __UNALIGNED_UINT32_READ
99 #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
100#endif
101#ifndef __ALIGNED
102 #define __ALIGNED(x) __attribute__((aligned(x)))
103#endif
104#ifndef __RESTRICT
105 #define __RESTRICT __restrict
106#endif
107#ifndef __COMPILER_BARRIER
108 #define __COMPILER_BARRIER() __memory_changed()
109#endif
110
111/* ######################### Startup and Lowlevel Init ######################## */
112
113#ifndef __PROGRAM_START
114#define __PROGRAM_START __main
115#endif
116
117#ifndef __INITIAL_SP
118#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
119#endif
120
121#ifndef __STACK_LIMIT
122#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
123#endif
124
125#ifndef __VECTOR_TABLE
126#define __VECTOR_TABLE __Vectors
127#endif
128
129#ifndef __VECTOR_TABLE_ATTRIBUTE
130#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
131#endif
132
133/* ########################### Core Function Access ########################### */
134/** \ingroup CMSIS_Core_FunctionInterface
135 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
136 @{
137 */
138
139/**
140 \brief Enable IRQ Interrupts
141 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
142 Can only be executed in Privileged modes.
143 */
144/* intrinsic void __enable_irq(); */
145
146
147/**
148 \brief Disable IRQ Interrupts
149 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
150 Can only be executed in Privileged modes.
151 */
152/* intrinsic void __disable_irq(); */
153
154/**
155 \brief Get Control Register
156 \details Returns the content of the Control Register.
157 \return Control Register value
158 */
159__STATIC_INLINE uint32_t __get_CONTROL(void)
160{
161 register uint32_t __regControl __ASM("control");
162 return(__regControl);
163}
164
165
166/**
167 \brief Set Control Register
168 \details Writes the given value to the Control Register.
169 \param [in] control Control Register value to set
170 */
171__STATIC_INLINE void __set_CONTROL(uint32_t control)
172{
173 register uint32_t __regControl __ASM("control");
174 __regControl = control;
175}
176
177
178/**
179 \brief Get IPSR Register
180 \details Returns the content of the IPSR Register.
181 \return IPSR Register value
182 */
183__STATIC_INLINE uint32_t __get_IPSR(void)
184{
185 register uint32_t __regIPSR __ASM("ipsr");
186 return(__regIPSR);
187}
188
189
190/**
191 \brief Get APSR Register
192 \details Returns the content of the APSR Register.
193 \return APSR Register value
194 */
195__STATIC_INLINE uint32_t __get_APSR(void)
196{
197 register uint32_t __regAPSR __ASM("apsr");
198 return(__regAPSR);
199}
200
201
202/**
203 \brief Get xPSR Register
204 \details Returns the content of the xPSR Register.
205 \return xPSR Register value
206 */
207__STATIC_INLINE uint32_t __get_xPSR(void)
208{
209 register uint32_t __regXPSR __ASM("xpsr");
210 return(__regXPSR);
211}
212
213
214/**
215 \brief Get Process Stack Pointer
216 \details Returns the current value of the Process Stack Pointer (PSP).
217 \return PSP Register value
218 */
219__STATIC_INLINE uint32_t __get_PSP(void)
220{
221 register uint32_t __regProcessStackPointer __ASM("psp");
222 return(__regProcessStackPointer);
223}
224
225
226/**
227 \brief Set Process Stack Pointer
228 \details Assigns the given value to the Process Stack Pointer (PSP).
229 \param [in] topOfProcStack Process Stack Pointer value to set
230 */
231__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
232{
233 register uint32_t __regProcessStackPointer __ASM("psp");
234 __regProcessStackPointer = topOfProcStack;
235}
236
237
238/**
239 \brief Get Main Stack Pointer
240 \details Returns the current value of the Main Stack Pointer (MSP).
241 \return MSP Register value
242 */
243__STATIC_INLINE uint32_t __get_MSP(void)
244{
245 register uint32_t __regMainStackPointer __ASM("msp");
246 return(__regMainStackPointer);
247}
248
249
250/**
251 \brief Set Main Stack Pointer
252 \details Assigns the given value to the Main Stack Pointer (MSP).
253 \param [in] topOfMainStack Main Stack Pointer value to set
254 */
255__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
256{
257 register uint32_t __regMainStackPointer __ASM("msp");
258 __regMainStackPointer = topOfMainStack;
259}
260
261
262/**
263 \brief Get Priority Mask
264 \details Returns the current state of the priority mask bit from the Priority Mask Register.
265 \return Priority Mask value
266 */
267__STATIC_INLINE uint32_t __get_PRIMASK(void)
268{
269 register uint32_t __regPriMask __ASM("primask");
270 return(__regPriMask);
271}
272
273
274/**
275 \brief Set Priority Mask
276 \details Assigns the given value to the Priority Mask Register.
277 \param [in] priMask Priority Mask
278 */
279__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
280{
281 register uint32_t __regPriMask __ASM("primask");
282 __regPriMask = (priMask);
283}
284
285
286#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
287 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
288
289/**
290 \brief Enable FIQ
291 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
292 Can only be executed in Privileged modes.
293 */
294#define __enable_fault_irq __enable_fiq
295
296
297/**
298 \brief Disable FIQ
299 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
300 Can only be executed in Privileged modes.
301 */
302#define __disable_fault_irq __disable_fiq
303
304
305/**
306 \brief Get Base Priority
307 \details Returns the current value of the Base Priority register.
308 \return Base Priority register value
309 */
310__STATIC_INLINE uint32_t __get_BASEPRI(void)
311{
312 register uint32_t __regBasePri __ASM("basepri");
313 return(__regBasePri);
314}
315
316
317/**
318 \brief Set Base Priority
319 \details Assigns the given value to the Base Priority register.
320 \param [in] basePri Base Priority value to set
321 */
322__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
323{
324 register uint32_t __regBasePri __ASM("basepri");
325 __regBasePri = (basePri & 0xFFU);
326}
327
328
329/**
330 \brief Set Base Priority with condition
331 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
332 or the new value increases the BASEPRI priority level.
333 \param [in] basePri Base Priority value to set
334 */
335__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
336{
337 register uint32_t __regBasePriMax __ASM("basepri_max");
338 __regBasePriMax = (basePri & 0xFFU);
339}
340
341
342/**
343 \brief Get Fault Mask
344 \details Returns the current value of the Fault Mask register.
345 \return Fault Mask register value
346 */
347__STATIC_INLINE uint32_t __get_FAULTMASK(void)
348{
349 register uint32_t __regFaultMask __ASM("faultmask");
350 return(__regFaultMask);
351}
352
353
354/**
355 \brief Set Fault Mask
356 \details Assigns the given value to the Fault Mask register.
357 \param [in] faultMask Fault Mask value to set
358 */
359__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
360{
361 register uint32_t __regFaultMask __ASM("faultmask");
362 __regFaultMask = (faultMask & (uint32_t)1U);
363}
364
365#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
366 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
367
368
369/**
370 \brief Get FPSCR
371 \details Returns the current value of the Floating Point Status/Control register.
372 \return Floating Point Status/Control register value
373 */
374__STATIC_INLINE uint32_t __get_FPSCR(void)
375{
376#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
377 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
378 register uint32_t __regfpscr __ASM("fpscr");
379 return(__regfpscr);
380#else
381 return(0U);
382#endif
383}
384
385
386/**
387 \brief Set FPSCR
388 \details Assigns the given value to the Floating Point Status/Control register.
389 \param [in] fpscr Floating Point Status/Control value to set
390 */
391__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
392{
393#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
394 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
395 register uint32_t __regfpscr __ASM("fpscr");
396 __regfpscr = (fpscr);
397#else
398 (void)fpscr;
399#endif
400}
401
402
403/*@} end of CMSIS_Core_RegAccFunctions */
404
405
406/* ########################## Core Instruction Access ######################### */
407/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
408 Access to dedicated instructions
409 @{
410*/
411
412/**
413 \brief No Operation
414 \details No Operation does nothing. This instruction can be used for code alignment purposes.
415 */
416#define __NOP __nop
417
418
419/**
420 \brief Wait For Interrupt
421 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
422 */
423#define __WFI __wfi
424
425
426/**
427 \brief Wait For Event
428 \details Wait For Event is a hint instruction that permits the processor to enter
429 a low-power state until one of a number of events occurs.
430 */
431#define __WFE __wfe
432
433
434/**
435 \brief Send Event
436 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
437 */
438#define __SEV __sev
439
440
441/**
442 \brief Instruction Synchronization Barrier
443 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
444 so that all instructions following the ISB are fetched from cache or memory,
445 after the instruction has been completed.
446 */
447#define __ISB() do {\
448 __schedule_barrier();\
449 __isb(0xF);\
450 __schedule_barrier();\
451 } while (0U)
452
453/**
454 \brief Data Synchronization Barrier
455 \details Acts as a special kind of Data Memory Barrier.
456 It completes when all explicit memory accesses before this instruction complete.
457 */
458#define __DSB() do {\
459 __schedule_barrier();\
460 __dsb(0xF);\
461 __schedule_barrier();\
462 } while (0U)
463
464/**
465 \brief Data Memory Barrier
466 \details Ensures the apparent order of the explicit memory operations before
467 and after the instruction, without ensuring their completion.
468 */
469#define __DMB() do {\
470 __schedule_barrier();\
471 __dmb(0xF);\
472 __schedule_barrier();\
473 } while (0U)
474
475
476/**
477 \brief Reverse byte order (32 bit)
478 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
479 \param [in] value Value to reverse
480 \return Reversed value
481 */
482#define __REV __rev
483
484
485/**
486 \brief Reverse byte order (16 bit)
487 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
488 \param [in] value Value to reverse
489 \return Reversed value
490 */
491#ifndef __NO_EMBEDDED_ASM
492__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
493{
494 rev16 r0, r0
495 bx lr
496}
497#endif
498
499
500/**
501 \brief Reverse byte order (16 bit)
502 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
503 \param [in] value Value to reverse
504 \return Reversed value
505 */
506#ifndef __NO_EMBEDDED_ASM
507__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
508{
509 revsh r0, r0
510 bx lr
511}
512#endif
513
514
515/**
516 \brief Rotate Right in unsigned value (32 bit)
517 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
518 \param [in] op1 Value to rotate
519 \param [in] op2 Number of Bits to rotate
520 \return Rotated value
521 */
522#define __ROR __ror
523
524
525/**
526 \brief Breakpoint
527 \details Causes the processor to enter Debug state.
528 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
529 \param [in] value is ignored by the processor.
530 If required, a debugger can use it to store additional information about the breakpoint.
531 */
532#define __BKPT(value) __breakpoint(value)
533
534
535/**
536 \brief Reverse bit order of value
537 \details Reverses the bit order of the given value.
538 \param [in] value Value to reverse
539 \return Reversed value
540 */
541#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
542 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
543 #define __RBIT __rbit
544#else
545__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
546{
547 uint32_t result;
548 uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
549
550 result = value; /* r will be reversed bits of v; first get LSB of v */
551 for (value >>= 1U; value != 0U; value >>= 1U)
552 {
553 result <<= 1U;
554 result |= value & 1U;
555 s--;
556 }
557 result <<= s; /* shift when v's highest bits are zero */
558 return result;
559}
560#endif
561
562
563/**
564 \brief Count leading zeros
565 \details Counts the number of leading zeros of a data value.
566 \param [in] value Value to count the leading zeros
567 \return number of leading zeros in value
568 */
569#define __CLZ __clz
570
571
572#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
573 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
574
575/**
576 \brief LDR Exclusive (8 bit)
577 \details Executes a exclusive LDR instruction for 8 bit value.
578 \param [in] ptr Pointer to data
579 \return value of type uint8_t at (*ptr)
580 */
581#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
582 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
583#else
584 #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
585#endif
586
587
588/**
589 \brief LDR Exclusive (16 bit)
590 \details Executes a exclusive LDR instruction for 16 bit values.
591 \param [in] ptr Pointer to data
592 \return value of type uint16_t at (*ptr)
593 */
594#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
595 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
596#else
597 #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
598#endif
599
600
601/**
602 \brief LDR Exclusive (32 bit)
603 \details Executes a exclusive LDR instruction for 32 bit values.
604 \param [in] ptr Pointer to data
605 \return value of type uint32_t at (*ptr)
606 */
607#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
608 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
609#else
610 #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
611#endif
612
613
614/**
615 \brief STR Exclusive (8 bit)
616 \details Executes a exclusive STR instruction for 8 bit values.
617 \param [in] value Value to store
618 \param [in] ptr Pointer to location
619 \return 0 Function succeeded
620 \return 1 Function failed
621 */
622#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
623 #define __STREXB(value, ptr) __strex(value, ptr)
624#else
625 #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
626#endif
627
628
629/**
630 \brief STR Exclusive (16 bit)
631 \details Executes a exclusive STR instruction for 16 bit values.
632 \param [in] value Value to store
633 \param [in] ptr Pointer to location
634 \return 0 Function succeeded
635 \return 1 Function failed
636 */
637#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
638 #define __STREXH(value, ptr) __strex(value, ptr)
639#else
640 #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
641#endif
642
643
644/**
645 \brief STR Exclusive (32 bit)
646 \details Executes a exclusive STR instruction for 32 bit values.
647 \param [in] value Value to store
648 \param [in] ptr Pointer to location
649 \return 0 Function succeeded
650 \return 1 Function failed
651 */
652#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
653 #define __STREXW(value, ptr) __strex(value, ptr)
654#else
655 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
656#endif
657
658
659/**
660 \brief Remove the exclusive lock
661 \details Removes the exclusive lock which is created by LDREX.
662 */
663#define __CLREX __clrex
664
665
666/**
667 \brief Signed Saturate
668 \details Saturates a signed value.
669 \param [in] value Value to be saturated
670 \param [in] sat Bit position to saturate to (1..32)
671 \return Saturated value
672 */
673#define __SSAT __ssat
674
675
676/**
677 \brief Unsigned Saturate
678 \details Saturates an unsigned value.
679 \param [in] value Value to be saturated
680 \param [in] sat Bit position to saturate to (0..31)
681 \return Saturated value
682 */
683#define __USAT __usat
684
685
686/**
687 \brief Rotate Right with Extend (32 bit)
688 \details Moves each bit of a bitstring right by one bit.
689 The carry input is shifted in at the left end of the bitstring.
690 \param [in] value Value to rotate
691 \return Rotated value
692 */
693#ifndef __NO_EMBEDDED_ASM
694__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
695{
696 rrx r0, r0
697 bx lr
698}
699#endif
700
701
702/**
703 \brief LDRT Unprivileged (8 bit)
704 \details Executes a Unprivileged LDRT instruction for 8 bit value.
705 \param [in] ptr Pointer to data
706 \return value of type uint8_t at (*ptr)
707 */
708#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
709
710
711/**
712 \brief LDRT Unprivileged (16 bit)
713 \details Executes a Unprivileged LDRT instruction for 16 bit values.
714 \param [in] ptr Pointer to data
715 \return value of type uint16_t at (*ptr)
716 */
717#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
718
719
720/**
721 \brief LDRT Unprivileged (32 bit)
722 \details Executes a Unprivileged LDRT instruction for 32 bit values.
723 \param [in] ptr Pointer to data
724 \return value of type uint32_t at (*ptr)
725 */
726#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
727
728
729/**
730 \brief STRT Unprivileged (8 bit)
731 \details Executes a Unprivileged STRT instruction for 8 bit values.
732 \param [in] value Value to store
733 \param [in] ptr Pointer to location
734 */
735#define __STRBT(value, ptr) __strt(value, ptr)
736
737
738/**
739 \brief STRT Unprivileged (16 bit)
740 \details Executes a Unprivileged STRT instruction for 16 bit values.
741 \param [in] value Value to store
742 \param [in] ptr Pointer to location
743 */
744#define __STRHT(value, ptr) __strt(value, ptr)
745
746
747/**
748 \brief STRT Unprivileged (32 bit)
749 \details Executes a Unprivileged STRT instruction for 32 bit values.
750 \param [in] value Value to store
751 \param [in] ptr Pointer to location
752 */
753#define __STRT(value, ptr) __strt(value, ptr)
754
755#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
756 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
757
758/**
759 \brief Signed Saturate
760 \details Saturates a signed value.
761 \param [in] value Value to be saturated
762 \param [in] sat Bit position to saturate to (1..32)
763 \return Saturated value
764 */
765__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
766{
767 if ((sat >= 1U) && (sat <= 32U))
768 {
769 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
770 const int32_t min = -1 - max ;
771 if (val > max)
772 {
773 return max;
774 }
775 else if (val < min)
776 {
777 return min;
778 }
779 }
780 return val;
781}
782
783/**
784 \brief Unsigned Saturate
785 \details Saturates an unsigned value.
786 \param [in] value Value to be saturated
787 \param [in] sat Bit position to saturate to (0..31)
788 \return Saturated value
789 */
790__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
791{
792 if (sat <= 31U)
793 {
794 const uint32_t max = ((1U << sat) - 1U);
795 if (val > (int32_t)max)
796 {
797 return max;
798 }
799 else if (val < 0)
800 {
801 return 0U;
802 }
803 }
804 return (uint32_t)val;
805}
806
807#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
808 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
809
810/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
811
812
813/* ################### Compiler specific Intrinsics ########################### */
814/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
815 Access to dedicated SIMD instructions
816 @{
817*/
818
819#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
820
821#define __SADD8 __sadd8
822#define __QADD8 __qadd8
823#define __SHADD8 __shadd8
824#define __UADD8 __uadd8
825#define __UQADD8 __uqadd8
826#define __UHADD8 __uhadd8
827#define __SSUB8 __ssub8
828#define __QSUB8 __qsub8
829#define __SHSUB8 __shsub8
830#define __USUB8 __usub8
831#define __UQSUB8 __uqsub8
832#define __UHSUB8 __uhsub8
833#define __SADD16 __sadd16
834#define __QADD16 __qadd16
835#define __SHADD16 __shadd16
836#define __UADD16 __uadd16
837#define __UQADD16 __uqadd16
838#define __UHADD16 __uhadd16
839#define __SSUB16 __ssub16
840#define __QSUB16 __qsub16
841#define __SHSUB16 __shsub16
842#define __USUB16 __usub16
843#define __UQSUB16 __uqsub16
844#define __UHSUB16 __uhsub16
845#define __SASX __sasx
846#define __QASX __qasx
847#define __SHASX __shasx
848#define __UASX __uasx
849#define __UQASX __uqasx
850#define __UHASX __uhasx
851#define __SSAX __ssax
852#define __QSAX __qsax
853#define __SHSAX __shsax
854#define __USAX __usax
855#define __UQSAX __uqsax
856#define __UHSAX __uhsax
857#define __USAD8 __usad8
858#define __USADA8 __usada8
859#define __SSAT16 __ssat16
860#define __USAT16 __usat16
861#define __UXTB16 __uxtb16
862#define __UXTAB16 __uxtab16
863#define __SXTB16 __sxtb16
864#define __SXTAB16 __sxtab16
865#define __SMUAD __smuad
866#define __SMUADX __smuadx
867#define __SMLAD __smlad
868#define __SMLADX __smladx
869#define __SMLALD __smlald
870#define __SMLALDX __smlaldx
871#define __SMUSD __smusd
872#define __SMUSDX __smusdx
873#define __SMLSD __smlsd
874#define __SMLSDX __smlsdx
875#define __SMLSLD __smlsld
876#define __SMLSLDX __smlsldx
877#define __SEL __sel
878#define __QADD __qadd
879#define __QSUB __qsub
880
881#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
882 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
883
884#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
885 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
886
887#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
888 ((int64_t)(ARG3) << 32U) ) >> 32U))
889
890#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
891/*@} end of group CMSIS_SIMD_intrinsics */
892
893
894#endif /* __CMSIS_ARMCC_H */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:56:12 +0100