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1/**************************************************************************//**
2 * @file core_armv81mml.h
3 * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
4 * @version V1.0.0
5 * @date 15. March 2019
6 ******************************************************************************/
7/*
8 * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_ARMV81MML_H_GENERIC
32#define __CORE_ARMV81MML_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
40/**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58/**
59 \ingroup Cortex_ARMV81MML
60 @{
61 */
62
63#include "cmsis_version.h"
64
65#define __ARM_ARCH_8M_MAIN__ 1 // patching for now
66/* CMSIS ARMV81MML definitions */
67#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
68#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
69#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \
70 __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
71
72#define __CORTEX_M (81U) /*!< Cortex-M Core */
73
74/** __FPU_USED indicates whether an FPU is used or not.
75 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
76*/
77#if defined ( __CC_ARM )
78 #if defined __TARGET_FPU_VFP
79 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
80 #define __FPU_USED 1U
81 #else
82 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
83 #define __FPU_USED 0U
84 #endif
85 #else
86 #define __FPU_USED 0U
87 #endif
88
89 #if defined(__ARM_FEATURE_DSP)
90 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
91 #define __DSP_USED 1U
92 #else
93 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
94 #define __DSP_USED 0U
95 #endif
96 #else
97 #define __DSP_USED 0U
98 #endif
99
100#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
101 #if defined __ARM_FP
102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103 #define __FPU_USED 1U
104 #else
105 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #define __FPU_USED 0U
107 #endif
108 #else
109 #define __FPU_USED 0U
110 #endif
111
112 #if defined(__ARM_FEATURE_DSP)
113 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
114 #define __DSP_USED 1U
115 #else
116 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
117 #define __DSP_USED 0U
118 #endif
119 #else
120 #define __DSP_USED 0U
121 #endif
122
123#elif defined ( __GNUC__ )
124 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
125 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
126 #define __FPU_USED 1U
127 #else
128 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129 #define __FPU_USED 0U
130 #endif
131 #else
132 #define __FPU_USED 0U
133 #endif
134
135 #if defined(__ARM_FEATURE_DSP)
136 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
137 #define __DSP_USED 1U
138 #else
139 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
140 #define __DSP_USED 0U
141 #endif
142 #else
143 #define __DSP_USED 0U
144 #endif
145
146#elif defined ( __ICCARM__ )
147 #if defined __ARMVFP__
148 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
149 #define __FPU_USED 1U
150 #else
151 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
152 #define __FPU_USED 0U
153 #endif
154 #else
155 #define __FPU_USED 0U
156 #endif
157
158 #if defined(__ARM_FEATURE_DSP)
159 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
160 #define __DSP_USED 1U
161 #else
162 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
163 #define __DSP_USED 0U
164 #endif
165 #else
166 #define __DSP_USED 0U
167 #endif
168
169#elif defined ( __TI_ARM__ )
170 #if defined __TI_VFP_SUPPORT__
171 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
172 #define __FPU_USED 1U
173 #else
174 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
175 #define __FPU_USED 0U
176 #endif
177 #else
178 #define __FPU_USED 0U
179 #endif
180
181#elif defined ( __TASKING__ )
182 #if defined __FPU_VFP__
183 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
184 #define __FPU_USED 1U
185 #else
186 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
187 #define __FPU_USED 0U
188 #endif
189 #else
190 #define __FPU_USED 0U
191 #endif
192
193#elif defined ( __CSMC__ )
194 #if ( __CSMC__ & 0x400U)
195 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
196 #define __FPU_USED 1U
197 #else
198 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
199 #define __FPU_USED 0U
200 #endif
201 #else
202 #define __FPU_USED 0U
203 #endif
204
205#endif
206
207#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
208
209
210#ifdef __cplusplus
211}
212#endif
213
214#endif /* __CORE_ARMV81MML_H_GENERIC */
215
216#ifndef __CMSIS_GENERIC
217
218#ifndef __CORE_ARMV81MML_H_DEPENDANT
219#define __CORE_ARMV81MML_H_DEPENDANT
220
221#ifdef __cplusplus
222 extern "C" {
223#endif
224
225/* check device defines and use defaults */
226#if defined __CHECK_DEVICE_DEFINES
227 #ifndef __ARMv81MML_REV
228 #define __ARMv81MML_REV 0x0000U
229 #warning "__ARMv81MML_REV not defined in device header file; using default!"
230 #endif
231
232 #ifndef __FPU_PRESENT
233 #define __FPU_PRESENT 0U
234 #warning "__FPU_PRESENT not defined in device header file; using default!"
235 #endif
236
237 #ifndef __MPU_PRESENT
238 #define __MPU_PRESENT 0U
239 #warning "__MPU_PRESENT not defined in device header file; using default!"
240 #endif
241
242 #ifndef __SAUREGION_PRESENT
243 #define __SAUREGION_PRESENT 0U
244 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
245 #endif
246
247 #ifndef __DSP_PRESENT
248 #define __DSP_PRESENT 0U
249 #warning "__DSP_PRESENT not defined in device header file; using default!"
250 #endif
251
252 #ifndef __NVIC_PRIO_BITS
253 #define __NVIC_PRIO_BITS 3U
254 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
255 #endif
256
257 #ifndef __Vendor_SysTickConfig
258 #define __Vendor_SysTickConfig 0U
259 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
260 #endif
261#endif
262
263/* IO definitions (access restrictions to peripheral registers) */
264/**
265 \defgroup CMSIS_glob_defs CMSIS Global Defines
266
267 <strong>IO Type Qualifiers</strong> are used
268 \li to specify the access to peripheral variables.
269 \li for automatic generation of peripheral register debug information.
270*/
271#ifdef __cplusplus
272 #define __I volatile /*!< Defines 'read only' permissions */
273#else
274 #define __I volatile const /*!< Defines 'read only' permissions */
275#endif
276#define __O volatile /*!< Defines 'write only' permissions */
277#define __IO volatile /*!< Defines 'read / write' permissions */
278
279/* following defines should be used for structure members */
280#define __IM volatile const /*! Defines 'read only' structure member permissions */
281#define __OM volatile /*! Defines 'write only' structure member permissions */
282#define __IOM volatile /*! Defines 'read / write' structure member permissions */
283
284/*@} end of group ARMv81MML */
285
286
287
288/*******************************************************************************
289 * Register Abstraction
290 Core Register contain:
291 - Core Register
292 - Core NVIC Register
293 - Core SCB Register
294 - Core SysTick Register
295 - Core Debug Register
296 - Core MPU Register
297 - Core SAU Register
298 - Core FPU Register
299 ******************************************************************************/
300/**
301 \defgroup CMSIS_core_register Defines and Type Definitions
302 \brief Type definitions and defines for Cortex-M processor based devices.
303*/
304
305/**
306 \ingroup CMSIS_core_register
307 \defgroup CMSIS_CORE Status and Control Registers
308 \brief Core Register type definitions.
309 @{
310 */
311
312/**
313 \brief Union type to access the Application Program Status Register (APSR).
314 */
315typedef union
316{
317 struct
318 {
319 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
320 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
321 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
322 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
323 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
324 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
325 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
326 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
327 } b; /*!< Structure used for bit access */
328 uint32_t w; /*!< Type used for word access */
329} APSR_Type;
330
331/* APSR Register Definitions */
332#define APSR_N_Pos 31U /*!< APSR: N Position */
333#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
334
335#define APSR_Z_Pos 30U /*!< APSR: Z Position */
336#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
337
338#define APSR_C_Pos 29U /*!< APSR: C Position */
339#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
340
341#define APSR_V_Pos 28U /*!< APSR: V Position */
342#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
343
344#define APSR_Q_Pos 27U /*!< APSR: Q Position */
345#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
346
347#define APSR_GE_Pos 16U /*!< APSR: GE Position */
348#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
349
350
351/**
352 \brief Union type to access the Interrupt Program Status Register (IPSR).
353 */
354typedef union
355{
356 struct
357 {
358 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
359 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
360 } b; /*!< Structure used for bit access */
361 uint32_t w; /*!< Type used for word access */
362} IPSR_Type;
363
364/* IPSR Register Definitions */
365#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
366#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
367
368
369/**
370 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
371 */
372typedef union
373{
374 struct
375 {
376 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
377 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
378 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
379 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
380 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
381 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
382 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
383 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
384 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
385 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
386 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
387 } b; /*!< Structure used for bit access */
388 uint32_t w; /*!< Type used for word access */
389} xPSR_Type;
390
391/* xPSR Register Definitions */
392#define xPSR_N_Pos 31U /*!< xPSR: N Position */
393#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
394
395#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
396#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
397
398#define xPSR_C_Pos 29U /*!< xPSR: C Position */
399#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
400
401#define xPSR_V_Pos 28U /*!< xPSR: V Position */
402#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
403
404#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
405#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
406
407#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
408#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
409
410#define xPSR_T_Pos 24U /*!< xPSR: T Position */
411#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
412
413#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
414#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
415
416#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
417#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
418
419
420/**
421 \brief Union type to access the Control Registers (CONTROL).
422 */
423typedef union
424{
425 struct
426 {
427 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
428 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
429 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
430 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
431 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
432 } b; /*!< Structure used for bit access */
433 uint32_t w; /*!< Type used for word access */
434} CONTROL_Type;
435
436/* CONTROL Register Definitions */
437#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
438#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
439
440#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
441#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
442
443#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
444#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
445
446#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
447#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
448
449/*@} end of group CMSIS_CORE */
450
451
452/**
453 \ingroup CMSIS_core_register
454 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
455 \brief Type definitions for the NVIC Registers
456 @{
457 */
458
459/**
460 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
461 */
462typedef struct
463{
464 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
465 uint32_t RESERVED0[16U];
466 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
467 uint32_t RSERVED1[16U];
468 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
469 uint32_t RESERVED2[16U];
470 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
471 uint32_t RESERVED3[16U];
472 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
473 uint32_t RESERVED4[16U];
474 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
475 uint32_t RESERVED5[16U];
476 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
477 uint32_t RESERVED6[580U];
478 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
479} NVIC_Type;
480
481/* Software Triggered Interrupt Register Definitions */
482#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
483#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
484
485/*@} end of group CMSIS_NVIC */
486
487
488/**
489 \ingroup CMSIS_core_register
490 \defgroup CMSIS_SCB System Control Block (SCB)
491 \brief Type definitions for the System Control Block Registers
492 @{
493 */
494
495/**
496 \brief Structure type to access the System Control Block (SCB).
497 */
498typedef struct
499{
500 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
501 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
502 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
503 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
504 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
505 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
506 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
507 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
508 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
509 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
510 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
511 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
512 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
513 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
514 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
515 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
516 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
517 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
518 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
519 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
520 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
521 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
522 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
523 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
524 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
525 uint32_t RESERVED3[92U];
526 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
527 uint32_t RESERVED4[15U];
528 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
529 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
530 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
531 uint32_t RESERVED5[1U];
532 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
533 uint32_t RESERVED6[1U];
534 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
535 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
536 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
537 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
538 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
539 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
540 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
541 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
542 uint32_t RESERVED7[6U];
543 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
544 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
545 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
546 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
547 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
548 uint32_t RESERVED8[1U];
549 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
550} SCB_Type;
551
552/* SCB CPUID Register Definitions */
553#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
554#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
555
556#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
557#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
558
559#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
560#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
561
562#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
563#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
564
565#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
566#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
567
568/* SCB Interrupt Control State Register Definitions */
569#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
570#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
571
572#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
573#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
574
575#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
576#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
577
578#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
579#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
580
581#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
582#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
583
584#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
585#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
586
587#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
588#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
589
590#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
591#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
592
593#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
594#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
595
596#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
597#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
598
599#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
600#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
601
602#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
603#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
604
605#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
606#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
607
608/* SCB Vector Table Offset Register Definitions */
609#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
610#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
611
612/* SCB Application Interrupt and Reset Control Register Definitions */
613#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
614#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
615
616#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
617#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
618
619#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
620#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
621
622#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
623#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
624
625#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
626#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
627
628#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
629#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
630
631#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
632#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
633
634#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
635#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
636
637#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
638#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
639
640/* SCB System Control Register Definitions */
641#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
642#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
643
644#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
645#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
646
647#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
648#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
649
650#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
651#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
652
653/* SCB Configuration Control Register Definitions */
654#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
655#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
656
657#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
658#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
659
660#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
661#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
662
663#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
664#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
665
666#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
667#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
668
669#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
670#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
671
672#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
673#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
674
675#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
676#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
677
678/* SCB System Handler Control and State Register Definitions */
679#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
680#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
681
682#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
683#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
684
685#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
686#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
687
688#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
689#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
690
691#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
692#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
693
694#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
695#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
696
697#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
698#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
699
700#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
701#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
702
703#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
704#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
705
706#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
707#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
708
709#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
710#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
711
712#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
713#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
714
715#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
716#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
717
718#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
719#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
720
721#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
722#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
723
724#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
725#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
726
727#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
728#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
729
730#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
731#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
732
733#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
734#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
735
736#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
737#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
738
739/* SCB Configurable Fault Status Register Definitions */
740#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
741#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
742
743#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
744#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
745
746#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
747#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
748
749/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
750#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
751#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
752
753#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
754#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
755
756#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
757#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
758
759#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
760#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
761
762#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
763#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
764
765#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
766#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
767
768/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
769#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
770#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
771
772#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
773#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
774
775#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
776#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
777
778#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
779#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
780
781#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
782#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
783
784#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
785#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
786
787#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
788#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
789
790/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
791#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
792#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
793
794#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
795#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
796
797#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
798#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
799
800#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
801#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
802
803#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
804#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
805
806#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
807#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
808
809#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
810#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
811
812/* SCB Hard Fault Status Register Definitions */
813#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
814#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
815
816#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
817#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
818
819#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
820#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
821
822/* SCB Debug Fault Status Register Definitions */
823#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
824#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
825
826#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
827#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
828
829#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
830#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
831
832#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
833#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
834
835#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
836#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
837
838/* SCB Non-Secure Access Control Register Definitions */
839#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
840#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
841
842#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
843#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
844
845#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
846#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
847
848/* SCB Cache Level ID Register Definitions */
849#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
850#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
851
852#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
853#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
854
855/* SCB Cache Type Register Definitions */
856#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
857#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
858
859#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
860#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
861
862#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
863#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
864
865#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
866#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
867
868#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
869#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
870
871/* SCB Cache Size ID Register Definitions */
872#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
873#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
874
875#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
876#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
877
878#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
879#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
880
881#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
882#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
883
884#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
885#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
886
887#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
888#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
889
890#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
891#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
892
893/* SCB Cache Size Selection Register Definitions */
894#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
895#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
896
897#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
898#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
899
900/* SCB Software Triggered Interrupt Register Definitions */
901#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
902#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
903
904/* SCB D-Cache Invalidate by Set-way Register Definitions */
905#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
906#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
907
908#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
909#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
910
911/* SCB D-Cache Clean by Set-way Register Definitions */
912#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
913#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
914
915#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
916#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
917
918/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
919#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
920#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
921
922#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
923#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
924
925/* Instruction Tightly-Coupled Memory Control Register Definitions */
926#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
927#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
928
929#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
930#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
931
932#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
933#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
934
935#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
936#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
937
938/* Data Tightly-Coupled Memory Control Register Definitions */
939#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
940#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
941
942#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
943#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
944
945#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
946#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
947
948#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
949#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
950
951/* AHBP Control Register Definitions */
952#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
953#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
954
955#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
956#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
957
958/* L1 Cache Control Register Definitions */
959#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
960#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
961
962#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
963#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
964
965#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
966#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
967
968/* AHBS Control Register Definitions */
969#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
970#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
971
972#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
973#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
974
975#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
976#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
977
978/* Auxiliary Bus Fault Status Register Definitions */
979#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
980#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
981
982#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
983#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
984
985#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
986#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
987
988#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
989#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
990
991#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
992#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
993
994#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
995#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
996
997/*@} end of group CMSIS_SCB */
998
999
1000/**
1001 \ingroup CMSIS_core_register
1002 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
1003 \brief Type definitions for the System Control and ID Register not in the SCB
1004 @{
1005 */
1006
1007/**
1008 \brief Structure type to access the System Control and ID Register not in the SCB.
1009 */
1010typedef struct
1011{
1012 uint32_t RESERVED0[1U];
1013 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
1014 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
1015 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
1016} SCnSCB_Type;
1017
1018/* Interrupt Controller Type Register Definitions */
1019#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
1020#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
1021
1022/*@} end of group CMSIS_SCnotSCB */
1023
1024
1025/**
1026 \ingroup CMSIS_core_register
1027 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
1028 \brief Type definitions for the System Timer Registers.
1029 @{
1030 */
1031
1032/**
1033 \brief Structure type to access the System Timer (SysTick).
1034 */
1035typedef struct
1036{
1037 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
1038 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
1039 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
1040 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
1041} SysTick_Type;
1042
1043/* SysTick Control / Status Register Definitions */
1044#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
1045#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
1046
1047#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
1048#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
1049
1050#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1051#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1052
1053#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1054#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1055
1056/* SysTick Reload Register Definitions */
1057#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
1058#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
1059
1060/* SysTick Current Register Definitions */
1061#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
1062#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
1063
1064/* SysTick Calibration Register Definitions */
1065#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
1066#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
1067
1068#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
1069#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
1070
1071#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
1072#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
1073
1074/*@} end of group CMSIS_SysTick */
1075
1076
1077/**
1078 \ingroup CMSIS_core_register
1079 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
1080 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1081 @{
1082 */
1083
1084/**
1085 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1086 */
1087typedef struct
1088{
1089 __OM union
1090 {
1091 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1092 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1093 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1094 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
1095 uint32_t RESERVED0[864U];
1096 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
1097 uint32_t RESERVED1[15U];
1098 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
1099 uint32_t RESERVED2[15U];
1100 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
1101 uint32_t RESERVED3[29U];
1102 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
1103 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
1104 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
1105 uint32_t RESERVED4[43U];
1106 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
1107 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1108 uint32_t RESERVED5[1U];
1109 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
1110 uint32_t RESERVED6[4U];
1111 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
1112 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
1113 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
1114 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
1115 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
1116 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
1117 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
1118 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
1119 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
1120 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
1121 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
1122 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
1123} ITM_Type;
1124
1125/* ITM Stimulus Port Register Definitions */
1126#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
1127#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
1128
1129#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
1130#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
1131
1132/* ITM Trace Privilege Register Definitions */
1133#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
1134#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
1135
1136/* ITM Trace Control Register Definitions */
1137#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
1138#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
1139
1140#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
1141#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
1142
1143#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
1144#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
1145
1146#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
1147#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
1148
1149#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
1150#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
1151
1152#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
1153#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
1154
1155#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
1156#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1157
1158#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
1159#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1160
1161#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
1162#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1163
1164#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
1165#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1166
1167/* ITM Integration Write Register Definitions */
1168#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
1169#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
1170
1171/* ITM Integration Read Register Definitions */
1172#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
1173#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
1174
1175/* ITM Integration Mode Control Register Definitions */
1176#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
1177#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
1178
1179/* ITM Lock Status Register Definitions */
1180#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
1181#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
1182
1183#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
1184#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
1185
1186#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
1187#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
1188
1189/*@}*/ /* end of group CMSIS_ITM */
1190
1191
1192/**
1193 \ingroup CMSIS_core_register
1194 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1195 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1196 @{
1197 */
1198
1199/**
1200 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1201 */
1202typedef struct
1203{
1204 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1205 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1206 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1207 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1208 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1209 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1210 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1211 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1212 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1213 uint32_t RESERVED1[1U];
1214 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1215 uint32_t RESERVED2[1U];
1216 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1217 uint32_t RESERVED3[1U];
1218 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1219 uint32_t RESERVED4[1U];
1220 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1221 uint32_t RESERVED5[1U];
1222 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1223 uint32_t RESERVED6[1U];
1224 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1225 uint32_t RESERVED7[1U];
1226 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1227 uint32_t RESERVED8[1U];
1228 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
1229 uint32_t RESERVED9[1U];
1230 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1231 uint32_t RESERVED10[1U];
1232 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
1233 uint32_t RESERVED11[1U];
1234 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
1235 uint32_t RESERVED12[1U];
1236 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
1237 uint32_t RESERVED13[1U];
1238 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
1239 uint32_t RESERVED14[1U];
1240 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
1241 uint32_t RESERVED15[1U];
1242 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
1243 uint32_t RESERVED16[1U];
1244 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
1245 uint32_t RESERVED17[1U];
1246 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
1247 uint32_t RESERVED18[1U];
1248 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
1249 uint32_t RESERVED19[1U];
1250 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
1251 uint32_t RESERVED20[1U];
1252 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
1253 uint32_t RESERVED21[1U];
1254 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
1255 uint32_t RESERVED22[1U];
1256 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
1257 uint32_t RESERVED23[1U];
1258 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
1259 uint32_t RESERVED24[1U];
1260 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
1261 uint32_t RESERVED25[1U];
1262 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
1263 uint32_t RESERVED26[1U];
1264 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
1265 uint32_t RESERVED27[1U];
1266 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
1267 uint32_t RESERVED28[1U];
1268 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
1269 uint32_t RESERVED29[1U];
1270 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
1271 uint32_t RESERVED30[1U];
1272 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
1273 uint32_t RESERVED31[1U];
1274 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
1275 uint32_t RESERVED32[934U];
1276 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1277 uint32_t RESERVED33[1U];
1278 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
1279} DWT_Type;
1280
1281/* DWT Control Register Definitions */
1282#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
1283#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1284
1285#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
1286#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1287
1288#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
1289#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1290
1291#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
1292#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1293
1294#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
1295#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1296
1297#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
1298#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
1299
1300#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
1301#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1302
1303#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
1304#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1305
1306#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
1307#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1308
1309#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
1310#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1311
1312#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
1313#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1314
1315#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
1316#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1317
1318#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
1319#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1320
1321#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
1322#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1323
1324#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
1325#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1326
1327#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
1328#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1329
1330#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
1331#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1332
1333#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
1334#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1335
1336#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
1337#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1338
1339/* DWT CPI Count Register Definitions */
1340#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1341#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1342
1343/* DWT Exception Overhead Count Register Definitions */
1344#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1345#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1346
1347/* DWT Sleep Count Register Definitions */
1348#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1349#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1350
1351/* DWT LSU Count Register Definitions */
1352#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1353#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1354
1355/* DWT Folded-instruction Count Register Definitions */
1356#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1357#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1358
1359/* DWT Comparator Function Register Definitions */
1360#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
1361#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
1362
1363#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1364#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1365
1366#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1367#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1368
1369#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
1370#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
1371
1372#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
1373#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
1374
1375/*@}*/ /* end of group CMSIS_DWT */
1376
1377
1378/**
1379 \ingroup CMSIS_core_register
1380 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1381 \brief Type definitions for the Trace Port Interface (TPI)
1382 @{
1383 */
1384
1385/**
1386 \brief Structure type to access the Trace Port Interface Register (TPI).
1387 */
1388typedef struct
1389{
1390 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
1391 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
1392 uint32_t RESERVED0[2U];
1393 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1394 uint32_t RESERVED1[55U];
1395 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1396 uint32_t RESERVED2[131U];
1397 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1398 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1399 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1400 uint32_t RESERVED3[759U];
1401 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
1402 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1403 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1404 uint32_t RESERVED4[1U];
1405 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1406 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1407 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1408 uint32_t RESERVED5[39U];
1409 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1410 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1411 uint32_t RESERVED7[8U];
1412 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1413 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1414} TPI_Type;
1415
1416/* TPI Asynchronous Clock Prescaler Register Definitions */
1417#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1418#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1419
1420/* TPI Selected Pin Protocol Register Definitions */
1421#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1422#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1423
1424/* TPI Formatter and Flush Status Register Definitions */
1425#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1426#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1427
1428#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1429#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1430
1431#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1432#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1433
1434#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1435#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1436
1437/* TPI Formatter and Flush Control Register Definitions */
1438#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1439#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1440
1441#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1442#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1443
1444/* TPI TRIGGER Register Definitions */
1445#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1446#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1447
1448/* TPI Integration ETM Data Register Definitions (FIFO0) */
1449#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1450#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1451
1452#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1453#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1454
1455#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1456#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1457
1458#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1459#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1460
1461#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1462#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1463
1464#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1465#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1466
1467#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1468#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1469
1470/* TPI ITATBCTR2 Register Definitions */
1471#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
1472#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
1473
1474/* TPI Integration ITM Data Register Definitions (FIFO1) */
1475#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1476#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1477
1478#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1479#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1480
1481#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1482#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1483
1484#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1485#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1486
1487#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1488#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1489
1490#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1491#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1492
1493#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1494#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1495
1496/* TPI ITATBCTR0 Register Definitions */
1497#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
1498#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
1499
1500/* TPI Integration Mode Control Register Definitions */
1501#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1502#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1503
1504/* TPI DEVID Register Definitions */
1505#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1506#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1507
1508#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1509#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1510
1511#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1512#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1513
1514#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1515#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1516
1517#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1518#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1519
1520#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1521#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1522
1523/* TPI DEVTYPE Register Definitions */
1524#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
1525#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1526
1527#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
1528#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1529
1530/*@}*/ /* end of group CMSIS_TPI */
1531
1532
1533#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1534/**
1535 \ingroup CMSIS_core_register
1536 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1537 \brief Type definitions for the Memory Protection Unit (MPU)
1538 @{
1539 */
1540
1541/**
1542 \brief Structure type to access the Memory Protection Unit (MPU).
1543 */
1544typedef struct
1545{
1546 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1547 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1548 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
1549 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1550 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
1551 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
1552 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
1553 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
1554 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
1555 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
1556 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
1557 uint32_t RESERVED0[1];
1558 union {
1559 __IOM uint32_t MAIR[2];
1560 struct {
1561 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
1562 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
1563 };
1564 };
1565} MPU_Type;
1566
1567#define MPU_TYPE_RALIASES 4U
1568
1569/* MPU Type Register Definitions */
1570#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1571#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1572
1573#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1574#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1575
1576#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1577#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1578
1579/* MPU Control Register Definitions */
1580#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1581#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1582
1583#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1584#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1585
1586#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1587#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1588
1589/* MPU Region Number Register Definitions */
1590#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1591#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1592
1593/* MPU Region Base Address Register Definitions */
1594#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1595#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1596
1597#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
1598#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
1599
1600#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
1601#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
1602
1603#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
1604#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
1605
1606/* MPU Region Limit Address Register Definitions */
1607#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
1608#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
1609
1610#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
1611#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
1612
1613#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
1614#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
1615
1616#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
1617#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
1618
1619/* MPU Memory Attribute Indirection Register 0 Definitions */
1620#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
1621#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
1622
1623#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
1624#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
1625
1626#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
1627#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
1628
1629#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
1630#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
1631
1632/* MPU Memory Attribute Indirection Register 1 Definitions */
1633#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
1634#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
1635
1636#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
1637#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
1638
1639#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
1640#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
1641
1642#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
1643#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
1644
1645/*@} end of group CMSIS_MPU */
1646#endif
1647
1648
1649#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1650/**
1651 \ingroup CMSIS_core_register
1652 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
1653 \brief Type definitions for the Security Attribution Unit (SAU)
1654 @{
1655 */
1656
1657/**
1658 \brief Structure type to access the Security Attribution Unit (SAU).
1659 */
1660typedef struct
1661{
1662 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
1663 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1664#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1665 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
1666 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
1667 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
1668#else
1669 uint32_t RESERVED0[3];
1670#endif
1671 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
1672 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
1673} SAU_Type;
1674
1675/* SAU Control Register Definitions */
1676#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
1677#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
1678
1679#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1680#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1681
1682/* SAU Type Register Definitions */
1683#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1684#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1685
1686#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1687/* SAU Region Number Register Definitions */
1688#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1689#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1690
1691/* SAU Region Base Address Register Definitions */
1692#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1693#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1694
1695/* SAU Region Limit Address Register Definitions */
1696#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1697#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1698
1699#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1700#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1701
1702#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1703#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1704
1705#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1706
1707/* Secure Fault Status Register Definitions */
1708#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
1709#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
1710
1711#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
1712#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
1713
1714#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
1715#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
1716
1717#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
1718#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
1719
1720#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
1721#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
1722
1723#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
1724#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
1725
1726#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
1727#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
1728
1729#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
1730#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
1731
1732/*@} end of group CMSIS_SAU */
1733#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1734
1735
1736/**
1737 \ingroup CMSIS_core_register
1738 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1739 \brief Type definitions for the Floating Point Unit (FPU)
1740 @{
1741 */
1742
1743/**
1744 \brief Structure type to access the Floating Point Unit (FPU).
1745 */
1746typedef struct
1747{
1748 uint32_t RESERVED0[1U];
1749 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1750 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1751 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1752 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1753 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1754} FPU_Type;
1755
1756/* Floating-Point Context Control Register Definitions */
1757#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1758#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1759
1760#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1761#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1762
1763#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
1764#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
1765
1766#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
1767#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
1768
1769#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
1770#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
1771
1772#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
1773#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
1774
1775#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
1776#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
1777
1778#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
1779#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
1780
1781#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1782#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1783
1784#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
1785#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
1786
1787#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1788#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1789
1790#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1791#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1792
1793#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1794#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1795
1796#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1797#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1798
1799#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
1800#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
1801
1802#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1803#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1804
1805#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1806#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1807
1808/* Floating-Point Context Address Register Definitions */
1809#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1810#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1811
1812/* Floating-Point Default Status Control Register Definitions */
1813#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1814#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1815
1816#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1817#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1818
1819#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1820#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1821
1822#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1823#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1824
1825/* Media and FP Feature Register 0 Definitions */
1826#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1827#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1828
1829#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1830#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1831
1832#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1833#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1834
1835#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1836#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1837
1838#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1839#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1840
1841#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1842#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1843
1844#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1845#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1846
1847#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1848#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1849
1850/* Media and FP Feature Register 1 Definitions */
1851#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1852#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1853
1854#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1855#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1856
1857#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1858#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1859
1860#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1861#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1862
1863/*@} end of group CMSIS_FPU */
1864
1865
1866/**
1867 \ingroup CMSIS_core_register
1868 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1869 \brief Type definitions for the Core Debug Registers
1870 @{
1871 */
1872
1873/**
1874 \brief Structure type to access the Core Debug Register (CoreDebug).
1875 */
1876typedef struct
1877{
1878 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1879 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1880 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1881 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1882 uint32_t RESERVED4[1U];
1883 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1884 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1885} CoreDebug_Type;
1886
1887/* Debug Halting Control and Status Register Definitions */
1888#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1889#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1890
1891#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
1892#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
1893
1894#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1895#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1896
1897#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1898#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1899
1900#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1901#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1902
1903#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1904#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1905
1906#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1907#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1908
1909#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1910#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1911
1912#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1913#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1914
1915#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1916#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1917
1918#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1919#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1920
1921#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1922#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1923
1924#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1925#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1926
1927/* Debug Core Register Selector Register Definitions */
1928#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1929#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1930
1931#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1932#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1933
1934/* Debug Exception and Monitor Control Register Definitions */
1935#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1936#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1937
1938#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1939#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1940
1941#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1942#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1943
1944#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1945#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1946
1947#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1948#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1949
1950#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1951#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1952
1953#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1954#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1955
1956#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1957#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1958
1959#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1960#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1961
1962#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1963#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1964
1965#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1966#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1967
1968#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1969#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1970
1971#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1972#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1973
1974/* Debug Authentication Control Register Definitions */
1975#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
1976#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
1977
1978#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
1979#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
1980
1981#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
1982#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
1983
1984#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
1985#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
1986
1987/* Debug Security Control and Status Register Definitions */
1988#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
1989#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
1990
1991#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
1992#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
1993
1994#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
1995#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
1996
1997/*@} end of group CMSIS_CoreDebug */
1998
1999
2000/**
2001 \ingroup CMSIS_core_register
2002 \defgroup CMSIS_core_bitfield Core register bit field macros
2003 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
2004 @{
2005 */
2006
2007/**
2008 \brief Mask and shift a bit field value for use in a register bit range.
2009 \param[in] field Name of the register bit field.
2010 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
2011 \return Masked and shifted value.
2012*/
2013#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2014
2015/**
2016 \brief Mask and shift a register value to extract a bit filed value.
2017 \param[in] field Name of the register bit field.
2018 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
2019 \return Masked and shifted bit field value.
2020*/
2021#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2022
2023/*@} end of group CMSIS_core_bitfield */
2024
2025
2026/**
2027 \ingroup CMSIS_core_register
2028 \defgroup CMSIS_core_base Core Definitions
2029 \brief Definitions for base addresses, unions, and structures.
2030 @{
2031 */
2032
2033/* Memory mapping of Core Hardware */
2034 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
2035 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
2036 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
2037 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
2038 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
2039 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
2040 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
2041 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
2042
2043 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
2044 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
2045 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
2046 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
2047 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
2048 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
2049 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
2050 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
2051
2052 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2053 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
2054 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
2055 #endif
2056
2057 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2058 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
2059 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
2060 #endif
2061
2062 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
2063 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
2064
2065#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2066 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
2067 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
2068 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
2069 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
2070 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
2071
2072 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
2073 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
2074 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
2075 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
2076 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
2077
2078 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2079 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
2080 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
2081 #endif
2082
2083 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
2084 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
2085
2086#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2087/*@} */
2088
2089
2090
2091/*******************************************************************************
2092 * Hardware Abstraction Layer
2093 Core Function Interface contains:
2094 - Core NVIC Functions
2095 - Core SysTick Functions
2096 - Core Debug Functions
2097 - Core Register Access Functions
2098 ******************************************************************************/
2099/**
2100 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
2101*/
2102
2103
2104
2105/* ########################## NVIC functions #################################### */
2106/**
2107 \ingroup CMSIS_Core_FunctionInterface
2108 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
2109 \brief Functions that manage interrupts and exceptions via the NVIC.
2110 @{
2111 */
2112
2113#ifdef CMSIS_NVIC_VIRTUAL
2114 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2115 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2116 #endif
2117 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2118#else
2119 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2120 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2121 #define NVIC_EnableIRQ __NVIC_EnableIRQ
2122 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2123 #define NVIC_DisableIRQ __NVIC_DisableIRQ
2124 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2125 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2126 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2127 #define NVIC_GetActive __NVIC_GetActive
2128 #define NVIC_SetPriority __NVIC_SetPriority
2129 #define NVIC_GetPriority __NVIC_GetPriority
2130 #define NVIC_SystemReset __NVIC_SystemReset
2131#endif /* CMSIS_NVIC_VIRTUAL */
2132
2133#ifdef CMSIS_VECTAB_VIRTUAL
2134 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2135 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2136 #endif
2137 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2138#else
2139 #define NVIC_SetVector __NVIC_SetVector
2140 #define NVIC_GetVector __NVIC_GetVector
2141#endif /* (CMSIS_VECTAB_VIRTUAL) */
2142
2143#define NVIC_USER_IRQ_OFFSET 16
2144
2145
2146
2147/**
2148 \brief Set Priority Grouping
2149 \details Sets the priority grouping field using the required unlock sequence.
2150 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2151 Only values from 0..7 are used.
2152 In case of a conflict between priority grouping and available
2153 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2154 \param [in] PriorityGroup Priority grouping field.
2155 */
2156__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2157{
2158 uint32_t reg_value;
2159 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2160
2161 reg_value = SCB->AIRCR; /* read old register configuration */
2162 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2163 reg_value = (reg_value |
2164 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2165 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
2166 SCB->AIRCR = reg_value;
2167}
2168
2169
2170/**
2171 \brief Get Priority Grouping
2172 \details Reads the priority grouping field from the NVIC Interrupt Controller.
2173 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2174 */
2175__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2176{
2177 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2178}
2179
2180
2181/**
2182 \brief Enable Interrupt
2183 \details Enables a device specific interrupt in the NVIC interrupt controller.
2184 \param [in] IRQn Device specific interrupt number.
2185 \note IRQn must not be negative.
2186 */
2187__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2188{
2189 if ((int32_t)(IRQn) >= 0)
2190 {
2191 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2192 }
2193}
2194
2195
2196/**
2197 \brief Get Interrupt Enable status
2198 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
2199 \param [in] IRQn Device specific interrupt number.
2200 \return 0 Interrupt is not enabled.
2201 \return 1 Interrupt is enabled.
2202 \note IRQn must not be negative.
2203 */
2204__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2205{
2206 if ((int32_t)(IRQn) >= 0)
2207 {
2208 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2209 }
2210 else
2211 {
2212 return(0U);
2213 }
2214}
2215
2216
2217/**
2218 \brief Disable Interrupt
2219 \details Disables a device specific interrupt in the NVIC interrupt controller.
2220 \param [in] IRQn Device specific interrupt number.
2221 \note IRQn must not be negative.
2222 */
2223__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2224{
2225 if ((int32_t)(IRQn) >= 0)
2226 {
2227 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2228 __DSB();
2229 __ISB();
2230 }
2231}
2232
2233
2234/**
2235 \brief Get Pending Interrupt
2236 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
2237 \param [in] IRQn Device specific interrupt number.
2238 \return 0 Interrupt status is not pending.
2239 \return 1 Interrupt status is pending.
2240 \note IRQn must not be negative.
2241 */
2242__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2243{
2244 if ((int32_t)(IRQn) >= 0)
2245 {
2246 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2247 }
2248 else
2249 {
2250 return(0U);
2251 }
2252}
2253
2254
2255/**
2256 \brief Set Pending Interrupt
2257 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
2258 \param [in] IRQn Device specific interrupt number.
2259 \note IRQn must not be negative.
2260 */
2261__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2262{
2263 if ((int32_t)(IRQn) >= 0)
2264 {
2265 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2266 }
2267}
2268
2269
2270/**
2271 \brief Clear Pending Interrupt
2272 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
2273 \param [in] IRQn Device specific interrupt number.
2274 \note IRQn must not be negative.
2275 */
2276__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2277{
2278 if ((int32_t)(IRQn) >= 0)
2279 {
2280 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2281 }
2282}
2283
2284
2285/**
2286 \brief Get Active Interrupt
2287 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2288 \param [in] IRQn Device specific interrupt number.
2289 \return 0 Interrupt status is not active.
2290 \return 1 Interrupt status is active.
2291 \note IRQn must not be negative.
2292 */
2293__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2294{
2295 if ((int32_t)(IRQn) >= 0)
2296 {
2297 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2298 }
2299 else
2300 {
2301 return(0U);
2302 }
2303}
2304
2305
2306#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2307/**
2308 \brief Get Interrupt Target State
2309 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2310 \param [in] IRQn Device specific interrupt number.
2311 \return 0 if interrupt is assigned to Secure
2312 \return 1 if interrupt is assigned to Non Secure
2313 \note IRQn must not be negative.
2314 */
2315__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2316{
2317 if ((int32_t)(IRQn) >= 0)
2318 {
2319 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2320 }
2321 else
2322 {
2323 return(0U);
2324 }
2325}
2326
2327
2328/**
2329 \brief Set Interrupt Target State
2330 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2331 \param [in] IRQn Device specific interrupt number.
2332 \return 0 if interrupt is assigned to Secure
2333 1 if interrupt is assigned to Non Secure
2334 \note IRQn must not be negative.
2335 */
2336__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2337{
2338 if ((int32_t)(IRQn) >= 0)
2339 {
2340 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2341 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2342 }
2343 else
2344 {
2345 return(0U);
2346 }
2347}
2348
2349
2350/**
2351 \brief Clear Interrupt Target State
2352 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2353 \param [in] IRQn Device specific interrupt number.
2354 \return 0 if interrupt is assigned to Secure
2355 1 if interrupt is assigned to Non Secure
2356 \note IRQn must not be negative.
2357 */
2358__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2359{
2360 if ((int32_t)(IRQn) >= 0)
2361 {
2362 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2363 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2364 }
2365 else
2366 {
2367 return(0U);
2368 }
2369}
2370#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2371
2372
2373/**
2374 \brief Set Interrupt Priority
2375 \details Sets the priority of a device specific interrupt or a processor exception.
2376 The interrupt number can be positive to specify a device specific interrupt,
2377 or negative to specify a processor exception.
2378 \param [in] IRQn Interrupt number.
2379 \param [in] priority Priority to set.
2380 \note The priority cannot be set for every processor exception.
2381 */
2382__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2383{
2384 if ((int32_t)(IRQn) >= 0)
2385 {
2386 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2387 }
2388 else
2389 {
2390 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2391 }
2392}
2393
2394
2395/**
2396 \brief Get Interrupt Priority
2397 \details Reads the priority of a device specific interrupt or a processor exception.
2398 The interrupt number can be positive to specify a device specific interrupt,
2399 or negative to specify a processor exception.
2400 \param [in] IRQn Interrupt number.
2401 \return Interrupt Priority.
2402 Value is aligned automatically to the implemented priority bits of the microcontroller.
2403 */
2404__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2405{
2406
2407 if ((int32_t)(IRQn) >= 0)
2408 {
2409 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2410 }
2411 else
2412 {
2413 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2414 }
2415}
2416
2417
2418/**
2419 \brief Encode Priority
2420 \details Encodes the priority for an interrupt with the given priority group,
2421 preemptive priority value, and subpriority value.
2422 In case of a conflict between priority grouping and available
2423 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2424 \param [in] PriorityGroup Used priority group.
2425 \param [in] PreemptPriority Preemptive priority value (starting from 0).
2426 \param [in] SubPriority Subpriority value (starting from 0).
2427 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2428 */
2429__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2430{
2431 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2432 uint32_t PreemptPriorityBits;
2433 uint32_t SubPriorityBits;
2434
2435 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2436 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2437
2438 return (
2439 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2440 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2441 );
2442}
2443
2444
2445/**
2446 \brief Decode Priority
2447 \details Decodes an interrupt priority value with a given priority group to
2448 preemptive priority value and subpriority value.
2449 In case of a conflict between priority grouping and available
2450 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2451 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2452 \param [in] PriorityGroup Used priority group.
2453 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
2454 \param [out] pSubPriority Subpriority value (starting from 0).
2455 */
2456__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2457{
2458 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2459 uint32_t PreemptPriorityBits;
2460 uint32_t SubPriorityBits;
2461
2462 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2463 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2464
2465 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2466 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2467}
2468
2469
2470/**
2471 \brief Set Interrupt Vector
2472 \details Sets an interrupt vector in SRAM based interrupt vector table.
2473 The interrupt number can be positive to specify a device specific interrupt,
2474 or negative to specify a processor exception.
2475 VTOR must been relocated to SRAM before.
2476 \param [in] IRQn Interrupt number
2477 \param [in] vector Address of interrupt handler function
2478 */
2479__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2480{
2481 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2482 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2483 __DSB();
2484}
2485
2486
2487/**
2488 \brief Get Interrupt Vector
2489 \details Reads an interrupt vector from interrupt vector table.
2490 The interrupt number can be positive to specify a device specific interrupt,
2491 or negative to specify a processor exception.
2492 \param [in] IRQn Interrupt number.
2493 \return Address of interrupt handler function
2494 */
2495__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2496{
2497 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2498 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2499}
2500
2501
2502/**
2503 \brief System Reset
2504 \details Initiates a system reset request to reset the MCU.
2505 */
2506__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2507{
2508 __DSB(); /* Ensure all outstanding memory accesses included
2509 buffered write are completed before reset */
2510 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2511 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2512 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2513 __DSB(); /* Ensure completion of memory access */
2514
2515 for(;;) /* wait until reset */
2516 {
2517 __NOP();
2518 }
2519}
2520
2521#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2522/**
2523 \brief Set Priority Grouping (non-secure)
2524 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
2525 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2526 Only values from 0..7 are used.
2527 In case of a conflict between priority grouping and available
2528 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2529 \param [in] PriorityGroup Priority grouping field.
2530 */
2531__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2532{
2533 uint32_t reg_value;
2534 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2535
2536 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2537 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2538 reg_value = (reg_value |
2539 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2540 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
2541 SCB_NS->AIRCR = reg_value;
2542}
2543
2544
2545/**
2546 \brief Get Priority Grouping (non-secure)
2547 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
2548 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2549 */
2550__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2551{
2552 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2553}
2554
2555
2556/**
2557 \brief Enable Interrupt (non-secure)
2558 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2559 \param [in] IRQn Device specific interrupt number.
2560 \note IRQn must not be negative.
2561 */
2562__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2563{
2564 if ((int32_t)(IRQn) >= 0)
2565 {
2566 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2567 }
2568}
2569
2570
2571/**
2572 \brief Get Interrupt Enable status (non-secure)
2573 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
2574 \param [in] IRQn Device specific interrupt number.
2575 \return 0 Interrupt is not enabled.
2576 \return 1 Interrupt is enabled.
2577 \note IRQn must not be negative.
2578 */
2579__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2580{
2581 if ((int32_t)(IRQn) >= 0)
2582 {
2583 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2584 }
2585 else
2586 {
2587 return(0U);
2588 }
2589}
2590
2591
2592/**
2593 \brief Disable Interrupt (non-secure)
2594 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2595 \param [in] IRQn Device specific interrupt number.
2596 \note IRQn must not be negative.
2597 */
2598__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2599{
2600 if ((int32_t)(IRQn) >= 0)
2601 {
2602 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2603 }
2604}
2605
2606
2607/**
2608 \brief Get Pending Interrupt (non-secure)
2609 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
2610 \param [in] IRQn Device specific interrupt number.
2611 \return 0 Interrupt status is not pending.
2612 \return 1 Interrupt status is pending.
2613 \note IRQn must not be negative.
2614 */
2615__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2616{
2617 if ((int32_t)(IRQn) >= 0)
2618 {
2619 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2620 }
2621 else
2622 {
2623 return(0U);
2624 }
2625}
2626
2627
2628/**
2629 \brief Set Pending Interrupt (non-secure)
2630 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2631 \param [in] IRQn Device specific interrupt number.
2632 \note IRQn must not be negative.
2633 */
2634__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2635{
2636 if ((int32_t)(IRQn) >= 0)
2637 {
2638 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2639 }
2640}
2641
2642
2643/**
2644 \brief Clear Pending Interrupt (non-secure)
2645 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2646 \param [in] IRQn Device specific interrupt number.
2647 \note IRQn must not be negative.
2648 */
2649__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2650{
2651 if ((int32_t)(IRQn) >= 0)
2652 {
2653 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2654 }
2655}
2656
2657
2658/**
2659 \brief Get Active Interrupt (non-secure)
2660 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
2661 \param [in] IRQn Device specific interrupt number.
2662 \return 0 Interrupt status is not active.
2663 \return 1 Interrupt status is active.
2664 \note IRQn must not be negative.
2665 */
2666__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2667{
2668 if ((int32_t)(IRQn) >= 0)
2669 {
2670 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2671 }
2672 else
2673 {
2674 return(0U);
2675 }
2676}
2677
2678
2679/**
2680 \brief Set Interrupt Priority (non-secure)
2681 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2682 The interrupt number can be positive to specify a device specific interrupt,
2683 or negative to specify a processor exception.
2684 \param [in] IRQn Interrupt number.
2685 \param [in] priority Priority to set.
2686 \note The priority cannot be set for every non-secure processor exception.
2687 */
2688__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2689{
2690 if ((int32_t)(IRQn) >= 0)
2691 {
2692 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2693 }
2694 else
2695 {
2696 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2697 }
2698}
2699
2700
2701/**
2702 \brief Get Interrupt Priority (non-secure)
2703 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2704 The interrupt number can be positive to specify a device specific interrupt,
2705 or negative to specify a processor exception.
2706 \param [in] IRQn Interrupt number.
2707 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
2708 */
2709__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2710{
2711
2712 if ((int32_t)(IRQn) >= 0)
2713 {
2714 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2715 }
2716 else
2717 {
2718 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2719 }
2720}
2721#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2722
2723/*@} end of CMSIS_Core_NVICFunctions */
2724
2725/* ########################## MPU functions #################################### */
2726
2727#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2728
2729#include "mpu_armv8.h"
2730
2731#endif
2732
2733/* ########################## FPU functions #################################### */
2734/**
2735 \ingroup CMSIS_Core_FunctionInterface
2736 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2737 \brief Function that provides FPU type.
2738 @{
2739 */
2740
2741/**
2742 \brief get FPU type
2743 \details returns the FPU type
2744 \returns
2745 - \b 0: No FPU
2746 - \b 1: Single precision FPU
2747 - \b 2: Double + Single precision FPU
2748 */
2749__STATIC_INLINE uint32_t SCB_GetFPUType(void)
2750{
2751 uint32_t mvfr0;
2752
2753 mvfr0 = FPU->MVFR0;
2754 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2755 {
2756 return 2U; /* Double + Single precision FPU */
2757 }
2758 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2759 {
2760 return 1U; /* Single precision FPU */
2761 }
2762 else
2763 {
2764 return 0U; /* No FPU */
2765 }
2766}
2767
2768
2769/*@} end of CMSIS_Core_FpuFunctions */
2770
2771
2772
2773/* ########################## SAU functions #################################### */
2774/**
2775 \ingroup CMSIS_Core_FunctionInterface
2776 \defgroup CMSIS_Core_SAUFunctions SAU Functions
2777 \brief Functions that configure the SAU.
2778 @{
2779 */
2780
2781#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2782
2783/**
2784 \brief Enable SAU
2785 \details Enables the Security Attribution Unit (SAU).
2786 */
2787__STATIC_INLINE void TZ_SAU_Enable(void)
2788{
2789 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2790}
2791
2792
2793
2794/**
2795 \brief Disable SAU
2796 \details Disables the Security Attribution Unit (SAU).
2797 */
2798__STATIC_INLINE void TZ_SAU_Disable(void)
2799{
2800 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2801}
2802
2803#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2804
2805/*@} end of CMSIS_Core_SAUFunctions */
2806
2807
2808
2809
2810/* ################################## SysTick function ############################################ */
2811/**
2812 \ingroup CMSIS_Core_FunctionInterface
2813 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2814 \brief Functions that configure the System.
2815 @{
2816 */
2817
2818#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2819
2820/**
2821 \brief System Tick Configuration
2822 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2823 Counter is in free running mode to generate periodic interrupts.
2824 \param [in] ticks Number of ticks between two interrupts.
2825 \return 0 Function succeeded.
2826 \return 1 Function failed.
2827 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2828 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2829 must contain a vendor-specific implementation of this function.
2830 */
2831__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2832{
2833 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2834 {
2835 return (1UL); /* Reload value impossible */
2836 }
2837
2838 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2839 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2840 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2841 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2842 SysTick_CTRL_TICKINT_Msk |
2843 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2844 return (0UL); /* Function successful */
2845}
2846
2847#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2848/**
2849 \brief System Tick Configuration (non-secure)
2850 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
2851 Counter is in free running mode to generate periodic interrupts.
2852 \param [in] ticks Number of ticks between two interrupts.
2853 \return 0 Function succeeded.
2854 \return 1 Function failed.
2855 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2856 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
2857 must contain a vendor-specific implementation of this function.
2858
2859 */
2860__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2861{
2862 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2863 {
2864 return (1UL); /* Reload value impossible */
2865 }
2866
2867 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2868 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2869 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2870 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2871 SysTick_CTRL_TICKINT_Msk |
2872 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2873 return (0UL); /* Function successful */
2874}
2875#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2876
2877#endif
2878
2879/*@} end of CMSIS_Core_SysTickFunctions */
2880
2881
2882
2883/* ##################################### Debug In/Output function ########################################### */
2884/**
2885 \ingroup CMSIS_Core_FunctionInterface
2886 \defgroup CMSIS_core_DebugFunctions ITM Functions
2887 \brief Functions that access the ITM debug interface.
2888 @{
2889 */
2890
2891extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2892#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2893
2894
2895/**
2896 \brief ITM Send Character
2897 \details Transmits a character via the ITM channel 0, and
2898 \li Just returns when no debugger is connected that has booked the output.
2899 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2900 \param [in] ch Character to transmit.
2901 \returns Character to transmit.
2902 */
2903__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2904{
2905 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2906 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2907 {
2908 while (ITM->PORT[0U].u32 == 0UL)
2909 {
2910 __NOP();
2911 }
2912 ITM->PORT[0U].u8 = (uint8_t)ch;
2913 }
2914 return (ch);
2915}
2916
2917
2918/**
2919 \brief ITM Receive Character
2920 \details Inputs a character via the external variable \ref ITM_RxBuffer.
2921 \return Received character.
2922 \return -1 No character pending.
2923 */
2924__STATIC_INLINE int32_t ITM_ReceiveChar (void)
2925{
2926 int32_t ch = -1; /* no character available */
2927
2928 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2929 {
2930 ch = ITM_RxBuffer;
2931 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2932 }
2933
2934 return (ch);
2935}
2936
2937
2938/**
2939 \brief ITM Check Character
2940 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2941 \return 0 No character available.
2942 \return 1 Character available.
2943 */
2944__STATIC_INLINE int32_t ITM_CheckChar (void)
2945{
2946
2947 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2948 {
2949 return (0); /* no character available */
2950 }
2951 else
2952 {
2953 return (1); /* character available */
2954 }
2955}
2956
2957/*@} end of CMSIS_core_DebugFunctions */
2958
2959
2960
2961
2962#ifdef __cplusplus
2963}
2964#endif
2965
2966#endif /* __CORE_ARMV81MML_H_DEPENDANT */
2967
2968#endif /* __CMSIS_GENERIC */
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