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1/**************************************************************************//**
2 * @file core_cm23.h
3 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
4 * @version V5.0.8
5 * @date 12. November 2018
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_CM23_H_GENERIC
32#define __CORE_CM23_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
40/**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58/**
59 \ingroup Cortex_M23
60 @{
61 */
62
63#include "cmsis_version.h"
64
65/* CMSIS definitions */
66#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
69 __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71#define __CORTEX_M (23U) /*!< Cortex-M Core */
72
73/** __FPU_USED indicates whether an FPU is used or not.
74 This core does not support an FPU at all
75*/
76#define __FPU_USED 0U
77
78#if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81 #endif
82
83#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_FP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86 #endif
87
88#elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91 #endif
92
93#elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #endif
97
98#elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101 #endif
102
103#elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #endif
107
108#elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111 #endif
112
113#endif
114
115#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
116
117
118#ifdef __cplusplus
119}
120#endif
121
122#endif /* __CORE_CM23_H_GENERIC */
123
124#ifndef __CMSIS_GENERIC
125
126#ifndef __CORE_CM23_H_DEPENDANT
127#define __CORE_CM23_H_DEPENDANT
128
129#ifdef __cplusplus
130 extern "C" {
131#endif
132
133/* check device defines and use defaults */
134#if defined __CHECK_DEVICE_DEFINES
135 #ifndef __CM23_REV
136 #define __CM23_REV 0x0000U
137 #warning "__CM23_REV not defined in device header file; using default!"
138 #endif
139
140 #ifndef __FPU_PRESENT
141 #define __FPU_PRESENT 0U
142 #warning "__FPU_PRESENT not defined in device header file; using default!"
143 #endif
144
145 #ifndef __MPU_PRESENT
146 #define __MPU_PRESENT 0U
147 #warning "__MPU_PRESENT not defined in device header file; using default!"
148 #endif
149
150 #ifndef __SAUREGION_PRESENT
151 #define __SAUREGION_PRESENT 0U
152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
153 #endif
154
155 #ifndef __VTOR_PRESENT
156 #define __VTOR_PRESENT 0U
157 #warning "__VTOR_PRESENT not defined in device header file; using default!"
158 #endif
159
160 #ifndef __NVIC_PRIO_BITS
161 #define __NVIC_PRIO_BITS 2U
162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
163 #endif
164
165 #ifndef __Vendor_SysTickConfig
166 #define __Vendor_SysTickConfig 0U
167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
168 #endif
169
170 #ifndef __ETM_PRESENT
171 #define __ETM_PRESENT 0U
172 #warning "__ETM_PRESENT not defined in device header file; using default!"
173 #endif
174
175 #ifndef __MTB_PRESENT
176 #define __MTB_PRESENT 0U
177 #warning "__MTB_PRESENT not defined in device header file; using default!"
178 #endif
179
180#endif
181
182/* IO definitions (access restrictions to peripheral registers) */
183/**
184 \defgroup CMSIS_glob_defs CMSIS Global Defines
185
186 <strong>IO Type Qualifiers</strong> are used
187 \li to specify the access to peripheral variables.
188 \li for automatic generation of peripheral register debug information.
189*/
190#ifdef __cplusplus
191 #define __I volatile /*!< Defines 'read only' permissions */
192#else
193 #define __I volatile const /*!< Defines 'read only' permissions */
194#endif
195#define __O volatile /*!< Defines 'write only' permissions */
196#define __IO volatile /*!< Defines 'read / write' permissions */
197
198/* following defines should be used for structure members */
199#define __IM volatile const /*! Defines 'read only' structure member permissions */
200#define __OM volatile /*! Defines 'write only' structure member permissions */
201#define __IOM volatile /*! Defines 'read / write' structure member permissions */
202
203/*@} end of group Cortex_M23 */
204
205
206
207/*******************************************************************************
208 * Register Abstraction
209 Core Register contain:
210 - Core Register
211 - Core NVIC Register
212 - Core SCB Register
213 - Core SysTick Register
214 - Core Debug Register
215 - Core MPU Register
216 - Core SAU Register
217 ******************************************************************************/
218/**
219 \defgroup CMSIS_core_register Defines and Type Definitions
220 \brief Type definitions and defines for Cortex-M processor based devices.
221*/
222
223/**
224 \ingroup CMSIS_core_register
225 \defgroup CMSIS_CORE Status and Control Registers
226 \brief Core Register type definitions.
227 @{
228 */
229
230/**
231 \brief Union type to access the Application Program Status Register (APSR).
232 */
233typedef union
234{
235 struct
236 {
237 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
242 } b; /*!< Structure used for bit access */
243 uint32_t w; /*!< Type used for word access */
244} APSR_Type;
245
246/* APSR Register Definitions */
247#define APSR_N_Pos 31U /*!< APSR: N Position */
248#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
249
250#define APSR_Z_Pos 30U /*!< APSR: Z Position */
251#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
252
253#define APSR_C_Pos 29U /*!< APSR: C Position */
254#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
255
256#define APSR_V_Pos 28U /*!< APSR: V Position */
257#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
258
259
260/**
261 \brief Union type to access the Interrupt Program Status Register (IPSR).
262 */
263typedef union
264{
265 struct
266 {
267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
268 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
269 } b; /*!< Structure used for bit access */
270 uint32_t w; /*!< Type used for word access */
271} IPSR_Type;
272
273/* IPSR Register Definitions */
274#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
275#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
276
277
278/**
279 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
280 */
281typedef union
282{
283 struct
284 {
285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
293 } b; /*!< Structure used for bit access */
294 uint32_t w; /*!< Type used for word access */
295} xPSR_Type;
296
297/* xPSR Register Definitions */
298#define xPSR_N_Pos 31U /*!< xPSR: N Position */
299#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
300
301#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
302#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
303
304#define xPSR_C_Pos 29U /*!< xPSR: C Position */
305#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
306
307#define xPSR_V_Pos 28U /*!< xPSR: V Position */
308#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
309
310#define xPSR_T_Pos 24U /*!< xPSR: T Position */
311#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
312
313#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
314#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
315
316
317/**
318 \brief Union type to access the Control Registers (CONTROL).
319 */
320typedef union
321{
322 struct
323 {
324 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
325 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
326 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
327 } b; /*!< Structure used for bit access */
328 uint32_t w; /*!< Type used for word access */
329} CONTROL_Type;
330
331/* CONTROL Register Definitions */
332#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
333#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
334
335#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
336#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
337
338/*@} end of group CMSIS_CORE */
339
340
341/**
342 \ingroup CMSIS_core_register
343 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
344 \brief Type definitions for the NVIC Registers
345 @{
346 */
347
348/**
349 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
350 */
351typedef struct
352{
353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
354 uint32_t RESERVED0[16U];
355 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
356 uint32_t RSERVED1[16U];
357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
358 uint32_t RESERVED2[16U];
359 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
360 uint32_t RESERVED3[16U];
361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
362 uint32_t RESERVED4[16U];
363 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
364 uint32_t RESERVED5[16U];
365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
366} NVIC_Type;
367
368/*@} end of group CMSIS_NVIC */
369
370
371/**
372 \ingroup CMSIS_core_register
373 \defgroup CMSIS_SCB System Control Block (SCB)
374 \brief Type definitions for the System Control Block Registers
375 @{
376 */
377
378/**
379 \brief Structure type to access the System Control Block (SCB).
380 */
381typedef struct
382{
383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
384 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
385#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
387#else
388 uint32_t RESERVED0;
389#endif
390 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
391 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
392 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
393 uint32_t RESERVED1;
394 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
395 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
396} SCB_Type;
397
398/* SCB CPUID Register Definitions */
399#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
400#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
401
402#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
403#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
404
405#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
406#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
407
408#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
409#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
410
411#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
412#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
413
414/* SCB Interrupt Control State Register Definitions */
415#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
416#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
417
418#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
419#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
420
421#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
422#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
423
424#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
425#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
426
427#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
428#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
429
430#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
431#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
432
433#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
434#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
435
436#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
437#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
438
439#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
440#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
441
442#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
443#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
444
445#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
446#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
447
448#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
449#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
450
451#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
452#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
453
454#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
455/* SCB Vector Table Offset Register Definitions */
456#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
457#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
458#endif
459
460/* SCB Application Interrupt and Reset Control Register Definitions */
461#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
462#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
463
464#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
465#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
466
467#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
468#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
469
470#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
471#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
472
473#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
474#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
475
476#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
477#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
478
479#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
480#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
481
482#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
483#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
484
485/* SCB System Control Register Definitions */
486#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
487#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
488
489#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
490#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
491
492#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
493#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
494
495#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
496#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
497
498/* SCB Configuration Control Register Definitions */
499#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
500#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
501
502#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
503#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
504
505#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
506#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
507
508#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
509#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
510
511#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
512#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
513
514#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
515#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
516
517#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
518#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
519
520#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
521#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
522
523/* SCB System Handler Control and State Register Definitions */
524#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
525#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
526
527#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
528#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
529
530#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
531#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
532
533#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
534#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
535
536#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
537#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
538
539#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
540#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
541
542#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
543#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
544
545/*@} end of group CMSIS_SCB */
546
547
548/**
549 \ingroup CMSIS_core_register
550 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
551 \brief Type definitions for the System Timer Registers.
552 @{
553 */
554
555/**
556 \brief Structure type to access the System Timer (SysTick).
557 */
558typedef struct
559{
560 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
561 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
562 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
563 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
564} SysTick_Type;
565
566/* SysTick Control / Status Register Definitions */
567#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
568#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
569
570#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
571#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
572
573#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
574#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
575
576#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
577#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
578
579/* SysTick Reload Register Definitions */
580#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
581#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
582
583/* SysTick Current Register Definitions */
584#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
585#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
586
587/* SysTick Calibration Register Definitions */
588#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
589#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
590
591#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
592#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
593
594#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
595#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
596
597/*@} end of group CMSIS_SysTick */
598
599
600/**
601 \ingroup CMSIS_core_register
602 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
603 \brief Type definitions for the Data Watchpoint and Trace (DWT)
604 @{
605 */
606
607/**
608 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
609 */
610typedef struct
611{
612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
613 uint32_t RESERVED0[6U];
614 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
615 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
616 uint32_t RESERVED1[1U];
617 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
618 uint32_t RESERVED2[1U];
619 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
620 uint32_t RESERVED3[1U];
621 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
622 uint32_t RESERVED4[1U];
623 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
624 uint32_t RESERVED5[1U];
625 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
626 uint32_t RESERVED6[1U];
627 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
628 uint32_t RESERVED7[1U];
629 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
630 uint32_t RESERVED8[1U];
631 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
632 uint32_t RESERVED9[1U];
633 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
634 uint32_t RESERVED10[1U];
635 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
636 uint32_t RESERVED11[1U];
637 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
638 uint32_t RESERVED12[1U];
639 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
640 uint32_t RESERVED13[1U];
641 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
642 uint32_t RESERVED14[1U];
643 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
644 uint32_t RESERVED15[1U];
645 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
646 uint32_t RESERVED16[1U];
647 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
648 uint32_t RESERVED17[1U];
649 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
650 uint32_t RESERVED18[1U];
651 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
652 uint32_t RESERVED19[1U];
653 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
654 uint32_t RESERVED20[1U];
655 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
656 uint32_t RESERVED21[1U];
657 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
658 uint32_t RESERVED22[1U];
659 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
660 uint32_t RESERVED23[1U];
661 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
662 uint32_t RESERVED24[1U];
663 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
664 uint32_t RESERVED25[1U];
665 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
666 uint32_t RESERVED26[1U];
667 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
668 uint32_t RESERVED27[1U];
669 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
670 uint32_t RESERVED28[1U];
671 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
672 uint32_t RESERVED29[1U];
673 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
674 uint32_t RESERVED30[1U];
675 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
676 uint32_t RESERVED31[1U];
677 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
678} DWT_Type;
679
680/* DWT Control Register Definitions */
681#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
682#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
683
684#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
685#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
686
687#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
688#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
689
690#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
691#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
692
693#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
694#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
695
696/* DWT Comparator Function Register Definitions */
697#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
698#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
699
700#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
701#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
702
703#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
704#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
705
706#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
707#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
708
709#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
710#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
711
712/*@}*/ /* end of group CMSIS_DWT */
713
714
715/**
716 \ingroup CMSIS_core_register
717 \defgroup CMSIS_TPI Trace Port Interface (TPI)
718 \brief Type definitions for the Trace Port Interface (TPI)
719 @{
720 */
721
722/**
723 \brief Structure type to access the Trace Port Interface Register (TPI).
724 */
725typedef struct
726{
727 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
728 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
729 uint32_t RESERVED0[2U];
730 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
731 uint32_t RESERVED1[55U];
732 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
733 uint32_t RESERVED2[131U];
734 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
735 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
736 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
737 uint32_t RESERVED3[759U];
738 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
739 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
740 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
741 uint32_t RESERVED4[1U];
742 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
743 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
744 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
745 uint32_t RESERVED5[39U];
746 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
747 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
748 uint32_t RESERVED7[8U];
749 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
750 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
751} TPI_Type;
752
753/* TPI Asynchronous Clock Prescaler Register Definitions */
754#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
755#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
756
757/* TPI Selected Pin Protocol Register Definitions */
758#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
759#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
760
761/* TPI Formatter and Flush Status Register Definitions */
762#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
763#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
764
765#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
766#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
767
768#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
769#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
770
771#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
772#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
773
774/* TPI Formatter and Flush Control Register Definitions */
775#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
776#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
777
778#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
779#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
780
781#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
782#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
783
784/* TPI TRIGGER Register Definitions */
785#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
786#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
787
788/* TPI Integration Test FIFO Test Data 0 Register Definitions */
789#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
790#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
791
792#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
793#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
794
795#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
796#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
797
798#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
799#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
800
801#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
802#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
803
804#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
805#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
806
807#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
808#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
809
810/* TPI Integration Test ATB Control Register 2 Register Definitions */
811#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
812#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
813
814#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
815#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
816
817#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
818#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
819
820#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
821#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
822
823/* TPI Integration Test FIFO Test Data 1 Register Definitions */
824#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
825#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
826
827#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
828#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
829
830#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
831#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
832
833#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
834#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
835
836#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
837#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
838
839#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
840#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
841
842#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
843#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
844
845/* TPI Integration Test ATB Control Register 0 Definitions */
846#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
847#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
848
849#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
850#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
851
852#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
853#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
854
855#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
856#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
857
858/* TPI Integration Mode Control Register Definitions */
859#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
860#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
861
862/* TPI DEVID Register Definitions */
863#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
864#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
865
866#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
867#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
868
869#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
870#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
871
872#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
873#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
874
875#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
876#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
877
878/* TPI DEVTYPE Register Definitions */
879#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
880#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
881
882#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
883#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
884
885/*@}*/ /* end of group CMSIS_TPI */
886
887
888#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
889/**
890 \ingroup CMSIS_core_register
891 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
892 \brief Type definitions for the Memory Protection Unit (MPU)
893 @{
894 */
895
896/**
897 \brief Structure type to access the Memory Protection Unit (MPU).
898 */
899typedef struct
900{
901 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
902 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
903 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
904 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
905 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
906 uint32_t RESERVED0[7U];
907 union {
908 __IOM uint32_t MAIR[2];
909 struct {
910 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
911 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
912 };
913 };
914} MPU_Type;
915
916#define MPU_TYPE_RALIASES 1U
917
918/* MPU Type Register Definitions */
919#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
920#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
921
922#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
923#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
924
925#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
926#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
927
928/* MPU Control Register Definitions */
929#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
930#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
931
932#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
933#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
934
935#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
936#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
937
938/* MPU Region Number Register Definitions */
939#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
940#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
941
942/* MPU Region Base Address Register Definitions */
943#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
944#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
945
946#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
947#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
948
949#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
950#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
951
952#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
953#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
954
955/* MPU Region Limit Address Register Definitions */
956#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
957#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
958
959#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
960#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
961
962#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
963#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
964
965/* MPU Memory Attribute Indirection Register 0 Definitions */
966#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
967#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
968
969#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
970#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
971
972#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
973#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
974
975#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
976#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
977
978/* MPU Memory Attribute Indirection Register 1 Definitions */
979#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
980#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
981
982#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
983#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
984
985#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
986#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
987
988#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
989#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
990
991/*@} end of group CMSIS_MPU */
992#endif
993
994
995#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
996/**
997 \ingroup CMSIS_core_register
998 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
999 \brief Type definitions for the Security Attribution Unit (SAU)
1000 @{
1001 */
1002
1003/**
1004 \brief Structure type to access the Security Attribution Unit (SAU).
1005 */
1006typedef struct
1007{
1008 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
1009 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1010#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1011 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
1012 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
1013 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
1014#endif
1015} SAU_Type;
1016
1017/* SAU Control Register Definitions */
1018#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
1019#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
1020
1021#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1022#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1023
1024/* SAU Type Register Definitions */
1025#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1026#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1027
1028#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1029/* SAU Region Number Register Definitions */
1030#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1031#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1032
1033/* SAU Region Base Address Register Definitions */
1034#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1035#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1036
1037/* SAU Region Limit Address Register Definitions */
1038#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1039#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1040
1041#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1042#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1043
1044#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1045#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1046
1047#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1048
1049/*@} end of group CMSIS_SAU */
1050#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1051
1052
1053/**
1054 \ingroup CMSIS_core_register
1055 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1056 \brief Type definitions for the Core Debug Registers
1057 @{
1058 */
1059
1060/**
1061 \brief Structure type to access the Core Debug Register (CoreDebug).
1062 */
1063typedef struct
1064{
1065 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1066 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1067 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1068 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1069 uint32_t RESERVED4[1U];
1070 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1071 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1072} CoreDebug_Type;
1073
1074/* Debug Halting Control and Status Register Definitions */
1075#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1076#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1077
1078#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
1079#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
1080
1081#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1082#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1083
1084#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1085#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1086
1087#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1088#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1089
1090#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1091#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1092
1093#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1094#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1095
1096#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1097#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1098
1099#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1100#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1101
1102#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1103#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1104
1105#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1106#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1107
1108#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1109#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1110
1111/* Debug Core Register Selector Register Definitions */
1112#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1113#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1114
1115#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1116#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1117
1118/* Debug Exception and Monitor Control Register */
1119#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
1120#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
1121
1122#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1123#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1124
1125#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1126#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1127
1128/* Debug Authentication Control Register Definitions */
1129#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
1130#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
1131
1132#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
1133#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
1134
1135#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
1136#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
1137
1138#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
1139#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
1140
1141/* Debug Security Control and Status Register Definitions */
1142#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
1143#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
1144
1145#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
1146#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
1147
1148#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
1149#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
1150
1151/*@} end of group CMSIS_CoreDebug */
1152
1153
1154/**
1155 \ingroup CMSIS_core_register
1156 \defgroup CMSIS_core_bitfield Core register bit field macros
1157 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1158 @{
1159 */
1160
1161/**
1162 \brief Mask and shift a bit field value for use in a register bit range.
1163 \param[in] field Name of the register bit field.
1164 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1165 \return Masked and shifted value.
1166*/
1167#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1168
1169/**
1170 \brief Mask and shift a register value to extract a bit filed value.
1171 \param[in] field Name of the register bit field.
1172 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1173 \return Masked and shifted bit field value.
1174*/
1175#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1176
1177/*@} end of group CMSIS_core_bitfield */
1178
1179
1180/**
1181 \ingroup CMSIS_core_register
1182 \defgroup CMSIS_core_base Core Definitions
1183 \brief Definitions for base addresses, unions, and structures.
1184 @{
1185 */
1186
1187/* Memory mapping of Core Hardware */
1188 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1189 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1190 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1191 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1192 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1193 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1194 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1195
1196
1197 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1198 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1199 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1200 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1201 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1202 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
1203
1204 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1205 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1206 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1207 #endif
1208
1209 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1210 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
1211 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
1212 #endif
1213
1214#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1215 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
1216 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
1217 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
1218 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
1219 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
1220
1221 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
1222 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
1223 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
1224 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
1225
1226 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1227 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
1228 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
1229 #endif
1230
1231#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1232/*@} */
1233
1234
1235
1236/*******************************************************************************
1237 * Hardware Abstraction Layer
1238 Core Function Interface contains:
1239 - Core NVIC Functions
1240 - Core SysTick Functions
1241 - Core Register Access Functions
1242 ******************************************************************************/
1243/**
1244 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1245*/
1246
1247
1248
1249/* ########################## NVIC functions #################################### */
1250/**
1251 \ingroup CMSIS_Core_FunctionInterface
1252 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1253 \brief Functions that manage interrupts and exceptions via the NVIC.
1254 @{
1255 */
1256
1257#ifdef CMSIS_NVIC_VIRTUAL
1258 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1259 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1260 #endif
1261 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1262#else
1263/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
1264/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
1265 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1266 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1267 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1268 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1269 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1270 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1271 #define NVIC_GetActive __NVIC_GetActive
1272 #define NVIC_SetPriority __NVIC_SetPriority
1273 #define NVIC_GetPriority __NVIC_GetPriority
1274 #define NVIC_SystemReset __NVIC_SystemReset
1275#endif /* CMSIS_NVIC_VIRTUAL */
1276
1277#ifdef CMSIS_VECTAB_VIRTUAL
1278 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1279 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1280 #endif
1281 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1282#else
1283 #define NVIC_SetVector __NVIC_SetVector
1284 #define NVIC_GetVector __NVIC_GetVector
1285#endif /* (CMSIS_VECTAB_VIRTUAL) */
1286
1287#define NVIC_USER_IRQ_OFFSET 16
1288
1289
1290/* Special LR values for Secure/Non-Secure call handling and exception handling */
1291
1292/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
1293#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
1294
1295/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
1296#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
1297#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
1298#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
1299#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
1300#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
1301#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
1302#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
1303
1304/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
1305#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
1306#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
1307#else
1308#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
1309#endif
1310
1311
1312/* Interrupt Priorities are WORD accessible only under Armv6-M */
1313/* The following MACROS handle generation of the register offset and byte masks */
1314#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
1315#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
1316#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
1317
1318#define __NVIC_SetPriorityGrouping(X) (void)(X)
1319#define __NVIC_GetPriorityGrouping() (0U)
1320
1321/**
1322 \brief Enable Interrupt
1323 \details Enables a device specific interrupt in the NVIC interrupt controller.
1324 \param [in] IRQn Device specific interrupt number.
1325 \note IRQn must not be negative.
1326 */
1327__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1328{
1329 if ((int32_t)(IRQn) >= 0)
1330 {
1331 __COMPILER_BARRIER();
1332 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1333 __COMPILER_BARRIER();
1334 }
1335}
1336
1337
1338/**
1339 \brief Get Interrupt Enable status
1340 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1341 \param [in] IRQn Device specific interrupt number.
1342 \return 0 Interrupt is not enabled.
1343 \return 1 Interrupt is enabled.
1344 \note IRQn must not be negative.
1345 */
1346__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1347{
1348 if ((int32_t)(IRQn) >= 0)
1349 {
1350 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1351 }
1352 else
1353 {
1354 return(0U);
1355 }
1356}
1357
1358
1359/**
1360 \brief Disable Interrupt
1361 \details Disables a device specific interrupt in the NVIC interrupt controller.
1362 \param [in] IRQn Device specific interrupt number.
1363 \note IRQn must not be negative.
1364 */
1365__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1366{
1367 if ((int32_t)(IRQn) >= 0)
1368 {
1369 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1370 __DSB();
1371 __ISB();
1372 }
1373}
1374
1375
1376/**
1377 \brief Get Pending Interrupt
1378 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1379 \param [in] IRQn Device specific interrupt number.
1380 \return 0 Interrupt status is not pending.
1381 \return 1 Interrupt status is pending.
1382 \note IRQn must not be negative.
1383 */
1384__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1385{
1386 if ((int32_t)(IRQn) >= 0)
1387 {
1388 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1389 }
1390 else
1391 {
1392 return(0U);
1393 }
1394}
1395
1396
1397/**
1398 \brief Set Pending Interrupt
1399 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1400 \param [in] IRQn Device specific interrupt number.
1401 \note IRQn must not be negative.
1402 */
1403__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1404{
1405 if ((int32_t)(IRQn) >= 0)
1406 {
1407 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1408 }
1409}
1410
1411
1412/**
1413 \brief Clear Pending Interrupt
1414 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1415 \param [in] IRQn Device specific interrupt number.
1416 \note IRQn must not be negative.
1417 */
1418__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1419{
1420 if ((int32_t)(IRQn) >= 0)
1421 {
1422 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1423 }
1424}
1425
1426
1427/**
1428 \brief Get Active Interrupt
1429 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1430 \param [in] IRQn Device specific interrupt number.
1431 \return 0 Interrupt status is not active.
1432 \return 1 Interrupt status is active.
1433 \note IRQn must not be negative.
1434 */
1435__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1436{
1437 if ((int32_t)(IRQn) >= 0)
1438 {
1439 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1440 }
1441 else
1442 {
1443 return(0U);
1444 }
1445}
1446
1447
1448#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1449/**
1450 \brief Get Interrupt Target State
1451 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1452 \param [in] IRQn Device specific interrupt number.
1453 \return 0 if interrupt is assigned to Secure
1454 \return 1 if interrupt is assigned to Non Secure
1455 \note IRQn must not be negative.
1456 */
1457__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
1458{
1459 if ((int32_t)(IRQn) >= 0)
1460 {
1461 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1462 }
1463 else
1464 {
1465 return(0U);
1466 }
1467}
1468
1469
1470/**
1471 \brief Set Interrupt Target State
1472 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1473 \param [in] IRQn Device specific interrupt number.
1474 \return 0 if interrupt is assigned to Secure
1475 1 if interrupt is assigned to Non Secure
1476 \note IRQn must not be negative.
1477 */
1478__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
1479{
1480 if ((int32_t)(IRQn) >= 0)
1481 {
1482 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1483 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1484 }
1485 else
1486 {
1487 return(0U);
1488 }
1489}
1490
1491
1492/**
1493 \brief Clear Interrupt Target State
1494 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1495 \param [in] IRQn Device specific interrupt number.
1496 \return 0 if interrupt is assigned to Secure
1497 1 if interrupt is assigned to Non Secure
1498 \note IRQn must not be negative.
1499 */
1500__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
1501{
1502 if ((int32_t)(IRQn) >= 0)
1503 {
1504 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1505 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1506 }
1507 else
1508 {
1509 return(0U);
1510 }
1511}
1512#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1513
1514
1515/**
1516 \brief Set Interrupt Priority
1517 \details Sets the priority of a device specific interrupt or a processor exception.
1518 The interrupt number can be positive to specify a device specific interrupt,
1519 or negative to specify a processor exception.
1520 \param [in] IRQn Interrupt number.
1521 \param [in] priority Priority to set.
1522 \note The priority cannot be set for every processor exception.
1523 */
1524__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1525{
1526 if ((int32_t)(IRQn) >= 0)
1527 {
1528 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1529 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1530 }
1531 else
1532 {
1533 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1534 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1535 }
1536}
1537
1538
1539/**
1540 \brief Get Interrupt Priority
1541 \details Reads the priority of a device specific interrupt or a processor exception.
1542 The interrupt number can be positive to specify a device specific interrupt,
1543 or negative to specify a processor exception.
1544 \param [in] IRQn Interrupt number.
1545 \return Interrupt Priority.
1546 Value is aligned automatically to the implemented priority bits of the microcontroller.
1547 */
1548__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1549{
1550
1551 if ((int32_t)(IRQn) >= 0)
1552 {
1553 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1554 }
1555 else
1556 {
1557 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1558 }
1559}
1560
1561
1562/**
1563 \brief Encode Priority
1564 \details Encodes the priority for an interrupt with the given priority group,
1565 preemptive priority value, and subpriority value.
1566 In case of a conflict between priority grouping and available
1567 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1568 \param [in] PriorityGroup Used priority group.
1569 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1570 \param [in] SubPriority Subpriority value (starting from 0).
1571 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1572 */
1573__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1574{
1575 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1576 uint32_t PreemptPriorityBits;
1577 uint32_t SubPriorityBits;
1578
1579 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1580 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1581
1582 return (
1583 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1584 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1585 );
1586}
1587
1588
1589/**
1590 \brief Decode Priority
1591 \details Decodes an interrupt priority value with a given priority group to
1592 preemptive priority value and subpriority value.
1593 In case of a conflict between priority grouping and available
1594 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1595 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1596 \param [in] PriorityGroup Used priority group.
1597 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1598 \param [out] pSubPriority Subpriority value (starting from 0).
1599 */
1600__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1601{
1602 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1603 uint32_t PreemptPriorityBits;
1604 uint32_t SubPriorityBits;
1605
1606 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1607 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1608
1609 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1610 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1611}
1612
1613
1614/**
1615 \brief Set Interrupt Vector
1616 \details Sets an interrupt vector in SRAM based interrupt vector table.
1617 The interrupt number can be positive to specify a device specific interrupt,
1618 or negative to specify a processor exception.
1619 VTOR must been relocated to SRAM before.
1620 If VTOR is not present address 0 must be mapped to SRAM.
1621 \param [in] IRQn Interrupt number
1622 \param [in] vector Address of interrupt handler function
1623 */
1624__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1625{
1626#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1627 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1628#else
1629 uint32_t *vectors = (uint32_t *)0x0U;
1630#endif
1631 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1632 __DSB();
1633}
1634
1635
1636/**
1637 \brief Get Interrupt Vector
1638 \details Reads an interrupt vector from interrupt vector table.
1639 The interrupt number can be positive to specify a device specific interrupt,
1640 or negative to specify a processor exception.
1641 \param [in] IRQn Interrupt number.
1642 \return Address of interrupt handler function
1643 */
1644__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1645{
1646#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1647 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1648#else
1649 uint32_t *vectors = (uint32_t *)0x0U;
1650#endif
1651 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1652}
1653
1654
1655/**
1656 \brief System Reset
1657 \details Initiates a system reset request to reset the MCU.
1658 */
1659__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1660{
1661 __DSB(); /* Ensure all outstanding memory accesses included
1662 buffered write are completed before reset */
1663 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1664 SCB_AIRCR_SYSRESETREQ_Msk);
1665 __DSB(); /* Ensure completion of memory access */
1666
1667 for(;;) /* wait until reset */
1668 {
1669 __NOP();
1670 }
1671}
1672
1673#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1674/**
1675 \brief Enable Interrupt (non-secure)
1676 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
1677 \param [in] IRQn Device specific interrupt number.
1678 \note IRQn must not be negative.
1679 */
1680__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
1681{
1682 if ((int32_t)(IRQn) >= 0)
1683 {
1684 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1685 }
1686}
1687
1688
1689/**
1690 \brief Get Interrupt Enable status (non-secure)
1691 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
1692 \param [in] IRQn Device specific interrupt number.
1693 \return 0 Interrupt is not enabled.
1694 \return 1 Interrupt is enabled.
1695 \note IRQn must not be negative.
1696 */
1697__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
1698{
1699 if ((int32_t)(IRQn) >= 0)
1700 {
1701 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1702 }
1703 else
1704 {
1705 return(0U);
1706 }
1707}
1708
1709
1710/**
1711 \brief Disable Interrupt (non-secure)
1712 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
1713 \param [in] IRQn Device specific interrupt number.
1714 \note IRQn must not be negative.
1715 */
1716__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
1717{
1718 if ((int32_t)(IRQn) >= 0)
1719 {
1720 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1721 }
1722}
1723
1724
1725/**
1726 \brief Get Pending Interrupt (non-secure)
1727 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
1728 \param [in] IRQn Device specific interrupt number.
1729 \return 0 Interrupt status is not pending.
1730 \return 1 Interrupt status is pending.
1731 \note IRQn must not be negative.
1732 */
1733__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
1734{
1735 if ((int32_t)(IRQn) >= 0)
1736 {
1737 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1738 }
1739 else
1740 {
1741 return(0U);
1742 }
1743}
1744
1745
1746/**
1747 \brief Set Pending Interrupt (non-secure)
1748 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
1749 \param [in] IRQn Device specific interrupt number.
1750 \note IRQn must not be negative.
1751 */
1752__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
1753{
1754 if ((int32_t)(IRQn) >= 0)
1755 {
1756 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1757 }
1758}
1759
1760
1761/**
1762 \brief Clear Pending Interrupt (non-secure)
1763 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
1764 \param [in] IRQn Device specific interrupt number.
1765 \note IRQn must not be negative.
1766 */
1767__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
1768{
1769 if ((int32_t)(IRQn) >= 0)
1770 {
1771 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1772 }
1773}
1774
1775
1776/**
1777 \brief Get Active Interrupt (non-secure)
1778 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
1779 \param [in] IRQn Device specific interrupt number.
1780 \return 0 Interrupt status is not active.
1781 \return 1 Interrupt status is active.
1782 \note IRQn must not be negative.
1783 */
1784__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
1785{
1786 if ((int32_t)(IRQn) >= 0)
1787 {
1788 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1789 }
1790 else
1791 {
1792 return(0U);
1793 }
1794}
1795
1796
1797/**
1798 \brief Set Interrupt Priority (non-secure)
1799 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
1800 The interrupt number can be positive to specify a device specific interrupt,
1801 or negative to specify a processor exception.
1802 \param [in] IRQn Interrupt number.
1803 \param [in] priority Priority to set.
1804 \note The priority cannot be set for every non-secure processor exception.
1805 */
1806__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
1807{
1808 if ((int32_t)(IRQn) >= 0)
1809 {
1810 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1811 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1812 }
1813 else
1814 {
1815 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1816 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1817 }
1818}
1819
1820
1821/**
1822 \brief Get Interrupt Priority (non-secure)
1823 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
1824 The interrupt number can be positive to specify a device specific interrupt,
1825 or negative to specify a processor exception.
1826 \param [in] IRQn Interrupt number.
1827 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
1828 */
1829__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
1830{
1831
1832 if ((int32_t)(IRQn) >= 0)
1833 {
1834 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1835 }
1836 else
1837 {
1838 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1839 }
1840}
1841#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
1842
1843/*@} end of CMSIS_Core_NVICFunctions */
1844
1845/* ########################## MPU functions #################################### */
1846
1847#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1848
1849#include "mpu_armv8.h"
1850
1851#endif
1852
1853/* ########################## FPU functions #################################### */
1854/**
1855 \ingroup CMSIS_Core_FunctionInterface
1856 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1857 \brief Function that provides FPU type.
1858 @{
1859 */
1860
1861/**
1862 \brief get FPU type
1863 \details returns the FPU type
1864 \returns
1865 - \b 0: No FPU
1866 - \b 1: Single precision FPU
1867 - \b 2: Double + Single precision FPU
1868 */
1869__STATIC_INLINE uint32_t SCB_GetFPUType(void)
1870{
1871 return 0U; /* No FPU */
1872}
1873
1874
1875/*@} end of CMSIS_Core_FpuFunctions */
1876
1877
1878
1879/* ########################## SAU functions #################################### */
1880/**
1881 \ingroup CMSIS_Core_FunctionInterface
1882 \defgroup CMSIS_Core_SAUFunctions SAU Functions
1883 \brief Functions that configure the SAU.
1884 @{
1885 */
1886
1887#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1888
1889/**
1890 \brief Enable SAU
1891 \details Enables the Security Attribution Unit (SAU).
1892 */
1893__STATIC_INLINE void TZ_SAU_Enable(void)
1894{
1895 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
1896}
1897
1898
1899
1900/**
1901 \brief Disable SAU
1902 \details Disables the Security Attribution Unit (SAU).
1903 */
1904__STATIC_INLINE void TZ_SAU_Disable(void)
1905{
1906 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
1907}
1908
1909#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1910
1911/*@} end of CMSIS_Core_SAUFunctions */
1912
1913
1914
1915
1916/* ################################## SysTick function ############################################ */
1917/**
1918 \ingroup CMSIS_Core_FunctionInterface
1919 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1920 \brief Functions that configure the System.
1921 @{
1922 */
1923
1924#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1925
1926/**
1927 \brief System Tick Configuration
1928 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1929 Counter is in free running mode to generate periodic interrupts.
1930 \param [in] ticks Number of ticks between two interrupts.
1931 \return 0 Function succeeded.
1932 \return 1 Function failed.
1933 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1934 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1935 must contain a vendor-specific implementation of this function.
1936 */
1937__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1938{
1939 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1940 {
1941 return (1UL); /* Reload value impossible */
1942 }
1943
1944 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1945 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1946 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1947 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1948 SysTick_CTRL_TICKINT_Msk |
1949 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1950 return (0UL); /* Function successful */
1951}
1952
1953#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1954/**
1955 \brief System Tick Configuration (non-secure)
1956 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
1957 Counter is in free running mode to generate periodic interrupts.
1958 \param [in] ticks Number of ticks between two interrupts.
1959 \return 0 Function succeeded.
1960 \return 1 Function failed.
1961 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1962 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
1963 must contain a vendor-specific implementation of this function.
1964
1965 */
1966__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
1967{
1968 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1969 {
1970 return (1UL); /* Reload value impossible */
1971 }
1972
1973 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1974 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1975 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
1976 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1977 SysTick_CTRL_TICKINT_Msk |
1978 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1979 return (0UL); /* Function successful */
1980}
1981#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1982
1983#endif
1984
1985/*@} end of CMSIS_Core_SysTickFunctions */
1986
1987
1988
1989
1990#ifdef __cplusplus
1991}
1992#endif
1993
1994#endif /* __CORE_CM23_H_DEPENDANT */
1995
1996#endif /* __CMSIS_GENERIC */
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