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diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1015/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1015/project_template/clock_config.c
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+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1015/project_template/clock_config.c
@@ -0,0 +1,364 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v5.0
26processor: MIMXRT1015xxxxx
27package_id: MIMXRT1015DAF5A
28mcu_data: ksdk2_0
29processor_version: 0.0.0
30board: MIMXRT1015-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33#include "clock_config.h"
34#include "fsl_iomuxc.h"
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*******************************************************************************
41 * Variables
42 ******************************************************************************/
43/* System clock frequency. */
44extern uint32_t SystemCoreClock;
45
46/*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
49void BOARD_InitBootClocks(void)
50{
51 BOARD_BootClockRUN();
52}
53
54/*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58!!Configuration
59name: BOARD_BootClockRUN
60called_from_default_init: true
61outputs:
62- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
63- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
64- {id: CLK_1M.outFreq, value: 1 MHz}
65- {id: CLK_24M.outFreq, value: 24 MHz}
66- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
67- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
68- {id: FLEXSPI_CLK_ROOT.outFreq, value: 125 MHz}
69- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
70- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
71- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
72- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
73- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
74- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
75- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
76- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
77- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
78- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
79- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
80- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
81- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
82- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
83- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
84- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
85- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
86- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
87- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
88- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
89settings:
90- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
91- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
92- {id: CCM.CLKO2_SEL.sel, value: CCM.LPI2C_CLK_ROOT}
93- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
94- {id: CCM.IPG_PODF.scale, value: '4'}
95- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
96- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
97- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
98- {id: CCM.SEMC_PODF.scale, value: '2'}
99- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
100- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
101- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
102- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
103- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
104- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
105- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
106- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
107- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
108- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
109- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
110- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
111- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
112- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
113- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
114- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
115- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
116- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
117- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
118- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
119- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
120- {id: CCM_ANALOG.PLL4.denom, value: '50'}
121- {id: CCM_ANALOG.PLL4.div, value: '47'}
122- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
123- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
124sources:
125- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
126- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
127 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
128
129/*******************************************************************************
130 * Variables for BOARD_BootClockRUN configuration
131 ******************************************************************************/
132const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
133 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
134 .numerator = 0, /* 30 bit numerator of fractional loop divider */
135 .denominator = 1, /* 30 bit denominator of fractional loop divider */
136 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
137};
138const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
139 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
140 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
141};
142const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = {
143 .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
144 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
145};
146/*******************************************************************************
147 * Code for BOARD_BootClockRUN configuration
148 ******************************************************************************/
149void BOARD_BootClockRUN(void)
150{
151 /* Init RTC OSC clock frequency. */
152 CLOCK_SetRtcXtalFreq(32768U);
153 /* Enable 1MHz clock output. */
154 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
155 /* Use free 1MHz clock output. */
156 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
157 /* Set XTAL 24MHz clock frequency. */
158 CLOCK_SetXtalFreq(24000000U);
159 /* Enable XTAL 24MHz clock source. */
160 CLOCK_InitExternalClk(0);
161 /* Enable internal RC. */
162 CLOCK_InitRcOsc24M();
163 /* Switch clock source to external OSC. */
164 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
165 /* Set Oscillator ready counter value. */
166 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
167 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
168 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
169 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
170 /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 500Mhz. */
171 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
172 /* Waiting for DCDC_STS_DC_OK bit is asserted */
173 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
174 {
175 }
176 /* Set AHB_PODF. */
177 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
178 /* Disable IPG clock gate. */
179 CLOCK_DisableClock(kCLOCK_Adc1);
180 CLOCK_DisableClock(kCLOCK_Xbar1);
181 CLOCK_DisableClock(kCLOCK_Xbar2);
182 /* Set IPG_PODF. */
183 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
184 /* Set ARM_PODF. */
185 CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
186 /* Set PERIPH_CLK2_PODF. */
187 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
188 /* Disable PERCLK clock gate. */
189 CLOCK_DisableClock(kCLOCK_Gpt1);
190 CLOCK_DisableClock(kCLOCK_Gpt1S);
191 CLOCK_DisableClock(kCLOCK_Gpt2);
192 CLOCK_DisableClock(kCLOCK_Gpt2S);
193 CLOCK_DisableClock(kCLOCK_Pit);
194 /* Set PERCLK_PODF. */
195 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
196 /* Set SEMC_PODF. */
197 CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
198 /* Set Semc alt clock source. */
199 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
200 /* Set Semc clock source. */
201 CLOCK_SetMux(kCLOCK_SemcMux, 0);
202 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
203 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
204 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
205 * well.*/
206#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
207 /* Disable Flexspi clock gate. */
208 CLOCK_DisableClock(kCLOCK_FlexSpi);
209 /* Set FLEXSPI_PODF. */
210 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
211 /* Set Flexspi clock source. */
212 CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
213#endif
214 /* Disable LPSPI clock gate. */
215 CLOCK_DisableClock(kCLOCK_Lpspi1);
216 CLOCK_DisableClock(kCLOCK_Lpspi2);
217 /* Set LPSPI_PODF. */
218 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
219 /* Set Lpspi clock source. */
220 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
221 /* Disable TRACE clock gate. */
222 CLOCK_DisableClock(kCLOCK_Trace);
223 /* Set TRACE_PODF. */
224 CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
225 /* Set Trace clock source. */
226 CLOCK_SetMux(kCLOCK_TraceMux, 2);
227 /* Disable SAI1 clock gate. */
228 CLOCK_DisableClock(kCLOCK_Sai1);
229 /* Set SAI1_CLK_PRED. */
230 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
231 /* Set SAI1_CLK_PODF. */
232 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
233 /* Set Sai1 clock source. */
234 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
235 /* Disable SAI2 clock gate. */
236 CLOCK_DisableClock(kCLOCK_Sai2);
237 /* Set SAI2_CLK_PRED. */
238 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
239 /* Set SAI2_CLK_PODF. */
240 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
241 /* Set Sai2 clock source. */
242 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
243 /* Disable SAI3 clock gate. */
244 CLOCK_DisableClock(kCLOCK_Sai3);
245 /* Set SAI3_CLK_PRED. */
246 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
247 /* Set SAI3_CLK_PODF. */
248 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
249 /* Set Sai3 clock source. */
250 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
251 /* Disable Lpi2c clock gate. */
252 CLOCK_DisableClock(kCLOCK_Lpi2c1);
253 CLOCK_DisableClock(kCLOCK_Lpi2c2);
254 /* Set LPI2C_CLK_PODF. */
255 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
256 /* Set Lpi2c clock source. */
257 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
258 /* Disable UART clock gate. */
259 CLOCK_DisableClock(kCLOCK_Lpuart1);
260 CLOCK_DisableClock(kCLOCK_Lpuart2);
261 CLOCK_DisableClock(kCLOCK_Lpuart3);
262 CLOCK_DisableClock(kCLOCK_Lpuart4);
263 /* Set UART_CLK_PODF. */
264 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
265 /* Set Uart clock source. */
266 CLOCK_SetMux(kCLOCK_UartMux, 0);
267 /* Disable SPDIF clock gate. */
268 CLOCK_DisableClock(kCLOCK_Spdif);
269 /* Set SPDIF0_CLK_PRED. */
270 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
271 /* Set SPDIF0_CLK_PODF. */
272 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
273 /* Set Spdif clock source. */
274 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
275 /* Disable Flexio1 clock gate. */
276 CLOCK_DisableClock(kCLOCK_Flexio1);
277 /* Set FLEXIO1_CLK_PRED. */
278 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
279 /* Set FLEXIO1_CLK_PODF. */
280 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
281 /* Set Flexio1 clock source. */
282 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
283 /* Set Pll3 sw clock source. */
284 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
285 /* Init System PLL. */
286 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
287 /* Init System pfd0. */
288 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
289 /* Init System pfd1. */
290 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
291 /* Init System pfd2. */
292 CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
293 /* Init System pfd3. */
294 CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
295 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
296 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
297 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
298 * well.*/
299#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
300 /* Init Usb1 PLL. */
301 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
302 /* Init Usb1 pfd0. */
303 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
304 /* Init Usb1 pfd1. */
305 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
306 /* Init Usb1 pfd2. */
307 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
308 /* Init Usb1 pfd3. */
309 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
310 /* Disable Usb1 PLL output for USBPHY1. */
311 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
312#endif
313 /* DeInit Audio PLL. */
314 CLOCK_DeinitAudioPll();
315 /* Bypass Audio PLL. */
316 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
317 /* Set divider for Audio PLL. */
318 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
319 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
320 /* Enable Audio PLL output. */
321 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
322 /* Init Enet PLL. */
323 CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
324 /* Set preperiph clock source. */
325 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
326 /* Set periph clock source. */
327 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
328 /* Set periph clock2 clock source. */
329 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
330 /* Set per clock source. */
331 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
332 /* Set clock out1 divider. */
333 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
334 /* Set clock out1 source. */
335 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
336 /* Set clock out2 divider. */
337 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
338 /* Set clock out2 source. */
339 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(6);
340 /* Set clock out1 drives clock out1. */
341 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
342 /* Disable clock out1. */
343 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
344 /* Disable clock out2. */
345 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
346 /* Set SAI1 MCLK1 clock source. */
347 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
348 /* Set SAI1 MCLK2 clock source. */
349 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
350 /* Set SAI1 MCLK3 clock source. */
351 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
352 /* Set SAI2 MCLK3 clock source. */
353 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
354 /* Set SAI3 MCLK3 clock source. */
355 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
356 /* Set MQS configuration. */
357 IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
358 /* Set GPT1 High frequency reference clock source. */
359 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
360 /* Set GPT2 High frequency reference clock source. */
361 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
362 /* Set SystemCoreClock variable. */
363 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
364}
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 16:58:30 +0100