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diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1020/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1020/clock_config.c
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1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7/*
8 * How to setup clock using clock driver functions:
9 *
10 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
11 *
12 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
13 *
14 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
15 *
16 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
17 *
18 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
19 *
20 */
21
22/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
23!!GlobalInfo
24product: Clocks v7.0
25processor: MIMXRT1021xxxxx
26package_id: MIMXRT1021DAG5A
27mcu_data: ksdk2_0
28processor_version: 0.7.10
29board: MIMXRT1020-EVK
30 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
31
32#include "clock_config.h"
33#include "fsl_iomuxc.h"
34
35/*******************************************************************************
36 * Definitions
37 ******************************************************************************/
38
39/*******************************************************************************
40 * Variables
41 ******************************************************************************/
42/* System clock frequency. */
43extern uint32_t SystemCoreClock;
44
45/*******************************************************************************
46 ************************ BOARD_InitBootClocks function ************************
47 ******************************************************************************/
48void BOARD_InitBootClocks(void)
49{
50 BOARD_BootClockRUN();
51}
52
53/*******************************************************************************
54 ********************** Configuration BOARD_BootClockRUN ***********************
55 ******************************************************************************/
56/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
57!!Configuration
58name: BOARD_BootClockRUN
59called_from_default_init: true
60outputs:
61- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
62- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
63- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
64- {id: CLK_1M.outFreq, value: 1 MHz}
65- {id: CLK_24M.outFreq, value: 24 MHz}
66- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
67- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
68- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
69- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
70- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
71- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
72- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
73- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
74- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
75- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
76- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
77- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
78- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
79- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
80- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
81- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
82- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
83- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
84- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
85- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
86- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
87- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
88- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
89- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
90- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
91- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
92settings:
93- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
94- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
95- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
96- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
97- {id: CCM.IPG_PODF.scale, value: '4'}
98- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
99- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
100- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
101- {id: CCM.SEMC_PODF.scale, value: '8'}
102- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
103- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
104- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
105- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
106- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
107- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
108- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
109- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
110- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
111- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
112- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
113- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
114- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
115- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
116- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
117- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
118- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
119- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
120- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
121- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
122- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
123- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
124- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
125- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
126- {id: CCM_ANALOG.PLL4.denom, value: '50'}
127- {id: CCM_ANALOG.PLL4.div, value: '47'}
128- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
129- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
130- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
131- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
132sources:
133- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
134 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
135
136/*******************************************************************************
137 * Variables for BOARD_BootClockRUN configuration
138 ******************************************************************************/
139const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
140 {
141 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
142 .numerator = 0, /* 30 bit numerator of fractional loop divider */
143 .denominator = 1, /* 30 bit denominator of fractional loop divider */
144 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
145 };
146const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
147 {
148 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
149 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
150 };
151const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
152 {
153 .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
154 .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
155 .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
156 .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
157 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
158 };
159/*******************************************************************************
160 * Code for BOARD_BootClockRUN configuration
161 ******************************************************************************/
162void BOARD_BootClockRUN(void)
163{
164 /* Init RTC OSC clock frequency. */
165 CLOCK_SetRtcXtalFreq(32768U);
166 /* Enable 1MHz clock output. */
167 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
168 /* Use free 1MHz clock output. */
169 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
170 /* Set XTAL 24MHz clock frequency. */
171 CLOCK_SetXtalFreq(24000000U);
172 /* Enable XTAL 24MHz clock source. */
173 CLOCK_InitExternalClk(0);
174 /* Enable internal RC. */
175 CLOCK_InitRcOsc24M();
176 /* Switch clock source to external OSC. */
177 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
178 /* Set Oscillator ready counter value. */
179 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
180 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
181 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
182 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
183 /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 500Mhz. */
184 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
185 /* Waiting for DCDC_STS_DC_OK bit is asserted */
186 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
187 {
188 }
189 /* Set AHB_PODF. */
190 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
191 /* Disable IPG clock gate. */
192 CLOCK_DisableClock(kCLOCK_Adc1);
193 CLOCK_DisableClock(kCLOCK_Adc2);
194 CLOCK_DisableClock(kCLOCK_Xbar1);
195 CLOCK_DisableClock(kCLOCK_Xbar2);
196 /* Set IPG_PODF. */
197 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
198 /* Set ARM_PODF. */
199 CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
200 /* Set PERIPH_CLK2_PODF. */
201 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
202 /* Disable PERCLK clock gate. */
203 CLOCK_DisableClock(kCLOCK_Gpt1);
204 CLOCK_DisableClock(kCLOCK_Gpt1S);
205 CLOCK_DisableClock(kCLOCK_Gpt2);
206 CLOCK_DisableClock(kCLOCK_Gpt2S);
207 CLOCK_DisableClock(kCLOCK_Pit);
208 /* Set PERCLK_PODF. */
209 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
210 /* Disable USDHC1 clock gate. */
211 CLOCK_DisableClock(kCLOCK_Usdhc1);
212 /* Set USDHC1_PODF. */
213 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
214 /* Set Usdhc1 clock source. */
215 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
216 /* Disable USDHC2 clock gate. */
217 CLOCK_DisableClock(kCLOCK_Usdhc2);
218 /* Set USDHC2_PODF. */
219 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
220 /* Set Usdhc2 clock source. */
221 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
222 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
223 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
224 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
225#ifndef SKIP_SYSCLK_INIT
226 /* Disable Semc clock gate. */
227 CLOCK_DisableClock(kCLOCK_Semc);
228 /* Set SEMC_PODF. */
229 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
230 /* Set Semc alt clock source. */
231 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
232 /* Set Semc clock source. */
233 CLOCK_SetMux(kCLOCK_SemcMux, 0);
234#endif
235 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
236 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
237 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
238#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
239 /* Disable Flexspi clock gate. */
240 CLOCK_DisableClock(kCLOCK_FlexSpi);
241 /* Set FLEXSPI_PODF. */
242 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
243 /* Set Flexspi clock source. */
244 CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
245#endif
246 /* Disable LPSPI clock gate. */
247 CLOCK_DisableClock(kCLOCK_Lpspi1);
248 CLOCK_DisableClock(kCLOCK_Lpspi2);
249 CLOCK_DisableClock(kCLOCK_Lpspi3);
250 CLOCK_DisableClock(kCLOCK_Lpspi4);
251 /* Set LPSPI_PODF. */
252 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
253 /* Set Lpspi clock source. */
254 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
255 /* Disable TRACE clock gate. */
256 CLOCK_DisableClock(kCLOCK_Trace);
257 /* Set TRACE_PODF. */
258 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
259 /* Set Trace clock source. */
260 CLOCK_SetMux(kCLOCK_TraceMux, 0);
261 /* Disable SAI1 clock gate. */
262 CLOCK_DisableClock(kCLOCK_Sai1);
263 /* Set SAI1_CLK_PRED. */
264 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
265 /* Set SAI1_CLK_PODF. */
266 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
267 /* Set Sai1 clock source. */
268 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
269 /* Disable SAI2 clock gate. */
270 CLOCK_DisableClock(kCLOCK_Sai2);
271 /* Set SAI2_CLK_PRED. */
272 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
273 /* Set SAI2_CLK_PODF. */
274 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
275 /* Set Sai2 clock source. */
276 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
277 /* Disable SAI3 clock gate. */
278 CLOCK_DisableClock(kCLOCK_Sai3);
279 /* Set SAI3_CLK_PRED. */
280 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
281 /* Set SAI3_CLK_PODF. */
282 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
283 /* Set Sai3 clock source. */
284 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
285 /* Disable Lpi2c clock gate. */
286 CLOCK_DisableClock(kCLOCK_Lpi2c1);
287 CLOCK_DisableClock(kCLOCK_Lpi2c2);
288 CLOCK_DisableClock(kCLOCK_Lpi2c3);
289 /* Set LPI2C_CLK_PODF. */
290 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
291 /* Set Lpi2c clock source. */
292 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
293 /* Disable CAN clock gate. */
294 CLOCK_DisableClock(kCLOCK_Can1);
295 CLOCK_DisableClock(kCLOCK_Can2);
296 CLOCK_DisableClock(kCLOCK_Can1S);
297 CLOCK_DisableClock(kCLOCK_Can2S);
298 /* Set CAN_CLK_PODF. */
299 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
300 /* Set Can clock source. */
301 CLOCK_SetMux(kCLOCK_CanMux, 2);
302 /* Disable UART clock gate. */
303 CLOCK_DisableClock(kCLOCK_Lpuart1);
304 CLOCK_DisableClock(kCLOCK_Lpuart2);
305 CLOCK_DisableClock(kCLOCK_Lpuart3);
306 CLOCK_DisableClock(kCLOCK_Lpuart4);
307 CLOCK_DisableClock(kCLOCK_Lpuart5);
308 CLOCK_DisableClock(kCLOCK_Lpuart6);
309 CLOCK_DisableClock(kCLOCK_Lpuart7);
310 CLOCK_DisableClock(kCLOCK_Lpuart8);
311 /* Set UART_CLK_PODF. */
312 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
313 /* Set Uart clock source. */
314 CLOCK_SetMux(kCLOCK_UartMux, 0);
315 /* Disable SPDIF clock gate. */
316 CLOCK_DisableClock(kCLOCK_Spdif);
317 /* Set SPDIF0_CLK_PRED. */
318 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
319 /* Set SPDIF0_CLK_PODF. */
320 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
321 /* Set Spdif clock source. */
322 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
323 /* Disable Flexio1 clock gate. */
324 CLOCK_DisableClock(kCLOCK_Flexio1);
325 /* Set FLEXIO1_CLK_PRED. */
326 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
327 /* Set FLEXIO1_CLK_PODF. */
328 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
329 /* Set Flexio1 clock source. */
330 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
331 /* Set Pll3 sw clock source. */
332 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
333 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
334 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
335 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
336#ifndef SKIP_SYSCLK_INIT
337#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
338 #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
339#endif
340 /* Init System PLL. */
341 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
342 /* Init System pfd0. */
343 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
344 /* Init System pfd1. */
345 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
346 /* Init System pfd2. */
347 CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
348 /* Init System pfd3. */
349 CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
350#endif
351 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
352 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
353 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
354#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
355 /* Init Usb1 PLL. */
356 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
357 /* Init Usb1 pfd0. */
358 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
359 /* Init Usb1 pfd1. */
360 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
361 /* Init Usb1 pfd2. */
362 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
363 /* Init Usb1 pfd3. */
364 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
365 /* Disable Usb1 PLL output for USBPHY1. */
366 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
367#endif
368 /* DeInit Audio PLL. */
369 CLOCK_DeinitAudioPll();
370 /* Bypass Audio PLL. */
371 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
372 /* Set divider for Audio PLL. */
373 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
374 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
375 /* Enable Audio PLL output. */
376 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
377 /* Init Enet PLL. */
378 CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
379 /* Set preperiph clock source. */
380 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
381 /* Set periph clock source. */
382 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
383 /* Set periph clock2 clock source. */
384 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
385 /* Set per clock source. */
386 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
387 /* Set clock out1 divider. */
388 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
389 /* Set clock out1 source. */
390 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
391 /* Set clock out2 divider. */
392 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
393 /* Set clock out2 source. */
394 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
395 /* Set clock out1 drives clock out1. */
396 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
397 /* Disable clock out1. */
398 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
399 /* Disable clock out2. */
400 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
401 /* Set SAI1 MCLK1 clock source. */
402 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
403 /* Set SAI1 MCLK2 clock source. */
404 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
405 /* Set SAI1 MCLK3 clock source. */
406 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
407 /* Set SAI2 MCLK3 clock source. */
408 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
409 /* Set SAI3 MCLK3 clock source. */
410 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
411 /* Set MQS configuration. */
412 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
413 /* Set ENET Tx clock source. */
414 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
415 /* Set GPT1 High frequency reference clock source. */
416 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
417 /* Set GPT2 High frequency reference clock source. */
418 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
419 /* Set SystemCoreClock variable. */
420 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
421}
422
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:56:58 +0100