1 files changed, 205 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt685/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt685/project_template/clock_config.c
new file mode 100644
index 000000000..1671b16f3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt685/project_template/clock_config.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up all selectors to provide selected clocks.
+ *
+ * 3. Set up all dividers.
+ */
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: MIMXRT685S
+package_id: MIMXRT685SFVKB
+mcu_data: ksdk2_0
+processor_version: 0.0.2
+board: MIMXRT685-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : BOARD_FlexspiClockSafeConfig
+ * Description   : FLEXSPI clock source safe configuration weak function.
+ *                 Called before clock source(Such as PLL, Main clock) configuration.
+ * Note          : Users need override this function to change FLEXSPI clock source to stable source when executing
+ *                 code on FLEXSPI memory(XIP). If XIP, the function should runs in RAM and move the FLEXSPI clock
+ *source to an stable clock to avoid instruction/data fetch issue during clock updating.
+ *END**************************************************************************/
+__attribute__((weak)) void BOARD_FlexspiClockSafeConfig(void)
+{
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : BOARD_SetFlexspiClock
+ * Description   : This function should be overridden if executing code on FLEXSPI memory(XIP).
+ *                 To Change FLEXSPI clock, should move to run from RAM and then configure FLEXSPI clock source.
+ *                 After the clock is changed and stable,  move back to run on FLEXSPI.
+ * Param src     : FLEXSPI clock source.
+ * Param divider : FLEXSPI clock divider.
+ *END**************************************************************************/
+__attribute__((weak)) void BOARD_SetFlexspiClock(uint32_t src, uint32_t divider)
+{
+    CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src);
+    CLKCTL0->FLEXSPIFCLKDIV |= CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */
+    CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1);
+    while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK)
+    {
+    }
+}
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: DSPRAM_clock.outFreq, value: 24 MHz}
+- {id: DSP_clock.outFreq, value: 48 MHz}
+- {id: FLEXSPI_clock.outFreq, value: 1900.8/19 MHz}
+- {id: I3C_SLOW_clock.outFreq, value: 1 MHz}
+- {id: LPOSC1M_clock.outFreq, value: 1 MHz}
+- {id: OSTIMER_clock.outFreq, value: 1 MHz}
+- {id: System_clock.outFreq, value: 4752/19 MHz}
+- {id: WAKE_32K_clock.outFreq, value: 31.25 kHz}
+- {id: WWDT0_clock.outFreq, value: 1 MHz}
+- {id: WWDT1_clock.outFreq, value: 1 MHz}
+settings:
+- {id: AUDIOPLL0_PFD0_CLK_GATE, value: 'No'}
+- {id: PLL0_PFD0_CLK_GATE, value: 'No'}
+- {id: PLL0_PFD2_CLK_GATE, value: 'No'}
+- {id: SYSCON.AUDIOPLL0CLKSEL.sel, value: SYSCON.SYSOSCBYPASS}
+- {id: SYSCON.AUDIOPLL0_PFD0_DIV.scale, value: '26', locked: true}
+- {id: SYSCON.AUDIOPLLCLKDIV.scale, value: '15', locked: true}
+- {id: SYSCON.AUDIO_PLL0_PFD0_MUL.scale, value: '18', locked: true}
+- {id: SYSCON.FLEXSPIFCLKDIV.scale, value: '5', locked: true}
+- {id: SYSCON.FLEXSPIFCLKSEL.sel, value: SYSCON.MAINPLLCLKDIV}
+- {id: SYSCON.FRGPLLCLKDIV.scale, value: '12', locked: true}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.MAINPLLCLKDIV}
+- {id: SYSCON.PFC1DIV.scale, value: '1', locked: true}
+- {id: SYSCON.PLL0.denom, value: '1'}
+- {id: SYSCON.PLL0.div, value: '22', locked: true}
+- {id: SYSCON.PLL0.num, value: '0'}
+- {id: SYSCON.PLL0_PFD0_DIV.scale, value: '19', locked: true}
+- {id: SYSCON.PLL0_PFD0_MUL.scale, value: '18', locked: true}
+- {id: SYSCON.PLL0_PFD2_DIV.scale, value: '24', locked: true}
+- {id: SYSCON.PLL0_PFD2_MUL.scale, value: '18', locked: true}
+- {id: SYSCON.PLL1.denom, value: '27000', locked: true}
+- {id: SYSCON.PLL1.div, value: '22'}
+- {id: SYSCON.PLL1.num, value: '5040', locked: true}
+- {id: SYSCON.SYSCPUAHBCLKDIV.scale, value: '2'}
+- {id: SYSCON.SYSPLL0CLKSEL.sel, value: SYSCON.SYSOSCBYPASS}
+- {id: SYSCTL_PDRUNCFG_AUDIOPLL_CFG, value: 'No'}
+- {id: SYSCTL_PDRUNCFG_SYSPLL_CFG, value: 'No'}
+- {id: SYSCTL_PDRUNCFG_SYSXTAL_CFG, value: Power_up}
+- {id: XTAL_LP_Enable, value: LowPowerMode}
+sources:
+- {id: SYSCON.XTAL.outFreq, value: 24 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t g_sysPllConfig_BOARD_BootClockRUN = {
+    .sys_pll_src  = kCLOCK_SysPllXtalIn, /* OSC clock */
+    .numerator    = 0,                   /* Numerator of the SYSPLL0 fractional loop divider isnull */
+    .denominator  = 1,                   /* Denominator of the SYSPLL0 fractional loop divider isnull */
+    .sys_pll_mult = kCLOCK_SysPllMult22  /* Divide by 22 */
+};
+const clock_audio_pll_config_t g_audioPllConfig_BOARD_BootClockRUN = {
+    .audio_pll_src  = kCLOCK_AudioPllXtalIn, /* OSC clock */
+    .numerator      = 5040,                  /* Numerator of the SYSPLL0 fractional loop divider isnull */
+    .denominator    = 27000,                 /* Denominator of the SYSPLL0 fractional loop divider isnull */
+    .audio_pll_mult = kCLOCK_AudioPllMult22  /* Divide by 22 */
+};
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Configure LPOSC clock*/
+    POWER_DisablePD(kPDRUNCFG_PD_LPOSC); /* Power on LPOSC (1MHz) */
+    /* Configure FFRO clock */
+    POWER_DisablePD(kPDRUNCFG_PD_FFRO);  /* Power on FFRO (48/60MHz) */
+    CLOCK_EnableFfroClk(kCLOCK_Ffro48M); /* Enable FFRO clock*/
+    /* Configure SFRO clock */
+    POWER_DisablePD(kPDRUNCFG_PD_SFRO); /* Power on SFRO (16MHz) */
+    CLOCK_EnableSfroClk();              /* Wait until SFRO stable */
+    /* Call function BOARD_FlexspiClockSafeConfig() to move FLEXSPI clock to a stable clock source to avoid
+       instruction/data fetch issue when updating PLL and Main clock if XIP(execute code on FLEXSPI memory). */
+    BOARD_FlexspiClockSafeConfig();
+    /* Let CPU run on ffro for safe switching */
+    CLOCK_AttachClk(kFFRO_to_MAIN_CLK);
+    /* Configure SYSOSC clock source */
+    POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL);                       /* Power on SYSXTAL */
+    POWER_UpdateOscSettlingTime(BOARD_SYSOSC_SETTLING_US);       /* Updated XTAL oscillator settling time */
+    CLOCK_EnableSysOscClk(true, true, BOARD_SYSOSC_SETTLING_US); /* Enable system OSC */
+    CLOCK_SetXtalFreq(BOARD_XTAL_SYS_CLK_HZ);                    /* Sets external XTAL OSC freq */
+    /* Configure SysPLL0 clock source */
+    CLOCK_InitSysPll(&g_sysPllConfig_BOARD_BootClockRUN);
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 19); /* Enable MAIN PLL clock */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); /* Enable AUX0 PLL clock */
+    /* Configure Audio PLL clock source */
+    CLOCK_InitAudioPll(&g_audioPllConfig_BOARD_BootClockRUN);
+    CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26); /* Enable Audio PLL clock */
+    CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); /* Set SYSCPUAHBCLKDIV divider to value 2 */
+    /* Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); /* Switch MAIN_CLK to MAIN_PLL */
+    /* Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); /* Set AUDIOPLLCLKDIV divider to value 15 */
+    CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 12U);   /* Set FRGPLLCLKDIV divider to value 12 */
+    /* Call weak function BOARD_SetFlexspiClock() to set user configured clock source/divider for FLEXSPI. */
+    BOARD_SetFlexspiClock(1U, 5U);
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}

diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt685/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt685/project_template/clock_config.c new file mode 100644 index 000000000..1671b16f3 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt685/project_template/clock_config.c
@@ -0,0 +1,205 @@
	1	/*
	2	* Copyright 2019 NXP
	3	*
	4	* SPDX-License-Identifier: BSD-3-Clause
	5	*/
	6
	7	/***********************************************************************************************************************
	8	* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
	9	* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
	10	**********************************************************************************************************************/
	11	/*
	12	* How to set up clock using clock driver functions:
	13	*
	14	* 1. Setup clock sources.
	15	*
	16	* 2. Set up all selectors to provide selected clocks.
	17	*
	18	* 3. Set up all dividers.
	19	*/
	20
	21	/* clang-format off */
	22	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	23	!!GlobalInfo
	24	product: Clocks v7.0
	25	processor: MIMXRT685S
	26	package_id: MIMXRT685SFVKB
	27	mcu_data: ksdk2_0
	28	processor_version: 0.0.2
	29	board: MIMXRT685-EVK
	30	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	31	/* clang-format on */
	32
	33	#include "fsl_power.h"
	34	#include "fsl_clock.h"
	35	#include "clock_config.h"
	36
	37	/*******************************************************************************
	38	* Definitions
	39	******************************************************************************/
	40
	41	/*******************************************************************************
	42	* Variables
	43	******************************************************************************/
	44	/* System clock frequency. */
	45	extern uint32_t SystemCoreClock;
	46
	47	/FUNCTION*********************************************************************
	48	*
	49	* Function Name : BOARD_FlexspiClockSafeConfig
	50	* Description : FLEXSPI clock source safe configuration weak function.
	51	* Called before clock source(Such as PLL, Main clock) configuration.
	52	* Note : Users need override this function to change FLEXSPI clock source to stable source when executing
	53	* code on FLEXSPI memory(XIP). If XIP, the function should runs in RAM and move the FLEXSPI clock
	54	*source to an stable clock to avoid instruction/data fetch issue during clock updating.
	55	END*************************************************************************/
	56	__attribute__((weak)) void BOARD_FlexspiClockSafeConfig(void)
	57	{
	58	}
	59
	60	/FUNCTION*********************************************************************
	61	*
	62	* Function Name : BOARD_SetFlexspiClock
	63	* Description : This function should be overridden if executing code on FLEXSPI memory(XIP).
	64	* To Change FLEXSPI clock, should move to run from RAM and then configure FLEXSPI clock source.
	65	* After the clock is changed and stable, move back to run on FLEXSPI.
	66	* Param src : FLEXSPI clock source.
	67	* Param divider : FLEXSPI clock divider.
	68	END*************************************************************************/
	69	__attribute__((weak)) void BOARD_SetFlexspiClock(uint32_t src, uint32_t divider)
	70	{
	71	CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src);
	72	CLKCTL0->FLEXSPIFCLKDIV \|= CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */
	73	CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1);
	74	while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK)
	75	{
	76	}
	77	}
	78
	79	/*******************************************************************************
	80	********************** BOARD_InitBootClocks function **********************
	81	******************************************************************************/
	82	void BOARD_InitBootClocks(void)
	83	{
	84	BOARD_BootClockRUN();
	85	}
	86
	87	/*******************************************************************************
	88	******************** Configuration BOARD_BootClockRUN *********************
	89	******************************************************************************/
	90	/* clang-format off */
	91	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	92	!!Configuration
	93	name: BOARD_BootClockRUN
	94	called_from_default_init: true
	95	outputs:
	96	- {id: DSPRAM_clock.outFreq, value: 24 MHz}
	97	- {id: DSP_clock.outFreq, value: 48 MHz}
	98	- {id: FLEXSPI_clock.outFreq, value: 1900.8/19 MHz}
	99	- {id: I3C_SLOW_clock.outFreq, value: 1 MHz}
	100	- {id: LPOSC1M_clock.outFreq, value: 1 MHz}
	101	- {id: OSTIMER_clock.outFreq, value: 1 MHz}
	102	- {id: System_clock.outFreq, value: 4752/19 MHz}
	103	- {id: WAKE_32K_clock.outFreq, value: 31.25 kHz}
	104	- {id: WWDT0_clock.outFreq, value: 1 MHz}
	105	- {id: WWDT1_clock.outFreq, value: 1 MHz}
	106	settings:
	107	- {id: AUDIOPLL0_PFD0_CLK_GATE, value: 'No'}
	108	- {id: PLL0_PFD0_CLK_GATE, value: 'No'}
	109	- {id: PLL0_PFD2_CLK_GATE, value: 'No'}
	110	- {id: SYSCON.AUDIOPLL0CLKSEL.sel, value: SYSCON.SYSOSCBYPASS}
	111	- {id: SYSCON.AUDIOPLL0_PFD0_DIV.scale, value: '26', locked: true}
	112	- {id: SYSCON.AUDIOPLLCLKDIV.scale, value: '15', locked: true}
	113	- {id: SYSCON.AUDIO_PLL0_PFD0_MUL.scale, value: '18', locked: true}
	114	- {id: SYSCON.FLEXSPIFCLKDIV.scale, value: '5', locked: true}
	115	- {id: SYSCON.FLEXSPIFCLKSEL.sel, value: SYSCON.MAINPLLCLKDIV}
	116	- {id: SYSCON.FRGPLLCLKDIV.scale, value: '12', locked: true}
	117	- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.MAINPLLCLKDIV}
	118	- {id: SYSCON.PFC1DIV.scale, value: '1', locked: true}
	119	- {id: SYSCON.PLL0.denom, value: '1'}
	120	- {id: SYSCON.PLL0.div, value: '22', locked: true}
	121	- {id: SYSCON.PLL0.num, value: '0'}
	122	- {id: SYSCON.PLL0_PFD0_DIV.scale, value: '19', locked: true}
	123	- {id: SYSCON.PLL0_PFD0_MUL.scale, value: '18', locked: true}
	124	- {id: SYSCON.PLL0_PFD2_DIV.scale, value: '24', locked: true}
	125	- {id: SYSCON.PLL0_PFD2_MUL.scale, value: '18', locked: true}
	126	- {id: SYSCON.PLL1.denom, value: '27000', locked: true}
	127	- {id: SYSCON.PLL1.div, value: '22'}
	128	- {id: SYSCON.PLL1.num, value: '5040', locked: true}
	129	- {id: SYSCON.SYSCPUAHBCLKDIV.scale, value: '2'}
	130	- {id: SYSCON.SYSPLL0CLKSEL.sel, value: SYSCON.SYSOSCBYPASS}
	131	- {id: SYSCTL_PDRUNCFG_AUDIOPLL_CFG, value: 'No'}
	132	- {id: SYSCTL_PDRUNCFG_SYSPLL_CFG, value: 'No'}
	133	- {id: SYSCTL_PDRUNCFG_SYSXTAL_CFG, value: Power_up}
	134	- {id: XTAL_LP_Enable, value: LowPowerMode}
	135	sources:
	136	- {id: SYSCON.XTAL.outFreq, value: 24 MHz, enabled: true}
	137	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	138	/* clang-format on */
	139
	140	/*******************************************************************************
	141	* Variables for BOARD_BootClockRUN configuration
	142	******************************************************************************/
	143	const clock_sys_pll_config_t g_sysPllConfig_BOARD_BootClockRUN = {
	144	.sys_pll_src = kCLOCK_SysPllXtalIn, /* OSC clock */
	145	.numerator = 0, /* Numerator of the SYSPLL0 fractional loop divider isnull */
	146	.denominator = 1, /* Denominator of the SYSPLL0 fractional loop divider isnull */
	147	.sys_pll_mult = kCLOCK_SysPllMult22 /* Divide by 22 */
	148	};
	149	const clock_audio_pll_config_t g_audioPllConfig_BOARD_BootClockRUN = {
	150	.audio_pll_src = kCLOCK_AudioPllXtalIn, /* OSC clock */
	151	.numerator = 5040, /* Numerator of the SYSPLL0 fractional loop divider isnull */
	152	.denominator = 27000, /* Denominator of the SYSPLL0 fractional loop divider isnull */
	153	.audio_pll_mult = kCLOCK_AudioPllMult22 /* Divide by 22 */
	154	};
	155	/*******************************************************************************
	156	* Code for BOARD_BootClockRUN configuration
	157	******************************************************************************/
	158	void BOARD_BootClockRUN(void)
	159	{
	160	/* Configure LPOSC clock*/
	161	POWER_DisablePD(kPDRUNCFG_PD_LPOSC); /* Power on LPOSC (1MHz) */
	162	/* Configure FFRO clock */
	163	POWER_DisablePD(kPDRUNCFG_PD_FFRO); /* Power on FFRO (48/60MHz) */
	164	CLOCK_EnableFfroClk(kCLOCK_Ffro48M); /* Enable FFRO clock*/
	165	/* Configure SFRO clock */
	166	POWER_DisablePD(kPDRUNCFG_PD_SFRO); /* Power on SFRO (16MHz) */
	167	CLOCK_EnableSfroClk(); /* Wait until SFRO stable */
	168
	169	/* Call function BOARD_FlexspiClockSafeConfig() to move FLEXSPI clock to a stable clock source to avoid
	170	instruction/data fetch issue when updating PLL and Main clock if XIP(execute code on FLEXSPI memory). */
	171	BOARD_FlexspiClockSafeConfig();
	172
	173	/* Let CPU run on ffro for safe switching */
	174	CLOCK_AttachClk(kFFRO_to_MAIN_CLK);
	175
	176	/* Configure SYSOSC clock source */
	177	POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL); /* Power on SYSXTAL */
	178	POWER_UpdateOscSettlingTime(BOARD_SYSOSC_SETTLING_US); /* Updated XTAL oscillator settling time */
	179	CLOCK_EnableSysOscClk(true, true, BOARD_SYSOSC_SETTLING_US); /* Enable system OSC */
	180	CLOCK_SetXtalFreq(BOARD_XTAL_SYS_CLK_HZ); /* Sets external XTAL OSC freq */
	181
	182	/* Configure SysPLL0 clock source */
	183	CLOCK_InitSysPll(&g_sysPllConfig_BOARD_BootClockRUN);
	184	CLOCK_InitSysPfd(kCLOCK_Pfd0, 19); /* Enable MAIN PLL clock */
	185	CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); /* Enable AUX0 PLL clock */
	186
	187	/* Configure Audio PLL clock source */
	188	CLOCK_InitAudioPll(&g_audioPllConfig_BOARD_BootClockRUN);
	189	CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26); /* Enable Audio PLL clock */
	190
	191	CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); /* Set SYSCPUAHBCLKDIV divider to value 2 */
	192
	193	/* Set up clock selectors - Attach clocks to the peripheries */
	194	CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); /* Switch MAIN_CLK to MAIN_PLL */
	195
	196	/* Set up dividers */
	197	CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); /* Set AUDIOPLLCLKDIV divider to value 15 */
	198	CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 12U); /* Set FRGPLLCLKDIV divider to value 12 */
	199
	200	/* Call weak function BOARD_SetFlexspiClock() to set user configured clock source/divider for FLEXSPI. */
	201	BOARD_SetFlexspiClock(1U, 5U);
	202
	203	/< Set SystemCoreClock variable. /
	204	SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
	205	}