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diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt685/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt685/project_template/pin_mux.c
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@@ -0,0 +1,1192 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7/***********************************************************************************************************************
8 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
9 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
10 **********************************************************************************************************************/
11
12/* clang-format off */
13/*
14 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Pins v7.0
17processor: MIMXRT685S
18package_id: MIMXRT685SFVKB
19mcu_data: ksdk2_0
20processor_version: 0.0.2
21board: MIMXRT685-EVK
22 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
23 */
24/* clang-format on */
25
26#include "fsl_common.h"
27#include "fsl_gpio.h"
28#include "fsl_iopctl.h"
29#include "pin_mux.h"
30
31/* FUNCTION ************************************************************************************************************
32 *
33 * Function Name : BOARD_InitBootPins
34 * Description : Calls initialization functions.
35 *
36 * END ****************************************************************************************************************/
37void BOARD_InitBootPins(void)
38{
39 BOARD_InitPins();
40 BOARD_InitDEBUG_UARTPins();
41}
42
43/* clang-format off */
44/*
45 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
46BOARD_InitPins:
47- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'}
48- pin_list: []
49 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
50 */
51/* clang-format on */
52
53/* FUNCTION ************************************************************************************************************
54 *
55 * Function Name : BOARD_InitPins
56 * Description : Configures pin routing and optionally pin electrical features.
57 *
58 * END ****************************************************************************************************************/
59/* Function assigned for the Cortex-M33 */
60void BOARD_InitPins(void)
61{
62}
63
64/* clang-format off */
65/*
66 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
67BOARD_InitDEBUG_UARTPins:
68- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'}
69- pin_list:
70 - {pin_num: G4, peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_2/FC0_RXD_SDA_MOSI_DATA/CTIMER0_MAT2/I2S_BRIDGE_DATA_IN/SEC_PIO0_2, pupdena: disabled,
71 pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
72 - {pin_num: G2, peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_1/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT1/I2S_BRIDGE_WS_IN/SEC_PIO0_1, pupdena: disabled,
73 pupdsel: pullDown, ibena: disabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
74 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
75 */
76/* clang-format on */
77
78/* FUNCTION ************************************************************************************************************
79 *
80 * Function Name : BOARD_InitDEBUG_UARTPins
81 * Description : Configures pin routing and optionally pin electrical features.
82 *
83 * END ****************************************************************************************************************/
84/* Function assigned for the Cortex-M33 */
85void BOARD_InitDEBUG_UARTPins(void)
86{
87
88 const uint32_t port0_pin1_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
89 IOPCTL_PIO_FUNC1 |
90 /* Disable pull-up / pull-down function */
91 IOPCTL_PIO_PUPD_DI |
92 /* Enable pull-down function */
93 IOPCTL_PIO_PULLDOWN_EN |
94 /* Disable input buffer function */
95 IOPCTL_PIO_INBUF_DI |
96 /* Normal mode */
97 IOPCTL_PIO_SLEW_RATE_NORMAL |
98 /* Normal drive */
99 IOPCTL_PIO_FULLDRIVE_DI |
100 /* Analog mux is disabled */
101 IOPCTL_PIO_ANAMUX_DI |
102 /* Pseudo Output Drain is disabled */
103 IOPCTL_PIO_PSEDRAIN_DI |
104 /* Input function is not inverted */
105 IOPCTL_PIO_INV_DI);
106 /* PORT0 PIN1 (coords: G2) is configured as FC0_TXD_SCL_MISO_WS */
107 IOPCTL_PinMuxSet(IOPCTL, 0U, 1U, port0_pin1_config);
108
109 const uint32_t port0_pin2_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
110 IOPCTL_PIO_FUNC1 |
111 /* Disable pull-up / pull-down function */
112 IOPCTL_PIO_PUPD_DI |
113 /* Enable pull-down function */
114 IOPCTL_PIO_PULLDOWN_EN |
115 /* Enables input buffer function */
116 IOPCTL_PIO_INBUF_EN |
117 /* Normal mode */
118 IOPCTL_PIO_SLEW_RATE_NORMAL |
119 /* Normal drive */
120 IOPCTL_PIO_FULLDRIVE_DI |
121 /* Analog mux is disabled */
122 IOPCTL_PIO_ANAMUX_DI |
123 /* Pseudo Output Drain is disabled */
124 IOPCTL_PIO_PSEDRAIN_DI |
125 /* Input function is not inverted */
126 IOPCTL_PIO_INV_DI);
127 /* PORT0 PIN2 (coords: G4) is configured as FC0_RXD_SDA_MOSI_DATA */
128 IOPCTL_PinMuxSet(IOPCTL, 0U, 2U, port0_pin2_config);
129}
130
131/* clang-format off */
132/*
133 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
134BOARD_InitFlexSPIFlashPins:
135- options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'}
136- pin_list:
137 - {pin_num: L2, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA0, pin_signal: PIO1_11/HS_SPI_SCK/CTIMER2_MAT0/FLEXSPI0B_DATA0, pupdena: disabled, pupdsel: pullDown,
138 ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
139 - {pin_num: M2, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA1, pin_signal: PIO1_12/HS_SPI_MISO/CTIMER2_MAT1/FLEXSPI0B_DATA1, pupdena: disabled, pupdsel: pullDown,
140 ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
141 - {pin_num: N1, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA2, pin_signal: PIO1_13/HS_SPI_MOSI/CTIMER2_MAT2/FLEXSPI0B_DATA2, pupdena: disabled, pupdsel: pullDown,
142 ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
143 - {pin_num: N2, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA3, pin_signal: PIO1_14/HS_SPI_SSEL0/CTIMER2_MAT3/FLEXSPI0B_DATA3, pupdena: disabled, pupdsel: pullDown,
144 ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
145 - {pin_num: U1, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA4, pin_signal: PIO2_17/PDM_CLK23/FLEXSPI0B_DATA4, pupdena: disabled, pupdsel: pullDown, ibena: enabled,
146 slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
147 - {pin_num: R2, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA5, pin_signal: PIO2_18/PDM_CLK45/FLEXSPI0B_DATA5, pupdena: disabled, pupdsel: pullDown, ibena: enabled,
148 slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
149 - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA6, pin_signal: PIO2_22/PDM_DATA45/FLEXSPI0B_DATA6, pupdena: disabled, pupdsel: pullDown, ibena: enabled,
150 slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
151 - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA7, pin_signal: PIO2_23/PDM_DATA67/FLEXSPI0B_DATA7, pupdena: disabled, pupdsel: pullDown, ibena: enabled,
152 slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
153 - {pin_num: T2, peripheral: FLEXSPI, signal: FLEXSPI_B_SS0_B, pin_signal: PIO2_19/PDM_CLK67/FLEXSPI0B_SS0_N, pupdena: disabled, pupdsel: pullDown, ibena: enabled,
154 slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
155 - {pin_num: U3, peripheral: FLEXSPI, signal: FLEXSPI_B_SCLK, pin_signal: PIO1_29/FLEXSPI0A_SS1_N/SCT0_OUT5/UTICK_CAP2/CTIMER_INP13/FLEXSPI0B_SCLK, pupdena: disabled,
156 pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
157 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
158 */
159/* clang-format on */
160
161/* FUNCTION ************************************************************************************************************
162 *
163 * Function Name : BOARD_InitFlexSPIFlashPins
164 * Description : Configures pin routing and optionally pin electrical features.
165 *
166 * END ****************************************************************************************************************/
167/* Function assigned for the Cortex-M33 */
168void BOARD_InitFlexSPIFlashPins(void)
169{
170
171 const uint32_t port1_pin11_config = (/* Pin is configured as FLEXSPI0B_DATA0 */
172 IOPCTL_PIO_FUNC6 |
173 /* Disable pull-up / pull-down function */
174 IOPCTL_PIO_PUPD_DI |
175 /* Enable pull-down function */
176 IOPCTL_PIO_PULLDOWN_EN |
177 /* Enables input buffer function */
178 IOPCTL_PIO_INBUF_EN |
179 /* Normal mode */
180 IOPCTL_PIO_SLEW_RATE_NORMAL |
181 /* Normal drive */
182 IOPCTL_PIO_FULLDRIVE_DI |
183 /* Analog mux is disabled */
184 IOPCTL_PIO_ANAMUX_DI |
185 /* Pseudo Output Drain is disabled */
186 IOPCTL_PIO_PSEDRAIN_DI |
187 /* Input function is not inverted */
188 IOPCTL_PIO_INV_DI);
189 /* PORT1 PIN11 (coords: L2) is configured as FLEXSPI0B_DATA0 */
190 IOPCTL_PinMuxSet(IOPCTL, 1U, 11U, port1_pin11_config);
191
192 const uint32_t port1_pin12_config = (/* Pin is configured as FLEXSPI0B_DATA1 */
193 IOPCTL_PIO_FUNC6 |
194 /* Disable pull-up / pull-down function */
195 IOPCTL_PIO_PUPD_DI |
196 /* Enable pull-down function */
197 IOPCTL_PIO_PULLDOWN_EN |
198 /* Enables input buffer function */
199 IOPCTL_PIO_INBUF_EN |
200 /* Normal mode */
201 IOPCTL_PIO_SLEW_RATE_NORMAL |
202 /* Full drive enable */
203 IOPCTL_PIO_FULLDRIVE_EN |
204 /* Analog mux is disabled */
205 IOPCTL_PIO_ANAMUX_DI |
206 /* Pseudo Output Drain is disabled */
207 IOPCTL_PIO_PSEDRAIN_DI |
208 /* Input function is not inverted */
209 IOPCTL_PIO_INV_DI);
210 /* PORT1 PIN12 (coords: M2) is configured as FLEXSPI0B_DATA1 */
211 IOPCTL_PinMuxSet(IOPCTL, 1U, 12U, port1_pin12_config);
212
213 const uint32_t port1_pin13_config = (/* Pin is configured as FLEXSPI0B_DATA2 */
214 IOPCTL_PIO_FUNC6 |
215 /* Disable pull-up / pull-down function */
216 IOPCTL_PIO_PUPD_DI |
217 /* Enable pull-down function */
218 IOPCTL_PIO_PULLDOWN_EN |
219 /* Enables input buffer function */
220 IOPCTL_PIO_INBUF_EN |
221 /* Normal mode */
222 IOPCTL_PIO_SLEW_RATE_NORMAL |
223 /* Full drive enable */
224 IOPCTL_PIO_FULLDRIVE_EN |
225 /* Analog mux is disabled */
226 IOPCTL_PIO_ANAMUX_DI |
227 /* Pseudo Output Drain is disabled */
228 IOPCTL_PIO_PSEDRAIN_DI |
229 /* Input function is not inverted */
230 IOPCTL_PIO_INV_DI);
231 /* PORT1 PIN13 (coords: N1) is configured as FLEXSPI0B_DATA2 */
232 IOPCTL_PinMuxSet(IOPCTL, 1U, 13U, port1_pin13_config);
233
234 const uint32_t port1_pin14_config = (/* Pin is configured as FLEXSPI0B_DATA3 */
235 IOPCTL_PIO_FUNC6 |
236 /* Disable pull-up / pull-down function */
237 IOPCTL_PIO_PUPD_DI |
238 /* Enable pull-down function */
239 IOPCTL_PIO_PULLDOWN_EN |
240 /* Enables input buffer function */
241 IOPCTL_PIO_INBUF_EN |
242 /* Normal mode */
243 IOPCTL_PIO_SLEW_RATE_NORMAL |
244 /* Full drive enable */
245 IOPCTL_PIO_FULLDRIVE_EN |
246 /* Analog mux is disabled */
247 IOPCTL_PIO_ANAMUX_DI |
248 /* Pseudo Output Drain is disabled */
249 IOPCTL_PIO_PSEDRAIN_DI |
250 /* Input function is not inverted */
251 IOPCTL_PIO_INV_DI);
252 /* PORT1 PIN14 (coords: N2) is configured as FLEXSPI0B_DATA3 */
253 IOPCTL_PinMuxSet(IOPCTL, 1U, 14U, port1_pin14_config);
254
255 const uint32_t port1_pin29_config = (/* Pin is configured as FLEXSPI0B_SCLK */
256 IOPCTL_PIO_FUNC5 |
257 /* Disable pull-up / pull-down function */
258 IOPCTL_PIO_PUPD_DI |
259 /* Enable pull-down function */
260 IOPCTL_PIO_PULLDOWN_EN |
261 /* Enables input buffer function */
262 IOPCTL_PIO_INBUF_EN |
263 /* Normal mode */
264 IOPCTL_PIO_SLEW_RATE_NORMAL |
265 /* Full drive enable */
266 IOPCTL_PIO_FULLDRIVE_EN |
267 /* Analog mux is disabled */
268 IOPCTL_PIO_ANAMUX_DI |
269 /* Pseudo Output Drain is disabled */
270 IOPCTL_PIO_PSEDRAIN_DI |
271 /* Input function is not inverted */
272 IOPCTL_PIO_INV_DI);
273 /* PORT1 PIN29 (coords: U3) is configured as FLEXSPI0B_SCLK */
274 IOPCTL_PinMuxSet(IOPCTL, 1U, 29U, port1_pin29_config);
275
276 const uint32_t port2_pin17_config = (/* Pin is configured as FLEXSPI0B_DATA4 */
277 IOPCTL_PIO_FUNC6 |
278 /* Disable pull-up / pull-down function */
279 IOPCTL_PIO_PUPD_DI |
280 /* Enable pull-down function */
281 IOPCTL_PIO_PULLDOWN_EN |
282 /* Enables input buffer function */
283 IOPCTL_PIO_INBUF_EN |
284 /* Normal mode */
285 IOPCTL_PIO_SLEW_RATE_NORMAL |
286 /* Full drive enable */
287 IOPCTL_PIO_FULLDRIVE_EN |
288 /* Analog mux is disabled */
289 IOPCTL_PIO_ANAMUX_DI |
290 /* Pseudo Output Drain is disabled */
291 IOPCTL_PIO_PSEDRAIN_DI |
292 /* Input function is not inverted */
293 IOPCTL_PIO_INV_DI);
294 /* PORT2 PIN17 (coords: U1) is configured as FLEXSPI0B_DATA4 */
295 IOPCTL_PinMuxSet(IOPCTL, 2U, 17U, port2_pin17_config);
296
297 const uint32_t port2_pin18_config = (/* Pin is configured as FLEXSPI0B_DATA5 */
298 IOPCTL_PIO_FUNC6 |
299 /* Disable pull-up / pull-down function */
300 IOPCTL_PIO_PUPD_DI |
301 /* Enable pull-down function */
302 IOPCTL_PIO_PULLDOWN_EN |
303 /* Enables input buffer function */
304 IOPCTL_PIO_INBUF_EN |
305 /* Normal mode */
306 IOPCTL_PIO_SLEW_RATE_NORMAL |
307 /* Full drive enable */
308 IOPCTL_PIO_FULLDRIVE_EN |
309 /* Analog mux is disabled */
310 IOPCTL_PIO_ANAMUX_DI |
311 /* Pseudo Output Drain is disabled */
312 IOPCTL_PIO_PSEDRAIN_DI |
313 /* Input function is not inverted */
314 IOPCTL_PIO_INV_DI);
315 /* PORT2 PIN18 (coords: R2) is configured as FLEXSPI0B_DATA5 */
316 IOPCTL_PinMuxSet(IOPCTL, 2U, 18U, port2_pin18_config);
317
318 const uint32_t port2_pin19_config = (/* Pin is configured as FLEXSPI0B_SS0_N */
319 IOPCTL_PIO_FUNC6 |
320 /* Disable pull-up / pull-down function */
321 IOPCTL_PIO_PUPD_DI |
322 /* Enable pull-down function */
323 IOPCTL_PIO_PULLDOWN_EN |
324 /* Enables input buffer function */
325 IOPCTL_PIO_INBUF_EN |
326 /* Normal mode */
327 IOPCTL_PIO_SLEW_RATE_NORMAL |
328 /* Full drive enable */
329 IOPCTL_PIO_FULLDRIVE_EN |
330 /* Analog mux is disabled */
331 IOPCTL_PIO_ANAMUX_DI |
332 /* Pseudo Output Drain is disabled */
333 IOPCTL_PIO_PSEDRAIN_DI |
334 /* Input function is not inverted */
335 IOPCTL_PIO_INV_DI);
336 /* PORT2 PIN19 (coords: T2) is configured as FLEXSPI0B_SS0_N */
337 IOPCTL_PinMuxSet(IOPCTL, 2U, 19U, port2_pin19_config);
338
339 const uint32_t port2_pin22_config = (/* Pin is configured as FLEXSPI0B_DATA6 */
340 IOPCTL_PIO_FUNC6 |
341 /* Disable pull-up / pull-down function */
342 IOPCTL_PIO_PUPD_DI |
343 /* Enable pull-down function */
344 IOPCTL_PIO_PULLDOWN_EN |
345 /* Enables input buffer function */
346 IOPCTL_PIO_INBUF_EN |
347 /* Normal mode */
348 IOPCTL_PIO_SLEW_RATE_NORMAL |
349 /* Full drive enable */
350 IOPCTL_PIO_FULLDRIVE_EN |
351 /* Analog mux is disabled */
352 IOPCTL_PIO_ANAMUX_DI |
353 /* Pseudo Output Drain is disabled */
354 IOPCTL_PIO_PSEDRAIN_DI |
355 /* Input function is not inverted */
356 IOPCTL_PIO_INV_DI);
357 /* PORT2 PIN22 (coords: P3) is configured as FLEXSPI0B_DATA6 */
358 IOPCTL_PinMuxSet(IOPCTL, 2U, 22U, port2_pin22_config);
359
360 const uint32_t port2_pin23_config = (/* Pin is configured as FLEXSPI0B_DATA7 */
361 IOPCTL_PIO_FUNC6 |
362 /* Disable pull-up / pull-down function */
363 IOPCTL_PIO_PUPD_DI |
364 /* Enable pull-down function */
365 IOPCTL_PIO_PULLDOWN_EN |
366 /* Enables input buffer function */
367 IOPCTL_PIO_INBUF_EN |
368 /* Normal mode */
369 IOPCTL_PIO_SLEW_RATE_NORMAL |
370 /* Full drive enable */
371 IOPCTL_PIO_FULLDRIVE_EN |
372 /* Analog mux is disabled */
373 IOPCTL_PIO_ANAMUX_DI |
374 /* Pseudo Output Drain is disabled */
375 IOPCTL_PIO_PSEDRAIN_DI |
376 /* Input function is not inverted */
377 IOPCTL_PIO_INV_DI);
378 /* PORT2 PIN23 (coords: P5) is configured as FLEXSPI0B_DATA7 */
379 IOPCTL_PinMuxSet(IOPCTL, 2U, 23U, port2_pin23_config);
380}
381
382/* clang-format off */
383/*
384 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
385BOARD_InitPSRAMPins:
386- options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'}
387- pin_list:
388 - {pin_num: T5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: PIO1_20/FLEXSPI0A_DATA0/SCT0_GPI1/CTIMER4_MAT1}
389 - {pin_num: U5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: PIO1_21/FLEXSPI0A_DATA1/SCT0_OUT1/CTIMER4_MAT2}
390 - {pin_num: P6, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: PIO1_22/FLEXSPI0A_DATA2/SCT0_GPI2/CTIMER4_MAT3, pupdena: disabled, pupdsel: pullDown,
391 ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
392 - {pin_num: P7, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: PIO1_23/FLEXSPI0A_DATA3/SCT0_OUT2/CTIMER_INP8, pupdena: disabled, pupdsel: pullDown, ibena: enabled,
393 slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
394 - {pin_num: T7, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA4, pin_signal: PIO1_24/FLEXSPI0A_DATA4/SCT0_GPI3, pupdena: disabled, pupdsel: pullDown, ibena: enabled,
395 slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
396 - {pin_num: U7, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA5, pin_signal: PIO1_25/FLEXSPI0A_DATA5/SCT0_OUT3, pupdena: disabled, pupdsel: pullDown, ibena: enabled,
397 slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
398 - {pin_num: R7, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA6, pin_signal: PIO1_26/FLEXSPI0A_DATA6/SCT0_GPI4, pupdena: disabled, pupdsel: pullDown, ibena: enabled,
399 slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
400 - {pin_num: T8, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA7, pin_signal: PIO1_27/FLEXSPI0A_DATA7/SCT0_OUT4, pupdena: disabled, pupdsel: pullDown, ibena: enabled,
401 slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
402 - {pin_num: U9, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: PIO1_28/FLEXSPI0A_DQS/SCT0_GPI5, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal,
403 drive: full, amena: disabled, odena: disabled, iiena: disabled}
404 - {pin_num: T9, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: PIO1_18/FLEXSPI0A_SCLK/SCT0_GPI0/CTIMER3_MAT3, pupdena: disabled, pupdsel: pullDown, ibena: enabled,
405 slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
406 - {pin_num: T4, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: PIO1_19/FLEXSPI0A_SS0_N/SCT0_OUT0/CTIMER4_MAT0, pupdena: disabled, pupdsel: pullDown,
407 ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled}
408 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
409 */
410/* clang-format on */
411
412/* FUNCTION ************************************************************************************************************
413 *
414 * Function Name : BOARD_InitPSRAMPins
415 * Description : Configures pin routing and optionally pin electrical features.
416 *
417 * END ****************************************************************************************************************/
418/* Function assigned for the Cortex-M33 */
419void BOARD_InitPSRAMPins(void)
420{
421
422 const uint32_t port1_pin18_config = (/* Pin is configured as FLEXSPI0A_SCLK */
423 IOPCTL_PIO_FUNC1 |
424 /* Disable pull-up / pull-down function */
425 IOPCTL_PIO_PUPD_DI |
426 /* Enable pull-down function */
427 IOPCTL_PIO_PULLDOWN_EN |
428 /* Enables input buffer function */
429 IOPCTL_PIO_INBUF_EN |
430 /* Normal mode */
431 IOPCTL_PIO_SLEW_RATE_NORMAL |
432 /* Full drive enable */
433 IOPCTL_PIO_FULLDRIVE_EN |
434 /* Analog mux is disabled */
435 IOPCTL_PIO_ANAMUX_DI |
436 /* Pseudo Output Drain is disabled */
437 IOPCTL_PIO_PSEDRAIN_DI |
438 /* Input function is not inverted */
439 IOPCTL_PIO_INV_DI);
440 /* PORT1 PIN18 (coords: T9) is configured as FLEXSPI0A_SCLK */
441 IOPCTL_PinMuxSet(IOPCTL, 1U, 18U, port1_pin18_config);
442
443 const uint32_t port1_pin19_config = (/* Pin is configured as FLEXSPI0A_SS0_N */
444 IOPCTL_PIO_FUNC1 |
445 /* Disable pull-up / pull-down function */
446 IOPCTL_PIO_PUPD_DI |
447 /* Enable pull-down function */
448 IOPCTL_PIO_PULLDOWN_EN |
449 /* Enables input buffer function */
450 IOPCTL_PIO_INBUF_EN |
451 /* Normal mode */
452 IOPCTL_PIO_SLEW_RATE_NORMAL |
453 /* Full drive enable */
454 IOPCTL_PIO_FULLDRIVE_EN |
455 /* Analog mux is disabled */
456 IOPCTL_PIO_ANAMUX_DI |
457 /* Pseudo Output Drain is disabled */
458 IOPCTL_PIO_PSEDRAIN_DI |
459 /* Input function is not inverted */
460 IOPCTL_PIO_INV_DI);
461 /* PORT1 PIN19 (coords: T4) is configured as FLEXSPI0A_SS0_N */
462 IOPCTL_PinMuxSet(IOPCTL, 1U, 19U, port1_pin19_config);
463
464 const uint32_t port1_pin20_config = (/* Pin is configured as FLEXSPI0A_DATA0 */
465 IOPCTL_PIO_FUNC1 |
466 /* Disable pull-up / pull-down function */
467 IOPCTL_PIO_PUPD_DI |
468 /* Enable pull-down function */
469 IOPCTL_PIO_PULLDOWN_EN |
470 /* Disable input buffer function */
471 IOPCTL_PIO_INBUF_DI |
472 /* Normal mode */
473 IOPCTL_PIO_SLEW_RATE_NORMAL |
474 /* Normal drive */
475 IOPCTL_PIO_FULLDRIVE_DI |
476 /* Analog mux is disabled */
477 IOPCTL_PIO_ANAMUX_DI |
478 /* Pseudo Output Drain is disabled */
479 IOPCTL_PIO_PSEDRAIN_DI |
480 /* Input function is not inverted */
481 IOPCTL_PIO_INV_DI);
482 /* PORT1 PIN20 (coords: T5) is configured as FLEXSPI0A_DATA0 */
483 IOPCTL_PinMuxSet(IOPCTL, 1U, 20U, port1_pin20_config);
484
485 const uint32_t port1_pin21_config = (/* Pin is configured as FLEXSPI0A_DATA1 */
486 IOPCTL_PIO_FUNC1 |
487 /* Disable pull-up / pull-down function */
488 IOPCTL_PIO_PUPD_DI |
489 /* Enable pull-down function */
490 IOPCTL_PIO_PULLDOWN_EN |
491 /* Disable input buffer function */
492 IOPCTL_PIO_INBUF_DI |
493 /* Normal mode */
494 IOPCTL_PIO_SLEW_RATE_NORMAL |
495 /* Normal drive */
496 IOPCTL_PIO_FULLDRIVE_DI |
497 /* Analog mux is disabled */
498 IOPCTL_PIO_ANAMUX_DI |
499 /* Pseudo Output Drain is disabled */
500 IOPCTL_PIO_PSEDRAIN_DI |
501 /* Input function is not inverted */
502 IOPCTL_PIO_INV_DI);
503 /* PORT1 PIN21 (coords: U5) is configured as FLEXSPI0A_DATA1 */
504 IOPCTL_PinMuxSet(IOPCTL, 1U, 21U, port1_pin21_config);
505
506 const uint32_t port1_pin22_config = (/* Pin is configured as FLEXSPI0A_DATA2 */
507 IOPCTL_PIO_FUNC1 |
508 /* Disable pull-up / pull-down function */
509 IOPCTL_PIO_PUPD_DI |
510 /* Enable pull-down function */
511 IOPCTL_PIO_PULLDOWN_EN |
512 /* Enables input buffer function */
513 IOPCTL_PIO_INBUF_EN |
514 /* Normal mode */
515 IOPCTL_PIO_SLEW_RATE_NORMAL |
516 /* Full drive enable */
517 IOPCTL_PIO_FULLDRIVE_EN |
518 /* Analog mux is disabled */
519 IOPCTL_PIO_ANAMUX_DI |
520 /* Pseudo Output Drain is disabled */
521 IOPCTL_PIO_PSEDRAIN_DI |
522 /* Input function is not inverted */
523 IOPCTL_PIO_INV_DI);
524 /* PORT1 PIN22 (coords: P6) is configured as FLEXSPI0A_DATA2 */
525 IOPCTL_PinMuxSet(IOPCTL, 1U, 22U, port1_pin22_config);
526
527 const uint32_t port1_pin23_config = (/* Pin is configured as FLEXSPI0A_DATA3 */
528 IOPCTL_PIO_FUNC1 |
529 /* Disable pull-up / pull-down function */
530 IOPCTL_PIO_PUPD_DI |
531 /* Enable pull-down function */
532 IOPCTL_PIO_PULLDOWN_EN |
533 /* Enables input buffer function */
534 IOPCTL_PIO_INBUF_EN |
535 /* Normal mode */
536 IOPCTL_PIO_SLEW_RATE_NORMAL |
537 /* Full drive enable */
538 IOPCTL_PIO_FULLDRIVE_EN |
539 /* Analog mux is disabled */
540 IOPCTL_PIO_ANAMUX_DI |
541 /* Pseudo Output Drain is disabled */
542 IOPCTL_PIO_PSEDRAIN_DI |
543 /* Input function is not inverted */
544 IOPCTL_PIO_INV_DI);
545 /* PORT1 PIN23 (coords: P7) is configured as FLEXSPI0A_DATA3 */
546 IOPCTL_PinMuxSet(IOPCTL, 1U, 23U, port1_pin23_config);
547
548 const uint32_t port1_pin24_config = (/* Pin is configured as FLEXSPI0A_DATA4 */
549 IOPCTL_PIO_FUNC1 |
550 /* Disable pull-up / pull-down function */
551 IOPCTL_PIO_PUPD_DI |
552 /* Enable pull-down function */
553 IOPCTL_PIO_PULLDOWN_EN |
554 /* Enables input buffer function */
555 IOPCTL_PIO_INBUF_EN |
556 /* Normal mode */
557 IOPCTL_PIO_SLEW_RATE_NORMAL |
558 /* Full drive enable */
559 IOPCTL_PIO_FULLDRIVE_EN |
560 /* Analog mux is disabled */
561 IOPCTL_PIO_ANAMUX_DI |
562 /* Pseudo Output Drain is disabled */
563 IOPCTL_PIO_PSEDRAIN_DI |
564 /* Input function is not inverted */
565 IOPCTL_PIO_INV_DI);
566 /* PORT1 PIN24 (coords: T7) is configured as FLEXSPI0A_DATA4 */
567 IOPCTL_PinMuxSet(IOPCTL, 1U, 24U, port1_pin24_config);
568
569 const uint32_t port1_pin25_config = (/* Pin is configured as FLEXSPI0A_DATA5 */
570 IOPCTL_PIO_FUNC1 |
571 /* Disable pull-up / pull-down function */
572 IOPCTL_PIO_PUPD_DI |
573 /* Enable pull-down function */
574 IOPCTL_PIO_PULLDOWN_EN |
575 /* Enables input buffer function */
576 IOPCTL_PIO_INBUF_EN |
577 /* Normal mode */
578 IOPCTL_PIO_SLEW_RATE_NORMAL |
579 /* Full drive enable */
580 IOPCTL_PIO_FULLDRIVE_EN |
581 /* Analog mux is disabled */
582 IOPCTL_PIO_ANAMUX_DI |
583 /* Pseudo Output Drain is disabled */
584 IOPCTL_PIO_PSEDRAIN_DI |
585 /* Input function is not inverted */
586 IOPCTL_PIO_INV_DI);
587 /* PORT1 PIN25 (coords: U7) is configured as FLEXSPI0A_DATA5 */
588 IOPCTL_PinMuxSet(IOPCTL, 1U, 25U, port1_pin25_config);
589
590 const uint32_t port1_pin26_config = (/* Pin is configured as FLEXSPI0A_DATA6 */
591 IOPCTL_PIO_FUNC1 |
592 /* Disable pull-up / pull-down function */
593 IOPCTL_PIO_PUPD_DI |
594 /* Enable pull-down function */
595 IOPCTL_PIO_PULLDOWN_EN |
596 /* Enables input buffer function */
597 IOPCTL_PIO_INBUF_EN |
598 /* Normal mode */
599 IOPCTL_PIO_SLEW_RATE_NORMAL |
600 /* Full drive enable */
601 IOPCTL_PIO_FULLDRIVE_EN |
602 /* Analog mux is disabled */
603 IOPCTL_PIO_ANAMUX_DI |
604 /* Pseudo Output Drain is disabled */
605 IOPCTL_PIO_PSEDRAIN_DI |
606 /* Input function is not inverted */
607 IOPCTL_PIO_INV_DI);
608 /* PORT1 PIN26 (coords: R7) is configured as FLEXSPI0A_DATA6 */
609 IOPCTL_PinMuxSet(IOPCTL, 1U, 26U, port1_pin26_config);
610
611 const uint32_t port1_pin27_config = (/* Pin is configured as FLEXSPI0A_DATA7 */
612 IOPCTL_PIO_FUNC1 |
613 /* Disable pull-up / pull-down function */
614 IOPCTL_PIO_PUPD_DI |
615 /* Enable pull-down function */
616 IOPCTL_PIO_PULLDOWN_EN |
617 /* Enables input buffer function */
618 IOPCTL_PIO_INBUF_EN |
619 /* Normal mode */
620 IOPCTL_PIO_SLEW_RATE_NORMAL |
621 /* Full drive enable */
622 IOPCTL_PIO_FULLDRIVE_EN |
623 /* Analog mux is disabled */
624 IOPCTL_PIO_ANAMUX_DI |
625 /* Pseudo Output Drain is disabled */
626 IOPCTL_PIO_PSEDRAIN_DI |
627 /* Input function is not inverted */
628 IOPCTL_PIO_INV_DI);
629 /* PORT1 PIN27 (coords: T8) is configured as FLEXSPI0A_DATA7 */
630 IOPCTL_PinMuxSet(IOPCTL, 1U, 27U, port1_pin27_config);
631
632 const uint32_t port1_pin28_config = (/* Pin is configured as FLEXSPI0A_DQS */
633 IOPCTL_PIO_FUNC1 |
634 /* Disable pull-up / pull-down function */
635 IOPCTL_PIO_PUPD_DI |
636 /* Enable pull-down function */
637 IOPCTL_PIO_PULLDOWN_EN |
638 /* Enables input buffer function */
639 IOPCTL_PIO_INBUF_EN |
640 /* Normal mode */
641 IOPCTL_PIO_SLEW_RATE_NORMAL |
642 /* Full drive enable */
643 IOPCTL_PIO_FULLDRIVE_EN |
644 /* Analog mux is disabled */
645 IOPCTL_PIO_ANAMUX_DI |
646 /* Pseudo Output Drain is disabled */
647 IOPCTL_PIO_PSEDRAIN_DI |
648 /* Input function is not inverted */
649 IOPCTL_PIO_INV_DI);
650 /* PORT1 PIN28 (coords: U9) is configured as FLEXSPI0A_DQS */
651 IOPCTL_PinMuxSet(IOPCTL, 1U, 28U, port1_pin28_config);
652}
653
654/* clang-format off */
655/*
656 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
657BOARD_InitUSDHC0Pins:
658- options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'}
659- pin_list:
660 - {pin_num: R11, peripheral: USDHC0, signal: 'USDHC_DATA, 0', pin_signal: PIO2_0/SD0_D0/SCT0_GPI2, pupdena: enabled, pupdsel: pullUp, ibena: enabled, slew_rate: normal,
661 drive: normal, amena: disabled, odena: disabled, iiena: disabled}
662 - {pin_num: T11, peripheral: USDHC0, signal: 'USDHC_DATA, 1', pin_signal: PIO2_1/SD0_D1/SCT0_GPI3, pupdena: enabled, pupdsel: pullUp, ibena: enabled, slew_rate: normal,
663 drive: normal, amena: disabled, odena: disabled, iiena: disabled}
664 - {pin_num: U11, peripheral: USDHC0, signal: 'USDHC_DATA, 2', pin_signal: PIO2_2/SD0_D2/SCT0_OUT0, pupdena: enabled, pupdsel: pullUp, ibena: enabled, slew_rate: normal,
665 drive: normal, amena: disabled, odena: disabled, iiena: disabled}
666 - {pin_num: T12, peripheral: USDHC0, signal: 'USDHC_DATA, 3', pin_signal: PIO2_3/SD0_D3/SCT0_OUT1, pupdena: enabled, pupdsel: pullUp, ibena: enabled, slew_rate: normal,
667 drive: normal, amena: disabled, odena: disabled, iiena: disabled}
668 - {pin_num: P10, peripheral: USDHC0, signal: USDHC_CLK, pin_signal: PIO1_30/SD0_CLK/SCT0_GPI0, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal,
669 drive: normal, amena: disabled, odena: disabled, iiena: disabled}
670 - {pin_num: R9, peripheral: USDHC0, signal: USDHC_CMD, pin_signal: PIO1_31/SD0_CMD/SCT0_GPI1, pupdena: enabled, pupdsel: pullUp, ibena: enabled, slew_rate: normal,
671 drive: normal, amena: disabled, odena: disabled, iiena: disabled}
672 - {pin_num: R13, peripheral: USDHC0, signal: USDHC_CD_B, pin_signal: PIO2_9/SD0_CARD_DET_N/SCT0_OUT5/CTIMER1_MAT3, pupdena: enabled, pupdsel: pullUp, ibena: enabled,
673 slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
674 - {pin_num: T15, peripheral: GPIO, signal: 'PIO2, 10', pin_signal: PIO2_10/SD0_RESET_N/SCT0_GPI6/CTIMER2_MAT0, pupdena: disabled, pupdsel: pullDown, ibena: disabled,
675 slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
676 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
677 */
678/* clang-format on */
679
680/* FUNCTION ************************************************************************************************************
681 *
682 * Function Name : BOARD_InitUSDHC0Pins
683 * Description : Configures pin routing and optionally pin electrical features.
684 *
685 * END ****************************************************************************************************************/
686/* Function assigned for the Cortex-M33 */
687void BOARD_InitUSDHC0Pins(void)
688{
689
690 const uint32_t port1_pin30_config = (/* Pin is configured as SD0_CLK */
691 IOPCTL_PIO_FUNC1 |
692 /* Disable pull-up / pull-down function */
693 IOPCTL_PIO_PUPD_DI |
694 /* Enable pull-down function */
695 IOPCTL_PIO_PULLDOWN_EN |
696 /* Enables input buffer function */
697 IOPCTL_PIO_INBUF_EN |
698 /* Normal mode */
699 IOPCTL_PIO_SLEW_RATE_NORMAL |
700 /* Normal drive */
701 IOPCTL_PIO_FULLDRIVE_DI |
702 /* Analog mux is disabled */
703 IOPCTL_PIO_ANAMUX_DI |
704 /* Pseudo Output Drain is disabled */
705 IOPCTL_PIO_PSEDRAIN_DI |
706 /* Input function is not inverted */
707 IOPCTL_PIO_INV_DI);
708 /* PORT1 PIN30 (coords: P10) is configured as SD0_CLK */
709 IOPCTL_PinMuxSet(IOPCTL, 1U, 30U, port1_pin30_config);
710
711 const uint32_t port1_pin31_config = (/* Pin is configured as SD0_CMD */
712 IOPCTL_PIO_FUNC1 |
713 /* Enable pull-up / pull-down function */
714 IOPCTL_PIO_PUPD_EN |
715 /* Enable pull-up function */
716 IOPCTL_PIO_PULLUP_EN |
717 /* Enables input buffer function */
718 IOPCTL_PIO_INBUF_EN |
719 /* Normal mode */
720 IOPCTL_PIO_SLEW_RATE_NORMAL |
721 /* Normal drive */
722 IOPCTL_PIO_FULLDRIVE_DI |
723 /* Analog mux is disabled */
724 IOPCTL_PIO_ANAMUX_DI |
725 /* Pseudo Output Drain is disabled */
726 IOPCTL_PIO_PSEDRAIN_DI |
727 /* Input function is not inverted */
728 IOPCTL_PIO_INV_DI);
729 /* PORT1 PIN31 (coords: R9) is configured as SD0_CMD */
730 IOPCTL_PinMuxSet(IOPCTL, 1U, 31U, port1_pin31_config);
731
732 const uint32_t port2_pin0_config = (/* Pin is configured as SD0_D0 */
733 IOPCTL_PIO_FUNC1 |
734 /* Enable pull-up / pull-down function */
735 IOPCTL_PIO_PUPD_EN |
736 /* Enable pull-up function */
737 IOPCTL_PIO_PULLUP_EN |
738 /* Enables input buffer function */
739 IOPCTL_PIO_INBUF_EN |
740 /* Normal mode */
741 IOPCTL_PIO_SLEW_RATE_NORMAL |
742 /* Normal drive */
743 IOPCTL_PIO_FULLDRIVE_DI |
744 /* Analog mux is disabled */
745 IOPCTL_PIO_ANAMUX_DI |
746 /* Pseudo Output Drain is disabled */
747 IOPCTL_PIO_PSEDRAIN_DI |
748 /* Input function is not inverted */
749 IOPCTL_PIO_INV_DI);
750 /* PORT2 PIN0 (coords: R11) is configured as SD0_D0 */
751 IOPCTL_PinMuxSet(IOPCTL, 2U, 0U, port2_pin0_config);
752
753 const uint32_t port2_pin1_config = (/* Pin is configured as SD0_D1 */
754 IOPCTL_PIO_FUNC1 |
755 /* Enable pull-up / pull-down function */
756 IOPCTL_PIO_PUPD_EN |
757 /* Enable pull-up function */
758 IOPCTL_PIO_PULLUP_EN |
759 /* Enables input buffer function */
760 IOPCTL_PIO_INBUF_EN |
761 /* Normal mode */
762 IOPCTL_PIO_SLEW_RATE_NORMAL |
763 /* Normal drive */
764 IOPCTL_PIO_FULLDRIVE_DI |
765 /* Analog mux is disabled */
766 IOPCTL_PIO_ANAMUX_DI |
767 /* Pseudo Output Drain is disabled */
768 IOPCTL_PIO_PSEDRAIN_DI |
769 /* Input function is not inverted */
770 IOPCTL_PIO_INV_DI);
771 /* PORT2 PIN1 (coords: T11) is configured as SD0_D1 */
772 IOPCTL_PinMuxSet(IOPCTL, 2U, 1U, port2_pin1_config);
773
774 const uint32_t SD_RST_N = (/* Pin is configured as PIO2_10 */
775 IOPCTL_PIO_FUNC0 |
776 /* Disable pull-up / pull-down function */
777 IOPCTL_PIO_PUPD_DI |
778 /* Enable pull-down function */
779 IOPCTL_PIO_PULLDOWN_EN |
780 /* Disable input buffer function */
781 IOPCTL_PIO_INBUF_DI |
782 /* Normal mode */
783 IOPCTL_PIO_SLEW_RATE_NORMAL |
784 /* Normal drive */
785 IOPCTL_PIO_FULLDRIVE_DI |
786 /* Analog mux is disabled */
787 IOPCTL_PIO_ANAMUX_DI |
788 /* Pseudo Output Drain is disabled */
789 IOPCTL_PIO_PSEDRAIN_DI |
790 /* Input function is not inverted */
791 IOPCTL_PIO_INV_DI);
792 /* PORT2 PIN10 (coords: T15) is configured as PIO2_10 */
793 IOPCTL_PinMuxSet(IOPCTL, BOARD_INITUSDHC0PINS_SD_RST_N_PORT, BOARD_INITUSDHC0PINS_SD_RST_N_PIN, SD_RST_N);
794
795 const uint32_t port2_pin2_config = (/* Pin is configured as SD0_D2 */
796 IOPCTL_PIO_FUNC1 |
797 /* Enable pull-up / pull-down function */
798 IOPCTL_PIO_PUPD_EN |
799 /* Enable pull-up function */
800 IOPCTL_PIO_PULLUP_EN |
801 /* Enables input buffer function */
802 IOPCTL_PIO_INBUF_EN |
803 /* Normal mode */
804 IOPCTL_PIO_SLEW_RATE_NORMAL |
805 /* Normal drive */
806 IOPCTL_PIO_FULLDRIVE_DI |
807 /* Analog mux is disabled */
808 IOPCTL_PIO_ANAMUX_DI |
809 /* Pseudo Output Drain is disabled */
810 IOPCTL_PIO_PSEDRAIN_DI |
811 /* Input function is not inverted */
812 IOPCTL_PIO_INV_DI);
813 /* PORT2 PIN2 (coords: U11) is configured as SD0_D2 */
814 IOPCTL_PinMuxSet(IOPCTL, 2U, 2U, port2_pin2_config);
815
816 const uint32_t port2_pin3_config = (/* Pin is configured as SD0_D3 */
817 IOPCTL_PIO_FUNC1 |
818 /* Enable pull-up / pull-down function */
819 IOPCTL_PIO_PUPD_EN |
820 /* Enable pull-up function */
821 IOPCTL_PIO_PULLUP_EN |
822 /* Enables input buffer function */
823 IOPCTL_PIO_INBUF_EN |
824 /* Normal mode */
825 IOPCTL_PIO_SLEW_RATE_NORMAL |
826 /* Normal drive */
827 IOPCTL_PIO_FULLDRIVE_DI |
828 /* Analog mux is disabled */
829 IOPCTL_PIO_ANAMUX_DI |
830 /* Pseudo Output Drain is disabled */
831 IOPCTL_PIO_PSEDRAIN_DI |
832 /* Input function is not inverted */
833 IOPCTL_PIO_INV_DI);
834 /* PORT2 PIN3 (coords: T12) is configured as SD0_D3 */
835 IOPCTL_PinMuxSet(IOPCTL, 2U, 3U, port2_pin3_config);
836
837 const uint32_t port2_pin9_config = (/* Pin is configured as SD0_CARD_DET_N */
838 IOPCTL_PIO_FUNC1 |
839 /* Enable pull-up / pull-down function */
840 IOPCTL_PIO_PUPD_EN |
841 /* Enable pull-up function */
842 IOPCTL_PIO_PULLUP_EN |
843 /* Enables input buffer function */
844 IOPCTL_PIO_INBUF_EN |
845 /* Normal mode */
846 IOPCTL_PIO_SLEW_RATE_NORMAL |
847 /* Normal drive */
848 IOPCTL_PIO_FULLDRIVE_DI |
849 /* Analog mux is disabled */
850 IOPCTL_PIO_ANAMUX_DI |
851 /* Pseudo Output Drain is disabled */
852 IOPCTL_PIO_PSEDRAIN_DI |
853 /* Input function is not inverted */
854 IOPCTL_PIO_INV_DI);
855 /* PORT2 PIN9 (coords: R13) is configured as SD0_CARD_DET_N */
856 IOPCTL_PinMuxSet(IOPCTL, 2U, 9U, port2_pin9_config);
857}
858
859/* clang-format off */
860/*
861 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
862BOARD_InitLEDsPins:
863- options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'}
864- pin_list:
865 - {pin_num: A3, peripheral: GPIO, signal: 'PIO0, 14', pin_signal: PIO0_14/FC2_SCK/SCT0_GPI0/SCT0_OUT0/CTIMER2_MAT0/I2S_BRIDGE_CLK_IN/SEC_PIO0_14, direction: OUTPUT,
866 gpio_init_state: 'true', pupdena: disabled, pupdsel: pullDown, ibena: disabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
867 - {pin_num: A2, peripheral: GPIO, signal: 'PIO0, 26', pin_signal: PIO0_26/FC3_SSEL2/SCT0_GPI6/SCT0_OUT6/CTIMER_INP7/SEC_PIO0_26/ADC0_3, direction: OUTPUT, gpio_init_state: 'true',
868 pupdena: disabled, pupdsel: pullDown, ibena: disabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
869 - {pin_num: A11, peripheral: GPIO, signal: 'PIO0, 31', pin_signal: PIO0_31/FC4_CTS_SDA_SSEL0/SCT0_GPI0/SCT0_OUT6/CTIMER4_MAT3/FC3_SSEL2/SEC_PIO0_31, direction: OUTPUT,
870 gpio_init_state: 'true', pupdena: disabled, pupdsel: pullDown, ibena: disabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
871 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
872 */
873/* clang-format on */
874
875/* FUNCTION ************************************************************************************************************
876 *
877 * Function Name : BOARD_InitLEDsPins
878 * Description : Configures pin routing and optionally pin electrical features.
879 *
880 * END ****************************************************************************************************************/
881/* Function assigned for the Cortex-M33 */
882void BOARD_InitLEDsPins(void)
883{
884
885 /* Enables the clock for the GPIO0 module */
886 CLOCK_EnableClock(kCLOCK_HsGpio0);
887
888 gpio_pin_config_t LED_GREEN_config = {
889 .pinDirection = kGPIO_DigitalOutput,
890 .outputLogic = 1U
891 };
892 /* Initialize GPIO functionality on pin PIO0_14 (pin A3) */
893 GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config);
894
895 gpio_pin_config_t LED_BLUE_config = {
896 .pinDirection = kGPIO_DigitalOutput,
897 .outputLogic = 1U
898 };
899 /* Initialize GPIO functionality on pin PIO0_26 (pin A2) */
900 GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config);
901
902 gpio_pin_config_t LED_RED_config = {
903 .pinDirection = kGPIO_DigitalOutput,
904 .outputLogic = 1U
905 };
906 /* Initialize GPIO functionality on pin PIO0_31 (pin A11) */
907 GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config);
908
909 const uint32_t LED_GREEN = (/* Pin is configured as PIO0_14 */
910 IOPCTL_PIO_FUNC0 |
911 /* Disable pull-up / pull-down function */
912 IOPCTL_PIO_PUPD_DI |
913 /* Enable pull-down function */
914 IOPCTL_PIO_PULLDOWN_EN |
915 /* Disable input buffer function */
916 IOPCTL_PIO_INBUF_DI |
917 /* Normal mode */
918 IOPCTL_PIO_SLEW_RATE_NORMAL |
919 /* Normal drive */
920 IOPCTL_PIO_FULLDRIVE_DI |
921 /* Analog mux is disabled */
922 IOPCTL_PIO_ANAMUX_DI |
923 /* Pseudo Output Drain is disabled */
924 IOPCTL_PIO_PSEDRAIN_DI |
925 /* Input function is not inverted */
926 IOPCTL_PIO_INV_DI);
927 /* PORT0 PIN14 (coords: A3) is configured as PIO0_14 */
928 IOPCTL_PinMuxSet(IOPCTL, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, LED_GREEN);
929
930 const uint32_t LED_BLUE = (/* Pin is configured as PIO0_26 */
931 IOPCTL_PIO_FUNC0 |
932 /* Disable pull-up / pull-down function */
933 IOPCTL_PIO_PUPD_DI |
934 /* Enable pull-down function */
935 IOPCTL_PIO_PULLDOWN_EN |
936 /* Disable input buffer function */
937 IOPCTL_PIO_INBUF_DI |
938 /* Normal mode */
939 IOPCTL_PIO_SLEW_RATE_NORMAL |
940 /* Normal drive */
941 IOPCTL_PIO_FULLDRIVE_DI |
942 /* Analog mux is disabled */
943 IOPCTL_PIO_ANAMUX_DI |
944 /* Pseudo Output Drain is disabled */
945 IOPCTL_PIO_PSEDRAIN_DI |
946 /* Input function is not inverted */
947 IOPCTL_PIO_INV_DI);
948 /* PORT0 PIN26 (coords: A2) is configured as PIO0_26 */
949 IOPCTL_PinMuxSet(IOPCTL, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, LED_BLUE);
950
951 const uint32_t LED_RED = (/* Pin is configured as PIO0_31 */
952 IOPCTL_PIO_FUNC0 |
953 /* Disable pull-up / pull-down function */
954 IOPCTL_PIO_PUPD_DI |
955 /* Enable pull-down function */
956 IOPCTL_PIO_PULLDOWN_EN |
957 /* Disable input buffer function */
958 IOPCTL_PIO_INBUF_DI |
959 /* Normal mode */
960 IOPCTL_PIO_SLEW_RATE_NORMAL |
961 /* Normal drive */
962 IOPCTL_PIO_FULLDRIVE_DI |
963 /* Analog mux is disabled */
964 IOPCTL_PIO_ANAMUX_DI |
965 /* Pseudo Output Drain is disabled */
966 IOPCTL_PIO_PSEDRAIN_DI |
967 /* Input function is not inverted */
968 IOPCTL_PIO_INV_DI);
969 /* PORT0 PIN31 (coords: A11) is configured as PIO0_31 */
970 IOPCTL_PinMuxSet(IOPCTL, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, LED_RED);
971}
972
973/* clang-format off */
974/*
975 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
976BOARD_InitBUTTONsPins:
977- options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'}
978- pin_list:
979 - {pin_num: J3, peripheral: GPIO, signal: 'PIO0, 10', pin_signal: PIO0_10/FC1_CTS_SDA_SSEL0/SCT0_GPI7/SCT0_OUT7/CTIMER1_MAT3/FC0_SSEL2/SEC_PIO0_10, direction: INPUT,
980 pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
981 - {pin_num: G15, peripheral: GPIO, signal: 'PIO1, 1', pin_signal: PIO1_1/FC4_SSEL2/SCT0_GPI2/SCT0_OUT8/CTIMER1_MAT0, direction: INPUT, pupdena: disabled, pupdsel: pullDown,
982 ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
983 - {pin_num: B15, peripheral: SYSCON, signal: RESET, pin_signal: RESETN}
984 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
985 */
986/* clang-format on */
987
988/* FUNCTION ************************************************************************************************************
989 *
990 * Function Name : BOARD_InitBUTTONsPins
991 * Description : Configures pin routing and optionally pin electrical features.
992 *
993 * END ****************************************************************************************************************/
994/* Function assigned for the Cortex-M33 */
995void BOARD_InitBUTTONsPins(void)
996{
997
998 /* Enables the clock for the GPIO0 module */
999 CLOCK_EnableClock(kCLOCK_HsGpio0);
1000
1001 /* Enables the clock for the GPIO1 module */
1002 CLOCK_EnableClock(kCLOCK_HsGpio1);
1003
1004 gpio_pin_config_t SW2_config = {
1005 .pinDirection = kGPIO_DigitalInput,
1006 .outputLogic = 0U
1007 };
1008 /* Initialize GPIO functionality on pin PIO0_10 (pin J3) */
1009 GPIO_PinInit(BOARD_INITBUTTONSPINS_SW2_GPIO, BOARD_INITBUTTONSPINS_SW2_PORT, BOARD_INITBUTTONSPINS_SW2_PIN, &SW2_config);
1010
1011 gpio_pin_config_t SW1_config = {
1012 .pinDirection = kGPIO_DigitalInput,
1013 .outputLogic = 0U
1014 };
1015 /* Initialize GPIO functionality on pin PIO1_1 (pin G15) */
1016 GPIO_PinInit(BOARD_INITBUTTONSPINS_SW1_GPIO, BOARD_INITBUTTONSPINS_SW1_PORT, BOARD_INITBUTTONSPINS_SW1_PIN, &SW1_config);
1017
1018 const uint32_t SW2 = (/* Pin is configured as PIO0_10 */
1019 IOPCTL_PIO_FUNC0 |
1020 /* Disable pull-up / pull-down function */
1021 IOPCTL_PIO_PUPD_DI |
1022 /* Enable pull-down function */
1023 IOPCTL_PIO_PULLDOWN_EN |
1024 /* Enables input buffer function */
1025 IOPCTL_PIO_INBUF_EN |
1026 /* Normal mode */
1027 IOPCTL_PIO_SLEW_RATE_NORMAL |
1028 /* Normal drive */
1029 IOPCTL_PIO_FULLDRIVE_DI |
1030 /* Analog mux is disabled */
1031 IOPCTL_PIO_ANAMUX_DI |
1032 /* Pseudo Output Drain is disabled */
1033 IOPCTL_PIO_PSEDRAIN_DI |
1034 /* Input function is not inverted */
1035 IOPCTL_PIO_INV_DI);
1036 /* PORT0 PIN10 (coords: J3) is configured as PIO0_10 */
1037 IOPCTL_PinMuxSet(IOPCTL, BOARD_INITBUTTONSPINS_SW2_PORT, BOARD_INITBUTTONSPINS_SW2_PIN, SW2);
1038
1039 const uint32_t SW1 = (/* Pin is configured as PIO1_1 */
1040 IOPCTL_PIO_FUNC0 |
1041 /* Disable pull-up / pull-down function */
1042 IOPCTL_PIO_PUPD_DI |
1043 /* Enable pull-down function */
1044 IOPCTL_PIO_PULLDOWN_EN |
1045 /* Enables input buffer function */
1046 IOPCTL_PIO_INBUF_EN |
1047 /* Normal mode */
1048 IOPCTL_PIO_SLEW_RATE_NORMAL |
1049 /* Normal drive */
1050 IOPCTL_PIO_FULLDRIVE_DI |
1051 /* Analog mux is disabled */
1052 IOPCTL_PIO_ANAMUX_DI |
1053 /* Pseudo Output Drain is disabled */
1054 IOPCTL_PIO_PSEDRAIN_DI |
1055 /* Input function is not inverted */
1056 IOPCTL_PIO_INV_DI);
1057 /* PORT1 PIN1 (coords: G15) is configured as PIO1_1 */
1058 IOPCTL_PinMuxSet(IOPCTL, BOARD_INITBUTTONSPINS_SW1_PORT, BOARD_INITBUTTONSPINS_SW1_PIN, SW1);
1059}
1060
1061/* clang-format off */
1062/*
1063 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
1064BOARD_InitACCELPins:
1065- options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'}
1066- pin_list:
1067 - {pin_num: B7, peripheral: FLEXCOMM2, signal: RTS_SCL_SSEL1, pin_signal: PIO0_18/FC2_RTS_SCL_SSEL1/SCT0_GPI6/SCT0_OUT6/CTIMER_INP4/FC5_SSEL3/SEC_PIO0_18, pupdena: enabled,
1068 pupdsel: pullUp, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: enabled, iiena: disabled}
1069 - {pin_num: D7, peripheral: FLEXCOMM2, signal: CTS_SDA_SSEL0, pin_signal: PIO0_17/FC2_CTS_SDA_SSEL0/SCT0_GPI3/SCT0_OUT3/CTIMER2_MAT3/FC5_SSEL2/SEC_PIO0_17, pupdena: enabled,
1070 pupdsel: pullUp, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: enabled, iiena: disabled}
1071 - {pin_num: J16, peripheral: GPIO, signal: 'PIO1, 5', pin_signal: PIO1_5/FC5_RXD_SDA_MOSI_DATA, direction: INPUT, pupdena: disabled, pupdsel: pullDown, ibena: enabled,
1072 slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
1073 - {pin_num: J15, peripheral: GPIO, signal: 'PIO1, 7', pin_signal: PIO1_7/FC5_RTS_SCL_SSEL1/SCT0_GPI5/SCT0_OUT5/CTIMER_INP9/FC4_SSEL3, direction: OUTPUT, gpio_init_state: 'true',
1074 pupdena: disabled, pupdsel: pullDown, ibena: disabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
1075 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
1076 */
1077/* clang-format on */
1078
1079/* FUNCTION ************************************************************************************************************
1080 *
1081 * Function Name : BOARD_InitACCELPins
1082 * Description : Configures pin routing and optionally pin electrical features.
1083 *
1084 * END ****************************************************************************************************************/
1085/* Function assigned for the Cortex-M33 */
1086void BOARD_InitACCELPins(void)
1087{
1088
1089 /* Enables the clock for the GPIO1 module */
1090 CLOCK_EnableClock(kCLOCK_HsGpio1);
1091
1092 gpio_pin_config_t ACC_INT_config = {
1093 .pinDirection = kGPIO_DigitalInput,
1094 .outputLogic = 0U
1095 };
1096 /* Initialize GPIO functionality on pin PIO1_5 (pin J16) */
1097 GPIO_PinInit(BOARD_INITACCELPINS_ACC_INT_GPIO, BOARD_INITACCELPINS_ACC_INT_PORT, BOARD_INITACCELPINS_ACC_INT_PIN, &ACC_INT_config);
1098
1099 gpio_pin_config_t ACC_RESET_config = {
1100 .pinDirection = kGPIO_DigitalOutput,
1101 .outputLogic = 1U
1102 };
1103 /* Initialize GPIO functionality on pin PIO1_7 (pin J15) */
1104 GPIO_PinInit(BOARD_INITACCELPINS_ACC_RESET_GPIO, BOARD_INITACCELPINS_ACC_RESET_PORT, BOARD_INITACCELPINS_ACC_RESET_PIN, &ACC_RESET_config);
1105
1106 const uint32_t port0_pin17_config = (/* Pin is configured as FC2_CTS_SDA_SSEL0 */
1107 IOPCTL_PIO_FUNC1 |
1108 /* Enable pull-up / pull-down function */
1109 IOPCTL_PIO_PUPD_EN |
1110 /* Enable pull-up function */
1111 IOPCTL_PIO_PULLUP_EN |
1112 /* Enables input buffer function */
1113 IOPCTL_PIO_INBUF_EN |
1114 /* Normal mode */
1115 IOPCTL_PIO_SLEW_RATE_NORMAL |
1116 /* Full drive enable */
1117 IOPCTL_PIO_FULLDRIVE_EN |
1118 /* Analog mux is disabled */
1119 IOPCTL_PIO_ANAMUX_DI |
1120 /* Pseudo Output Drain is enabled */
1121 IOPCTL_PIO_PSEDRAIN_EN |
1122 /* Input function is not inverted */
1123 IOPCTL_PIO_INV_DI);
1124 /* PORT0 PIN17 (coords: D7) is configured as FC2_CTS_SDA_SSEL0 */
1125 IOPCTL_PinMuxSet(IOPCTL, 0U, 17U, port0_pin17_config);
1126
1127 const uint32_t port0_pin18_config = (/* Pin is configured as FC2_RTS_SCL_SSEL1 */
1128 IOPCTL_PIO_FUNC1 |
1129 /* Enable pull-up / pull-down function */
1130 IOPCTL_PIO_PUPD_EN |
1131 /* Enable pull-up function */
1132 IOPCTL_PIO_PULLUP_EN |
1133 /* Enables input buffer function */
1134 IOPCTL_PIO_INBUF_EN |
1135 /* Normal mode */
1136 IOPCTL_PIO_SLEW_RATE_NORMAL |
1137 /* Full drive enable */
1138 IOPCTL_PIO_FULLDRIVE_EN |
1139 /* Analog mux is disabled */
1140 IOPCTL_PIO_ANAMUX_DI |
1141 /* Pseudo Output Drain is enabled */
1142 IOPCTL_PIO_PSEDRAIN_EN |
1143 /* Input function is not inverted */
1144 IOPCTL_PIO_INV_DI);
1145 /* PORT0 PIN18 (coords: B7) is configured as FC2_RTS_SCL_SSEL1 */
1146 IOPCTL_PinMuxSet(IOPCTL, 0U, 18U, port0_pin18_config);
1147
1148 const uint32_t ACC_INT = (/* Pin is configured as PIO1_5 */
1149 IOPCTL_PIO_FUNC0 |
1150 /* Disable pull-up / pull-down function */
1151 IOPCTL_PIO_PUPD_DI |
1152 /* Enable pull-down function */
1153 IOPCTL_PIO_PULLDOWN_EN |
1154 /* Enables input buffer function */
1155 IOPCTL_PIO_INBUF_EN |
1156 /* Normal mode */
1157 IOPCTL_PIO_SLEW_RATE_NORMAL |
1158 /* Normal drive */
1159 IOPCTL_PIO_FULLDRIVE_DI |
1160 /* Analog mux is disabled */
1161 IOPCTL_PIO_ANAMUX_DI |
1162 /* Pseudo Output Drain is disabled */
1163 IOPCTL_PIO_PSEDRAIN_DI |
1164 /* Input function is not inverted */
1165 IOPCTL_PIO_INV_DI);
1166 /* PORT1 PIN5 (coords: J16) is configured as PIO1_5 */
1167 IOPCTL_PinMuxSet(IOPCTL, BOARD_INITACCELPINS_ACC_INT_PORT, BOARD_INITACCELPINS_ACC_INT_PIN, ACC_INT);
1168
1169 const uint32_t ACC_RESET = (/* Pin is configured as PIO1_7 */
1170 IOPCTL_PIO_FUNC0 |
1171 /* Disable pull-up / pull-down function */
1172 IOPCTL_PIO_PUPD_DI |
1173 /* Enable pull-down function */
1174 IOPCTL_PIO_PULLDOWN_EN |
1175 /* Disable input buffer function */
1176 IOPCTL_PIO_INBUF_DI |
1177 /* Normal mode */
1178 IOPCTL_PIO_SLEW_RATE_NORMAL |
1179 /* Normal drive */
1180 IOPCTL_PIO_FULLDRIVE_DI |
1181 /* Analog mux is disabled */
1182 IOPCTL_PIO_ANAMUX_DI |
1183 /* Pseudo Output Drain is disabled */
1184 IOPCTL_PIO_PSEDRAIN_DI |
1185 /* Input function is not inverted */
1186 IOPCTL_PIO_INV_DI);
1187 /* PORT1 PIN7 (coords: J15) is configured as PIO1_7 */
1188 IOPCTL_PinMuxSet(IOPCTL, BOARD_INITACCELPINS_ACC_RESET_PORT, BOARD_INITACCELPINS_ACC_RESET_PIN, ACC_RESET);
1189}
1190/***********************************************************************************************************************
1191 * EOF
1192 **********************************************************************************************************************/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:56:12 +0100