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diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt685/project_template/pin_mux.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt685/project_template/pin_mux.h
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1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7/***********************************************************************************************************************
8 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
9 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
10 **********************************************************************************************************************/
11
12#ifndef _PIN_MUX_H_
13#define _PIN_MUX_H_
14
15/*!
16 * @addtogroup pin_mux
17 * @{
18 */
19
20/***********************************************************************************************************************
21 * API
22 **********************************************************************************************************************/
23
24#if defined(__cplusplus)
25extern "C" {
26#endif
27
28/*!
29 * @brief Calls initialization functions.
30 *
31 */
32void BOARD_InitBootPins(void);
33
34/*!
35 * @brief Configures pin routing and optionally pin electrical features.
36 *
37 */
38void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
39
40#define IOPCTL_PIO_ANAMUX_DI 0x00u /*!<@brief Analog mux is disabled */
41#define IOPCTL_PIO_FULLDRIVE_DI 0x00u /*!<@brief Normal drive */
42#define IOPCTL_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */
43#define IOPCTL_PIO_INBUF_DI 0x00u /*!<@brief Disable input buffer function */
44#define IOPCTL_PIO_INBUF_EN 0x40u /*!<@brief Enables input buffer function */
45#define IOPCTL_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
46#define IOPCTL_PIO_PSEDRAIN_DI 0x00u /*!<@brief Pseudo Output Drain is disabled */
47#define IOPCTL_PIO_PULLDOWN_EN 0x00u /*!<@brief Enable pull-down function */
48#define IOPCTL_PIO_PUPD_DI 0x00u /*!<@brief Disable pull-up / pull-down function */
49#define IOPCTL_PIO_SLEW_RATE_NORMAL 0x00u /*!<@brief Normal mode */
50
51/*! @name FC0_RXD_SDA_MOSI_DATA (coord G4), JP21[2]/U28[3]/U9[13]
52 @{ */
53/* @} */
54
55/*! @name FC0_TXD_SCL_MISO_WS (coord G2), J16[1]/U27[3]/U9[12]
56 @{ */
57/* @} */
58
59/*!
60 * @brief Configures pin routing and optionally pin electrical features.
61 *
62 */
63void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 */
64
65#define IOPCTL_PIO_ANAMUX_DI 0x00u /*!<@brief Analog mux is disabled */
66#define IOPCTL_PIO_FULLDRIVE_DI 0x00u /*!<@brief Normal drive */
67#define IOPCTL_PIO_FULLDRIVE_EN 0x0100u /*!<@brief Full drive enable */
68#define IOPCTL_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */
69#define IOPCTL_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */
70#define IOPCTL_PIO_INBUF_EN 0x40u /*!<@brief Enables input buffer function */
71#define IOPCTL_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
72#define IOPCTL_PIO_PSEDRAIN_DI 0x00u /*!<@brief Pseudo Output Drain is disabled */
73#define IOPCTL_PIO_PULLDOWN_EN 0x00u /*!<@brief Enable pull-down function */
74#define IOPCTL_PIO_PUPD_DI 0x00u /*!<@brief Disable pull-up / pull-down function */
75#define IOPCTL_PIO_SLEW_RATE_NORMAL 0x00u /*!<@brief Normal mode */
76
77/*! @name FLEXSPI0B_DATA0 (coord L2), U19[D3]
78 @{ */
79/* @} */
80
81/*! @name FLEXSPI0B_DATA1 (coord M2), U19[D2]
82 @{ */
83/* @} */
84
85/*! @name FLEXSPI0B_DATA2 (coord N1), U19[C4]
86 @{ */
87/* @} */
88
89/*! @name FLEXSPI0B_DATA3 (coord N2), U19[D4]
90 @{ */
91/* @} */
92
93/*! @name FLEXSPI0B_DATA4 (coord U1), U19[D5]
94 @{ */
95/* @} */
96
97/*! @name FLEXSPI0B_DATA5 (coord R2), U19[E3]
98 @{ */
99/* @} */
100
101/*! @name FLEXSPI0B_DATA6 (coord P3), U19[E2]
102 @{ */
103/* @} */
104
105/*! @name FLEXSPI0B_DATA7 (coord P5), U19[E1]
106 @{ */
107/* @} */
108
109/*! @name FLEXSPI0B_SS0_N (coord T2), U19[C2]
110 @{ */
111 /* @} */
112
113/*! @name FLEXSPI0B_SCLK (coord U3), U19[B2]
114 @{ */
115 /* @} */
116
117/*!
118 * @brief Configures pin routing and optionally pin electrical features.
119 *
120 */
121void BOARD_InitFlexSPIFlashPins(void); /* Function assigned for the Cortex-M33 */
122
123#define IOPCTL_PIO_ANAMUX_DI 0x00u /*!<@brief Analog mux is disabled */
124#define IOPCTL_PIO_FULLDRIVE_DI 0x00u /*!<@brief Normal drive */
125#define IOPCTL_PIO_FULLDRIVE_EN 0x0100u /*!<@brief Full drive enable */
126#define IOPCTL_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */
127#define IOPCTL_PIO_INBUF_DI 0x00u /*!<@brief Disable input buffer function */
128#define IOPCTL_PIO_INBUF_EN 0x40u /*!<@brief Enables input buffer function */
129#define IOPCTL_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
130#define IOPCTL_PIO_PSEDRAIN_DI 0x00u /*!<@brief Pseudo Output Drain is disabled */
131#define IOPCTL_PIO_PULLDOWN_EN 0x00u /*!<@brief Enable pull-down function */
132#define IOPCTL_PIO_PUPD_DI 0x00u /*!<@brief Disable pull-up / pull-down function */
133#define IOPCTL_PIO_SLEW_RATE_NORMAL 0x00u /*!<@brief Normal mode */
134
135/*! @name FLEXSPI0A_DATA0 (coord T5), U108[D3]
136 @{ */
137 /* @} */
138
139/*! @name FLEXSPI0A_DATA1 (coord U5), U108[D2]
140 @{ */
141 /* @} */
142
143/*! @name FLEXSPI0A_DATA2 (coord P6), U108[C4]
144 @{ */
145 /* @} */
146
147/*! @name FLEXSPI0A_DATA3 (coord P7), U108[D4]
148 @{ */
149 /* @} */
150
151/*! @name FLEXSPI0A_DATA4 (coord T7), U108[D5]
152 @{ */
153 /* @} */
154
155/*! @name FLEXSPI0A_DATA5 (coord U7), U108[E3]
156 @{ */
157 /* @} */
158
159/*! @name FLEXSPI0A_DATA6 (coord R7), U108[E2]
160 @{ */
161 /* @} */
162
163/*! @name FLEXSPI0A_DATA7 (coord T8), U108[E1]
164 @{ */
165 /* @} */
166
167/*! @name FLEXSPI0A_DQS (coord U9), U108[C3]
168 @{ */
169 /* @} */
170
171/*! @name FLEXSPI0A_SCLK (coord T9), U108[B2]
172 @{ */
173 /* @} */
174
175/*! @name FLEXSPI0A_SS0_N (coord T4), U108[A3]
176 @{ */
177 /* @} */
178
179/*!
180 * @brief Configures pin routing and optionally pin electrical features.
181 *
182 */
183void BOARD_InitPSRAMPins(void); /* Function assigned for the Cortex-M33 */
184
185#define IOPCTL_PIO_ANAMUX_DI 0x00u /*!<@brief Analog mux is disabled */
186#define IOPCTL_PIO_FULLDRIVE_DI 0x00u /*!<@brief Normal drive */
187#define IOPCTL_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */
188#define IOPCTL_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */
189#define IOPCTL_PIO_INBUF_DI 0x00u /*!<@brief Disable input buffer function */
190#define IOPCTL_PIO_INBUF_EN 0x40u /*!<@brief Enables input buffer function */
191#define IOPCTL_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
192#define IOPCTL_PIO_PSEDRAIN_DI 0x00u /*!<@brief Pseudo Output Drain is disabled */
193#define IOPCTL_PIO_PULLDOWN_EN 0x00u /*!<@brief Enable pull-down function */
194#define IOPCTL_PIO_PULLUP_EN 0x20u /*!<@brief Enable pull-up function */
195#define IOPCTL_PIO_PUPD_DI 0x00u /*!<@brief Disable pull-up / pull-down function */
196#define IOPCTL_PIO_PUPD_EN 0x10u /*!<@brief Enable pull-up / pull-down function */
197#define IOPCTL_PIO_SLEW_RATE_NORMAL 0x00u /*!<@brief Normal mode */
198
199/*! @name SD0_D0 (coord R11), J32[7]/SD_DAT0
200 @{ */
201 /* @} */
202
203/*! @name SD0_D1 (coord T11), J32[8]/SD_DAT1
204 @{ */
205 /* @} */
206
207/*! @name SD0_D2 (coord U11), J32[9]/SD_DAT2
208 @{ */
209 /* @} */
210
211/*! @name SD0_D3 (coord T12), J32[1]/SD_DAT3
212 @{ */
213 /* @} */
214
215/*! @name SD0_CLK (coord P10), J32[5]/SD_CLK
216 @{ */
217 /* @} */
218
219/*! @name SD0_CMD (coord R9), J32[2]/SD_CMD
220 @{ */
221 /* @} */
222
223/*! @name SD0_CARD_DET_N (coord R13), J32[10]/CARD_CD/SD_CD
224 @{ */
225 /* @} */
226
227/*! @name PIO2_10 (coord T15), U23[3]/SD_RST_N
228 @{ */
229#define BOARD_INITUSDHC0PINS_SD_RST_N_GPIO GPIO /*!<@brief GPIO device name: GPIO */
230#define BOARD_INITUSDHC0PINS_SD_RST_N_PORT 2U /*!<@brief PORT device name: 2U */
231#define BOARD_INITUSDHC0PINS_SD_RST_N_PIN 10U /*!<@brief 2U pin index: 10 */
232 /* @} */
233
234/*!
235 * @brief Configures pin routing and optionally pin electrical features.
236 *
237 */
238void BOARD_InitUSDHC0Pins(void); /* Function assigned for the Cortex-M33 */
239
240#define IOPCTL_PIO_ANAMUX_DI 0x00u /*!<@brief Analog mux is disabled */
241#define IOPCTL_PIO_FULLDRIVE_DI 0x00u /*!<@brief Normal drive */
242#define IOPCTL_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */
243#define IOPCTL_PIO_INBUF_DI 0x00u /*!<@brief Disable input buffer function */
244#define IOPCTL_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
245#define IOPCTL_PIO_PSEDRAIN_DI 0x00u /*!<@brief Pseudo Output Drain is disabled */
246#define IOPCTL_PIO_PULLDOWN_EN 0x00u /*!<@brief Enable pull-down function */
247#define IOPCTL_PIO_PUPD_DI 0x00u /*!<@brief Disable pull-up / pull-down function */
248#define IOPCTL_PIO_SLEW_RATE_NORMAL 0x00u /*!<@brief Normal mode */
249
250/*! @name PIO0_14 (coord A3), Q4[5]
251 @{ */
252/*!
253 * @brief GPIO device name: GPIO */
254#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO
255/*!
256 * @brief PORT device name: 0U */
257#define BOARD_INITLEDSPINS_LED_GREEN_PORT 0U
258/*!
259 * @brief 0U pin index: 14 */
260#define BOARD_INITLEDSPINS_LED_GREEN_PIN 14U
261/* @} */
262
263/*! @name PIO0_26 (coord A2), Q3[2]
264 @{ */
265#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO /*!<@brief GPIO device name: GPIO */
266#define BOARD_INITLEDSPINS_LED_BLUE_PORT 0U /*!<@brief PORT device name: 0U */
267#define BOARD_INITLEDSPINS_LED_BLUE_PIN 26U /*!<@brief 0U pin index: 26 */
268 /* @} */
269
270/*! @name PIO0_31 (coord A11), Q4[2]
271 @{ */
272#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO /*!<@brief GPIO device name: GPIO */
273#define BOARD_INITLEDSPINS_LED_RED_PORT 0U /*!<@brief PORT device name: 0U */
274#define BOARD_INITLEDSPINS_LED_RED_PIN 31U /*!<@brief 0U pin index: 31 */
275 /* @} */
276
277/*!
278 * @brief Configures pin routing and optionally pin electrical features.
279 *
280 */
281void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M33 */
282
283#define IOPCTL_PIO_ANAMUX_DI 0x00u /*!<@brief Analog mux is disabled */
284#define IOPCTL_PIO_FULLDRIVE_DI 0x00u /*!<@brief Normal drive */
285#define IOPCTL_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */
286#define IOPCTL_PIO_INBUF_EN 0x40u /*!<@brief Enables input buffer function */
287#define IOPCTL_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
288#define IOPCTL_PIO_PSEDRAIN_DI 0x00u /*!<@brief Pseudo Output Drain is disabled */
289#define IOPCTL_PIO_PULLDOWN_EN 0x00u /*!<@brief Enable pull-down function */
290#define IOPCTL_PIO_PUPD_DI 0x00u /*!<@brief Disable pull-up / pull-down function */
291#define IOPCTL_PIO_SLEW_RATE_NORMAL 0x00u /*!<@brief Normal mode */
292
293/*! @name PIO0_10 (coord J3), SW2
294 @{ */
295#define BOARD_INITBUTTONSPINS_SW2_GPIO GPIO /*!<@brief GPIO device name: GPIO */
296#define BOARD_INITBUTTONSPINS_SW2_PORT 0U /*!<@brief PORT device name: 0U */
297#define BOARD_INITBUTTONSPINS_SW2_PIN 10U /*!<@brief 0U pin index: 10 */
298 /* @} */
299
300/*! @name PIO1_1 (coord G15), SW1
301 @{ */
302#define BOARD_INITBUTTONSPINS_SW1_GPIO GPIO /*!<@brief GPIO device name: GPIO */
303#define BOARD_INITBUTTONSPINS_SW1_PORT 1U /*!<@brief PORT device name: 1U */
304#define BOARD_INITBUTTONSPINS_SW1_PIN 1U /*!<@brief 1U pin index: 1 */
305 /* @} */
306
307/*! @name RESETN (coord B15), JP16[3]/JP14[2]
308 @{ */
309 /* @} */
310
311/*!
312 * @brief Configures pin routing and optionally pin electrical features.
313 *
314 */
315void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M33 */
316
317#define IOPCTL_PIO_ANAMUX_DI 0x00u /*!<@brief Analog mux is disabled */
318#define IOPCTL_PIO_FULLDRIVE_DI 0x00u /*!<@brief Normal drive */
319#define IOPCTL_PIO_FULLDRIVE_EN 0x0100u /*!<@brief Full drive enable */
320#define IOPCTL_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */
321#define IOPCTL_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */
322#define IOPCTL_PIO_INBUF_DI 0x00u /*!<@brief Disable input buffer function */
323#define IOPCTL_PIO_INBUF_EN 0x40u /*!<@brief Enables input buffer function */
324#define IOPCTL_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
325#define IOPCTL_PIO_PSEDRAIN_DI 0x00u /*!<@brief Pseudo Output Drain is disabled */
326#define IOPCTL_PIO_PSEDRAIN_EN 0x0400u /*!<@brief Pseudo Output Drain is enabled */
327#define IOPCTL_PIO_PULLDOWN_EN 0x00u /*!<@brief Enable pull-down function */
328#define IOPCTL_PIO_PULLUP_EN 0x20u /*!<@brief Enable pull-up function */
329#define IOPCTL_PIO_PUPD_DI 0x00u /*!<@brief Disable pull-up / pull-down function */
330#define IOPCTL_PIO_PUPD_EN 0x10u /*!<@brief Enable pull-up / pull-down function */
331#define IOPCTL_PIO_SLEW_RATE_NORMAL 0x00u /*!<@brief Normal mode */
332
333/*! @name FC2_RTS_SCL_SSEL1 (coord B7), J28[10]/J30[6]/U6[4]
334 @{ */
335 /* @} */
336
337/*! @name FC2_CTS_SDA_SSEL0 (coord D7), J28[9]/J30[5]/J47[8]/U6[6]
338 @{ */
339/* @} */
340
341/*! @name PIO1_5 (coord J16), J28[4]/JP30[1]/J45[22]
342 @{ */
343#define BOARD_INITACCELPINS_ACC_INT_GPIO GPIO /*!<@brief GPIO device name: GPIO */
344#define BOARD_INITACCELPINS_ACC_INT_PORT 1U /*!<@brief PORT device name: 1U */
345#define BOARD_INITACCELPINS_ACC_INT_PIN 5U /*!<@brief 1U pin index: 5 */
346 /* @} */
347
348/*! @name PIO1_7 (coord J15), J28[2]/J45[36]
349 @{ */
350/*!
351 * @brief GPIO device name: GPIO */
352#define BOARD_INITACCELPINS_ACC_RESET_GPIO GPIO
353/*!
354 * @brief PORT device name: 1U */
355#define BOARD_INITACCELPINS_ACC_RESET_PORT 1U
356/*!
357 * @brief 1U pin index: 7 */
358#define BOARD_INITACCELPINS_ACC_RESET_PIN 7U
359/* @} */
360
361/*!
362 * @brief Configures pin routing and optionally pin electrical features.
363 *
364 */
365void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 */
366
367#if defined(__cplusplus)
368}
369#endif
370
371/*!
372 * @}
373 */
374#endif /* _PIN_MUX_H_ */
375
376/***********************************************************************************************************************
377 * EOF
378 **********************************************************************************************************************/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 16:58:08 +0100