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diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk32l3a6/project_template/cm4/pin_mux.h b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk32l3a6/project_template/cm4/pin_mux.h
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1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PIN_MUX_H_
14#define _PIN_MUX_H_
15
16/***********************************************************************************************************************
17 * Definitions
18 **********************************************************************************************************************/
19
20/*! @brief Direction type */
21typedef enum _pin_mux_direction
22{
23 kPIN_MUX_DirectionInput = 0U, /* Input direction */
24 kPIN_MUX_DirectionOutput = 1U, /* Output direction */
25 kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
26} pin_mux_direction_t;
27
28/*!
29 * @addtogroup pin_mux
30 * @{
31 */
32
33/***********************************************************************************************************************
34 * API
35 **********************************************************************************************************************/
36
37#if defined(__cplusplus)
38extern "C" {
39#endif
40
41/*!
42 * @brief Calls initialization functions.
43 *
44 */
45void BOARD_InitBootPins(void);
46
47/*!
48 * @brief Configures pin routing and optionally pin electrical features.
49 *
50 */
51void BOARD_InitPins_cm4(void); /* Function assigned for the Cortex-M4F */
52
53/*! @name PORTA0 (coord B10), BUTTON_NMI
54 @{ */
55#define BOARD_INITBUTTONSPINS_SW2_PERIPHERAL GPIOA /*!<@brief Device name: GPIOA */
56#define BOARD_INITBUTTONSPINS_SW2_SIGNAL GPIO /*!<@brief GPIOA signal: GPIO */
57#define BOARD_INITBUTTONSPINS_SW2_GPIO GPIOA /*!<@brief GPIO device name: GPIOA */
58#define BOARD_INITBUTTONSPINS_SW2_GPIO_PIN 0U /*!<@brief PORTA pin index: 0 */
59#define BOARD_INITBUTTONSPINS_SW2_PORT PORTA /*!<@brief PORT device name: PORTA */
60#define BOARD_INITBUTTONSPINS_SW2_PIN 0U /*!<@brief PORTA pin index: 0 */
61#define BOARD_INITBUTTONSPINS_SW2_CHANNEL 0 /*!<@brief GPIOA GPIO channel: 0 */
62#define BOARD_INITBUTTONSPINS_SW2_PIN_NAME PTA0 /*!<@brief Pin name */
63#define BOARD_INITBUTTONSPINS_SW2_LABEL "BUTTON_NMI" /*!<@brief Label */
64#define BOARD_INITBUTTONSPINS_SW2_NAME "SW2" /*!<@brief Identifier name */
65#define BOARD_INITBUTTONSPINS_SW2_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
66 /* @} */
67
68/*! @name PORTE8 (coord P16), BUTTON_LLWUP23
69 @{ */
70#define BOARD_INITBUTTONSPINS_SW3_PERIPHERAL GPIOE /*!<@brief Device name: GPIOE */
71#define BOARD_INITBUTTONSPINS_SW3_SIGNAL GPIO /*!<@brief GPIOE signal: GPIO */
72#define BOARD_INITBUTTONSPINS_SW3_FGPIO FGPIOE /*!<@brief FGPIO device name: FGPIOE */
73#define BOARD_INITBUTTONSPINS_SW3_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
74#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN 8U /*!<@brief PORTE pin index: 8 */
75#define BOARD_INITBUTTONSPINS_SW3_PORT PORTE /*!<@brief PORT device name: PORTE */
76#define BOARD_INITBUTTONSPINS_SW3_PIN 8U /*!<@brief PORTE pin index: 8 */
77#define BOARD_INITBUTTONSPINS_SW3_CHANNEL 8 /*!<@brief GPIOE GPIO channel: 8 */
78#define BOARD_INITBUTTONSPINS_SW3_PIN_NAME PTE8 /*!<@brief Pin name */
79#define BOARD_INITBUTTONSPINS_SW3_LABEL "BUTTON_LLWUP23" /*!<@brief Label */
80#define BOARD_INITBUTTONSPINS_SW3_NAME "SW3" /*!<@brief Identifier name */
81#define BOARD_INITBUTTONSPINS_SW3_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
82 /* @} */
83
84/*! @name PORTE9 (coord N16), BUTTON_LLWUP24
85 @{ */
86#define BOARD_INITBUTTONSPINS_SW4_PERIPHERAL GPIOE /*!<@brief Device name: GPIOE */
87#define BOARD_INITBUTTONSPINS_SW4_SIGNAL GPIO /*!<@brief GPIOE signal: GPIO */
88#define BOARD_INITBUTTONSPINS_SW4_FGPIO FGPIOE /*!<@brief FGPIO device name: FGPIOE */
89#define BOARD_INITBUTTONSPINS_SW4_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
90#define BOARD_INITBUTTONSPINS_SW4_GPIO_PIN 9U /*!<@brief PORTE pin index: 9 */
91#define BOARD_INITBUTTONSPINS_SW4_PORT PORTE /*!<@brief PORT device name: PORTE */
92#define BOARD_INITBUTTONSPINS_SW4_PIN 9U /*!<@brief PORTE pin index: 9 */
93#define BOARD_INITBUTTONSPINS_SW4_CHANNEL 9 /*!<@brief GPIOE GPIO channel: 9 */
94#define BOARD_INITBUTTONSPINS_SW4_PIN_NAME PTE9 /*!<@brief Pin name */
95#define BOARD_INITBUTTONSPINS_SW4_LABEL "BUTTON_LLWUP24" /*!<@brief Label */
96#define BOARD_INITBUTTONSPINS_SW4_NAME "SW4" /*!<@brief Identifier name */
97#define BOARD_INITBUTTONSPINS_SW4_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
98 /* @} */
99
100/*! @name PORTE12 (coord L12), BUTTON_LLWUP26
101 @{ */
102#define BOARD_INITBUTTONSPINS_SW5_PERIPHERAL GPIOE /*!<@brief Device name: GPIOE */
103#define BOARD_INITBUTTONSPINS_SW5_SIGNAL GPIO /*!<@brief GPIOE signal: GPIO */
104#define BOARD_INITBUTTONSPINS_SW5_FGPIO FGPIOE /*!<@brief FGPIO device name: FGPIOE */
105#define BOARD_INITBUTTONSPINS_SW5_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
106#define BOARD_INITBUTTONSPINS_SW5_GPIO_PIN 12U /*!<@brief PORTE pin index: 12 */
107#define BOARD_INITBUTTONSPINS_SW5_PORT PORTE /*!<@brief PORT device name: PORTE */
108#define BOARD_INITBUTTONSPINS_SW5_PIN 12U /*!<@brief PORTE pin index: 12 */
109#define BOARD_INITBUTTONSPINS_SW5_CHANNEL 12 /*!<@brief GPIOE GPIO channel: 12 */
110#define BOARD_INITBUTTONSPINS_SW5_PIN_NAME PTE12 /*!<@brief Pin name */
111#define BOARD_INITBUTTONSPINS_SW5_LABEL "BUTTON_LLWUP26" /*!<@brief Label */
112#define BOARD_INITBUTTONSPINS_SW5_NAME "SW5" /*!<@brief Identifier name */
113#define BOARD_INITBUTTONSPINS_SW5_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
114 /* @} */
115
116/*!
117 * @brief Configures pin routing and optionally pin electrical features.
118 *
119 */
120void BOARD_InitButtonsPins(void); /* Function assigned for the Cortex-M4F */
121
122/*! @name PORTA22 (coord B6), Q6[2]/LED_BLUE
123 @{ */
124#define BOARD_INITLEDSPINS_RGB_BLUE_PERIPHERAL GPIOA /*!<@brief Device name: GPIOA */
125#define BOARD_INITLEDSPINS_RGB_BLUE_SIGNAL GPIO /*!<@brief GPIOA signal: GPIO */
126#define BOARD_INITLEDSPINS_RGB_BLUE_GPIO GPIOA /*!<@brief GPIO device name: GPIOA */
127#define BOARD_INITLEDSPINS_RGB_BLUE_GPIO_PIN 22U /*!<@brief PORTA pin index: 22 */
128#define BOARD_INITLEDSPINS_RGB_BLUE_PORT PORTA /*!<@brief PORT device name: PORTA */
129#define BOARD_INITLEDSPINS_RGB_BLUE_PIN 22U /*!<@brief PORTA pin index: 22 */
130#define BOARD_INITLEDSPINS_RGB_BLUE_CHANNEL 22 /*!<@brief GPIOA GPIO channel: 22 */
131#define BOARD_INITLEDSPINS_RGB_BLUE_PIN_NAME PTA22 /*!<@brief Pin name */
132#define BOARD_INITLEDSPINS_RGB_BLUE_LABEL "Q6[2]/LED_BLUE" /*!<@brief Label */
133#define BOARD_INITLEDSPINS_RGB_BLUE_NAME "RGB_BLUE" /*!<@brief Identifier name */
134#define BOARD_INITLEDSPINS_RGB_BLUE_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
135 /* @} */
136
137/*! @name PORTA23 (coord E6), Q7[5]/LED_GREEN
138 @{ */
139#define BOARD_INITLEDSPINS_RGB_GREEN_PERIPHERAL GPIOA /*!<@brief Device name: GPIOA */
140#define BOARD_INITLEDSPINS_RGB_GREEN_SIGNAL GPIO /*!<@brief GPIOA signal: GPIO */
141#define BOARD_INITLEDSPINS_RGB_GREEN_GPIO GPIOA /*!<@brief GPIO device name: GPIOA */
142#define BOARD_INITLEDSPINS_RGB_GREEN_GPIO_PIN 23U /*!<@brief PORTA pin index: 23 */
143#define BOARD_INITLEDSPINS_RGB_GREEN_PORT PORTA /*!<@brief PORT device name: PORTA */
144#define BOARD_INITLEDSPINS_RGB_GREEN_PIN 23U /*!<@brief PORTA pin index: 23 */
145#define BOARD_INITLEDSPINS_RGB_GREEN_CHANNEL 23 /*!<@brief GPIOA GPIO channel: 23 */
146#define BOARD_INITLEDSPINS_RGB_GREEN_PIN_NAME PTA23 /*!<@brief Pin name */
147#define BOARD_INITLEDSPINS_RGB_GREEN_LABEL "Q7[5]/LED_GREEN" /*!<@brief Label */
148#define BOARD_INITLEDSPINS_RGB_GREEN_NAME "RGB_GREEN" /*!<@brief Identifier name */
149#define BOARD_INITLEDSPINS_RGB_GREEN_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
150 /* @} */
151
152/*! @name PORTA24 (coord D6), Q7[2]/LED_RED
153 @{ */
154#define BOARD_INITLEDSPINS_RGB_RED_PERIPHERAL GPIOA /*!<@brief Device name: GPIOA */
155#define BOARD_INITLEDSPINS_RGB_RED_SIGNAL GPIO /*!<@brief GPIOA signal: GPIO */
156#define BOARD_INITLEDSPINS_RGB_RED_GPIO GPIOA /*!<@brief GPIO device name: GPIOA */
157#define BOARD_INITLEDSPINS_RGB_RED_GPIO_PIN 24U /*!<@brief PORTA pin index: 24 */
158#define BOARD_INITLEDSPINS_RGB_RED_PORT PORTA /*!<@brief PORT device name: PORTA */
159#define BOARD_INITLEDSPINS_RGB_RED_PIN 24U /*!<@brief PORTA pin index: 24 */
160#define BOARD_INITLEDSPINS_RGB_RED_CHANNEL 24 /*!<@brief GPIOA GPIO channel: 24 */
161#define BOARD_INITLEDSPINS_RGB_RED_PIN_NAME PTA24 /*!<@brief Pin name */
162#define BOARD_INITLEDSPINS_RGB_RED_LABEL "Q7[2]/LED_RED" /*!<@brief Label */
163#define BOARD_INITLEDSPINS_RGB_RED_NAME "RGB_RED" /*!<@brief Identifier name */
164#define BOARD_INITLEDSPINS_RGB_RED_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
165 /* @} */
166//note can be FGPIE on cortex M0+
167#define BOARD_INITLEDSPINS_LED_RED_PERIPHERAL GPIOE /*!<@brief Device name: GPIOE */
168#define BOARD_INITLEDSPINS_LED_RED_SIGNAL GPIO /*!<@brief GPIOA signal: GPIO */
169#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
170#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN 0U /*!<@brief PORTE pin index: 0 */
171#define BOARD_INITLEDSPINS_LED_RED_PORT PORTE /*!<@brief PORT device name: PORTE */
172#define BOARD_INITLEDSPINS_LED_RED_PIN 0U /*!<@brief PORTE pin index: 0 */
173#define BOARD_INITLEDSPINS_LED_RED_CHANNEL 0 /*!<@brief GPIOA GPIO channel: 0 */
174#define BOARD_INITLEDSPINS_LED_RED_PIN_NAME PTE0 /*!<@brief Pin name */
175#define BOARD_INITLEDSPINS_LED_RED_LABEL "LED_RED" /*!<@brief Label */
176#define BOARD_INITLEDSPINS_LED_RED_NAME "RED" /*!<@brief Identifier name */
177#define BOARD_INITLEDSPINS_LED_RED_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
178
179/*!
180 * @brief Configures pin routing and optionally pin electrical features.
181 *
182 */
183void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M4F */
184
185/*! @name PORTC7 (coord N2), U40[1]/K32L_UART0_RX
186 @{ */
187#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_RX_PERIPHERAL LPUART0 /*!<@brief Device name: LPUART0 */
188#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_RX_SIGNAL RX /*!<@brief LPUART0 signal: RX */
189#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_RX_PORT PORTC /*!<@brief PORT device name: PORTC */
190#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_RX_PIN 7U /*!<@brief PORTC pin index: 7 */
191#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_RX_PIN_NAME LPUART0_RX /*!<@brief Pin name */
192#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_RX_LABEL "U40[1]/K32L_UART0_RX" /*!<@brief Label */
193#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_RX_NAME "DEBUG_UART0_RX" /*!<@brief Identifier name */
194 /* @} */
195
196/*! @name PORTC8 (coord P3), U11[1]/K32L_UART0_TX
197 @{ */
198#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_TX_PERIPHERAL LPUART0 /*!<@brief Device name: LPUART0 */
199#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_TX_SIGNAL TX /*!<@brief LPUART0 signal: TX */
200#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_TX_PORT PORTC /*!<@brief PORT device name: PORTC */
201#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_TX_PIN 8U /*!<@brief PORTC pin index: 8 */
202#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_TX_PIN_NAME LPUART0_TX /*!<@brief Pin name */
203#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_TX_LABEL "U11[1]/K32L_UART0_TX" /*!<@brief Label */
204#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_TX_NAME "DEBUG_UART0_TX" /*!<@brief Identifier name */
205 /* @} */
206
207/*!
208 * @brief Configures pin routing and optionally pin electrical features.
209 *
210 */
211void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M4F */
212
213/*! @name EXTAL32 (coord E16), Y1[1]/EXTAL_32KHZ
214 @{ */
215#define BOARD_INITOSCPINS_EXTAL32_PERIPHERAL RTC /*!<@brief Device name: RTC */
216#define BOARD_INITOSCPINS_EXTAL32_SIGNAL EXTAL32 /*!<@brief RTC signal: EXTAL32 */
217#define BOARD_INITOSCPINS_EXTAL32_PIN_NAME EXTAL32 /*!<@brief Pin name */
218#define BOARD_INITOSCPINS_EXTAL32_LABEL "Y1[1]/EXTAL_32KHZ" /*!<@brief Label */
219#define BOARD_INITOSCPINS_EXTAL32_NAME "EXTAL32" /*!<@brief Identifier name */
220 /* @} */
221
222/*! @name XTAL32 (coord E17), Y1[2]/XTAL_32KHZ
223 @{ */
224#define BOARD_INITOSCPINS_XTAL32_PERIPHERAL RTC /*!<@brief Device name: RTC */
225#define BOARD_INITOSCPINS_XTAL32_SIGNAL XTAL32 /*!<@brief RTC signal: XTAL32 */
226#define BOARD_INITOSCPINS_XTAL32_PIN_NAME XTAL32 /*!<@brief Pin name */
227#define BOARD_INITOSCPINS_XTAL32_LABEL "Y1[2]/XTAL_32KHZ" /*!<@brief Label */
228#define BOARD_INITOSCPINS_XTAL32_NAME "XTAL32" /*!<@brief Identifier name */
229 /* @} */
230
231/*!
232 * @brief Configures pin routing and optionally pin electrical features.
233 *
234 */
235void BOARD_InitOSCPins(void); /* Function assigned for the Cortex-M4F */
236
237/*! @name PORTE30 (coord G17), U14[4]/ACCEL_I2C3_SCL
238 @{ */
239#define BOARD_INITACCELPINS_ACCEL_SCL_PERIPHERAL LPI2C3 /*!<@brief Device name: LPI2C3 */
240#define BOARD_INITACCELPINS_ACCEL_SCL_SIGNAL SCL /*!<@brief LPI2C3 signal: SCL */
241#define BOARD_INITACCELPINS_ACCEL_SCL_PORT PORTE /*!<@brief PORT device name: PORTE */
242#define BOARD_INITACCELPINS_ACCEL_SCL_PIN 30U /*!<@brief PORTE pin index: 30 */
243#define BOARD_INITACCELPINS_ACCEL_SCL_PIN_NAME LPI2C3_SCL /*!<@brief Pin name */
244#define BOARD_INITACCELPINS_ACCEL_SCL_LABEL "U14[4]/ACCEL_I2C3_SCL" /*!<@brief Label */
245#define BOARD_INITACCELPINS_ACCEL_SCL_NAME "ACCEL_SCL" /*!<@brief Identifier name */
246 /* @} */
247
248/*! @name PORTE29 (coord G15), U14[6]/ACCEL_I2C3_SDA
249 @{ */
250#define BOARD_INITACCELPINS_ACCEL_SDA_PERIPHERAL LPI2C3 /*!<@brief Device name: LPI2C3 */
251#define BOARD_INITACCELPINS_ACCEL_SDA_SIGNAL SDA /*!<@brief LPI2C3 signal: SDA */
252#define BOARD_INITACCELPINS_ACCEL_SDA_PORT PORTE /*!<@brief PORT device name: PORTE */
253#define BOARD_INITACCELPINS_ACCEL_SDA_PIN 29U /*!<@brief PORTE pin index: 29 */
254#define BOARD_INITACCELPINS_ACCEL_SDA_PIN_NAME LPI2C3_SDA /*!<@brief Pin name */
255#define BOARD_INITACCELPINS_ACCEL_SDA_LABEL "U14[6]/ACCEL_I2C3_SDA" /*!<@brief Label */
256#define BOARD_INITACCELPINS_ACCEL_SDA_NAME "ACCEL_SDA" /*!<@brief Identifier name */
257 /* @} */
258
259/*! @name PORTE1 (coord R16), U14[11]/ACCEL_INT1
260 @{ */
261#define BOARD_INITACCELPINS_ACCEL_INT1_PERIPHERAL GPIOE /*!<@brief Device name: GPIOE */
262#define BOARD_INITACCELPINS_ACCEL_INT1_SIGNAL GPIO /*!<@brief GPIOE signal: GPIO */
263#define BOARD_INITACCELPINS_ACCEL_INT1_FGPIO FGPIOE /*!<@brief FGPIO device name: FGPIOE */
264#define BOARD_INITACCELPINS_ACCEL_INT1_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
265#define BOARD_INITACCELPINS_ACCEL_INT1_GPIO_PIN 1U /*!<@brief PORTE pin index: 1 */
266#define BOARD_INITACCELPINS_ACCEL_INT1_PORT PORTE /*!<@brief PORT device name: PORTE */
267#define BOARD_INITACCELPINS_ACCEL_INT1_PIN 1U /*!<@brief PORTE pin index: 1 */
268#define BOARD_INITACCELPINS_ACCEL_INT1_CHANNEL 1 /*!<@brief GPIOE GPIO channel: 1 */
269#define BOARD_INITACCELPINS_ACCEL_INT1_PIN_NAME PTE1 /*!<@brief Pin name */
270#define BOARD_INITACCELPINS_ACCEL_INT1_LABEL "U14[11]/ACCEL_INT1" /*!<@brief Label */
271#define BOARD_INITACCELPINS_ACCEL_INT1_NAME "ACCEL_INT1" /*!<@brief Identifier name */
272#define BOARD_INITACCELPINS_ACCEL_INT1_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
273 /* @} */
274
275/*! @name PORTE22 (coord J16), U14[9]/ACCEL_INT2
276 @{ */
277#define BOARD_INITACCELPINS_ACCEL_INT2_PERIPHERAL GPIOE /*!<@brief Device name: GPIOE */
278#define BOARD_INITACCELPINS_ACCEL_INT2_SIGNAL GPIO /*!<@brief GPIOE signal: GPIO */
279#define BOARD_INITACCELPINS_ACCEL_INT2_FGPIO FGPIOE /*!<@brief FGPIO device name: FGPIOE */
280#define BOARD_INITACCELPINS_ACCEL_INT2_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
281#define BOARD_INITACCELPINS_ACCEL_INT2_GPIO_PIN 22U /*!<@brief PORTE pin index: 22 */
282#define BOARD_INITACCELPINS_ACCEL_INT2_PORT PORTE /*!<@brief PORT device name: PORTE */
283#define BOARD_INITACCELPINS_ACCEL_INT2_PIN 22U /*!<@brief PORTE pin index: 22 */
284#define BOARD_INITACCELPINS_ACCEL_INT2_CHANNEL 22 /*!<@brief GPIOE GPIO channel: 22 */
285#define BOARD_INITACCELPINS_ACCEL_INT2_PIN_NAME PTE22 /*!<@brief Pin name */
286#define BOARD_INITACCELPINS_ACCEL_INT2_LABEL "U14[9]/ACCEL_INT2" /*!<@brief Label */
287#define BOARD_INITACCELPINS_ACCEL_INT2_NAME "ACCEL_INT2" /*!<@brief Identifier name */
288#define BOARD_INITACCELPINS_ACCEL_INT2_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
289 /* @} */
290
291/*! @name PORTE27 (coord H14), U14[16]/ACCEL_RST
292 @{ */
293#define BOARD_INITACCELPINS_ACCEL_RST_PERIPHERAL GPIOE /*!<@brief Device name: GPIOE */
294#define BOARD_INITACCELPINS_ACCEL_RST_SIGNAL GPIO /*!<@brief GPIOE signal: GPIO */
295#define BOARD_INITACCELPINS_ACCEL_RST_FGPIO FGPIOE /*!<@brief FGPIO device name: FGPIOE */
296#define BOARD_INITACCELPINS_ACCEL_RST_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
297#define BOARD_INITACCELPINS_ACCEL_RST_GPIO_PIN 27U /*!<@brief PORTE pin index: 27 */
298#define BOARD_INITACCELPINS_ACCEL_RST_PORT PORTE /*!<@brief PORT device name: PORTE */
299#define BOARD_INITACCELPINS_ACCEL_RST_PIN 27U /*!<@brief PORTE pin index: 27 */
300#define BOARD_INITACCELPINS_ACCEL_RST_CHANNEL 27 /*!<@brief GPIOE GPIO channel: 27 */
301#define BOARD_INITACCELPINS_ACCEL_RST_PIN_NAME PTE27 /*!<@brief Pin name */
302#define BOARD_INITACCELPINS_ACCEL_RST_LABEL "U14[16]/ACCEL_RST" /*!<@brief Label */
303#define BOARD_INITACCELPINS_ACCEL_RST_NAME "ACCEL_RST" /*!<@brief Identifier name */
304#define BOARD_INITACCELPINS_ACCEL_RST_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
305 /* @} */
306
307/*!
308 * @brief Configures pin routing and optionally pin electrical features.
309 *
310 */
311void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M4F */
312
313/*! @name PORTB9 (coord F4), J4[6]/J47[2]/ARDUINO_A2/ADC0_SE3
314 @{ */
315/*!
316 * @brief Device name: GPIOB */
317#define BOARD_INITLIGHT_SENSORPINS_SNS_LIGHT_ADC_PERIPHERAL GPIOB
318/*!
319 * @brief GPIOB signal: GPIO */
320#define BOARD_INITLIGHT_SENSORPINS_SNS_LIGHT_ADC_SIGNAL GPIO
321/*!
322 * @brief GPIO device name: GPIOB */
323#define BOARD_INITLIGHT_SENSORPINS_SNS_LIGHT_ADC_GPIO GPIOB
324/*!
325 * @brief PORTB pin index: 9 */
326#define BOARD_INITLIGHT_SENSORPINS_SNS_LIGHT_ADC_GPIO_PIN 9U
327/*!
328 * @brief PORT device name: PORTB */
329#define BOARD_INITLIGHT_SENSORPINS_SNS_LIGHT_ADC_PORT PORTB
330/*!
331 * @brief PORTB pin index: 9 */
332#define BOARD_INITLIGHT_SENSORPINS_SNS_LIGHT_ADC_PIN 9U
333/*!
334 * @brief GPIOB GPIO channel: 9 */
335#define BOARD_INITLIGHT_SENSORPINS_SNS_LIGHT_ADC_CHANNEL 9
336/*!
337 * @brief Pin name */
338#define BOARD_INITLIGHT_SENSORPINS_SNS_LIGHT_ADC_PIN_NAME PTB9
339/*!
340 * @brief Label */
341#define BOARD_INITLIGHT_SENSORPINS_SNS_LIGHT_ADC_LABEL "J4[6]/J47[2]/ARDUINO_A2/ADC0_SE3"
342/*!
343 * @brief Identifier name */
344#define BOARD_INITLIGHT_SENSORPINS_SNS_LIGHT_ADC_NAME "SNS_LIGHT_ADC"
345/* @} */
346
347/*!
348 * @brief Configures pin routing and optionally pin electrical features.
349 *
350 */
351void BOARD_InitLIGHT_SENSORPins(void); /* Function assigned for the Cortex-M4F */
352
353/*! @name USB0_DM (coord T12), J8[2]/K32L_USB_DN
354 @{ */
355#define BOARD_INITUSBPINS_USB0_DM_PERIPHERAL USB0 /*!<@brief Device name: USB0 */
356#define BOARD_INITUSBPINS_USB0_DM_SIGNAL DM /*!<@brief USB0 signal: DM */
357#define BOARD_INITUSBPINS_USB0_DM_PIN_NAME USB0_DM /*!<@brief Pin name */
358#define BOARD_INITUSBPINS_USB0_DM_LABEL "J8[2]/K32L_USB_DN" /*!<@brief Label */
359#define BOARD_INITUSBPINS_USB0_DM_NAME "USB0_DM" /*!<@brief Identifier name */
360 /* @} */
361
362/*! @name USB0_DP (coord T11), J8[3]/K32L_USB_DP
363 @{ */
364#define BOARD_INITUSBPINS_USB0_DP_PERIPHERAL USB0 /*!<@brief Device name: USB0 */
365#define BOARD_INITUSBPINS_USB0_DP_SIGNAL DP /*!<@brief USB0 signal: DP */
366#define BOARD_INITUSBPINS_USB0_DP_PIN_NAME USB0_DP /*!<@brief Pin name */
367#define BOARD_INITUSBPINS_USB0_DP_LABEL "J8[3]/K32L_USB_DP" /*!<@brief Label */
368#define BOARD_INITUSBPINS_USB0_DP_NAME "USB0_DP" /*!<@brief Identifier name */
369 /* @} */
370
371/*!
372 * @brief Configures pin routing and optionally pin electrical features.
373 *
374 */
375void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M4F */
376
377/*! @name PORTD11 (coord R11), J9[P1]/SDHC0_D2
378 @{ */
379#define BOARD_INITSDHCPINS_SDHC0_D2_PERIPHERAL USDHC0 /*!<@brief Device name: USDHC0 */
380#define BOARD_INITSDHCPINS_SDHC0_D2_SIGNAL DATA /*!<@brief USDHC0 signal: DATA */
381#define BOARD_INITSDHCPINS_SDHC0_D2_PORT PORTD /*!<@brief PORT device name: PORTD */
382#define BOARD_INITSDHCPINS_SDHC0_D2_PIN 11U /*!<@brief PORTD pin index: 11 */
383#define BOARD_INITSDHCPINS_SDHC0_D2_CHANNEL 2 /*!<@brief USDHC0 DATA channel: 2 */
384#define BOARD_INITSDHCPINS_SDHC0_D2_PIN_NAME SDHC0_D2 /*!<@brief Pin name */
385#define BOARD_INITSDHCPINS_SDHC0_D2_LABEL "J9[P1]/SDHC0_D2" /*!<@brief Label */
386#define BOARD_INITSDHCPINS_SDHC0_D2_NAME "SDHC0_D2" /*!<@brief Identifier name */
387 /* @} */
388
389/*! @name PORTD10 (coord P11), J9[P2]/SDHC0_D3
390 @{ */
391#define BOARD_INITSDHCPINS_SDHC0_D3_PERIPHERAL USDHC0 /*!<@brief Device name: USDHC0 */
392#define BOARD_INITSDHCPINS_SDHC0_D3_SIGNAL DATA /*!<@brief USDHC0 signal: DATA */
393#define BOARD_INITSDHCPINS_SDHC0_D3_PORT PORTD /*!<@brief PORT device name: PORTD */
394#define BOARD_INITSDHCPINS_SDHC0_D3_PIN 10U /*!<@brief PORTD pin index: 10 */
395#define BOARD_INITSDHCPINS_SDHC0_D3_CHANNEL 3 /*!<@brief USDHC0 DATA channel: 3 */
396#define BOARD_INITSDHCPINS_SDHC0_D3_PIN_NAME SDHC0_D3 /*!<@brief Pin name */
397#define BOARD_INITSDHCPINS_SDHC0_D3_LABEL "J9[P2]/SDHC0_D3" /*!<@brief Label */
398#define BOARD_INITSDHCPINS_SDHC0_D3_NAME "SDHC0_D3" /*!<@brief Identifier name */
399 /* @} */
400
401/*! @name PORTD9 (coord U11), J9[P3]/SDHC0_CMD
402 @{ */
403#define BOARD_INITSDHCPINS_SDHC0_CMD_PERIPHERAL USDHC0 /*!<@brief Device name: USDHC0 */
404#define BOARD_INITSDHCPINS_SDHC0_CMD_SIGNAL CMD /*!<@brief USDHC0 signal: CMD */
405#define BOARD_INITSDHCPINS_SDHC0_CMD_PORT PORTD /*!<@brief PORT device name: PORTD */
406#define BOARD_INITSDHCPINS_SDHC0_CMD_PIN 9U /*!<@brief PORTD pin index: 9 */
407#define BOARD_INITSDHCPINS_SDHC0_CMD_PIN_NAME SDHC0_CMD /*!<@brief Pin name */
408#define BOARD_INITSDHCPINS_SDHC0_CMD_LABEL "J9[P3]/SDHC0_CMD" /*!<@brief Label */
409#define BOARD_INITSDHCPINS_SDHC0_CMD_NAME "SDHC0_CMD" /*!<@brief Identifier name */
410 /* @} */
411
412/*! @name PORTD8 (coord T9), J9[P5]/SDHC0_DCLK
413 @{ */
414#define BOARD_INITSDHCPINS_SDHC0_DCLK_PERIPHERAL USDHC0 /*!<@brief Device name: USDHC0 */
415#define BOARD_INITSDHCPINS_SDHC0_DCLK_SIGNAL DCLK /*!<@brief USDHC0 signal: DCLK */
416#define BOARD_INITSDHCPINS_SDHC0_DCLK_PORT PORTD /*!<@brief PORT device name: PORTD */
417#define BOARD_INITSDHCPINS_SDHC0_DCLK_PIN 8U /*!<@brief PORTD pin index: 8 */
418#define BOARD_INITSDHCPINS_SDHC0_DCLK_PIN_NAME SDHC0_DCLK /*!<@brief Pin name */
419#define BOARD_INITSDHCPINS_SDHC0_DCLK_LABEL "J9[P5]/SDHC0_DCLK" /*!<@brief Label */
420#define BOARD_INITSDHCPINS_SDHC0_DCLK_NAME "SDHC0_DCLK" /*!<@brief Identifier name */
421 /* @} */
422
423/*! @name PORTD7 (coord P10), J9[P7]/SDHC0_D0
424 @{ */
425#define BOARD_INITSDHCPINS_SDHC0_D0_PERIPHERAL USDHC0 /*!<@brief Device name: USDHC0 */
426#define BOARD_INITSDHCPINS_SDHC0_D0_SIGNAL DATA /*!<@brief USDHC0 signal: DATA */
427#define BOARD_INITSDHCPINS_SDHC0_D0_PORT PORTD /*!<@brief PORT device name: PORTD */
428#define BOARD_INITSDHCPINS_SDHC0_D0_PIN 7U /*!<@brief PORTD pin index: 7 */
429#define BOARD_INITSDHCPINS_SDHC0_D0_CHANNEL 0 /*!<@brief USDHC0 DATA channel: 0 */
430#define BOARD_INITSDHCPINS_SDHC0_D0_PIN_NAME SDHC0_D0 /*!<@brief Pin name */
431#define BOARD_INITSDHCPINS_SDHC0_D0_LABEL "J9[P7]/SDHC0_D0" /*!<@brief Label */
432#define BOARD_INITSDHCPINS_SDHC0_D0_NAME "SDHC0_D0" /*!<@brief Identifier name */
433 /* @} */
434
435/*! @name PORTD6 (coord U9), J9[P8]/SDHC0_D1
436 @{ */
437#define BOARD_INITSDHCPINS_SDHC0_D1_PERIPHERAL USDHC0 /*!<@brief Device name: USDHC0 */
438#define BOARD_INITSDHCPINS_SDHC0_D1_SIGNAL DATA /*!<@brief USDHC0 signal: DATA */
439#define BOARD_INITSDHCPINS_SDHC0_D1_PORT PORTD /*!<@brief PORT device name: PORTD */
440#define BOARD_INITSDHCPINS_SDHC0_D1_PIN 6U /*!<@brief PORTD pin index: 6 */
441#define BOARD_INITSDHCPINS_SDHC0_D1_CHANNEL 1 /*!<@brief USDHC0 DATA channel: 1 */
442#define BOARD_INITSDHCPINS_SDHC0_D1_PIN_NAME SDHC0_D1 /*!<@brief Pin name */
443#define BOARD_INITSDHCPINS_SDHC0_D1_LABEL "J9[P8]/SDHC0_D1" /*!<@brief Label */
444#define BOARD_INITSDHCPINS_SDHC0_D1_NAME "SDHC0_D1" /*!<@brief Identifier name */
445 /* @} */
446
447/*! @name PORTC27 (coord P6), J9[G1]/SD_DETECT
448 @{ */
449#define BOARD_INITSDHCPINS_SD_DETECT_PERIPHERAL GPIOC /*!<@brief Device name: GPIOC */
450#define BOARD_INITSDHCPINS_SD_DETECT_SIGNAL GPIO /*!<@brief GPIOC signal: GPIO */
451#define BOARD_INITSDHCPINS_SD_DETECT_GPIO GPIOC /*!<@brief GPIO device name: GPIOC */
452#define BOARD_INITSDHCPINS_SD_DETECT_GPIO_PIN 27U /*!<@brief PORTC pin index: 27 */
453#define BOARD_INITSDHCPINS_SD_DETECT_PORT PORTC /*!<@brief PORT device name: PORTC */
454#define BOARD_INITSDHCPINS_SD_DETECT_PIN 27U /*!<@brief PORTC pin index: 27 */
455#define BOARD_INITSDHCPINS_SD_DETECT_CHANNEL 27 /*!<@brief GPIOC GPIO channel: 27 */
456#define BOARD_INITSDHCPINS_SD_DETECT_PIN_NAME PTC27 /*!<@brief Pin name */
457#define BOARD_INITSDHCPINS_SD_DETECT_LABEL "J9[G1]/SD_DETECT" /*!<@brief Label */
458#define BOARD_INITSDHCPINS_SD_DETECT_NAME "SD_DETECT" /*!<@brief Identifier name */
459#define BOARD_INITSDHCPINS_SD_DETECT_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
460 /* @} */
461
462/*!
463 * @brief Configures pin routing and optionally pin electrical features.
464 *
465 */
466void BOARD_InitSDHCPins(void); /* Function assigned for the Cortex-M4F */
467
468#if defined(__cplusplus)
469}
470#endif
471
472/*!
473 * @}
474 */
475#endif /* _PIN_MUX_H_ */
476
477/***********************************************************************************************************************
478 * EOF
479 **********************************************************************************************************************/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 17:03:27 +0100