1 files changed, 323 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk64f/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk64f/project_template/clock_config.c
new file mode 100644
index 000000000..1504635c3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk64f/project_template/clock_config.c
@@ -0,0 +1,323 @@
+/*
+ * Copyright 2018 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ *    internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ *    1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ *    2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ *        correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ *        explicitly to setup MCGIRCLK.
+ *
+ *    3). Don't need to configure FLL explicitly, because if target mode is FLL
+ *        mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ *        if the target mode is not FLL mode, the FLL is disabled.
+ *
+ *    4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ *        setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ *        be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v4.1
+processor: MK64FN1M0xxx12
+package_id: MK64FN1M0VLL12
+mcu_data: ksdk2_0
+processor_version: 4.0.0
+board: FRDM-K64F
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+#include "fsl_smc.h"
+#include "clock_config.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define MCG_IRCLK_DISABLE 0U                   /*!< MCGIRCLK disabled */
+#define MCG_PLL_DISABLE 0U                     /*!< MCGPLLCLK disabled */
+#define OSC_CAP0P 0U                           /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE 0U                  /*!< Disable external reference clock */
+#define SIM_CLKOUT_SEL_FLEXBUS_CLK 0U          /*!< CLKOUT pin clock select: FlexBus clock */
+#define SIM_ENET_1588T_CLK_SEL_OSCERCLK_CLK 2U /*!< SDHC clock select: OSCERCLK clock */
+#define SIM_ENET_RMII_CLK_SEL_EXTAL_CLK 0U     /*!< SDHC clock select: Core/system clock */
+#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U         /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+#define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U         /*!< PLLFLL select: IRC48MCLK clock */
+#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U         /*!< PLLFLL select: MCGPLLCLK clock */
+#define SIM_SDHC_CLK_SEL_OSCERCLK_CLK 2U       /*!< SDHC clock select: OSCERCLK clock */
+#define SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK 1U   /*!< Trace clock select: Core/system clock */
+#define SIM_USB_CLK_120000000HZ 120000000U     /*!< Input SIM frequency for USB: 120000000Hz */
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
+ * Description   : Configure FLL external reference divider (FRDIV).
+ * Param frdiv   : The value to set FRDIV.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
+{
+    MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
+}
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 60 MHz}
+- {id: CLKOUT.outFreq, value: 40 MHz}
+- {id: Core_clock.outFreq, value: 120 MHz, locked: true, accuracy: '0.001'}
+- {id: ENET1588TSCLK.outFreq, value: 50 MHz}
+- {id: Flash_clock.outFreq, value: 24 MHz}
+- {id: FlexBus_clock.outFreq, value: 40 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGFFCLK.outFreq, value: 1.5625 MHz}
+- {id: MCGIRCLK.outFreq, value: 2 MHz}
+- {id: OSCERCLK.outFreq, value: 50 MHz}
+- {id: PLLFLLCLK.outFreq, value: 120 MHz}
+- {id: RMIICLK.outFreq, value: 50 MHz}
+- {id: SDHCCLK.outFreq, value: 50 MHz}
+- {id: System_clock.outFreq, value: 120 MHz}
+- {id: TRACECLKIN.outFreq, value: 120 MHz}
+- {id: USB48MCLK.outFreq, value: 48 MHz}
+settings:
+- {id: MCGMode, value: PEE}
+- {id: CLKOUTConfig, value: 'yes'}
+- {id: ENETTimeSrcConfig, value: 'yes'}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG.IREFS.sel, value: MCG.FRDIV}
+- {id: MCG.PLLS.sel, value: MCG.PLL}
+- {id: MCG.PRDIV.scale, value: '15'}
+- {id: MCG.VDIV.scale, value: '36'}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+- {id: RMIISrcConfig, value: 'yes'}
+- {id: RTCCLKOUTConfig, value: 'yes'}
+- {id: RTC_CR_OSCE_CFG, value: Enabled}
+- {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
+- {id: SDHCClkConfig, value: 'yes'}
+- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
+- {id: SIM.OUTDIV2.scale, value: '2'}
+- {id: SIM.OUTDIV3.scale, value: '3'}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
+- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
+- {id: SIM.SDHCSRCSEL.sel, value: OSC.OSCERCLK}
+- {id: SIM.TIMESRCSEL.sel, value: OSC.OSCERCLK}
+- {id: SIM.USBDIV.scale, value: '5'}
+- {id: SIM.USBFRAC.scale, value: '2'}
+- {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
+- {id: TraceClkConfig, value: 'yes'}
+- {id: USBClkConfig, value: 'yes'}
+sources:
+- {id: OSC.OSC.outFreq, value: 50 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
+    .mcgMode         = kMCG_ModePEE,      /* PEE - PLL Engaged External */
+    .irclkEnableMode = kMCG_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCG_IrcFast,      /* Fast internal reference clock selected */
+    .fcrdiv          = 0x1U,              /* Fast IRC divider: divided by 2 */
+    .frdiv           = 0x0U,              /* FLL reference clock divider: divided by 32 */
+    .drs             = kMCG_DrsLow,       /* Low frequency range */
+    .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+    .oscsel          = kMCG_OscselOsc,    /* Selects System Oscillator (OSCCLK) */
+    .pll0Config =
+        {
+            .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
+            .prdiv      = 0xeU,            /* PLL Reference divider: divided by 15 */
+            .vdiv       = 0xcU,            /* VCO divider: multiplied by 36 */
+        },
+};
+const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
+    .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
+    .er32kSrc  = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+    .clkdiv1   = 0x1240000U,                  /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /5 */
+};
+const osc_config_t oscConfig_BOARD_BootClockRUN = {
+    .freq        = 50000000U,    /* Oscillator frequency: 50000000Hz */
+    .capLoad     = (OSC_CAP0P),  /* Oscillator capacity load: 0pF */
+    .workMode    = kOSC_ModeExt, /* Use external clock */
+    .oscerConfig = {
+        .enableMode =
+            kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
+    }};
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
+                                  mcgConfig_BOARD_BootClockRUN.fcrdiv);
+    /* Configure FLL external reference divider (FRDIV). */
+    CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
+    /* Set MCG to PEE mode. */
+    CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, kMCG_PllClkSelPll0,
+                        &mcgConfig_BOARD_BootClockRUN.pll0Config);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+    /* Enable USB FS clock. */
+    CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, SIM_USB_CLK_120000000HZ);
+    /* Set enet timestamp clock source. */
+    CLOCK_SetEnetTime0Clock(SIM_ENET_1588T_CLK_SEL_OSCERCLK_CLK);
+    /* Set RMII clock source. */
+    CLOCK_SetRmii0Clock(SIM_ENET_RMII_CLK_SEL_EXTAL_CLK);
+    /* Set SDHC clock source. */
+    CLOCK_SetSdhc0Clock(SIM_SDHC_CLK_SEL_OSCERCLK_CLK);
+    /* Set CLKOUT source. */
+    CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_FLEXBUS_CLK);
+    /* Set debug trace clock source. */
+    CLOCK_SetTraceClock(SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK);
+}
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 4 MHz}
+- {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
+- {id: Flash_clock.outFreq, value: 800 kHz}
+- {id: FlexBus_clock.outFreq, value: 4 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: System_clock.outFreq, value: 4 MHz}
+settings:
+- {id: MCGMode, value: BLPI}
+- {id: powerMode, value: VLPR}
+- {id: MCG.CLKS.sel, value: MCG.IRCS}
+- {id: MCG.FCRDIV.scale, value: '1'}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: RTC_CR_OSCE_CFG, value: Enabled}
+- {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
+- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
+- {id: SIM.OUTDIV3.scale, value: '1'}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+- {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
+- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
+sources:
+- {id: OSC.OSC.outFreq, value: 50 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
+    .mcgMode         = kMCG_ModeBLPI,     /* BLPI - Bypassed Low Power Internal */
+    .irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */
+    .ircs            = kMCG_IrcFast,      /* Fast internal reference clock selected */
+    .fcrdiv          = 0x0U,              /* Fast IRC divider: divided by 1 */
+    .frdiv           = 0x0U,              /* FLL reference clock divider: divided by 32 */
+    .drs             = kMCG_DrsLow,       /* Low frequency range */
+    .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+    .oscsel          = kMCG_OscselOsc,    /* Selects System Oscillator (OSCCLK) */
+    .pll0Config =
+        {
+            .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
+            .prdiv      = 0x0U,            /* PLL Reference divider: divided by 1 */
+            .vdiv       = 0x0U,            /* VCO divider: multiplied by 24 */
+        },
+};
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
+    .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
+    .er32kSrc  = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+    .clkdiv1   = 0x40000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
+};
+const osc_config_t oscConfig_BOARD_BootClockVLPR = {
+    .freq        = 0U,           /* Oscillator frequency: 0Hz */
+    .capLoad     = (OSC_CAP0P),  /* Oscillator capacity load: 0pF */
+    .workMode    = kOSC_ModeExt, /* Use external clock */
+    .oscerConfig = {
+        .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+    }};
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to BLPI mode. */
+    CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
+                         mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    SMC_SetPowerModeVlpr(SMC, false);
+#else
+    SMC_SetPowerModeVlpr(SMC);
+#endif
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+}

diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk64f/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk64f/project_template/clock_config.c new file mode 100644 index 000000000..1504635c3 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk64f/project_template/clock_config.c
@@ -0,0 +1,323 @@
	1	/*
	2	* Copyright 2018 NXP.
	3	* All rights reserved.
	4	*
	5	* SPDX-License-Identifier: BSD-3-Clause
	6	*/
	7
	8	/***********************************************************************************************************************
	9	* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
	10	* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
	11	**********************************************************************************************************************/
	12	/*
	13	* How to setup clock using clock driver functions:
	14	*
	15	* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
	16	* and flash clock are in allowed range during clock mode switch.
	17	*
	18	* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
	19	*
	20	* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
	21	* internal reference clock(MCGIRCLK). Follow the steps to setup:
	22	*
	23	* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
	24	*
	25	* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
	26	* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
	27	* explicitly to setup MCGIRCLK.
	28	*
	29	* 3). Don't need to configure FLL explicitly, because if target mode is FLL
	30	* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
	31	* if the target mode is not FLL mode, the FLL is disabled.
	32	*
	33	* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
	34	* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
	35	* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
	36	*
	37	* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
	38	*/
	39
	40	/* clang-format off */
	41	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	42	!!GlobalInfo
	43	product: Clocks v4.1
	44	processor: MK64FN1M0xxx12
	45	package_id: MK64FN1M0VLL12
	46	mcu_data: ksdk2_0
	47	processor_version: 4.0.0
	48	board: FRDM-K64F
	49	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	50	/* clang-format on */
	51
	52	#include "fsl_smc.h"
	53	#include "clock_config.h"
	54
	55	/*******************************************************************************
	56	* Definitions
	57	******************************************************************************/
	58	#define MCG_IRCLK_DISABLE 0U /!< MCGIRCLK disabled /
	59	#define MCG_PLL_DISABLE 0U /!< MCGPLLCLK disabled /
	60	#define OSC_CAP0P 0U /!< Oscillator 0pF capacitor load /
	61	#define OSC_ER_CLK_DISABLE 0U /!< Disable external reference clock /
	62	#define SIM_CLKOUT_SEL_FLEXBUS_CLK 0U /!< CLKOUT pin clock select: FlexBus clock /
	63	#define SIM_ENET_1588T_CLK_SEL_OSCERCLK_CLK 2U /!< SDHC clock select: OSCERCLK clock /
	64	#define SIM_ENET_RMII_CLK_SEL_EXTAL_CLK 0U /!< SDHC clock select: Core/system clock /
	65	#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) /
	66	#define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /!< PLLFLL select: IRC48MCLK clock /
	67	#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /!< PLLFLL select: MCGPLLCLK clock /
	68	#define SIM_SDHC_CLK_SEL_OSCERCLK_CLK 2U /!< SDHC clock select: OSCERCLK clock /
	69	#define SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK 1U /!< Trace clock select: Core/system clock /
	70	#define SIM_USB_CLK_120000000HZ 120000000U /!< Input SIM frequency for USB: 120000000Hz /
	71
	72	/*******************************************************************************
	73	* Variables
	74	******************************************************************************/
	75	/* System clock frequency. */
	76	extern uint32_t SystemCoreClock;
	77
	78	/*******************************************************************************
	79	* Code
	80	******************************************************************************/
	81	/FUNCTION*********************************************************************
	82	*
	83	* Function Name : CLOCK_CONFIG_SetFllExtRefDiv
	84	* Description : Configure FLL external reference divider (FRDIV).
	85	* Param frdiv : The value to set FRDIV.
	86	*
	87	END*************************************************************************/
	88	static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
	89	{
	90	MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) \| MCG_C1_FRDIV(frdiv));
	91	}
	92
	93	/*******************************************************************************
	94	********************** BOARD_InitBootClocks function **********************
	95	******************************************************************************/
	96	void BOARD_InitBootClocks(void)
	97	{
	98	BOARD_BootClockRUN();
	99	}
	100
	101	/*******************************************************************************
	102	******************** Configuration BOARD_BootClockRUN *********************
	103	******************************************************************************/
	104	/* clang-format off */
	105	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	106	!!Configuration
	107	name: BOARD_BootClockRUN
	108	called_from_default_init: true
	109	outputs:
	110	- {id: Bus_clock.outFreq, value: 60 MHz}
	111	- {id: CLKOUT.outFreq, value: 40 MHz}
	112	- {id: Core_clock.outFreq, value: 120 MHz, locked: true, accuracy: '0.001'}
	113	- {id: ENET1588TSCLK.outFreq, value: 50 MHz}
	114	- {id: Flash_clock.outFreq, value: 24 MHz}
	115	- {id: FlexBus_clock.outFreq, value: 40 MHz}
	116	- {id: LPO_clock.outFreq, value: 1 kHz}
	117	- {id: MCGFFCLK.outFreq, value: 1.5625 MHz}
	118	- {id: MCGIRCLK.outFreq, value: 2 MHz}
	119	- {id: OSCERCLK.outFreq, value: 50 MHz}
	120	- {id: PLLFLLCLK.outFreq, value: 120 MHz}
	121	- {id: RMIICLK.outFreq, value: 50 MHz}
	122	- {id: SDHCCLK.outFreq, value: 50 MHz}
	123	- {id: System_clock.outFreq, value: 120 MHz}
	124	- {id: TRACECLKIN.outFreq, value: 120 MHz}
	125	- {id: USB48MCLK.outFreq, value: 48 MHz}
	126	settings:
	127	- {id: MCGMode, value: PEE}
	128	- {id: CLKOUTConfig, value: 'yes'}
	129	- {id: ENETTimeSrcConfig, value: 'yes'}
	130	- {id: MCG.FRDIV.scale, value: '32'}
	131	- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
	132	- {id: MCG.IREFS.sel, value: MCG.FRDIV}
	133	- {id: MCG.PLLS.sel, value: MCG.PLL}
	134	- {id: MCG.PRDIV.scale, value: '15'}
	135	- {id: MCG.VDIV.scale, value: '36'}
	136	- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
	137	- {id: MCG_C2_RANGE0_CFG, value: Very_high}
	138	- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
	139	- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
	140	- {id: RMIISrcConfig, value: 'yes'}
	141	- {id: RTCCLKOUTConfig, value: 'yes'}
	142	- {id: RTC_CR_OSCE_CFG, value: Enabled}
	143	- {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
	144	- {id: SDHCClkConfig, value: 'yes'}
	145	- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
	146	- {id: SIM.OUTDIV2.scale, value: '2'}
	147	- {id: SIM.OUTDIV3.scale, value: '3'}
	148	- {id: SIM.OUTDIV4.scale, value: '5'}
	149	- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
	150	- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
	151	- {id: SIM.SDHCSRCSEL.sel, value: OSC.OSCERCLK}
	152	- {id: SIM.TIMESRCSEL.sel, value: OSC.OSCERCLK}
	153	- {id: SIM.USBDIV.scale, value: '5'}
	154	- {id: SIM.USBFRAC.scale, value: '2'}
	155	- {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
	156	- {id: TraceClkConfig, value: 'yes'}
	157	- {id: USBClkConfig, value: 'yes'}
	158	sources:
	159	- {id: OSC.OSC.outFreq, value: 50 MHz, enabled: true}
	160	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	161	/* clang-format on */
	162
	163	/*******************************************************************************
	164	* Variables for BOARD_BootClockRUN configuration
	165	******************************************************************************/
	166	const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
	167	.mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
	168	.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	169	.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
	170	.fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */
	171	.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
	172	.drs = kMCG_DrsLow, /* Low frequency range */
	173	.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
	174	.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
	175	.pll0Config =
	176	{
	177	.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
	178	.prdiv = 0xeU, /* PLL Reference divider: divided by 15 */
	179	.vdiv = 0xcU, /* VCO divider: multiplied by 36 */
	180	},
	181	};
	182	const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
	183	.pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
	184	.er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
	185	.clkdiv1 = 0x1240000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /5 */
	186	};
	187	const osc_config_t oscConfig_BOARD_BootClockRUN = {
	188	.freq = 50000000U, /* Oscillator frequency: 50000000Hz */
	189	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	190	.workMode = kOSC_ModeExt, /* Use external clock */
	191	.oscerConfig = {
	192	.enableMode =
	193	kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
	194	}};
	195
	196	/*******************************************************************************
	197	* Code for BOARD_BootClockRUN configuration
	198	******************************************************************************/
	199	void BOARD_BootClockRUN(void)
	200	{
	201	/* Set the system clock dividers in SIM to safe value. */
	202	CLOCK_SetSimSafeDivs();
	203	/* Initializes OSC0 according to board configuration. */
	204	CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
	205	CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
	206	/* Configure the Internal Reference clock (MCGIRCLK). */
	207	CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
	208	mcgConfig_BOARD_BootClockRUN.fcrdiv);
	209	/* Configure FLL external reference divider (FRDIV). */
	210	CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
	211	/* Set MCG to PEE mode. */
	212	CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, kMCG_PllClkSelPll0,
	213	&mcgConfig_BOARD_BootClockRUN.pll0Config);
	214	/* Set the clock configuration in SIM module. */
	215	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
	216	/* Set SystemCoreClock variable. */
	217	SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
	218	/* Enable USB FS clock. */
	219	CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, SIM_USB_CLK_120000000HZ);
	220	/* Set enet timestamp clock source. */
	221	CLOCK_SetEnetTime0Clock(SIM_ENET_1588T_CLK_SEL_OSCERCLK_CLK);
	222	/* Set RMII clock source. */
	223	CLOCK_SetRmii0Clock(SIM_ENET_RMII_CLK_SEL_EXTAL_CLK);
	224	/* Set SDHC clock source. */
	225	CLOCK_SetSdhc0Clock(SIM_SDHC_CLK_SEL_OSCERCLK_CLK);
	226	/* Set CLKOUT source. */
	227	CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_FLEXBUS_CLK);
	228	/* Set debug trace clock source. */
	229	CLOCK_SetTraceClock(SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK);
	230	}
	231
	232	/*******************************************************************************
	233	******************* Configuration BOARD_BootClockVLPR *********************
	234	******************************************************************************/
	235	/* clang-format off */
	236	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	237	!!Configuration
	238	name: BOARD_BootClockVLPR
	239	outputs:
	240	- {id: Bus_clock.outFreq, value: 4 MHz}
	241	- {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
	242	- {id: Flash_clock.outFreq, value: 800 kHz}
	243	- {id: FlexBus_clock.outFreq, value: 4 MHz}
	244	- {id: LPO_clock.outFreq, value: 1 kHz}
	245	- {id: System_clock.outFreq, value: 4 MHz}
	246	settings:
	247	- {id: MCGMode, value: BLPI}
	248	- {id: powerMode, value: VLPR}
	249	- {id: MCG.CLKS.sel, value: MCG.IRCS}
	250	- {id: MCG.FCRDIV.scale, value: '1'}
	251	- {id: MCG.FRDIV.scale, value: '32'}
	252	- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
	253	- {id: MCG_C2_RANGE0_CFG, value: Very_high}
	254	- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
	255	- {id: RTC_CR_OSCE_CFG, value: Enabled}
	256	- {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
	257	- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
	258	- {id: SIM.OUTDIV3.scale, value: '1'}
	259	- {id: SIM.OUTDIV4.scale, value: '5'}
	260	- {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
	261	- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
	262	sources:
	263	- {id: OSC.OSC.outFreq, value: 50 MHz}
	264	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	265	/* clang-format on */
	266
	267	/*******************************************************************************
	268	* Variables for BOARD_BootClockVLPR configuration
	269	******************************************************************************/
	270	const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
	271	.mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
	272	.irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */
	273	.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
	274	.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
	275	.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
	276	.drs = kMCG_DrsLow, /* Low frequency range */
	277	.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
	278	.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
	279	.pll0Config =
	280	{
	281	.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
	282	.prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
	283	.vdiv = 0x0U, /* VCO divider: multiplied by 24 */
	284	},
	285	};
	286	const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
	287	.pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
	288	.er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
	289	.clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
	290	};
	291	const osc_config_t oscConfig_BOARD_BootClockVLPR = {
	292	.freq = 0U, /* Oscillator frequency: 0Hz */
	293	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	294	.workMode = kOSC_ModeExt, /* Use external clock */
	295	.oscerConfig = {
	296	.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
	297	}};
	298
	299	/*******************************************************************************
	300	* Code for BOARD_BootClockVLPR configuration
	301	******************************************************************************/
	302	void BOARD_BootClockVLPR(void)
	303	{
	304	/* Set the system clock dividers in SIM to safe value. */
	305	CLOCK_SetSimSafeDivs();
	306	/* Set MCG to BLPI mode. */
	307	CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
	308	mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
	309	/* Set the clock configuration in SIM module. */
	310	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
	311	/* Set VLPR power mode. */
	312	SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
	313	#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
	314	SMC_SetPowerModeVlpr(SMC, false);
	315	#else
	316	SMC_SetPowerModeVlpr(SMC);
	317	#endif
	318	while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
	319	{
	320	}
	321	/* Set SystemCoreClock variable. */
	322	SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
	323	}