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diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmke15z/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmke15z/project_template/clock_config.c
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1/*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12/*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
16 * Note: The clock could not be set when it is being used as system clock.
17 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
18 * so before setting FIRC, change to use another avaliable clock source.
19 *
20 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
21 *
22 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
23 * Wait until the system clock source is changed to target source.
24 *
25 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
26 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
27 * Supported run mode and clock restrictions could be found in Reference Manual.
28 */
29
30/* clang-format off */
31/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
32!!GlobalInfo
33product: Clocks v4.1
34processor: MKE15Z256xxx7
35package_id: MKE15Z256VLL7
36mcu_data: ksdk2_0
37processor_version: 4.0.0
38board: FRDM-KE15Z
39 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
40/* clang-format on */
41
42#include "fsl_smc.h"
43#include "clock_config.h"
44
45/*******************************************************************************
46 * Definitions
47 ******************************************************************************/
48
49/*******************************************************************************
50 * Variables
51 ******************************************************************************/
52/* System clock frequency. */
53extern uint32_t SystemCoreClock;
54
55/*******************************************************************************
56 * Code
57 ******************************************************************************/
58/*FUNCTION**********************************************************************
59 *
60 * Function Name : CLOCK_CONFIG_FircSafeConfig
61 * Description : This function is used to safely configure FIRC clock.
62 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
63 * Before setting FIRC, change to use SIRC as system clock,
64 * then configure FIRC. After FIRC is set, change back to use FIRC
65 * in case SIRC need to be configured.
66 * Param fircConfig : FIRC configuration.
67 *
68 *END**************************************************************************/
69static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
70{
71 scg_sys_clk_config_t curConfig;
72 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
73 .div2 = kSCG_AsyncClkDivBy2,
74 .range = kSCG_SircRangeHigh};
75 scg_sys_clk_config_t sysClkSafeConfigSource = {
76 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
77 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
78 .src = kSCG_SysClkSrcSirc /* System clock source */
79 };
80 /* Init Sirc. */
81 CLOCK_InitSirc(&scgSircConfig);
82 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
83 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
84 /* Wait for clock source switch finished. */
85 do
86 {
87 CLOCK_GetCurSysClkConfig(&curConfig);
88 } while (curConfig.src != sysClkSafeConfigSource.src);
89
90 /* Init Firc. */
91 CLOCK_InitFirc(fircConfig);
92 /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
93 sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
94 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
95 /* Wait for clock source switch finished. */
96 do
97 {
98 CLOCK_GetCurSysClkConfig(&curConfig);
99 } while (curConfig.src != sysClkSafeConfigSource.src);
100}
101
102/*******************************************************************************
103 ************************ BOARD_InitBootClocks function ************************
104 ******************************************************************************/
105void BOARD_InitBootClocks(void)
106{
107 BOARD_BootClockRUN();
108}
109
110/*******************************************************************************
111 ********************** Configuration BOARD_BootClockRUN ***********************
112 ******************************************************************************/
113/* clang-format off */
114/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
115!!Configuration
116name: BOARD_BootClockRUN
117called_from_default_init: true
118outputs:
119- {id: Bus_clock.outFreq, value: 24 MHz}
120- {id: Core_clock.outFreq, value: 72 MHz}
121- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
122- {id: FLLDIV2_CLK.outFreq, value: 36 MHz}
123- {id: Flash_clock.outFreq, value: 24 MHz}
124- {id: LPO1KCLK.outFreq, value: 1 kHz}
125- {id: LPO_clock.outFreq, value: 128 kHz}
126- {id: PCC.PCC_ADC1_CLK.outFreq, value: 8 MHz}
127- {id: PCC.PCC_LPI2C0_CLK.outFreq, value: 8 MHz}
128- {id: PCC.PCC_LPUART1_CLK.outFreq, value: 8 MHz}
129- {id: SIRCDIV2_CLK.outFreq, value: 4 MHz}
130- {id: SIRC_CLK.outFreq, value: 8 MHz}
131- {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
132- {id: SOSC_CLK.outFreq, value: 8 MHz}
133- {id: System_clock.outFreq, value: 72 MHz}
134settings:
135- {id: SCGMode, value: LPFLL}
136- {id: OSC32_CR_ROSCE_CFG, value: Enabled}
137- {id: PCC.PCC_ADC1_SEL.sel, value: SCG.SOSCDIV2_CLK}
138- {id: PCC.PCC_LPI2C0_SEL.sel, value: SCG.SOSCDIV2_CLK}
139- {id: PCC.PCC_LPUART1_SEL.sel, value: SCG.SOSCDIV2_CLK}
140- {id: SCG.DIVCORE.scale, value: '1', locked: true}
141- {id: SCG.DIVSLOW.scale, value: '3', locked: true}
142- {id: SCG.FIRCDIV2.scale, value: '1'}
143- {id: SCG.LPFLLDIV2.scale, value: '2'}
144- {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
145- {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
146- {id: SCG.SIRCDIV2.scale, value: '2'}
147- {id: SCG.SOSCDIV2.scale, value: '1'}
148- {id: SCG.TRIMDIV.scale, value: '4'}
149- {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
150- {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
151- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
152- {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
153- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
154- {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
155sources:
156- {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
157 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
158/* clang-format on */
159
160/*******************************************************************************
161 * Variables for BOARD_BootClockRUN configuration
162 ******************************************************************************/
163const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN = {
164 .divSlow = kSCG_SysClkDivBy3, /* Slow Clock Divider: divided by 3 */
165 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
166 .src = kSCG_SysClkSrcLpFll, /* Low power FLL is selected as System Clock Source */
167};
168const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN = {
169 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
170 .enableMode = kSCG_SysOscEnable |
171 kSCG_SysOscEnableInLowPower, /* Enable System OSC clock, Enable System OSC in low power mode */
172 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
173 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
174 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
175};
176const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN = {
177 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
178 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
179 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
180};
181const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN = {
182 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
183 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
184 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
185 .trimConfig = NULL, /* Fast IRC Trim disabled */
186};
187const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN = {
188 .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
189 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
190 .range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
191 .trimConfig = NULL,
192};
193/*******************************************************************************
194 * Code for BOARD_BootClockRUN configuration
195 ******************************************************************************/
196void BOARD_BootClockRUN(void)
197{
198 scg_sys_clk_config_t curConfig;
199
200 /* Init SOSC according to board configuration. */
201 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
202 /* Set the XTAL0 frequency based on board settings. */
203 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
204 /* Init FIRC. */
205 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
206 /* Init SIRC. */
207 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
208 /* Init LPFLL. */
209 CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
210 /* Set SCG to LPFLL mode. */
211 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
212 /* Wait for clock source switch finished. */
213 do
214 {
215 CLOCK_GetCurSysClkConfig(&curConfig);
216 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
217 /* Set SystemCoreClock variable. */
218 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
219 /* Set PCC ADC1 selection */
220 CLOCK_SetIpSrc(kCLOCK_Adc1, kCLOCK_IpSrcSysOscAsync);
221 /* Set PCC LPI2C0 selection */
222 CLOCK_SetIpSrc(kCLOCK_Lpi2c0, kCLOCK_IpSrcSysOscAsync);
223 /* Set PCC LPUART1 selection */
224 CLOCK_SetIpSrc(kCLOCK_Lpuart1, kCLOCK_IpSrcSysOscAsync);
225}
226
227/*******************************************************************************
228 ********************* Configuration BOARD_BootClockVLPR ***********************
229 ******************************************************************************/
230/* clang-format off */
231/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
232!!Configuration
233name: BOARD_BootClockVLPR
234outputs:
235- {id: Bus_clock.outFreq, value: 1 MHz}
236- {id: Core_clock.outFreq, value: 4 MHz}
237- {id: Flash_clock.outFreq, value: 1 MHz}
238- {id: LPO1KCLK.outFreq, value: 1 kHz}
239- {id: LPO_clock.outFreq, value: 128 kHz}
240- {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
241- {id: SOSC_CLK.outFreq, value: 8 MHz}
242- {id: System_clock.outFreq, value: 4 MHz}
243settings:
244- {id: SCGMode, value: SOSC}
245- {id: powerMode, value: VLPR}
246- {id: OSC32_CR_ROSCE_CFG, value: Enabled}
247- {id: SCG.DIVCORE.scale, value: '2', locked: true}
248- {id: SCG.DIVSLOW.scale, value: '4', locked: true}
249- {id: SCG.FIRCDIV2.scale, value: '1'}
250- {id: SCG.LPFLLDIV2.scale, value: '2'}
251- {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
252- {id: SCG.SCSSEL.sel, value: SCG.SOSC}
253- {id: SCG.SIRCDIV2.scale, value: '2'}
254- {id: SCG.SOSCDIV2.scale, value: '1'}
255- {id: SCG.TRIMDIV.scale, value: '4'}
256- {id: 'SCG::FIRCCFG[RANGE].bitField', value: BitFieldValue}
257- {id: 'SCG::RCCR[DIVCORE].bitField', value: BitFieldValue}
258- {id: 'SCG::RCCR[DIVSLOW].bitField', value: BitFieldValue}
259- {id: 'SCG::RCCR[SCS].bitField', value: BitFieldValue}
260- {id: 'SCG::SIRCCFG[RANGE].bitField', value: BitFieldValue}
261- {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
262- {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
263- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
264- {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
265- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
266- {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
267sources:
268- {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
269 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
270/* clang-format on */
271
272/*******************************************************************************
273 * Variables for BOARD_BootClockVLPR configuration
274 ******************************************************************************/
275const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR = {
276 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
277 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
278 .src = kSCG_SysClkSrcSysOsc, /* System OSC is selected as System Clock Source */
279};
280const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR = {
281 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
282 .enableMode = kSCG_SysOscEnable |
283 kSCG_SysOscEnableInLowPower, /* Enable System OSC clock, Enable System OSC in low power mode */
284 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
285 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
286 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
287};
288const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR = {
289 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
290 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
291 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
292};
293const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR = {
294 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
295 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
296 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
297 .trimConfig = NULL, /* Fast IRC Trim disabled */
298};
299const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR = {
300 .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
301 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
302 .range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
303 .trimConfig = NULL,
304};
305/*******************************************************************************
306 * Code for BOARD_BootClockVLPR configuration
307 ******************************************************************************/
308void BOARD_BootClockVLPR(void)
309{
310 /* Init SOSC according to board configuration. */
311 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockVLPR);
312 /* Set the XTAL0 frequency based on board settings. */
313 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockVLPR.freq);
314 /* Set SCG to SOSC mode. */
315 CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
316 /* Allow SMC all power modes. */
317 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
318 /* Set VLPR power mode. */
319 SMC_SetPowerModeVlpr(SMC);
320 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
321 {
322 }
323 /* Set SystemCoreClock variable. */
324 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
325}
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:57:11 +0100