1 files changed, 248 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmkv11z/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmkv11z/clock_config.c
new file mode 100644
index 000000000..1b3a7d96a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmkv11z/clock_config.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ *    internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ *    1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ *    2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ *        correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ *        explicitly to setup MCGIRCLK.
+ *
+ *    3). Don't need to configure FLL explicitly, because if target mode is FLL
+ *        mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ *        if the target mode is not FLL mode, the FLL is disabled.
+ *
+ *    4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ *        setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ *        be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v3.0
+processor: MKV11Z128xxx7
+package_id: MKV11Z128VLH7
+mcu_data: ksdk2_0
+processor_version: 0.0.5
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+#include "fsl_smc.h"
+#include "clock_config.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define OSC_CAP0P 0U             /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE 0U    /*!< Disable external reference clock */
+#define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_FllStableDelay
+ * Description   : This function is used to delay for FLL stable.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_FllStableDelay(void)
+{
+    uint32_t i = 30000U;
+    while (i--)
+    {
+        __NOP();
+    }
+}
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 25 MHz}
+- {id: Core_clock.outFreq, value: 75 MHz}
+- {id: ERCLK32K.outFreq, value: 1 kHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGFLLCLK.outFreq, value: 75 MHz}
+- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
+- {id: OSCERCLK.outFreq, value: 10 MHz}
+- {id: System_clock.outFreq, value: 75 MHz}
+settings:
+- {id: MCGMode, value: FEE}
+- {id: MCG.FCRDIV.scale, value: '1'}
+- {id: MCG.FLL_mul.scale, value: '1920'}
+- {id: MCG.FRDIV.scale, value: '256'}
+- {id: MCG.IREFS.sel, value: MCG.FRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
+- {id: SIM.OUTDIV4.scale, value: '3'}
+- {id: SIM.OUTDIV5.scale, value: '1'}
+sources:
+- {id: OSC.OSC.outFreq, value: 10 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
+    .mcgMode         = kMCG_ModeFEE,      /* FEE - FLL Engaged External */
+    .irclkEnableMode = kMCG_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCG_IrcSlow,      /* Slow internal reference clock selected */
+    .fcrdiv          = 0x0U,              /* Fast IRC divider: divided by 1 */
+    .frdiv           = 0x3U,              /* FLL reference clock divider: divided by 256 */
+    .drs             = kMCG_DrsMidHigh,   /* Mid-High frequency range */
+    .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+};
+const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
+    .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
+    .clkdiv1  = 0x20000U,              /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /3, OUTDIV5: /1, disabled */
+};
+const osc_config_t oscConfig_BOARD_BootClockRUN = {
+    .freq        = 10000000U,            /* Oscillator frequency: 10000000Hz */
+    .capLoad     = (OSC_CAP0P),          /* Oscillator capacity load: 0pF */
+    .workMode    = kOSC_ModeOscLowPower, /* Oscillator low power */
+    .oscerConfig = {
+        .enableMode =
+            kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
+    }};
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
+    /* Set MCG to FEE mode. */
+    CLOCK_BootToFeeMode(kMCG_OscselOsc, mcgConfig_BOARD_BootClockRUN.frdiv, mcgConfig_BOARD_BootClockRUN.dmx32,
+                        mcgConfig_BOARD_BootClockRUN.drs, CLOCK_CONFIG_FllStableDelay);
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
+                                  mcgConfig_BOARD_BootClockRUN.fcrdiv);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 800 kHz}
+- {id: Core_clock.outFreq, value: 4 MHz}
+- {id: ERCLK32K.outFreq, value: 1 kHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 4 MHz}
+- {id: System_clock.outFreq, value: 4 MHz}
+settings:
+- {id: MCGMode, value: BLPI}
+- {id: powerMode, value: VLPR}
+- {id: MCG.CLKS.sel, value: MCG.IRCS}
+- {id: MCG.FCRDIV.scale, value: '1'}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+- {id: SIM.OUTDIV5.scale, value: '1'}
+sources:
+- {id: OSC.OSC.outFreq, value: 10 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
+    .mcgMode         = kMCG_ModeBLPI,     /* BLPI - Bypassed Low Power Internal */
+    .irclkEnableMode = kMCG_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCG_IrcFast,      /* Fast internal reference clock selected */
+    .fcrdiv          = 0x0U,              /* Fast IRC divider: divided by 1 */
+    .frdiv           = 0x0U,              /* FLL reference clock divider: divided by 32 */
+    .drs             = kMCG_DrsLow,       /* Low frequency range */
+    .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+};
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
+    .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
+    .clkdiv1  = 0x40000U,              /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /5, OUTDIV5: /1, disabled */
+};
+const osc_config_t oscConfig_BOARD_BootClockVLPR = {
+    .freq        = 0U,                   /* Oscillator frequency: 0Hz */
+    .capLoad     = (OSC_CAP0P),          /* Oscillator capacity load: 0pF */
+    .workMode    = kOSC_ModeOscLowPower, /* Oscillator low power */
+    .oscerConfig = {
+        .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+    }};
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to BLPI mode. */
+    CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
+                         mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    SMC_SetPowerModeVlpr(SMC, false);
+#else
+    SMC_SetPowerModeVlpr(SMC);
+#endif
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+}

diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmkv11z/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmkv11z/clock_config.c new file mode 100644 index 000000000..1b3a7d96a --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmkv11z/clock_config.c
@@ -0,0 +1,248 @@
	1	/*
	2	* Copyright (c) 2015, Freescale Semiconductor, Inc.
	3	* Copyright 2016-2017 NXP
	4	* All rights reserved.
	5	*
	6	* SPDX-License-Identifier: BSD-3-Clause
	7	*/
	8
	9	/*
	10	* How to setup clock using clock driver functions:
	11	*
	12	* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
	13	* and flash clock are in allowed range during clock mode switch.
	14	*
	15	* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
	16	*
	17	* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
	18	* internal reference clock(MCGIRCLK). Follow the steps to setup:
	19	*
	20	* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
	21	*
	22	* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
	23	* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
	24	* explicitly to setup MCGIRCLK.
	25	*
	26	* 3). Don't need to configure FLL explicitly, because if target mode is FLL
	27	* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
	28	* if the target mode is not FLL mode, the FLL is disabled.
	29	*
	30	* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
	31	* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
	32	* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
	33	*
	34	* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
	35	*/
	36
	37	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	38	!!GlobalInfo
	39	product: Clocks v3.0
	40	processor: MKV11Z128xxx7
	41	package_id: MKV11Z128VLH7
	42	mcu_data: ksdk2_0
	43	processor_version: 0.0.5
	44	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	45
	46	#include "fsl_smc.h"
	47	#include "clock_config.h"
	48
	49	/*******************************************************************************
	50	* Definitions
	51	******************************************************************************/
	52	#define OSC_CAP0P 0U /!< Oscillator 0pF capacitor load /
	53	#define OSC_ER_CLK_DISABLE 0U /!< Disable external reference clock /
	54	#define SIM_OSC32KSEL_LPO_CLK 3U /!< OSC32KSEL select: LPO clock /
	55
	56	/*******************************************************************************
	57	* Variables
	58	******************************************************************************/
	59	/* System clock frequency. */
	60	extern uint32_t SystemCoreClock;
	61
	62	/*******************************************************************************
	63	* Code
	64	******************************************************************************/
	65	/FUNCTION*********************************************************************
	66	*
	67	* Function Name : CLOCK_CONFIG_FllStableDelay
	68	* Description : This function is used to delay for FLL stable.
	69	*
	70	END*************************************************************************/
	71	static void CLOCK_CONFIG_FllStableDelay(void)
	72	{
	73	uint32_t i = 30000U;
	74	while (i--)
	75	{
	76	__NOP();
	77	}
	78	}
	79
	80	/*******************************************************************************
	81	********************** BOARD_InitBootClocks function **********************
	82	******************************************************************************/
	83	void BOARD_InitBootClocks(void)
	84	{
	85	BOARD_BootClockRUN();
	86	}
	87
	88	/*******************************************************************************
	89	******************** Configuration BOARD_BootClockRUN *********************
	90	******************************************************************************/
	91	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	92	!!Configuration
	93	name: BOARD_BootClockRUN
	94	called_from_default_init: true
	95	outputs:
	96	- {id: Bus_clock.outFreq, value: 25 MHz}
	97	- {id: Core_clock.outFreq, value: 75 MHz}
	98	- {id: ERCLK32K.outFreq, value: 1 kHz}
	99	- {id: LPO_clock.outFreq, value: 1 kHz}
	100	- {id: MCGFLLCLK.outFreq, value: 75 MHz}
	101	- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
	102	- {id: OSCERCLK.outFreq, value: 10 MHz}
	103	- {id: System_clock.outFreq, value: 75 MHz}
	104	settings:
	105	- {id: MCGMode, value: FEE}
	106	- {id: MCG.FCRDIV.scale, value: '1'}
	107	- {id: MCG.FLL_mul.scale, value: '1920'}
	108	- {id: MCG.FRDIV.scale, value: '256'}
	109	- {id: MCG.IREFS.sel, value: MCG.FRDIV}
	110	- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
	111	- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
	112	- {id: MCG_C2_RANGE0_CFG, value: Very_high}
	113	- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
	114	- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
	115	- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
	116	- {id: SIM.OUTDIV4.scale, value: '3'}
	117	- {id: SIM.OUTDIV5.scale, value: '1'}
	118	sources:
	119	- {id: OSC.OSC.outFreq, value: 10 MHz, enabled: true}
	120	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	121
	122	/*******************************************************************************
	123	* Variables for BOARD_BootClockRUN configuration
	124	******************************************************************************/
	125	const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
	126	.mcgMode = kMCG_ModeFEE, /* FEE - FLL Engaged External */
	127	.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	128	.ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
	129	.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
	130	.frdiv = 0x3U, /* FLL reference clock divider: divided by 256 */
	131	.drs = kMCG_DrsMidHigh, /* Mid-High frequency range */
	132	.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
	133	};
	134	const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
	135	.er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
	136	.clkdiv1 = 0x20000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /3, OUTDIV5: /1, disabled */
	137	};
	138	const osc_config_t oscConfig_BOARD_BootClockRUN = {
	139	.freq = 10000000U, /* Oscillator frequency: 10000000Hz */
	140	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	141	.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
	142	.oscerConfig = {
	143	.enableMode =
	144	kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
	145	}};
	146
	147	/*******************************************************************************
	148	* Code for BOARD_BootClockRUN configuration
	149	******************************************************************************/
	150	void BOARD_BootClockRUN(void)
	151	{
	152	/* Set the system clock dividers in SIM to safe value. */
	153	CLOCK_SetSimSafeDivs();
	154	/* Initializes OSC0 according to board configuration. */
	155	CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
	156	CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
	157	/* Set MCG to FEE mode. */
	158	CLOCK_BootToFeeMode(kMCG_OscselOsc, mcgConfig_BOARD_BootClockRUN.frdiv, mcgConfig_BOARD_BootClockRUN.dmx32,
	159	mcgConfig_BOARD_BootClockRUN.drs, CLOCK_CONFIG_FllStableDelay);
	160	/* Configure the Internal Reference clock (MCGIRCLK). */
	161	CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
	162	mcgConfig_BOARD_BootClockRUN.fcrdiv);
	163	/* Set the clock configuration in SIM module. */
	164	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
	165	/* Set SystemCoreClock variable. */
	166	SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
	167	}
	168
	169	/*******************************************************************************
	170	******************* Configuration BOARD_BootClockVLPR *********************
	171	******************************************************************************/
	172	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	173	!!Configuration
	174	name: BOARD_BootClockVLPR
	175	outputs:
	176	- {id: Bus_clock.outFreq, value: 800 kHz}
	177	- {id: Core_clock.outFreq, value: 4 MHz}
	178	- {id: ERCLK32K.outFreq, value: 1 kHz}
	179	- {id: LPO_clock.outFreq, value: 1 kHz}
	180	- {id: MCGIRCLK.outFreq, value: 4 MHz}
	181	- {id: System_clock.outFreq, value: 4 MHz}
	182	settings:
	183	- {id: MCGMode, value: BLPI}
	184	- {id: powerMode, value: VLPR}
	185	- {id: MCG.CLKS.sel, value: MCG.IRCS}
	186	- {id: MCG.FCRDIV.scale, value: '1'}
	187	- {id: MCG.FRDIV.scale, value: '32'}
	188	- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
	189	- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
	190	- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
	191	- {id: MCG_C2_RANGE0_CFG, value: Very_high}
	192	- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
	193	- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
	194	- {id: SIM.OUTDIV4.scale, value: '5'}
	195	- {id: SIM.OUTDIV5.scale, value: '1'}
	196	sources:
	197	- {id: OSC.OSC.outFreq, value: 10 MHz}
	198	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	199
	200	/*******************************************************************************
	201	* Variables for BOARD_BootClockVLPR configuration
	202	******************************************************************************/
	203	const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
	204	.mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
	205	.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	206	.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
	207	.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
	208	.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
	209	.drs = kMCG_DrsLow, /* Low frequency range */
	210	.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
	211	};
	212	const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
	213	.er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
	214	.clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /5, OUTDIV5: /1, disabled */
	215	};
	216	const osc_config_t oscConfig_BOARD_BootClockVLPR = {
	217	.freq = 0U, /* Oscillator frequency: 0Hz */
	218	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	219	.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
	220	.oscerConfig = {
	221	.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
	222	}};
	223
	224	/*******************************************************************************
	225	* Code for BOARD_BootClockVLPR configuration
	226	******************************************************************************/
	227	void BOARD_BootClockVLPR(void)
	228	{
	229	/* Set the system clock dividers in SIM to safe value. */
	230	CLOCK_SetSimSafeDivs();
	231	/* Set MCG to BLPI mode. */
	232	CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
	233	mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
	234	/* Set the clock configuration in SIM module. */
	235	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
	236	/* Set VLPR power mode. */
	237	SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
	238	#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
	239	SMC_SetPowerModeVlpr(SMC, false);
	240	#else
	241	SMC_SetPowerModeVlpr(SMC);
	242	#endif
	243	while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
	244	{
	245	}
	246	/* Set SystemCoreClock variable. */
	247	SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
	248	}