1 files changed, 259 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmkv11z/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmkv11z/project_template/clock_config.c
new file mode 100644
index 000000000..04536b54e
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmkv11z/project_template/clock_config.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright 2018 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ *    internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ *    1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ *    2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ *        correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ *        explicitly to setup MCGIRCLK.
+ *
+ *    3). Don't need to configure FLL explicitly, because if target mode is FLL
+ *        mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ *        if the target mode is not FLL mode, the FLL is disabled.
+ *
+ *    4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ *        setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ *        be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v4.1
+processor: MKV11Z128xxx7
+package_id: MKV11Z128VLH7
+mcu_data: ksdk2_0
+processor_version: 4.0.0
+board: FRDM-KV11Z
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+#include "fsl_smc.h"
+#include "clock_config.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define OSC_CAP0P 0U             /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE 0U    /*!< Disable external reference clock */
+#define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_FllStableDelay
+ * Description   : This function is used to delay for FLL stable.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_FllStableDelay(void)
+{
+    uint32_t i = 30000U;
+    while (i--)
+    {
+        __NOP();
+    }
+}
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 25 MHz}
+- {id: Core_clock.outFreq, value: 75 MHz}
+- {id: ERCLK32K.outFreq, value: 1 kHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGFLLCLK.outFreq, value: 75 MHz}
+- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
+- {id: OSCERCLK.outFreq, value: 10 MHz}
+- {id: System_clock.outFreq, value: 75 MHz}
+settings:
+- {id: MCGMode, value: FEE}
+- {id: MCG.FCRDIV.scale, value: '1'}
+- {id: MCG.FLL_mul.scale, value: '1920'}
+- {id: MCG.FRDIV.scale, value: '256'}
+- {id: MCG.IREFS.sel, value: MCG.FRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+- {id: OSC_CR_SYS_OSC_CAP_LOAD_CFG, value: SC18PF}
+- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
+- {id: SIM.OUTDIV4.scale, value: '3'}
+- {id: SIM.OUTDIV5.scale, value: '1'}
+sources:
+- {id: OSC.OSC.outFreq, value: 10 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
+    .mcgMode         = kMCG_ModeFEE,      /* FEE - FLL Engaged External */
+    .irclkEnableMode = kMCG_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCG_IrcSlow,      /* Slow internal reference clock selected */
+    .fcrdiv          = 0x0U,              /* Fast IRC divider: divided by 1 */
+    .frdiv           = 0x3U,              /* FLL reference clock divider: divided by 256 */
+    .drs             = kMCG_DrsMidHigh,   /* Mid-High frequency range */
+    .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+};
+const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
+    .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
+    .clkdiv1  = 0x20000U,              /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /3, OUTDIV5: /1, disabled */
+};
+const osc_config_t oscConfig_BOARD_BootClockRUN = {
+    .freq        = 10000000U,                  /* Oscillator frequency: 10000000Hz */
+    .capLoad     = (kOSC_Cap2P | kOSC_Cap16P), /* Oscillator capacity load: 18pF */
+    .workMode    = kOSC_ModeOscLowPower,       /* Oscillator low power */
+    .oscerConfig = {
+        .enableMode =
+            kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
+    }};
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
+    /* Set MCG to FEE mode. */
+    CLOCK_BootToFeeMode(kMCG_OscselOsc, mcgConfig_BOARD_BootClockRUN.frdiv, mcgConfig_BOARD_BootClockRUN.dmx32,
+                        mcgConfig_BOARD_BootClockRUN.drs, CLOCK_CONFIG_FllStableDelay);
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
+                                  mcgConfig_BOARD_BootClockRUN.fcrdiv);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 800 kHz}
+- {id: Core_clock.outFreq, value: 4 MHz}
+- {id: ERCLK32K.outFreq, value: 1 kHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 4 MHz}
+- {id: System_clock.outFreq, value: 4 MHz}
+settings:
+- {id: MCGMode, value: BLPI}
+- {id: powerMode, value: VLPR}
+- {id: MCG.CLKS.sel, value: MCG.IRCS}
+- {id: MCG.FCRDIV.scale, value: '1'}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+- {id: SIM.OUTDIV5.scale, value: '1'}
+sources:
+- {id: OSC.OSC.outFreq, value: 10 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
+    .mcgMode         = kMCG_ModeBLPI,     /* BLPI - Bypassed Low Power Internal */
+    .irclkEnableMode = kMCG_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCG_IrcFast,      /* Fast internal reference clock selected */
+    .fcrdiv          = 0x0U,              /* Fast IRC divider: divided by 1 */
+    .frdiv           = 0x0U,              /* FLL reference clock divider: divided by 32 */
+    .drs             = kMCG_DrsLow,       /* Low frequency range */
+    .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+};
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
+    .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
+    .clkdiv1  = 0x40000U,              /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /5, OUTDIV5: /1, disabled */
+};
+const osc_config_t oscConfig_BOARD_BootClockVLPR = {
+    .freq        = 0U,                   /* Oscillator frequency: 0Hz */
+    .capLoad     = (OSC_CAP0P),          /* Oscillator capacity load: 0pF */
+    .workMode    = kOSC_ModeOscLowPower, /* Oscillator low power */
+    .oscerConfig = {
+        .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+    }};
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to BLPI mode. */
+    CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
+                         mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    SMC_SetPowerModeVlpr(SMC, false);
+#else
+    SMC_SetPowerModeVlpr(SMC);
+#endif
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+}

diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmkv11z/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmkv11z/project_template/clock_config.c new file mode 100644 index 000000000..04536b54e --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmkv11z/project_template/clock_config.c
@@ -0,0 +1,259 @@
	1	/*
	2	* Copyright 2018 NXP.
	3	* All rights reserved.
	4	*
	5	* SPDX-License-Identifier: BSD-3-Clause
	6	*/
	7
	8	/***********************************************************************************************************************
	9	* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
	10	* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
	11	**********************************************************************************************************************/
	12	/*
	13	* How to setup clock using clock driver functions:
	14	*
	15	* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
	16	* and flash clock are in allowed range during clock mode switch.
	17	*
	18	* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
	19	*
	20	* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
	21	* internal reference clock(MCGIRCLK). Follow the steps to setup:
	22	*
	23	* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
	24	*
	25	* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
	26	* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
	27	* explicitly to setup MCGIRCLK.
	28	*
	29	* 3). Don't need to configure FLL explicitly, because if target mode is FLL
	30	* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
	31	* if the target mode is not FLL mode, the FLL is disabled.
	32	*
	33	* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
	34	* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
	35	* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
	36	*
	37	* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
	38	*/
	39
	40	/* clang-format off */
	41	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	42	!!GlobalInfo
	43	product: Clocks v4.1
	44	processor: MKV11Z128xxx7
	45	package_id: MKV11Z128VLH7
	46	mcu_data: ksdk2_0
	47	processor_version: 4.0.0
	48	board: FRDM-KV11Z
	49	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	50	/* clang-format on */
	51
	52	#include "fsl_smc.h"
	53	#include "clock_config.h"
	54
	55	/*******************************************************************************
	56	* Definitions
	57	******************************************************************************/
	58	#define OSC_CAP0P 0U /!< Oscillator 0pF capacitor load /
	59	#define OSC_ER_CLK_DISABLE 0U /!< Disable external reference clock /
	60	#define SIM_OSC32KSEL_LPO_CLK 3U /!< OSC32KSEL select: LPO clock /
	61
	62	/*******************************************************************************
	63	* Variables
	64	******************************************************************************/
	65	/* System clock frequency. */
	66	extern uint32_t SystemCoreClock;
	67
	68	/*******************************************************************************
	69	* Code
	70	******************************************************************************/
	71	/FUNCTION*********************************************************************
	72	*
	73	* Function Name : CLOCK_CONFIG_FllStableDelay
	74	* Description : This function is used to delay for FLL stable.
	75	*
	76	END*************************************************************************/
	77	static void CLOCK_CONFIG_FllStableDelay(void)
	78	{
	79	uint32_t i = 30000U;
	80	while (i--)
	81	{
	82	__NOP();
	83	}
	84	}
	85
	86	/*******************************************************************************
	87	********************** BOARD_InitBootClocks function **********************
	88	******************************************************************************/
	89	void BOARD_InitBootClocks(void)
	90	{
	91	BOARD_BootClockRUN();
	92	}
	93
	94	/*******************************************************************************
	95	******************** Configuration BOARD_BootClockRUN *********************
	96	******************************************************************************/
	97	/* clang-format off */
	98	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	99	!!Configuration
	100	name: BOARD_BootClockRUN
	101	called_from_default_init: true
	102	outputs:
	103	- {id: Bus_clock.outFreq, value: 25 MHz}
	104	- {id: Core_clock.outFreq, value: 75 MHz}
	105	- {id: ERCLK32K.outFreq, value: 1 kHz}
	106	- {id: LPO_clock.outFreq, value: 1 kHz}
	107	- {id: MCGFLLCLK.outFreq, value: 75 MHz}
	108	- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
	109	- {id: OSCERCLK.outFreq, value: 10 MHz}
	110	- {id: System_clock.outFreq, value: 75 MHz}
	111	settings:
	112	- {id: MCGMode, value: FEE}
	113	- {id: MCG.FCRDIV.scale, value: '1'}
	114	- {id: MCG.FLL_mul.scale, value: '1920'}
	115	- {id: MCG.FRDIV.scale, value: '256'}
	116	- {id: MCG.IREFS.sel, value: MCG.FRDIV}
	117	- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
	118	- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
	119	- {id: MCG_C2_RANGE0_CFG, value: Very_high}
	120	- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
	121	- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
	122	- {id: OSC_CR_SYS_OSC_CAP_LOAD_CFG, value: SC18PF}
	123	- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
	124	- {id: SIM.OUTDIV4.scale, value: '3'}
	125	- {id: SIM.OUTDIV5.scale, value: '1'}
	126	sources:
	127	- {id: OSC.OSC.outFreq, value: 10 MHz, enabled: true}
	128	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	129	/* clang-format on */
	130
	131	/*******************************************************************************
	132	* Variables for BOARD_BootClockRUN configuration
	133	******************************************************************************/
	134	const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
	135	.mcgMode = kMCG_ModeFEE, /* FEE - FLL Engaged External */
	136	.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	137	.ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
	138	.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
	139	.frdiv = 0x3U, /* FLL reference clock divider: divided by 256 */
	140	.drs = kMCG_DrsMidHigh, /* Mid-High frequency range */
	141	.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
	142	};
	143	const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
	144	.er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
	145	.clkdiv1 = 0x20000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /3, OUTDIV5: /1, disabled */
	146	};
	147	const osc_config_t oscConfig_BOARD_BootClockRUN = {
	148	.freq = 10000000U, /* Oscillator frequency: 10000000Hz */
	149	.capLoad = (kOSC_Cap2P \| kOSC_Cap16P), /* Oscillator capacity load: 18pF */
	150	.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
	151	.oscerConfig = {
	152	.enableMode =
	153	kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
	154	}};
	155
	156	/*******************************************************************************
	157	* Code for BOARD_BootClockRUN configuration
	158	******************************************************************************/
	159	void BOARD_BootClockRUN(void)
	160	{
	161	/* Set the system clock dividers in SIM to safe value. */
	162	CLOCK_SetSimSafeDivs();
	163	/* Initializes OSC0 according to board configuration. */
	164	CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
	165	CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
	166	/* Set MCG to FEE mode. */
	167	CLOCK_BootToFeeMode(kMCG_OscselOsc, mcgConfig_BOARD_BootClockRUN.frdiv, mcgConfig_BOARD_BootClockRUN.dmx32,
	168	mcgConfig_BOARD_BootClockRUN.drs, CLOCK_CONFIG_FllStableDelay);
	169	/* Configure the Internal Reference clock (MCGIRCLK). */
	170	CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
	171	mcgConfig_BOARD_BootClockRUN.fcrdiv);
	172	/* Set the clock configuration in SIM module. */
	173	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
	174	/* Set SystemCoreClock variable. */
	175	SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
	176	}
	177
	178	/*******************************************************************************
	179	******************* Configuration BOARD_BootClockVLPR *********************
	180	******************************************************************************/
	181	/* clang-format off */
	182	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	183	!!Configuration
	184	name: BOARD_BootClockVLPR
	185	outputs:
	186	- {id: Bus_clock.outFreq, value: 800 kHz}
	187	- {id: Core_clock.outFreq, value: 4 MHz}
	188	- {id: ERCLK32K.outFreq, value: 1 kHz}
	189	- {id: LPO_clock.outFreq, value: 1 kHz}
	190	- {id: MCGIRCLK.outFreq, value: 4 MHz}
	191	- {id: System_clock.outFreq, value: 4 MHz}
	192	settings:
	193	- {id: MCGMode, value: BLPI}
	194	- {id: powerMode, value: VLPR}
	195	- {id: MCG.CLKS.sel, value: MCG.IRCS}
	196	- {id: MCG.FCRDIV.scale, value: '1'}
	197	- {id: MCG.FRDIV.scale, value: '32'}
	198	- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
	199	- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
	200	- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
	201	- {id: MCG_C2_RANGE0_CFG, value: Very_high}
	202	- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
	203	- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
	204	- {id: SIM.OUTDIV4.scale, value: '5'}
	205	- {id: SIM.OUTDIV5.scale, value: '1'}
	206	sources:
	207	- {id: OSC.OSC.outFreq, value: 10 MHz}
	208	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	209	/* clang-format on */
	210
	211	/*******************************************************************************
	212	* Variables for BOARD_BootClockVLPR configuration
	213	******************************************************************************/
	214	const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
	215	.mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
	216	.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	217	.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
	218	.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
	219	.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
	220	.drs = kMCG_DrsLow, /* Low frequency range */
	221	.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
	222	};
	223	const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
	224	.er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
	225	.clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /5, OUTDIV5: /1, disabled */
	226	};
	227	const osc_config_t oscConfig_BOARD_BootClockVLPR = {
	228	.freq = 0U, /* Oscillator frequency: 0Hz */
	229	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	230	.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
	231	.oscerConfig = {
	232	.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
	233	}};
	234
	235	/*******************************************************************************
	236	* Code for BOARD_BootClockVLPR configuration
	237	******************************************************************************/
	238	void BOARD_BootClockVLPR(void)
	239	{
	240	/* Set the system clock dividers in SIM to safe value. */
	241	CLOCK_SetSimSafeDivs();
	242	/* Set MCG to BLPI mode. */
	243	CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
	244	mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
	245	/* Set the clock configuration in SIM module. */
	246	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
	247	/* Set VLPR power mode. */
	248	SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
	249	#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
	250	SMC_SetPowerModeVlpr(SMC, false);
	251	#else
	252	SMC_SetPowerModeVlpr(SMC);
	253	#endif
	254	while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
	255	{
	256	}
	257	/* Set SystemCoreClock variable. */
	258	SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
	259	}