1 files changed, 371 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/clock_config.c
new file mode 100644
index 000000000..0417bb23e
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/clock_config.c
@@ -0,0 +1,371 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017,2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ *    internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ *    1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ *    2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ *        correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ *        explicitly to setup MCGIRCLK.
+ *
+ *    3). Don't need to configure FLL explicitly, because if target mode is FLL
+ *        mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ *        if the target mode is not FLL mode, the FLL is disabled.
+ *
+ *    4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ *        setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ *        be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: MKV31F512xxx12
+package_id: MKV31F512VLL12
+mcu_data: ksdk2_0
+processor_version: 0.7.1
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+#include "fsl_smc.h"
+#include "clock_config.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define MCG_PLL_DISABLE 0U                 /*!< MCGPLLCLK disabled */
+#define OSC_CAP0P 0U                       /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE 0U              /*!< Disable external reference clock */
+#define SIM_LPUART_CLK_SEL_MCGIRCLK_CLK 3U /*!< LPUART clock select: MCGIRCLK clock */
+#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U     /*!< OSC32KSEL select: OSC32KCLK clock */
+#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U     /*!< PLLFLL select: MCGFLLCLK clock */
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_FllStableDelay
+ * Description   : This function is used to delay for FLL stable.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_FllStableDelay(void)
+{
+    uint32_t i = 30000U;
+    while (i--)
+    {
+        __NOP();
+    }
+}
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 31.45728 MHz}
+- {id: Core_clock.outFreq, value: 62.91456 MHz}
+- {id: Flash_clock.outFreq, value: 15.72864 MHz}
+- {id: FlexBus_clock.outFreq, value: 15.72864 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: LPUARTCLK.outFreq, value: 4 MHz}
+- {id: MCGFFCLK.outFreq, value: 32.768 kHz}
+- {id: MCGIRCLK.outFreq, value: 4 MHz}
+- {id: PLLFLLCLK.outFreq, value: 62.91456 MHz}
+- {id: System_clock.outFreq, value: 62.91456 MHz}
+settings:
+- {id: LPUARTClkConfig, value: 'yes'}
+- {id: MCG.FCRDIV.scale, value: '1'}
+- {id: MCG.FLL_mul.scale, value: '1920', locked: true}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
+- {id: SIM.OUTDIV1.scale, value: '1', locked: true}
+- {id: SIM.OUTDIV2.scale, value: '2'}
+- {id: SIM.OUTDIV3.scale, value: '4'}
+- {id: SIM.OUTDIV4.scale, value: '4'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
+    .mcgMode         = kMCG_ModeFEI,      /* FEI - FLL Engaged Internal */
+    .irclkEnableMode = kMCG_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCG_IrcFast,      /* Fast internal reference clock selected */
+    .fcrdiv          = 0x0U,              /* Fast IRC divider: divided by 1 */
+    .frdiv           = 0x0U,              /* FLL reference clock divider: divided by 1 */
+    .drs             = kMCG_DrsMidHigh,   /* Mid-High frequency range */
+    .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+    .oscsel          = kMCG_OscselOsc,    /* Selects System Oscillator (OSCCLK) */
+    .pll0Config =
+        {
+            .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
+            .prdiv      = 0x0U,            /* PLL Reference divider: divided by 1 */
+            .vdiv       = 0x0U,            /* VCO divider: multiplied by 24 */
+        },
+};
+const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
+    .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
+    .er32kSrc  = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
+    .clkdiv1   = 0x1330000U,                  /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /4 */
+};
+const osc_config_t oscConfig_BOARD_BootClockRUN = {
+    .freq        = 0U,           /* Oscillator frequency: 0Hz */
+    .capLoad     = (OSC_CAP0P),  /* Oscillator capacity load: 0pF */
+    .workMode    = kOSC_ModeExt, /* Use external clock */
+    .oscerConfig = {
+        .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+        .erclkDiv   = 0,                  /* Divider for OSCERCLK: divided by 1 */
+    }};
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
+                                  mcgConfig_BOARD_BootClockRUN.fcrdiv);
+    /* Set MCG to FEI mode. */
+#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
+    CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.dmx32, mcgConfig_BOARD_BootClockRUN.drs,
+                        CLOCK_CONFIG_FllStableDelay);
+#else
+    CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.drs, CLOCK_CONFIG_FllStableDelay);
+#endif
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+    /* Set LPUART clock source. */
+    CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
+}
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockHSRUN **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockHSRUN
+outputs:
+- {id: Bus_clock.outFreq, value: 41.94304 MHz}
+- {id: Core_clock.outFreq, value: 83.88608 MHz}
+- {id: Flash_clock.outFreq, value: 20.97152 MHz}
+- {id: FlexBus_clock.outFreq, value: 83.88608/3 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: LPUARTCLK.outFreq, value: 4 MHz}
+- {id: MCGFFCLK.outFreq, value: 32.768 kHz}
+- {id: MCGIRCLK.outFreq, value: 4 MHz}
+- {id: PLLFLLCLK.outFreq, value: 83.88608 MHz}
+- {id: System_clock.outFreq, value: 83.88608 MHz}
+settings:
+- {id: powerMode, value: HSRUN}
+- {id: LPUARTClkConfig, value: 'yes'}
+- {id: MCG.FCRDIV.scale, value: '1'}
+- {id: MCG.FLL_mul.scale, value: '2560'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
+- {id: SIM.OUTDIV2.scale, value: '2'}
+- {id: SIM.OUTDIV3.scale, value: '3'}
+- {id: SIM.OUTDIV4.scale, value: '4'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockHSRUN = {
+    .mcgMode         = kMCG_ModeFEI,      /* FEI - FLL Engaged Internal */
+    .irclkEnableMode = kMCG_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCG_IrcFast,      /* Fast internal reference clock selected */
+    .fcrdiv          = 0x0U,              /* Fast IRC divider: divided by 1 */
+    .frdiv           = 0x0U,              /* FLL reference clock divider: divided by 1 */
+    .drs             = kMCG_DrsHigh,      /* High frequency range */
+    .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+    .oscsel          = kMCG_OscselOsc,    /* Selects System Oscillator (OSCCLK) */
+    .pll0Config =
+        {
+            .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
+            .prdiv      = 0x0U,            /* PLL Reference divider: divided by 1 */
+            .vdiv       = 0x0U,            /* VCO divider: multiplied by 24 */
+        },
+};
+const sim_clock_config_t simConfig_BOARD_BootClockHSRUN = {
+    .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
+    .er32kSrc  = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
+    .clkdiv1   = 0x1230000U,                  /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /4 */
+};
+const osc_config_t oscConfig_BOARD_BootClockHSRUN = {
+    .freq        = 0U,           /* Oscillator frequency: 0Hz */
+    .capLoad     = (OSC_CAP0P),  /* Oscillator capacity load: 0pF */
+    .workMode    = kOSC_ModeExt, /* Use external clock */
+    .oscerConfig = {
+        .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+        .erclkDiv   = 0,                  /* Divider for OSCERCLK: divided by 1 */
+    }};
+/*******************************************************************************
+ * Code for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockHSRUN(void)
+{
+    /* Set HSRUN power mode */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+    SMC_SetPowerModeHsrun(SMC);
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
+    {
+    }
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode, mcgConfig_BOARD_BootClockHSRUN.ircs,
+                                  mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
+    /* Set MCG to FEI mode. */
+#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
+    CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockHSRUN.dmx32, mcgConfig_BOARD_BootClockHSRUN.drs,
+                        CLOCK_CONFIG_FllStableDelay);
+#else
+    CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockHSRUN.drs, CLOCK_CONFIG_FllStableDelay);
+#endif
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
+    /* Set LPUART clock source. */
+    CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
+}
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 4 MHz}
+- {id: Core_clock.outFreq, value: 4 MHz}
+- {id: Flash_clock.outFreq, value: 800 kHz}
+- {id: FlexBus_clock.outFreq, value: 2 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: LPUARTCLK.outFreq, value: 4 MHz}
+- {id: MCGIRCLK.outFreq, value: 4 MHz}
+- {id: System_clock.outFreq, value: 4 MHz}
+settings:
+- {id: MCGMode, value: BLPI}
+- {id: powerMode, value: VLPR}
+- {id: LPUARTClkConfig, value: 'yes'}
+- {id: MCG.CLKS.sel, value: MCG.IRCS}
+- {id: MCG.FCRDIV.scale, value: '1'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
+    .mcgMode         = kMCG_ModeBLPI,     /* BLPI - Bypassed Low Power Internal */
+    .irclkEnableMode = kMCG_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCG_IrcFast,      /* Fast internal reference clock selected */
+    .fcrdiv          = 0x0U,              /* Fast IRC divider: divided by 1 */
+    .frdiv           = 0x0U,              /* FLL reference clock divider: divided by 1 */
+    .drs             = kMCG_DrsLow,       /* Low frequency range */
+    .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+    .oscsel          = kMCG_OscselOsc,    /* Selects System Oscillator (OSCCLK) */
+    .pll0Config =
+        {
+            .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
+            .prdiv      = 0x0U,            /* PLL Reference divider: divided by 1 */
+            .vdiv       = 0x0U,            /* VCO divider: multiplied by 24 */
+        },
+};
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
+    .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
+    .er32kSrc  = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
+    .clkdiv1   = 0x140000U,                   /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /2, OUTDIV4: /5 */
+};
+const osc_config_t oscConfig_BOARD_BootClockVLPR = {
+    .freq        = 0U,           /* Oscillator frequency: 0Hz */
+    .capLoad     = (OSC_CAP0P),  /* Oscillator capacity load: 0pF */
+    .workMode    = kOSC_ModeExt, /* Use external clock */
+    .oscerConfig = {
+        .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+        .erclkDiv   = 0,                  /* Divider for OSCERCLK: divided by 1 */
+    }};
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to BLPI mode. */
+    CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
+                         mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    SMC_SetPowerModeVlpr(SMC, false);
+#else
+    SMC_SetPowerModeVlpr(SMC);
+#endif
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+    /* Set LPUART clock source. */
+    CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
+}

diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/clock_config.c new file mode 100644 index 000000000..0417bb23e --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/clock_config.c
@@ -0,0 +1,371 @@
	1	/*
	2	* Copyright (c) 2015, Freescale Semiconductor, Inc.
	3	* Copyright 2016-2017,2019 NXP
	4	* All rights reserved.
	5	*
	6	* SPDX-License-Identifier: BSD-3-Clause
	7	*/
	8	/***********************************************************************************************************************
	9	* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
	10	* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
	11	**********************************************************************************************************************/
	12	/*
	13	* How to setup clock using clock driver functions:
	14	*
	15	* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
	16	* and flash clock are in allowed range during clock mode switch.
	17	*
	18	* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
	19	*
	20	* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
	21	* internal reference clock(MCGIRCLK). Follow the steps to setup:
	22	*
	23	* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
	24	*
	25	* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
	26	* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
	27	* explicitly to setup MCGIRCLK.
	28	*
	29	* 3). Don't need to configure FLL explicitly, because if target mode is FLL
	30	* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
	31	* if the target mode is not FLL mode, the FLL is disabled.
	32	*
	33	* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
	34	* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
	35	* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
	36	*
	37	* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
	38	*/
	39
	40	/* clang-format off */
	41	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	42	!!GlobalInfo
	43	product: Clocks v7.0
	44	processor: MKV31F512xxx12
	45	package_id: MKV31F512VLL12
	46	mcu_data: ksdk2_0
	47	processor_version: 0.7.1
	48	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	49	/* clang-format on */
	50
	51	#include "fsl_smc.h"
	52	#include "clock_config.h"
	53
	54	/*******************************************************************************
	55	* Definitions
	56	******************************************************************************/
	57	#define MCG_PLL_DISABLE 0U /!< MCGPLLCLK disabled /
	58	#define OSC_CAP0P 0U /!< Oscillator 0pF capacitor load /
	59	#define OSC_ER_CLK_DISABLE 0U /!< Disable external reference clock /
	60	#define SIM_LPUART_CLK_SEL_MCGIRCLK_CLK 3U /!< LPUART clock select: MCGIRCLK clock /
	61	#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /!< OSC32KSEL select: OSC32KCLK clock /
	62	#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /!< PLLFLL select: MCGFLLCLK clock /
	63
	64	/*******************************************************************************
	65	* Variables
	66	******************************************************************************/
	67	/* System clock frequency. */
	68	extern uint32_t SystemCoreClock;
	69
	70	/*******************************************************************************
	71	* Code
	72	******************************************************************************/
	73	/FUNCTION*********************************************************************
	74	*
	75	* Function Name : CLOCK_CONFIG_FllStableDelay
	76	* Description : This function is used to delay for FLL stable.
	77	*
	78	END*************************************************************************/
	79	static void CLOCK_CONFIG_FllStableDelay(void)
	80	{
	81	uint32_t i = 30000U;
	82	while (i--)
	83	{
	84	__NOP();
	85	}
	86	}
	87
	88	/*******************************************************************************
	89	********************** BOARD_InitBootClocks function **********************
	90	******************************************************************************/
	91	void BOARD_InitBootClocks(void)
	92	{
	93	BOARD_BootClockRUN();
	94	}
	95
	96	/*******************************************************************************
	97	******************** Configuration BOARD_BootClockRUN *********************
	98	******************************************************************************/
	99	/* clang-format off */
	100	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	101	!!Configuration
	102	name: BOARD_BootClockRUN
	103	called_from_default_init: true
	104	outputs:
	105	- {id: Bus_clock.outFreq, value: 31.45728 MHz}
	106	- {id: Core_clock.outFreq, value: 62.91456 MHz}
	107	- {id: Flash_clock.outFreq, value: 15.72864 MHz}
	108	- {id: FlexBus_clock.outFreq, value: 15.72864 MHz}
	109	- {id: LPO_clock.outFreq, value: 1 kHz}
	110	- {id: LPUARTCLK.outFreq, value: 4 MHz}
	111	- {id: MCGFFCLK.outFreq, value: 32.768 kHz}
	112	- {id: MCGIRCLK.outFreq, value: 4 MHz}
	113	- {id: PLLFLLCLK.outFreq, value: 62.91456 MHz}
	114	- {id: System_clock.outFreq, value: 62.91456 MHz}
	115	settings:
	116	- {id: LPUARTClkConfig, value: 'yes'}
	117	- {id: MCG.FCRDIV.scale, value: '1'}
	118	- {id: MCG.FLL_mul.scale, value: '1920', locked: true}
	119	- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
	120	- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
	121	- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
	122	- {id: SIM.OUTDIV1.scale, value: '1', locked: true}
	123	- {id: SIM.OUTDIV2.scale, value: '2'}
	124	- {id: SIM.OUTDIV3.scale, value: '4'}
	125	- {id: SIM.OUTDIV4.scale, value: '4'}
	126	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	127	/* clang-format on */
	128
	129	/*******************************************************************************
	130	* Variables for BOARD_BootClockRUN configuration
	131	******************************************************************************/
	132	const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
	133	.mcgMode = kMCG_ModeFEI, /* FEI - FLL Engaged Internal */
	134	.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	135	.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
	136	.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
	137	.frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
	138	.drs = kMCG_DrsMidHigh, /* Mid-High frequency range */
	139	.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
	140	.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
	141	.pll0Config =
	142	{
	143	.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
	144	.prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
	145	.vdiv = 0x0U, /* VCO divider: multiplied by 24 */
	146	},
	147	};
	148	const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
	149	.pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
	150	.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
	151	.clkdiv1 = 0x1330000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /4 */
	152	};
	153	const osc_config_t oscConfig_BOARD_BootClockRUN = {
	154	.freq = 0U, /* Oscillator frequency: 0Hz */
	155	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	156	.workMode = kOSC_ModeExt, /* Use external clock */
	157	.oscerConfig = {
	158	.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
	159	.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
	160	}};
	161
	162	/*******************************************************************************
	163	* Code for BOARD_BootClockRUN configuration
	164	******************************************************************************/
	165	void BOARD_BootClockRUN(void)
	166	{
	167	/* Set the system clock dividers in SIM to safe value. */
	168	CLOCK_SetSimSafeDivs();
	169	/* Configure the Internal Reference clock (MCGIRCLK). */
	170	CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
	171	mcgConfig_BOARD_BootClockRUN.fcrdiv);
	172	/* Set MCG to FEI mode. */
	173	#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
	174	CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.dmx32, mcgConfig_BOARD_BootClockRUN.drs,
	175	CLOCK_CONFIG_FllStableDelay);
	176	#else
	177	CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.drs, CLOCK_CONFIG_FllStableDelay);
	178	#endif
	179	/* Set the clock configuration in SIM module. */
	180	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
	181	/* Set SystemCoreClock variable. */
	182	SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
	183	/* Set LPUART clock source. */
	184	CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
	185	}
	186
	187	/*******************************************************************************
	188	******************* Configuration BOARD_BootClockHSRUN ********************
	189	******************************************************************************/
	190	/* clang-format off */
	191	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	192	!!Configuration
	193	name: BOARD_BootClockHSRUN
	194	outputs:
	195	- {id: Bus_clock.outFreq, value: 41.94304 MHz}
	196	- {id: Core_clock.outFreq, value: 83.88608 MHz}
	197	- {id: Flash_clock.outFreq, value: 20.97152 MHz}
	198	- {id: FlexBus_clock.outFreq, value: 83.88608/3 MHz}
	199	- {id: LPO_clock.outFreq, value: 1 kHz}
	200	- {id: LPUARTCLK.outFreq, value: 4 MHz}
	201	- {id: MCGFFCLK.outFreq, value: 32.768 kHz}
	202	- {id: MCGIRCLK.outFreq, value: 4 MHz}
	203	- {id: PLLFLLCLK.outFreq, value: 83.88608 MHz}
	204	- {id: System_clock.outFreq, value: 83.88608 MHz}
	205	settings:
	206	- {id: powerMode, value: HSRUN}
	207	- {id: LPUARTClkConfig, value: 'yes'}
	208	- {id: MCG.FCRDIV.scale, value: '1'}
	209	- {id: MCG.FLL_mul.scale, value: '2560'}
	210	- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
	211	- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
	212	- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
	213	- {id: SIM.OUTDIV2.scale, value: '2'}
	214	- {id: SIM.OUTDIV3.scale, value: '3'}
	215	- {id: SIM.OUTDIV4.scale, value: '4'}
	216	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	217	/* clang-format on */
	218
	219	/*******************************************************************************
	220	* Variables for BOARD_BootClockHSRUN configuration
	221	******************************************************************************/
	222	const mcg_config_t mcgConfig_BOARD_BootClockHSRUN = {
	223	.mcgMode = kMCG_ModeFEI, /* FEI - FLL Engaged Internal */
	224	.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	225	.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
	226	.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
	227	.frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
	228	.drs = kMCG_DrsHigh, /* High frequency range */
	229	.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
	230	.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
	231	.pll0Config =
	232	{
	233	.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
	234	.prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
	235	.vdiv = 0x0U, /* VCO divider: multiplied by 24 */
	236	},
	237	};
	238	const sim_clock_config_t simConfig_BOARD_BootClockHSRUN = {
	239	.pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
	240	.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
	241	.clkdiv1 = 0x1230000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /4 */
	242	};
	243	const osc_config_t oscConfig_BOARD_BootClockHSRUN = {
	244	.freq = 0U, /* Oscillator frequency: 0Hz */
	245	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	246	.workMode = kOSC_ModeExt, /* Use external clock */
	247	.oscerConfig = {
	248	.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
	249	.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
	250	}};
	251
	252	/*******************************************************************************
	253	* Code for BOARD_BootClockHSRUN configuration
	254	******************************************************************************/
	255	void BOARD_BootClockHSRUN(void)
	256	{
	257	/* Set HSRUN power mode */
	258	SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
	259	SMC_SetPowerModeHsrun(SMC);
	260	while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
	261	{
	262	}
	263	/* Set the system clock dividers in SIM to safe value. */
	264	CLOCK_SetSimSafeDivs();
	265	/* Configure the Internal Reference clock (MCGIRCLK). */
	266	CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode, mcgConfig_BOARD_BootClockHSRUN.ircs,
	267	mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
	268	/* Set MCG to FEI mode. */
	269	#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
	270	CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockHSRUN.dmx32, mcgConfig_BOARD_BootClockHSRUN.drs,
	271	CLOCK_CONFIG_FllStableDelay);
	272	#else
	273	CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockHSRUN.drs, CLOCK_CONFIG_FllStableDelay);
	274	#endif
	275	/* Set the clock configuration in SIM module. */
	276	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
	277	/* Set SystemCoreClock variable. */
	278	SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
	279	/* Set LPUART clock source. */
	280	CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
	281	}
	282
	283	/*******************************************************************************
	284	******************* Configuration BOARD_BootClockVLPR *********************
	285	******************************************************************************/
	286	/* clang-format off */
	287	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	288	!!Configuration
	289	name: BOARD_BootClockVLPR
	290	outputs:
	291	- {id: Bus_clock.outFreq, value: 4 MHz}
	292	- {id: Core_clock.outFreq, value: 4 MHz}
	293	- {id: Flash_clock.outFreq, value: 800 kHz}
	294	- {id: FlexBus_clock.outFreq, value: 2 MHz}
	295	- {id: LPO_clock.outFreq, value: 1 kHz}
	296	- {id: LPUARTCLK.outFreq, value: 4 MHz}
	297	- {id: MCGIRCLK.outFreq, value: 4 MHz}
	298	- {id: System_clock.outFreq, value: 4 MHz}
	299	settings:
	300	- {id: MCGMode, value: BLPI}
	301	- {id: powerMode, value: VLPR}
	302	- {id: LPUARTClkConfig, value: 'yes'}
	303	- {id: MCG.CLKS.sel, value: MCG.IRCS}
	304	- {id: MCG.FCRDIV.scale, value: '1'}
	305	- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
	306	- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
	307	- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
	308	- {id: SIM.OUTDIV4.scale, value: '5'}
	309	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	310	/* clang-format on */
	311
	312	/*******************************************************************************
	313	* Variables for BOARD_BootClockVLPR configuration
	314	******************************************************************************/
	315	const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
	316	.mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
	317	.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	318	.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
	319	.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
	320	.frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
	321	.drs = kMCG_DrsLow, /* Low frequency range */
	322	.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
	323	.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
	324	.pll0Config =
	325	{
	326	.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
	327	.prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
	328	.vdiv = 0x0U, /* VCO divider: multiplied by 24 */
	329	},
	330	};
	331	const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
	332	.pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
	333	.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
	334	.clkdiv1 = 0x140000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /2, OUTDIV4: /5 */
	335	};
	336	const osc_config_t oscConfig_BOARD_BootClockVLPR = {
	337	.freq = 0U, /* Oscillator frequency: 0Hz */
	338	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	339	.workMode = kOSC_ModeExt, /* Use external clock */
	340	.oscerConfig = {
	341	.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
	342	.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
	343	}};
	344
	345	/*******************************************************************************
	346	* Code for BOARD_BootClockVLPR configuration
	347	******************************************************************************/
	348	void BOARD_BootClockVLPR(void)
	349	{
	350	/* Set the system clock dividers in SIM to safe value. */
	351	CLOCK_SetSimSafeDivs();
	352	/* Set MCG to BLPI mode. */
	353	CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
	354	mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
	355	/* Set the clock configuration in SIM module. */
	356	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
	357	/* Set VLPR power mode. */
	358	SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
	359	#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
	360	SMC_SetPowerModeVlpr(SMC, false);
	361	#else
	362	SMC_SetPowerModeVlpr(SMC);
	363	#endif
	364	while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
	365	{
	366	}
	367	/* Set SystemCoreClock variable. */
	368	SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
	369	/* Set LPUART clock source. */
	370	CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
	371	}