1 files changed, 271 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso54s018/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso54s018/clock_config.c
new file mode 100644
index 000000000..a06de1eff
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso54s018/clock_config.c
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017,2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Setup voltage for the fastest of the clock outputs
+ *
+ * 3. Set up wait states of the flash.
+ *
+ * 4. Set up all dividers.
+ *
+ * 5. Set up all selectors to provide selected clocks.
+ */
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: LPC54S018
+package_id: LPC54S018JET180
+mcu_data: ksdk2_0
+processor_version: 0.8.3
+board: LPCXpresso54S018
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL180M();
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+                                             accidentally being below the voltage for current speed */
+    /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
+         before calling this API since this API is implemented in ROM code */
+    CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
+    POWER_SetVoltageForFreq(
+        12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF48M
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF48M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+                                             accidentally being below the voltage for current speed */
+    POWER_SetVoltageForFreq(
+        48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
+         before calling this API since this API is implemented in ROM code */
+    CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 96 MHz}
+- {id: MAIN_clock.outFreq, value: 96 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+sources:
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+                                             accidentally being below the voltage for current speed */
+    POWER_SetVoltageForFreq(
+        96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
+         before calling this API since this API is implemented in ROM code */
+    CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL180M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL180M
+called_from_default_init: true
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 96 MHz}
+- {id: MAIN_clock.outFreq, value: 180 MHz}
+- {id: SYSPLL_clock.outFreq, value: 180 MHz}
+- {id: System_clock.outFreq, value: 180 MHz}
+- {id: USB0_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
+- {id: SYSCON.M_MULT.scale, value: '30', locked: true}
+- {id: SYSCON.N_DIV.scale, value: '1', locked: true}
+- {id: SYSCON.PDEC.scale, value: '2', locked: true}
+- {id: SYSCON.USB0CLKDIV.scale, value: '2'}
+- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.fro_hf}
+- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
+sources:
+- {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true}
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL180M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);  /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);  /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+                                              accidentally  being below the voltage for current speed */
+    POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC); /*!< Enable System Oscillator Power */
+    SYSCON->SYSOSCCTRL = ((SYSCON->SYSOSCCTRL & ~SYSCON_SYSOSCCTRL_FREQRANGE_MASK) |
+                          SYSCON_SYSOSCCTRL_FREQRANGE(0U)); /*!< Set system oscillator range */
+    POWER_SetVoltageForFreq(
+        180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    /*!< Set up SYS PLL */
+    const pll_setup_t pllSetup = {
+        .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U),
+        .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
+        .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
+        .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
+        .pllRate = 180000000U,
+        .flags   = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP};
+    CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
+    CLOCK_SetPLLFreq(&pllSetup);         /*!< Configure PLL to the desired value */
+    /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
+         before calling this API since this API is implemented in ROM code */
+    CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);  /*!< Reset divider counter and set divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true);  /*!< Reset USB0CLKDIV divider counter and halt it */
+    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Set USB0CLKDIV divider to value 2 */
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
+    CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);  /*!< Switch USB0_CLK to FRO_HF */
+    SYSCON->MAINCLKSELA =
+        ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) |
+         SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK;
+}

diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso54s018/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso54s018/clock_config.c new file mode 100644 index 000000000..a06de1eff --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso54s018/clock_config.c
@@ -0,0 +1,271 @@
	1	/*
	2	* Copyright (c) 2015, Freescale Semiconductor, Inc.
	3	* Copyright 2016-2017,2019 NXP
	4	* All rights reserved.
	5	*
	6	* SPDX-License-Identifier: BSD-3-Clause
	7	*/
	8	/***********************************************************************************************************************
	9	* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
	10	* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
	11	**********************************************************************************************************************/
	12	/*
	13	* How to set up clock using clock driver functions:
	14	*
	15	* 1. Setup clock sources.
	16	*
	17	* 2. Setup voltage for the fastest of the clock outputs
	18	*
	19	* 3. Set up wait states of the flash.
	20	*
	21	* 4. Set up all dividers.
	22	*
	23	* 5. Set up all selectors to provide selected clocks.
	24	*/
	25
	26	/* clang-format off */
	27	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	28	!!GlobalInfo
	29	product: Clocks v7.0
	30	processor: LPC54S018
	31	package_id: LPC54S018JET180
	32	mcu_data: ksdk2_0
	33	processor_version: 0.8.3
	34	board: LPCXpresso54S018
	35	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	36	/* clang-format on */
	37
	38	#include "fsl_power.h"
	39	#include "fsl_clock.h"
	40	#include "clock_config.h"
	41
	42	/*******************************************************************************
	43	* Definitions
	44	******************************************************************************/
	45
	46	/*******************************************************************************
	47	* Variables
	48	******************************************************************************/
	49	/* System clock frequency. */
	50	extern uint32_t SystemCoreClock;
	51
	52	/*******************************************************************************
	53	********************** BOARD_InitBootClocks function **********************
	54	******************************************************************************/
	55	void BOARD_InitBootClocks(void)
	56	{
	57	BOARD_BootClockPLL180M();
	58	}
	59
	60	/*******************************************************************************
	61	****************** Configuration BOARD_BootClockFRO12M ********************
	62	******************************************************************************/
	63	/* clang-format off */
	64	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	65	!!Configuration
	66	name: BOARD_BootClockFRO12M
	67	outputs:
	68	- {id: FRO12M_clock.outFreq, value: 12 MHz}
	69	- {id: FROHF_clock.outFreq, value: 48 MHz}
	70	- {id: MAIN_clock.outFreq, value: 12 MHz}
	71	- {id: System_clock.outFreq, value: 12 MHz}
	72	settings:
	73	- {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true}
	74	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	75	/* clang-format on */
	76
	77	/*******************************************************************************
	78	* Variables for BOARD_BootClockFRO12M configuration
	79	******************************************************************************/
	80	/*******************************************************************************
	81	* Code for BOARD_BootClockFRO12M configuration
	82	******************************************************************************/
	83	void BOARD_BootClockFRO12M(void)
	84	{
	85	/!< Set up the clock sources /
	86	/!< Set up FRO /
	87	POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /!< Ensure FRO is on /
	88	CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
	89	accidentally being below the voltage for current speed */
	90	/*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
	91	before calling this API since this API is implemented in ROM code */
	92	CLOCK_SetupFROClocking(12000000U); /!< Set up FRO to the 12 MHz, just for sure /
	93	POWER_SetVoltageForFreq(
	94	12000000U); /!< Set voltage for the one of the fastest clock outputs: System clock output /
	95
	96	/!< Set up dividers /
	97	CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /!< Reset divider counter and set divider to value 1 /
	98
	99	/!< Set up clock selectors - Attach clocks to the peripheries /
	100	CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /!< Switch MAIN_CLK to FRO12M /
	101	/* Set SystemCoreClock variable. */
	102	SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
	103	}
	104
	105	/*******************************************************************************
	106	***************** Configuration BOARD_BootClockFROHF48M *******************
	107	******************************************************************************/
	108	/* clang-format off */
	109	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	110	!!Configuration
	111	name: BOARD_BootClockFROHF48M
	112	outputs:
	113	- {id: FRO12M_clock.outFreq, value: 12 MHz}
	114	- {id: FROHF_clock.outFreq, value: 48 MHz}
	115	- {id: MAIN_clock.outFreq, value: 48 MHz}
	116	- {id: System_clock.outFreq, value: 48 MHz}
	117	settings:
	118	- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
	119	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	120	/* clang-format on */
	121
	122	/*******************************************************************************
	123	* Variables for BOARD_BootClockFROHF48M configuration
	124	******************************************************************************/
	125	/*******************************************************************************
	126	* Code for BOARD_BootClockFROHF48M configuration
	127	******************************************************************************/
	128	void BOARD_BootClockFROHF48M(void)
	129	{
	130	/!< Set up the clock sources /
	131	/!< Set up FRO /
	132	POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /!< Ensure FRO is on /
	133	CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
	134	accidentally being below the voltage for current speed */
	135	POWER_SetVoltageForFreq(
	136	48000000U); /!< Set voltage for the one of the fastest clock outputs: System clock output /
	137	/*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
	138	before calling this API since this API is implemented in ROM code */
	139	CLOCK_SetupFROClocking(48000000U); /!< Set up high frequency FRO output to selected frequency /
	140
	141	/!< Set up dividers /
	142	CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /!< Reset divider counter and set divider to value 1 /
	143
	144	/!< Set up clock selectors - Attach clocks to the peripheries /
	145	CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /!< Switch MAIN_CLK to FRO_HF /
	146	/* Set SystemCoreClock variable. */
	147	SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
	148	}
	149
	150	/*******************************************************************************
	151	***************** Configuration BOARD_BootClockFROHF96M *******************
	152	******************************************************************************/
	153	/* clang-format off */
	154	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	155	!!Configuration
	156	name: BOARD_BootClockFROHF96M
	157	outputs:
	158	- {id: FRO12M_clock.outFreq, value: 12 MHz}
	159	- {id: FROHF_clock.outFreq, value: 96 MHz}
	160	- {id: MAIN_clock.outFreq, value: 96 MHz}
	161	- {id: System_clock.outFreq, value: 96 MHz}
	162	settings:
	163	- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
	164	sources:
	165	- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
	166	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	167	/* clang-format on */
	168
	169	/*******************************************************************************
	170	* Variables for BOARD_BootClockFROHF96M configuration
	171	******************************************************************************/
	172	/*******************************************************************************
	173	* Code for BOARD_BootClockFROHF96M configuration
	174	******************************************************************************/
	175	void BOARD_BootClockFROHF96M(void)
	176	{
	177	/!< Set up the clock sources /
	178	/!< Set up FRO /
	179	POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /!< Ensure FRO is on /
	180	CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
	181	accidentally being below the voltage for current speed */
	182	POWER_SetVoltageForFreq(
	183	96000000U); /!< Set voltage for the one of the fastest clock outputs: System clock output /
	184	/*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
	185	before calling this API since this API is implemented in ROM code */
	186	CLOCK_SetupFROClocking(96000000U); /!< Set up high frequency FRO output to selected frequency /
	187
	188	/!< Set up dividers /
	189	CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /!< Reset divider counter and set divider to value 1 /
	190
	191	/!< Set up clock selectors - Attach clocks to the peripheries /
	192	CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /!< Switch MAIN_CLK to FRO_HF /
	193	/* Set SystemCoreClock variable. */
	194	SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
	195	}
	196
	197	/*******************************************************************************
	198	****************** Configuration BOARD_BootClockPLL180M *******************
	199	******************************************************************************/
	200	/* clang-format off */
	201	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	202	!!Configuration
	203	name: BOARD_BootClockPLL180M
	204	called_from_default_init: true
	205	outputs:
	206	- {id: FRO12M_clock.outFreq, value: 12 MHz}
	207	- {id: FROHF_clock.outFreq, value: 96 MHz}
	208	- {id: MAIN_clock.outFreq, value: 180 MHz}
	209	- {id: SYSPLL_clock.outFreq, value: 180 MHz}
	210	- {id: System_clock.outFreq, value: 180 MHz}
	211	- {id: USB0_clock.outFreq, value: 48 MHz}
	212	settings:
	213	- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
	214	- {id: SYSCON.M_MULT.scale, value: '30', locked: true}
	215	- {id: SYSCON.N_DIV.scale, value: '1', locked: true}
	216	- {id: SYSCON.PDEC.scale, value: '2', locked: true}
	217	- {id: SYSCON.USB0CLKDIV.scale, value: '2'}
	218	- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.fro_hf}
	219	- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
	220	sources:
	221	- {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true}
	222	- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
	223	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	224	/* clang-format on */
	225
	226	/*******************************************************************************
	227	* Variables for BOARD_BootClockPLL180M configuration
	228	******************************************************************************/
	229	/*******************************************************************************
	230	* Code for BOARD_BootClockPLL180M configuration
	231	******************************************************************************/
	232	void BOARD_BootClockPLL180M(void)
	233	{
	234	/!< Set up the clock sources /
	235	/!< Set up FRO /
	236	POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /!< Ensure FRO is on /
	237	CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
	238	accidentally being below the voltage for current speed */
	239	POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC); /!< Enable System Oscillator Power /
	240	SYSCON->SYSOSCCTRL = ((SYSCON->SYSOSCCTRL & ~SYSCON_SYSOSCCTRL_FREQRANGE_MASK) \|
	241	SYSCON_SYSOSCCTRL_FREQRANGE(0U)); /!< Set system oscillator range /
	242	POWER_SetVoltageForFreq(
	243	180000000U); /!< Set voltage for the one of the fastest clock outputs: System clock output /
	244	/!< Set up SYS PLL /
	245	const pll_setup_t pllSetup = {
	246	.pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) \| SYSCON_SYSPLLCTRL_SELP(16U) \| SYSCON_SYSPLLCTRL_SELR(0U),
	247	.pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
	248	.pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
	249	.pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
	250	.pllRate = 180000000U,
	251	.flags = PLL_SETUPFLAG_WAITLOCK \| PLL_SETUPFLAG_POWERUP};
	252	CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /!< Set sys pll clock source/
	253	CLOCK_SetPLLFreq(&pllSetup); /!< Configure PLL to the desired value /
	254	/*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
	255	before calling this API since this API is implemented in ROM code */
	256	CLOCK_SetupFROClocking(96000000U); /!< Set up high frequency FRO output to selected frequency /
	257
	258	/!< Set up dividers /
	259	CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /!< Reset divider counter and set divider to value 1 /
	260	CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /!< Reset USB0CLKDIV divider counter and halt it /
	261	CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /!< Set USB0CLKDIV divider to value 2 /
	262
	263	/!< Set up clock selectors - Attach clocks to the peripheries /
	264	CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /!< Switch MAIN_CLK to SYS_PLL /
	265	CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); /!< Switch USB0_CLK to FRO_HF /
	266	SYSCON->MAINCLKSELA =
	267	((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) \|
	268	SYSCON_MAINCLKSELA_SEL(0U)); /!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB /
	269	/* Set SystemCoreClock variable. */
	270	SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK;
	271	}