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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/board.c122
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/board.h252
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/clock_config.c379
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/clock_config.h173
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/board.c122
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/board.h252
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/clock_config.c369
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/clock_config.h173
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/peripherals.c23
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/peripherals.h23
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/pin_mux.c99
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/pin_mux.h59
12 files changed, 2046 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/board.c b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/board.c
new file mode 100644
index 000000000..4774ebb65
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/board.c
@@ -0,0 +1,122 @@
1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include <stdint.h>
9#include "fsl_common.h"
10#include "fsl_debug_console.h"
11#include "board.h"
12#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
13#include "fsl_i2c.h"
14#endif /* SDK_I2C_BASED_COMPONENT_USED */
15
16/*******************************************************************************
17 * Variables
18 ******************************************************************************/
19
20/*******************************************************************************
21 * Code
22 ******************************************************************************/
23/* Initialize debug console. */
24void BOARD_InitDebugConsole(void)
25{
26 /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
27 CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
28
29 RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
30
31 uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
32
33 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
34}
35
36#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
37void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
38{
39 i2c_master_config_t i2cConfig = {0};
40
41 I2C_MasterGetDefaultConfig(&i2cConfig);
42 I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
43}
44
45status_t BOARD_I2C_Send(I2C_Type *base,
46 uint8_t deviceAddress,
47 uint32_t subAddress,
48 uint8_t subaddressSize,
49 uint8_t *txBuff,
50 uint8_t txBuffSize)
51{
52 i2c_master_transfer_t masterXfer;
53
54 /* Prepare transfer structure. */
55 masterXfer.slaveAddress = deviceAddress;
56 masterXfer.direction = kI2C_Write;
57 masterXfer.subaddress = subAddress;
58 masterXfer.subaddressSize = subaddressSize;
59 masterXfer.data = txBuff;
60 masterXfer.dataSize = txBuffSize;
61 masterXfer.flags = kI2C_TransferDefaultFlag;
62
63 return I2C_MasterTransferBlocking(base, &masterXfer);
64}
65
66status_t BOARD_I2C_Receive(I2C_Type *base,
67 uint8_t deviceAddress,
68 uint32_t subAddress,
69 uint8_t subaddressSize,
70 uint8_t *rxBuff,
71 uint8_t rxBuffSize)
72{
73 i2c_master_transfer_t masterXfer;
74
75 /* Prepare transfer structure. */
76 masterXfer.slaveAddress = deviceAddress;
77 masterXfer.subaddress = subAddress;
78 masterXfer.subaddressSize = subaddressSize;
79 masterXfer.data = rxBuff;
80 masterXfer.dataSize = rxBuffSize;
81 masterXfer.direction = kI2C_Read;
82 masterXfer.flags = kI2C_TransferDefaultFlag;
83
84 return I2C_MasterTransferBlocking(base, &masterXfer);
85}
86
87void BOARD_Accel_I2C_Init(void)
88{
89 BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
90}
91
92status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
93{
94 uint8_t data = (uint8_t)txBuff;
95
96 return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
97}
98
99status_t BOARD_Accel_I2C_Receive(
100 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
101{
102 return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
103}
104
105void BOARD_Codec_I2C_Init(void)
106{
107 BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
108}
109
110status_t BOARD_Codec_I2C_Send(
111 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
112{
113 return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
114 txBuffSize);
115}
116
117status_t BOARD_Codec_I2C_Receive(
118 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
119{
120 return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
121}
122#endif /* SDK_I2C_BASED_COMPONENT_USED */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/board.h b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/board.h
new file mode 100644
index 000000000..1a31bb77a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/board.h
@@ -0,0 +1,252 @@
1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10
11#include "clock_config.h"
12#include "fsl_common.h"
13#include "fsl_reset.h"
14#include "fsl_gpio.h"
15#include "fsl_iocon.h"
16
17/*******************************************************************************
18 * Definitions
19 ******************************************************************************/
20/*! @brief The board name */
21#define BOARD_NAME "LPCXpresso55S16"
22
23/*! @brief The UART to use for debug messages. */
24/* TODO: rename UART to USART */
25#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
26#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0
27#define BOARD_DEBUG_UART_INSTANCE 0U
28#define BOARD_DEBUG_UART_CLK_FREQ 12000000U
29#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
30#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn
31#define BOARD_DEBUG_UART_CLKSRC kCLOCK_Flexcomm0
32#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler
33#define BOARD_UART_IRQ FLEXCOMM0_IRQn
34
35#define BOARD_ACCEL_I2C_BASEADDR I2C4
36#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
37
38#ifndef BOARD_DEBUG_UART_BAUDRATE
39#define BOARD_DEBUG_UART_BAUDRATE 115200U
40#endif /* BOARD_DEBUG_UART_BAUDRATE */
41
42#define BOARD_CODEC_I2C_BASEADDR I2C4
43#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
44#define BOARD_CODEC_I2C_INSTANCE 4
45#ifndef BOARD_LED_RED_GPIO
46#define BOARD_LED_RED_GPIO GPIO
47#endif
48#define BOARD_LED_RED_GPIO_PORT 1U
49#ifndef BOARD_LED_RED_GPIO_PIN
50#define BOARD_LED_RED_GPIO_PIN 4U
51#endif
52
53#ifndef BOARD_LED_BLUE_GPIO
54#define BOARD_LED_BLUE_GPIO GPIO
55#endif
56#define BOARD_LED_BLUE_GPIO_PORT 1U
57#ifndef BOARD_LED_BLUE_GPIO_PIN
58#define BOARD_LED_BLUE_GPIO_PIN 6U
59#endif
60
61#ifndef BOARD_LED_GREEN_GPIO
62#define BOARD_LED_GREEN_GPIO GPIO
63#endif
64#define BOARD_LED_GREEN_GPIO_PORT 1U
65#ifndef BOARD_LED_GREEN_GPIO_PIN
66#define BOARD_LED_GREEN_GPIO_PIN 7U
67#endif
68
69#ifndef BOARD_SW1_GPIO
70#define BOARD_SW1_GPIO GPIO
71#endif
72#define BOARD_SW1_GPIO_PORT 1U
73#ifndef BOARD_SW1_GPIO_PIN
74#define BOARD_SW1_GPIO_PIN 18U
75#endif
76#define BOARD_SW1_NAME "SW1"
77#define BOARD_SW1_IRQ PIN_INT1_IRQn
78#define BOARD_SW1_IRQ_HANDLER PIN_INT1_IRQHandler
79
80#ifndef BOARD_SW3_GPIO
81#define BOARD_SW3_GPIO GPIO
82#endif
83#define BOARD_SW3_GPIO_PORT 1U
84#ifndef BOARD_SW3_GPIO_PIN
85#define BOARD_SW3_GPIO_PIN 9U
86#endif
87#define BOARD_SW3_NAME "SW3"
88#define BOARD_SW3_IRQ PIN_INT1_IRQn
89#define BOARD_SW3_IRQ_HANDLER PIN_INT1_IRQHandler
90#define BOARD_SW3_GPIO_PININT_INDEX 1
91
92#ifndef BOARD_SW4_GPIO
93#define BOARD_SW4_GPIO GPIO
94#endif
95#define BOARD_SW4_GPIO_PORT 0U
96#ifndef BOARD_SW4_GPIO_PIN
97#define BOARD_SW4_GPIO_PIN 5U
98#endif
99#define BOARD_SW4_NAME "SW4"
100#define BOARD_SW4_IRQ PIN_INT0_IRQn
101#define BOARD_SW4_IRQ_HANDLER PIN_INT0_IRQHandler
102#define BOARD_SW4_GPIO_PININT_INDEX 1
103
104#define BOARD_SDIF_BASEADDR SDIF
105#define BOARD_SDIF_CLKSRC kCLOCK_SDio
106#define BOARD_SDIF_CLK_FREQ CLOCK_GetSdioClkFreq()
107#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
108#define BOARD_SDIF_IRQ SDIO_IRQn
109#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
110#define BOARD_SD_CARD_DETECT_PIN 17
111#define BOARD_SD_CARD_DETECT_PORT 0
112#define BOARD_SD_CARD_DETECT_GPIO GPIO
113#define BOARD_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostCD
114
115#define BOARD_SDIF_CD_GPIO_INIT() \
116 { \
117 CLOCK_EnableClock(kCLOCK_Gpio2); \
118 GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \
119 &(gpio_pin_config_t){kGPIO_DigitalInput, 0U}); \
120 }
121#define BOARD_SDIF_CD_STATUS() \
122 GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)
123
124/* Board led color mapping */
125#define LOGIC_LED_ON 1U
126#define LOGIC_LED_OFF 0U
127
128#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
129
130#define LED_RED_INIT(output) \
131 { \
132 IOCON_PinMuxSet(IOCON, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, IOCON_DIGITAL_EN); \
133 GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \
134 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
135 }
136#define LED_RED_OFF() \
137 GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
138 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED1 */
139#define LED_RED_ON() \
140 GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
141 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED1 \ \ \ \ \ \ \ \ \ \ \
142 */
143#define LED_RED_TOGGLE() \
144 GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
145 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED1 */
146
147#define LED_BLUE_INIT(output) \
148 { \
149 IOCON_PinMuxSet(IOCON, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, IOCON_DIGITAL_EN); \
150 GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \
151 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
152 }
153#define LED_BLUE_OFF() \
154 GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
155 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED1 */
156#define LED_BLUE_ON() \
157 GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
158 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED1 */
159#define LED_BLUE_TOGGLE() \
160 GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
161 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED1 */
162
163#define LED_GREEN_INIT(output) \
164 GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
165 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */
166#define LED_GREEN_OFF() \
167 GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
168 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED1 */
169#define LED_GREEN_ON() \
170 GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
171 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED1 */
172#define LED_GREEN_TOGGLE() \
173 GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
174 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED1 */
175
176/*! @brief The WIFI-QCA shield pin. */
177#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO
178#define BOARD_INITGT202SHIELD_PWRON_PORT 1U
179#define BOARD_INITGT202SHIELD_PWRON_PIN 8U
180
181#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO
182#define BOARD_INITGT202SHIELD_IRQ_PORT 1U
183#define BOARD_INITGT202SHIELD_IRQ_PIN 9U
184
185/*! @brief The WIFI-QCA shield pin. */
186#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO
187#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U
188#define BOARD_INITSILEX2401SHIELD_PWRON_PIN 7U
189
190#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO
191#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 0U
192#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 15U
193
194/*! @brief The WIFI-QCA shield pin. */
195#define BOARD_INITWIFI10CLICKSHIELD_PWRON_GPIO GPIO
196#define BOARD_INITWIFI10CLICKSHIELD_PWRON_PORT 1U
197#define BOARD_INITWIFI10CLICKSHIELD_PWRON_PIN 5U
198
199#define BOARD_INITWIFI10CLICKSHIELD_IRQ_GPIO GPIO
200#define BOARD_INITWIFI10CLICKSHIELD_IRQ_PORT 1U
201#define BOARD_INITWIFI10CLICKSHIELD_IRQ_GPIO_PIN 18U
202
203/* Display. */
204#define BOARD_LCD_DC_GPIO GPIO
205#define BOARD_LCD_DC_GPIO_PORT 1U
206#define BOARD_LCD_DC_GPIO_PIN 5U
207
208/* Serial MWM WIFI */
209#define BOARD_SERIAL_MWM_PORT_CLK_FREQ CLOCK_GetFlexCommClkFreq(2)
210#define BOARD_SERIAL_MWM_PORT USART2
211#define BOARD_SERIAL_MWM_PORT_IRQn FLEXCOMM2_IRQn
212#define BOARD_SERIAL_MWM_RST_WRITE(output)
213
214#if defined(__cplusplus)
215extern "C" {
216#endif /* __cplusplus */
217
218/*******************************************************************************
219 * API
220 ******************************************************************************/
221
222void BOARD_InitDebugConsole(void);
223#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
224void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
225status_t BOARD_I2C_Send(I2C_Type *base,
226 uint8_t deviceAddress,
227 uint32_t subAddress,
228 uint8_t subaddressSize,
229 uint8_t *txBuff,
230 uint8_t txBuffSize);
231status_t BOARD_I2C_Receive(I2C_Type *base,
232 uint8_t deviceAddress,
233 uint32_t subAddress,
234 uint8_t subaddressSize,
235 uint8_t *rxBuff,
236 uint8_t rxBuffSize);
237void BOARD_Accel_I2C_Init(void);
238status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
239status_t BOARD_Accel_I2C_Receive(
240 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
241void BOARD_Codec_I2C_Init(void);
242status_t BOARD_Codec_I2C_Send(
243 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
244status_t BOARD_Codec_I2C_Receive(
245 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
246#endif /* SDK_I2C_BASED_COMPONENT_USED */
247
248#if defined(__cplusplus)
249}
250#endif /* __cplusplus */
251
252#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/clock_config.c
new file mode 100644
index 000000000..bf38e4959
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/clock_config.c
@@ -0,0 +1,379 @@
1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12/*
13 * How to set up clock using clock driver functions:
14 *
15 * 1. Setup clock sources.
16 *
17 * 2. Set up wait states of the flash.
18 *
19 * 3. Set up all dividers.
20 *
21 * 4. Set up all selectors to provide selected clocks.
22 */
23
24/* clang-format off */
25/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
26!!GlobalInfo
27product: Clocks v6.0
28processor: LPC55S16
29package_id: LPC55S16JBD100
30mcu_data: ksdk2_0
31processor_version: 0.0.4
32board: LPCXpresso55S16
33 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
34/* clang-format on */
35
36#include "fsl_power.h"
37#include "fsl_clock.h"
38#include "clock_config.h"
39
40/*******************************************************************************
41 * Definitions
42 ******************************************************************************/
43
44/*******************************************************************************
45 * Variables
46 ******************************************************************************/
47/* System clock frequency. */
48extern uint32_t SystemCoreClock;
49
50/*******************************************************************************
51 ************************ BOARD_InitBootClocks function ************************
52 ******************************************************************************/
53void BOARD_InitBootClocks(void)
54{
55 BOARD_BootClockPLL150M();
56}
57
58/*******************************************************************************
59 ******************** Configuration BOARD_BootClockFRO12M **********************
60 ******************************************************************************/
61/* clang-format off */
62/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
63!!Configuration
64name: BOARD_BootClockFRO12M
65outputs:
66- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
67- {id: System_clock.outFreq, value: 12 MHz}
68settings:
69- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
70sources:
71- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
72 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
73/* clang-format on */
74
75/*******************************************************************************
76 * Variables for BOARD_BootClockFRO12M configuration
77 ******************************************************************************/
78/*******************************************************************************
79 * Code for BOARD_BootClockFRO12M configuration
80 ******************************************************************************/
81void BOARD_BootClockFRO12M(void)
82{
83#ifndef SDK_SECONDARY_CORE
84 /*!< Set up the clock sources */
85 /*!< Configure FRO192M */
86 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
87 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
88 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
89
90 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
91
92 POWER_SetVoltageForFreq(
93 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
94 CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
95
96 /*!< Set up dividers */
97 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
98
99 /*!< Set up clock selectors - Attach clocks to the peripheries */
100 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
101
102 /*< Set SystemCoreClock variable. */
103 SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
104#endif
105}
106
107/*******************************************************************************
108 ******************* Configuration BOARD_BootClockFROHF96M *********************
109 ******************************************************************************/
110/* clang-format off */
111/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
112!!Configuration
113name: BOARD_BootClockFROHF96M
114outputs:
115- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
116- {id: System_clock.outFreq, value: 96 MHz}
117settings:
118- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
119- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
120sources:
121- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
122 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
123/* clang-format on */
124
125/*******************************************************************************
126 * Variables for BOARD_BootClockFROHF96M configuration
127 ******************************************************************************/
128/*******************************************************************************
129 * Code for BOARD_BootClockFROHF96M configuration
130 ******************************************************************************/
131void BOARD_BootClockFROHF96M(void)
132{
133#ifndef SDK_SECONDARY_CORE
134 /*!< Set up the clock sources */
135 /*!< Configure FRO192M */
136 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
137 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
138 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
139
140 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
141
142 POWER_SetVoltageForFreq(
143 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
144 CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
145
146 /*!< Set up dividers */
147 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
148
149 /*!< Set up clock selectors - Attach clocks to the peripheries */
150 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
151
152 /*< Set SystemCoreClock variable. */
153 SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
154#endif
155}
156
157/*******************************************************************************
158 ******************** Configuration BOARD_BootClockPLL100M *********************
159 ******************************************************************************/
160/* clang-format off */
161/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
162!!Configuration
163name: BOARD_BootClockPLL100M
164outputs:
165- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
166- {id: System_clock.outFreq, value: 100 MHz}
167settings:
168- {id: PLL0_Mode, value: Normal}
169- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
170- {id: ENABLE_CLKIN_ENA, value: Enabled}
171- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
172- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
173- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
174- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
175- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
176- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
177sources:
178- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
179- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
180 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
181/* clang-format on */
182
183/*******************************************************************************
184 * Variables for BOARD_BootClockPLL100M configuration
185 ******************************************************************************/
186/*******************************************************************************
187 * Code for BOARD_BootClockPLL100M configuration
188 ******************************************************************************/
189void BOARD_BootClockPLL100M(void)
190{
191#ifndef SDK_SECONDARY_CORE
192 /*!< Set up the clock sources */
193 /*!< Configure FRO192M */
194 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
195 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
196 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
197
198 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
199
200 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
201 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
202 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
203 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
204 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
205
206 POWER_SetVoltageForFreq(
207 100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
208 CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
209
210 /*!< Set up PLL */
211 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
212 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
213 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
214 const pll_setup_t pll0Setup = {
215 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
216 .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
217 .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
218 .pllsscg = {0x0U, (SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
219 .pllRate = 100000000U,
220 .flags = PLL_SETUPFLAG_WAITLOCK};
221 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
222
223 /*!< Set up dividers */
224 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
225
226 /*!< Set up clock selectors - Attach clocks to the peripheries */
227 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
228
229 /*< Set SystemCoreClock variable. */
230 SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
231#endif
232}
233
234/*******************************************************************************
235 ******************** Configuration BOARD_BootClockPLL150M *********************
236 ******************************************************************************/
237/* clang-format off */
238/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
239!!Configuration
240name: BOARD_BootClockPLL150M
241called_from_default_init: true
242outputs:
243- {id: System_clock.outFreq, value: 150 MHz}
244settings:
245- {id: PLL0_Mode, value: Normal}
246- {id: ENABLE_CLKIN_ENA, value: Enabled}
247- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
248- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
249- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
250- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
251- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
252- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
253sources:
254- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
255 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
256/* clang-format on */
257
258/*******************************************************************************
259 * Variables for BOARD_BootClockPLL150M configuration
260 ******************************************************************************/
261/*******************************************************************************
262 * Code for BOARD_BootClockPLL150M configuration
263 ******************************************************************************/
264void BOARD_BootClockPLL150M(void)
265{
266#ifndef SDK_SECONDARY_CORE
267 /*!< Set up the clock sources */
268 /*!< Configure FRO192M */
269 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
270 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
271 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
272
273 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
274 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
275 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
276 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
277 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
278
279 POWER_SetVoltageForFreq(
280 150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
281 CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
282
283 /*!< Set up PLL */
284 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
285 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
286 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
287 const pll_setup_t pll0Setup = {
288 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
289 .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
290 .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
291 .pllsscg = {0x0U, (SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
292 .pllRate = 150000000U,
293 .flags = PLL_SETUPFLAG_WAITLOCK};
294 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
295
296 /*!< Set up dividers */
297 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
298
299 /*!< Set up clock selectors - Attach clocks to the peripheries */
300 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
301
302 /*< Set SystemCoreClock variable. */
303 SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
304#endif
305}
306
307/*******************************************************************************
308 ******************* Configuration BOARD_BootClockPLL1_150M ********************
309 ******************************************************************************/
310/* clang-format off */
311/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
312!!Configuration
313name: BOARD_BootClockPLL1_150M
314outputs:
315- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
316- {id: System_clock.outFreq, value: 150 MHz}
317settings:
318- {id: PLL1_Mode, value: Normal}
319- {id: ENABLE_CLKIN_ENA, value: Enabled}
320- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
321- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
322- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
323- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
324- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
325- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
326sources:
327- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
328 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
329/* clang-format on */
330
331/*******************************************************************************
332 * Variables for BOARD_BootClockPLL1_150M configuration
333 ******************************************************************************/
334/*******************************************************************************
335 * Code for BOARD_BootClockPLL1_150M configuration
336 ******************************************************************************/
337void BOARD_BootClockPLL1_150M(void)
338{
339#ifndef SDK_SECONDARY_CORE
340 /*!< Set up the clock sources */
341 /*!< Configure FRO192M */
342 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
343 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
344 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
345
346 /*!< Configure XTAL32M */
347 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
348 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
349 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
350 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
351 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
352
353 POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
354 CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
355
356 /*!< Set up PLL1 */
357 CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */
358 POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */
359 const pll_setup_t pll1Setup = {
360 .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
361 .pllndec = SYSCON_PLL1NDEC_NDIV(8U),
362 .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
363 .pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
364 .pllRate = 150000000U,
365 .flags = PLL_SETUPFLAG_WAITLOCK
366 };
367 CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
368
369 /*!< Set up dividers */
370 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
371
372 /*!< Set up clock selectors - Attach clocks to the peripheries */
373 CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
374
375 /*< Set SystemCoreClock variable. */
376 SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
377#endif
378}
379
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/clock_config.h
new file mode 100644
index 000000000..b9c591c22
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/clock_config.h
@@ -0,0 +1,173 @@
1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _CLOCK_CONFIG_H_
14#define _CLOCK_CONFIG_H_
15
16#include "fsl_common.h"
17
18/*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */
22#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
23
24/*******************************************************************************
25 ************************ BOARD_InitBootClocks function ************************
26 ******************************************************************************/
27
28#if defined(__cplusplus)
29extern "C" {
30#endif /* __cplusplus*/
31
32/*!
33 * @brief This function executes default configuration of clocks.
34 *
35 */
36void BOARD_InitBootClocks(void);
37
38#if defined(__cplusplus)
39}
40#endif /* __cplusplus*/
41
42/*******************************************************************************
43 ******************** Configuration BOARD_BootClockFRO12M **********************
44 ******************************************************************************/
45/*******************************************************************************
46 * Definitions for BOARD_BootClockFRO12M configuration
47 ******************************************************************************/
48#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
49
50
51/*******************************************************************************
52 * API for BOARD_BootClockFRO12M configuration
53 ******************************************************************************/
54#if defined(__cplusplus)
55extern "C" {
56#endif /* __cplusplus*/
57
58/*!
59 * @brief This function executes configuration of clocks.
60 *
61 */
62void BOARD_BootClockFRO12M(void);
63
64#if defined(__cplusplus)
65}
66#endif /* __cplusplus*/
67
68/*******************************************************************************
69 ******************* Configuration BOARD_BootClockFROHF96M *********************
70 ******************************************************************************/
71/*******************************************************************************
72 * Definitions for BOARD_BootClockFROHF96M configuration
73 ******************************************************************************/
74#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
75
76
77/*******************************************************************************
78 * API for BOARD_BootClockFROHF96M configuration
79 ******************************************************************************/
80#if defined(__cplusplus)
81extern "C" {
82#endif /* __cplusplus*/
83
84/*!
85 * @brief This function executes configuration of clocks.
86 *
87 */
88void BOARD_BootClockFROHF96M(void);
89
90#if defined(__cplusplus)
91}
92#endif /* __cplusplus*/
93
94/*******************************************************************************
95 ******************** Configuration BOARD_BootClockPLL100M *********************
96 ******************************************************************************/
97/*******************************************************************************
98 * Definitions for BOARD_BootClockPLL100M configuration
99 ******************************************************************************/
100#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
101
102
103/*******************************************************************************
104 * API for BOARD_BootClockPLL100M configuration
105 ******************************************************************************/
106#if defined(__cplusplus)
107extern "C" {
108#endif /* __cplusplus*/
109
110/*!
111 * @brief This function executes configuration of clocks.
112 *
113 */
114void BOARD_BootClockPLL100M(void);
115
116#if defined(__cplusplus)
117}
118#endif /* __cplusplus*/
119
120/*******************************************************************************
121 ******************** Configuration BOARD_BootClockPLL150M *********************
122 ******************************************************************************/
123/*******************************************************************************
124 * Definitions for BOARD_BootClockPLL150M configuration
125 ******************************************************************************/
126#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
127
128
129/*******************************************************************************
130 * API for BOARD_BootClockPLL150M configuration
131 ******************************************************************************/
132#if defined(__cplusplus)
133extern "C" {
134#endif /* __cplusplus*/
135
136/*!
137 * @brief This function executes configuration of clocks.
138 *
139 */
140void BOARD_BootClockPLL150M(void);
141
142#if defined(__cplusplus)
143}
144#endif /* __cplusplus*/
145
146/*******************************************************************************
147 ******************* Configuration BOARD_BootClockPLL1_150M ********************
148 ******************************************************************************/
149/*******************************************************************************
150 * Definitions for BOARD_BootClockPLL1_150M configuration
151 ******************************************************************************/
152#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
153
154
155/*******************************************************************************
156 * API for BOARD_BootClockPLL1_150M configuration
157 ******************************************************************************/
158#if defined(__cplusplus)
159extern "C" {
160#endif /* __cplusplus*/
161
162/*!
163 * @brief This function executes configuration of clocks.
164 *
165 */
166void BOARD_BootClockPLL1_150M(void);
167
168#if defined(__cplusplus)
169}
170#endif /* __cplusplus*/
171
172#endif /* _CLOCK_CONFIG_H_ */
173
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/board.c
new file mode 100644
index 000000000..4774ebb65
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/board.c
@@ -0,0 +1,122 @@
1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include <stdint.h>
9#include "fsl_common.h"
10#include "fsl_debug_console.h"
11#include "board.h"
12#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
13#include "fsl_i2c.h"
14#endif /* SDK_I2C_BASED_COMPONENT_USED */
15
16/*******************************************************************************
17 * Variables
18 ******************************************************************************/
19
20/*******************************************************************************
21 * Code
22 ******************************************************************************/
23/* Initialize debug console. */
24void BOARD_InitDebugConsole(void)
25{
26 /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
27 CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
28
29 RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
30
31 uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
32
33 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
34}
35
36#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
37void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
38{
39 i2c_master_config_t i2cConfig = {0};
40
41 I2C_MasterGetDefaultConfig(&i2cConfig);
42 I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
43}
44
45status_t BOARD_I2C_Send(I2C_Type *base,
46 uint8_t deviceAddress,
47 uint32_t subAddress,
48 uint8_t subaddressSize,
49 uint8_t *txBuff,
50 uint8_t txBuffSize)
51{
52 i2c_master_transfer_t masterXfer;
53
54 /* Prepare transfer structure. */
55 masterXfer.slaveAddress = deviceAddress;
56 masterXfer.direction = kI2C_Write;
57 masterXfer.subaddress = subAddress;
58 masterXfer.subaddressSize = subaddressSize;
59 masterXfer.data = txBuff;
60 masterXfer.dataSize = txBuffSize;
61 masterXfer.flags = kI2C_TransferDefaultFlag;
62
63 return I2C_MasterTransferBlocking(base, &masterXfer);
64}
65
66status_t BOARD_I2C_Receive(I2C_Type *base,
67 uint8_t deviceAddress,
68 uint32_t subAddress,
69 uint8_t subaddressSize,
70 uint8_t *rxBuff,
71 uint8_t rxBuffSize)
72{
73 i2c_master_transfer_t masterXfer;
74
75 /* Prepare transfer structure. */
76 masterXfer.slaveAddress = deviceAddress;
77 masterXfer.subaddress = subAddress;
78 masterXfer.subaddressSize = subaddressSize;
79 masterXfer.data = rxBuff;
80 masterXfer.dataSize = rxBuffSize;
81 masterXfer.direction = kI2C_Read;
82 masterXfer.flags = kI2C_TransferDefaultFlag;
83
84 return I2C_MasterTransferBlocking(base, &masterXfer);
85}
86
87void BOARD_Accel_I2C_Init(void)
88{
89 BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
90}
91
92status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
93{
94 uint8_t data = (uint8_t)txBuff;
95
96 return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
97}
98
99status_t BOARD_Accel_I2C_Receive(
100 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
101{
102 return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
103}
104
105void BOARD_Codec_I2C_Init(void)
106{
107 BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
108}
109
110status_t BOARD_Codec_I2C_Send(
111 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
112{
113 return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
114 txBuffSize);
115}
116
117status_t BOARD_Codec_I2C_Receive(
118 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
119{
120 return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
121}
122#endif /* SDK_I2C_BASED_COMPONENT_USED */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/board.h
new file mode 100644
index 000000000..1a31bb77a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/board.h
@@ -0,0 +1,252 @@
1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10
11#include "clock_config.h"
12#include "fsl_common.h"
13#include "fsl_reset.h"
14#include "fsl_gpio.h"
15#include "fsl_iocon.h"
16
17/*******************************************************************************
18 * Definitions
19 ******************************************************************************/
20/*! @brief The board name */
21#define BOARD_NAME "LPCXpresso55S16"
22
23/*! @brief The UART to use for debug messages. */
24/* TODO: rename UART to USART */
25#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
26#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0
27#define BOARD_DEBUG_UART_INSTANCE 0U
28#define BOARD_DEBUG_UART_CLK_FREQ 12000000U
29#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
30#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn
31#define BOARD_DEBUG_UART_CLKSRC kCLOCK_Flexcomm0
32#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler
33#define BOARD_UART_IRQ FLEXCOMM0_IRQn
34
35#define BOARD_ACCEL_I2C_BASEADDR I2C4
36#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
37
38#ifndef BOARD_DEBUG_UART_BAUDRATE
39#define BOARD_DEBUG_UART_BAUDRATE 115200U
40#endif /* BOARD_DEBUG_UART_BAUDRATE */
41
42#define BOARD_CODEC_I2C_BASEADDR I2C4
43#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
44#define BOARD_CODEC_I2C_INSTANCE 4
45#ifndef BOARD_LED_RED_GPIO
46#define BOARD_LED_RED_GPIO GPIO
47#endif
48#define BOARD_LED_RED_GPIO_PORT 1U
49#ifndef BOARD_LED_RED_GPIO_PIN
50#define BOARD_LED_RED_GPIO_PIN 4U
51#endif
52
53#ifndef BOARD_LED_BLUE_GPIO
54#define BOARD_LED_BLUE_GPIO GPIO
55#endif
56#define BOARD_LED_BLUE_GPIO_PORT 1U
57#ifndef BOARD_LED_BLUE_GPIO_PIN
58#define BOARD_LED_BLUE_GPIO_PIN 6U
59#endif
60
61#ifndef BOARD_LED_GREEN_GPIO
62#define BOARD_LED_GREEN_GPIO GPIO
63#endif
64#define BOARD_LED_GREEN_GPIO_PORT 1U
65#ifndef BOARD_LED_GREEN_GPIO_PIN
66#define BOARD_LED_GREEN_GPIO_PIN 7U
67#endif
68
69#ifndef BOARD_SW1_GPIO
70#define BOARD_SW1_GPIO GPIO
71#endif
72#define BOARD_SW1_GPIO_PORT 1U
73#ifndef BOARD_SW1_GPIO_PIN
74#define BOARD_SW1_GPIO_PIN 18U
75#endif
76#define BOARD_SW1_NAME "SW1"
77#define BOARD_SW1_IRQ PIN_INT1_IRQn
78#define BOARD_SW1_IRQ_HANDLER PIN_INT1_IRQHandler
79
80#ifndef BOARD_SW3_GPIO
81#define BOARD_SW3_GPIO GPIO
82#endif
83#define BOARD_SW3_GPIO_PORT 1U
84#ifndef BOARD_SW3_GPIO_PIN
85#define BOARD_SW3_GPIO_PIN 9U
86#endif
87#define BOARD_SW3_NAME "SW3"
88#define BOARD_SW3_IRQ PIN_INT1_IRQn
89#define BOARD_SW3_IRQ_HANDLER PIN_INT1_IRQHandler
90#define BOARD_SW3_GPIO_PININT_INDEX 1
91
92#ifndef BOARD_SW4_GPIO
93#define BOARD_SW4_GPIO GPIO
94#endif
95#define BOARD_SW4_GPIO_PORT 0U
96#ifndef BOARD_SW4_GPIO_PIN
97#define BOARD_SW4_GPIO_PIN 5U
98#endif
99#define BOARD_SW4_NAME "SW4"
100#define BOARD_SW4_IRQ PIN_INT0_IRQn
101#define BOARD_SW4_IRQ_HANDLER PIN_INT0_IRQHandler
102#define BOARD_SW4_GPIO_PININT_INDEX 1
103
104#define BOARD_SDIF_BASEADDR SDIF
105#define BOARD_SDIF_CLKSRC kCLOCK_SDio
106#define BOARD_SDIF_CLK_FREQ CLOCK_GetSdioClkFreq()
107#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
108#define BOARD_SDIF_IRQ SDIO_IRQn
109#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
110#define BOARD_SD_CARD_DETECT_PIN 17
111#define BOARD_SD_CARD_DETECT_PORT 0
112#define BOARD_SD_CARD_DETECT_GPIO GPIO
113#define BOARD_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostCD
114
115#define BOARD_SDIF_CD_GPIO_INIT() \
116 { \
117 CLOCK_EnableClock(kCLOCK_Gpio2); \
118 GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \
119 &(gpio_pin_config_t){kGPIO_DigitalInput, 0U}); \
120 }
121#define BOARD_SDIF_CD_STATUS() \
122 GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)
123
124/* Board led color mapping */
125#define LOGIC_LED_ON 1U
126#define LOGIC_LED_OFF 0U
127
128#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
129
130#define LED_RED_INIT(output) \
131 { \
132 IOCON_PinMuxSet(IOCON, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, IOCON_DIGITAL_EN); \
133 GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \
134 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
135 }
136#define LED_RED_OFF() \
137 GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
138 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED1 */
139#define LED_RED_ON() \
140 GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
141 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED1 \ \ \ \ \ \ \ \ \ \ \
142 */
143#define LED_RED_TOGGLE() \
144 GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
145 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED1 */
146
147#define LED_BLUE_INIT(output) \
148 { \
149 IOCON_PinMuxSet(IOCON, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, IOCON_DIGITAL_EN); \
150 GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \
151 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
152 }
153#define LED_BLUE_OFF() \
154 GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
155 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED1 */
156#define LED_BLUE_ON() \
157 GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
158 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED1 */
159#define LED_BLUE_TOGGLE() \
160 GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
161 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED1 */
162
163#define LED_GREEN_INIT(output) \
164 GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
165 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */
166#define LED_GREEN_OFF() \
167 GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
168 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED1 */
169#define LED_GREEN_ON() \
170 GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
171 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED1 */
172#define LED_GREEN_TOGGLE() \
173 GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
174 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED1 */
175
176/*! @brief The WIFI-QCA shield pin. */
177#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO
178#define BOARD_INITGT202SHIELD_PWRON_PORT 1U
179#define BOARD_INITGT202SHIELD_PWRON_PIN 8U
180
181#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO
182#define BOARD_INITGT202SHIELD_IRQ_PORT 1U
183#define BOARD_INITGT202SHIELD_IRQ_PIN 9U
184
185/*! @brief The WIFI-QCA shield pin. */
186#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO
187#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U
188#define BOARD_INITSILEX2401SHIELD_PWRON_PIN 7U
189
190#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO
191#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 0U
192#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 15U
193
194/*! @brief The WIFI-QCA shield pin. */
195#define BOARD_INITWIFI10CLICKSHIELD_PWRON_GPIO GPIO
196#define BOARD_INITWIFI10CLICKSHIELD_PWRON_PORT 1U
197#define BOARD_INITWIFI10CLICKSHIELD_PWRON_PIN 5U
198
199#define BOARD_INITWIFI10CLICKSHIELD_IRQ_GPIO GPIO
200#define BOARD_INITWIFI10CLICKSHIELD_IRQ_PORT 1U
201#define BOARD_INITWIFI10CLICKSHIELD_IRQ_GPIO_PIN 18U
202
203/* Display. */
204#define BOARD_LCD_DC_GPIO GPIO
205#define BOARD_LCD_DC_GPIO_PORT 1U
206#define BOARD_LCD_DC_GPIO_PIN 5U
207
208/* Serial MWM WIFI */
209#define BOARD_SERIAL_MWM_PORT_CLK_FREQ CLOCK_GetFlexCommClkFreq(2)
210#define BOARD_SERIAL_MWM_PORT USART2
211#define BOARD_SERIAL_MWM_PORT_IRQn FLEXCOMM2_IRQn
212#define BOARD_SERIAL_MWM_RST_WRITE(output)
213
214#if defined(__cplusplus)
215extern "C" {
216#endif /* __cplusplus */
217
218/*******************************************************************************
219 * API
220 ******************************************************************************/
221
222void BOARD_InitDebugConsole(void);
223#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
224void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
225status_t BOARD_I2C_Send(I2C_Type *base,
226 uint8_t deviceAddress,
227 uint32_t subAddress,
228 uint8_t subaddressSize,
229 uint8_t *txBuff,
230 uint8_t txBuffSize);
231status_t BOARD_I2C_Receive(I2C_Type *base,
232 uint8_t deviceAddress,
233 uint32_t subAddress,
234 uint8_t subaddressSize,
235 uint8_t *rxBuff,
236 uint8_t rxBuffSize);
237void BOARD_Accel_I2C_Init(void);
238status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
239status_t BOARD_Accel_I2C_Receive(
240 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
241void BOARD_Codec_I2C_Init(void);
242status_t BOARD_Codec_I2C_Send(
243 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
244status_t BOARD_Codec_I2C_Receive(
245 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
246#endif /* SDK_I2C_BASED_COMPONENT_USED */
247
248#if defined(__cplusplus)
249}
250#endif /* __cplusplus */
251
252#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/clock_config.c
new file mode 100644
index 000000000..bb4352e37
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/clock_config.c
@@ -0,0 +1,369 @@
1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12/*
13 * How to set up clock using clock driver functions:
14 *
15 * 1. Setup clock sources.
16 *
17 * 2. Set up wait states of the flash.
18 *
19 * 3. Set up all dividers.
20 *
21 * 4. Set up all selectors to provide selected clocks.
22 */
23
24/* clang-format off */
25/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
26!!GlobalInfo
27product: Clocks v6.0
28processor: LPC55S16
29package_id: LPC55S16JBD100
30mcu_data: ksdk2_0
31processor_version: 0.0.4
32board: LPCXpresso55S16
33 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
34/* clang-format on */
35
36#include "fsl_power.h"
37#include "fsl_clock.h"
38#include "clock_config.h"
39
40/*******************************************************************************
41 * Definitions
42 ******************************************************************************/
43
44/*******************************************************************************
45 * Variables
46 ******************************************************************************/
47/* System clock frequency. */
48extern uint32_t SystemCoreClock;
49
50/*******************************************************************************
51 ************************ BOARD_InitBootClocks function ************************
52 ******************************************************************************/
53void BOARD_InitBootClocks(void)
54{
55 BOARD_BootClockPLL150M();
56}
57
58/*******************************************************************************
59 ******************** Configuration BOARD_BootClockFRO12M **********************
60 ******************************************************************************/
61/* clang-format off */
62/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
63!!Configuration
64name: BOARD_BootClockFRO12M
65outputs:
66- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
67- {id: System_clock.outFreq, value: 12 MHz}
68 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
69/* clang-format on */
70
71/*******************************************************************************
72 * Variables for BOARD_BootClockFRO12M configuration
73 ******************************************************************************/
74/*******************************************************************************
75 * Code for BOARD_BootClockFRO12M configuration
76 ******************************************************************************/
77void BOARD_BootClockFRO12M(void)
78{
79#ifndef SDK_SECONDARY_CORE
80 /*!< Set up the clock sources */
81 /*!< Configure FRO192M */
82 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
83 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
84 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
85
86 POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
87 CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
88
89 /*!< Set up dividers */
90 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
91
92 /*!< Set up clock selectors - Attach clocks to the peripheries */
93 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
94
95 /*< Set SystemCoreClock variable. */
96 SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
97#endif
98}
99
100/*******************************************************************************
101 ******************* Configuration BOARD_BootClockFROHF96M *********************
102 ******************************************************************************/
103/* clang-format off */
104/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
105!!Configuration
106name: BOARD_BootClockFROHF96M
107outputs:
108- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
109- {id: System_clock.outFreq, value: 96 MHz}
110settings:
111- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
112- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
113sources:
114- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
115 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
116/* clang-format on */
117
118/*******************************************************************************
119 * Variables for BOARD_BootClockFROHF96M configuration
120 ******************************************************************************/
121/*******************************************************************************
122 * Code for BOARD_BootClockFROHF96M configuration
123 ******************************************************************************/
124void BOARD_BootClockFROHF96M(void)
125{
126#ifndef SDK_SECONDARY_CORE
127 /*!< Set up the clock sources */
128 /*!< Configure FRO192M */
129 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
130 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
131 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
132
133 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
134
135 POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
136 CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
137
138 /*!< Set up dividers */
139 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
140
141 /*!< Set up clock selectors - Attach clocks to the peripheries */
142 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
143
144 /*< Set SystemCoreClock variable. */
145 SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
146#endif
147}
148
149/*******************************************************************************
150 ******************** Configuration BOARD_BootClockPLL100M *********************
151 ******************************************************************************/
152/* clang-format off */
153/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
154!!Configuration
155name: BOARD_BootClockPLL100M
156outputs:
157- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
158- {id: System_clock.outFreq, value: 100 MHz}
159settings:
160- {id: PLL0_Mode, value: Normal}
161- {id: ENABLE_CLKIN_ENA, value: Enabled}
162- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
163- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
164- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
165- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
166- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
167sources:
168- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
169 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
170/* clang-format on */
171
172/*******************************************************************************
173 * Variables for BOARD_BootClockPLL100M configuration
174 ******************************************************************************/
175/*******************************************************************************
176 * Code for BOARD_BootClockPLL100M configuration
177 ******************************************************************************/
178void BOARD_BootClockPLL100M(void)
179{
180#ifndef SDK_SECONDARY_CORE
181 /*!< Set up the clock sources */
182 /*!< Configure FRO192M */
183 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
184 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
185 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
186
187 /*!< Configure XTAL32M */
188 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
189 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
190 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
191 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
192 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
193
194 POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
195 CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
196
197 /*!< Set up PLL */
198 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
199 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
200 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
201 const pll_setup_t pll0Setup = {
202 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
203 .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
204 .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
205 .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
206 .pllRate = 100000000U,
207 .flags = PLL_SETUPFLAG_WAITLOCK
208 };
209 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
210
211 /*!< Set up dividers */
212 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
213
214 /*!< Set up clock selectors - Attach clocks to the peripheries */
215 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
216
217 /*< Set SystemCoreClock variable. */
218 SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
219#endif
220}
221
222/*******************************************************************************
223 ******************** Configuration BOARD_BootClockPLL150M *********************
224 ******************************************************************************/
225/* clang-format off */
226/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
227!!Configuration
228name: BOARD_BootClockPLL150M
229called_from_default_init: true
230outputs:
231- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
232- {id: System_clock.outFreq, value: 150 MHz}
233settings:
234- {id: PLL0_Mode, value: Normal}
235- {id: ENABLE_CLKIN_ENA, value: Enabled}
236- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
237- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
238- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
239- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
240- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
241- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
242sources:
243- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
244 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
245/* clang-format on */
246
247/*******************************************************************************
248 * Variables for BOARD_BootClockPLL150M configuration
249 ******************************************************************************/
250/*******************************************************************************
251 * Code for BOARD_BootClockPLL150M configuration
252 ******************************************************************************/
253void BOARD_BootClockPLL150M(void)
254{
255#ifndef SDK_SECONDARY_CORE
256 /*!< Set up the clock sources */
257 /*!< Configure FRO192M */
258 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
259 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
260 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
261
262 /*!< Configure XTAL32M */
263 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
264 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
265 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
266 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
267 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
268
269 POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
270 CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
271
272 /*!< Set up PLL */
273 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
274 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
275 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
276 const pll_setup_t pll0Setup = {
277 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
278 .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
279 .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
280 .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
281 .pllRate = 150000000U,
282 .flags = PLL_SETUPFLAG_WAITLOCK
283 };
284 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
285
286 /*!< Set up dividers */
287 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
288
289 /*!< Set up clock selectors - Attach clocks to the peripheries */
290 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
291
292 /*< Set SystemCoreClock variable. */
293 SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
294#endif
295}
296
297/*******************************************************************************
298 ******************* Configuration BOARD_BootClockPLL1_150M ********************
299 ******************************************************************************/
300/* clang-format off */
301/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
302!!Configuration
303name: BOARD_BootClockPLL1_150M
304outputs:
305- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
306- {id: System_clock.outFreq, value: 150 MHz}
307settings:
308- {id: PLL1_Mode, value: Normal}
309- {id: ENABLE_CLKIN_ENA, value: Enabled}
310- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
311- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
312- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
313- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
314- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
315- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
316sources:
317- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
318 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
319/* clang-format on */
320
321/*******************************************************************************
322 * Variables for BOARD_BootClockPLL1_150M configuration
323 ******************************************************************************/
324/*******************************************************************************
325 * Code for BOARD_BootClockPLL1_150M configuration
326 ******************************************************************************/
327void BOARD_BootClockPLL1_150M(void)
328{
329#ifndef SDK_SECONDARY_CORE
330 /*!< Set up the clock sources */
331 /*!< Configure FRO192M */
332 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
333 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
334 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
335
336 /*!< Configure XTAL32M */
337 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
338 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
339 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
340 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
341 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
342
343 POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
344 CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
345
346 /*!< Set up PLL1 */
347 CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */
348 POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */
349 const pll_setup_t pll1Setup = {
350 .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
351 .pllndec = SYSCON_PLL1NDEC_NDIV(8U),
352 .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
353 .pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
354 .pllRate = 150000000U,
355 .flags = PLL_SETUPFLAG_WAITLOCK
356 };
357 CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
358
359 /*!< Set up dividers */
360 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
361
362 /*!< Set up clock selectors - Attach clocks to the peripheries */
363 CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
364
365 /*< Set SystemCoreClock variable. */
366 SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
367#endif
368}
369
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/clock_config.h
new file mode 100644
index 000000000..b9c591c22
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/clock_config.h
@@ -0,0 +1,173 @@
1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _CLOCK_CONFIG_H_
14#define _CLOCK_CONFIG_H_
15
16#include "fsl_common.h"
17
18/*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */
22#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
23
24/*******************************************************************************
25 ************************ BOARD_InitBootClocks function ************************
26 ******************************************************************************/
27
28#if defined(__cplusplus)
29extern "C" {
30#endif /* __cplusplus*/
31
32/*!
33 * @brief This function executes default configuration of clocks.
34 *
35 */
36void BOARD_InitBootClocks(void);
37
38#if defined(__cplusplus)
39}
40#endif /* __cplusplus*/
41
42/*******************************************************************************
43 ******************** Configuration BOARD_BootClockFRO12M **********************
44 ******************************************************************************/
45/*******************************************************************************
46 * Definitions for BOARD_BootClockFRO12M configuration
47 ******************************************************************************/
48#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
49
50
51/*******************************************************************************
52 * API for BOARD_BootClockFRO12M configuration
53 ******************************************************************************/
54#if defined(__cplusplus)
55extern "C" {
56#endif /* __cplusplus*/
57
58/*!
59 * @brief This function executes configuration of clocks.
60 *
61 */
62void BOARD_BootClockFRO12M(void);
63
64#if defined(__cplusplus)
65}
66#endif /* __cplusplus*/
67
68/*******************************************************************************
69 ******************* Configuration BOARD_BootClockFROHF96M *********************
70 ******************************************************************************/
71/*******************************************************************************
72 * Definitions for BOARD_BootClockFROHF96M configuration
73 ******************************************************************************/
74#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
75
76
77/*******************************************************************************
78 * API for BOARD_BootClockFROHF96M configuration
79 ******************************************************************************/
80#if defined(__cplusplus)
81extern "C" {
82#endif /* __cplusplus*/
83
84/*!
85 * @brief This function executes configuration of clocks.
86 *
87 */
88void BOARD_BootClockFROHF96M(void);
89
90#if defined(__cplusplus)
91}
92#endif /* __cplusplus*/
93
94/*******************************************************************************
95 ******************** Configuration BOARD_BootClockPLL100M *********************
96 ******************************************************************************/
97/*******************************************************************************
98 * Definitions for BOARD_BootClockPLL100M configuration
99 ******************************************************************************/
100#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
101
102
103/*******************************************************************************
104 * API for BOARD_BootClockPLL100M configuration
105 ******************************************************************************/
106#if defined(__cplusplus)
107extern "C" {
108#endif /* __cplusplus*/
109
110/*!
111 * @brief This function executes configuration of clocks.
112 *
113 */
114void BOARD_BootClockPLL100M(void);
115
116#if defined(__cplusplus)
117}
118#endif /* __cplusplus*/
119
120/*******************************************************************************
121 ******************** Configuration BOARD_BootClockPLL150M *********************
122 ******************************************************************************/
123/*******************************************************************************
124 * Definitions for BOARD_BootClockPLL150M configuration
125 ******************************************************************************/
126#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
127
128
129/*******************************************************************************
130 * API for BOARD_BootClockPLL150M configuration
131 ******************************************************************************/
132#if defined(__cplusplus)
133extern "C" {
134#endif /* __cplusplus*/
135
136/*!
137 * @brief This function executes configuration of clocks.
138 *
139 */
140void BOARD_BootClockPLL150M(void);
141
142#if defined(__cplusplus)
143}
144#endif /* __cplusplus*/
145
146/*******************************************************************************
147 ******************* Configuration BOARD_BootClockPLL1_150M ********************
148 ******************************************************************************/
149/*******************************************************************************
150 * Definitions for BOARD_BootClockPLL1_150M configuration
151 ******************************************************************************/
152#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
153
154
155/*******************************************************************************
156 * API for BOARD_BootClockPLL1_150M configuration
157 ******************************************************************************/
158#if defined(__cplusplus)
159extern "C" {
160#endif /* __cplusplus*/
161
162/*!
163 * @brief This function executes configuration of clocks.
164 *
165 */
166void BOARD_BootClockPLL1_150M(void);
167
168#if defined(__cplusplus)
169}
170#endif /* __cplusplus*/
171
172#endif /* _CLOCK_CONFIG_H_ */
173
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/peripherals.c b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/peripherals.c
new file mode 100644
index 000000000..69af4a74c
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/peripherals.c
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
9!!GlobalInfo
10product: Peripherals v1.0
11 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
12
13/*******************************************************************************
14 * Included files
15 ******************************************************************************/
16#include "peripherals.h"
17
18/*******************************************************************************
19 * BOARD_InitBootPeripherals function
20 ******************************************************************************/
21void BOARD_InitBootPeripherals(void)
22{
23}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/peripherals.h b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/peripherals.h
new file mode 100644
index 000000000..36b2e05a7
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/peripherals.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _PERIPHERALS_H_
9#define _PERIPHERALS_H_
10
11#if defined(__cplusplus)
12extern "C" {
13#endif /*_cplusplus. */
14/*******************************************************************************
15 * BOARD_InitBootPeripherals function
16 ******************************************************************************/
17void BOARD_InitBootPeripherals(void);
18
19#if defined(__cplusplus)
20}
21#endif /*_cplusplus. */
22
23#endif /* _PERIPHERALS_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/pin_mux.c
new file mode 100644
index 000000000..0179264b3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/pin_mux.c
@@ -0,0 +1,99 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/* clang-format off */
14/*
15 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
16!!GlobalInfo
17product: Pins v8.0
18processor: LPC55S16
19package_id: LPC55S16JBD100
20mcu_data: ksdk2_0
21processor_version: 0.8.6
22 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
23 */
24/* clang-format on */
25
26#include "fsl_common.h"
27#include "fsl_iocon.h"
28#include "pin_mux.h"
29
30/* FUNCTION ************************************************************************************************************
31 *
32 * Function Name : BOARD_InitBootPins
33 * Description : Calls initialization functions.
34 *
35 * END ****************************************************************************************************************/
36void BOARD_InitBootPins(void)
37{
38 BOARD_InitPins();
39}
40
41/* clang-format off */
42/*
43 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
44BOARD_InitPins:
45- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
46- pin_list:
47 - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
48 mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
49 - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
50 slew_rate: standard, invert: disabled, open_drain: disabled}
51 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
52 */
53/* clang-format on */
54
55/* FUNCTION ************************************************************************************************************
56 *
57 * Function Name : BOARD_InitPins
58 * Description : Configures pin routing and optionally pin electrical features.
59 *
60 * END ****************************************************************************************************************/
61/* Function assigned for the Cortex-M33 */
62void BOARD_InitPins(void)
63{
64 /* Enables the clock for the I/O controller.: Enable Clock. */
65 CLOCK_EnableClock(kCLOCK_Iocon);
66
67 const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
68 IOCON_PIO_FUNC1 |
69 /* No addition pin function */
70 IOCON_PIO_MODE_INACT |
71 /* Standard mode, output slew rate control is enabled */
72 IOCON_PIO_SLEW_STANDARD |
73 /* Input function is not inverted */
74 IOCON_PIO_INV_DI |
75 /* Enables digital function */
76 IOCON_PIO_DIGITAL_EN |
77 /* Open drain is disabled */
78 IOCON_PIO_OPENDRAIN_DI);
79 /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
80 IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
81
82 const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
83 IOCON_PIO_FUNC1 |
84 /* No addition pin function */
85 IOCON_PIO_MODE_INACT |
86 /* Standard mode, output slew rate control is enabled */
87 IOCON_PIO_SLEW_STANDARD |
88 /* Input function is not inverted */
89 IOCON_PIO_INV_DI |
90 /* Enables digital function */
91 IOCON_PIO_DIGITAL_EN |
92 /* Open drain is disabled */
93 IOCON_PIO_OPENDRAIN_DI);
94 /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
95 IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
96}
97/***********************************************************************************************************************
98 * EOF
99 **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/pin_mux.h b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/pin_mux.h
new file mode 100644
index 000000000..bf3e2e409
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/lpcxpresso55s16/project_template/pin_mux.h
@@ -0,0 +1,59 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PIN_MUX_H_
14#define _PIN_MUX_H_
15
16/*!
17 * @addtogroup pin_mux
18 * @{
19 */
20
21/***********************************************************************************************************************
22 * API
23 **********************************************************************************************************************/
24
25#if defined(__cplusplus)
26extern "C" {
27#endif
28
29/*!
30 * @brief Calls initialization functions.
31 *
32 */
33void BOARD_InitBootPins(void);
34
35#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
36#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */
37#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
38#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */
39#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
40#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
41
42/*!
43 * @brief Configures pin routing and optionally pin electrical features.
44 *
45 */
46void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
47
48#if defined(__cplusplus)
49}
50#endif
51
52/*!
53 * @}
54 */
55#endif /* _PIN_MUX_H_ */
56
57/***********************************************************************************************************************
58 * EOF
59 **********************************************************************************************************************/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 13:24:04 +0100