1 files changed, 324 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/twrkm35z75m/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/twrkm35z75m/clock_config.c
new file mode 100644
index 000000000..4270c0c5c
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/twrkm35z75m/clock_config.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ *    internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ *    1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ *    2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ *        correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ *        explicitly to setup MCGIRCLK.
+ *
+ *    3). Don't need to configure FLL explicitly, because if target mode is FLL
+ *        mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ *        if the target mode is not FLL mode, the FLL is disabled.
+ *
+ *    4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ *        setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ *        be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: MKM35Z512xxx7
+package_id: MKM35Z512VLQ7
+mcu_data: ksdk2_0
+processor_version: 0.0.1
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+#include "fsl_smc.h"
+#include "fsl_irtc.h"
+#include "clock_config.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define IRTC_OSC_CAP0P                                    0U  /*!< RTC oscillator 0pF capacitor load */
+#define MCG_PLL_DISABLE                                   0U  /*!< MCGPLLCLK disabled */
+#define OSC_CAP0P                                         0U  /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE                                0U  /*!< Disable external reference clock */
+#define SIM_OSC32KSEL_OSC32KCLK_CLK                       0U  /*!< OSC32KSEL select: OSC32KCLK clock */
+#define SIM_PLLFLLSEL_MCGFLLCLK_CLK                       0U  /*!< PLLFLL select: MCGFLLCLK clock */
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_FllStableDelay
+ * Description   : This function is used to delay for FLL stable.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_FllStableDelay(void)
+{
+    uint32_t i = 30000U;
+    while (i--)
+    {
+        __NOP();
+    }
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_EnableRtcOsc
+ * Description   : This function is used to configuring RTC oscillator 
+ * Param capLoad : RTC oscillator capacity load
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_EnableRtcOsc(uint32_t capLoad)
+{
+    /* Wait RTC POR finished before accessing RTC registers. */
+    while (!(SIM->MISC_CTL & SIM_MISC_CTL_RTC_OSC32K_INIT_MASK))
+    {
+    }
+    if ((RTC->GP_DATA_REG & 0x01U) != 0U) { /* Only if the Rtc oscillator is not already enabled */
+        /* Set the specified capacitor configuration for the RTC oscillator */
+        IRTC_SetOscCapLoad(RTC, capLoad);
+        /* Enable the RTC 32KHz oscillator */
+        RTC->GP_DATA_REG &= ~0x01U;
+    }
+}
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 71.991296/3 MHz}
+- {id: Core_clock.outFreq, value: 71.991296 MHz}
+- {id: Flash_clock.outFreq, value: 71.991296/3 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
+- {id: OSC32KSELCLK.outFreq, value: 32.768 kHz}
+- {id: OSCERCLK.outFreq, value: 8 MHz}
+- {id: PLLFLLCLK.outFreq, value: 71.991296 MHz}
+- {id: System_clock.outFreq, value: 71.991296 MHz}
+settings:
+- {id: MCGMode, value: FEE}
+- {id: MCG.CLKS.sel, value: MCG.PLLS}
+- {id: MCG.FCRDIV.scale, value: '1', locked: true}
+- {id: MCG.FLL_mul.scale, value: '2197', locked: true}
+- {id: MCG.IRCS.sel, value: MCG.SLOW_IRCLK}
+- {id: MCG.IREFS.sel, value: MCG.FRDIV}
+- {id: MCG.OSCSEL.sel, value: SIM.RTC32KCLK}
+- {id: MCG.PLL32KREFSEL.sel, value: MCG.FRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: High}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+- {id: SIM.ADCTRGSEL.sel, value: SIM.ADC_asynchronous_clk}
+- {id: SIM.AFECLKSEL.sel, value: MCG.MCGFLLCLK}
+- {id: SIM.CLKDIVBUS.scale, value: '3', locked: true}
+- {id: SIM.CLKDIVSYS.scale, value: '1', locked: true}
+- {id: SIM.CLKOUTSEL.sel, value: PMC.LPOCLK}
+- {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
+- {id: SIM.RTCCLKSEL.sel, value: MCG.MCGIRCLK}
+- {id: SIM.XBARCLKOUTSEL.sel, value: PMC.LPOCLK}
+- {id: XBARCLKOUTConfig, value: 'no'}
+sources:
+- {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
+- {id: RTC.OSC32kHz.outFreq, value: 32.768 kHz, enabled: true}
+- {id: SIM.ADC_asynchronous_clk.outFreq, value: 1.255 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN =
+    {
+        .mcgMode = kMCG_ModeFEE,                  /* FEE - FLL Engaged External */
+        .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCG_IrcSlow,                     /* Slow internal reference clock selected */
+        .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 1 */
+        .drs = kMCG_DrsMidHigh,                   /* Mid-High frequency range */
+        .dmx32 = kMCG_Dmx32Fine,                  /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
+        .oscsel = kMCG_OscselRtc,                 /* Selects 32 kHz RTC Oscillator */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .refSrc = kMCG_PllRefFllRef,      /* Selects FLL reference clock, the clock after FRDIV */
+                .frdiv = 0x0U,                    /* FLL reference clock divider: divided by 1 */
+            },
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockRUN =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
+        .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
+        .clkdiv1 = 0x2000000U,                    /* SIM_CLKDIV1 - CLKDIVSYS: /1, CLKDIVBUS: /3, FLASHCLKMODE: /1 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockRUN =
+    {
+        .freq = 8000000U,                         /* Oscillator frequency: 8000000Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = kOSC_ErClkEnable,   /* Enable external reference clock, disable external reference clock in STOP mode */
+            }
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Use RTC_CLKIN input clock directly. */
+    CLOCK_SetXtal32Freq(32768U);
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Enable RTC oscillator. */
+    CLOCK_CONFIG_EnableRtcOsc((IRTC_OSC_CAP0P));
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
+    /* Set MCG to FEE mode. */
+    CLOCK_BootToFeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
+                        mcgConfig_BOARD_BootClockRUN.frdiv,
+                        mcgConfig_BOARD_BootClockRUN.dmx32,
+                        mcgConfig_BOARD_BootClockRUN.drs,
+                        CLOCK_CONFIG_FllStableDelay);
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
+                                  mcgConfig_BOARD_BootClockRUN.ircs, 
+                                  mcgConfig_BOARD_BootClockRUN.fcrdiv);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 1 MHz}
+- {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
+- {id: Flash_clock.outFreq, value: 1 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 4 MHz}
+- {id: System_clock.outFreq, value: 4 MHz}
+settings:
+- {id: powerMode, value: VLPR}
+- {id: MCG.FCRDIV.scale, value: '1'}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: High}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
+- {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC18PF}
+- {id: SIM.CLKDIVBUS.scale, value: '4'}
+sources:
+- {id: OSC.OSC.outFreq, value: 8 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
+    {
+        .mcgMode = kMCG_ModeBLPI,                 /* BLPI - Bypassed Low Power Internal */
+        .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCG_IrcFast,                     /* Fast internal reference clock selected */
+        .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 32 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .oscsel = kMCG_OscselOsc,                 /* Selects System Oscillator (OSCCLK) */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .refSrc = kMCG_PllRefRtc,         /* Selects 32k RTC oscillator */
+                .frdiv = 0x0U,                    /* FLL reference clock divider: divided by 32 */
+            },
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
+        .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
+        .clkdiv1 = 0x3000000U,                    /* SIM_CLKDIV1 - CLKDIVSYS: /1, CLKDIVBUS: /4, FLASHCLKMODE: /1 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockVLPR =
+    {
+        .freq = 0U,                               /* Oscillator frequency: 0Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+            }
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to BLPI mode. */
+    CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
+                         mcgConfig_BOARD_BootClockVLPR.ircs,
+                         mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    SMC_SetPowerModeVlpr(SMC, false);
+#else
+    SMC_SetPowerModeVlpr(SMC);
+#endif
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+}

diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/twrkm35z75m/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/twrkm35z75m/clock_config.c new file mode 100644 index 000000000..4270c0c5c --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/boards/twrkm35z75m/clock_config.c
@@ -0,0 +1,324 @@
	1	/*
	2	* Copyright 2019 NXP
	3	*
	4	* SPDX-License-Identifier: BSD-3-Clause
	5	*/
	6
	7	/***********************************************************************************************************************
	8	* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
	9	* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
	10	**********************************************************************************************************************/
	11	/*
	12	* How to setup clock using clock driver functions:
	13	*
	14	* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
	15	* and flash clock are in allowed range during clock mode switch.
	16	*
	17	* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
	18	*
	19	* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
	20	* internal reference clock(MCGIRCLK). Follow the steps to setup:
	21	*
	22	* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
	23	*
	24	* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
	25	* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
	26	* explicitly to setup MCGIRCLK.
	27	*
	28	* 3). Don't need to configure FLL explicitly, because if target mode is FLL
	29	* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
	30	* if the target mode is not FLL mode, the FLL is disabled.
	31	*
	32	* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
	33	* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
	34	* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
	35	*
	36	* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
	37	*/
	38
	39	/* clang-format off */
	40	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	41	!!GlobalInfo
	42	product: Clocks v7.0
	43	processor: MKM35Z512xxx7
	44	package_id: MKM35Z512VLQ7
	45	mcu_data: ksdk2_0
	46	processor_version: 0.0.1
	47	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	48	/* clang-format on */
	49
	50	#include "fsl_smc.h"
	51	#include "fsl_irtc.h"
	52	#include "clock_config.h"
	53
	54	/*******************************************************************************
	55	* Definitions
	56	******************************************************************************/
	57	#define IRTC_OSC_CAP0P 0U /!< RTC oscillator 0pF capacitor load /
	58	#define MCG_PLL_DISABLE 0U /!< MCGPLLCLK disabled /
	59	#define OSC_CAP0P 0U /!< Oscillator 0pF capacitor load /
	60	#define OSC_ER_CLK_DISABLE 0U /!< Disable external reference clock /
	61	#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /!< OSC32KSEL select: OSC32KCLK clock /
	62	#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /!< PLLFLL select: MCGFLLCLK clock /
	63
	64	/*******************************************************************************
	65	* Variables
	66	******************************************************************************/
	67	/* System clock frequency. */
	68	extern uint32_t SystemCoreClock;
	69
	70	/*******************************************************************************
	71	* Code
	72	******************************************************************************/
	73	/FUNCTION*********************************************************************
	74	*
	75	* Function Name : CLOCK_CONFIG_FllStableDelay
	76	* Description : This function is used to delay for FLL stable.
	77	*
	78	END*************************************************************************/
	79	static void CLOCK_CONFIG_FllStableDelay(void)
	80	{
	81	uint32_t i = 30000U;
	82	while (i--)
	83	{
	84	__NOP();
	85	}
	86	}
	87
	88	/FUNCTION*********************************************************************
	89	*
	90	* Function Name : CLOCK_CONFIG_EnableRtcOsc
	91	* Description : This function is used to configuring RTC oscillator
	92	* Param capLoad : RTC oscillator capacity load
	93	*
	94	END*************************************************************************/
	95	static void CLOCK_CONFIG_EnableRtcOsc(uint32_t capLoad)
	96	{
	97	/* Wait RTC POR finished before accessing RTC registers. */
	98	while (!(SIM->MISC_CTL & SIM_MISC_CTL_RTC_OSC32K_INIT_MASK))
	99	{
	100	}
	101	if ((RTC->GP_DATA_REG & 0x01U) != 0U) { /* Only if the Rtc oscillator is not already enabled */
	102	/* Set the specified capacitor configuration for the RTC oscillator */
	103	IRTC_SetOscCapLoad(RTC, capLoad);
	104	/* Enable the RTC 32KHz oscillator */
	105	RTC->GP_DATA_REG &= ~0x01U;
	106	}
	107	}
	108
	109	/*******************************************************************************
	110	********************** BOARD_InitBootClocks function **********************
	111	******************************************************************************/
	112	void BOARD_InitBootClocks(void)
	113	{
	114	BOARD_BootClockRUN();
	115	}
	116
	117	/*******************************************************************************
	118	******************** Configuration BOARD_BootClockRUN *********************
	119	******************************************************************************/
	120	/* clang-format off */
	121	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	122	!!Configuration
	123	name: BOARD_BootClockRUN
	124	called_from_default_init: true
	125	outputs:
	126	- {id: Bus_clock.outFreq, value: 71.991296/3 MHz}
	127	- {id: Core_clock.outFreq, value: 71.991296 MHz}
	128	- {id: Flash_clock.outFreq, value: 71.991296/3 MHz}
	129	- {id: LPO_clock.outFreq, value: 1 kHz}
	130	- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
	131	- {id: OSC32KSELCLK.outFreq, value: 32.768 kHz}
	132	- {id: OSCERCLK.outFreq, value: 8 MHz}
	133	- {id: PLLFLLCLK.outFreq, value: 71.991296 MHz}
	134	- {id: System_clock.outFreq, value: 71.991296 MHz}
	135	settings:
	136	- {id: MCGMode, value: FEE}
	137	- {id: MCG.CLKS.sel, value: MCG.PLLS}
	138	- {id: MCG.FCRDIV.scale, value: '1', locked: true}
	139	- {id: MCG.FLL_mul.scale, value: '2197', locked: true}
	140	- {id: MCG.IRCS.sel, value: MCG.SLOW_IRCLK}
	141	- {id: MCG.IREFS.sel, value: MCG.FRDIV}
	142	- {id: MCG.OSCSEL.sel, value: SIM.RTC32KCLK}
	143	- {id: MCG.PLL32KREFSEL.sel, value: MCG.FRDIV}
	144	- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
	145	- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
	146	- {id: MCG_C2_RANGE0_CFG, value: High}
	147	- {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
	148	- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
	149	- {id: SIM.ADCTRGSEL.sel, value: SIM.ADC_asynchronous_clk}
	150	- {id: SIM.AFECLKSEL.sel, value: MCG.MCGFLLCLK}
	151	- {id: SIM.CLKDIVBUS.scale, value: '3', locked: true}
	152	- {id: SIM.CLKDIVSYS.scale, value: '1', locked: true}
	153	- {id: SIM.CLKOUTSEL.sel, value: PMC.LPOCLK}
	154	- {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
	155	- {id: SIM.RTCCLKSEL.sel, value: MCG.MCGIRCLK}
	156	- {id: SIM.XBARCLKOUTSEL.sel, value: PMC.LPOCLK}
	157	- {id: XBARCLKOUTConfig, value: 'no'}
	158	sources:
	159	- {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
	160	- {id: RTC.OSC32kHz.outFreq, value: 32.768 kHz, enabled: true}
	161	- {id: SIM.ADC_asynchronous_clk.outFreq, value: 1.255 MHz}
	162	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	163	/* clang-format on */
	164
	165	/*******************************************************************************
	166	* Variables for BOARD_BootClockRUN configuration
	167	******************************************************************************/
	168	const mcg_config_t mcgConfig_BOARD_BootClockRUN =
	169	{
	170	.mcgMode = kMCG_ModeFEE, /* FEE - FLL Engaged External */
	171	.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	172	.ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
	173	.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
	174	.frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
	175	.drs = kMCG_DrsMidHigh, /* Mid-High frequency range */
	176	.dmx32 = kMCG_Dmx32Fine, /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
	177	.oscsel = kMCG_OscselRtc, /* Selects 32 kHz RTC Oscillator */
	178	.pll0Config =
	179	{
	180	.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
	181	.refSrc = kMCG_PllRefFllRef, /* Selects FLL reference clock, the clock after FRDIV */
	182	.frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
	183	},
	184	};
	185	const sim_clock_config_t simConfig_BOARD_BootClockRUN =
	186	{
	187	.pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
	188	.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
	189	.clkdiv1 = 0x2000000U, /* SIM_CLKDIV1 - CLKDIVSYS: /1, CLKDIVBUS: /3, FLASHCLKMODE: /1 */
	190	};
	191	const osc_config_t oscConfig_BOARD_BootClockRUN =
	192	{
	193	.freq = 8000000U, /* Oscillator frequency: 8000000Hz */
	194	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	195	.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
	196	.oscerConfig =
	197	{
	198	.enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
	199	}
	200	};
	201
	202	/*******************************************************************************
	203	* Code for BOARD_BootClockRUN configuration
	204	******************************************************************************/
	205	void BOARD_BootClockRUN(void)
	206	{
	207	/* Use RTC_CLKIN input clock directly. */
	208	CLOCK_SetXtal32Freq(32768U);
	209	/* Set the system clock dividers in SIM to safe value. */
	210	CLOCK_SetSimSafeDivs();
	211	/* Enable RTC oscillator. */
	212	CLOCK_CONFIG_EnableRtcOsc((IRTC_OSC_CAP0P));
	213	/* Initializes OSC0 according to board configuration. */
	214	CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
	215	CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
	216	/* Set MCG to FEE mode. */
	217	CLOCK_BootToFeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
	218	mcgConfig_BOARD_BootClockRUN.frdiv,
	219	mcgConfig_BOARD_BootClockRUN.dmx32,
	220	mcgConfig_BOARD_BootClockRUN.drs,
	221	CLOCK_CONFIG_FllStableDelay);
	222	/* Configure the Internal Reference clock (MCGIRCLK). */
	223	CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
	224	mcgConfig_BOARD_BootClockRUN.ircs,
	225	mcgConfig_BOARD_BootClockRUN.fcrdiv);
	226	/* Set the clock configuration in SIM module. */
	227	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
	228	/* Set SystemCoreClock variable. */
	229	SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
	230	}
	231
	232	/*******************************************************************************
	233	******************* Configuration BOARD_BootClockVLPR *********************
	234	******************************************************************************/
	235	/* clang-format off */
	236	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	237	!!Configuration
	238	name: BOARD_BootClockVLPR
	239	outputs:
	240	- {id: Bus_clock.outFreq, value: 1 MHz}
	241	- {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
	242	- {id: Flash_clock.outFreq, value: 1 MHz}
	243	- {id: LPO_clock.outFreq, value: 1 kHz}
	244	- {id: MCGIRCLK.outFreq, value: 4 MHz}
	245	- {id: System_clock.outFreq, value: 4 MHz}
	246	settings:
	247	- {id: powerMode, value: VLPR}
	248	- {id: MCG.FCRDIV.scale, value: '1'}
	249	- {id: MCG.FRDIV.scale, value: '32'}
	250	- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
	251	- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
	252	- {id: MCG_C2_RANGE0_CFG, value: High}
	253	- {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
	254	- {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC18PF}
	255	- {id: SIM.CLKDIVBUS.scale, value: '4'}
	256	sources:
	257	- {id: OSC.OSC.outFreq, value: 8 MHz}
	258	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	259	/* clang-format on */
	260
	261	/*******************************************************************************
	262	* Variables for BOARD_BootClockVLPR configuration
	263	******************************************************************************/
	264	const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
	265	{
	266	.mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
	267	.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	268	.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
	269	.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
	270	.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
	271	.drs = kMCG_DrsLow, /* Low frequency range */
	272	.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
	273	.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
	274	.pll0Config =
	275	{
	276	.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
	277	.refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
	278	.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
	279	},
	280	};
	281	const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
	282	{
	283	.pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
	284	.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
	285	.clkdiv1 = 0x3000000U, /* SIM_CLKDIV1 - CLKDIVSYS: /1, CLKDIVBUS: /4, FLASHCLKMODE: /1 */
	286	};
	287	const osc_config_t oscConfig_BOARD_BootClockVLPR =
	288	{
	289	.freq = 0U, /* Oscillator frequency: 0Hz */
	290	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	291	.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
	292	.oscerConfig =
	293	{
	294	.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
	295	}
	296	};
	297
	298	/*******************************************************************************
	299	* Code for BOARD_BootClockVLPR configuration
	300	******************************************************************************/
	301	void BOARD_BootClockVLPR(void)
	302	{
	303	/* Set the system clock dividers in SIM to safe value. */
	304	CLOCK_SetSimSafeDivs();
	305	/* Set MCG to BLPI mode. */
	306	CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
	307	mcgConfig_BOARD_BootClockVLPR.ircs,
	308	mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
	309	/* Set the clock configuration in SIM module. */
	310	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
	311	/* Set VLPR power mode. */
	312	SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
	313	#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
	314	SMC_SetPowerModeVlpr(SMC, false);
	315	#else
	316	SMC_SetPowerModeVlpr(SMC);
	317	#endif
	318	while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
	319	{
	320	}
	321	/* Set SystemCoreClock variable. */
	322	SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
	323	}
	324