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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/components/codec/ak4497/driver_ak4497.cmake17
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/components/codec/ak4497/fsl_ak4497.c394
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/components/codec/ak4497/fsl_ak4497.h447
3 files changed, 858 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/components/codec/ak4497/driver_ak4497.cmake b/lib/chibios-contrib/ext/mcux-sdk/components/codec/ak4497/driver_ak4497.cmake
new file mode 100644
index 000000000..f4edcec65
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/components/codec/ak4497/driver_ak4497.cmake
@@ -0,0 +1,17 @@
1if(NOT DRIVER_AK4497_INCLUDED)
2
3 set(DRIVER_AK4497_INCLUDED true CACHE BOOL "driver_ak4497 component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 ${CMAKE_CURRENT_LIST_DIR}/fsl_ak4497.c
7 )
8
9 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
10 ${CMAKE_CURRENT_LIST_DIR}/.
11 )
12
13
14 include(driver_common)
15 include(component_codec_i2c_MIMX8MM6)
16
17endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/components/codec/ak4497/fsl_ak4497.c b/lib/chibios-contrib/ext/mcux-sdk/components/codec/ak4497/fsl_ak4497.c
new file mode 100644
index 000000000..8ecb23d72
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/components/codec/ak4497/fsl_ak4497.c
@@ -0,0 +1,394 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_ak4497.h"
9
10/*******************************************************************************
11 * Definitions
12 ******************************************************************************/
13
14/*******************************************************************************
15 * Prototypes
16 ******************************************************************************/
17
18/*******************************************************************************
19 * Variables
20 ******************************************************************************/
21
22/*******************************************************************************
23 * Code
24 ******************************************************************************/
25static void Delay(void)
26{
27 uint32_t i;
28 for (i = 0; i < 1000U; i++)
29 {
30 __NOP();
31 }
32}
33
34void AK4497_DefaultConfig(ak4497_config_t *config)
35{
36 config->ak4497Mode = kAK4497_PcmMode;
37 config->dataChannelMode = kAK4497_NormalMode;
38 /* PCM mode setting. */
39 config->pcmConfig.pcmSampleFreqMode = kAK4497_AutoSettingMode;
40 config->pcmConfig.pcmSdataFormat = kAK4497_32BitI2S;
41 config->pcmConfig.pcmTdmMode = kAK4497_Normal;
42 config->pcmConfig.pcmSdsSlot = kAK4497_L1R1;
43 /* DSD mode setting. */
44 config->dsdConfig.dsdMclk = kAK4497_mclk512fs;
45 config->dsdConfig.dsdPath = kAK4497_Path1;
46 config->dsdConfig.dsdPlaybackPath = kAK4497_NormalPath;
47 config->dsdConfig.dsdDataMute = kAK4497_DsdMuteDisable;
48 config->dsdConfig.dsdDclkPolarity = kAK4497_FallingEdge;
49}
50
51status_t AK4497_Init(ak4497_handle_t *handle, ak4497_config_t *config)
52{
53 assert(handle != NULL);
54 assert(config != NULL);
55 status_t ret = kStatus_Success;
56
57 handle->config = config;
58
59 /* i2c bus initialization */
60 if (CODEC_I2C_Init(handle->i2cHandle, config->i2cConfig.codecI2CInstance, AK4497_I2C_BITRATE,
61 config->i2cConfig.codecI2CSourceClock) != (status_t)kStatus_HAL_I2cSuccess)
62 {
63 return kStatus_Fail;
64 }
65
66 ret = AK4497_ModifyReg(handle, AK4497_CONTROL2, AK4497_CONTROL2_SMUTE_MASK,
67 1U << AK4497_CONTROL2_SMUTE_SHIFT); /* Soft ware mute */
68
69 ret = AK4497_ModifyReg(handle, AK4497_CONTROL1,
70 AK4497_CONTROL1_DIF0_MASK | AK4497_CONTROL1_DIF1_MASK | AK4497_CONTROL1_DIF2_MASK,
71 (uint8_t)config->pcmConfig.pcmSdataFormat << AK4497_CONTROL1_DIF0_SHIFT);
72 ret = AK4497_ModifyReg(handle, AK4497_CONTROL3, AK4497_CONTROL3_SELLR_MASK,
73 (uint8_t)config->dataChannelMode << AK4497_CONTROL3_SELLR_SHIFT);
74 if (config->ak4497Mode == kAK4497_PcmMode) /* PCM mode*/
75 {
76 if (config->pcmConfig.pcmSampleFreqMode != kAK4497_ManualSettingMode)
77 {
78 if (config->pcmConfig.pcmSampleFreqMode == kAK4497_AutoSettingMode)
79 {
80 ret = AK4497_ModifyReg(handle, AK4497_CONTROL1, AK4497_CONTROL1_AFSD_MASK,
81 0U << AK4497_CONTROL1_AFSD_SHIFT); /*Auto setting mode*/
82 ret = AK4497_ModifyReg(handle, AK4497_CONTROL1, AK4497_CONTROL1_ACKS_MASK,
83 1U << AK4497_CONTROL1_ACKS_SHIFT);
84 }
85 else
86 {
87 ret = AK4497_ModifyReg(handle, AK4497_CONTROL1, AK4497_CONTROL1_AFSD_MASK,
88 1U << AK4497_CONTROL1_AFSD_SHIFT); /* Auto Detect mode*/
89 ret = AK4497_ModifyReg(handle, AK4497_CONTROL1, AK4497_CONTROL1_ACKS_MASK,
90 0U << AK4497_CONTROL1_ACKS_SHIFT);
91 }
92 }
93 ret = AK4497_ModifyReg(handle, AK4497_CONTROL7, AK4497_CONTROL7_TDM0_MASK | AK4497_CONTROL7_TDM1_MASK,
94 (uint8_t)config->pcmConfig.pcmTdmMode << AK4497_CONTROL7_TDM0_SHIFT);
95 ret = AK4497_ModifyReg(handle, AK4497_CONTROL8, AK4497_CONTROL8_SDS0_MASK,
96 ((uint8_t)config->pcmConfig.pcmSdsSlot & 0x1U) << AK4497_CONTROL8_SDS0_SHIFT);
97 ret = AK4497_ModifyReg(handle, AK4497_CONTROL7, AK4497_CONTROL7_SDS1_MASK,
98 (((uint8_t)config->pcmConfig.pcmSdsSlot & 0x2U) >> 1U) << AK4497_CONTROL7_SDS1_SHIFT);
99 ret = AK4497_ModifyReg(handle, AK4497_CONTROL7, AK4497_CONTROL7_SDS2_MASK,
100 (((uint8_t)config->pcmConfig.pcmSdsSlot & 0x4U) >> 2U) << AK4497_CONTROL7_SDS2_SHIFT);
101 }
102
103 else if (config->ak4497Mode == kAK4497_DsdMode) /*DSD mode*/
104 {
105 ret = AK4497_ModifyReg(handle, AK4497_CONTROL1, AK4497_CONTROL1_EXDF_MASK, 0U << AK4497_CONTROL1_EXDF_SHIFT);
106 ret = AK4497_ModifyReg(handle, AK4497_CONTROL3, AK4497_CONTROL3_DP_MASK, 1U << AK4497_CONTROL3_DP_SHIFT);
107 ret = AK4497_ModifyReg(handle, AK4497_CONTROL3, AK4497_CONTROL3_DCKS_MASK,
108 (uint8_t)config->dsdConfig.dsdMclk << AK4497_CONTROL3_DCKS_SHIFT);
109 ret = AK4497_ModifyReg(handle, AK4497_DSD2, AK4497_DSD2_DSDPATH_MASK,
110 (uint8_t)config->dsdConfig.dsdPath << AK4497_DSD2_DSDPATH_SHIFT);
111 ret = AK4497_ModifyReg(handle, AK4497_DSD1, AK4497_DSD1_DSDD_MASK,
112 (uint8_t)config->dsdConfig.dsdPlaybackPath << AK4497_DSD1_DSDD_SHIFT);
113 ret = AK4497_ModifyReg(handle, AK4497_DSD1, AK4497_DSD1_DDM_MASK,
114 (uint8_t)config->dsdConfig.dsdDataMute << AK4497_DSD1_DDM_SHIFT);
115 ret = AK4497_ModifyReg(handle, AK4497_CONTROL3, AK4497_CONTROL3_DCKB_MASK,
116 (uint8_t)config->dsdConfig.dsdDclkPolarity << AK4497_CONTROL3_DCKB_SHIFT);
117 }
118 else /* EXDF mode*/
119 {
120 ret = AK4497_ModifyReg(handle, AK4497_CONTROL1, AK4497_CONTROL1_EXDF_MASK, 1U << AK4497_CONTROL1_EXDF_SHIFT);
121 ret = AK4497_ModifyReg(handle, AK4497_CONTROL3, AK4497_CONTROL3_DP_MASK, 0U << AK4497_CONTROL3_DP_SHIFT);
122 }
123
124 ret = AK4497_ModifyReg(handle, AK4497_CONTROL2, AK4497_CONTROL2_SMUTE_MASK,
125 0U << AK4497_CONTROL2_SMUTE_SHIFT); /* Normal Operation */
126
127 ret = AK4497_ModifyReg(handle, AK4497_CONTROL1, AK4497_CONTROL1_RSTN_MASK,
128 0U << AK4497_CONTROL1_RSTN_SHIFT); /* Rest the ak4497 */
129 Delay(); /* Need to wait to ensure the ak4497 has updated the above registers. */
130 ret = AK4497_ModifyReg(handle, AK4497_CONTROL1, AK4497_CONTROL1_RSTN_MASK,
131 1U << AK4497_CONTROL1_RSTN_SHIFT); /* Normal Operation */
132 Delay();
133
134 return ret;
135}
136
137status_t AK4497_SetEncoding(ak4497_handle_t *handle, uint8_t format)
138{
139 ak4497_config_t *config = (ak4497_config_t *)handle->config;
140 status_t ret = kStatus_Success;
141
142 if (format == (uint8_t)kAK4497_DsdMode)
143 {
144 ret = AK4497_ModifyReg(handle, AK4497_CONTROL1, AK4497_CONTROL1_EXDF_MASK, 0U << AK4497_CONTROL1_EXDF_SHIFT);
145 ret = AK4497_ModifyReg(handle, AK4497_CONTROL3, AK4497_CONTROL3_DP_MASK, 1U << AK4497_CONTROL3_DP_SHIFT);
146 ret = AK4497_ModifyReg(handle, AK4497_CONTROL3, AK4497_CONTROL3_DCKS_MASK,
147 (uint8_t)config->dsdConfig.dsdMclk << AK4497_CONTROL3_DCKS_SHIFT);
148 ret = AK4497_ModifyReg(handle, AK4497_DSD2, AK4497_DSD2_DSDPATH_MASK,
149 (uint8_t)config->dsdConfig.dsdPath << AK4497_DSD2_DSDPATH_SHIFT);
150 ret = AK4497_ModifyReg(handle, AK4497_DSD1, AK4497_DSD1_DSDD_MASK,
151 (uint8_t)config->dsdConfig.dsdPlaybackPath << AK4497_DSD1_DSDD_SHIFT);
152 ret = AK4497_ModifyReg(handle, AK4497_DSD1, AK4497_DSD1_DDM_MASK,
153 (uint8_t)config->dsdConfig.dsdDataMute << AK4497_DSD1_DDM_SHIFT);
154 ret = AK4497_ModifyReg(handle, AK4497_CONTROL3, AK4497_CONTROL3_DCKB_MASK,
155 (uint8_t)config->dsdConfig.dsdDclkPolarity << AK4497_CONTROL3_DCKB_SHIFT);
156 config->ak4497Mode = kAK4497_DsdMode;
157 }
158
159 if (format == (uint8_t)kAK4497_PcmMode)
160 {
161 ret = AK4497_ModifyReg(handle, AK4497_CONTROL7, AK4497_CONTROL7_TDM0_MASK | AK4497_CONTROL7_TDM1_MASK,
162 (uint8_t)config->pcmConfig.pcmTdmMode << AK4497_CONTROL7_TDM0_SHIFT);
163 ret = AK4497_ModifyReg(handle, AK4497_CONTROL8, AK4497_CONTROL8_SDS0_MASK,
164 ((uint8_t)config->pcmConfig.pcmSdsSlot & 0x1U) << AK4497_CONTROL8_SDS0_SHIFT);
165 ret = AK4497_ModifyReg(handle, AK4497_CONTROL7, AK4497_CONTROL7_SDS1_MASK,
166 (((uint8_t)config->pcmConfig.pcmSdsSlot & 0x2U) >> 1U) << AK4497_CONTROL7_SDS1_SHIFT);
167 ret = AK4497_ModifyReg(handle, AK4497_CONTROL7, AK4497_CONTROL7_SDS2_MASK,
168 (((uint8_t)config->pcmConfig.pcmSdsSlot & 0x4U) >> 2U) << AK4497_CONTROL7_SDS2_SHIFT);
169 ret = AK4497_ModifyReg(handle, AK4497_CONTROL1, AK4497_CONTROL1_EXDF_MASK, 0U << AK4497_CONTROL1_EXDF_SHIFT);
170 ret = AK4497_ModifyReg(handle, AK4497_CONTROL3, AK4497_CONTROL3_DP_MASK, 0U << AK4497_CONTROL3_DP_SHIFT);
171
172 config->ak4497Mode = kAK4497_PcmMode;
173 }
174
175 return ret;
176}
177
178status_t AK4497_ConfigDataFormat(ak4497_handle_t *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth)
179{
180 ak4497_pcm_samplefreqselect_t samplefreq;
181 ak4497_dsd_dclk_t dsdsel;
182 ak4497_pcm_sdata_format_t sdataFormat;
183 ak4497_config_t *config = (ak4497_config_t *)handle->config;
184 status_t ret = kStatus_Success;
185
186 if (config->ak4497Mode == kAK4497_DsdMode)
187 {
188 switch (sampleRate * bitWidth)
189 {
190 case 2048000U:
191 case 2822400U:
192 case 3072000U:
193 dsdsel = kAK4497_dclk64fs;
194 break;
195 case 4096000U:
196 case 5644800U:
197 case 6144000U:
198 dsdsel = kAK4497_dclk128fs;
199 break;
200 case 8192000U:
201 case 11289600U:
202 case 12288000U:
203 dsdsel = kAK4497_dclk256fs;
204 break;
205 case 16284000U:
206 case 22579200U:
207 case 24576000U:
208 dsdsel = kAK4497_dclk512fs;
209 break;
210 default:
211 ret = kStatus_Fail;
212 break;
213 }
214
215 if (ret != kStatus_Success)
216 {
217 return ret;
218 }
219
220 ret = AK4497_ModifyReg(handle, AK4497_DSD1, AK4497_DSD1_DSDSEL0_MASK,
221 ((uint8_t)dsdsel & 0x1U) << AK4497_DSD1_DSDSEL0_SHIFT); /* Set DSDSEL0 */
222 ret = AK4497_ModifyReg(handle, AK4497_DSD2, AK4497_DSD2_DSDSEL1_MASK,
223 (((uint8_t)dsdsel & 0x2U) >> 1U) << AK4497_DSD2_DSDSEL1_SHIFT); /* Set DSDSEL1 */
224 }
225 else /* PCM mode */
226 {
227 switch (sampleRate)
228 {
229 case 8000U:
230 case 11025U:
231 case 16000U:
232 case 22050U:
233 case 32000U:
234 case 44100U:
235 case 48000U:
236 samplefreq = kAK4497_NormalSpeed;
237 break;
238 case 88200U:
239 case 96000U:
240 samplefreq = kAK4497_DoubleSpeed;
241 break;
242 case 176400U:
243 case 192000U:
244 samplefreq = kAK4497_QuadSpeed;
245 break;
246 case 352800U:
247 case 384000U:
248 samplefreq = kAK4497_OctSpeed;
249 break;
250 case 705600U:
251 case 768000U:
252 samplefreq = kAK4497_HexSpeed;
253 break;
254 default:
255 ret = kStatus_Fail;
256 break;
257 }
258
259 if (ret != kStatus_Success)
260 {
261 return ret;
262 }
263
264 switch (bitWidth)
265 {
266 /* For PCM, only strero mode supported. */
267 case 16U:
268 case 24U:
269 sdataFormat = kAK4497_16_24BitI2S;
270 break;
271 case 32U:
272 sdataFormat = kAK4497_32BitI2S;
273 break;
274 default:
275 ret = kStatus_Fail;
276 break;
277 }
278
279 if (ret != kStatus_Success)
280 {
281 return ret;
282 }
283
284 ret = AK4497_ModifyReg(handle, AK4497_CONTROL2, AK4497_CONTROL2_DFS0_MASK | AK4497_CONTROL2_DFS1_MASK,
285 ((uint8_t)samplefreq & 0x3U) << AK4497_CONTROL2_DFS0_SHIFT); /* Set DFS[1:0] */
286 ret = AK4497_ModifyReg(handle, AK4497_CONTROL4, AK4497_CONTROL4_DFS2_MASK | AK4497_CONTROL4_DFS2_MASK,
287 (((uint8_t)samplefreq & 0x4U) >> 2U) << AK4497_CONTROL4_DFS2_SHIFT); /* Set DFS[2] */
288 ret = AK4497_ModifyReg(handle, AK4497_CONTROL1,
289 AK4497_CONTROL1_DIF0_MASK | AK4497_CONTROL1_DIF1_MASK | AK4497_CONTROL1_DIF2_MASK,
290 (uint8_t)sdataFormat << AK4497_CONTROL1_DIF0_SHIFT);
291 }
292
293 ret = AK4497_ModifyReg(handle, AK4497_CONTROL1, AK4497_CONTROL1_RSTN_MASK,
294 0U << AK4497_CONTROL1_RSTN_SHIFT); /* Rest the ak4497 */
295
296 Delay();
297
298 ret = AK4497_ModifyReg(handle, AK4497_CONTROL1, AK4497_CONTROL1_RSTN_MASK,
299 1U << AK4497_CONTROL1_RSTN_SHIFT); /* Normal Operation */
300 Delay();
301
302 return ret;
303}
304
305status_t AK4497_SetVolume(ak4497_handle_t *handle, uint8_t value)
306{
307 status_t retval = kStatus_Success;
308 /*
309 * 255 levels, 0.5dB setp + mute (value = 0)
310 */
311 retval = AK4497_WriteReg(handle, AK4497_LCHATT, value);
312 retval = AK4497_WriteReg(handle, AK4497_RCHATT, value);
313
314 return retval;
315}
316
317status_t AK4497_GetVolume(ak4497_handle_t *handle, uint8_t *value)
318{
319 status_t retval = kStatus_Success;
320 /*
321 * 255 levels, 0.5dB setp + mute (value = 0);
322 * R-channel volume regarded the same as the L-channel, here just read the L-channel value.
323 */
324 retval = AK4497_ReadReg(handle, AK4497_LCHATT, value);
325
326 return retval;
327}
328
329status_t AK4497_Deinit(ak4497_handle_t *handle)
330{
331 status_t ret = kStatus_Success;
332
333 ret = AK4497_ModifyReg(handle, AK4497_CONTROL2, AK4497_CONTROL2_SMUTE_MASK,
334 1U << AK4497_CONTROL2_SMUTE_SHIFT); /* Soft ware mute */
335
336 ret = CODEC_I2C_Deinit(handle->i2cHandle);
337
338 return ret;
339}
340
341status_t AK4497_ModuleControl(ak4497_handle_t *handle, ak4497_module_ctrl_cmd_t cmd, uint32_t data)
342{
343 status_t ret = kStatus_Success;
344
345 if (cmd == kAK4497_ModuleSwitchI2SInInterface)
346 {
347 ret = AK4497_SetEncoding(handle, (uint8_t)data);
348 }
349 else
350 {
351 ret = kStatus_InvalidArgument;
352 }
353
354 return ret;
355}
356
357status_t AK4497_WriteReg(ak4497_handle_t *handle, uint8_t reg, uint8_t val)
358{
359 assert(handle->config != NULL);
360 assert(handle->config->slaveAddress != 0U);
361
362 Delay(); /* Ensure the Codec I2C bus free before writing the slave. */
363
364 return CODEC_I2C_Send(handle->i2cHandle, handle->config->slaveAddress, reg, 1U, (uint8_t *)&val, 1U);
365}
366
367status_t AK4497_ReadReg(ak4497_handle_t *handle, uint8_t reg, uint8_t *val)
368{
369 assert(handle->config != NULL);
370 assert(handle->config->slaveAddress != 0U);
371
372 Delay(); /* Ensure the Codec I2C bus free before reading the slave. */
373
374 return CODEC_I2C_Receive(handle->i2cHandle, handle->config->slaveAddress, reg, 1U, val, 1U);
375}
376
377status_t AK4497_ModifyReg(ak4497_handle_t *handle, uint8_t reg, uint8_t mask, uint8_t val)
378{
379 status_t retval = kStatus_Success;
380 uint8_t reg_val = 0;
381 retval = AK4497_ReadReg(handle, reg, &reg_val);
382 if (retval != kStatus_Success)
383 {
384 return kStatus_Fail;
385 }
386 reg_val &= (uint8_t)~mask;
387 reg_val |= val;
388 retval = AK4497_WriteReg(handle, reg, reg_val);
389 if (retval != kStatus_Success)
390 {
391 return kStatus_Fail;
392 }
393 return kStatus_Success;
394}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/components/codec/ak4497/fsl_ak4497.h b/lib/chibios-contrib/ext/mcux-sdk/components/codec/ak4497/fsl_ak4497.h
new file mode 100644
index 000000000..fc5a28b76
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/components/codec/ak4497/fsl_ak4497.h
@@ -0,0 +1,447 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_AK4497_H_
9#define _FSL_AK4497_H_
10
11#include "fsl_common.h"
12#include "fsl_codec_i2c.h"
13/*!
14 * @addtogroup ak4497
15 * @{
16 */
17
18/*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21/*! @name Driver version */
22/*@{*/
23/*! @brief CLOCK driver version 2.1.2 */
24#define FSL_AK4497_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
25/*@}*/
26
27/*! @brief ak4497 handle size */
28#ifndef AK4497_I2C_HANDLER_SIZE
29#define AK4497_I2C_HANDLER_SIZE CODEC_I2C_MASTER_HANDLER_SIZE
30#endif
31
32/*! @brief define the registers offset of AK4497. */
33#define AK4497_CONTROL1 (0x00U)
34#define AK4497_CONTROL2 (0x01U)
35#define AK4497_CONTROL3 (0x02U)
36#define AK4497_LCHATT (0x03U)
37#define AK4497_RCHATT (0x04U)
38#define AK4497_CONTROL4 (0x05U)
39#define AK4497_DSD1 (0x06U)
40#define AK4497_CONTROL5 (0x07U)
41#define AK4497_SOUNDCONTROL (0x08U)
42#define AK4497_DSD2 (0x09U)
43#define AK4497_CONTROL7 (0x0AU)
44#define AK4497_CONTROL8 (0x0BU)
45#define AK4497_DFSREAD (0x15U)
46/*! @brief define BIT info of AK4497. */
47#define AK4497_CONTROL1_RSTN_MASK (0x1U)
48#define AK4497_CONTROL1_RSTN_SHIFT (0U)
49#define AK4497_CONTROL1_DIF0_MASK (0x2U)
50#define AK4497_CONTROL1_DIF0_SHIFT (1U)
51#define AK4497_CONTROL1_DIF1_MASK (0x4U)
52#define AK4497_CONTROL1_DIF1_SHIFT (2U)
53#define AK4497_CONTROL1_DIF2_MASK (0x8U)
54#define AK4497_CONTROL1_DIF2_SHIFT (3U)
55#define AK4497_CONTROL1_AFSD_MASK (0x10U)
56#define AK4497_CONTROL1_AFSD_SHIFT (4U)
57#define AK4497_CONTROL1_ECS_MASK (0x20U)
58#define AK4497_CONTROL1_ECS_SHIFT (5U)
59#define AK4497_CONTROL1_EXDF_MASK (0x40U)
60#define AK4497_CONTROL1_EXDF_SHIFT (6U)
61#define AK4497_CONTROL1_ACKS_MASK (0x80U)
62#define AK4497_CONTROL1_ACKS_SHIFT (7U)
63
64#define AK4497_CONTROL2_SMUTE_MASK (0x1U)
65#define AK4497_CONTROL2_SMUTE_SHIFT (0U)
66#define AK4497_CONTROL2_DEM0_MASK (0x2U)
67#define AK4497_CONTROL2_DEM0_SHIFT (1U)
68#define AK4497_CONTROL2_DEM1_MASK (0x4U)
69#define AK4497_CONTROL2_DEM1_SHIFT (2U)
70#define AK4497_CONTROL2_DFS0_MASK (0x8U)
71#define AK4497_CONTROL2_DFS0_SHIFT (3U)
72#define AK4497_CONTROL2_DFS1_MASK (0x10U)
73#define AK4497_CONTROL2_DFS1_SHIFT (4U)
74#define AK4497_CONTROL2_SD_MASK (0x20U)
75#define AK4497_CONTROL2_SD_SHIFT (5U)
76#define AK4497_CONTROL2_DZFM_MASK (0x40U)
77#define AK4497_CONTROL2_DZFM_SHIFT (6U)
78#define AK4497_CONTROL2_DZFE_MASK (0x80U)
79#define AK4497_CONTROL2_DZFE_SHIFT (7U)
80
81#define AK4497_CONTROL3_SLOW_MASK (0x1U)
82#define AK4497_CONTROL3_SLOW_SHIFT (0U)
83#define AK4497_CONTROL3_SELLR_MASK (0x2U)
84#define AK4497_CONTROL3_SELLR_SHIFT (1U)
85#define AK4497_CONTROL3_DZFB_MASK (0x4U)
86#define AK4497_CONTROL3_DZFB_SHIFT (2U)
87#define AK4497_CONTROL3_MONO_MASK (0x8U)
88#define AK4497_CONTROL3_MONO_SHIFT (3U)
89#define AK4497_CONTROL3_DCKB_MASK (0x10U)
90#define AK4497_CONTROL3_DCKB_SHIFT (4U)
91#define AK4497_CONTROL3_DCKS_MASK (0x20U)
92#define AK4497_CONTROL3_DCKS_SHIFT (5U)
93#define AK4497_CONTROL3_DP_MASK (0x80U)
94#define AK4497_CONTROL3_DP_SHIFT (7U)
95
96#define AK4497_CONTROL4_SSLOW_MASK (0x1U)
97#define AK4497_CONTROL4_SSLOW_SHIFT (0U)
98#define AK4497_CONTROL4_DFS2_MASK (0x2U)
99#define AK4497_CONTROL4_DFS2_SHIFT (1U)
100#define AK4497_CONTROL4_INVR_MASK (0x40U)
101#define AK4497_CONTROL4_INVR_SHIFT (6U)
102#define AK4497_CONTROL4_INVL_MASK (0x80U)
103#define AK4497_CONTROL4_INVL_SHIFT (7U)
104
105#define AK4497_DSD1_DSDSEL0_MASK (0x1U)
106#define AK4497_DSD1_DSDSEL0_SHIFT (0U)
107#define AK4497_DSD1_DSDD_MASK (0x2U)
108#define AK4497_DSD1_DSDD_SHIFT (1U)
109#define AK4497_DSD1_DMRE_MASK (0x8U)
110#define AK4497_DSD1_DMRE_SHIFT (3U)
111#define AK4497_DSD1_DMC_MASK (0x10U)
112#define AK4497_DSD1_DMC_SHIFT (4U)
113#define AK4497_DSD1_DMR_MASK (0x20U)
114#define AK4497_DSD1_DMR_SHIFT (5U)
115#define AK4497_DSD1_DML_MASK (0x40U)
116#define AK4497_DSD1_DML_SHIFT (6U)
117#define AK4497_DSD1_DDM_MASK (0x80U)
118#define AK4497_DSD1_DDM_SHIFT (7U)
119
120#define AK4497_CONTROL5_SYNCE_MASK (0x1U)
121#define AK4497_CONTROL5_SYNCE_SHIFT (0U)
122#define AK4497_CONTROL5_GC0_MASK (0x2U)
123#define AK4497_CONTROL5_GC0_SHIFT (1U)
124#define AK4497_CONTROL5_GC1_MASK (0x4U)
125#define AK4497_CONTROL5_GC1_SHIFT (2U)
126#define AK4497_CONTROL5_GC2_MASK (0x8U)
127#define AK4497_CONTROL5_GC2_SHIFT (3U)
128
129#define AK4497_SOUNDCONTROL_SC0_MASK (0x1U)
130#define AK4497_SOUNDCONTROL_SC0_SHIFT (0U)
131#define AK4497_SOUNDCONTROL_SC1_MASK (0x2U)
132#define AK4497_SOUNDCONTROL_SC1_SHIFT (1U)
133#define AK4497_SOUNDCONTROL_SC2_MASK (0x4U)
134#define AK4497_SOUNDCONTROL_SC2_SHIFT (2U)
135#define AK4497_SOUNDCONTROL_HLOAD_MASK (0x8U)
136#define AK4497_SOUNDCONTROL_HLOAD_SHIFT (3U)
137
138#define AK4497_DSD2_DSDSEL1_MASK (0x1U)
139#define AK4497_DSD2_DSDSEL1_SHIFT (0U)
140#define AK4497_DSD2_DSDF_MASK (0x2U)
141#define AK4497_DSD2_DSDF_SHIFT (1U)
142#define AK4497_DSD2_DSDPATH_MASK (0x4U)
143#define AK4497_DSD2_DSDPATH_SHIFT (2U)
144
145#define AK4497_CONTROL7_PW_MASK (0x4U)
146#define AK4497_CONTROL7_PW_SHIFT (2U)
147#define AK4497_CONTROL7_SDS2_MASK (0x10U)
148#define AK4497_CONTROL7_SDS2_SHIFT (4U)
149#define AK4497_CONTROL7_SDS1_MASK (0x20U)
150#define AK4497_CONTROL7_SDS1_SHIFT (5U)
151#define AK4497_CONTROL7_TDM0_MASK (0x40U)
152#define AK4497_CONTROL7_TDM0_SHIFT (6U)
153#define AK4497_CONTROL7_TDM1_MASK (0x80U)
154#define AK4497_CONTROL7_TDM1_SHIFT (7U)
155
156#define AK4497_CONTROL8_TSET_MASK (0x1U)
157#define AK4497_CONTROL8_TSET_SHIFT (0U)
158#define AK4497_CONTROL8_DCHAIN_MASK (0x2U)
159#define AK4497_CONTROL8_DCHAIN_SHIFT (1U)
160#define AK4497_CONTROL8_SDS0_MASK (0x10U)
161#define AK4497_CONTROL8_SDS0_SHIFT (4U)
162#define AK4497_CONTROL8_ATS0_MASK (0x40U)
163#define AK4497_CONTROL8_ATS0_SHIFT (6U)
164#define AK4497_CONTROL8_ATS1_MASK (0x80U)
165#define AK4497_CONTROL8_ATS1_SHIFT (7U)
166
167/*! @brief AK4497 I2C address. */
168#define AK4497_I2C_ADDR (0x11U)
169/*! @brief AK4497 i2c baudrate */
170#define AK4497_I2C_BITRATE (100000U)
171/*! @brief The AK4497 playback mode */
172typedef enum _ak4497_mode
173{
174 kAK4497_PcmMode = 0x0,
175 kAK4497_DsdMode = 0x1,
176 kAK4497_ExdfMode = 0x2,
177} ak4497_mode_t;
178
179/*! @brief The Data selection of L-channel and R-channel for DSD mode, defined by SELLR bit */
180typedef enum _ak4497_data_channel_mode
181{
182 kAK4497_NormalMode = 0x0, /*!< L-channel output L-channel data, R-channel output R-channel data. */
183 kAK4497_ExchangeMode = 0x1, /*!< L-channel output R-channel data, R-channel output L-channel data. */
184} ak4497_data_channel_mode_t;
185
186/*! @brief The data path select for DSD mode */
187typedef enum _ak4497_dsd_input_path
188{
189 kAK4497_Path0 = 0x0, /*!< Pin 16,17,19 used. */
190 kAK4497_Path1 = 0x1, /*!< Pin 3,4,5 used. */
191} ak4497_dsd_input_path_t;
192
193/*! @brief The MCLK select for DSD mode, defined by DCKS bit */
194typedef enum _ak4497_dsd_mclk
195{
196 kAK4497_mclk512fs = 0x0, /*!< MCLK equals 512fs. */
197 kAK4497_mclk768fs = 0x1, /*!< MCLK equals 768fs. */
198} ak4497_dsd_mclk_t;
199
200/*! @brief The DCLK select for DSD mode, defined by DSDSEL[1:0] */
201typedef enum _ak4497_dsd_dclk
202{
203 kAK4497_dclk64fs = 0x0, /*!< DCLK equals 64fs. */
204 kAK4497_dclk128fs = 0x1, /*!< DCLK equals 128fs. */
205 kAK4497_dclk256fs = 0x2, /*!< DCLK equals 256fs. */
206 kAK4497_dclk512fs = 0x3, /*!< DCLK equals 512fs. */
207} ak4497_dsd_dclk_t;
208
209/*! @brief DSD playback path */
210typedef enum _ak4497_dsd_playback_path
211{
212 kAK4497_NormalPath = 0x0, /*!< Normal path mode. */
213 kAK4497_VolumeBypass = 0x1, /*!< Volume Bypass mode. */
214} ak4497_dsd_playback_path_t;
215
216/*! @brief DSD mute flag */
217typedef enum _ak4497_dsd_data_mute
218{
219 kAK4497_DsdMuteDisable = 0x0,
220 kAK4497_DsdMuteEnable = 0x1,
221} ak4497_dsd_data_mute_t;
222
223/*! @brief DSD bclk polarity */
224typedef enum _ak4497_dsd_dclk_polarity
225{
226 kAK4497_FallingEdge = 0x0, /*!< DSD data is output from DCLK falling edge. */
227 kAK4497_RisingEdge = 0x1, /*!< DSD data is output from DCLK rising edge. */
228} ak4497_dsd_dclk_polarity_t;
229/*! @brief The sampling frequency mode for PCM and EXDF mode, defined by CR01[AFSD], CR00[ACKS]*/
230typedef enum _ak4497_pcm_samplefreqmode
231{
232 kAK4497_ManualSettingMode = 0x0, /*!< Manual setting mode */
233 kAK4497_AutoSettingMode = 0x1, /*!< Auto setting mode */
234 kAK4497_FsAutoDetectMode = 0x2, /*!< Auto detect mode */
235} ak4497_pcm_samplefreqmode_t;
236/*! @brief The sampling speed select, defined by DFS[2:0]*/
237typedef enum _ak4497_pcm_samplefreqselect
238{
239 kAK4497_NormalSpeed = 0x0, /*!< 8kHZ ~ 54kHZ */
240 kAK4497_DoubleSpeed = 0x1, /*!< 54kHZ ~ 108kHZ */
241 kAK4497_QuadSpeed = 0x2, /*!< 120kHZ ~ 216kHZ, note that value 3 also stands for Quad Speed Mode */
242 kAK4497_OctSpeed = 0x4, /*!< 384kHZ, note that value 6 also stands for Oct Speed Mode */
243 kAK4497_HexSpeed = 0x5, /*!< 768kHZ, note that value 7 also stands for Hex Speed Mode */
244} ak4497_pcm_samplefreqselect_t;
245
246/*! @brief The audio data interface modes, defined by DIF[2:0]*/
247typedef enum _ak4497_pcm_sdata_format
248{
249 kAK4497_16BitLSB = 0x0, /*!< 16-bit LSB justified */
250 kAK4497_20BitLSB = 0x1, /*!< 20-bit LSB justified */
251 kAK4497_24BitMSB = 0x2, /*!< 24-bit MSB justified */
252 kAK4497_16_24BitI2S = 0x3, /*!< 16 and 24-bit I2S compatible */
253 kAK4497_24BitLSB = 0x4, /*!< 24-bit LSB justified */
254 kAK4497_32BitLSB = 0x5, /*!< 32-bit LSB justified */
255 kAK4497_32BitMSB = 0x6, /*!< 32-bit MSB justified */
256 kAK4497_32BitI2S = 0x7, /*!< 32-bit I2S compatible */
257} ak4497_pcm_sdata_format_t;
258
259/*! @brief The TDM mode select, defined by TDM[1:0]*/
260typedef enum _ak4497_pcm_tdm_mode
261{
262 kAK4497_Normal = 0x0, /*!< Normal mode */
263 kAK4497_TDM128 = 0x1, /*!< BCLK is fixed to 128fs */
264 kAK4497_TDM256 = 0x2, /*!< BCLK is fixed to 256fs */
265 kAK4497_TDM512 = 0x3, /*!< BCLK is fixed to 512fs */
266} ak4497_pcm_tdm_mode_t;
267
268/*! @brief The audio data slot selection, defined by SDS[2:0]*/
269typedef enum _ak4497_pcm_sds_select
270{
271 kAK4497_L1R1 = 0x0,
272 kAK4497_L2R2 = 0x1,
273 kAK4497_L3R3 = 0x2,
274 kAK4497_L4R4 = 0x3,
275 kAK4497_L5R5 = 0x4,
276 kAK4497_L6R6 = 0x5,
277 kAK4497_L7R7 = 0x6,
278 kAK4497_L8R8 = 0x7,
279} ak4497_pcm_sds_select_t;
280
281/*! @brief audio codec module control cmd */
282typedef enum _ak4497_module_ctrl_cmd
283{
284 kAK4497_ModuleSwitchI2SInInterface = 0U, /*!< module digital interface siwtch. */
285} ak4497_module_ctrl_cmd_t;
286
287/*! @brief audio codec module digital interface
288 * @anchor _ak4497_module_ctrl_i2s_in_interface
289 */
290enum
291{
292 kAK4497_ModuleI2SInInterfacePCM = 0U, /*!< Pcm interface*/
293 kAK4497_ModuleI2SInInterfaceDSD = 1U, /*!< DSD interface */
294};
295
296/*! @brief Initialize DSD mode structure of AK4497 */
297typedef struct _ak4497_dsd_config
298{
299 ak4497_dsd_input_path_t dsdPath;
300 ak4497_dsd_mclk_t dsdMclk;
301 ak4497_dsd_playback_path_t dsdPlaybackPath;
302 ak4497_dsd_data_mute_t dsdDataMute;
303 ak4497_dsd_dclk_polarity_t dsdDclkPolarity;
304} ak4497_dsd_config_t;
305
306/*! @brief Initialize PCM mode structure of AK4497 */
307typedef struct _ak4497_pcm_config
308{
309 ak4497_pcm_samplefreqmode_t pcmSampleFreqMode;
310 ak4497_pcm_sdata_format_t pcmSdataFormat;
311 ak4497_pcm_tdm_mode_t pcmTdmMode;
312 ak4497_pcm_sds_select_t pcmSdsSlot;
313} ak4497_pcm_config_t;
314
315/*! @brief Initialize structure of AK4497 */
316typedef struct _ak4497_config
317{
318 ak4497_mode_t ak4497Mode;
319 ak4497_data_channel_mode_t dataChannelMode;
320 ak4497_pcm_config_t pcmConfig;
321 ak4497_dsd_config_t dsdConfig;
322
323 uint8_t slaveAddress; /*!< code device slave address */
324 codec_i2c_config_t i2cConfig; /*!< i2c bus configuration */
325} ak4497_config_t;
326
327/*! @brief ak4497 codec handler
328 */
329typedef struct _ak4497_handle
330{
331 ak4497_config_t *config; /*!< ak4497 config pointer */
332 uint8_t i2cHandle[AK4497_I2C_HANDLER_SIZE]; /*!< i2c handle */
333} ak4497_handle_t;
334
335/*******************************************************************************
336 * API
337 ******************************************************************************/
338#if defined(__cplusplus)
339extern "C" {
340#endif
341
342/*!
343 * @brief Default initializes AK4497.
344 *
345 * @param config AK4497 configure structure.
346 */
347void AK4497_DefaultConfig(ak4497_config_t *config);
348/*!
349 * @brief Initializes AK4497.
350 *
351 * @param handle AK4497 handle structure.
352 * @param config AK4497 configure structure.
353 */
354status_t AK4497_Init(ak4497_handle_t *handle, ak4497_config_t *config);
355/*!
356 * @brief Set the codec PCM mode or DSD mode based on the format info
357 *
358 * This function would configure the codec playback mode.
359 *
360 * @param handle AK4497 handle structure pointer.
361 * @param format info.
362 */
363status_t AK4497_SetEncoding(ak4497_handle_t *handle, uint8_t format);
364/*!
365 * @brief Configure the data format of audio data.
366 *
367 * This function would configure the registers about the sample rate, bit depths.
368 *
369 * @param handle AK4497 handle structure pointer.
370 * @param mclk system clock of the codec which can be generated by MCLK or PLL output.
371 * @param sampleRate Sample rate of audio file running in AK4497.
372 * @param bitWidth Bit depth of audio file.
373 */
374status_t AK4497_ConfigDataFormat(ak4497_handle_t *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth);
375
376/*!
377 * @brief Set the volume of different modules in AK4497.
378 *
379 * This function would set the volume of AK4497 modules. Users need to appoint the module.
380 * The function assume that left channel and right channel has the same volume.
381 *
382 * @param handle AK4497 handle structure.
383 * @param value Volume value need to be set.
384 */
385status_t AK4497_SetVolume(ak4497_handle_t *handle, uint8_t value);
386
387/*!
388 * @brief Get the volume of different modules in AK4497.
389 *
390 * This function gets the volume of AK4497. Users need to appoint the module.
391 * The function assume that left channel and right channel has the same volume.
392 *
393 * @param handle AK4497 handle structure.
394 * @param value volume value
395 * @return value value of the module.
396 */
397status_t AK4497_GetVolume(ak4497_handle_t *handle, uint8_t *value);
398
399/*!
400 * @brief AK4497 codec module control.
401 *
402 * @param handle AK4497 handle structure pointer.
403 * @param cmd module control command, support cmd kAK4497_ModuleSwitchDigitalInterface.
404 * @param data control data, support data kCODEC_ModuleDigitalInterfacePCM/kCODEC_ModuleDigitalInterfaceDSD.
405 */
406status_t AK4497_ModuleControl(ak4497_handle_t *handle, ak4497_module_ctrl_cmd_t cmd, uint32_t data);
407
408/*!
409 * @brief Deinit the AK4497 codec.
410 *
411 * This function close all modules in AK4497 to save power.
412 *
413 * @param handle AK4497 handle structure pointer.
414 */
415status_t AK4497_Deinit(ak4497_handle_t *handle);
416/*!
417 * @brief Write register to AK4497 using I2C.
418 *
419 * @param handle AK4497 handle structure.
420 * @param reg The register address in AK4497.
421 * @param val Value needs to write into the register.
422 */
423status_t AK4497_WriteReg(ak4497_handle_t *handle, uint8_t reg, uint8_t val);
424
425/*!
426 * @brief Read register from AK4497 using I2C.
427 * @param handle AK4497 handle structure.
428 * @param reg The register address in AK4497.
429 * @param val Value written to.
430 */
431status_t AK4497_ReadReg(ak4497_handle_t *handle, uint8_t reg, uint8_t *val);
432
433/*!
434 * @brief Modify some bits in the register using I2C.
435 * @param handle AK4497 handle structure.
436 * @param reg The register address in AK4497.
437 * @param mask The mask code for the bits want to write. The bit you want to write should be 0.
438 * @param val Value needs to write into the register.
439 */
440status_t AK4497_ModifyReg(ak4497_handle_t *handle, uint8_t reg, uint8_t mask, uint8_t val);
441
442#if defined(__cplusplus)
443}
444#endif
445
446/*! @} */
447#endif /* _FSL_AK4497_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 18:52:11 +0100