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1/*
2** ###################################################################
3** Version: rev. 1.0, 2019-07-30
4** Build: b200921
5**
6** Abstract:
7** Chip specific module features.
8**
9** Copyright 2016 Freescale Semiconductor, Inc.
10** Copyright 2016-2020 NXP
11** All rights reserved.
12**
13** SPDX-License-Identifier: BSD-3-Clause
14**
15** http: www.nxp.com
16** mail: [email protected]
17**
18** Revisions:
19** - rev. 1.0 (2019-07-30)
20** Initial version.
21**
22** ###################################################################
23*/
24
25#ifndef _K32L2B11A_FEATURES_H_
26#define _K32L2B11A_FEATURES_H_
27
28/* SOC module features */
29
30/* @brief ADC16 availability on the SoC. */
31#define FSL_FEATURE_SOC_ADC16_COUNT (1)
32/* @brief CMP availability on the SoC. */
33#define FSL_FEATURE_SOC_CMP_COUNT (1)
34/* @brief DAC availability on the SoC. */
35#define FSL_FEATURE_SOC_DAC_COUNT (1)
36/* @brief DMA availability on the SoC. */
37#define FSL_FEATURE_SOC_DMA_COUNT (1)
38/* @brief DMAMUX availability on the SoC. */
39#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
40/* @brief FGPIO availability on the SoC. */
41#define FSL_FEATURE_SOC_FGPIO_COUNT (5)
42/* @brief FLEXIO availability on the SoC. */
43#define FSL_FEATURE_SOC_FLEXIO_COUNT (1)
44/* @brief FTFA availability on the SoC. */
45#define FSL_FEATURE_SOC_FTFA_COUNT (1)
46/* @brief GPIO availability on the SoC. */
47#define FSL_FEATURE_SOC_GPIO_COUNT (5)
48/* @brief I2C availability on the SoC. */
49#define FSL_FEATURE_SOC_I2C_COUNT (2)
50/* @brief SLCD availability on the SoC. */
51#define FSL_FEATURE_SOC_SLCD_COUNT (1)
52/* @brief LLWU availability on the SoC. */
53#define FSL_FEATURE_SOC_LLWU_COUNT (1)
54/* @brief LPTMR availability on the SoC. */
55#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
56/* @brief LPUART availability on the SoC. */
57#define FSL_FEATURE_SOC_LPUART_COUNT (2)
58/* @brief MCGLITE availability on the SoC. */
59#define FSL_FEATURE_SOC_MCGLITE_COUNT (1)
60/* @brief MCM availability on the SoC. */
61#define FSL_FEATURE_SOC_MCM_COUNT (1)
62/* @brief MTB availability on the SoC. */
63#define FSL_FEATURE_SOC_MTB_COUNT (1)
64/* @brief MTBDWT availability on the SoC. */
65#define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
66/* @brief OSC availability on the SoC. */
67#define FSL_FEATURE_SOC_OSC_COUNT (1)
68/* @brief PIT availability on the SoC. */
69#define FSL_FEATURE_SOC_PIT_COUNT (1)
70/* @brief PMC availability on the SoC. */
71#define FSL_FEATURE_SOC_PMC_COUNT (1)
72/* @brief PORT availability on the SoC. */
73#define FSL_FEATURE_SOC_PORT_COUNT (5)
74/* @brief RCM availability on the SoC. */
75#define FSL_FEATURE_SOC_RCM_COUNT (1)
76/* @brief RFSYS availability on the SoC. */
77#define FSL_FEATURE_SOC_RFSYS_COUNT (1)
78/* @brief ROM availability on the SoC. */
79#define FSL_FEATURE_SOC_ROM_COUNT (1)
80/* @brief RTC availability on the SoC. */
81#define FSL_FEATURE_SOC_RTC_COUNT (1)
82/* @brief SIM availability on the SoC. */
83#define FSL_FEATURE_SOC_SIM_COUNT (1)
84/* @brief SMC availability on the SoC. */
85#define FSL_FEATURE_SOC_SMC_COUNT (1)
86/* @brief SPI availability on the SoC. */
87#define FSL_FEATURE_SOC_SPI_COUNT (2)
88/* @brief TPM availability on the SoC. */
89#define FSL_FEATURE_SOC_TPM_COUNT (3)
90/* @brief UART availability on the SoC. */
91#define FSL_FEATURE_SOC_UART_COUNT (1)
92/* @brief USB availability on the SoC. */
93#define FSL_FEATURE_SOC_USB_COUNT (1)
94/* @brief VREF availability on the SoC. */
95#define FSL_FEATURE_SOC_VREF_COUNT (1)
96
97/* ADC16 module features */
98
99/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
100#define FSL_FEATURE_ADC16_HAS_PGA (0)
101/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
102#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
103/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
104#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
105/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
106#define FSL_FEATURE_ADC16_HAS_DMA (1)
107/* @brief Has differential mode (bitfield SC1x[DIFF]). */
108#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
109/* @brief Has FIFO (bit SC4[AFDEP]). */
110#define FSL_FEATURE_ADC16_HAS_FIFO (0)
111/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
112#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
113/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
114#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
115/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
116#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
117/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
118#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
119/* @brief Has HW averaging (bit SC3[AVGE]). */
120#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
121/* @brief Has offset correction (register OFS). */
122#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
123/* @brief Maximum ADC resolution. */
124#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
125/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
126#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
127
128/* CMP module features */
129
130/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
131#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
132/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
133#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0)
134/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
135#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0)
136/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
137#define FSL_FEATURE_CMP_HAS_DMA (1)
138/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
139#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
140/* @brief Has DAC Test function in CMP (register DACTEST). */
141#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
142
143/* COP module features */
144
145/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */
146#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1)
147/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */
148#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1)
149/* @brief Has more clock sources like MCGIRC */
150#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1)
151/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */
152#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1)
153
154/* DAC module features */
155
156/* @brief Define the size of hardware buffer */
157#define FSL_FEATURE_DAC_BUFFER_SIZE (2)
158/* @brief Define whether the buffer supports watermark event detection or not. */
159#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (0)
160/* @brief Define whether the buffer supports watermark selection detection or not. */
161#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (0)
162/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
163#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (0)
164/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
165#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (0)
166/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
167#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (0)
168/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
169#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (0)
170/* @brief Define whether FIFO buffer mode is available or not. */
171#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1)
172/* @brief Define whether swing buffer mode is available or not.. */
173#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0)
174
175/* DMA module features */
176
177/* @brief Number of DMA channels. */
178#define FSL_FEATURE_DMA_MODULE_CHANNEL (4)
179/* @brief Total number of DMA channels on all modules. */
180#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (4)
181
182/* DMAMUX module features */
183
184/* @brief Number of DMA channels (related to number of register CHCFGn). */
185#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
186/* @brief Total number of DMA channels on all modules. */
187#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (4)
188/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
189#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
190/* @brief Register CHCFGn width. */
191#define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8)
192
193/* FGPIO module features */
194
195/* No feature definitions */
196
197/* FLEXIO module features */
198
199/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
200#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
201/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
202#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (0)
203/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
204#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (0)
205/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
206#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (0)
207/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
208#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (0)
209/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
210#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (0)
211/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
212#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (0)
213/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
214#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (0)
215/* @brief Reset value of the FLEXIO_VERID register */
216#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1000000)
217/* @brief Reset value of the FLEXIO_PARAM register */
218#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x10080404)
219/* @brief Flexio DMA request base channel */
220#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0)
221
222/* FLASH module features */
223
224/* @brief Is of type FTFA. */
225#define FSL_FEATURE_FLASH_IS_FTFA (1)
226/* @brief Is of type FTFE. */
227#define FSL_FEATURE_FLASH_IS_FTFE (0)
228/* @brief Is of type FTFL. */
229#define FSL_FEATURE_FLASH_IS_FTFL (0)
230/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
231#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
232/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
233#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
234/* @brief Has EEPROM region protection (register FEPROT). */
235#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
236/* @brief Has data flash region protection (register FDPROT). */
237#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
238/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
239#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
240/* @brief Has flash cache control in FMC module. */
241#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
242/* @brief Has flash cache control in MCM module. */
243#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
244/* @brief Has flash cache control in MSCM module. */
245#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
246/* @brief Has prefetch speculation control in flash, such as kv5x. */
247#define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
248/* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
249#define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
250/* @brief P-Flash start address. */
251#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
252/* @brief P-Flash block count. */
253#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
254/* @brief P-Flash block size. */
255#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536)
256/* @brief P-Flash sector size. */
257#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
258/* @brief P-Flash write unit size. */
259#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
260/* @brief P-Flash data path width. */
261#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
262/* @brief P-Flash block swap feature. */
263#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
264/* @brief P-Flash protection region count. */
265#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
266/* @brief Has FlexNVM memory. */
267#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
268/* @brief Has FlexNVM alias. */
269#define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0)
270/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
271#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
272/* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */
273#define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000)
274/* @brief FlexNVM block count. */
275#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
276/* @brief FlexNVM block size. */
277#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
278/* @brief FlexNVM sector size. */
279#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
280/* @brief FlexNVM write unit size. */
281#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
282/* @brief FlexNVM data path width. */
283#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
284/* @brief Has FlexRAM memory. */
285#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
286/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
287#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
288/* @brief FlexRAM size. */
289#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
290/* @brief Has 0x00 Read 1s Block command. */
291#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
292/* @brief Has 0x01 Read 1s Section command. */
293#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
294/* @brief Has 0x02 Program Check command. */
295#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
296/* @brief Has 0x03 Read Resource command. */
297#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
298/* @brief Has 0x06 Program Longword command. */
299#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
300/* @brief Has 0x07 Program Phrase command. */
301#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
302/* @brief Has 0x08 Erase Flash Block command. */
303#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
304/* @brief Has 0x09 Erase Flash Sector command. */
305#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
306/* @brief Has 0x0B Program Section command. */
307#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
308/* @brief Has 0x40 Read 1s All Blocks command. */
309#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
310/* @brief Has 0x41 Read Once command. */
311#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
312/* @brief Has 0x43 Program Once command. */
313#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
314/* @brief Has 0x44 Erase All Blocks command. */
315#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
316/* @brief Has 0x45 Verify Backdoor Access Key command. */
317#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
318/* @brief Has 0x46 Swap Control command. */
319#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
320/* @brief Has 0x49 Erase All Blocks Unsecure command. */
321#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
322/* @brief Has 0x4A Read 1s All Execute-only Segments command. */
323#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
324/* @brief Has 0x4B Erase All Execute-only Segments command. */
325#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
326/* @brief Has 0x80 Program Partition command. */
327#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
328/* @brief Has 0x81 Set FlexRAM Function command. */
329#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
330/* @brief P-Flash Erase/Read 1st all block command address alignment. */
331#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
332/* @brief P-Flash Erase sector command address alignment. */
333#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
334/* @brief P-Flash Rrogram/Verify section command address alignment. */
335#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
336/* @brief P-Flash Read resource command address alignment. */
337#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
338/* @brief P-Flash Program check command address alignment. */
339#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
340/* @brief P-Flash Program check command address alignment. */
341#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
342/* @brief FlexNVM Erase/Read 1st all block command address alignment. */
343#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
344/* @brief FlexNVM Erase sector command address alignment. */
345#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
346/* @brief FlexNVM Rrogram/Verify section command address alignment. */
347#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
348/* @brief FlexNVM Read resource command address alignment. */
349#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
350/* @brief FlexNVM Program check command address alignment. */
351#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
352/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
353#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU)
354/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
355#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU)
356/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
357#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU)
358/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
359#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU)
360/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
361#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU)
362/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
363#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU)
364/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
365#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU)
366/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
367#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU)
368/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
369#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU)
370/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
371#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU)
372/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
373#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU)
374/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
375#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU)
376/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
377#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU)
378/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
379#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU)
380/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
381#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU)
382/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
383#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU)
384/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
385#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
386/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
387#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
388/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
389#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
390/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
391#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
392/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
393#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
394/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
395#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
396/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
397#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
398/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
399#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
400/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
401#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
402/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
403#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
404/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
405#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
406/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
407#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
408/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
409#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
410/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
411#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
412/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
413#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
414/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
415#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
416
417/* GPIO module features */
418
419/* @brief Has GPIO attribute checker register (GACR). */
420#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0)
421
422/* I2C module features */
423
424/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
425#define FSL_FEATURE_I2C_HAS_SMBUS (1)
426/* @brief Maximum supported baud rate in kilobit per second. */
427#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
428/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
429#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
430/* @brief Has DMA support (register bit C1[DMAEN]). */
431#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
432/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
433#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
434/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
435#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
436/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
437#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
438/* @brief Maximum width of the glitch filter in number of bus clocks. */
439#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
440/* @brief Has control of the drive capability of the I2C pins. */
441#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
442/* @brief Has double buffering support (register S2). */
443#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1)
444/* @brief Has double buffer enable. */
445#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0)
446
447/* SLCD module features */
448
449#if defined(CPU_K32L2B11VLH0A) || defined(CPU_K32L2B11VMP0A)
450 /* @brief Has Multi Alternate Clock Source (register bit GCR[ATLSOURCE]). */
451 #define FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE (1)
452 /* @brief Has fast frame rate (register bit GCR[FFR]). */
453 #define FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE (1)
454 /* @brief Has frame frequency interrupt (register bit GCR[LCDIEN]). */
455 #define FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT (0)
456 /* @brief Has high reference select (register bit GCR[HREFSEL]). */
457 #define FSL_FEATURE_SLCD_HAS_HIGH_REFERENCE_SELECT (0)
458 /* @brief Has pad safe (register bit GCR[PADSAFE]). */
459 #define FSL_FEATURE_SLCD_HAS_PAD_SAFE (1)
460 /* @brief Has lcd wait (register bit GCR[LCDWAIT]). */
461 #define FSL_FEATURE_SLCD_HAS_LCD_WAIT (0)
462 /* @brief Has lcd doze enable (register bit GCR[LCDDOZE]). */
463 #define FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE (1)
464 /* @brief Total pin number on LCD. */
465 #define FSL_FEATURE_SLCD_HAS_PIN_NUM (64)
466 /* @brief Total phase number on SLCD. */
467 #define FSL_FEATURE_SLCD_HAS_PHASE_NUM (8)
468#endif /* defined(CPU_K32L2B11VLH0A) || defined(CPU_K32L2B11VMP0A) */
469
470/* LLWU module features */
471
472/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
473#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
474/* @brief Has pins 8-15 connected to LLWU device. */
475#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
476/* @brief Maximum number of internal modules connected to LLWU device. */
477#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
478/* @brief Number of digital filters. */
479#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
480/* @brief Has MF register. */
481#define FSL_FEATURE_LLWU_HAS_MF (0)
482/* @brief Has PF register. */
483#define FSL_FEATURE_LLWU_HAS_PF (0)
484/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
485#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
486/* @brief Has no internal module wakeup flag register. */
487#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
488/* @brief Has external pin 0 connected to LLWU device. */
489#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0)
490/* @brief Index of port of external pin. */
491#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0)
492/* @brief Number of external pin port on specified port. */
493#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0)
494/* @brief Has external pin 1 connected to LLWU device. */
495#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0)
496/* @brief Index of port of external pin. */
497#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0)
498/* @brief Number of external pin port on specified port. */
499#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0)
500/* @brief Has external pin 2 connected to LLWU device. */
501#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0)
502/* @brief Index of port of external pin. */
503#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0)
504/* @brief Number of external pin port on specified port. */
505#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0)
506/* @brief Has external pin 3 connected to LLWU device. */
507#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (0)
508/* @brief Index of port of external pin. */
509#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (0)
510/* @brief Number of external pin port on specified port. */
511#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (0)
512/* @brief Has external pin 4 connected to LLWU device. */
513#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0)
514/* @brief Index of port of external pin. */
515#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0)
516/* @brief Number of external pin port on specified port. */
517#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0)
518/* @brief Has external pin 5 connected to LLWU device. */
519#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
520/* @brief Index of port of external pin. */
521#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
522/* @brief Number of external pin port on specified port. */
523#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
524/* @brief Has external pin 6 connected to LLWU device. */
525#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
526/* @brief Index of port of external pin. */
527#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
528/* @brief Number of external pin port on specified port. */
529#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
530/* @brief Has external pin 7 connected to LLWU device. */
531#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
532/* @brief Index of port of external pin. */
533#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
534/* @brief Number of external pin port on specified port. */
535#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
536/* @brief Has external pin 8 connected to LLWU device. */
537#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
538/* @brief Index of port of external pin. */
539#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
540/* @brief Number of external pin port on specified port. */
541#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
542/* @brief Has external pin 9 connected to LLWU device. */
543#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
544/* @brief Index of port of external pin. */
545#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
546/* @brief Number of external pin port on specified port. */
547#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
548/* @brief Has external pin 10 connected to LLWU device. */
549#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
550/* @brief Index of port of external pin. */
551#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
552/* @brief Number of external pin port on specified port. */
553#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
554/* @brief Has external pin 11 connected to LLWU device. */
555#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0)
556/* @brief Index of port of external pin. */
557#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0)
558/* @brief Number of external pin port on specified port. */
559#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0)
560/* @brief Has external pin 12 connected to LLWU device. */
561#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0)
562/* @brief Index of port of external pin. */
563#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0)
564/* @brief Number of external pin port on specified port. */
565#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
566/* @brief Has external pin 13 connected to LLWU device. */
567#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0)
568/* @brief Index of port of external pin. */
569#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0)
570/* @brief Number of external pin port on specified port. */
571#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0)
572/* @brief Has external pin 14 connected to LLWU device. */
573#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
574/* @brief Index of port of external pin. */
575#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
576/* @brief Number of external pin port on specified port. */
577#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
578/* @brief Has external pin 15 connected to LLWU device. */
579#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
580/* @brief Index of port of external pin. */
581#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
582/* @brief Number of external pin port on specified port. */
583#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
584/* @brief Has external pin 16 connected to LLWU device. */
585#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
586/* @brief Index of port of external pin. */
587#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
588/* @brief Number of external pin port on specified port. */
589#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
590/* @brief Has external pin 17 connected to LLWU device. */
591#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
592/* @brief Index of port of external pin. */
593#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
594/* @brief Number of external pin port on specified port. */
595#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
596/* @brief Has external pin 18 connected to LLWU device. */
597#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
598/* @brief Index of port of external pin. */
599#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
600/* @brief Number of external pin port on specified port. */
601#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
602/* @brief Has external pin 19 connected to LLWU device. */
603#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
604/* @brief Index of port of external pin. */
605#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
606/* @brief Number of external pin port on specified port. */
607#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
608/* @brief Has external pin 20 connected to LLWU device. */
609#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
610/* @brief Index of port of external pin. */
611#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
612/* @brief Number of external pin port on specified port. */
613#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
614/* @brief Has external pin 21 connected to LLWU device. */
615#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
616/* @brief Index of port of external pin. */
617#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
618/* @brief Number of external pin port on specified port. */
619#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
620/* @brief Has external pin 22 connected to LLWU device. */
621#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
622/* @brief Index of port of external pin. */
623#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
624/* @brief Number of external pin port on specified port. */
625#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
626/* @brief Has external pin 23 connected to LLWU device. */
627#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
628/* @brief Index of port of external pin. */
629#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
630/* @brief Number of external pin port on specified port. */
631#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
632/* @brief Has external pin 24 connected to LLWU device. */
633#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
634/* @brief Index of port of external pin. */
635#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
636/* @brief Number of external pin port on specified port. */
637#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
638/* @brief Has external pin 25 connected to LLWU device. */
639#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
640/* @brief Index of port of external pin. */
641#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
642/* @brief Number of external pin port on specified port. */
643#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
644/* @brief Has external pin 26 connected to LLWU device. */
645#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
646/* @brief Index of port of external pin. */
647#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
648/* @brief Number of external pin port on specified port. */
649#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
650/* @brief Has external pin 27 connected to LLWU device. */
651#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
652/* @brief Index of port of external pin. */
653#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
654/* @brief Number of external pin port on specified port. */
655#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
656/* @brief Has external pin 28 connected to LLWU device. */
657#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
658/* @brief Index of port of external pin. */
659#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
660/* @brief Number of external pin port on specified port. */
661#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
662/* @brief Has external pin 29 connected to LLWU device. */
663#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
664/* @brief Index of port of external pin. */
665#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
666/* @brief Number of external pin port on specified port. */
667#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
668/* @brief Has external pin 30 connected to LLWU device. */
669#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
670/* @brief Index of port of external pin. */
671#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
672/* @brief Number of external pin port on specified port. */
673#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
674/* @brief Has external pin 31 connected to LLWU device. */
675#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
676/* @brief Index of port of external pin. */
677#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
678/* @brief Number of external pin port on specified port. */
679#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
680/* @brief Has internal module 0 connected to LLWU device. */
681#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
682/* @brief Has internal module 1 connected to LLWU device. */
683#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
684/* @brief Has internal module 2 connected to LLWU device. */
685#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0)
686/* @brief Has internal module 3 connected to LLWU device. */
687#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
688/* @brief Has internal module 4 connected to LLWU device. */
689#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
690/* @brief Has internal module 5 connected to LLWU device. */
691#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
692/* @brief Has internal module 6 connected to LLWU device. */
693#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
694/* @brief Has internal module 7 connected to LLWU device. */
695#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
696/* @brief Has Version ID Register (LLWU_VERID). */
697#define FSL_FEATURE_LLWU_HAS_VERID (0)
698/* @brief Has Parameter Register (LLWU_PARAM). */
699#define FSL_FEATURE_LLWU_HAS_PARAM (0)
700/* @brief Width of registers of the LLWU. */
701#define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
702/* @brief Has DMA Enable register (LLWU_DE). */
703#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
704
705/* LPTMR module features */
706
707/* @brief Has shared interrupt handler with another LPTMR module. */
708#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
709/* @brief Whether LPTMR counter is 32 bits width. */
710#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
711/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
712#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
713
714/* LPUART module features */
715
716/* @brief LPUART0 and LPUART1 has shared interrupt vector. */
717#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0)
718/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
719#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
720/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
721#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
722/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
723#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
724/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
725#define FSL_FEATURE_LPUART_HAS_FIFO (0)
726/* @brief Has 32-bit register MODIR */
727#define FSL_FEATURE_LPUART_HAS_MODIR (0)
728/* @brief Hardware flow control (RTS, CTS) is supported. */
729#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0)
730/* @brief Infrared (modulation) is supported. */
731#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0)
732/* @brief 2 bits long stop bit is available. */
733#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
734/* @brief If 10-bit mode is supported. */
735#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
736/* @brief If 7-bit mode is supported. */
737#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0)
738/* @brief Baud rate fine adjustment is available. */
739#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
740/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
741#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
742/* @brief Baud rate oversampling is available. */
743#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
744/* @brief Baud rate oversampling is available. */
745#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
746/* @brief Peripheral type. */
747#define FSL_FEATURE_LPUART_IS_SCI (1)
748/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
749#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0)
750/* @brief Supports two match addresses to filter incoming frames. */
751#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
752/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
753#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
754/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
755#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
756/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
757#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
758/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
759#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
760/* @brief Has improved smart card (ISO7816 protocol) support. */
761#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
762/* @brief Has local operation network (CEA709.1-B protocol) support. */
763#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
764/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
765#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
766/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
767#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
768/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
769#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
770/* @brief Has separate DMA RX and TX requests. */
771#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
772/* @brief Has separate RX and TX interrupts. */
773#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
774/* @brief Has LPAURT_PARAM. */
775#define FSL_FEATURE_LPUART_HAS_PARAM (0)
776/* @brief Has LPUART_VERID. */
777#define FSL_FEATURE_LPUART_HAS_VERID (0)
778/* @brief Has LPUART_GLOBAL. */
779#define FSL_FEATURE_LPUART_HAS_GLOBAL (0)
780/* @brief Has LPUART_PINCFG. */
781#define FSL_FEATURE_LPUART_HAS_PINCFG (0)
782
783/* MCGLITE module features */
784
785/* @brief Defines that clock generator is MCG Lite. */
786#define FSL_FEATURE_MCGLITE_MCGLITE (1)
787/* @brief Has Crystal Oscillator Operation Mode Selection. */
788#define FSL_FEATURE_MCGLITE_HAS_HGO0 (1)
789/* @brief Has HCTRIM register available. */
790#define FSL_FEATURE_MCGLITE_HAS_HCTRIM (0)
791/* @brief Has HTTRIM register available. */
792#define FSL_FEATURE_MCGLITE_HAS_HTTRIM (0)
793/* @brief Has HFTRIM register available. */
794#define FSL_FEATURE_MCGLITE_HAS_HFTRIM (0)
795/* @brief Has LTRIMRNG register available. */
796#define FSL_FEATURE_MCGLITE_HAS_LTRIMRNG (0)
797/* @brief Has LFTRIM register available. */
798#define FSL_FEATURE_MCGLITE_HAS_LFTRIM (0)
799/* @brief Has LSTRIM register available. */
800#define FSL_FEATURE_MCGLITE_HAS_LSTRIM (0)
801/* @brief Has External Clock Source Frequency Range Selection. */
802#define FSL_FEATURE_MCGLITE_HAS_RANGE0 (1)
803
804/* interrupt module features */
805
806/* @brief Lowest interrupt request number. */
807#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
808/* @brief Highest interrupt request number. */
809#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
810
811/* OSC module features */
812
813/* @brief Has OSC1 external oscillator. */
814#define FSL_FEATURE_OSC_HAS_OSC1 (0)
815/* @brief Has OSC0 external oscillator. */
816#define FSL_FEATURE_OSC_HAS_OSC0 (1)
817/* @brief Has OSC external oscillator (without index). */
818#define FSL_FEATURE_OSC_HAS_OSC (0)
819/* @brief Number of OSC external oscillators. */
820#define FSL_FEATURE_OSC_OSC_COUNT (1)
821/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
822#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
823
824/* PIT module features */
825
826/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
827#define FSL_FEATURE_PIT_TIMER_COUNT (2)
828/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
829#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
830/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
831#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
832/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
833#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
834/* @brief Has timer enable control. */
835#define FSL_FEATURE_PIT_HAS_MDIS (1)
836
837/* PMC module features */
838
839/* @brief Has Bandgap Enable In VLPx Operation support. */
840#define FSL_FEATURE_PMC_HAS_BGEN (1)
841/* @brief Has Bandgap Buffer Enable. */
842#define FSL_FEATURE_PMC_HAS_BGBE (1)
843/* @brief Has Bandgap Buffer Drive Select. */
844#define FSL_FEATURE_PMC_HAS_BGBDS (0)
845/* @brief Has Low-Voltage Detect Voltage Select support. */
846#define FSL_FEATURE_PMC_HAS_LVDV (1)
847/* @brief Has Low-Voltage Warning Voltage Select support. */
848#define FSL_FEATURE_PMC_HAS_LVWV (1)
849/* @brief Has LPO. */
850#define FSL_FEATURE_PMC_HAS_LPO (0)
851/* @brief Has VLPx option PMC_REGSC[VLPO]. */
852#define FSL_FEATURE_PMC_HAS_VLPO (0)
853/* @brief Has acknowledge isolation support. */
854#define FSL_FEATURE_PMC_HAS_ACKISO (1)
855/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
856#define FSL_FEATURE_PMC_HAS_REGFPM (0)
857/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
858#define FSL_FEATURE_PMC_HAS_REGONS (1)
859/* @brief Has PMC_HVDSC1. */
860#define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
861/* @brief Has PMC_PARAM. */
862#define FSL_FEATURE_PMC_HAS_PARAM (0)
863/* @brief Has PMC_VERID. */
864#define FSL_FEATURE_PMC_HAS_VERID (0)
865
866/* PORT module features */
867
868/* @brief Has control lock (register bit PCR[LK]). */
869#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
870/* @brief Has open drain control (register bit PCR[ODE]). */
871#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
872/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
873#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
874/* @brief Has DMA request (register bit field PCR[IRQC] values). */
875#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
876/* @brief Has pull resistor selection available. */
877#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
878/* @brief Has pull resistor enable (register bit PCR[PE]). */
879#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
880/* @brief Has slew rate control (register bit PCR[SRE]). */
881#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
882/* @brief Has passive filter (register bit field PCR[PFE]). */
883#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
884/* @brief Has drive strength control (register bit PCR[DSE]). */
885#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
886/* @brief Has separate drive strength register (HDRVE). */
887#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
888/* @brief Has glitch filter (register IOFLT). */
889#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
890/* @brief Defines width of PCR[MUX] field. */
891#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
892/* @brief Has dedicated interrupt vector. */
893#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
894/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
895#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
896/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
897#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
898/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
899#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
900
901/* RCM module features */
902
903/* @brief Has Loss-of-Lock Reset support. */
904#define FSL_FEATURE_RCM_HAS_LOL (0)
905/* @brief Has Loss-of-Clock Reset support. */
906#define FSL_FEATURE_RCM_HAS_LOC (0)
907/* @brief Has JTAG generated Reset support. */
908#define FSL_FEATURE_RCM_HAS_JTAG (0)
909/* @brief Has EzPort generated Reset support. */
910#define FSL_FEATURE_RCM_HAS_EZPORT (0)
911/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
912#define FSL_FEATURE_RCM_HAS_EZPMS (0)
913/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
914#define FSL_FEATURE_RCM_HAS_BOOTROM (1)
915/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
916#define FSL_FEATURE_RCM_HAS_SSRS (1)
917/* @brief Has Version ID Register (RCM_VERID). */
918#define FSL_FEATURE_RCM_HAS_VERID (0)
919/* @brief Has Parameter Register (RCM_PARAM). */
920#define FSL_FEATURE_RCM_HAS_PARAM (0)
921/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
922#define FSL_FEATURE_RCM_HAS_SRIE (0)
923/* @brief Width of registers of the RCM. */
924#define FSL_FEATURE_RCM_REG_WIDTH (8)
925/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
926#define FSL_FEATURE_RCM_HAS_CORE1 (0)
927/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
928#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
929/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
930#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
931
932/* RTC module features */
933
934/* @brief Has wakeup pin. */
935#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
936/* @brief Has wakeup pin selection (bit field CR[WPS]). */
937#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
938/* @brief Has low power features (registers MER, MCLR and MCHR). */
939#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
940/* @brief Has read/write access control (registers WAR and RAR). */
941#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
942/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
943#define FSL_FEATURE_RTC_HAS_SECURITY (0)
944/* @brief Has RTC_CLKIN available. */
945#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1)
946/* @brief Has prescaler adjust for LPO. */
947#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
948/* @brief Has Clock Pin Enable field. */
949#define FSL_FEATURE_RTC_HAS_CPE (0)
950/* @brief Has Timer Seconds Interrupt Configuration field. */
951#define FSL_FEATURE_RTC_HAS_TSIC (0)
952/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
953#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
954/* @brief Has Tamper Interrupt Register (register TIR). */
955#define FSL_FEATURE_RTC_HAS_TIR (0)
956/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
957#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
958/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
959#define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
960/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
961#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
962/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
963#define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
964/* @brief Has Tamper Detect Register (register TDR). */
965#define FSL_FEATURE_RTC_HAS_TDR (0)
966/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
967#define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
968/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
969#define FSL_FEATURE_RTC_HAS_TDR_STF (0)
970/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
971#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
972/* @brief Has Tamper Time Seconds Register (register TTSR). */
973#define FSL_FEATURE_RTC_HAS_TTSR (0)
974/* @brief Has Pin Configuration Register (register PCR). */
975#define FSL_FEATURE_RTC_HAS_PCR (0)
976
977/* SIM module features */
978
979/* @brief Has USB FS divider. */
980#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
981/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
982#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
983/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
984#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
985/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
986#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
987/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
988#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
989/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
990#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
991/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
992#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
993/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
994#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
995/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
996#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
997/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
998#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
999/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1000#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
1001/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1002#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1003/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1004#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1005/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1006#define FSL_FEATURE_SIM_OPT_HAS_ODE (1)
1007/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
1008#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (2)
1009/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1010#define FSL_FEATURE_SIM_OPT_UART_COUNT (1)
1011/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
1012#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
1013/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
1014#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
1015/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
1016#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (1)
1017/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1018#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1)
1019/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1020#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (1)
1021/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1022#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1023/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1024#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
1025/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1026#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
1027/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1028#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1)
1029/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1030#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1)
1031/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1032#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
1033/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1034#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
1035/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1036#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
1037/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1038#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
1039/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1040#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
1041/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1042#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
1043/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1044#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
1045/* @brief Has FTM module(s) configuration. */
1046#define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
1047/* @brief Number of FTM modules. */
1048#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
1049/* @brief Number of FTM triggers with selectable source. */
1050#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
1051/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1052#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
1053/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1054#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
1055/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1056#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
1057/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1058#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
1059/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1060#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1061/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1062#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1063/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1064#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
1065/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1066#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
1067/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1068#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
1069/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1070#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
1071/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1072#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
1073/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1074#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
1075/* @brief Has TPM module(s) configuration. */
1076#define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
1077/* @brief The highest TPM module index. */
1078#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
1079/* @brief Has TPM module with index 0. */
1080#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
1081/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
1082#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1)
1083/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1084#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1)
1085/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1086#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
1087/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
1088#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1)
1089/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1090#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2)
1091/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1092#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
1093/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1094#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
1095/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1096#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
1097/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1098#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
1099/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1100#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1101/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1102#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1103/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1104#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
1105/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1106#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1107/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1108#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
1109/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1110#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
1111/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1112#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
1113/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1114#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1115/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1116#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1117/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1118#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1119/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1120#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1)
1121/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1122#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (1)
1123/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1124#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1)
1125/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1126#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1127/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1128#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
1129/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1130#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
1131/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1132#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
1133/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1134#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
1135/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1136#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
1137/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1138#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
1139/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1140#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
1141/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
1142#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
1143/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1144#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
1145/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1146#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1147/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1148#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1149/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1150#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1151/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1152#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1153/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1154#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
1155/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1156#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1157/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1158#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
1159/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1160#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1161/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1162#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1163/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1164#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
1165/* @brief Has device die ID (register bit field SDID[DIEID]). */
1166#define FSL_FEATURE_SIM_SDID_HAS_DIEID (0)
1167/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1168#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
1169/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1170#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
1171/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1172#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
1173/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1174#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1175/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1176#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
1177/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1178#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
1179/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1180#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
1181/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1182#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
1183/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1184#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
1185/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1186#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
1187/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1188#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1189/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1190#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
1191/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1192#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
1193/* @brief Has miscellanious control register (register MCR). */
1194#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1195/* @brief Has COP watchdog (registers COPC and SRVCOP). */
1196#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
1197/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1198#define FSL_FEATURE_SIM_HAS_COP_STOP (1)
1199/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
1200#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
1201
1202/* SMC module features */
1203
1204/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
1205#define FSL_FEATURE_SMC_HAS_PSTOPO (1)
1206/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
1207#define FSL_FEATURE_SMC_HAS_LPOPO (0)
1208/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
1209#define FSL_FEATURE_SMC_HAS_PORPO (1)
1210/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
1211#define FSL_FEATURE_SMC_HAS_LPWUI (0)
1212/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
1213#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
1214/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
1215#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
1216/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
1217#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1)
1218/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
1219#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
1220/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
1221#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
1222/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
1223#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
1224/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
1225#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
1226/* @brief Has stop submode. */
1227#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
1228/* @brief Has stop submode 0(VLLS0). */
1229#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
1230/* @brief Has stop submode 1(VLLS1). */
1231#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1)
1232/* @brief Has stop submode 2(VLLS2). */
1233#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0)
1234/* @brief Has SMC_PARAM. */
1235#define FSL_FEATURE_SMC_HAS_PARAM (0)
1236/* @brief Has SMC_VERID. */
1237#define FSL_FEATURE_SMC_HAS_VERID (0)
1238/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
1239#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
1240/* @brief Has tamper reset (register bit SRS[TAMPER]). */
1241#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
1242/* @brief Has security violation reset (register bit SRS[SECVIO]). */
1243#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
1244/* @brief Width of SMC registers. */
1245#define FSL_FEATURE_SMC_REG_WIDTH (8)
1246
1247/* SPI module features */
1248
1249/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1250#define FSL_FEATURE_SPI_HAS_FIFO (1)
1251/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */
1252#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
1253/* @brief Has separate DMA RX and TX requests. */
1254#define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
1255/* @brief Receive/transmit FIFO size in number of 16-bit communication items. */
1256#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
1257 (((x) == SPI0) ? (0) : \
1258 (((x) == SPI1) ? (4) : (-1)))
1259/* @brief Maximum transfer data width in bits. */
1260#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
1261/* @brief The data register name has postfix (L as low and H as high). */
1262#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
1263/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
1264#define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
1265/* @brief Has 16-bit data transfer support. */
1266#define FSL_FEATURE_SPI_16BIT_TRANSFERS (1)
1267
1268/* SysTick module features */
1269
1270/* @brief Systick has external reference clock. */
1271#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
1272/* @brief Systick external reference clock is core clock divided by this value. */
1273#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
1274
1275/* TPM module features */
1276
1277/* @brief Bus clock is the source clock for the module. */
1278#define FSL_FEATURE_TPM_BUS_CLOCK (0)
1279/* @brief Number of channels. */
1280#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
1281 (((x) == TPM0) ? (6) : \
1282 (((x) == TPM1) ? (2) : \
1283 (((x) == TPM2) ? (2) : (-1))))
1284/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
1285#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
1286/* @brief Has TPM_PARAM. */
1287#define FSL_FEATURE_TPM_HAS_PARAM (0)
1288/* @brief Has TPM_VERID. */
1289#define FSL_FEATURE_TPM_HAS_VERID (0)
1290/* @brief Has TPM_GLOBAL. */
1291#define FSL_FEATURE_TPM_HAS_GLOBAL (0)
1292/* @brief Has TPM_TRIG. */
1293#define FSL_FEATURE_TPM_HAS_TRIG (0)
1294/* @brief Has counter pause on trigger. */
1295#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
1296/* @brief Has external trigger selection. */
1297#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
1298/* @brief Has TPM_COMBINE register. */
1299#define FSL_FEATURE_TPM_HAS_COMBINE (0)
1300/* @brief Whether COMBINE register has effect. */
1301#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (0)
1302/* @brief Has TPM_POL. */
1303#define FSL_FEATURE_TPM_HAS_POL (1)
1304/* @brief Has TPM_FILTER register. */
1305#define FSL_FEATURE_TPM_HAS_FILTER (0)
1306/* @brief Whether FILTER register has effect. */
1307#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (0)
1308/* @brief Has TPM_QDCTRL register. */
1309#define FSL_FEATURE_TPM_HAS_QDCTRL (0)
1310/* @brief Whether QDCTRL register has effect. */
1311#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (0)
1312/* @brief Is affected by errata with ID 050050 (Incorrect duty output when EPWM mode is set to PS=0 during write 1 to CnV register). */
1313#define FSL_FEATURE_TPM_HAS_ERRATA_050050 (0)
1314
1315/* UART module features */
1316
1317/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
1318#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
1319/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
1320#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
1321/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
1322#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0)
1323/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1324#define FSL_FEATURE_UART_HAS_FIFO (0)
1325/* @brief Hardware flow control (RTS, CTS) is supported. */
1326#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0)
1327/* @brief Infrared (modulation) is supported. */
1328#define FSL_FEATURE_UART_HAS_IR_SUPPORT (0)
1329/* @brief 2 bits long stop bit is available. */
1330#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0)
1331/* @brief If 10-bit mode is supported. */
1332#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
1333/* @brief Baud rate fine adjustment is available. */
1334#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
1335/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
1336#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
1337/* @brief Baud rate oversampling is available. */
1338#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
1339/* @brief Baud rate oversampling is available. */
1340#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
1341/* @brief Peripheral type. */
1342#define FSL_FEATURE_UART_IS_SCI (0)
1343/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1344#define FSL_FEATURE_UART_FIFO_SIZEn(x) (0)
1345/* @brief Supports two match addresses to filter incoming frames. */
1346#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
1347/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
1348#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
1349/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
1350#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
1351/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
1352#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
1353/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
1354#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
1355/* @brief Has improved smart card (ISO7816 protocol) support. */
1356#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1)
1357/* @brief Has local operation network (CEA709.1-B protocol) support. */
1358#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
1359/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
1360#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
1361/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
1362#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (0)
1363/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
1364#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (0)
1365/* @brief Has separate DMA RX and TX requests. */
1366#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
1367
1368/* USB module features */
1369
1370/* @brief KHCI module instance count */
1371#define FSL_FEATURE_USB_KHCI_COUNT (1)
1372/* @brief HOST mode enabled */
1373#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0)
1374/* @brief OTG mode enabled */
1375#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0)
1376/* @brief Size of the USB dedicated RAM */
1377#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
1378/* @brief Has KEEP_ALIVE_CTRL register */
1379#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
1380/* @brief Has the Dynamic SOF threshold compare support */
1381#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
1382/* @brief Has the VBUS detect support */
1383#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
1384/* @brief Has the IRC48M module clock support */
1385#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
1386/* @brief Number of endpoints supported */
1387#define FSL_FEATURE_USB_ENDPT_COUNT (16)
1388/* @brief Has STALL_IL/OL_DIS registers */
1389#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0)
1390/* @brief Has STALL_IH/OH_DIS registers */
1391#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0)
1392
1393/* VREF module features */
1394
1395/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
1396#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
1397/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
1398#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
1399/* @brief If high/low buffer mode supported */
1400#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
1401/* @brief Module has also low reference (registers VREFL/VREFH) */
1402#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
1403/* @brief Has VREF_TRM4. */
1404#define FSL_FEATURE_VREF_HAS_TRM4 (0)
1405
1406#endif /* _K32L2B11A_FEATURES_H_ */
1407
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